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2024-05-26 - 16:37

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OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (by arch) - (x86 CPU strings)

BoxArch ↑CoresMHzBogo​MIPSEffective
ras6aarch​648 x 12,0003,20020.05. 17:01
res3saarch​640 x 1 x 11,0001,60026.05. 06:47
r4s5saarch​644 x 11,60020027.03. 14:13
r2s6saarch​644 x 11,3506426.05. 14:23
r2s7aarch​644 x 12,40043226.05. 14:25
res6saarch​644 x 101,60026.05. 06:58
rbs5saarch​644 x 11,6006426.05. 05:40
r1s5aarch​644 x 11,20079626.05. 14:06
rfs1aarch​644 x 11,50043226.05. 07:07
rfs2aarch​644 x 11,50043226.05. 07:08
r2s7saarch​644 x 11,50043226.05. 14:27
r3s4aarch​646 x 11,3009626.05. 14:40
ras3aarch​648 x 12,0004,00026.05. 05:16
r2s1arm​v5tejl1 x 120019926.05. 14:16
r1s7arm​v6l1 x 120053026.05. 14:10
r7s3arm​v6l1 x 1700526.05. 16:22
r9s8sarm​v7l1 x 180079626.05. 05:11
r2s2arm​v7l1 x 172049926.05. 14:17
r1s4arm​v7l2 x 11,2004826.05. 14:04
r4s2sarm​v7l1 x 180053026.05. 15:04
r7s8arm​v7l1 x 11,00099526.05. 04:24
ras5arm​v7l2 x 11,0002426.05. 05:19
r7s4arm​v7l1 x 153634826.05. 16:29
r4s2arm​v7l1 x 180079626.05. 15:01
rbs3arm​v7l4 x 19962826.05. 05:32
r7s3sarm​v7l4 x 11,40035626.05. 16:25
ras4arm​v7l1 x 150039826.05. 05:18
r7s4sarm​v7l4 x 11,5001,08026.05. 16:31
r4s8sarm​v7l1 x 140039826.05. 15:28
rfs4sarm​v7l1 x 180080026.05. 07:16
r4s1sarm​v7l4 x 11,5001,08026.05. 14:58
r7s6arm​v7l1 x 11,00039828.02. 14:10
ras5sarm​v7l2 x 11,0002426.05. 05:20
r4s1arm​v7l4 x 11,50079226.05. 02:47
res7arm​v7l0 x 1 x 11,0001226.05. 07:00
rbs7sarm​v7l4 x 19962426.05. 05:47
rfs4arm​v7l1 x 180080026.05. 07:09
ras3sarm​v7l1 x 11,30084026.05. 05:17
r7s8sarm​v7l1 x 11,00059726.05. 04:26
r9s7arm​v7l2 x 11,000026.05. 05:10
rfs6sarm​v7l1 x 16671,33226.05. 07:26
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
r1s4sarm​v7l2 x 14004826.05. 14:05
r8s6arm​v7l1 x 150049826.05. 04:43
r5s5sarm​v7l1 x 160060026.05. 15:49
r2s3sarm​v7l0 x 1 x 16001,20026.05. 14:19
rbs3sarm​v7l4 x 11,40035626.05. 05:33
r5s7arm​v7l1 x 15286426.05. 15:59
rfs6arm​v7l1 x 16671,33226.05. 07:26
r9s1sarm​v7l1 x 101,25014.04. 18:03
rbs7arm​v7l4 x 19962826.05. 05:45
r5s5arm​v7l1 x 160059726.05. 15:46
ras4sarm​v7l1 x 160059707.02. 02:45
rbs8arm​v7l2 x 16662,65026.05. 05:50
r4s5arm​v7l1 x 1500026.05. 15:15
r4s6sarm​v7l0 x 1 x 11,0006626.05. 15:20
r4s8arm​v7l1 x 140039826.05. 15:26
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r5s7sarm​v7l1 x 15284826.05. 16:02
r2s3arm​v7l0 x 1 x 162462426.05. 14:18
ras6sarm​v7l1 x 11,0001,98726.05. 05:22
r4s3i5861 x 150099626.05. 15:08
r8s1i5861 x 135070126.05. 04:29
r3s5i5861 x 113326526.05. 14:46
r9s4i6861 x 21,0003,99026.05. 04:58
r3s8i6866 x 13,20038,52626.05. 14:55
rbs5i6864 x 2049,53926.05. 05:38
r6s6i6861 x 11,6003,19126.05. 16:16
r2s6i6861 x 11,5002,99926.05. 14:21
r6s5i6861 x 11,5002,99226.05. 16:14
rbs0i6862 x 22,50017,60026.05. 05:27
ras1i6861 x 11,4002,79926.05. 05:14
r4s3si6861 x 11,4662,93224.05. 15:04
r7s5i6861 x 11,3002,59326.05. 16:32
r3s0i6864 x 23,50055,99226.05. 14:31
r1s8i6861 x 21,6006,39826.05. 14:11
r6s7i6862 x 12,3009,17611.01. 02:44
r8s5i6864 x 23,40054,40026.05. 04:41
rcs3i6862 x 11,4005,58626.05. 06:02
r3s1i6864 x 12,40019,12726.05. 14:32
r3s7i6861 x 15331,06626.05. 14:53
r4s7i6864 x 11,83314,66426.05. 15:23
r2s4mips​641 x 180053124.12. 13:46
r5s6ppc1 x 153313326.05. 15:57
r2s8ppc1 x 14006626.05. 14:29
ras7ppc1 x 13966526.05. 05:23
r2s5ppc1 x 13966627.03. 13:43
r4s4ppc4 x 11,20049826.05. 15:11
r3s5sppc2 x 11,20040026.05. 14:49
r3s2sriscv644 x 1028426.05. 14:37
r3s2riscv641 x 11,00028426.05. 14:34
rds3x86_​644 x 11,91015,32426.05. 06:31
ras0x86_​642 x 22,30018,41626.05. 05:12
r9s3x86_​644 x 11,60012,74826.05. 04:54
r0s4x86_​648 x 23,600115,20026.05. 13:26
r6s0x86_​642 x 10 x 21,700136,18026.05. 03:51
rbs8sx86_​644 x 22,40038,70426.05. 05:52
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r9s2x86_​644 x 11,60012,74826.05. 04:52
r9s5sx86_​642 x 13,50013,99826.05. 05:05
r1s0x86_​644 x 13,10024,80026.05. 13:55
rcs7sx86_​644 x 11,50011,98026.05. 06:17
r1s8sx86_​644 x 11,90015,19626.05. 14:14
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s0x86_​642 x 22,30018,40026.05. 04:49
rds6x86_​644 x 11,60012,74826.05. 06:36
res8sx86_​644 x 11,90015,05226.05. 07:04
r5s3x86_​644 x 22,00031,87226.05. 15:35
ras8sx86_​644 x 11,60012,74826.05. 05:26
r0s7x86_​648 x 23,600115,20026.05. 13:43
r0s2sx86_​6410 x 13,70073,99026.05. 13:16
rfs0x86_​6416 x 22,000128,00026.05. 07:06
r5s2x86_​644 x 12,70021,69926.05. 15:32
r0s8x86_​648 x 23,600115,20026.05. 13:50
rbs4sx86_​644 x 11,60012,74826.05. 05:37
rcs4sx86_​644 x 11,1008,75226.05. 06:06
r9s4sx86_​642 x 11,3335,34726.05. 05:04
r1s3x86_​644 x 12,80022,42426.05. 14:02
res2x86_​644 x 11,60014,40026.05. 06:45
r8s7sx86_​642 x 13,30013,19826.05. 04:45
rcs6x86_​644 x 23,50063,99226.05. 06:13
r5s1x86_​646 x 13,33340,09226.05. 15:30
rcs1x86_​646 x 23,46783,37626.05. 05:58
r0s1sx86_​644 x 23,30052,67226.05. 13:13
r0s0x86_​644 x 22,50040,00026.05. 13:10
res8x86_​644 x 11,90015,05226.05. 07:02
r6s8x86_​642 x 22,30018,35626.05. 16:18
res1x86_​644 x 11,60014,40026.05. 06:42
r0s2x86_​644 x 23,50055,86426.05. 13:15
rds8x86_​644 x 11,60012,74826.05. 06:39
rbs4x86_​644 x 11,2009,60026.05. 05:36
r4s6x86_​644 x 23,40054,25626.05. 15:16
r3s6sx86_​642 x 22,66721,33226.05. 14:51
rbs2x86_​644 x 12,00015,97226.05. 05:30
r0s3x86_​648 x 23,600115,20026.05. 13:18
res4sx86_​644 x 11,90015,05226.05. 06:51
r4s7sx86_​642 x 11,8337,33226.05. 15:25
r0s7sx86_​642 x 23,70029,52826.05. 13:48
res6x86_​644 x 11,1008,75226.05. 06:56
r0s5x86_​648 x 23,500115,20026.05. 13:31
r8s0x86_​642 x 22,30018,40026.05. 04:27
r5s3sx86_​644 x 11,60012,74826.05. 15:37
r6s3x86_​644 x 22,20035,12026.05. 16:09
r7s1x86_​644 x 11,60012,84026.05. 16:21
rbs1x86_​644 x 12,00015,97226.05. 05:29
rds4x86_​644 x 11,91015,32426.05. 06:33
rcs8sx86_​644 x 23,30052,79226.05. 06:25
r6s2x86_​642 x 11,6679,57826.05. 16:07
rcs8x86_​6416 x 23,700217,15226.05. 06:23
r8s4x86_​644 x 21,60028,80026.05. 04:37
rcs0x86_​648 x 22,40076,60026.05. 05:57
rbs6sx86_​642 x 11,3335,33226.05. 05:44
r9s3sx86_​644 x 13,00024,00026.05. 04:56
r1s1x86_​642 x 22,60021,69626.05. 13:56
res4x86_​644 x 11,90015,05226.05. 06:49
r8s7x86_​642 x 12,70010,77626.05. 04:44
r0s8sx86_​646 x 23,47083,38826.05. 13:53
r5s4sx86_​642 x 22,53020,26426.05. 15:41
r8s8x86_​642 x 11,3005,14426.05. 04:47
r7s7sx86_​642 x 22,30018,39626.05. 16:35
ras2x86_​642 x 11,0674,26626.05. 05:15
rds2x86_​644 x 11,91015,32426.05. 06:30
r4s0x86_​642 x 22,30018,39626.05. 14:56
res3x86_​644 x 12,00015,97226.05. 06:46
r8s2x86_​642 x 22,10016,76026.05. 04:31
rbs6x86_​644 x 11,91515,32426.05. 05:41
r0s1x86_​644 x 22,30055,99226.05. 13:11
r3s3x86_​646 x 23,33379,99226.05. 14:38
r9s2sx86_​644 x 11,60012,74830.08. 17:02
rcs5sx86_​642 x 12,80011,19826.05. 06:12
res0x86_​644 x 21,80031,99226.05. 06:40
r5s0x86_​642 x 22,20017,58226.05. 15:29
r8s4sx86_​644 x 21,60028,80026.05. 04:39
rcs3sx86_​644 x 23,30052,69625.05. 18:13
r9s1x86_​642 x 12,0003,99226.05. 04:50
r7s7x86_​644 x 11,60012,76726.05. 16:33
res5sx86_​642 x 22,20019,20026.05. 06:54
r9s6x86_​642 x 23,00023,94426.05. 05:07
r1s6x86_​642 x 22,13017,06426.05. 14:07
rcs7x86_​642 x 21,80014,39626.05. 06:15
r1s2sx86_​644 x 12,30028,00026.05. 14:00
r0s6sx86_​6410 x 23,700147,98026.05. 13:39
r3s6x86_​641 x 11,6603,33326.05. 14:50
r1s6sx86_​642 x 21,66713,33226.05. 14:09
rcs5x86_​642 x 12,80011,19826.05. 06:08
rds0x86_​644 x 21,80031,99226.05. 06:27
res1sx86_​644 x 11,60014,40026.05. 06:43
rds7x86_​644 x 11,60012,74826.05. 06:38
r5s2sx86_​644 x 24,00063,86312.04. 01:34
rcs2x86_​642 x 12,80011,23226.05. 06:01
r5s4x86_​642 x 22,53020,26426.05. 15:39
rcs4x86_​642 x 11,1004,37626.05. 06:05
r8s3x86_​644 x 12,66721,28026.05. 04:35
r2s0x86_​644 x 13,10024,80026.05. 14:15
r1s2x86_​644 x 12,30028,00026.05. 13:59
r0s3sx86_​644 x 23,60067,20026.05. 13:24
r6s1x86_​642 x 12,0007,97826.05. 16:05
r7s0x86_​642 x 22,30018,40026.05. 16:20
rds1x86_​644 x 11,91015,32426.05. 06:28
r0s6x86_​648 x 23,600115,20026.05. 13:36
r8s2sx86_​642 x 22,10016,76026.05. 04:33
r0s4sx86_​648 x 23,600115,20026.05. 13:28
rbs2sx86_​641 x 13,500007.09. 15:06
r6s4x86_​642 x 11,1004,37626.05. 16:11
rds5x86_​644 x 11,60012,74826.05. 06:35
ras8x86_​644 x 11,60014,40026.05. 05:24
res5x86_​642 x 22,20019,20026.05. 06:52
r0s5sx86_​648 x 23,600115,20026.05. 13:33
 

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