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2023-12-04 - 04:01

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OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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Number of cores/hyperthreads and bogoMIPS (by arch) - (x86 CPU strings)

BoxArch ↑CoresMHzBogo​MIPSEffective
r2s6saarch​644 x 11,3506404.12. 01:57
res3saarch​640 x 1 x 11,0001,60003.12. 15:47
r4s5saarch​644 x 11,60020004.12. 02:21
res6saarch​644 x 101,60003.12. 15:49
rbs5saarch​644 x 11,6006404.12. 03:39
r1s5aarch​644 x 11,20079604.12. 01:48
rfs1aarch​644 x 11,50043203.12. 15:54
rfs2aarch​644 x 11,50043203.12. 15:54
ras3aarch​648 x 12,0004,00004.12. 03:28
r2s1arm​v5tejl1 x 120019904.12. 01:52
r1s7arm​v6l1 x 120053020.11. 13:43
r7s3arm​v6l1 x 1700504.12. 02:51
r1s4arm​v7l2 x 11,2004804.12. 01:47
r4s2sarm​v7l1 x 180053004.12. 02:12
ras6arm​v7l1 x 11,0001,98704.12. 03:30
r7s8arm​v7l1 x 11,00099504.12. 02:57
ras5arm​v7l2 x 11,0002404.12. 03:29
r7s4arm​v7l1 x 153635104.12. 02:54
r4s2arm​v7l1 x 180079604.12. 02:11
rbs3arm​v7l4 x 19962404.12. 03:36
r7s3sarm​v7l4 x 11,40035603.12. 14:38
ras4arm​v7l1 x 150039804.12. 03:28
r7s4sarm​v7l4 x 11,50079204.12. 02:55
r4s8sarm​v7l1 x 140039804.12. 02:25
r4s1sarm​v7l4 x 11,50093604.12. 02:10
ras3sarm​v7l1 x 11,30084013.10. 03:01
r7s6arm​v7l1 x 11,00039828.02. 14:10
ras5sarm​v7l2 x 11,0002404.12. 03:29
r4s1arm​v7l4 x 11,50079204.12. 02:09
res7arm​v7l0 x 1 x 11,0001203.12. 15:50
rbs7sarm​v7l4 x 19962403.12. 15:19
r7s8sarm​v7l1 x 11,00079604.12. 02:59
r8s6arm​v7l1 x 150049804.12. 03:07
r9s7arm​v7l2 x 11,000004.12. 03:23
res7sarm​v7l0 x 1 x 11,0001203.12. 15:51
r1s4sarm​v7l2 x 14004804.12. 01:47
r5s5sarm​v7l1 x 160060004.12. 02:33
r2s3sarm​v7l0 x 1 x 16001,20004.12. 01:55
rbs3sarm​v7l4 x 11,40035604.12. 03:36
r5s7arm​v7l1 x 15286404.12. 02:38
r9s1sarm​v7l1 x 101,25014.04. 18:03
rbs7arm​v7l4 x 19961204.12. 03:42
r5s5arm​v7l1 x 160059704.12. 02:31
ras4sarm​v7l1 x 160059707.02. 02:45
rbs8arm​v7l2 x 16662,65004.12. 03:43
r5s7sarm​v7l1 x 15284804.12. 02:40
r4s5arm​v7l1 x 1500004.12. 02:21
r4s6sarm​v7l0 x 1 x 11,0006604.12. 02:22
r4s8arm​v7l1 x 140039804.12. 02:24
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r2s3arm​v7l0 x 1 x 162462404.12. 01:54
ras6sarm​v7l1 x 11,0001,98704.12. 03:31
r9s8sarm​v7l1 x 180079604.12. 03:25
r2s2arm​v7l1 x 172049904.12. 01:53
r4s3i5861 x 150099604.12. 02:15
r8s1i5861 x 130060104.12. 03:00
r3s5i5861 x 113326504.12. 02:02
rbs5i6864 x 2049,16804.12. 03:39
r3s8i6866 x 13,20038,52604.12. 02:07
r6s6i6861 x 11,6003,19104.12. 02:48
r2s6i6861 x 11,5002,99904.12. 01:56
r6s5i6861 x 11,5002,24404.12. 02:46
rbs0i6862 x 22,50017,60004.12. 03:33
ras1i6861 x 11,4002,79904.12. 03:27
r4s3si6861 x 11,4662,93204.12. 02:16
r8s5i6864 x 23,40054,39204.12. 03:07
r7s5i6861 x 11,3002,59304.12. 02:55
r3s0i6864 x 23,50055,99204.12. 01:58
r1s8i6861 x 21,6006,39804.12. 01:50
r6s7i6862 x 12,3009,17604.12. 02:49
rcs3i6862 x 11,4005,58604.12. 03:49
r3s1i6864 x 12,40019,12704.12. 01:59
r3s7i6861 x 15331,06604.12. 02:06
r4s7i6864 x 11,83314,66404.12. 02:23
r9s4i6861 x 21,0003,98804.12. 03:20
r2s4mips​641 x 180053122.09. 01:44
r5s6ppc1 x 153313304.12. 02:38
r2s8ppc1 x 14006604.12. 01:57
ras7ppc1 x 13966504.12. 03:32
r2s5ppc1 x 13966620.10. 13:50
r4s4ppc4 x 11,20049804.12. 02:17
r3s5sppc2 x 11,20040004.12. 02:04
r3s2sriscv644 x 1028404.12. 02:00
r3s2riscv641 x 11,00028404.12. 01:59
r0s4x86_​648 x 23,600115,20004.12. 01:21
r6s0x86_​642 x 10 x 21,700136,14004.12. 02:42
rbs8sx86_​644 x 22,40038,70404.12. 03:43
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r9s2x86_​644 x 11,60012,74804.12. 03:18
r9s5sx86_​642 x 13,50013,99804.12. 03:22
r1s0x86_​644 x 13,10024,79604.12. 01:44
rcs6x86_​644 x 23,50063,99204.12. 03:59
rcs7sx86_​644 x 11,50011,98004.12. 04:01
r1s8sx86_​644 x 11,90015,19604.12. 01:51
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s0x86_​642 x 22,30018,40004.12. 03:16
rds6x86_​644 x 11,60012,74803.12. 15:41
r6s8x86_​642 x 22,30018,35604.12. 02:50
res8sx86_​644 x 11,90015,05203.12. 15:52
r5s3x86_​644 x 22,00031,87204.12. 02:27
ras8sx86_​644 x 11,60012,74804.12. 03:32
r0s7x86_​648 x 23,600115,20004.12. 01:34
r0s2sx86_​6410 x 13,70073,99004.12. 01:15
r5s2x86_​644 x 12,70021,69904.12. 02:26
r0s8x86_​648 x 23,600115,20004.12. 01:39
rbs4sx86_​644 x 11,60012,74804.12. 03:38
r4s6x86_​644 x 23,40054,25604.12. 02:22
rcs4sx86_​644 x 11,1008,75201.11. 15:23
r9s4sx86_​642 x 11,3335,34704.12. 03:21
r1s3x86_​644 x 12,80022,42404.12. 01:46
res2x86_​644 x 11,60014,40003.12. 15:45
r8s7sx86_​642 x 13,30013,19804.12. 03:09
r5s1x86_​646 x 13,33340,09204.12. 02:26
rcs1x86_​646 x 23,46783,37604.12. 03:47
r0s1sx86_​644 x 23,30052,67204.12. 01:11
r0s0x86_​644 x 22,50039,99204.12. 01:10
res8x86_​644 x 11,90015,05203.12. 15:51
res1x86_​644 x 11,60014,40003.12. 15:43
r0s2x86_​644 x 23,50055,87204.12. 01:12
rds4x86_​644 x 11,91015,32403.12. 15:39
rds8x86_​644 x 11,60012,74803.12. 15:42
rbs4x86_​644 x 11,2009,60004.12. 03:37
r3s6sx86_​642 x 22,66721,33204.12. 02:05
rbs2x86_​644 x 23,20051,20004.12. 03:34
rbs6sx86_​642 x 11,3335,33204.12. 03:41
r0s3x86_​648 x 23,600115,20004.12. 01:16
r4s7sx86_​642 x 11,8337,33204.12. 02:23
r0s7sx86_​642 x 23,70029,52804.12. 01:37
res6x86_​644 x 11,1008,75203.12. 15:48
r0s5x86_​648 x 23,500115,20004.12. 01:27
r8s0x86_​642 x 22,30018,40004.12. 02:59
r5s3sx86_​644 x 11,60012,74804.12. 02:27
r6s3x86_​644 x 22,20035,12004.12. 02:45
r7s1x86_​644 x 11,60012,84004.12. 02:51
rbs1x86_​644 x 13,10028,80004.12. 03:34
rcs8sx86_​644 x 23,30052,79203.12. 15:36
r6s2x86_​642 x 11,6679,57604.12. 02:44
rcs8x86_​6416 x 23,700217,15203.12. 15:36
r8s4x86_​644 x 21,60028,80004.12. 03:03
rcs0x86_​648 x 22,40076,60004.12. 03:46
r9s3sx86_​644 x 13,00024,00004.12. 03:19
r1s1x86_​642 x 22,60021,69604.12. 01:44
res4x86_​644 x 11,90015,05225.10. 03:17
rds2x86_​644 x 11,91015,32403.12. 15:38
r8s7x86_​642 x 12,70010,77604.12. 03:08
r0s8sx86_​646 x 23,47083,38804.12. 01:43
r5s4sx86_​642 x 22,53020,26404.12. 02:29
r8s8x86_​642 x 11,3005,14404.12. 03:10
r4s0x86_​642 x 22,30018,39604.12. 02:08
r7s7sx86_​642 x 22,30018,39604.12. 02:57
ras2x86_​642 x 11,0674,26604.12. 03:27
res3x86_​644 x 12,00015,97203.12. 15:46
r8s2x86_​642 x 22,10016,76004.12. 03:01
rbs6x86_​644 x 11,91515,32404.12. 03:40
r0s1x86_​644 x 22,30055,99204.12. 01:11
r3s3x86_​646 x 23,33379,99204.12. 02:01
r9s2sx86_​644 x 11,60012,74830.08. 17:02
rcs5sx86_​642 x 12,80011,19804.12. 03:58
res0x86_​644 x 21,80031,99203.12. 15:42
r5s0x86_​642 x 22,20017,58204.12. 02:25
r8s4sx86_​644 x 21,60028,80004.12. 03:05
r1s6x86_​642 x 22,13017,06404.12. 01:48
rcs3sx86_​644 x 23,30052,69604.12. 03:50
r9s1x86_​642 x 12,0003,99204.12. 03:17
r7s7x86_​644 x 11,60012,76704.12. 02:56
res5sx86_​642 x 22,20019,20003.12. 15:48
r9s6x86_​642 x 23,00023,94404.12. 03:22
rcs5x86_​642 x 12,80011,19804.12. 03:55
rcs7x86_​642 x 21,80014,39604.12. 04:00
r1s2sx86_​644 x 12,30028,00004.12. 01:46
r0s6sx86_​6410 x 23,700147,98004.12. 01:32
r3s6x86_​641 x 21,6606,66624.11. 13:58
r1s6sx86_​642 x 21,66713,33204.12. 01:49
rds0x86_​644 x 21,80031,99203.12. 15:37
res1sx86_​644 x 11,60014,40003.12. 15:44
rds7x86_​644 x 11,60012,74803.12. 15:41
r5s2sx86_​644 x 24,00063,86312.04. 01:34
rcs2x86_​642 x 12,80011,23204.12. 03:48
r5s4x86_​642 x 22,53020,26404.12. 02:28
rcs4x86_​642 x 11,1004,37604.12. 03:52
r8s3x86_​644 x 12,66721,27604.12. 03:02
r2s0x86_​644 x 13,10024,79604.12. 01:51
r1s2x86_​644 x 12,30028,00004.12. 01:45
r0s3sx86_​644 x 23,60067,20004.12. 01:18
r6s1x86_​642 x 12,0007,97804.12. 02:43
rds3x86_​644 x 11,91015,32403.12. 15:39
r7s0x86_​642 x 22,30018,40004.12. 02:50
rds1x86_​644 x 11,91015,32403.12. 15:37
r0s6x86_​648 x 23,600115,20004.12. 01:30
r3s4x86_​641 x 21,4005,60010.01. 01:28
r8s2sx86_​642 x 22,10016,76004.12. 03:02
r0s4sx86_​648 x 23,600115,20004.12. 01:23
rbs2sx86_​641 x 13,500007.09. 15:06
r6s4x86_​642 x 11,1004,37630.11. 14:32
rds5x86_​644 x 11,60012,74803.12. 15:40
ras8x86_​644 x 11,60014,40003.12. 15:11
res5x86_​642 x 22,20019,20003.12. 15:47
r0s5sx86_​648 x 23,600115,20004.12. 01:29
ras0x86_​642 x 22,30018,41704.12. 03:26
r9s3x86_​644 x 11,60012,74804.12. 03:18
 

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