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2024-09-18 - 16:20

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OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (by cores) - (x86 CPU strings)

BoxArchCores ↑MHzBogo​MIPSEffective
res7sarm​v7l0 x 1 x 11,0001218.09. 15:10
r2s3sarm​v7l0 x 1 x 16001,20018.09. 13:29
r4s6sarm​v7l0 x 1 x 11,0006618.09. 13:51
r2s3arm​v7l0 x 1 x 162462418.09. 13:28
res3saarch​640 x 1 x 11,0001,60018.09. 15:05
res7arm​v7l0 x 1 x 11,0001218.09. 15:09
rfs4arm​v7l1 x 180080018.09. 15:13
r8s6arm​v7l1 x 150049818.09. 14:21
r5s7sarm​v7l1 x 15284818.09. 14:03
ras3sarm​v7l1 x 11,30084018.09. 14:35
r2s5ppc1 x 13966618.09. 13:30
r5s5sarm​v7l1 x 160060018.09. 13:59
r3s2riscv641 x 11,00028418.09. 13:34
r1s7arm​v6l1 x 11,00053018.09. 13:25
r5s7arm​v7l1 x 15286418.09. 14:02
r7s3arm​v6l1 x 1700518.09. 14:11
rfs6arm​v7l1 x 16671,33218.09. 15:15
r9s1sarm​v7l1 x 101,25014.04. 18:03
r5s5arm​v7l1 x 160059718.09. 13:58
ras4sarm​v7l1 x 160059707.02. 02:45
r3s5i5861 x 113326518.09. 13:37
r3s7i6861 x 15331,06618.09. 13:40
r4s5arm​v7l1 x 1500018.09. 13:49
r4s8arm​v7l1 x 140039818.09. 13:53
rbs2sx86_​641 x 13,500007.09. 15:06
ras6sarm​v7l1 x 11,0001,98718.09. 14:38
r9s8sarm​v7l1 x 180079618.09. 14:33
r2s2arm​v7l1 x 172049918.09. 13:28
r4s2sarm​v7l1 x 180053018.09. 13:44
r7s8arm​v7l1 x 11,00099518.09. 14:16
r5s6ppc1 x 153313318.09. 14:02
r7s4arm​v7l1 x 153634818.09. 14:13
r4s2arm​v7l1 x 180079618.09. 13:43
r4s3i5861 x 150099618.09. 13:46
r6s6i6861 x 11,6003,19218.09. 14:08
r2s6i6861 x 11,5002,99918.09. 13:30
r6s5i6861 x 11,5002,99218.09. 14:07
r2s8ppc1 x 14006618.09. 13:32
ras1i6861 x 11,4002,79918.09. 14:34
ras4arm​v7l1 x 150039818.09. 14:36
r4s3si6861 x 11,4662,93228.07. 02:17
r4s8sarm​v7l1 x 140039818.09. 13:53
rfs4sarm​v7l1 x 180080018.09. 15:14
r7s6arm​v7l1 x 11,00039828.02. 14:10
r8s1i5861 x 135070118.09. 14:18
r7s5i6861 x 11,3002,59318.09. 14:14
rfs8arm​v7l1 x 11,00012018.09. 15:17
r2s1arm​v5tejl1 x 120019918.09. 13:27
r7s8sarm​v7l1 x 11,00099618.09. 14:17
r2s4mips​641 x 180053124.12. 13:46
ras7ppc1 x 13966518.09. 14:38
rfs6sarm​v7l1 x 16671,33218.09. 15:16
r9s4i6861 x 21,0003,99018.09. 14:26
r3s6x86_​641 x 21,6606,66618.09. 13:39
rcs5x86_​642 x 12,80011,19818.09. 14:52
rbs6sx86_​642 x 11,3335,33229.08. 03:00
r1s4sarm​v7l2 x 14004818.09. 13:23
rcs3i6862 x 11,4005,58818.09. 14:49
rcs5sx86_​642 x 12,80011,19818.09. 14:53
r9s1x86_​642 x 12,0003,99218.09. 14:24
rcs2x86_​642 x 12,80011,23218.09. 14:48
rbs8arm​v7l2 x 16662,65018.09. 14:45
rcs4x86_​642 x 11,1004,37618.09. 14:50
r3s5sppc2 x 11,20040018.09. 13:39
r6s1x86_​642 x 12,0007,97818.09. 14:06
r6s4x86_​642 x 11,1004,37618.09. 14:07
r1s4arm​v7l2 x 11,2004818.09. 13:22
r1s8i6861 x 21,6006,39818.09. 13:25
r9s5sx86_​642 x 13,30013,19818.09. 14:32
r7s2aarch​642 x 11,7009618.09. 14:10
r9s5x86_​642 x 12,70010,77413.07. 03:15
ras5arm​v7l2 x 11,0002418.09. 14:36
r9s4sx86_​642 x 11,3335,34718.09. 14:31
r8s7sx86_​642 x 13,00011,98018.09. 14:22
r4s7sx86_​642 x 11,8337,33218.09. 13:52
ras5sarm​v7l2 x 11,0002418.09. 14:37
r6s2x86_​642 x 11,6679,57818.09. 14:06
r6s7i6862 x 12,3009,17618.09. 14:09
r8s8x86_​642 x 11,3005,14418.09. 14:23
r9s7arm​v7l2 x 11,000018.09. 14:32
ras2x86_​642 x 11,0674,26618.09. 14:34
r1s6x86_​642 x 22,13017,06418.09. 13:24
r6s8x86_​642 x 22,30018,35618.09. 14:09
r4s0x86_​642 x 22,30018,39618.09. 13:42
r8s2x86_​642 x 22,10016,76018.09. 14:19
r5s0x86_​642 x 22,20017,58218.09. 13:53
res5sx86_​642 x 22,20019,20018.09. 15:07
r9s6x86_​642 x 23,00023,94418.09. 14:32
rcs7x86_​642 x 21,80014,40018.09. 14:54
r1s6sx86_​642 x 21,66713,33218.09. 13:24
r5s4x86_​642 x 22,53020,26418.09. 13:56
r7s0x86_​642 x 22,30018,40018.09. 14:09
r8s2sx86_​642 x 22,10016,76018.09. 14:19
res5x86_​642 x 22,20019,20018.09. 15:07
ras0x86_​642 x 22,30018,41718.09. 14:34
r9s0x86_​642 x 22,30018,39618.09. 14:23
rbs0i6862 x 22,50017,60018.09. 14:39
r3s6sx86_​642 x 22,66721,33218.09. 13:40
r0s7sx86_​642 x 23,70029,53226.08. 13:20
r8s0x86_​642 x 22,30018,40018.09. 14:17
r1s1x86_​642 x 22,60021,69618.09. 13:21
r4s4ppc4 x 11,20049818.09. 13:47
r3s1i6864 x 12,40019,12718.09. 13:34
r2s7saarch​644 x 11,50043218.09. 13:32
r5s4sx86_​642 x 22,53020,26418.09. 13:56
r7s7sx86_​642 x 22,30018,39618.09. 14:15
rds4x86_​644 x 11,91015,32418.09. 15:01
r5s8x86_​644 x 12,00015,97218.09. 14:05
rds2x86_​644 x 11,91015,32418.09. 15:00
res3x86_​644 x 12,00015,97218.09. 15:05
rbs6x86_​644 x 11,91515,32418.09. 14:43
r9s2sx86_​644 x 11,60012,74830.08. 17:02
rbs3sarm​v7l4 x 11,40035618.09. 14:40
rcs3sx86_​644 x 13,30026,39618.09. 14:50
r7s7x86_​644 x 11,60012,76718.09. 14:15
r1s5aarch​644 x 11,20079618.09. 13:23
rbs7arm​v7l4 x 19961218.09. 14:44
r1s2sx86_​644 x 12,30028,00018.09. 13:21
rfs1aarch​644 x 11,50043218.09. 15:12
res1sx86_​644 x 11,60014,40018.09. 15:04
rds7x86_​644 x 11,60012,74818.09. 15:02
r8s6sx86_​644 x 13,30026,41618.09. 14:22
rfs2aarch​644 x 11,50043218.09. 15:12
r8s3x86_​644 x 12,66721,28018.09. 14:20
r2s0x86_​644 x 13,10024,80018.09. 13:26
r1s2x86_​644 x 12,30028,00018.09. 13:21
r4s7i6864 x 11,83314,66418.09. 13:52
r7s2sarm​v7l4 x 11,50072013.07. 02:16
rds1x86_​644 x 11,91015,32418.09. 14:59
rds5x86_​644 x 11,60012,74818.09. 15:01
ras8x86_​644 x 11,60014,40018.09. 14:39
r9s3x86_​644 x 11,60012,74818.09. 14:25
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r9s2x86_​644 x 11,60012,74818.09. 14:25
r1s0x86_​644 x 13,10024,80018.09. 13:20
rcs7sx86_​644 x 11,50011,98018.09. 14:55
r1s8sx86_​644 x 11,90015,19618.09. 13:26
rds6x86_​644 x 11,60012,74818.09. 15:02
res8sx86_​644 x 11,90015,05218.09. 15:11
rfs3x86_​644 x 11,60012,74818.09. 15:13
ras8sx86_​644 x 11,60012,74818.09. 14:39
r5s2x86_​644 x 12,70021,69918.09. 13:54
rbs4sx86_​644 x 11,60012,74818.09. 14:42
rcs4sx86_​644 x 11,1008,75216.09. 03:07
r1s3x86_​644 x 12,80022,42418.09. 13:22
res2x86_​644 x 11,60014,40018.09. 15:04
ras2sx86_​644 x 11,90015,05218.09. 14:35
rbs3arm​v7l4 x 19962418.09. 14:40
rfs3sx86_​644 x 11,60012,74818.09. 15:13
r3s2sriscv644 x 1028418.09. 13:35
res8x86_​644 x 11,90015,05218.09. 15:11
res1x86_​644 x 11,60014,40018.09. 15:04
r7s3sarm​v7l4 x 11,40015218.09. 14:12
rds8x86_​644 x 11,60012,74818.09. 15:03
rfs7sx86_​644 x 17006,44818.09. 15:17
rbs4x86_​644 x 11,2009,60018.09. 14:41
r7s4sarm​v7l4 x 11,5001,08018.09. 14:14
rbs2x86_​644 x 12,00015,97230.06. 06:26
res4sx86_​644 x 11,90015,05218.09. 15:06
r4s5saarch​644 x 11,60020018.09. 13:49
res6x86_​644 x 11,1008,75218.09. 15:08
r5s3sx86_​644 x 11,60012,74818.09. 13:55
r4s1sarm​v7l4 x 11,50086418.09. 13:42
r7s1x86_​644 x 11,60012,84018.09. 14:10
rbs1x86_​644 x 12,00015,97230.06. 06:25
r4s1arm​v7l4 x 11,50072018.09. 13:42
r2s7aarch​644 x 12,40043218.09. 13:31
rbs7sarm​v7l4 x 19962418.09. 14:45
r9s3sx86_​644 x 13,00024,00018.09. 14:26
res4x86_​644 x 11,90015,05218.09. 15:06
r8s7x86_​644 x 13,20025,49618.09. 14:22
res6saarch​644 x 101,60018.09. 15:08
rbs5saarch​644 x 11,6006418.09. 14:43
r3s4aarch​646 x 11,3009618.09. 13:36
r3s8i6866 x 13,20038,52618.09. 13:41
r5s1x86_​646 x 13,33340,09218.09. 13:54
rbs5i6864 x 2049,53918.09. 14:42
rcs6x86_​644 x 23,50063,99218.09. 14:53
r4s6x86_​644 x 23,40054,25618.09. 13:50
r8s5i6864 x 23,40054,40018.09. 14:21
rfs7x86_​644 x 22,60041,60018.09. 15:16
r0s1x86_​644 x 22,30056,00018.09. 13:10
res0x86_​644 x 23,40054,39218.09. 15:03
r8s4sx86_​644 x 21,60028,80018.09. 14:20
rds0x86_​644 x 21,80031,99218.09. 14:59
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r0s3sx86_​644 x 23,60067,20026.08. 01:14
rbs8sx86_​644 x 22,40038,70418.09. 14:46
r5s3x86_​644 x 22,00031,87218.09. 13:55
r0s1sx86_​644 x 23,30052,67218.09. 13:10
r0s0x86_​644 x 22,50040,00018.09. 13:10
r0s2x86_​644 x 23,50055,86418.09. 13:11
r6s3x86_​644 x 22,20035,12018.09. 14:06
rcs8sx86_​644 x 23,30052,80018.09. 14:58
r8s4x86_​644 x 21,60028,80018.09. 14:20
r3s0i6864 x 23,50055,99218.09. 13:33
ras3aarch​648 x 12,0004,00018.09. 14:35
ras6aarch​648 x 12,0003,20018.09. 14:37
r0s2sx86_​6410 x 13,70073,99018.09. 13:11
r3s3x86_​646 x 23,33379,99218.09. 13:35
rcs1x86_​646 x 23,46783,37618.09. 14:48
r0s8sx86_​646 x 23,47083,37618.09. 13:20
r0s6x86_​648 x 23,600115,20018.09. 13:16
r0s4sx86_​648 x 23,600115,20018.09. 13:14
r0s5sx86_​648 x 23,600115,20018.09. 13:16
r0s4x86_​648 x 23,600115,20018.09. 13:14
r0s7x86_​648 x 23,600115,20018.09. 13:18
r0s8x86_​648 x 23,600115,20018.09. 13:19
r0s3x86_​648 x 23,600115,20018.09. 13:12
r0s5x86_​648 x 23,500115,20018.09. 13:15
rcs0x86_​648 x 22,40076,60018.09. 14:47
r0s6sx86_​6410 x 23,700147,98018.09. 13:17
rfs0x86_​6416 x 22,000127,96818.09. 15:12
rcs8x86_​6416 x 23,700217,15218.09. 14:58
r6s0x86_​642 x 10 x 21,700136,18018.09. 14:05
 

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