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2017-03-27 - 06:42

Number of cores/hyperthreads and bogoMIPS (by bogoMIPS) - (x86 CPU strings)

BoxArchCoresMHzBogo​MIPSEffective
r4s5arm​v7l1 x 1500027.03. 01:34
r9s7arm​v7l2 x 11000027.03. 01:59
rbs7arm​v7l4 x 19962427.03. 02:07
ras7ppc1 x 13966527.03. 02:04
r2s5ppc1 x 13966627.03. 01:19
r5s6ppc1 x 153313327.03. 01:37
r7s3sarm​v7l4 x 1120015227.03. 01:45
r2s1arm​v5tejl1 x 120019927.03. 01:18
rbs3sarm​v7l4 x 1120022827.03. 02:06
r7s4arm​v7l1 x 153634827.03. 01:45
r4s2sarm​v7l1 x 180039827.03. 01:31
r4s2arm​v7l1 x 180039827.03. 01:29
ras4arm​v7l1 x 150039827.03. 02:03
r7s6arm​v7l1 x 1100039827.03. 01:46
r1s5ppc2 x 1120040027.03. 01:16
r5s7mips​1 x 149249227.03. 01:38
r2s3arm​v7l1 x 160049527.03. 01:18
r8s6arm​v7l1 x 150049827.03. 01:55
r2s2arm​v7l1 x 172049927.03. 01:18
r1s7arm​v6l1 x 172053027.03. 01:16
r2s8arm​v6l1 x 153253027.03. 01:20
r2s4mips​641 x 180053127.03. 01:18
r8s1i5861 x 130060127.03. 01:53
ras3sarm​v7l8 x 1130074427.03. 02:03
r7s8arm​v7l1 x 1100079627.03. 01:51
r7s8sarm​v7l1 x 1100099327.03. 01:52
r4s3i5861 x 150099627.03. 01:33
r3s7i6861 x 1533106627.03. 01:24
r7s7arm​v7l2 x 11000118127.03. 01:48
r7s2i6861 x 1600119627.03. 01:43
r7s1i6861 x 1800160227.03. 01:42
rbs2i6861 x 11000199927.03. 02:05
r7s5i6861 x 11300259327.03. 01:46
rbs8arm​v7l2 x 1666265027.03. 02:07
ras1i6861 x 11400279927.03. 02:02
r6s5i6861 x 11500299227.03. 01:40
r2s6i6861 x 11500299927.03. 01:19
r3s2i6861 x 11530306127.03. 01:21
r6s6i6861 x 11600319227.03. 01:41
r1s3x86_​641 x 11800359027.03. 01:15
r9s4i6861 x 21000399027.03. 01:58
r9s1x86_​642 x 12000399227.03. 01:57
r4s8x86_​642 x 11140400027.03. 01:35
ras2x86_​642 x 11067426627.03. 02:03
r6s4x86_​641 x 12200438925.03. 13:34
r4s4x86_​642 x 11333532827.03. 01:33
rcs3i6862 x 11400558627.03. 02:08
r3s4x86_​641 x 21400560027.03. 01:22
r9s8arm​v7l4 x 1996632427.03. 01:59
r1s8i6861 x 21600639827.03. 01:17
r3s6x86_​641 x 21667666627.03. 01:22
r8s8i6862 x 11900758227.03. 01:56
r6s1x86_​642 x 12000798027.03. 01:38
rbs5i6862 x 12000799927.03. 02:06
r6s7i6862 x 12300917627.03. 01:41
ras8i6862 x 125001077627.03. 02:04
r9s5x86_​642 x 127001077627.03. 01:58
r8s7x86_​642 x 127001077627.03. 01:55
rcs2x86_​642 x 128001123327.03. 02:07
r8s2x86_​642 x 129001157227.03. 01:53
r4s7x86_​644 x 116001279627.03. 01:35
r1s4x86_​642 x 216671333227.03. 01:15
rcs7x86_​642 x 218001439627.03. 02:09
r8s4si6864 x 118331466427.03. 01:54
r8s4i6864 x 118331466427.03. 01:54
r4s1sx86_​642 x 221001673827.03. 01:29
r1s6x86_​642 x 221301702027.03. 01:16
r5s0x86_​642 x 222001756027.03. 01:36
r6s8x86_​642 x 223001835627.03. 01:42
r0s1x86_​642 x 223001839627.03. 01:10
r9s0x86_​642 x 223001839627.03. 01:56
r8s0x86_​642 x 223001839627.03. 01:52
r4s0x86_​642 x 223001840027.03. 01:27
r7s0x86_​642 x 223001840027.03. 01:42
ras0x86_​642 x 223001840027.03. 02:02
r3s1i6864 x 124001912727.03. 01:21
rcs6x86_​644 x 125001995227.03. 02:08
rbs0i6862 x 225001995227.03. 02:05
r0s0x86_​642 x 225001995227.03. 01:10
r3s0i6862 x 225001995227.03. 01:20
r5s4x86_​642 x 225302026827.03. 01:37
r0s2x86_​644 x 126672127627.03. 01:10
r4s1x86_​642 x 227002155427.03. 01:28
r9s6x86_​642 x 230002394427.03. 01:59
r2s0x86_​644 x 131002480027.03. 01:17
r1s0x86_​644 x 131002480027.03. 01:14
rbs1x86_​644 x 131002480027.03. 02:05
r0s4x86_​642 x 237002953227.03. 01:11
r6s3x86_​644 x 222003512027.03. 01:39
r9s3x86_​644 x 225003664027.03. 01:57
r3s8i6866 x 132003852627.03. 01:25
r9s2x86_​644 x 227004320027.03. 01:57
r0s1sx86_​644 x 233005279227.03. 01:10
r5s1i6864 x 233305318527.03. 01:36
r4s6x86_​644 x 234005425627.03. 01:34
r8s5i6864 x 234005440027.03. 01:54
r9s5sx86_​644 x 234005452827.03. 01:58
r8s7sx86_​644 x 234005452827.03. 01:55
r8s3x86_​644 x 235005587227.03. 01:54
r0s6x86_​644 x 235005587227.03. 01:12
r0s5x86_​644 x 235005587227.03. 01:12
r6s0x86_​648 x 136005779227.03. 01:38
r0s8x86_​644 x 240006416127.03. 01:12
r3s3x86_​646 x 233337999227.03. 01:21
r0s8sx86_​646 x 234708334727.03. 01:13
r0s3x86_​646 x 236008640027.03. 01:11
r0s7x86_​648 x 230009593625.03. 13:13
r1s1x86_​642 x 16 x 1210013438427.03. 01:14
 

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