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2024-04-15 - 01:22

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OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (by bogoMIPS) - (x86 CPU strings)

BoxArchCoresMHzBogo​MIPS ↑Effective
r4s5arm​v7l1 x 1500014.04. 02:12
rbs2sx86_​641 x 13,500007.09. 15:06
r9s7arm​v7l2 x 11,000014.04. 16:13
r7s3arm​v6l1 x 1700514.04. 15:42
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
rbs7arm​v7l4 x 19961214.04. 16:29
res7arm​v7l0 x 1 x 11,0001214.04. 17:05
ras5arm​v7l2 x 11,0002414.04. 16:18
rbs3arm​v7l4 x 19962414.04. 16:23
ras5sarm​v7l2 x 11,0002414.04. 16:18
rbs7sarm​v7l4 x 19962414.04. 16:30
r1s4sarm​v7l2 x 14004814.04. 01:34
r1s4arm​v7l2 x 11,2004814.04. 01:33
r5s7sarm​v7l1 x 15286414.04. 15:34
r2s6saarch​644 x 11,3506414.04. 01:43
r5s7arm​v7l1 x 15286414.04. 15:32
rbs5saarch​644 x 11,6006414.04. 16:27
r2s5ppc1 x 13966627.03. 13:43
r4s6sarm​v7l0 x 1 x 11,0006614.04. 02:14
ras7ppc1 x 13966514.04. 16:20
r2s8ppc1 x 14006614.04. 01:46
r3s4aarch​646 x 11,3009614.04. 01:51
r5s6ppc1 x 153313314.04. 15:31
r2s1arm​v5tejl1 x 120019914.04. 01:40
r4s5saarch​644 x 11,60020027.03. 14:13
r3s5i5861 x 113326514.04. 01:52
r3s2riscv641 x 11,00028414.04. 01:48
r3s2sriscv644 x 1028414.04. 01:50
r7s4arm​v7l1 x 153634814.04. 15:45
rbs3sarm​v7l4 x 11,40035614.04. 16:24
r7s3sarm​v7l4 x 11,40035614.04. 15:44
r4s8arm​v7l1 x 140039814.04. 02:16
ras4arm​v7l1 x 150039814.04. 16:17
r4s8sarm​v7l1 x 140039814.04. 02:17
r7s6arm​v7l1 x 11,00039828.02. 14:10
r3s5sppc2 x 11,20040014.04. 01:54
r2s7saarch​644 x 11,50043214.04. 01:45
rfs1aarch​644 x 11,50043214.04. 17:08
rfs2aarch​644 x 11,50043214.04. 17:08
r2s7aarch​644 x 12,40043214.04. 01:44
r8s6arm​v7l1 x 150049814.04. 15:57
r4s4ppc4 x 11,20049814.04. 02:07
r2s2arm​v7l1 x 172049914.04. 01:40
r1s7arm​v6l1 x 172053014.04. 01:37
r4s2sarm​v7l1 x 180053014.04. 02:02
r2s4mips​641 x 180053124.12. 13:46
r5s5arm​v7l1 x 160059714.04. 15:25
ras4sarm​v7l1 x 160059707.02. 02:45
r5s5sarm​v7l1 x 160060014.04. 15:28
r8s1i5861 x 130060126.03. 02:51
r2s3arm​v7l0 x 1 x 162462414.04. 01:41
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r4s1arm​v7l4 x 11,50072014.04. 01:59
r1s5aarch​644 x 11,20079614.04. 01:35
r9s8sarm​v7l1 x 180079614.04. 16:14
r4s2arm​v7l1 x 180079614.04. 02:01
r7s8sarm​v7l1 x 11,00079614.04. 15:51
rfs4arm​v7l1 x 180080014.04. 17:09
rfs4sarm​v7l1 x 180080014.04. 17:11
ras3sarm​v7l1 x 11,30084014.04. 16:17
r7s8arm​v7l1 x 11,00099514.04. 15:50
r4s3i5861 x 150099614.04. 02:04
r4s1sarm​v7l4 x 11,5001,00814.04. 02:00
r3s7i6861 x 15331,06614.04. 01:56
r7s4sarm​v7l4 x 11,5001,08014.04. 15:46
r2s3sarm​v7l0 x 1 x 16001,20014.04. 01:42
r9s1sarm​v7l1 x 101,25014.04. 18:03
res3saarch​640 x 1 x 11,0001,60014.04. 17:00
res6saarch​644 x 101,60014.04. 17:05
ras6sarm​v7l1 x 11,0001,98714.04. 16:19
ras6arm​v7l1 x 11,0001,98714.04. 16:19
r7s5i6861 x 11,3002,59314.04. 15:46
rbs8arm​v7l2 x 16662,65014.04. 16:31
ras1i6861 x 11,4002,79914.04. 16:16
r4s3si6861 x 11,4662,93214.04. 02:06
r6s5i6861 x 11,5002,99214.04. 15:39
r2s6i6861 x 11,5002,99914.04. 01:43
r6s6i6861 x 11,6003,19114.04. 15:40
r3s6x86_​641 x 11,6603,33314.04. 01:55
r9s4i6861 x 21,0003,99014.04. 16:05
r9s1x86_​642 x 12,0003,99214.04. 16:02
ras3aarch​648 x 12,0004,00014.04. 16:16
ras2x86_​642 x 11,0674,26614.04. 16:16
rcs4x86_​642 x 11,1004,37614.04. 16:40
r6s4x86_​642 x 11,1004,37614.04. 15:38
r8s8x86_​642 x 11,3005,14414.04. 16:00
rbs6sx86_​642 x 11,3335,33214.04. 16:28
r9s4sx86_​642 x 11,3335,34714.04. 16:10
rcs3i6862 x 11,4005,58614.04. 16:36
r1s8i6861 x 21,6006,39814.04. 01:37
r4s7sx86_​642 x 11,8337,33214.04. 02:15
r6s1x86_​642 x 12,0007,97814.04. 15:36
rcs4sx86_​644 x 11,1008,75214.04. 16:41
res6x86_​644 x 11,1008,75214.04. 17:04
r6s7i6862 x 12,3009,17611.01. 02:44
r6s2x86_​642 x 11,6679,57814.04. 15:37
rbs4x86_​644 x 11,2009,60014.04. 16:25
r9s5x86_​642 x 12,70010,77413.07. 03:15
r8s7x86_​642 x 12,70010,77614.04. 15:58
rcs5x86_​642 x 12,80011,19814.04. 16:41
rcs5sx86_​642 x 12,80011,19814.04. 16:43
rcs2x86_​642 x 12,80011,23214.04. 16:36
rcs7sx86_​644 x 11,50011,98014.04. 16:46
r9s2sx86_​644 x 11,60012,74830.08. 17:02
rds7x86_​644 x 11,60012,74814.04. 16:56
rds5x86_​644 x 11,60012,74814.04. 16:54
r9s3x86_​644 x 11,60012,74814.04. 16:04
r9s2x86_​644 x 11,60012,74814.04. 16:03
rds6x86_​644 x 11,60012,74814.04. 16:55
ras8sx86_​644 x 11,60012,74809.04. 15:24
rbs4sx86_​644 x 11,60012,74814.04. 16:26
rds8x86_​644 x 11,60012,74814.04. 16:56
r5s3sx86_​644 x 11,60012,74814.04. 02:20
r7s7x86_​644 x 11,60012,76714.04. 15:47
r7s1x86_​644 x 11,60012,84014.04. 15:41
r8s7sx86_​642 x 13,30013,19814.04. 15:58
r1s6sx86_​642 x 21,66713,33214.04. 01:36
r9s5sx86_​642 x 13,50013,99814.04. 16:11
rcs7x86_​642 x 21,80014,39614.04. 16:45
res1sx86_​644 x 11,60014,40014.04. 16:58
ras8x86_​644 x 11,60014,40014.04. 16:21
res2x86_​644 x 11,60014,40014.04. 16:59
res1x86_​644 x 11,60014,40014.04. 16:57
r4s7i6864 x 11,83314,66414.04. 02:15
res8sx86_​644 x 11,90015,05214.04. 17:07
res8x86_​644 x 11,90015,05214.04. 17:06
res4sx86_​644 x 11,90015,05214.04. 17:01
res4x86_​644 x 11,90015,05214.04. 17:01
r1s8sx86_​644 x 11,90015,19614.04. 01:39
rds3x86_​644 x 11,91015,32414.04. 16:53
rds4x86_​644 x 11,91015,32414.04. 16:53
rds2x86_​644 x 11,91015,32414.04. 16:52
rbs6x86_​644 x 11,91515,32414.04. 16:27
rds1x86_​644 x 11,91015,32414.04. 16:51
res3x86_​644 x 12,00015,97214.04. 16:59
r8s2x86_​642 x 22,10016,76014.04. 15:52
r8s2sx86_​642 x 22,10016,76014.04. 15:53
r1s6x86_​642 x 22,13017,06414.04. 01:35
r5s0x86_​642 x 22,20017,58214.04. 02:17
rbs0i6862 x 22,50017,60014.04. 16:21
r6s8x86_​642 x 22,30018,35614.04. 15:40
r4s0x86_​642 x 22,30018,39614.04. 01:58
r7s7sx86_​642 x 22,30018,39614.04. 15:48
r7s0x86_​642 x 22,30018,40014.04. 15:41
r9s0x86_​642 x 22,30018,40014.04. 16:01
r8s0x86_​642 x 22,30018,40014.04. 15:51
ras0x86_​642 x 22,30018,41614.04. 16:15
r3s1i6864 x 12,40019,12714.04. 01:48
res5sx86_​642 x 22,20019,20014.04. 17:03
res5x86_​642 x 22,20019,20014.04. 17:02
r5s4x86_​642 x 22,53020,26414.04. 13:22
r5s4sx86_​642 x 22,53020,26414.04. 15:23
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r8s3x86_​644 x 12,66721,28014.04. 15:54
r3s6sx86_​642 x 22,66721,33214.04. 01:55
r1s1x86_​642 x 22,60021,69614.04. 01:30
r5s2x86_​644 x 12,70021,69913.04. 14:24
r1s3x86_​644 x 12,80022,42414.04. 01:32
r9s6x86_​642 x 23,00023,94414.04. 16:12
r9s3sx86_​644 x 13,00024,00014.04. 16:04
r1s0x86_​644 x 13,10024,79614.04. 01:29
r2s0x86_​644 x 13,10024,80014.04. 01:39
r1s2sx86_​644 x 12,30028,00014.04. 01:32
r1s2x86_​644 x 12,30028,00014.04. 01:31
r8s4sx86_​644 x 21,60028,80014.04. 15:55
rbs1x86_​644 x 13,10028,80014.04. 16:22
r8s4x86_​644 x 21,60028,80014.04. 15:55
r0s7sx86_​642 x 23,70029,52814.04. 01:26
r5s3x86_​644 x 22,00031,87214.04. 02:19
res0x86_​644 x 21,80031,99214.04. 16:57
rds0x86_​644 x 21,80031,99214.04. 16:51
r6s3x86_​644 x 22,20035,12014.04. 15:37
r3s8i6866 x 13,20038,52614.04. 01:57
rbs8sx86_​644 x 22,40038,70414.04. 16:32
r0s0x86_​644 x 22,50040,00015.04. 01:10
r5s1x86_​646 x 13,33340,09214.04. 02:18
rbs5i6864 x 2049,53914.04. 16:26
rbs2x86_​644 x 23,20051,20014.04. 16:23
r0s1sx86_​644 x 23,30052,67215.04. 01:11
rcs3sx86_​644 x 23,30052,69614.04. 16:37
rcs8sx86_​644 x 23,30052,79214.04. 16:50
r4s6x86_​644 x 23,40054,25614.04. 02:12
r8s5i6864 x 23,40054,40014.04. 15:56
r0s2x86_​644 x 23,50055,86415.04. 01:11
r0s1x86_​644 x 22,30055,99215.04. 01:10
r3s0i6864 x 23,50055,99214.04. 01:47
r5s2sx86_​644 x 24,00063,86312.04. 01:34
rcs6x86_​644 x 23,50063,99214.04. 16:44
r0s3sx86_​644 x 23,60067,20015.04. 01:15
r0s2sx86_​6410 x 13,70073,99015.04. 01:12
rcs0x86_​648 x 22,40076,60014.04. 16:34
r3s3x86_​646 x 23,33379,99214.04. 01:50
rcs1x86_​646 x 23,46783,37614.04. 16:35
r0s8sx86_​646 x 23,47083,38814.04. 01:29
r0s6x86_​648 x 23,600115,20015.04. 01:21
r0s4sx86_​648 x 23,600115,20015.04. 01:16
r0s5sx86_​648 x 23,600115,20015.04. 01:18
r0s4x86_​648 x 23,600115,20015.04. 01:16
r0s7x86_​648 x 23,600115,20014.04. 01:24
r0s8x86_​648 x 23,600115,20014.04. 01:27
r0s3x86_​648 x 23,600115,20015.04. 01:13
r0s5x86_​648 x 23,500115,20015.04. 01:17
rfs0x86_​6416 x 22,000128,00014.04. 17:07
r6s0x86_​642 x 10 x 21,700136,18014.04. 15:35
r0s6sx86_​6410 x 23,700147,98015.04. 01:21
rcs8x86_​6416 x 23,700217,15214.04. 16:49
 

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