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2024-02-27 - 02:47

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (by cores) - (x86 CPU strings)

BoxArchCoresMHz ↑Bogo​MIPSEffective
rbs5i6864 x 2049,53926.02. 15:24
r9s1sarm​v7l1 x 101,25014.04. 18:03
r3s2sriscv644 x 1028427.02. 01:55
res6saarch​644 x 101,60026.02. 16:10
r3s5i5861 x 113326527.02. 01:57
r2s1arm​v5tejl1 x 120019927.02. 01:45
r8s1i5861 x 130060122.02. 14:52
r2s5ppc1 x 13966621.02. 13:54
ras7ppc1 x 13966526.02. 15:16
r1s4sarm​v7l2 x 14004827.02. 01:40
r4s8arm​v7l1 x 140039827.02. 02:21
r2s8ppc1 x 14006627.02. 01:51
r4s8sarm​v7l1 x 140039827.02. 02:21
r8s6arm​v7l1 x 150049826.02. 14:58
r4s5arm​v7l1 x 1500027.02. 02:16
r4s3i5861 x 150099627.02. 02:09
ras4arm​v7l1 x 150039826.02. 15:13
r5s7sarm​v7l1 x 15284827.02. 02:36
r5s7arm​v7l1 x 15286427.02. 02:35
r3s7i6861 x 15331,06627.02. 02:01
r5s6ppc1 x 153313327.02. 02:34
r7s4arm​v7l1 x 153634826.02. 14:46
r5s5sarm​v7l1 x 160060027.02. 02:31
r2s3sarm​v7l0 x 1 x 16001,20013.02. 01:50
r5s5arm​v7l1 x 160059727.02. 02:29
ras4sarm​v7l1 x 160059707.02. 02:45
r2s3arm​v7l0 x 1 x 162462427.02. 01:46
rbs8arm​v7l2 x 16662,65026.02. 15:29
r7s3arm​v6l1 x 1700526.02. 14:43
r2s2arm​v7l1 x 172049927.02. 01:46
r9s8sarm​v7l1 x 180079626.02. 15:09
r4s2sarm​v7l1 x 180053027.02. 02:07
r4s2arm​v7l1 x 180079627.02. 02:06
r9s8sarm​v7l1 x 180079608.02. 11:18
r2s4mips​641 x 180053124.12. 13:46
rbs7arm​v7l4 x 19961226.02. 15:27
rbs3arm​v7l4 x 19962426.02. 15:20
rbs7sarm​v7l4 x 19962426.02. 15:28
r9s4i6861 x 21,0003,98826.02. 15:05
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
r3s2riscv641 x 11,00028427.02. 01:54
r4s6sarm​v7l0 x 1 x 11,0006627.02. 02:18
ras6sarm​v7l1 x 11,0001,98726.02. 15:16
ras6arm​v7l1 x 11,0001,98726.02. 15:15
r7s8arm​v7l1 x 11,00099526.02. 14:50
ras5arm​v7l2 x 11,0002426.02. 15:14
res3saarch​640 x 1 x 11,0001,60026.02. 16:03
r7s6arm​v7l1 x 11,00039828.02. 14:10
ras5sarm​v7l2 x 11,0002426.02. 15:14
res7arm​v7l0 x 1 x 11,0001226.02. 16:11
r7s8sarm​v7l1 x 11,00079626.02. 14:51
r9s7arm​v7l2 x 11,000026.02. 15:08
ras2x86_​642 x 11,0674,26626.02. 15:11
rcs4x86_​642 x 11,1004,37626.02. 15:39
r6s4x86_​642 x 11,1004,37627.02. 02:41
rcs4sx86_​644 x 11,1008,75226.02. 15:40
res6x86_​644 x 11,1008,75226.02. 16:08
r4s4ppc4 x 11,20049827.02. 02:12
r1s5aarch​644 x 11,20079627.02. 01:40
r3s5sppc2 x 11,20040027.02. 01:58
r1s4arm​v7l2 x 11,2004827.02. 01:39
rbs4x86_​644 x 11,2009,60026.02. 15:22
ras3sarm​v7l1 x 11,30084026.02. 15:13
r7s5i6861 x 11,3002,59326.02. 14:47
r8s8x86_​642 x 11,3005,14426.02. 15:00
rbs6sx86_​642 x 11,3335,33226.02. 15:26
r9s4sx86_​642 x 11,3335,34726.02. 15:06
r2s6saarch​644 x 11,3506427.02. 01:49
rcs3i6862 x 11,4005,58626.02. 15:35
rbs3sarm​v7l4 x 11,40035626.02. 15:21
r3s4x86_​641 x 21,4005,60010.01. 01:28
r7s3sarm​v7l4 x 11,40035626.02. 14:44
ras1i6861 x 11,4002,79926.02. 15:11
r4s3si6861 x 11,4662,93227.02. 02:11
r2s7saarch​644 x 11,50043224.02. 13:49
rfs1aarch​644 x 11,50043226.02. 04:18
rfs2aarch​644 x 11,50043226.02. 04:19
r7s2sarm​v7l4 x 11,50072013.07. 02:16
rcs7sx86_​644 x 11,50011,98026.02. 15:46
r2s6i6861 x 11,5002,99927.02. 01:48
r6s5i6861 x 11,5002,24427.02. 02:42
r7s4sarm​v7l4 x 11,5001,08026.02. 14:47
r4s1sarm​v7l4 x 11,50086427.02. 02:04
r4s1arm​v7l4 x 11,50079227.02. 02:03
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r8s4sx86_​644 x 21,60028,80026.02. 14:56
r7s7x86_​644 x 11,60012,76726.02. 14:48
res1sx86_​644 x 11,60014,40026.02. 16:00
rds7x86_​644 x 11,60012,74826.02. 15:58
rds5x86_​644 x 11,60012,74826.02. 15:56
ras8x86_​644 x 11,60014,40026.02. 15:17
r9s3x86_​644 x 11,60012,74826.02. 15:03
r9s2x86_​644 x 11,60012,74826.02. 15:02
rds6x86_​644 x 11,60012,74826.02. 15:57
ras8sx86_​644 x 11,60012,74826.02. 15:17
rbs4sx86_​644 x 11,60012,74826.02. 15:23
res2x86_​644 x 11,60014,40026.02. 16:01
r6s6i6861 x 11,6003,19127.02. 02:45
res1x86_​644 x 11,60014,40026.02. 04:04
rds8x86_​644 x 11,60012,74826.02. 15:58
r4s5saarch​644 x 11,60020027.02. 02:17
r5s3sx86_​644 x 11,60012,74827.02. 02:25
r7s1x86_​644 x 11,60012,84027.02. 02:47
r8s4x86_​644 x 21,60028,80026.02. 14:55
rbs5saarch​644 x 11,6006426.02. 15:24
r1s8i6861 x 21,6006,39827.02. 01:43
r3s6x86_​641 x 11,6603,33327.02. 01:59
r1s6sx86_​642 x 21,66713,33227.02. 01:41
r6s2x86_​642 x 11,6679,57827.02. 02:40
r6s0x86_​642 x 10 x 21,700136,14027.02. 02:38
res0x86_​644 x 11,80015,99626.02. 15:59
r1s7arm​v6l1 x 11,80053027.02. 01:42
rcs7x86_​642 x 21,80014,39626.02. 15:44
rds0x86_​644 x 21,80031,99226.02. 15:52
r4s7i6864 x 11,83314,66427.02. 02:19
r4s7sx86_​642 x 11,8337,33227.02. 02:20
r1s8sx86_​644 x 11,90015,19627.02. 01:44
res8sx86_​644 x 11,90015,05226.02. 16:13
res8x86_​644 x 11,90015,05226.02. 16:12
res4sx86_​644 x 11,90015,05226.02. 16:05
res4x86_​644 x 11,90015,05226.02. 16:04
rds3x86_​644 x 11,91015,32426.02. 15:54
rds4x86_​644 x 11,91015,32426.02. 15:55
rds2x86_​644 x 11,91015,32426.02. 15:53
rds1x86_​644 x 11,91015,32426.02. 15:52
rbs6x86_​644 x 11,91515,32426.02. 15:25
rfs0x86_​6416 x 22,000127,96826.02. 16:14
res3x86_​644 x 12,00015,97226.02. 16:02
r9s1x86_​642 x 12,0003,99226.02. 15:01
r6s1x86_​642 x 12,0007,97827.02. 02:39
ras3aarch​648 x 12,0004,00026.02. 15:12
r5s3x86_​644 x 22,00031,87227.02. 02:24
r8s2x86_​642 x 22,10016,76026.02. 14:52
r8s2sx86_​642 x 22,10016,76026.02. 14:53
r1s6x86_​642 x 22,13017,06427.02. 01:41
r5s0x86_​642 x 22,20017,58227.02. 02:22
res5sx86_​642 x 22,20019,20026.02. 16:08
res5x86_​642 x 22,20019,20026.02. 16:07
r6s3x86_​644 x 22,20035,12027.02. 02:40
r6s8x86_​642 x 22,30018,35627.02. 02:46
r4s0x86_​642 x 22,30018,39627.02. 02:02
r0s1x86_​644 x 22,30055,99227.02. 01:11
r1s2sx86_​644 x 12,30028,00027.02. 01:37
r1s2x86_​644 x 12,30028,00027.02. 01:36
r7s0x86_​642 x 22,30018,40027.02. 02:46
ras0x86_​642 x 22,30018,41626.02. 15:10
r9s0x86_​642 x 22,30018,40026.02. 15:01
r8s0x86_​642 x 22,30018,40026.02. 14:52
r6s7i6862 x 12,3009,17611.01. 02:44
r7s7sx86_​642 x 22,30018,39626.02. 14:49
r3s1i6864 x 12,40019,12727.02. 01:53
rbs8sx86_​644 x 22,40038,70426.02. 15:30
rcs0x86_​648 x 22,40076,60026.02. 15:32
r2s7aarch​644 x 12,40043227.02. 01:49
rbs0i6862 x 22,50017,60026.02. 15:18
r0s0x86_​644 x 22,50039,99227.02. 01:10
r5s4x86_​642 x 22,53020,26427.02. 02:26
r5s4sx86_​642 x 22,53020,26427.02. 02:27
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s1x86_​642 x 22,60021,69627.02. 01:36
r8s3x86_​644 x 12,66721,28026.02. 14:54
r3s6sx86_​642 x 22,66721,33227.02. 02:00
r9s5x86_​642 x 12,70010,77413.07. 03:15
r5s2x86_​644 x 12,70021,69927.02. 02:23
r8s7x86_​642 x 12,70010,77626.02. 14:58
rcs5x86_​642 x 12,80011,19826.02. 15:41
rcs5sx86_​642 x 12,80011,19826.02. 15:42
rcs2x86_​642 x 12,80011,23226.02. 15:34
r1s3x86_​644 x 12,80022,42427.02. 01:38
r9s6x86_​642 x 23,00023,94426.02. 15:07
r9s3sx86_​644 x 13,00024,00026.02. 15:04
r2s0x86_​644 x 13,10024,79627.02. 01:44
r1s0x86_​644 x 13,10024,79627.02. 01:35
rbs1x86_​644 x 13,10028,80026.02. 15:19
r3s8i6866 x 13,20038,52627.02. 02:02
rbs2x86_​644 x 23,20051,20026.02. 15:20
rcs3sx86_​644 x 23,30052,69626.02. 15:36
r8s7sx86_​642 x 13,30013,19826.02. 14:59
r0s1sx86_​644 x 23,30052,67226.02. 13:11
rcs8sx86_​644 x 23,30052,79226.02. 15:51
r3s3x86_​646 x 23,33379,99227.02. 01:55
r5s1x86_​646 x 13,33340,09227.02. 02:22
r4s6x86_​644 x 23,40054,25627.02. 02:17
r8s5i6864 x 23,40054,39226.02. 14:57
rcs1x86_​646 x 23,46783,37626.02. 15:33
r0s8sx86_​646 x 23,47083,38827.02. 01:34
rcs6x86_​644 x 23,50063,99226.02. 15:43
rbs2sx86_​641 x 13,500007.09. 15:06
r9s5sx86_​642 x 13,50013,99826.02. 15:07
r0s2x86_​644 x 23,50055,86427.02. 01:12
r0s5x86_​648 x 23,500115,20027.02. 01:21
r3s0i6864 x 23,50055,99227.02. 01:52
r0s3sx86_​644 x 23,60067,20027.02. 01:17
r0s6x86_​648 x 23,600115,20027.02. 01:25
r0s4sx86_​648 x 23,600115,20027.02. 01:19
r0s5sx86_​648 x 23,600115,20027.02. 01:22
r0s4x86_​648 x 23,600115,20027.02. 01:18
r0s7x86_​648 x 23,600115,20027.02. 01:27
r0s8x86_​648 x 23,600115,20027.02. 01:31
r0s3x86_​648 x 23,600115,20027.02. 01:14
r0s6sx86_​6410 x 23,700147,98027.02. 01:26
r0s2sx86_​6410 x 13,70073,99027.02. 01:13
r0s7sx86_​642 x 23,70029,52827.02. 01:30
rcs8x86_​6416 x 23,700217,15226.02. 15:50
r5s2sx86_​644 x 24,00063,86312.04. 01:34
 

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