You are here: Home / Projects / OSADL QA Farm Real-time / CPUs under test / 
2023-09-24 - 00:23

Dates and Events:

OSADL Articles:

2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available


2016-11-12 12:00

Raspberry Pi and real-time Linux

Let's have a look at the OSADL QA Farm data



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Number of cores/hyperthreads and bogoMIPS (by cores) - (x86 CPU strings)

BoxArchCoresMHz ↑Bogo​MIPSEffective
rbs5i6864 x 2049,16823.09. 15:34
r9s1sarm​v7l1 x 101,25014.04. 18:03
res6saarch​644 x 101,60023.09. 16:16
r3s5i5861 x 113326523.09. 13:52
r2s1arm​v5tejl1 x 120019923.09. 13:44
r8s1i5861 x 130060123.09. 15:05
r2s5ppc1 x 13966623.09. 13:46
ras7ppc1 x 13966523.09. 15:27
r1s4sarm​v7l2 x 14004823.09. 13:40
r4s8arm​v7l1 x 140039823.09. 14:10
r2s8ppc1 x 14006623.09. 13:48
r4s8sarm​v7l1 x 140039823.09. 14:11
r8s6arm​v7l1 x 150049823.09. 15:11
r4s5arm​v7l1 x 1500023.09. 14:07
r4s3i5861 x 150099623.09. 14:02
ras4arm​v7l1 x 150039823.09. 15:25
r5s7sarm​v7l1 x 15284823.09. 14:24
r5s7arm​v7l1 x 15286423.09. 14:22
r3s7i6861 x 15331,06623.09. 13:55
r5s6ppc1 x 153313323.09. 14:22
r7s4arm​v7l1 x 153635123.09. 14:59
r5s5sarm​v7l1 x 160060023.09. 14:18
r5s5arm​v7l1 x 160059723.09. 14:17
ras4sarm​v7l1 x 160059707.02. 02:45
r2s3arm​v7l0 x 1 x 162462423.09. 13:45
rbs8arm​v7l2 x 16662,65023.09. 15:38
r7s3arm​v6l1 x 1700523.09. 14:55
r2s2arm​v7l1 x 172049923.09. 13:45
r9s8sarm​v7l1 x 180079623.09. 15:21
r4s2sarm​v7l1 x 180053023.09. 14:00
r4s2arm​v7l1 x 180079623.09. 13:59
r2s4mips​641 x 180053122.09. 01:44
rbs7arm​v7l4 x 19961223.09. 15:37
rbs3arm​v7l4 x 19962423.09. 03:29
rbs7sarm​v7l4 x 19962423.09. 15:38
r9s4i6861 x 21,0003,98823.09. 15:17
res7sarm​v7l0 x 1 x 11,0001223.09. 16:18
r3s2riscv641 x 11,00028423.09. 13:50
r4s6sarm​v7l0 x 1 x 11,0006623.09. 14:09
ras6sarm​v7l1 x 11,0001,98723.09. 15:27
ras6arm​v7l1 x 11,0001,98723.09. 15:26
r7s8arm​v7l1 x 11,00099523.09. 15:02
ras5arm​v7l2 x 11,0002423.09. 15:25
res3saarch​640 x 1 x 11,0001,60023.09. 16:13
r7s6arm​v7l1 x 11,00039828.02. 14:10
ras5sarm​v7l2 x 11,0002423.09. 15:26
res7arm​v7l0 x 1 x 11,0001223.09. 16:17
r7s8sarm​v7l1 x 11,00079623.09. 15:03
r9s7arm​v7l2 x 11,000023.09. 15:20
ras2x86_​642 x 11,0674,26623.09. 15:23
rcs4x86_​642 x 11,1004,37623.09. 15:48
r6s4x86_​642 x 11,1004,37623.09. 14:28
rcs4sx86_​644 x 11,1008,75223.09. 15:50
res6x86_​644 x 11,1008,75223.09. 16:15
r4s4ppc4 x 11,20049823.09. 14:04
r1s5aarch​644 x 11,20079623.09. 13:40
r3s5sppc2 x 11,20040013.09. 13:56
r1s4arm​v7l2 x 11,2004823.09. 13:39
rbs4x86_​644 x 11,2009,60023.09. 15:33
ras3sarm​v7l1 x 11,30084023.09. 15:24
r7s5i6861 x 11,3002,59323.09. 15:00
r8s8x86_​642 x 11,3005,14423.09. 15:13
rbs6sx86_​642 x 11,3335,33223.09. 15:36
r9s4sx86_​642 x 11,3335,34723.09. 15:18
r2s6saarch​644 x 11,3506423.09. 13:47
rcs3i6862 x 11,4005,58623.09. 15:44
rbs3sarm​v7l4 x 11,40035623.09. 15:31
r3s4x86_​641 x 21,4005,60010.01. 01:28
r7s3sarm​v7l4 x 11,40035623.09. 14:57
ras1i6861 x 11,4002,79923.09. 15:22
r4s3si6861 x 11,4662,93223.09. 14:03
r7s2sarm​v7l4 x 11,50072013.07. 02:16
rcs7sx86_​644 x 11,50011,98023.09. 15:56
r2s6i6861 x 11,5002,99923.09. 13:47
r6s5i6861 x 11,5002,24423.09. 14:49
r7s4sarm​v7l4 x 11,50057623.09. 15:00
r4s1sarm​v7l4 x 11,50079223.09. 13:58
r4s1arm​v7l4 x 11,50079223.09. 13:58
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r8s4sx86_​644 x 21,60028,80023.09. 15:09
r7s7x86_​644 x 11,60012,76723.09. 15:01
res1sx86_​644 x 11,60014,40023.09. 16:11
rds7x86_​644 x 11,60012,74823.09. 16:07
rds5x86_​644 x 11,60012,74823.09. 16:06
ras8x86_​644 x 11,60014,40023.09. 15:28
r9s3x86_​644 x 11,60012,74823.09. 15:16
r9s2x86_​644 x 11,60012,74823.09. 15:15
rds6x86_​644 x 11,60012,74823.09. 16:06
ras8sx86_​644 x 11,60012,74823.09. 15:28
rbs4sx86_​644 x 11,60012,74823.09. 15:33
res2x86_​644 x 11,60014,40023.09. 16:11
r6s6i6861 x 11,6003,19123.09. 14:52
res1x86_​644 x 11,60014,40023.09. 16:10
rds8x86_​644 x 11,60012,74823.09. 16:07
r4s5saarch​644 x 11,60020023.09. 14:08
r5s3sx86_​644 x 11,60012,74823.09. 14:13
r7s1x86_​644 x 11,60012,84023.09. 14:54
r8s4x86_​644 x 21,60028,80023.09. 15:07
rbs5saarch​644 x 11,6006423.09. 15:34
r1s8i6861 x 21,6006,39823.09. 13:42
r3s6x86_​641 x 21,6606,66623.09. 13:54
r1s6sx86_​642 x 21,66713,33223.09. 13:41
r6s2x86_​642 x 11,6679,57623.09. 14:26
r6s0x86_​642 x 10 x 21,700136,14023.09. 14:25
res0x86_​644 x 21,80031,99223.09. 16:08
r1s7arm​v6l1 x 11,80053023.09. 13:42
rcs7x86_​642 x 21,80014,39623.09. 15:55
rds0x86_​644 x 21,80031,99223.09. 16:02
r4s7i6864 x 11,83314,66423.09. 14:09
r4s7sx86_​642 x 11,8337,33223.09. 14:10
r1s8sx86_​644 x 11,90015,19623.09. 13:43
res8sx86_​644 x 11,90015,05223.09. 16:20
res8x86_​644 x 11,90015,05223.09. 16:19
res4x86_​644 x 11,90015,05225.10. 03:17
rds3x86_​644 x 11,91015,32423.09. 16:04
rds4x86_​644 x 11,91015,32423.09. 16:05
rds2x86_​644 x 11,91015,32423.09. 16:03
rds1x86_​644 x 11,91015,32423.09. 16:03
rbs6x86_​644 x 11,91515,32423.09. 15:35
res3x86_​644 x 12,00015,97223.09. 16:13
r9s1x86_​642 x 12,0003,99223.09. 15:14
r6s1x86_​642 x 12,0007,97823.09. 14:26
ras3aarch​648 x 12,0004,00023.09. 15:23
r5s3x86_​644 x 22,00031,87223.09. 14:13
r8s2x86_​642 x 22,10016,76023.09. 03:05
r8s2sx86_​642 x 22,10016,76023.09. 03:06
r1s6x86_​642 x 22,13017,06423.09. 13:41
r5s0x86_​642 x 22,20017,58223.09. 14:11
res5sx86_​642 x 22,20019,20023.09. 16:15
res5x86_​642 x 22,20019,20023.09. 16:14
r6s3x86_​644 x 22,20035,12023.09. 14:27
r6s8x86_​642 x 22,30018,35623.09. 14:53
r4s0x86_​642 x 22,30018,39623.09. 13:57
r0s1x86_​644 x 22,30055,99223.09. 13:10
r1s2sx86_​644 x 12,30028,00023.09. 13:37
r1s2x86_​644 x 12,30028,00023.09. 13:37
r7s0x86_​642 x 22,30018,40023.09. 14:54
ras0x86_​642 x 22,30018,41723.09. 15:22
r9s0x86_​642 x 22,30018,40023.09. 15:14
r8s0x86_​642 x 22,30018,40023.09. 15:04
r6s7i6862 x 12,3009,17623.09. 14:52
r7s7sx86_​642 x 22,30018,39623.09. 15:01
r3s1i6864 x 12,40019,12723.09. 13:49
rbs8sx86_​644 x 22,40038,70423.09. 15:39
rcs0x86_​648 x 22,40077,36823.09. 15:42
rbs0i6862 x 22,50017,60023.09. 15:29
r0s0x86_​644 x 22,50039,99223.09. 13:10
r5s4x86_​642 x 22,53020,26423.09. 14:14
r5s4sx86_​642 x 22,53020,26423.09. 14:15
r1s1x86_​642 x 22,60021,69623.09. 13:36
r8s3x86_​644 x 12,66721,27623.09. 15:06
r3s6sx86_​642 x 22,66721,33223.09. 13:55
r9s5x86_​642 x 12,70010,77413.07. 03:15
r5s2x86_​644 x 12,70021,69923.09. 14:12
r8s7x86_​642 x 12,70010,77623.09. 15:12
rcs5x86_​642 x 12,80011,19823.09. 15:51
rcs5sx86_​642 x 12,80011,19823.09. 15:53
rcs2x86_​642 x 12,80011,23223.09. 15:43
r1s3x86_​644 x 12,80022,42423.09. 13:38
r9s6x86_​642 x 23,00023,94423.09. 15:20
r9s3sx86_​644 x 13,00024,00023.09. 15:17
r2s0x86_​644 x 13,10024,79623.09. 13:44
r1s0x86_​644 x 13,10024,79623.09. 13:36
rbs1x86_​644 x 13,10028,80023.09. 15:30
r3s8i6866 x 13,20038,52023.09. 13:56
rbs2x86_​644 x 23,20051,20023.09. 15:31
rcs3sx86_​644 x 23,30052,69623.09. 15:45
r8s7sx86_​642 x 13,30013,19823.09. 15:12
r0s1sx86_​644 x 23,30052,80023.09. 13:11
rcs8sx86_​644 x 23,30052,79223.09. 16:01
r3s3x86_​646 x 23,33379,99223.09. 13:51
r5s1x86_​646 x 13,33340,09223.09. 14:12
r4s6x86_​644 x 23,40054,25623.09. 14:08
r8s5i6864 x 23,40054,39223.09. 15:11
rcs1x86_​646 x 23,46783,37623.09. 15:42
r0s8sx86_​646 x 23,47083,38823.09. 13:35
rcs6x86_​644 x 23,50063,99223.09. 15:54
rbs2sx86_​641 x 13,500007.09. 15:06
r1s3sx86_​644 x 23,50056,00026.05. 01:16
r9s5sx86_​642 x 13,50013,99823.09. 15:19
r0s2x86_​644 x 23,50055,86423.09. 13:11
r0s5x86_​648 x 23,500115,20023.09. 13:23
r3s0i6864 x 23,50055,99223.09. 13:48
r0s3sx86_​644 x 23,60067,20023.09. 13:16
r0s6x86_​648 x 23,600115,20023.09. 13:26
r0s4sx86_​648 x 23,600115,20023.09. 13:21
r0s5sx86_​648 x 23,600115,20023.09. 13:25
r0s4x86_​648 x 23,600115,20023.09. 13:19
r0s7x86_​648 x 23,600115,20023.09. 13:28
r0s8x86_​648 x 23,600115,20023.09. 13:32
r0s3x86_​648 x 23,600115,20023.09. 13:14
r0s6sx86_​6410 x 23,700147,98015.09. 13:29
r0s2sx86_​6410 x 13,70073,99023.09. 13:14
r0s7sx86_​642 x 23,70029,52823.09. 13:30
rcs8x86_​6416 x 23,700217,15223.09. 16:01
r5s2sx86_​644 x 24,00063,86312.04. 01:34
 

Valid XHTML 1.0 Transitional