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2026-06-16 - 05:28

Dates and Events:

OSADL Articles:

2024-10-02 12:00

Linux is now an RTOS!

PREEMPT_RT is mainline - What's next?


2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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Number of cores/hyperthreads and bogoMIPS (by arch) - (x86 CPU strings)

BoxArch ↑CoresMHzBogo​MIPSEffective
ras3aarch​648 x 12,0004,00006.05. 03:01
rfs5saarch​644 x 11,2006416.06. 03:32
ras6aarch​648 x 12,0003,20016.06. 02:46
r7s2aarch​642 x 11,7009616.06. 02:18
ras4aarch​648 x 12,40038416.06. 02:45
res3saarch​640 x 1 x 11,0001,60016.06. 03:20
r4s5saarch​644 x 11,60020016.06. 01:52
r2s6saarch​644 x 11,3506416.06. 01:31
rfs5aarch​644 x 11,2006416.06. 03:31
r2s7aarch​644 x 12,40043230.05. 13:34
rfs4aarch​641 x 11,4001,60016.06. 03:29
res6saarch​644 x 101,60016.06. 03:23
rbs5saarch​644 x 11,6006416.06. 02:52
r8s2aarch​644 x 11,4001,60016.06. 02:29
r1s5aarch​644 x 11,20079616.06. 01:24
rfs1aarch​644 x 11,50043216.06. 03:27
rfs1saarch​644 x 11,50043216.06. 03:27
ras4saarch​648 x 12,40038429.09. 03:02
r2s7saarch​644 x 11,50043216.06. 01:32
r3s4aarch​646 x 11,3009616.06. 01:37
r8s2saarch​644 x 11,4001,60016.06. 02:29
r2s1arm​v5tejl1 x 120019916.06. 01:28
r1s7arm​v6l1 x 120053016.06. 01:26
r7s3arm​v6l1 x 1700516.06. 02:19
r2s3arm​v7l0 x 1 x 162462416.06. 01:29
ras6sarm​v7l1 x 11,0001,98716.06. 02:47
r9s8sarm​v7l1 x 180079616.06. 02:42
r2s2arm​v7l1 x 172049916.06. 01:28
r1s4arm​v7l2 x 11,2004816.06. 01:23
r4s2sarm​v7l1 x 180053016.06. 01:45
r9s2arm​v7l0 x 1 x 155040016.06. 02:36
r7s8arm​v7l1 x 11,00099516.06. 02:25
ras5arm​v7l2 x 11,0002416.06. 02:45
r7s4arm​v7l1 x 153634816.06. 02:22
r4s2arm​v7l1 x 180079614.06. 13:47
rbs3arm​v7l4 x 19962416.06. 02:50
r7s3sarm​v7l4 x 11,40015216.06. 02:21
r7s4sarm​v7l4 x 11,5001,08016.06. 02:23
r4s8sarm​v7l1 x 140039816.06. 01:57
rfs4sarm​v7l1 x 180080016.06. 03:30
r4s1sarm​v7l4 x 11,5001,00816.06. 01:44
ras5sarm​v7l2 x 11,0002416.06. 02:46
r4s1arm​v7l4 x 11,50072016.06. 01:43
res7arm​v7l0 x 1 x 11,0001216.06. 03:24
rfs8arm​v7l1 x 11,00012016.06. 03:35
rbs7sarm​v7l4 x 19962416.06. 02:56
r7s8sarm​v7l1 x 11,00099616.06. 02:27
r9s7arm​v7l2 x 11,000016.06. 02:41
rfs6sarm​v7l1 x 16671,33216.06. 03:34
ras3sarm​v7l1 x 11,30084016.06. 02:44
res7sarm​v7l0 x 1 x 11,0001216.06. 03:25
r8s6arm​v7l1 x 150049816.06. 02:32
r1s4sarm​v7l2 x 14004816.06. 01:23
r5s5sarm​v7l1 x 160060016.06. 02:04
r2s3sarm​v7l0 x 2 x 16001,20016.06. 01:30
rbs3sarm​v7l4 x 11,40035616.06. 02:50
r5s7arm​v7l1 x 15286416.06. 02:08
rfs6arm​v7l1 x 16671,33216.06. 03:33
r9s1sarm​v7l1 x 101,25014.04. 18:03
rbs7arm​v7l4 x 19961216.06. 02:54
r5s5arm​v7l1 x 160059716.06. 02:02
rbs8arm​v7l2 x 16662,65016.06. 02:56
r4s5arm​v7l1 x 1500016.06. 01:52
r4s6sarm​v7l0 x 1 x 11,0006616.06. 01:54
r4s8arm​v7l1 x 140039816.06. 01:56
r5s7sarm​v7l1 x 15284816.06. 02:09
r2s5sarm​v7l4 x 11,20015212.12. 01:35
r4s3i5861 x 150099616.06. 01:47
r8s1i5861 x 135070116.06. 02:28
r3s5i5861 x 113326516.06. 01:38
r9s4i6861 x 21,0003,99016.06. 02:39
rbs5i6864 x 2052,36516.06. 02:52
r6s6i6861 x 11,6003,19216.06. 02:15
r2s6i6861 x 11,5002,99916.06. 01:31
r6s5i6861 x 11,5002,99216.06. 02:14
rbs0i6862 x 22,50017,60016.06. 02:49
ras1i6861 x 11,4002,79916.06. 02:43
r4s3si6861 x 11,4662,93228.07. 02:17
r7s5i6861 x 11,3002,59316.06. 02:23
r3s0i6864 x 23,50055,99216.06. 01:33
r1s8i6861 x 21,6006,40016.06. 01:26
r6s7i6862 x 12,3009,17616.06. 02:16
r8s5i6864 x 23,40054,40016.06. 02:31
rcs3i6862 x 11,4005,58616.06. 03:00
r3s1i6864 x 12,40019,12816.06. 01:34
r3s7i6861 x 15331,06616.06. 01:42
r4s7i6864 x 11,83314,66416.06. 01:55
r2s4mips​641 x 180053129.09. 13:34
r5s6ppc1 x 153313316.06. 02:07
r2s8ppc1 x 14006616.06. 01:33
ras7ppc1 x 13966516.06. 02:47
r2s5ppc1 x 13966615.06. 13:35
r4s4ppc4 x 11,20049816.06. 01:48
r3s5sppc2 x 11,20040016.06. 01:40
r3s2sriscv644 x 1028416.06. 01:36
r3s2riscv641 x 11,00028416.06. 01:35
r7s2sriscv644 x 1028406.06. 02:20
rds3x86_​644 x 11,60012,74816.06. 03:13
res5x86_​642 x 22,20019,20016.06. 03:21
r0s5sx86_​648 x 23,600115,20016.06. 01:16
ras0x86_​642 x 22,30018,41816.06. 02:43
r9s3x86_​644 x 11,60012,74816.06. 02:38
r0s4x86_​648 x 23,600115,20016.06. 01:14
r6s0x86_​642 x 10 x 21,700136,14016.06. 02:12
rbs8sx86_​644 x 22,40038,70416.06. 02:57
r9s5sx86_​642 x 13,30013,19816.06. 02:41
r1s0x86_​644 x 13,10024,80016.06. 01:20
rcs7sx86_​644 x 11,50011,98016.06. 03:07
r1s8sx86_​644 x 11,90015,19616.06. 01:27
r9s0x86_​644 x 23,60057,60016.06. 02:35
rds6x86_​644 x 11,60012,74816.06. 03:15
res8sx86_​644 x 11,90015,05216.06. 03:26
rfs3x86_​644 x 11,60012,74816.06. 03:28
rfs0x86_​6416 x 22,000128,00016.06. 03:26
rfs2sx86_​642 x 13,00011,99816.06. 03:28
r5s3x86_​644 x 22,00031,87216.06. 01:59
ras8sx86_​644 x 11,60012,74816.06. 02:48
r0s7x86_​6410 x 13,70073,99016.06. 01:18
r0s2sx86_​6410 x 13,70073,99016.06. 01:11
r5s2x86_​644 x 12,70021,69916.06. 01:58
r0s8x86_​648 x 23,600115,20014.03. 13:20
rbs4sx86_​644 x 11,60012,74816.06. 02:51
rcs6x86_​644 x 23,50063,99216.06. 03:05
r9s4sx86_​642 x 11,3335,34716.06. 02:40
r1s3x86_​644 x 12,80022,42416.06. 01:22
res2x86_​644 x 11,60014,40016.06. 03:19
r8s7sx86_​642 x 13,00011,98016.06. 02:33
r5s1x86_​646 x 13,33340,08616.06. 01:57
ras2sx86_​644 x 11,90015,05214.06. 14:47
r0s0sx86_​644 x 23,40054,39216.06. 01:10
rcs1x86_​646 x 23,46783,37616.06. 02:59
rfs3sx86_​644 x 11,60012,74816.06. 03:29
r0s1sx86_​644 x 23,30052,80016.06. 01:11
r0s0x86_​644 x 22,50039,99216.06. 01:10
res8x86_​644 x 11,90015,05216.06. 03:25
res1x86_​644 x 11,60014,40016.06. 03:17
r6s8x86_​642 x 22,30018,35616.06. 02:16
r0s2x86_​644 x 23,50055,87214.06. 13:11
rds8x86_​644 x 11,60012,74816.06. 03:16
rfs7sx86_​644 x 17006,44816.06. 03:35
rbs4x86_​644 x 11,2009,60016.06. 02:51
r4s6x86_​644 x 23,40054,25616.06. 01:52
r3s6sx86_​642 x 22,66721,33216.06. 01:41
r0s3x86_​648 x 23,600115,20016.06. 01:12
res4sx86_​644 x 11,90015,05216.06. 03:21
r4s7sx86_​642 x 11,8337,33216.06. 01:55
r0s7sx86_​642 x 23,70029,53223.05. 13:21
res6x86_​644 x 11,1008,75216.06. 03:22
r0s5x86_​648 x 23,500115,20016.06. 01:16
r8s0x86_​642 x 22,30018,40016.06. 02:27
r5s3sx86_​644 x 11,60012,74816.06. 02:00
r6s3x86_​644 x 22,20035,12016.06. 02:13
r7s1x86_​644 x 11,60012,83916.06. 02:17
rcs8sx86_​644 x 23,30052,80016.06. 03:11
rds4x86_​644 x 11,60012,74816.06. 03:14
r6s2x86_​642 x 11,6679,57816.06. 02:12
rcs8x86_​6416 x 23,700217,18416.06. 03:11
r8s4x86_​644 x 21,60028,80016.06. 02:30
rcs0x86_​648 x 22,40076,40016.06. 02:58
rbs6sx86_​642 x 11,3335,33229.08. 03:00
r9s3sx86_​644 x 13,00024,00016.06. 02:38
r1s1x86_​642 x 22,60021,69616.06. 01:20
res4x86_​644 x 11,90015,05216.06. 03:20
r8s7x86_​644 x 13,20025,49616.06. 02:33
r0s8sx86_​646 x 23,47083,38816.06. 01:19
r5s4sx86_​644 x 11,60012,74816.06. 02:01
r5s8x86_​644 x 12,00015,97216.06. 02:11
r8s8x86_​642 x 11,3005,14416.06. 02:34
r7s7sx86_​642 x 22,30018,39616.06. 02:24
ras2x86_​642 x 11,0674,26616.06. 02:44
rds2x86_​644 x 11,60012,74816.06. 03:13
r4s0x86_​642 x 22,30018,39616.06. 01:43
res3x86_​644 x 12,00015,97216.06. 03:19
rbs6x86_​644 x 11,91515,32416.06. 02:53
rfs7x86_​644 x 22,60041,60016.06. 03:34
r0s1x86_​644 x 22,30056,00016.06. 01:11
r3s3x86_​646 x 23,33379,99216.06. 01:36
r9s2sx86_​644 x 11,60012,74830.08. 17:02
rcs5sx86_​642 x 12,80011,19816.06. 03:05
res0x86_​644 x 23,40054,39216.06. 03:17
r5s0x86_​642 x 22,20017,58416.06. 01:57
r8s4sx86_​644 x 21,60028,80016.06. 02:31
rcs3sx86_​644 x 13,30026,39616.06. 03:02
r9s1x86_​642 x 12,0007,98412.02. 14:30
r3s3sx86_​644 x 13,40011,98016.06. 01:37
r7s7x86_​644 x 11,60012,76716.06. 02:24
r1s6x86_​642 x 22,13017,06416.06. 01:24
res5sx86_​642 x 22,20019,20016.06. 03:22
r9s6x86_​642 x 23,00023,94409.06. 14:37
rcs7x86_​642 x 21,80014,40016.06. 03:06
r1s2sx86_​644 x 12,30028,00016.06. 01:21
rcs5x86_​642 x 12,80011,19816.06. 03:04
r0s6sx86_​6410 x 23,700147,98016.06. 01:18
r3s6x86_​641 x 21,6606,66616.06. 01:41
r1s6sx86_​642 x 21,66713,33216.06. 01:25
rds0x86_​644 x 21,80031,99216.06. 03:12
res1sx86_​644 x 11,60014,40016.06. 03:18
rds7x86_​644 x 11,60012,74816.06. 03:16
r8s6sx86_​644 x 13,30026,41616.06. 02:32
r5s2sx86_​644 x 24,00063,86312.04. 01:34
rfs2x86_​644 x 13,00024,00016.06. 03:27
rcs2x86_​642 x 12,80011,23216.06. 03:00
r5s4x86_​642 x 22,53020,26416.06. 02:00
rcs4x86_​642 x 11,1004,37616.06. 03:02
r8s3x86_​644 x 12,66721,28016.06. 02:30
r2s0x86_​644 x 13,60024,79616.06. 01:27
r1s2x86_​644 x 12,30027,99616.06. 01:21
r0s3sx86_​644 x 23,60067,20016.06. 01:14
r6s1x86_​642 x 12,0007,97812.12. 02:21
r7s0x86_​642 x 22,30018,40016.06. 02:17
rds1x86_​644 x 11,60012,74816.06. 03:12
r0s6x86_​648 x 23,600115,20016.06. 01:17
r0s4sx86_​648 x 23,600115,20016.06. 01:15
r6s4x86_​642 x 11,1004,37616.06. 02:14
rds5x86_​644 x 11,60012,74816.06. 03:15
ras8x86_​644 x 11,60014,40016.06. 02:48
 

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