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2026-03-16 - 00:48

Dates and Events:

OSADL Articles:

2024-10-02 12:00

Linux is now an RTOS!

PREEMPT_RT is mainline - What's next?


2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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Number of cores/hyperthreads and bogoMIPS (by arch) - (x86 CPU strings)

BoxArch ↑CoresMHzBogo​MIPSEffective
ras3aarch​648 x 12,0004,00006.05. 03:01
rfs5saarch​644 x 11,2006415.03. 15:28
ras6aarch​648 x 12,0003,20015.03. 14:42
r7s2aarch​642 x 11,7009615.03. 14:16
ras4aarch​648 x 12,40038415.03. 14:40
res3saarch​640 x 1 x 11,0001,60015.03. 15:14
r4s5saarch​644 x 11,60020015.03. 13:52
r2s6saarch​644 x 11,3506415.03. 13:31
rfs5aarch​644 x 11,2006415.03. 15:27
rfs4aarch​641 x 11,4001,60015.03. 15:25
r2s7aarch​644 x 12,40043215.03. 13:31
res6saarch​644 x 101,60015.03. 15:18
rbs5saarch​644 x 11,6006415.03. 14:48
r1s5aarch​644 x 11,20079615.03. 13:24
rfs1aarch​644 x 11,50043215.03. 15:22
rfs1saarch​644 x 11,50043215.03. 15:23
ras4saarch​648 x 12,40038429.09. 03:02
r2s7saarch​644 x 11,50043215.03. 13:32
r3s4aarch​646 x 11,3009615.03. 13:37
r2s1arm​v5tejl1 x 120019915.03. 13:27
r1s7arm​v6l1 x 120053015.03. 13:25
r7s3arm​v6l1 x 1700515.03. 14:18
r2s3arm​v7l0 x 1 x 162462415.03. 13:28
ras6sarm​v7l1 x 11,0001,98715.03. 14:42
r9s8sarm​v7l1 x 180079615.03. 14:37
r2s2arm​v7l1 x 172049915.03. 13:28
r1s4arm​v7l2 x 11,2004815.03. 13:22
r4s2sarm​v7l1 x 180053015.03. 13:46
r7s8arm​v7l1 x 11,00099515.03. 14:24
ras5arm​v7l2 x 11,0002415.03. 14:41
r7s4arm​v7l1 x 153634815.03. 14:20
r4s2arm​v7l1 x 180079615.03. 13:45
rbs3arm​v7l4 x 19962415.03. 14:45
r7s3sarm​v7l4 x 11,40035615.03. 14:19
r7s4sarm​v7l4 x 11,5001,08015.03. 14:21
r4s8sarm​v7l1 x 140039815.03. 13:56
rfs4sarm​v7l1 x 180080015.03. 15:26
r4s1sarm​v7l4 x 11,50086415.03. 13:44
r7s6arm​v7l1 x 11,00039828.02. 14:10
ras5sarm​v7l2 x 11,0002415.03. 14:41
r4s1arm​v7l4 x 11,50079215.03. 13:43
res7arm​v7l0 x 1 x 11,0001215.03. 15:19
rfs8arm​v7l1 x 11,00012015.03. 15:31
rbs7sarm​v7l4 x 19962415.03. 14:51
r7s8sarm​v7l1 x 11,00079615.03. 14:24
ras3sarm​v7l1 x 11,30084015.03. 14:40
r9s7arm​v7l2 x 11,000015.03. 14:37
rfs6sarm​v7l1 x 16671,33215.03. 15:29
res7sarm​v7l0 x 1 x 11,0001215.03. 15:20
r8s6arm​v7l1 x 150049815.03. 14:29
r1s4sarm​v7l2 x 14004815.03. 13:23
r5s5sarm​v7l1 x 160060015.03. 14:03
r2s3sarm​v7l0 x 2 x 16001,20015.03. 13:29
rbs3sarm​v7l4 x 11,40035615.03. 14:46
r5s7arm​v7l1 x 15286415.03. 14:07
rfs6arm​v7l1 x 16671,33215.03. 15:29
r9s1sarm​v7l1 x 101,25014.04. 18:03
rbs7arm​v7l4 x 19961215.03. 14:49
r5s5arm​v7l1 x 160059715.03. 14:01
rbs8arm​v7l2 x 16662,65015.03. 14:52
r4s5arm​v7l1 x 1500015.03. 13:52
r4s6sarm​v7l0 x 1 x 11,0006615.03. 13:53
r4s8arm​v7l1 x 140039815.03. 13:55
r5s7sarm​v7l1 x 15284815.03. 14:08
r2s5sarm​v7l4 x 11,20015212.12. 01:35
r4s3i5861 x 150099615.03. 13:48
r8s1i5861 x 135070115.03. 14:26
r3s5i5861 x 113326515.03. 13:38
r9s4i6861 x 21,0003,99015.03. 14:34
rbs5i6864 x 2052,36515.03. 14:47
r3s8i6864 x 13,20027,36614.03. 13:46
r6s6i6861 x 11,6003,19215.03. 14:14
r2s6i6861 x 11,5002,99915.03. 13:30
r6s5i6861 x 11,5002,99215.03. 14:13
rbs0i6862 x 22,50017,60015.03. 14:45
ras1i6861 x 11,4002,79915.03. 14:38
r4s3si6861 x 11,4662,93228.07. 02:17
r7s5i6861 x 11,3002,59315.03. 14:22
r3s0i6864 x 23,50055,99215.03. 13:33
r1s8i6861 x 21,6006,40015.03. 13:26
r6s7i6862 x 12,3009,17615.03. 14:14
r8s5i6864 x 23,40054,40015.03. 14:29
rcs3i6862 x 11,4005,58615.03. 14:56
r3s1i6864 x 12,40019,12815.03. 13:34
r3s7i6861 x 15331,06615.03. 13:41
r4s7i6864 x 11,83314,66415.03. 13:54
r2s4mips​641 x 180053129.09. 13:34
r5s6ppc1 x 153313315.03. 14:06
r2s8ppc1 x 14006615.03. 13:33
ras7ppc1 x 13966515.03. 14:43
r2s5ppc1 x 13966625.12. 13:33
r4s4ppc4 x 11,20049815.03. 13:49
r3s5sppc2 x 11,20040015.03. 13:40
r3s2sriscv644 x 1028415.03. 13:36
r3s2riscv641 x 11,00028415.03. 13:35
r7s2sriscv644 x 1028415.03. 14:17
rds3x86_​644 x 11,60012,74815.03. 15:08
r0s5sx86_​648 x 23,600115,20015.03. 13:16
ras0x86_​642 x 22,30018,41815.03. 14:38
r9s3x86_​644 x 11,60012,74815.03. 14:33
r0s4x86_​648 x 23,600115,20015.03. 13:14
r6s0x86_​642 x 10 x 21,700136,14015.03. 14:10
rbs8sx86_​644 x 22,40038,70415.03. 14:52
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r9s2x86_​644 x 11,60012,74802.01. 02:36
r9s5sx86_​642 x 13,30013,19815.03. 14:35
r1s0x86_​644 x 13,10024,80015.03. 13:20
rcs7sx86_​644 x 11,50011,98015.03. 15:02
r1s8sx86_​644 x 11,90015,19615.03. 13:26
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s0x86_​644 x 23,60057,60015.03. 14:32
rds6x86_​644 x 11,60012,74815.03. 15:10
rfs0x86_​6416 x 22,000128,00015.03. 15:22
res8sx86_​644 x 11,90015,05215.03. 15:21
rfs3x86_​644 x 11,60012,74815.03. 15:24
rfs2sx86_​642 x 13,00011,99815.03. 15:23
r5s3x86_​644 x 22,00031,87214.03. 02:01
ras8sx86_​644 x 11,60012,74815.03. 14:44
r0s7x86_​648 x 23,600115,20006.01. 13:20
r0s2sx86_​6410 x 13,70073,99015.03. 13:12
r5s2x86_​644 x 12,70021,69915.03. 13:57
r0s8x86_​648 x 23,600115,20014.03. 13:20
rcs6x86_​644 x 23,50063,99215.03. 15:00
rbs4sx86_​644 x 11,60012,74815.03. 14:47
r9s4sx86_​642 x 11,3335,34715.03. 14:35
r1s3x86_​644 x 12,80022,42415.03. 13:22
res2x86_​644 x 11,60014,40015.03. 15:13
r8s7sx86_​642 x 13,00011,98015.03. 14:31
r5s1x86_​646 x 13,33340,08615.03. 13:57
r0s0sx86_​644 x 23,40054,39215.03. 13:10
ras2sx86_​644 x 11,90015,05215.03. 14:39
rcs1x86_​646 x 23,46783,37615.03. 14:55
rfs3sx86_​644 x 11,60012,74815.03. 15:24
r0s1sx86_​644 x 23,30052,80015.03. 13:11
r0s0x86_​644 x 22,50039,99215.03. 13:10
res8x86_​644 x 11,90015,05215.03. 15:21
res1x86_​644 x 11,60014,40015.03. 15:12
r6s8x86_​642 x 22,30018,35615.03. 14:15
r0s2x86_​644 x 23,50055,86415.03. 13:11
rds8x86_​644 x 11,60012,74815.03. 15:11
rfs7sx86_​644 x 17006,44815.03. 15:30
rbs4x86_​644 x 11,2009,60015.03. 14:46
r4s6x86_​644 x 23,40054,25615.03. 13:53
r3s6sx86_​642 x 22,66721,33215.03. 13:41
thlfwx86_​644 x 12,00015,97214.03. 14:51
r0s3x86_​648 x 23,600115,20015.03. 13:13
res4sx86_​644 x 11,90015,05215.03. 15:16
r4s7sx86_​642 x 11,8337,33215.03. 13:55
r0s7sx86_​642 x 23,70029,53223.05. 13:21
res6x86_​644 x 11,1008,75215.03. 15:17
r0s5x86_​648 x 23,500115,20015.03. 13:16
r8s0x86_​642 x 22,30018,40015.03. 14:25
r5s3sx86_​644 x 11,60012,74815.03. 13:58
r6s3x86_​644 x 22,20035,12015.03. 14:11
r7s1x86_​644 x 11,60012,83915.03. 14:16
thlfw2x86_​644 x 12,00015,97214.03. 14:50
rds4x86_​644 x 11,60012,74815.03. 15:09
rcs8sx86_​644 x 23,30052,80015.03. 15:06
r6s2x86_​642 x 11,6679,57815.03. 14:11
rcs8x86_​6416 x 23,700217,18415.03. 15:06
r8s4x86_​644 x 21,60028,80015.03. 14:27
rbs6sx86_​642 x 11,3335,33229.08. 03:00
rcs0x86_​648 x 22,40076,40015.03. 14:54
r9s3sx86_​644 x 13,00024,00015.03. 14:34
r1s1x86_​642 x 22,60021,69615.03. 13:20
res4x86_​644 x 11,90015,05215.03. 15:15
r8s7x86_​644 x 13,20025,49615.03. 14:30
r5s8x86_​644 x 12,00015,97215.03. 14:10
r0s8sx86_​646 x 23,47083,38815.03. 13:19
r5s4sx86_​644 x 11,60012,74815.03. 14:00
r8s8x86_​642 x 11,3005,14415.03. 14:31
r7s7sx86_​642 x 22,30018,39615.03. 14:23
ras2x86_​642 x 11,0674,26615.03. 14:39
rds2x86_​644 x 11,60012,74815.03. 15:08
r4s0x86_​642 x 22,30018,40015.03. 13:42
res3x86_​644 x 12,00015,97215.03. 15:14
rbs6x86_​644 x 11,91515,32415.03. 14:48
rfs7x86_​644 x 22,60041,60015.03. 15:30
r0s1x86_​644 x 22,30056,00015.03. 13:11
r3s3x86_​646 x 23,33379,99215.03. 13:36
r9s2sx86_​644 x 11,60012,74830.08. 17:02
rcs5sx86_​642 x 12,80011,19815.03. 15:00
res0x86_​644 x 23,40054,39215.03. 15:11
r5s0x86_​642 x 22,20017,58415.03. 13:56
r8s4sx86_​644 x 21,60028,80015.03. 14:28
rcs3sx86_​644 x 13,30026,39615.03. 14:57
r9s1x86_​642 x 12,0007,98412.02. 14:30
r3s3sx86_​644 x 13,40011,98015.03. 13:37
r7s7x86_​644 x 11,60012,76715.03. 14:22
res5sx86_​642 x 22,20019,20015.03. 15:16
r1s6x86_​642 x 22,13017,06415.03. 13:24
r9s6x86_​642 x 23,00023,94415.03. 14:36
rcs7x86_​642 x 21,80014,40015.03. 15:01
r1s2sx86_​644 x 12,30028,00015.03. 13:21
rcs5x86_​642 x 12,80011,19815.03. 14:59
r0s6sx86_​6410 x 23,700147,98015.03. 13:18
r3s6x86_​641 x 21,6606,66615.03. 13:40
r1s6sx86_​642 x 21,66713,33215.03. 13:25
rds0x86_​644 x 21,80031,99215.03. 15:07
res1sx86_​644 x 11,60014,40015.03. 15:13
rds7x86_​644 x 11,60012,74815.03. 15:11
r8s6sx86_​644 x 13,30026,41615.03. 14:30
r5s2sx86_​644 x 24,00063,86312.04. 01:34
rfs2x86_​644 x 13,00024,00015.03. 15:23
rcs2x86_​642 x 12,80011,23215.03. 14:55
r5s4x86_​642 x 22,53020,26415.03. 13:59
rcs4x86_​642 x 11,1004,37615.03. 14:57
r8s3x86_​644 x 12,66721,28015.03. 14:27
r2s0x86_​644 x 13,10024,79615.03. 13:27
r1s2x86_​644 x 12,30027,99615.03. 13:21
r0s3sx86_​644 x 23,60067,20015.03. 13:13
r6s1x86_​642 x 12,0007,97812.12. 02:21
r7s0x86_​642 x 22,30018,40015.03. 14:15
rds1x86_​644 x 11,60012,74815.03. 15:07
r0s6x86_​648 x 23,600115,20015.03. 13:17
r0s4sx86_​648 x 23,600115,20015.03. 13:15
rbs2sx86_​641 x 13,500007.09. 15:06
r6s4x86_​642 x 11,1004,37615.03. 14:12
rds5x86_​644 x 11,60012,74815.03. 15:10
ras8x86_​644 x 11,60014,40015.03. 14:43
res5x86_​642 x 22,20019,20015.03. 15:16
 

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