You are here: Home / Projects / QA Farm Realtime / CPUs under test / 
2017-07-21 - 22:39

Dates and Events:

Breaking News:

2016-11-12 12:00

Raspberry Pi and real-time Linux

Let's have a look at the OSADL QA Farm data


2016-09-17 12:00

Preemption latency of real-time Linux systems

How to measure it – and how to fix it, if it's too high?


2014-11-18 00:00

Linux real-time: New stable release available -

but next one depends on more support from industrial users



Number of cores/hyperthreads and bogoMIPS (by bogoMIPS) - (x86 CPU strings)

BoxArchCoresMHzBogo​MIPSEffective
r4s5arm​v7l1 x 1500021.07. 13:32
r9s7arm​v7l2 x 11000021.07. 13:58
rbs7arm​v7l4 x 19962421.07. 14:19
r2s5ppc1 x 13966621.07. 13:21
ras7ppc1 x 13966521.07. 14:03
r5s6ppc1 x 153313321.07. 13:38
rbs3sarm​v7l4 x 1120015221.07. 14:18
rbs3arm​v7l4 x 190015221.07. 14:17
r7s3sarm​v7l4 x 1120015221.07. 13:45
r2s1arm​v5tejl1 x 120019921.07. 13:20
r7s4arm​v7l1 x 153634821.07. 13:45
r4s2sarm​v7l1 x 180039821.07. 13:30
ras4arm​v7l1 x 150039821.07. 14:03
r7s6arm​v7l1 x 1100039821.07. 13:47
r1s5ppc2 x 1120040021.07. 13:18
r5s7mips​1 x 149249204.07. 01:39
r2s3arm​v7l1 x 160049521.07. 13:21
r8s6arm​v7l1 x 150049821.07. 13:53
r2s2arm​v7l1 x 172049921.07. 13:20
r1s7arm​v6l1 x 172053021.07. 13:19
r4s2arm​v7l1 x 180053021.07. 13:29
r2s8arm​v6l1 x 153253021.07. 13:22
r2s4mips​641 x 180053121.07. 13:21
r5s5arm​v7l1 x 160059721.07. 13:36
r5s5sarm​v7l1 x 160060021.07. 13:37
r8s1i5861 x 130060121.07. 13:50
ras3sarm​v7l8 x 1130074421.05. 14:08
r7s8arm​v7l1 x 1100079621.07. 13:49
r7s8sarm​v7l1 x 1100099321.07. 13:50
r4s3i5861 x 150099621.07. 13:32
r3s7i6861 x 1533106621.07. 13:26
r7s2i6861 x 1600119621.07. 13:43
r7s3i6861 x 1800160221.07. 13:44
ras6sarm​v7l1 x 11000198730.05. 14:09
rbs2i6861 x 11000199921.07. 14:17
r7s5i6861 x 11300259321.07. 13:46
r5s8ppc1 x 1400263721.07. 13:38
rbs8arm​v7l2 x 1666265021.07. 14:20
ras1i6861 x 11400279921.07. 14:02
r6s5i6861 x 11500299221.07. 13:40
r2s6i6861 x 11500299921.07. 13:21
r3s2i6861 x 11530306221.07. 13:23
r6s6i6861 x 11600319221.07. 13:41
r1s3x86_​641 x 11800359021.07. 13:17
r9s4i6861 x 21000399021.07. 13:56
r9s1x86_​642 x 12000399221.07. 13:55
r4s8x86_​642 x 11140399921.07. 13:33
ras3aarch​648 x 12000400021.07. 14:02
ras2x86_​642 x 11067426621.07. 14:02
r6s4x86_​641 x 12200438821.07. 13:40
r9s4sx86_​642 x 11333532821.07. 13:56
rcs3i6862 x 11400558621.07. 14:21
r3s4x86_​641 x 21400560021.07. 13:24
r9s8arm​v7l4 x 1996632421.07. 13:58
r1s8i6861 x 21600640021.07. 13:19
r3s6x86_​641 x 21667666621.07. 13:25
r8s8i6862 x 11900758721.07. 13:54
r6s1x86_​642 x 12000798021.07. 13:39
rbs5i6862 x 12000799821.07. 14:19
r6s7i6862 x 12300917621.07. 13:42
r6s2x86_​642 x 11667957621.07. 13:39
r1s2x86_​642 x 12400960021.07. 13:16
rbs4x86_​644 x 11200960021.07. 14:18
ras8i6862 x 125001077621.07. 14:04
r9s5x86_​642 x 127001077621.07. 13:57
r8s7x86_​642 x 127001077621.07. 13:53
rcs2x86_​642 x 128001123321.07. 14:21
r8s2x86_​642 x 129001157221.07. 13:51
r4s7x86_​644 x 116001279621.07. 13:33
r7s1x86_​644 x 116001283921.07. 13:43
r1s4x86_​642 x 216671333221.07. 13:17
rcs7x86_​642 x 218001439621.07. 14:23
r8s4si6864 x 118331466421.07. 13:52
r8s4i6864 x 118331466421.07. 13:52
rbs6x86_​644 x 119901603721.07. 14:19
r4s1sx86_​642 x 221001673821.07. 13:28
r1s6x86_​642 x 221301702421.07. 13:18
r5s0x86_​642 x 222001757921.07. 13:34
r6s8x86_​642 x 223001838021.07. 13:42
r7s0x86_​642 x 223001839621.07. 13:42
r4s0x86_​642 x 223001840021.07. 13:27
r0s1x86_​642 x 223001840021.07. 13:10
ras0x86_​642 x 223001840021.07. 14:01
r8s0x86_​642 x 223001841521.07. 13:50
r9s0x86_​642 x 223001841621.07. 13:54
r3s1i6864 x 124001912821.07. 13:23
rbs0i6862 x 225001995221.07. 14:04
r3s0i6862 x 225001995221.07. 13:23
rcs6x86_​644 x 125001996421.07. 14:22
r0s0x86_​642 x 225001997521.07. 13:10
r5s4x86_​642 x 225302026421.07. 13:35
r5s4si6862 x 225302026421.07. 13:36
r0s2x86_​644 x 126672127721.07. 13:10
r3s6sx86_​642 x 226672133221.07. 13:25
r4s1x86_​642 x 227002155321.07. 13:27
r5s2x86_​644 x 127002169821.07. 13:35
r9s6x86_​642 x 230002394421.07. 13:58
rbs1x86_​644 x 131002480021.07. 14:05
r2s0x86_​644 x 131002481421.07. 13:19
r1s0x86_​644 x 131002481421.07. 13:15
r0s4x86_​642 x 237002954221.07. 13:11
r2s7x86_​644 x 137002959421.07. 13:22
r5s3x86_​644 x 220003187921.07. 13:35
r6s3x86_​644 x 222003512021.07. 13:39
r9s3x86_​644 x 225003669521.07. 13:55
r3s8i6866 x 132003852421.07. 13:26
r9s2x86_​644 x 227004320021.07. 13:55
r0s1sx86_​644 x 233005280021.07. 13:10
r5s1i6864 x 233305318521.07. 13:34
r4s6x86_​644 x 234005425621.07. 13:33
r8s5i6864 x 234005440021.07. 13:52
r9s5sx86_​644 x 234005452821.07. 13:57
r8s7sx86_​644 x 234005452804.07. 01:59
rcs5x86_​644 x 234005455921.07. 14:21
r8s3x86_​644 x 235005587221.07. 13:51
r0s6x86_​644 x 235005590721.07. 13:12
r0s5x86_​644 x 235005590821.07. 13:12
r6s0x86_​648 x 136005778421.07. 13:38
r5s2sx86_​644 x 240006386312.04. 01:34
rcs8x86_​646 x 226706411321.07. 14:23
r0s8x86_​644 x 240006416221.07. 13:14
r3s3x86_​646 x 233337999221.07. 13:24
r0s7x86_​646 x 230008017221.07. 13:13
r0s8sx86_​646 x 234708319621.07. 13:14
rcs1x86_​646 x 234678324821.07. 14:20
r0s3x86_​646 x 236008645721.07. 13:11
r1s1x86_​642 x 16 x 1210013438421.07. 13:16
 

Valid XHTML 1.0 Transitional