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2019-03-27 - 03:29

Number of cores/hyperthreads and bogoMIPS (by bogoMIPS) - (x86 CPU strings)

BoxArchCoresMHzBogo​MIPSEffective
r4s5arm​v7l1 x 1500027.03. 01:37
r9s7arm​v7l2 x 11000027.03. 02:15
r7s3arm​v6l1 x 1700527.03. 01:56
rbs7arm​v7l4 x 19962427.03. 02:35
ras5arm​v7l2 x 110002427.03. 02:23
ras5sarm​v7l2 x 110002427.03. 02:23
r5s7sarm​v7l1 x 15284827.03. 01:49
r1s4sarm​v7l2 x 14004827.03. 01:18
r5s7arm​v7l1 x 15284827.03. 01:48
r1s4arm​v7l2 x 14004827.03. 01:17
r2s5ppc1 x 13966626.01. 13:22
ras7ppc1 x 13966527.03. 02:24
r2s8ppc1 x 14006627.03. 01:24
r5s6ppc1 x 153313327.03. 01:47
rbs3arm​v7l4 x 190017627.03. 02:32
r2s1arm​v5tejl1 x 120019927.03. 01:21
r4s5saarch​644 x 1160020027.03. 01:37
r3s5i5861 x 113326527.03. 01:26
r7s4arm​v7l1 x 153634827.03. 01:58
rbs3sarm​v7l4 x 1140035627.03. 02:33
r7s3sarm​v7l4 x 1140035627.03. 01:57
ras4sarm​v7l1 x 180039827.03. 02:21
r4s8arm​v7l1 x 140039827.03. 01:40
r4s2sarm​v7l1 x 180039827.03. 01:33
r4s2arm​v7l1 x 180039827.03. 01:31
ras4arm​v7l1 x 150039827.03. 02:21
r4s8sarm​v7l1 x 140039827.03. 01:40
r7s6arm​v7l1 x 1100039827.03. 01:59
r3s5sppc2 x 1120040027.03. 01:27
r7s5sarm​v7l2 x 140040024.03. 13:59
r2s3arm​v7l1 x 160049527.03. 01:21
r8s6arm​v7l1 x 150049827.03. 02:07
r4s4ppc4 x 1120049827.03. 01:36
r2s2arm​v7l1 x 172049927.03. 01:21
r1s7arm​v6l1 x 172053027.03. 01:19
r2s4mips​641 x 180053110.01. 01:23
r5s5arm​v7l1 x 160059727.03. 01:43
r9s8arm​v7l1 x 160059727.03. 02:16
r5s5sarm​v7l1 x 160060027.03. 01:44
r8s1i5861 x 130060127.03. 02:04
ras3sarm​v7l8 x 1130074421.05. 14:08
r1s5aarch​644 x 1120079627.03. 01:18
r9s8sarm​v7l1 x 180079627.03. 02:17
r7s8arm​v7l1 x 1100079627.03. 02:02
r7s8sarm​v7l1 x 1100079627.03. 02:03
r4s3i5861 x 150099627.03. 01:35
r3s7i6861 x 1533106627.03. 01:28
r7s2i6861 x 1600119627.03. 01:54
ras6sarm​v7l1 x 11000198727.03. 02:24
ras6arm​v7l1 x 11000198727.03. 02:23
rbs2i6861 x 11000199927.03. 02:29
r7s5i6861 x 11300259327.03. 01:58
r5s8ppc1 x 1400263727.03. 01:50
rbs8arm​v7l2 x 1666265027.03. 02:39
ras1i6861 x 11400279927.03. 02:19
r6s5i6861 x 11500299228.01. 13:54
r2s6i6861 x 11500299927.03. 01:22
r3s2i6861 x 11530306127.03. 01:25
r6s6i6861 x 11600319127.03. 01:52
r1s3x86_​641 x 11800359027.03. 01:17
r9s4i6861 x 21000399027.03. 02:12
r9s1x86_​642 x 12000399127.03. 02:09
r9s1sx86_​642 x 11140399927.03. 02:10
ras3aarch​648 x 12000400027.03. 02:20
ras2x86_​642 x 11067426627.03. 02:19
rcs4x86_​642 x 11100437627.03. 02:45
r6s4x86_​642 x 11100437627.03. 01:52
rbs6sx86_​642 x 11333533227.03. 02:35
r9s4sx86_​642 x 11333534727.03. 02:12
rcs3i6862 x 11400558627.03. 02:42
r3s4x86_​641 x 21400559822.12. 01:28
rbs7sarm​v7l4 x 1996632427.03. 02:36
r1s8i6861 x 21600640027.03. 01:20
r3s6x86_​641 x 21667666427.03. 01:27
r4s7sx86_​642 x 11833733027.03. 01:39
r8s8i6862 x 11900758727.03. 02:08
r6s1x86_​642 x 12000798027.03. 01:51
rbs5i6862 x 12000799927.03. 02:34
r6s7i6862 x 12300917627.03. 01:53
r6s2x86_​642 x 11667957827.03. 01:51
r3s1i6862 x 12400959927.03. 01:25
r1s2x86_​642 x 12400960027.03. 01:17
rbs4x86_​644 x 11200960027.03. 02:33
ras8i6862 x 125001077427.03. 02:24
r9s5x86_​642 x 127001077827.03. 02:13
r8s7x86_​642 x 127001077927.03. 02:07
rcs5x86_​642 x 128001123227.03. 02:45
rcs5sx86_​642 x 128001123227.03. 02:47
rcs2x86_​642 x 128001123227.03. 02:42
rcs7sx86_​644 x 115001198027.03. 02:50
ras8sx86_​644 x 116001274827.03. 02:25
rbs4sx86_​644 x 116001274827.03. 02:33
r5s3sx86_​644 x 116001274827.03. 01:42
r7s7x86_​644 x 116001276727.03. 02:01
r7s1x86_​644 x 116001283927.03. 01:54
r8s7sx86_​642 x 133001324827.03. 02:07
r1s6sx86_​642 x 216671333227.03. 01:19
rcs7x86_​642 x 218001440027.03. 02:50
r4s7i6864 x 118331466027.03. 01:38
r8s4si6864 x 118331466427.03. 02:06
r8s4i6864 x 118331466427.03. 02:05
r1s8sx86_​644 x 119001518027.03. 01:20
rbs6x86_​644 x 119151532427.03. 02:34
r2s6sx86_​644 x 119901599227.03. 01:22
r8s2x86_​642 x 221001676027.03. 02:04
r8s2sx86_​642 x 221001676027.03. 02:05
r4s1sx86_​642 x 221001676827.03. 01:31
r1s6x86_​642 x 221301706427.03. 01:18
r5s0x86_​642 x 222001758427.03. 01:41
rbs0i6862 x 225001760027.03. 02:26
r6s8x86_​642 x 223001835627.03. 01:53
r8s0x86_​642 x 223001839627.03. 02:03
r4s0x86_​642 x 223001840027.03. 01:30
r9s0x86_​642 x 223001840027.03. 02:09
ras0x86_​642 x 223001841527.03. 02:18
r7s0x86_​642 x 223001841627.03. 01:54
r7s7sx86_​642 x 223001844827.03. 02:02
r5s4x86_​642 x 225302026427.03. 01:43
r5s4si6862 x 225302026427.03. 01:43
r8s3x86_​644 x 126672127627.03. 02:05
r3s6sx86_​642 x 226672133227.03. 01:28
r4s1x86_​642 x 227002155327.03. 01:30
r5s2x86_​644 x 127002169927.03. 01:41
r9s6x86_​642 x 230002396727.03. 02:14
r9s3sx86_​644 x 130002400027.03. 02:11
r2s0x86_​644 x 131002479627.03. 01:20
r1s0x86_​644 x 131002480027.03. 01:16
rbs1x86_​644 x 131002480027.03. 02:26
r0s4x86_​642 x 237002952827.03. 01:12
r2s7x86_​644 x 137002960027.03. 01:23
r5s3x86_​644 x 220003187227.03. 01:41
r6s3x86_​644 x 222003512027.03. 01:51
r9s3x86_​644 x 225003670427.03. 02:11
r3s8i6866 x 132003852627.03. 01:29
r0s0x86_​644 x 225004000027.03. 01:10
r9s2x86_​644 x 227004320027.03. 02:10
rcs3sx86_​644 x 233005269627.03. 02:43
r0s1sx86_​644 x 233005280027.03. 01:10
rcs8sx86_​644 x 233005280027.03. 02:52
r5s1i6864 x 233305318519.01. 13:44
r4s6x86_​644 x 234005426427.03. 01:37
r8s5i6864 x 234005439227.03. 02:06
r0s5sx86_​644 x 234005452827.03. 01:13
r9s5sx86_​644 x 234005452827.03. 02:13
r0s6x86_​644 x 235005586427.03. 01:14
r0s2sx86_​644 x 235005586427.03. 01:11
r0s5x86_​644 x 235005586427.03. 01:13
r0s1x86_​644 x 223005599227.03. 01:10
r3s0i6864 x 235005600027.03. 01:24
r5s2sx86_​644 x 240006386312.04. 01:34
rcs6x86_​644 x 240006412827.03. 02:49
rcs8x86_​646 x 226706414027.03. 02:51
r0s2x86_​644 x 242006720027.03. 01:11
rcs0x86_​642 x 4 x 224007697627.03. 02:40
r3s3x86_​646 x 233337999227.03. 01:26
r0s7x86_​646 x 233337999227.03. 01:14
rcs1x86_​646 x 234678326427.03. 02:42
r0s8sx86_​646 x 234708337627.03. 01:16
r0s3x86_​646 x 236008638827.03. 01:12
r1s1x86_​642 x 16 x 1210013438410.02. 13:16
r4s4sppc4 x 1120013438406.08. 11:25
r6s0x86_​642 x 10 x 2170013614027.03. 01:50
r0s8x86_​6416 x 2370021715227.03. 01:15
 

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