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2026-01-13 - 08:20

Dates and Events:

OSADL Articles:

2024-10-02 12:00

Linux is now an RTOS!

PREEMPT_RT is mainline - What's next?


2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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[ 290.152] (II) VESA: driver for VESA chipsets: vesa [ 290.152] (II) VESA: driver for VESA chipsets: vesa

Number of cores/hyperthreads and bogoMIPS (by cores) - (x86 CPU strings)

[ 290.152] (II) VESA: driver for VESA chipsets: vesa
BoxArchCoresMHz ↑Bogo​MIPSEffective
rbs5i6864 x 2049,66013.01. 02:50
r9s1sarm​v7l1 x 101,25014.04. 18:03
r7s2sriscv644 x 1028412.12. 02:29
r3s2sriscv644 x 1028413.01. 01:41
res6saarch​644 x 101,60013.01. 03:21
r3s5i5861 x 113326513.01. 01:44
r2s1arm​v5tejl1 x 120019913.01. 01:30
r8s1i5861 x 135070113.01. 02:29
r2s5ppc1 x 13966625.12. 13:33
ras7ppc1 x 13966513.01. 02:44
r1s4sarm​v7l2 x 14004813.01. 01:26
r4s8arm​v7l1 x 140039813.01. 02:01
r2s8ppc1 x 14006613.01. 01:38
r4s8sarm​v7l1 x 140039813.01. 02:02
r8s6arm​v7l1 x 150049813.01. 02:31
r4s5arm​v7l1 x 1500013.01. 01:58
r4s3i5861 x 150099613.01. 01:54
r5s7sarm​v7l1 x 15284813.01. 02:12
r5s7arm​v7l1 x 15286412.12. 02:17
r3s7i6861 x 15331,06613.01. 01:47
r5s6ppc1 x 153313313.01. 02:12
r7s4arm​v7l1 x 153634813.01. 02:23
r5s5sarm​v7l1 x 160060013.01. 02:09
r2s3sarm​v7l0 x 2 x 16001,20013.01. 01:35
r5s5arm​v7l1 x 160059713.01. 02:07
r2s3arm​v7l0 x 1 x 162462413.01. 01:34
rbs8arm​v7l2 x 16662,65013.01. 02:55
rfs6arm​v7l1 x 16671,33213.01. 03:30
rfs6sarm​v7l1 x 16671,33213.01. 03:31
r7s3arm​v6l1 x 1700513.01. 02:21
rfs7sx86_​644 x 17006,44813.01. 03:32
r2s2arm​v7l1 x 172049913.01. 01:33
r9s8sarm​v7l1 x 180079612.12. 02:52
r4s2sarm​v7l1 x 180053013.01. 01:52
r4s2arm​v7l1 x 180079613.01. 01:51
rfs4sarm​v7l1 x 180080013.01. 03:28
r2s4mips​641 x 180053129.09. 13:34
rbs7arm​v7l4 x 19961213.01. 02:52
rbs3arm​v7l4 x 19962413.01. 02:48
rbs7sarm​v7l4 x 19962413.01. 02:54
r9s4i6861 x 21,0003,99013.01. 02:37
res7sarm​v7l0 x 1 x 11,0001213.01. 03:22
r3s2riscv641 x 11,00028413.01. 01:40
r4s6sarm​v7l0 x 1 x 11,0006613.01. 01:59
ras6sarm​v7l1 x 11,0001,98713.01. 02:44
r7s8arm​v7l1 x 11,00099513.01. 02:27
ras5arm​v7l2 x 11,0002413.01. 02:42
res3saarch​640 x 1 x 11,0001,60013.01. 03:17
r7s6arm​v7l1 x 11,00039828.02. 14:10
ras5sarm​v7l2 x 11,0002413.01. 02:43
res7arm​v7l0 x 1 x 11,0001213.01. 03:21
rfs8arm​v7l1 x 11,00012004.03. 03:47
r7s8sarm​v7l1 x 11,00099613.01. 02:27
r9s7arm​v7l2 x 11,000013.01. 02:39
ras2x86_​642 x 11,0674,26613.01. 02:41
rcs4x86_​642 x 11,1004,37613.01. 03:00
r6s4x86_​642 x 11,1004,37613.01. 02:16
res6x86_​644 x 11,1008,75213.01. 03:20
r4s4ppc4 x 11,20049813.01. 01:55
r1s5aarch​644 x 11,20079613.01. 01:26
r3s5sppc2 x 11,20040013.01. 01:46
r2s5sarm​v7l4 x 11,20015212.12. 01:35
r1s4arm​v7l2 x 11,2004813.01. 01:25
rfs5saarch​644 x 11,2006427.08. 03:49
rbs4x86_​644 x 11,2009,60013.01. 02:49
rfs5aarch​644 x 11,2006413.01. 03:29
ras3sarm​v7l1 x 11,30084013.01. 02:42
r3s4aarch​646 x 11,3009613.01. 01:43
r7s5i6861 x 11,3002,59313.01. 02:24
r8s8x86_​642 x 11,3005,14413.01. 02:34
rbs6sx86_​642 x 11,3335,33229.08. 03:00
r9s4sx86_​642 x 11,3335,34713.01. 02:37
r2s6saarch​644 x 11,3506413.01. 01:36
rfs4aarch​641 x 11,4001,60013.01. 03:27
rcs3i6862 x 11,4005,58613.01. 02:59
rbs3sarm​v7l4 x 11,40035613.01. 02:48
r7s3sarm​v7l4 x 11,40015213.01. 02:22
ras1i6861 x 11,4002,79913.01. 02:40
r4s3si6861 x 11,4662,93228.07. 02:17
r2s7saarch​644 x 11,50043213.01. 01:37
rfs1aarch​644 x 11,50043213.01. 03:24
rfs1saarch​644 x 11,50043213.01. 03:25
rcs7sx86_​644 x 11,50011,98013.01. 03:05
r2s6i6861 x 11,5002,99913.01. 01:36
r6s5i6861 x 11,5002,99213.01. 02:16
r7s4sarm​v7l4 x 11,5001,08013.01. 02:24
r4s1sarm​v7l4 x 11,50086413.01. 01:50
r4s1arm​v7l4 x 11,50072013.01. 01:50
rds3x86_​644 x 11,60012,74813.01. 03:11
rds4x86_​644 x 11,60012,74813.01. 03:12
rds2x86_​644 x 11,60012,74813.01. 03:11
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r8s4sx86_​644 x 21,60028,80013.01. 02:31
r7s7x86_​644 x 11,60012,76713.01. 02:26
res1sx86_​644 x 11,60014,40013.01. 03:16
rds7x86_​644 x 11,60012,74813.01. 03:14
rds1x86_​644 x 11,60012,74813.01. 03:10
rds5x86_​644 x 11,60012,74813.01. 03:12
ras8x86_​644 x 11,60014,40013.01. 02:45
r9s3x86_​644 x 11,60012,74813.01. 02:36
r9s2x86_​644 x 11,60012,74802.01. 02:36
rds6x86_​644 x 11,60012,74813.01. 03:13
rfs3x86_​644 x 11,60012,74813.01. 03:25
ras8sx86_​644 x 11,60012,74813.01. 02:46
rbs4sx86_​644 x 11,60012,74813.01. 02:50
res2x86_​644 x 11,60014,40013.01. 03:16
r6s6i6861 x 11,6003,19213.01. 02:17
rfs3sx86_​644 x 11,60012,74813.01. 03:26
res1x86_​644 x 11,60014,40013.01. 03:16
rds8x86_​644 x 11,60012,74813.01. 03:14
r4s5saarch​644 x 11,60020012.12. 02:02
r5s3sx86_​644 x 11,60012,74813.01. 02:04
r7s1x86_​644 x 11,60012,83913.01. 02:20
r8s4x86_​644 x 21,60028,80013.01. 02:30
rbs5saarch​644 x 11,6006413.01. 02:51
r5s4sx86_​644 x 11,60012,74813.01. 02:06
r1s8i6861 x 21,6006,40013.01. 01:28
r3s6x86_​641 x 21,6606,66613.01. 01:46
r1s6sx86_​642 x 21,66713,33213.01. 01:27
r6s2x86_​642 x 11,6679,57812.12. 02:22
r6s0x86_​642 x 10 x 21,700136,14013.01. 02:14
r7s2aarch​642 x 11,7009613.01. 02:20
rcs7x86_​642 x 21,80014,40013.01. 03:04
rds0x86_​644 x 21,80031,99213.01. 03:10
r4s7i6864 x 11,83314,66413.01. 02:00
r4s7sx86_​642 x 11,8337,33213.01. 02:00
r1s8sx86_​644 x 11,90015,19613.01. 01:29
res8sx86_​644 x 11,90015,05213.01. 03:23
ras2sx86_​644 x 11,90015,05213.01. 02:41
res8x86_​644 x 11,90015,05213.01. 03:23
res4sx86_​644 x 11,90015,05213.01. 03:19
res4x86_​644 x 11,90015,05213.01. 03:18
rbs6x86_​644 x 11,91515,32413.01. 02:51
rfs0x86_​6416 x 22,000128,00013.01. 03:24
r5s8x86_​644 x 12,00015,97213.01. 02:14
res3x86_​644 x 12,00015,97213.01. 03:17
r9s1x86_​642 x 12,0003,99212.12. 02:46
r6s1x86_​642 x 12,0007,97812.12. 02:21
ras3aarch​648 x 12,0004,00006.05. 03:01
ras6aarch​648 x 12,0003,20013.01. 02:43
r5s3x86_​644 x 22,00031,87213.01. 02:04
thlfwx86_​644 x 12,00015,97213.01. 02:47
thlfw2x86_​644 x 12,00015,97213.01. 02:47
r1s6x86_​642 x 22,13017,06413.01. 01:26
r5s0x86_​642 x 22,20017,58213.01. 02:02
res5sx86_​642 x 22,20019,20013.01. 03:20
res5x86_​642 x 22,20019,20013.01. 03:19
r6s3x86_​644 x 22,20035,12013.01. 02:15
r6s8x86_​642 x 22,30018,35613.01. 02:19
r4s0x86_​642 x 22,30018,40013.01. 01:49
r0s1x86_​644 x 22,30056,00013.01. 01:11
r1s2sx86_​644 x 12,30028,00013.01. 01:24
r1s2x86_​644 x 12,30027,99613.01. 01:23
r7s0x86_​642 x 22,30018,40013.01. 02:19
ras0x86_​642 x 22,30018,41813.01. 02:40
r8s0x86_​642 x 22,30018,40013.01. 02:28
r6s7i6862 x 12,3009,17613.01. 02:18
r7s7sx86_​642 x 22,30018,39613.01. 02:26
r3s1i6864 x 12,40019,12813.01. 01:39
ras4saarch​648 x 12,40038429.09. 03:02
rbs8sx86_​644 x 22,40038,70413.01. 02:55
ras4aarch​648 x 12,40038413.01. 02:42
rcs0x86_​648 x 22,40076,40013.01. 02:57
r2s7aarch​644 x 12,40043213.01. 01:36
rbs0i6862 x 22,50017,60013.01. 02:46
r0s0x86_​644 x 22,50039,99213.01. 01:10
r5s4x86_​642 x 22,53020,26413.01. 02:05
rfs7x86_​644 x 22,60041,60013.01. 03:31
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s1x86_​642 x 22,60021,69613.01. 01:23
r8s3x86_​644 x 12,66721,28013.01. 02:30
r3s6sx86_​642 x 22,66721,33213.01. 01:47
r9s5x86_​642 x 12,70010,77413.07. 03:15
r5s2x86_​644 x 12,70021,69913.01. 02:03
rcs5x86_​642 x 12,80011,19813.01. 03:01
rcs5sx86_​642 x 12,80011,19813.01. 03:03
rcs2x86_​642 x 12,80011,23213.01. 02:58
r1s3x86_​644 x 12,80022,42413.01. 01:24
r9s6x86_​642 x 23,00023,94413.01. 02:39
rfs2x86_​644 x 13,00024,00013.01. 03:25
rfs2sx86_​642 x 13,00011,99813.01. 03:25
r8s7sx86_​642 x 13,00011,98013.01. 02:33
r9s3sx86_​644 x 13,00024,00013.01. 02:36
r2s0x86_​644 x 13,10024,79613.01. 01:29
r1s0x86_​644 x 13,10024,80013.01. 01:22
r3s8i6864 x 13,20027,37113.01. 01:48
r8s7x86_​644 x 13,20025,49613.01. 02:33
rcs3sx86_​644 x 13,30026,39613.01. 03:00
r8s6sx86_​644 x 13,30026,41613.01. 02:32
r9s5sx86_​642 x 13,30013,19813.01. 02:38
r0s1sx86_​644 x 23,30052,80013.01. 01:11
rcs8sx86_​644 x 23,30052,80013.01. 03:09
r3s3x86_​646 x 23,33379,99213.01. 01:41
r5s1x86_​646 x 13,33340,00213.01. 02:02
r0s0sx86_​644 x 23,40054,39213.01. 01:10
r4s6x86_​644 x 23,40054,25613.01. 01:58
r8s5i6864 x 23,40054,40013.01. 02:31
res0x86_​644 x 23,40054,39213.01. 03:15
r1s7arm​v6l1 x 13,40053013.01. 01:27
r3s3sx86_​644 x 13,40011,98013.01. 01:42
rcs1x86_​646 x 23,46783,37613.01. 02:57
r0s8sx86_​646 x 23,47083,37612.12. 01:22
rcs6x86_​644 x 23,50063,99213.01. 03:03
rbs2sx86_​641 x 13,500007.09. 15:06
r0s2x86_​644 x 23,50055,86413.01. 01:11
r0s5x86_​648 x 23,500115,20013.01. 01:16
r3s0i6864 x 23,50055,99213.01. 01:39
r0s3sx86_​644 x 23,60067,20013.01. 01:14
r0s6x86_​648 x 23,600115,20013.01. 01:17
r0s4sx86_​648 x 23,600115,20013.01. 01:16
r0s5sx86_​648 x 23,600115,20013.01. 01:17
r0s4x86_​648 x 23,600115,20013.01. 01:15
r9s0x86_​644 x 23,60057,60013.01. 02:34
r0s7x86_​648 x 23,600115,20006.01. 13:20
r0s8x86_​648 x 23,600115,20013.01. 01:21
r0s3x86_​648 x 23,600115,20013.01. 01:13
r0s6sx86_​6410 x 23,700147,98013.01. 01:20
r0s2sx86_​6410 x 13,70073,99013.01. 01:12
r0s7sx86_​642 x 23,70029,53223.05. 13:21
rcs8x86_​6416 x 23,700217,18413.01. 03:09
r5s2sx86_​644 x 24,00063,86312.04. 01:34
 

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