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2023-05-29 - 03:22

Dates and Events:

OSADL Articles:

2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available


2016-11-12 12:00

Raspberry Pi and real-time Linux

Let's have a look at the OSADL QA Farm data



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OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (by cores) - (x86 CPU strings)

BoxArchCoresMHz ↑Bogo​MIPSEffective
rbs5i6864 x 2049,16829.05. 02:46
r9s1sarm​v7l1 x 101,25014.04. 18:03
res3saarch​646 x 109625.05. 15:27
res6saarch​644 x 101,60028.05. 15:32
r3s5i5861 x 113326519.05. 13:44
r2s1arm​v5tejl1 x 120019929.05. 01:37
r8s1i5861 x 130060129.05. 02:24
r2s5ppc1 x 13966627.04. 13:39
ras7ppc1 x 13966529.05. 02:40
r1s4sarm​v7l2 x 14004829.05. 01:34
r4s8arm​v7l1 x 140039829.05. 01:58
r2s8ppc1 x 14006629.05. 01:39
r4s8sarm​v7l1 x 140039829.05. 01:58
r8s6arm​v7l1 x 150049829.05. 02:30
r4s5arm​v7l1 x 1500029.05. 01:55
r4s3i5861 x 150099629.05. 01:50
ras4arm​v7l1 x 150039829.05. 02:38
r5s7sarm​v7l1 x 15286429.05. 02:10
r5s7arm​v7l1 x 15286429.05. 02:08
r3s7i6861 x 15331,06629.05. 01:44
r5s6ppc1 x 153313329.05. 02:08
r7s4arm​v7l1 x 153635129.05. 02:20
r5s5sarm​v7l1 x 160060029.05. 02:04
r5s5arm​v7l1 x 160059729.05. 02:03
ras4sarm​v7l1 x 160059707.02. 02:45
rbs8arm​v7l2 x 16662,65029.05. 02:50
r7s3arm​v6l1 x 1700529.05. 02:17
r2s2arm​v7l1 x 172049929.05. 01:38
r9s8sarm​v7l1 x 180079629.05. 02:36
r4s2sarm​v7l1 x 180053029.05. 01:48
r4s2arm​v7l1 x 180079629.05. 01:47
r2s4mips​641 x 180053110.01. 01:23
rbs7arm​v7l4 x 19961229.05. 02:48
rbs3arm​v7l4 x 19962429.05. 02:44
rbs7sarm​v7l4 x 19962429.05. 02:49
r9s4i6861 x 21,0003,98829.05. 02:33
r3s2riscv641 x 11,00028429.05. 01:41
r4s6sarm​v7l0 x 1 x 11,0006629.05. 01:56
ras6sarm​v7l1 x 11,0001,98729.05. 02:39
ras6arm​v7l1 x 11,0001,98729.05. 02:39
r7s8arm​v7l1 x 11,00099529.05. 02:23
ras5arm​v7l2 x 11,0002429.05. 02:38
r7s6arm​v7l1 x 11,00039828.02. 14:10
ras5sarm​v7l2 x 11,0002429.05. 02:39
r7s8sarm​v7l1 x 11,00079629.05. 02:24
r9s7arm​v7l2 x 11,000029.05. 02:36
ras2x86_​642 x 11,0674,26629.05. 02:37
rcs4x86_​642 x 11,1004,37629.05. 03:18
r6s4x86_​642 x 11,1004,37629.05. 02:13
rcs4sx86_​644 x 11,1008,75229.05. 03:19
res6x86_​644 x 11,1008,75228.05. 15:31
r4s4ppc4 x 11,20049829.05. 01:52
r1s5aarch​644 x 11,20079629.05. 01:34
r3s5sppc2 x 11,20040029.05. 01:42
r1s4arm​v7l2 x 11,2004829.05. 01:33
rbs4x86_​644 x 11,2009,60029.05. 02:45
ras3sarm​v7l8 x 11,30084025.11. 02:17
r7s5i6861 x 11,3002,59329.05. 02:21
r8s8x86_​642 x 11,3005,14429.05. 02:31
rbs6sx86_​642 x 11,3335,33229.05. 02:47
r9s4sx86_​642 x 11,3335,34729.05. 02:34
rcs3i6862 x 11,4005,58829.05. 03:15
rbs3sarm​v7l4 x 11,40035629.05. 02:44
r3s4x86_​641 x 21,4005,60010.01. 01:28
r7s3sarm​v7l4 x 11,40015229.05. 02:19
ras1i6861 x 11,4002,79929.05. 02:37
r4s3si6861 x 11,4662,93229.05. 01:51
r7s2sarm​v7l4 x 11,50072013.07. 02:16
rcs7sx86_​644 x 11,50011,98028.05. 15:18
r2s6i6861 x 11,5002,99929.05. 01:38
r6s5i6861 x 11,5002,99229.05. 02:14
r7s4sarm​v7l4 x 11,50057629.05. 02:21
r4s1sarm​v7l4 x 11,50086429.05. 01:46
r4s1arm​v7l4 x 11,50079229.05. 01:46
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r8s4sx86_​644 x 21,60028,80029.05. 02:28
r7s7x86_​644 x 11,60012,76729.05. 02:22
res1sx86_​644 x 11,60014,40028.05. 15:28
rds7x86_​644 x 11,60012,74828.05. 15:25
rds5x86_​644 x 11,60012,74828.05. 15:24
ras8x86_​644 x 11,60014,40029.05. 02:40
r9s3x86_​644 x 11,60012,74829.05. 02:33
r9s2x86_​644 x 11,60012,74829.05. 02:32
rds6x86_​644 x 11,60012,74828.05. 15:25
ras8sx86_​644 x 11,60012,74829.05. 02:41
rbs4sx86_​644 x 11,60012,74829.05. 02:46
res2x86_​644 x 11,60014,40028.05. 15:29
r6s6i6861 x 11,6003,19129.05. 02:15
res1x86_​644 x 11,60014,40028.05. 15:28
rds8x86_​644 x 11,60012,74828.05. 15:26
r4s5saarch​644 x 11,60020029.05. 01:55
r5s3sx86_​644 x 11,60012,74829.05. 02:00
r7s1x86_​644 x 11,60012,84029.05. 02:17
r8s4x86_​644 x 21,60028,80029.05. 02:27
rbs5saarch​644 x 11,6006429.05. 02:47
r1s8i6861 x 21,6006,40029.05. 01:36
r3s6x86_​641 x 21,6606,66429.05. 01:43
r1s6sx86_​642 x 21,66713,33229.05. 01:35
r6s2x86_​642 x 11,6679,57629.05. 02:12
r6s0x86_​642 x 10 x 21,700136,14029.05. 02:12
res0x86_​644 x 21,80031,99228.05. 15:26
r1s7arm​v6l1 x 11,80053029.05. 01:35
rcs7x86_​642 x 21,80014,39629.05. 03:22
rds0x86_​644 x 21,80031,99228.05. 15:22
r4s7i6864 x 11,83314,66429.05. 01:57
r4s7sx86_​642 x 11,8337,33229.05. 01:58
r1s8sx86_​644 x 11,90015,19629.05. 01:37
res8x86_​644 x 11,90015,05228.05. 15:34
res7x86_​644 x 11,90015,05228.05. 15:33
res4x86_​644 x 11,90015,05225.10. 03:17
rds3x86_​644 x 11,91015,32428.05. 15:23
rds4x86_​644 x 11,91015,32428.05. 15:24
rds2x86_​644 x 11,91015,32428.05. 15:23
rds1x86_​644 x 11,91015,32428.05. 15:22
rbs6x86_​644 x 11,91515,32429.05. 02:47
r2s6sx86_​644 x 11,99015,99209.02. 01:27
res3x86_​644 x 12,00015,97228.05. 15:30
r9s1x86_​642 x 12,0003,99229.05. 02:32
r6s1x86_​642 x 12,0007,97829.05. 02:12
r5s3x86_​644 x 22,00031,87229.05. 02:00
r8s2x86_​642 x 22,10016,76029.05. 02:26
r8s2sx86_​642 x 22,10016,76029.05. 02:26
r1s6x86_​642 x 22,13017,06429.05. 01:34
r5s0x86_​642 x 22,20017,58229.05. 01:59
res5sx86_​642 x 22,20019,20028.05. 15:31
res5x86_​642 x 22,20019,20028.05. 15:30
r6s3x86_​644 x 22,20035,12029.05. 02:13
r6s8x86_​642 x 22,30018,35629.05. 02:16
r4s0x86_​642 x 22,30018,39629.05. 01:45
r0s1x86_​644 x 22,30055,99229.05. 01:10
r1s2sx86_​644 x 12,30028,00029.05. 01:33
r1s2x86_​644 x 12,30028,00029.05. 01:32
r7s0x86_​642 x 22,30018,40029.05. 02:16
ras0x86_​642 x 22,30018,41629.05. 02:37
r9s0x86_​642 x 22,30018,40029.05. 02:31
r8s0x86_​642 x 22,30018,40029.05. 02:24
r6s7i6862 x 12,3009,17629.05. 02:15
r7s7sx86_​642 x 22,30018,39629.05. 02:22
r3s1i6864 x 12,40019,12729.05. 01:41
rbs8sx86_​644 x 22,40038,70429.05. 02:50
rcs0x86_​648 x 22,40077,36829.05. 02:52
rbs0i6862 x 22,50017,60029.05. 02:41
r0s0x86_​644 x 22,50039,99229.05. 01:10
r5s4x86_​642 x 22,53020,26429.05. 02:01
r5s4sx86_​642 x 22,53020,26429.05. 02:01
r1s1x86_​642 x 22,60021,69629.05. 01:32
r8s3x86_​644 x 12,66721,27629.05. 02:27
r3s6sx86_​642 x 22,66721,33229.05. 01:43
r9s5x86_​642 x 12,70010,77629.05. 02:34
r5s2x86_​644 x 12,70021,69929.05. 01:59
r8s7x86_​642 x 12,70010,77429.05. 02:30
rcs5x86_​642 x 12,80011,19829.05. 03:20
rcs5sx86_​642 x 12,80011,19829.05. 03:21
rcs2x86_​642 x 12,80011,23229.05. 03:14
r9s6x86_​642 x 23,00023,94429.05. 02:35
r9s3sx86_​644 x 13,00024,00018.04. 14:30
r2s0x86_​644 x 13,10024,79629.05. 01:37
r1s0x86_​644 x 13,10024,79629.05. 01:31
rbs1x86_​644 x 13,10028,80029.05. 02:42
r3s8i6866 x 13,20038,52629.05. 01:45
rbs2x86_​644 x 23,20051,20029.05. 02:42
rcs3sx86_​644 x 23,30052,69629.05. 03:16
r8s7sx86_​642 x 13,30013,24829.05. 02:30
r0s1sx86_​644 x 23,30052,80029.05. 01:11
rcs8sx86_​644 x 23,30052,79228.05. 15:22
r3s3x86_​646 x 23,33379,99229.05. 01:42
r5s1x86_​646 x 13,33340,09229.05. 01:59
r4s6x86_​644 x 23,40054,25629.05. 01:56
r8s5i6864 x 23,40054,39229.05. 02:29
rcs1x86_​646 x 23,46783,37629.05. 03:14
r0s8sx86_​646 x 23,47083,38829.05. 01:31
rcs6x86_​644 x 23,50063,99229.05. 03:21
rbs2sx86_​644 x 23,50055,86429.05. 02:43
r1s3sx86_​644 x 23,50056,00026.05. 01:16
r9s5sx86_​642 x 13,50013,99829.05. 02:35
r1s3x86_​644 x 23,50056,00026.05. 01:16
r0s2x86_​644 x 23,50055,86429.05. 01:11
r0s5x86_​648 x 23,500115,20029.05. 01:19
r3s0i6864 x 23,50056,00029.05. 01:40
r0s3sx86_​644 x 23,60067,20029.05. 01:16
r0s6x86_​648 x 23,600115,20029.05. 01:21
r0s4sx86_​648 x 23,600115,20019.04. 13:19
r0s5sx86_​648 x 23,600115,20029.05. 01:21
r0s4x86_​648 x 23,600115,20029.05. 01:17
r0s7x86_​648 x 23,600115,20029.05. 01:24
r0s8x86_​648 x 23,600115,20029.05. 01:28
r0s3x86_​648 x 23,600115,20029.05. 01:14
r0s6sx86_​6410 x 23,700147,98029.05. 01:23
r0s2sx86_​6410 x 13,70073,99029.05. 01:13
r0s7sx86_​642 x 23,70029,53229.05. 01:26
rcs8x86_​6416 x 23,700217,15228.05. 15:21
r2s7x86_​644 x 13,70029,60010.03. 13:24
r5s2sx86_​644 x 24,00063,86312.04. 01:34
 

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