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2024-05-25 - 09:22

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (by cores) - (x86 CPU strings)

BoxArchCoresMHz ↑Bogo​MIPSEffective
rbs5i6864 x 2049,53925.05. 06:06
r9s1sarm​v7l1 x 101,25014.04. 18:03
r3s2sriscv644 x 1028425.05. 02:32
res6saarch​644 x 101,60025.05. 07:28
r3s5i5861 x 113326525.05. 02:40
r2s1arm​v5tejl1 x 120019925.05. 02:14
r8s1i5861 x 135070125.05. 04:48
r2s5ppc1 x 13966627.03. 13:43
ras7ppc1 x 13966525.05. 05:47
r1s4sarm​v7l2 x 14004825.05. 02:03
r4s8arm​v7l1 x 140039825.05. 03:26
r2s8ppc1 x 14006625.05. 02:26
r4s8sarm​v7l1 x 140039825.05. 03:27
r8s6arm​v7l1 x 150049825.05. 05:02
r4s5arm​v7l1 x 1500025.05. 03:15
r4s3i5861 x 150099625.05. 03:08
ras4arm​v7l1 x 150039825.05. 05:38
r5s7sarm​v7l1 x 15286425.05. 04:00
r5s7arm​v7l1 x 15286425.05. 03:57
r3s7i6861 x 15331,06625.05. 02:49
r5s6ppc1 x 153313325.05. 03:56
r7s4arm​v7l1 x 153634825.05. 04:34
r5s5sarm​v7l1 x 160060025.05. 03:48
r2s3sarm​v7l0 x 1 x 16001,20025.05. 02:17
r5s5arm​v7l1 x 160059725.05. 03:44
ras4sarm​v7l1 x 160059707.02. 02:45
r2s3arm​v7l0 x 1 x 162462425.05. 02:15
rbs8arm​v7l2 x 16662,65025.05. 06:17
rfs6arm​v7l1 x 16671,33225.05. 07:56
rfs6sarm​v7l1 x 16671,33225.05. 07:57
r7s3arm​v6l1 x 1700525.05. 04:27
r2s2arm​v7l1 x 172049925.05. 02:15
rfs4arm​v7l1 x 180080025.05. 07:39
r9s8sarm​v7l1 x 180079625.05. 05:30
r4s2sarm​v7l1 x 180053025.05. 03:03
r4s2arm​v7l1 x 180079625.05. 03:00
rfs4sarm​v7l1 x 180080025.05. 07:47
r2s4mips​641 x 180053124.12. 13:46
rbs7arm​v7l4 x 19962825.05. 06:12
rbs3arm​v7l4 x 19962825.05. 05:56
rbs7sarm​v7l4 x 19962425.05. 06:14
r9s4i6861 x 21,0003,99025.05. 05:16
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
r3s2riscv641 x 11,00028425.05. 02:31
r4s6sarm​v7l0 x 1 x 11,0006625.05. 03:20
ras6sarm​v7l1 x 11,0001,98725.05. 05:46
r7s8arm​v7l1 x 11,00099525.05. 04:42
ras5arm​v7l2 x 11,0002425.05. 05:39
res3saarch​640 x 1 x 11,0001,60025.05. 07:18
r7s6arm​v7l1 x 11,00039828.02. 14:10
ras5sarm​v7l2 x 11,0002425.05. 05:41
res7arm​v7l0 x 1 x 11,0001225.05. 07:31
r7s8sarm​v7l1 x 11,00079625.05. 04:45
r9s7arm​v7l2 x 11,000025.05. 05:28
ras2x86_​642 x 11,0674,26625.05. 05:35
rcs4x86_​642 x 11,1004,37625.05. 06:31
r6s4x86_​642 x 11,1004,37625.05. 04:12
rcs4sx86_​644 x 11,1008,75225.05. 06:33
res6x86_​644 x 11,1008,75225.05. 07:26
r4s4ppc4 x 11,20049825.05. 03:10
r1s5aarch​644 x 11,20079625.05. 02:04
r3s5sppc2 x 11,20040025.05. 02:43
r1s4arm​v7l2 x 11,2004825.05. 02:02
rbs4x86_​644 x 11,2009,60025.05. 06:01
ras3sarm​v7l1 x 11,30084025.05. 05:38
r3s4aarch​646 x 11,3009625.05. 02:34
r7s5i6861 x 11,3002,59325.05. 04:37
r8s8x86_​642 x 11,3005,14425.05. 05:06
rbs6sx86_​642 x 11,3335,33225.05. 06:10
r9s4sx86_​642 x 11,3335,34725.05. 05:22
r2s6saarch​644 x 11,3506425.05. 02:20
rcs3i6862 x 11,4005,58625.05. 06:26
rbs3sarm​v7l4 x 11,40035625.05. 05:57
r7s3sarm​v7l4 x 11,40015225.05. 04:30
ras1i6861 x 11,4002,79925.05. 05:35
r4s3si6861 x 11,4662,93224.05. 15:04
r2s7saarch​644 x 11,50043225.05. 02:24
rfs1aarch​644 x 11,50043225.05. 07:37
rfs2aarch​644 x 11,50043225.05. 07:38
r7s2sarm​v7l4 x 11,50072013.07. 02:16
rcs7sx86_​644 x 11,50011,98025.05. 06:46
r2s6i6861 x 11,5002,99925.05. 02:18
r6s5i6861 x 11,5002,99225.05. 04:15
r7s4sarm​v7l4 x 11,5001,08025.05. 04:36
r4s1sarm​v7l4 x 11,5001,08025.05. 02:56
r4s1arm​v7l4 x 11,5001,08025.05. 02:54
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r8s4sx86_​644 x 21,60028,80025.05. 04:58
r7s7x86_​644 x 11,60012,76725.05. 04:39
res1sx86_​644 x 11,60014,40025.05. 07:13
rds7x86_​644 x 11,60012,74825.05. 07:08
rds5x86_​644 x 11,60012,74825.05. 07:05
ras8x86_​644 x 11,60014,40025.05. 05:48
r9s3x86_​644 x 11,60012,74825.05. 05:12
r9s2x86_​644 x 11,60012,74825.05. 05:11
rds6x86_​644 x 11,60012,74825.05. 07:06
ras8sx86_​644 x 11,60012,74825.05. 05:50
rbs4sx86_​644 x 11,60012,74825.05. 06:03
res2x86_​644 x 11,60014,40025.05. 07:15
r6s6i6861 x 11,6003,19125.05. 04:17
res1x86_​644 x 11,60014,40025.05. 07:12
rds8x86_​644 x 11,60012,74825.05. 07:10
r4s5saarch​644 x 11,60020027.03. 14:13
r5s3sx86_​644 x 11,60012,74825.05. 03:36
r7s1x86_​644 x 11,60012,84025.05. 04:25
r8s4x86_​644 x 21,60028,80025.05. 04:56
rbs5saarch​644 x 11,6006425.05. 06:07
r1s8i6861 x 21,6006,39825.05. 02:09
r3s6x86_​641 x 11,6603,33325.05. 02:44
r1s6sx86_​642 x 21,66713,33225.05. 02:06
r6s2x86_​642 x 11,6679,57825.05. 04:08
r6s0x86_​642 x 10 x 21,700136,18025.05. 04:04
res0x86_​644 x 21,80031,99225.05. 07:10
r1s7arm​v6l1 x 11,80053025.05. 02:08
rcs7x86_​642 x 21,80014,39625.05. 06:44
rds0x86_​644 x 21,80031,99225.05. 06:56
r4s7i6864 x 11,83314,66425.05. 03:23
r4s7sx86_​642 x 11,8337,33225.05. 03:25
r1s8sx86_​644 x 11,90015,19625.05. 02:11
res8sx86_​644 x 11,90015,05225.05. 07:34
res8x86_​644 x 11,90015,05225.05. 07:32
res4sx86_​644 x 11,90015,05225.05. 07:21
res4x86_​644 x 11,90015,05225.05. 07:20
rds3x86_​644 x 11,91015,32425.05. 07:02
rds4x86_​644 x 11,91015,32425.05. 07:03
rds2x86_​644 x 11,91015,32425.05. 07:00
rds1x86_​644 x 11,91015,32425.05. 06:58
rbs6x86_​644 x 11,91515,32425.05. 06:08
rfs0x86_​6416 x 22,000128,00025.05. 07:35
res3x86_​644 x 12,00015,97225.05. 07:16
r9s1x86_​642 x 12,0003,99225.05. 05:09
r6s1x86_​642 x 12,0007,97825.05. 04:05
ras3aarch​648 x 12,0004,00025.05. 05:37
ras6aarch​648 x 12,0003,20020.05. 17:01
r5s3x86_​644 x 22,00031,87225.05. 03:34
rbs2x86_​644 x 12,00015,97225.05. 05:55
rbs1x86_​644 x 12,00015,97225.05. 05:54
r8s2x86_​642 x 22,10016,76025.05. 04:49
r8s2sx86_​642 x 22,10016,76025.05. 04:51
r1s6x86_​642 x 22,13017,06425.05. 02:05
r5s0x86_​642 x 22,20017,58225.05. 03:29
res5sx86_​642 x 22,20019,20025.05. 07:24
res5x86_​642 x 22,20019,20025.05. 07:23
r6s3x86_​644 x 22,20035,12025.05. 04:10
r6s8x86_​642 x 22,30018,35625.05. 04:19
r4s0x86_​642 x 22,30018,39625.05. 02:52
r0s1x86_​644 x 22,30055,99225.05. 01:11
r1s2sx86_​644 x 12,30028,00025.05. 01:59
r1s2x86_​644 x 12,30028,00025.05. 01:56
r7s0x86_​642 x 22,30018,40025.05. 04:23
ras0x86_​642 x 22,30018,41625.05. 05:32
r9s0x86_​642 x 22,30018,40025.05. 05:07
r8s0x86_​642 x 22,30018,40025.05. 04:46
r6s7i6862 x 12,3009,17611.01. 02:44
r7s7sx86_​642 x 22,30018,39625.05. 04:40
r3s1i6864 x 12,40019,12725.05. 02:29
rbs8sx86_​644 x 22,40038,70424.05. 17:46
rcs0x86_​648 x 22,40076,60025.05. 06:20
r2s7aarch​644 x 12,40043225.05. 02:21
rbs0i6862 x 22,50017,60025.05. 05:52
r0s0x86_​644 x 22,50040,00025.05. 01:10
r5s4x86_​642 x 22,53020,26425.05. 03:38
r5s4sx86_​642 x 22,53020,26425.05. 03:40
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s1x86_​642 x 22,60021,69625.05. 01:54
r8s3x86_​644 x 12,66721,28025.05. 04:54
r3s6sx86_​642 x 22,66721,33225.05. 02:46
r9s5x86_​642 x 12,70010,77413.07. 03:15
r5s2x86_​644 x 12,70021,69925.05. 03:32
r8s7x86_​642 x 12,70010,77625.05. 05:02
rcs5x86_​642 x 12,80011,19825.05. 06:36
rcs5sx86_​642 x 12,80011,19825.05. 06:41
rcs2x86_​642 x 12,80011,23225.05. 06:25
r1s3x86_​644 x 12,80022,42425.05. 02:00
r9s6x86_​642 x 23,00023,94425.05. 05:25
r9s3sx86_​644 x 13,00024,00025.05. 05:14
r2s0x86_​644 x 13,10024,80025.05. 02:11
r1s0x86_​644 x 13,10024,80025.05. 01:52
r3s8i6866 x 13,20038,52625.05. 02:50
rcs3sx86_​644 x 23,30052,69625.05. 06:28
r8s7sx86_​642 x 13,30013,19825.05. 05:04
r0s1sx86_​644 x 23,30052,67225.05. 01:13
rcs8sx86_​644 x 23,30052,79225.05. 06:55
r3s3x86_​646 x 23,33379,99224.05. 14:30
r5s1x86_​646 x 13,33340,09225.05. 03:30
r4s6x86_​644 x 23,40054,25625.05. 03:15
r8s5i6864 x 23,40054,40025.05. 05:00
rcs1x86_​646 x 23,46783,37625.05. 06:22
r0s8sx86_​646 x 23,47083,38825.05. 01:50
rcs6x86_​644 x 23,50063,99225.05. 06:42
rbs2sx86_​641 x 13,500007.09. 15:06
r9s5sx86_​642 x 13,50013,99825.05. 05:24
r0s2x86_​644 x 23,50055,86425.05. 01:15
r0s5x86_​648 x 23,500115,20025.05. 01:30
r3s0i6864 x 23,50055,99225.05. 02:27
r0s3sx86_​644 x 23,60067,20025.05. 01:24
r0s6x86_​648 x 23,600115,20025.05. 01:35
r0s4sx86_​648 x 23,600115,20025.05. 01:27
r0s5sx86_​648 x 23,600115,20025.05. 01:31
r0s4x86_​648 x 23,600115,20025.05. 01:25
r0s7x86_​648 x 23,600115,20025.05. 01:41
r0s8x86_​648 x 23,600115,20025.05. 01:48
r0s3x86_​648 x 23,600115,20025.05. 01:19
r0s6sx86_​6410 x 23,700147,98025.05. 01:37
r0s2sx86_​6410 x 13,70073,99025.05. 01:16
r0s7sx86_​642 x 23,70029,52825.05. 01:46
rcs8x86_​6416 x 23,700217,15225.05. 06:53
r5s2sx86_​644 x 24,00063,86312.04. 01:34
 

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