You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-11 - 03:27

Dates and Events:

OSADL Articles:

2024-10-02 12:00

Linux is now an RTOS!

PREEMPT_RT is mainline - What's next?


2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Number of cores/hyperthreads and bogoMIPS (by cores) - (x86 CPU strings)

BoxArchCoresMHz ↑Bogo​MIPSEffective
rbs5i6864 x 2052,36511.06. 03:00
r9s1sarm​v7l1 x 101,25014.04. 18:03
r7s2sriscv644 x 1028406.06. 02:20
r3s2sriscv644 x 1028411.06. 01:36
res6saarch​644 x 101,60010.06. 15:27
r3s5i5861 x 113326511.06. 01:39
r2s1arm​v5tejl1 x 120019911.06. 01:27
r8s1i5861 x 135070111.06. 02:28
r2s5ppc1 x 13966625.12. 13:33
ras7ppc1 x 13966511.06. 02:55
r1s4sarm​v7l2 x 14004811.06. 01:23
r4s8arm​v7l1 x 140039811.06. 01:57
r2s8ppc1 x 14006611.06. 01:33
r4s8sarm​v7l1 x 140039811.06. 01:58
r8s6arm​v7l1 x 150049811.06. 02:33
r4s5arm​v7l1 x 1500011.06. 01:53
r4s3i5861 x 150099611.06. 01:49
r5s7sarm​v7l1 x 15286411.06. 02:11
r5s7arm​v7l1 x 15286411.06. 02:09
r3s7i6861 x 15331,06611.06. 01:42
r5s6ppc1 x 153313311.06. 02:08
r7s4arm​v7l1 x 153634811.06. 02:23
r9s2arm​v7l0 x 1 x 155040011.06. 02:36
r5s5sarm​v7l1 x 160060011.06. 02:06
r2s3sarm​v7l0 x 2 x 16001,20011.06. 01:29
r5s5arm​v7l1 x 160059711.06. 02:04
r2s3arm​v7l0 x 1 x 162462411.06. 01:28
rbs8arm​v7l2 x 16662,65011.06. 03:04
rfs6arm​v7l1 x 16671,33210.06. 15:37
rfs6sarm​v7l1 x 16671,33210.06. 15:38
r7s3arm​v6l1 x 1700511.06. 02:20
rfs7sx86_​644 x 17006,44810.06. 15:39
r2s2arm​v7l1 x 172049911.06. 01:28
r9s8sarm​v7l1 x 180079611.06. 02:50
r4s2sarm​v7l1 x 180053011.06. 01:46
r4s2arm​v7l1 x 180079611.06. 01:45
rfs4sarm​v7l1 x 180080010.06. 15:34
r2s4mips​641 x 180053129.09. 13:34
rbs7arm​v7l4 x 19961211.06. 03:02
rbs3arm​v7l4 x 19962411.06. 02:58
rbs7sarm​v7l4 x 19962410.06. 15:00
r9s4i6861 x 21,0003,99011.06. 02:39
res7sarm​v7l0 x 1 x 11,0001210.06. 15:29
r3s2riscv641 x 11,00028411.06. 01:34
r4s6sarm​v7l0 x 1 x 11,0006611.06. 01:55
ras6sarm​v7l1 x 11,0001,98711.06. 02:55
r7s8arm​v7l1 x 11,00099511.06. 02:26
ras5arm​v7l2 x 11,0002411.06. 02:53
res3saarch​640 x 1 x 11,0001,60010.06. 15:24
ras5sarm​v7l2 x 11,0002411.06. 02:54
res7arm​v7l0 x 1 x 11,0001210.06. 15:28
rfs8arm​v7l1 x 11,00012010.06. 15:40
r7s8sarm​v7l1 x 11,00099611.06. 02:27
r9s7arm​v7l2 x 11,000011.06. 02:49
ras2x86_​642 x 11,0674,26611.06. 02:51
rcs4x86_​642 x 11,1004,37611.06. 03:10
r6s4x86_​642 x 11,1004,37616.04. 14:14
res6x86_​644 x 11,1008,75210.06. 15:27
r4s4ppc4 x 11,20049811.06. 01:50
r1s5aarch​644 x 11,20079611.06. 01:24
r3s5sppc2 x 11,20040011.06. 01:41
r2s5sarm​v7l4 x 11,20015212.12. 01:35
r1s4arm​v7l2 x 11,2004811.06. 01:23
rfs5saarch​644 x 11,2006410.06. 15:37
rbs4x86_​644 x 11,2009,60011.06. 02:59
rfs5aarch​644 x 11,2006410.06. 15:36
ras3sarm​v7l1 x 11,30084011.06. 02:52
r3s4aarch​646 x 11,3009611.06. 01:37
r7s5i6861 x 11,3002,59311.06. 02:24
r8s8x86_​642 x 11,3005,14411.06. 02:35
rbs6sx86_​642 x 11,3335,33229.08. 03:00
r9s4sx86_​642 x 11,3335,34711.06. 02:39
r2s6saarch​644 x 11,3506411.06. 01:31
rfs4aarch​641 x 11,4001,60010.06. 15:33
r8s2aarch​644 x 11,4001,60011.06. 02:29
rcs3i6862 x 11,4005,58611.06. 03:08
rbs3sarm​v7l4 x 11,40035611.06. 02:58
r8s2saarch​644 x 11,4001,60011.06. 02:30
r7s3sarm​v7l4 x 11,40035611.06. 02:22
ras1i6861 x 11,4002,79911.06. 02:51
r4s3si6861 x 11,4662,93228.07. 02:17
r2s7saarch​644 x 11,50043211.06. 01:32
rfs1aarch​644 x 11,50043210.06. 15:31
rfs1saarch​644 x 11,50043210.06. 15:31
rcs7sx86_​644 x 11,50011,98011.06. 03:16
r2s6i6861 x 11,5002,99911.06. 01:30
r6s5i6861 x 11,5002,99211.06. 02:15
r7s4sarm​v7l4 x 11,5001,08011.06. 02:24
r4s1sarm​v7l4 x 11,5001,00811.06. 01:45
r4s1arm​v7l4 x 11,50086411.06. 01:44
rds3x86_​644 x 11,60012,74811.06. 03:22
rds4x86_​644 x 11,60012,74811.06. 03:23
rds2x86_​644 x 11,60012,74811.06. 03:22
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r8s4sx86_​644 x 21,60028,80011.06. 02:31
r7s7x86_​644 x 11,60012,76711.06. 02:25
res1sx86_​644 x 11,60014,40011.06. 03:27
rds7x86_​644 x 11,60012,74811.06. 03:25
rds1x86_​644 x 11,60012,74811.06. 03:21
rds5x86_​644 x 11,60012,74811.06. 03:24
ras8x86_​644 x 11,60014,40011.06. 02:56
r9s3x86_​644 x 11,60012,74811.06. 02:37
rds6x86_​644 x 11,60012,74811.06. 03:24
rfs3x86_​644 x 11,60012,74810.06. 15:32
ras8sx86_​644 x 11,60012,74811.06. 02:56
rbs4sx86_​644 x 11,60012,74811.06. 02:59
res2x86_​644 x 11,60014,40010.06. 15:23
r6s6i6861 x 11,6003,19211.06. 02:16
rfs3sx86_​644 x 11,60012,74810.06. 15:33
res1x86_​644 x 11,60014,40011.06. 03:27
rds8x86_​644 x 11,60012,74811.06. 03:25
r4s5saarch​644 x 11,60020011.06. 01:53
r5s3sx86_​644 x 11,60012,74811.06. 02:01
r7s1x86_​644 x 11,60012,83911.06. 02:18
r8s4x86_​644 x 21,60028,80011.06. 02:31
rbs5saarch​644 x 11,6006411.06. 03:00
r5s4sx86_​644 x 11,60012,74811.06. 02:02
r1s8i6861 x 21,6006,40011.06. 01:26
r3s6x86_​641 x 21,6606,66611.06. 01:41
r1s6sx86_​642 x 21,66713,33211.06. 01:25
r6s2x86_​642 x 11,6679,57811.06. 02:13
r6s0x86_​642 x 10 x 21,700136,14011.06. 02:13
r7s2aarch​642 x 11,7009611.06. 02:19
rcs7x86_​642 x 21,80014,40011.06. 03:15
rds0x86_​644 x 21,80031,99211.06. 03:21
r4s7i6864 x 11,83314,66411.06. 01:56
r4s7sx86_​642 x 11,8337,33211.06. 01:56
r1s8sx86_​644 x 11,90015,19611.06. 01:27
res8sx86_​644 x 11,90015,05210.06. 15:30
ras2sx86_​644 x 11,90015,05211.06. 02:52
res8x86_​644 x 11,90015,05210.06. 15:30
res4sx86_​644 x 11,90015,05210.06. 15:25
res4x86_​644 x 11,90015,05210.06. 15:25
rbs6x86_​644 x 11,91515,32411.06. 03:01
rfs0x86_​6416 x 22,000128,00010.06. 15:31
r5s8x86_​644 x 12,00015,97211.06. 02:12
res3x86_​644 x 12,00015,97210.06. 15:23
r9s1x86_​642 x 12,0007,98412.02. 14:30
r6s1x86_​642 x 12,0007,97812.12. 02:21
ras3aarch​648 x 12,0004,00006.05. 03:01
ras6aarch​648 x 12,0003,20011.06. 02:54
r5s3x86_​644 x 22,00031,87211.06. 02:00
r1s6x86_​642 x 22,13017,06411.06. 01:24
r5s0x86_​642 x 22,20017,58411.06. 01:58
res5sx86_​642 x 22,20019,20010.06. 15:26
res5x86_​642 x 22,20019,20010.06. 15:26
r6s3x86_​644 x 22,20035,12011.06. 02:14
r6s8x86_​642 x 22,30018,35611.06. 02:17
r4s0x86_​642 x 22,30018,39611.06. 01:43
r0s1x86_​644 x 22,30056,00011.06. 01:11
r1s2sx86_​644 x 12,30028,00011.06. 01:21
r1s2x86_​644 x 12,30027,99611.06. 01:21
r7s0x86_​642 x 22,30018,40011.06. 02:18
ras0x86_​642 x 22,30018,41811.06. 02:50
r8s0x86_​642 x 22,30018,40011.06. 02:27
r6s7i6862 x 12,3009,17611.06. 02:16
r7s7sx86_​642 x 22,30018,39611.06. 02:25
r3s1i6864 x 12,40019,12811.06. 01:34
ras4saarch​648 x 12,40038429.09. 03:02
rbs8sx86_​644 x 22,40038,70411.06. 03:05
ras4aarch​648 x 12,40038411.06. 02:52
rcs0x86_​648 x 22,40076,40011.06. 03:06
r2s7aarch​644 x 12,40043230.05. 13:34
rbs0i6862 x 22,50017,60011.06. 02:57
r0s0x86_​644 x 22,50039,99211.06. 01:10
r5s4x86_​642 x 22,53020,26411.06. 02:01
rfs7x86_​644 x 22,60041,60010.06. 15:39
r1s1x86_​642 x 22,60021,69611.06. 01:20
r8s3x86_​644 x 12,66721,28011.06. 02:30
r3s6sx86_​642 x 22,66721,33211.06. 01:42
r5s2x86_​644 x 12,70021,69911.06. 01:59
rcs5x86_​642 x 12,80011,19811.06. 03:12
rcs5sx86_​642 x 12,80011,19811.06. 03:13
rcs2x86_​642 x 12,80011,23211.06. 03:08
r1s3x86_​644 x 12,80022,42411.06. 01:22
r9s6x86_​642 x 23,00023,94409.06. 14:37
rfs2x86_​644 x 13,00024,00010.06. 15:32
rfs2sx86_​642 x 13,00011,99810.06. 15:32
r8s7sx86_​642 x 13,00011,98011.06. 02:34
r9s3sx86_​644 x 13,00024,00011.06. 02:38
r2s0x86_​644 x 13,10024,79628.05. 01:28
r1s0x86_​644 x 13,10024,80011.06. 01:19
r8s7x86_​644 x 13,20025,49611.06. 02:34
rcs3sx86_​644 x 13,30026,39611.06. 03:09
r8s6sx86_​644 x 13,30026,41611.06. 02:33
r9s5sx86_​642 x 13,30013,19811.06. 02:40
r0s1sx86_​644 x 23,30052,80011.06. 01:11
rcs8sx86_​644 x 23,30052,80011.06. 03:20
r3s3x86_​646 x 23,33379,99211.06. 01:36
r5s1x86_​646 x 13,33340,08611.06. 01:59
r0s0sx86_​644 x 23,40054,39211.06. 01:10
r4s6x86_​644 x 23,40054,25611.06. 01:54
r8s5i6864 x 23,40054,40011.06. 02:32
res0x86_​644 x 23,40054,39211.06. 03:26
r1s7arm​v6l1 x 13,40053011.06. 01:26
r3s3sx86_​644 x 13,40011,98011.06. 01:36
rcs1x86_​646 x 23,46783,37611.06. 03:07
r0s8sx86_​646 x 23,47083,38811.06. 01:19
rcs6x86_​644 x 23,50063,99211.06. 03:14
r0s2x86_​644 x 23,50055,87211.06. 01:11
r0s5x86_​648 x 23,500115,20011.06. 01:15
r3s0i6864 x 23,50055,99211.06. 01:33
r0s3sx86_​644 x 23,60067,20011.06. 01:13
r0s6x86_​648 x 23,600115,20011.06. 01:16
r0s4sx86_​648 x 23,600115,20011.06. 01:14
r0s5sx86_​648 x 23,600115,20011.06. 01:16
r0s4x86_​648 x 23,600115,20011.06. 01:14
r9s0x86_​644 x 23,60057,60004.05. 02:36
r0s8x86_​648 x 23,600115,20014.03. 13:20
r0s3x86_​648 x 23,600115,20021.05. 13:12
r0s6sx86_​6410 x 23,700147,98011.06. 01:17
r0s7x86_​6410 x 13,70073,99011.06. 01:18
r0s2sx86_​6410 x 13,70073,99011.06. 01:12
r0s7sx86_​642 x 23,70029,53223.05. 13:21
rcs8x86_​6416 x 23,700217,18411.06. 03:20
r5s2sx86_​644 x 24,00063,86312.04. 01:34
 

Valid XHTML 1.0 Transitional