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2018-02-22 - 02:04

Number of cores/hyperthreads and bogoMIPS (by cores) - (x86 CPU strings)

BoxArchCoresMHzBogo​MIPSEffective
r2s1arm​v5tejl1 x 120019922.02. 01:20
r8s1i5861 x 130060122.02. 01:59
r2s5ppc1 x 13966626.01. 13:22
ras7ppc1 x 13966521.02. 14:20
r5s8ppc1 x 1400263722.02. 01:46
r4s8arm​v7l1 x 140039822.02. 01:36
r2s8ppc1 x 14006622.02. 01:22
r4s8sarm​v7l1 x 140039822.02. 01:36
r8s6arm​v7l1 x 150049822.02. 02:02
r4s5arm​v7l1 x 1500022.02. 01:34
r4s3i5861 x 150099622.02. 01:33
ras4arm​v7l1 x 150039821.02. 14:19
r5s7sarm​v7l1 x 15286422.02. 01:44
r5s7arm​v7l1 x 15286422.02. 01:43
r9s8arm​v7l1 x 152859721.02. 14:17
r3s7i6861 x 1533106622.02. 01:26
r5s6ppc1 x 153313322.02. 01:42
r7s4arm​v7l1 x 153635122.02. 01:54
r5s5sarm​v7l1 x 160060022.02. 01:42
r5s5arm​v7l1 x 160059722.02. 01:40
r2s3arm​v7l1 x 160049522.02. 01:21
r7s2i6861 x 1600119622.02. 01:51
rbs8arm​v7l2 x 1666265021.02. 14:25
r2s2arm​v7l1 x 172049922.02. 01:20
r7s3i6861 x 1800160222.02. 01:53
r4s2sarm​v7l1 x 180047722.02. 01:31
r4s2arm​v7l1 x 180047722.02. 01:29
r2s4mips​641 x 180053122.02. 01:21
rbs3arm​v7l4 x 190015221.02. 14:22
rbs7arm​v7l4 x 19962415.02. 14:23
r9s4i6861 x 21000399021.02. 14:12
ras6sarm​v7l1 x 11000198721.02. 14:20
ras6arm​v7l1 x 11000198721.02. 14:19
r7s8arm​v7l1 x 1100079622.02. 01:58
ras5arm​v7l2 x 110002421.02. 14:19
rbs2i6861 x 11000199921.02. 14:22
r7s6arm​v7l1 x 1100039822.02. 01:55
ras5sarm​v7l2 x 110002421.02. 02:13
r7s8sarm​v7l1 x 1100079622.02. 01:58
r9s7arm​v7l2 x 11000021.02. 14:17
ras2x86_​642 x 11067426621.02. 14:18
rcs4x86_​642 x 11100437821.02. 14:31
r9s1sx86_​642 x 11140399921.02. 14:11
r4s4ppc4 x 1120049822.02. 01:34
rbs3sarm​v7l4 x 1120022821.02. 14:23
r1s5ppc2 x 1120040022.02. 01:18
r7s3sarm​v7l4 x 1120015222.02. 01:53
rbs4x86_​644 x 11200960021.02. 14:24
r4s4sppc1 x 1120049821.01. 17:44
ras3sarm​v7l8 x 1130074421.05. 14:08
r7s5i6861 x 11300259322.02. 01:54
rbs6sx86_​642 x 11333533221.02. 14:25
r9s4sx86_​642 x 11333534721.02. 14:13
rcs3i6862 x 11400558821.02. 14:30
r3s4x86_​641 x 21400560022.02. 01:25
ras1i6861 x 11400279921.02. 14:18
r2s6i6861 x 11500299922.02. 01:21
r6s5i6861 x 11500299322.02. 01:48
r3s2i6861 x 11530306122.02. 01:24
r7s7x86_​644 x 116001276722.02. 01:57
r6s6i6861 x 11600319122.02. 01:49
r4s5saarch​644 x 1160020022.02. 01:34
r5s3sx86_​644 x 116001274822.02. 01:38
r7s1x86_​644 x 116001283922.02. 01:51
r1s8i6861 x 21600639822.02. 01:19
r3s6x86_​641 x 21667666622.02. 01:25
r1s4x86_​642 x 216671333222.02. 01:18
r6s2x86_​642 x 11667958122.02. 01:47
rcs0sx86_​642 x 20 x 2170013612021.02. 14:28
rcs7x86_​642 x 218001439921.02. 14:39
r1s3x86_​641 x 11800359022.02. 01:17
r8s4si6864 x 118331466422.02. 02:01
r4s7i6864 x 118331466422.02. 01:35
r4s7sx86_​642 x 11833733022.02. 01:35
r8s4i6864 x 118331466422.02. 02:01
r8s8i6862 x 11900758722.02. 02:03
rbs6x86_​644 x 119901599220.02. 14:20
rbs5i6862 x 12000799921.02. 14:24
r9s1x86_​642 x 12000399122.02. 02:04
r6s1x86_​642 x 12000797822.02. 01:46
ras3aarch​648 x 12000400021.02. 14:18
r5s3x86_​644 x 220003187922.02. 01:38
r8s2x86_​642 x 221001676022.02. 02:00
r4s1sx86_​642 x 221001673822.02. 01:29
r1s1x86_​642 x 16 x 1210013438422.02. 01:16
r1s6x86_​642 x 221301702022.02. 01:18
r5s0x86_​642 x 222001758322.02. 01:37
r6s4x86_​641 x 12200438922.02. 01:48
r6s3x86_​644 x 222003523622.02. 01:47
r6s8x86_​642 x 223001838222.02. 01:50
r4s0x86_​642 x 223001841822.02. 01:28
r0s1x86_​642 x 223001839622.02. 01:10
r7s0x86_​642 x 223001841722.02. 01:51
ras0x86_​642 x 223001841921.02. 14:17
r9s0x86_​642 x 223001841622.02. 02:04
r8s0x86_​642 x 223001841522.02. 01:59
r6s7i6862 x 12300917622.02. 01:50
r7s7sx86_​642 x 223001844822.02. 01:57
r3s1i6864 x 124001912722.02. 01:23
r1s2x86_​642 x 12400960022.02. 01:17
rcs0x86_​642 x 8 x 224007680021.02. 14:26
ras8i6862 x 125001077421.02. 14:20
r9s3x86_​644 x 225003670521.02. 14:12
rbs0i6862 x 225001995221.02. 14:21
r0s0x86_​644 x 225003999222.02. 01:10
r5s4x86_​642 x 225302026422.02. 01:39
r5s4si6862 x 225302026422.02. 01:39
r0s2x86_​644 x 126672127622.02. 01:11
r3s6sx86_​642 x 226672133222.02. 01:26
rcs8x86_​646 x 226706414021.02. 14:39
r9s2x86_​644 x 227004320021.02. 14:12
r9s5x86_​642 x 127001078021.02. 14:13
r5s2x86_​644 x 127002169922.02. 01:37
r4s1x86_​642 x 227002155322.02. 01:28
r8s7x86_​642 x 127001077822.02. 02:02
rcs5x86_​642 x 128001123221.02. 14:32
rcs5sx86_​642 x 128001123221.02. 14:35
r1s7arm​v6l1 x 1280053022.02. 01:19
rcs2x86_​642 x 128001123321.02. 14:30
ras8sx86_​642 x 129001157221.02. 14:21
r9s6x86_​642 x 230002396721.02. 14:16
r0s7x86_​646 x 230008017222.02. 01:14
r2s0x86_​644 x 131002481422.02. 01:20
r1s0x86_​644 x 131002481422.02. 01:16
rbs1x86_​644 x 131002481421.02. 14:21
r3s8i6866 x 132003852722.02. 01:27
r7s5sx86_​642 x 133001324805.02. 13:54
r8s7sx86_​642 x 133001324822.02. 02:03
r0s1sx86_​644 x 233005280022.02. 01:10
rcs8sx86_​644 x 233005279221.02. 14:40
r5s1i6864 x 233305318522.02. 01:37
r3s3x86_​646 x 233337999222.02. 01:24
r4s6x86_​644 x 234005431722.02. 01:34
r8s5i6864 x 234005440022.02. 02:02
r0s5sx86_​644 x 234005456222.02. 01:13
r9s5sx86_​644 x 234005455321.02. 14:14
rcs1x86_​646 x 234678337621.02. 14:29
r0s8sx86_​646 x 234708337622.02. 01:15
rcs6x86_​644 x 135002793221.02. 14:38
r8s3x86_​644 x 235005586422.02. 02:00
r0s6x86_​644 x 235005590822.02. 01:13
r0s5x86_​644 x 235005587222.02. 01:12
r3s0i6864 x 235005599222.02. 01:23
r6s0x86_​648 x 136005779222.02. 01:46
r0s3x86_​646 x 236008646122.02. 01:11
r0s4x86_​642 x 237002953222.02. 01:12
r2s7x86_​644 x 137002959422.02. 01:22
r5s2sx86_​644 x 240006386312.04. 01:34
r0s8x86_​644 x 240006412822.02. 01:15
 

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