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2018-04-23 - 07:40

Number of cores/hyperthreads and bogoMIPS (by cores) - (x86 CPU strings)

BoxArchCoresMHzBogo​MIPSEffective
r2s1arm​v5tejl1 x 120019923.04. 01:20
r8s1i5861 x 130060123.04. 01:55
r2s5ppc1 x 13966626.01. 13:22
ras7ppc1 x 13966523.04. 02:10
r5s8ppc1 x 1400263723.04. 01:43
r4s8arm​v7l1 x 140039823.04. 01:35
r2s8ppc1 x 14006623.04. 01:22
r4s8sarm​v7l1 x 140039823.04. 01:35
r8s6arm​v7l1 x 150049823.04. 01:58
r4s5arm​v7l1 x 1500023.04. 01:33
r4s3i5861 x 150099623.04. 01:32
ras4arm​v7l1 x 150039823.04. 02:09
r5s7sarm​v7l1 x 15286423.04. 01:42
r5s7arm​v7l1 x 15286423.04. 01:41
r3s7i6861 x 1533106623.04. 01:26
r5s6ppc1 x 153313323.04. 01:40
r7s4arm​v7l1 x 153635123.04. 01:50
r5s5sarm​v7l1 x 160060023.04. 01:39
r5s5arm​v7l1 x 160059723.04. 01:39
r2s3arm​v7l1 x 160049523.04. 01:20
r9s8arm​v7l1 x 160059723.04. 02:06
r9s8sarm​v7l1 x 160059723.04. 02:07
r7s2i6861 x 1600119623.04. 01:48
rbs8arm​v7l2 x 1666265023.04. 02:17
r7s3arm​v6l1 x 1700523.04. 01:49
r2s2arm​v7l1 x 172049923.04. 01:20
r4s2sarm​v7l1 x 180047723.04. 01:30
r4s2arm​v7l1 x 180039823.04. 01:29
r2s4mips​641 x 180053123.04. 01:20
rbs3arm​v7l4 x 190015223.04. 02:13
rbs7arm​v7l4 x 19964823.04. 02:16
rbs7sarm​v7l4 x 1996632423.04. 02:16
r9s4i6861 x 21000399023.04. 02:02
ras6sarm​v7l1 x 11000198723.04. 02:10
ras6arm​v7l1 x 11000198723.04. 02:09
r7s8arm​v7l1 x 1100099623.04. 01:54
ras5arm​v7l2 x 110002423.04. 02:09
rbs2i6861 x 11000199923.04. 02:12
r7s6arm​v7l1 x 1100039823.04. 01:51
ras5sarm​v7l2 x 110002423.04. 02:09
r7s8sarm​v7l1 x 1100079623.04. 01:54
r9s7arm​v7l2 x 11000023.04. 02:06
ras2x86_​642 x 11067426623.04. 02:08
rcs4x86_​642 x 11100437823.04. 02:24
r6s4x86_​642 x 11100437623.04. 01:45
r9s1sx86_​642 x 11140399923.04. 02:01
r4s4ppc4 x 1120049823.04. 01:32
rbs3sarm​v7l4 x 1120022823.04. 02:13
r1s5ppc2 x 1120040023.04. 01:18
r7s3sarm​v7l4 x 1120015223.04. 01:49
rbs4x86_​644 x 11200960023.04. 02:14
r4s4sppc1 x 1120049821.01. 17:44
ras3sarm​v7l8 x 1130074421.05. 14:08
r7s5i6861 x 11300259323.04. 01:50
rbs6sx86_​642 x 11333533223.04. 02:15
r9s4sx86_​642 x 11333534723.04. 02:03
rcs3i6862 x 11400558823.04. 02:21
r3s4x86_​641 x 21400559823.04. 01:24
ras1i6861 x 11400279923.04. 02:08
rcs7sx86_​644 x 115001198023.04. 02:32
r2s6i6861 x 11500299923.04. 01:21
r6s5i6861 x 11500299323.04. 01:45
r3s2i6861 x 11530306123.04. 01:23
r7s7x86_​644 x 116001276723.04. 01:53
ras8sx86_​644 x 116001274823.04. 02:11
r6s6i6861 x 11600319223.04. 01:46
r4s5saarch​644 x 1160020023.04. 01:33
r5s3sx86_​644 x 116001274823.04. 01:37
r7s1x86_​644 x 116001283923.04. 01:47
r1s8i6861 x 21600639823.04. 01:19
r3s6x86_​641 x 21667666623.04. 01:25
r1s4x86_​642 x 216671333223.04. 01:17
r6s2x86_​642 x 11667957623.04. 01:44
r6s0x86_​642 x 20 x 2170013614023.04. 01:43
rcs7x86_​642 x 218001439923.04. 02:32
r1s3x86_​641 x 11800359023.04. 01:17
r8s4si6864 x 118331466423.04. 01:57
r4s7i6864 x 118331466423.04. 01:34
r4s7sx86_​642 x 11833733023.04. 01:34
r8s4i6864 x 118331466423.04. 01:57
r8s8i6862 x 11900758723.04. 01:59
rbs6x86_​644 x 119901597223.04. 02:15
rbs5i6862 x 12000799823.04. 02:14
r9s1x86_​642 x 12000399123.04. 02:00
r6s1x86_​642 x 12000797823.04. 01:44
ras3aarch​648 x 12000400023.04. 02:08
r5s3x86_​644 x 220003187923.04. 01:37
r8s2x86_​642 x 221001676023.04. 01:56
r8s2sx86_​642 x 221001676023.04. 01:56
r4s1sx86_​642 x 221001673823.04. 01:28
r1s1x86_​642 x 16 x 1210013438423.04. 01:16
r1s6x86_​642 x 221301702423.04. 01:18
r5s0x86_​642 x 222001758123.04. 01:35
r6s3x86_​644 x 222003511223.04. 01:44
r6s8x86_​642 x 223001838223.04. 01:47
r4s0x86_​642 x 223001841623.04. 01:27
r0s1x86_​642 x 223001840023.04. 01:10
r7s0x86_​642 x 223001841723.04. 01:47
ras0x86_​642 x 223001841623.04. 02:07
r9s0x86_​642 x 223001841223.04. 02:00
r8s0x86_​642 x 223001841523.04. 01:55
r6s7i6862 x 12300917623.04. 01:46
r7s7sx86_​642 x 223001844823.04. 01:53
r3s1i6862 x 12400960023.04. 01:23
r1s2x86_​642 x 12400959823.04. 01:16
rcs0x86_​642 x 8 x 224007680023.04. 02:17
ras8i6862 x 125001077423.04. 02:10
r9s3x86_​644 x 225003670523.04. 02:02
rbs0i6862 x 225001759623.04. 02:11
r0s0x86_​644 x 225003999223.04. 01:10
r5s4x86_​642 x 225302026423.04. 01:38
r5s4si6862 x 225302026523.04. 01:38
r0s2x86_​644 x 126672127723.04. 01:11
r3s6sx86_​642 x 226672133223.04. 01:25
rcs8x86_​646 x 226706405023.04. 02:33
r9s2x86_​644 x 227004320023.04. 02:01
r9s5x86_​642 x 127001078023.04. 02:03
r5s2x86_​644 x 127002169923.04. 01:36
r4s1x86_​642 x 227002155323.04. 01:27
r8s7x86_​642 x 127001078023.04. 01:58
rcs5x86_​642 x 128001123223.04. 02:24
rcs5sx86_​642 x 128001123223.04. 02:28
r1s7arm​v6l1 x 1280053023.04. 01:18
rcs2x86_​642 x 128001123323.04. 02:20
r9s6x86_​642 x 230002396723.04. 02:06
r0s7x86_​646 x 230008017223.04. 01:13
r2s0x86_​644 x 131002481723.04. 01:19
r1s0x86_​644 x 131002481523.04. 01:15
rbs1x86_​644 x 131002481423.04. 02:11
r3s8i6866 x 132003849823.04. 01:26
rcs3sx86_​644 x 233005269623.04. 02:21
r7s5sx86_​642 x 133001324805.02. 13:54
r8s7sx86_​642 x 133001324823.04. 01:59
r0s1sx86_​644 x 233005280023.04. 01:10
rcs8sx86_​644 x 233005280023.04. 02:34
r5s1i6864 x 233305318523.04. 01:36
r3s3x86_​646 x 233337999223.04. 01:23
r4s6x86_​644 x 234005431623.04. 01:33
r8s5i6864 x 234005439223.04. 01:58
r0s5sx86_​644 x 234005456223.04. 01:12
r9s5sx86_​644 x 234005455423.04. 02:03
rcs1x86_​646 x 234678337623.04. 02:20
r0s8sx86_​646 x 234708338823.04. 01:15
rcs6x86_​644 x 135002793223.04. 02:31
r8s3x86_​644 x 235005586423.04. 01:57
r0s6x86_​644 x 235005587223.04. 01:13
r0s5x86_​644 x 235005586423.04. 01:12
r3s0i6864 x 235005600023.04. 01:22
rcs0sx86_​648 x 136005779223.04. 02:19
r0s3x86_​646 x 236008645923.04. 01:11
r0s4x86_​642 x 237002953223.04. 01:11
r2s7x86_​644 x 137002959423.04. 01:21
r5s2sx86_​644 x 240006386312.04. 01:34
r0s8x86_​644 x 240006412823.04. 01:14
 

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