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2018-06-22 - 05:11

Dates and Events:


Number of cores/hyperthreads and bogoMIPS (by cores) - (x86 CPU strings)

BoxArchCoresMHzBogo​MIPSEffective
r2s1arm​v5tejl1 x 120019922.06. 01:20
r8s1i5861 x 130060122.06. 01:58
r2s5ppc1 x 13966626.01. 13:22
ras7ppc1 x 13966522.06. 02:11
r5s8ppc1 x 1400263722.06. 01:44
r4s8arm​v7l1 x 140039822.06. 01:36
r2s8ppc1 x 14006622.06. 01:22
r4s8sarm​v7l1 x 140039822.06. 01:36
r8s6arm​v7l1 x 150049822.06. 02:01
r4s5arm​v7l1 x 1500022.06. 01:34
r4s3i5861 x 150099622.06. 01:33
ras4arm​v7l1 x 150039822.06. 02:10
r5s7sarm​v7l1 x 15286422.06. 01:43
r5s7arm​v7l1 x 15286422.06. 01:42
r3s7i6861 x 1533106622.06. 01:26
r5s6ppc1 x 153313322.06. 01:42
r7s4arm​v7l1 x 153634822.06. 01:52
r5s5sarm​v7l1 x 160060022.06. 01:41
r5s5arm​v7l1 x 160059722.06. 01:40
r2s3arm​v7l1 x 160049522.06. 01:21
r9s8arm​v7l1 x 160059722.06. 02:08
r9s8sarm​v7l1 x 160059722.06. 02:08
r7s2i6861 x 1600119622.06. 01:49
rbs8arm​v7l2 x 1666265022.06. 02:18
r7s3arm​v6l1 x 1700522.06. 01:51
r2s2arm​v7l1 x 172049922.06. 01:20
r4s2sarm​v7l1 x 180039822.06. 01:31
r4s2arm​v7l1 x 180039822.06. 01:29
r2s4mips​641 x 180053122.06. 01:21
rbs3arm​v7l4 x 190015222.06. 02:14
rbs7arm​v7l4 x 19962422.06. 02:17
rbs7sarm​v7l4 x 1996632422.06. 02:18
r9s4i6861 x 21000399022.06. 02:05
ras6sarm​v7l1 x 11000198722.06. 02:11
ras6arm​v7l1 x 11000198722.06. 02:11
r7s8arm​v7l1 x 1100079622.06. 01:57
ras5arm​v7l2 x 110002422.06. 02:10
rbs2i6861 x 11000199922.06. 02:13
r7s6arm​v7l1 x 1100039822.06. 01:53
ras5sarm​v7l2 x 110002422.06. 02:11
r7s8sarm​v7l1 x 1100079622.06. 01:57
r9s7arm​v7l2 x 11000022.06. 02:08
ras2x86_​642 x 11067426622.06. 02:09
rcs4x86_​642 x 11100437822.06. 02:25
r6s4x86_​642 x 11100437622.06. 01:46
r9s1sx86_​642 x 11140399922.06. 02:04
r4s4ppc4 x 1120049822.06. 01:33
rbs3sarm​v7l4 x 1120022822.06. 02:14
r1s5ppc2 x 1120040022.06. 01:18
r7s3sarm​v7l4 x 1120015222.06. 01:51
rbs4x86_​644 x 11200960022.06. 02:15
r4s4sppc1 x 1120049821.01. 17:44
ras3sarm​v7l8 x 1130074421.05. 14:08
r7s5i6861 x 11300259322.06. 01:53
rbs6sx86_​642 x 11333533222.06. 02:16
r9s4sx86_​642 x 11333534722.06. 02:06
rcs3i6862 x 11400558822.06. 02:22
r3s4x86_​641 x 21400559822.06. 01:25
ras1i6861 x 11400279922.06. 02:09
rcs7sx86_​644 x 115001198022.06. 02:33
r2s6i6861 x 11500299922.06. 01:21
r6s5i6861 x 11500299222.06. 01:46
r3s2i6861 x 11530306122.06. 01:24
r7s7x86_​644 x 116001276722.06. 01:56
ras8sx86_​644 x 116001274822.06. 02:12
r6s6i6861 x 11600319222.06. 01:47
r4s5saarch​644 x 1160020022.06. 01:34
r5s3sx86_​644 x 116001274822.06. 01:38
r7s1x86_​644 x 116001283922.06. 01:49
r1s8i6861 x 21600639822.06. 01:19
r3s6x86_​641 x 21667666622.06. 01:25
r1s4x86_​642 x 216671333222.06. 01:17
r6s2x86_​642 x 11667957622.06. 01:45
r6s0x86_​642 x 20 x 2170013614022.06. 01:44
rcs7x86_​642 x 218001439922.06. 02:33
r1s3x86_​641 x 11800359022.06. 01:17
r8s4si6864 x 118331466422.06. 02:00
r4s7i6864 x 118331466022.06. 01:35
r4s7sx86_​642 x 11833733022.06. 01:35
r8s4i6864 x 118331466422.06. 02:00
r8s8i6862 x 11900758722.06. 02:02
rbs6x86_​644 x 119901599222.06. 02:16
rbs5i6862 x 12000799922.06. 02:16
r9s1x86_​642 x 12000399122.06. 02:03
r6s1x86_​642 x 12000797822.06. 01:45
ras3aarch​648 x 12000400022.06. 02:10
r5s3x86_​644 x 220003187222.06. 01:38
r8s2x86_​642 x 221001676022.06. 01:58
r8s2sx86_​642 x 221001676022.06. 01:59
r4s1sx86_​642 x 221001673822.06. 01:29
r1s1x86_​642 x 16 x 1210013436822.06. 01:16
r1s6x86_​642 x 221301702422.06. 01:18
r5s0x86_​642 x 222001758422.06. 01:37
r6s3x86_​644 x 222003511222.06. 01:45
r6s8x86_​642 x 223001838222.06. 01:48
r4s0x86_​642 x 223001840022.06. 01:28
r0s1x86_​642 x 223001840022.06. 01:10
r7s0x86_​642 x 223001841822.06. 01:48
ras0x86_​642 x 223001841822.06. 02:09
r9s0x86_​642 x 223001841222.06. 02:03
r8s0x86_​642 x 223001841522.06. 01:57
r6s7i6862 x 12300917622.06. 01:48
r7s7sx86_​642 x 223001844822.06. 01:56
r3s1i6862 x 12400960022.06. 01:23
r1s2x86_​642 x 12400959822.06. 01:16
rcs0x86_​642 x 8 x 224007794422.06. 02:19
ras8i6862 x 125001077422.06. 02:12
r9s3x86_​644 x 225003670522.06. 02:04
rbs0i6862 x 225001759622.06. 02:13
r0s0x86_​644 x 225003999222.06. 01:10
r5s4x86_​642 x 225302026422.06. 01:39
r5s4si6862 x 225302026522.06. 01:39
r0s2x86_​644 x 126672127722.06. 01:11
r3s6sx86_​642 x 226672133222.06. 01:26
rcs8x86_​646 x 226706414022.06. 02:34
r9s2x86_​644 x 227004319222.06. 02:04
r9s5x86_​642 x 127001077822.06. 02:06
r5s2x86_​644 x 127002169622.06. 01:37
r4s1x86_​642 x 227002155322.06. 01:28
r8s7x86_​642 x 127001078022.06. 02:01
rcs5x86_​642 x 128001123222.06. 02:26
rcs5sx86_​642 x 128001123222.06. 02:29
r1s7arm​v6l1 x 1280053022.06. 01:19
rcs2x86_​642 x 128001123222.06. 02:21
r9s6x86_​642 x 230002396722.06. 02:07
r0s7x86_​646 x 230008018422.06. 01:13
r9s3sx86_​644 x 130002400022.06. 02:05
r2s0x86_​644 x 131002481722.06. 01:19
r1s0x86_​644 x 131002481522.06. 01:15
rbs1x86_​644 x 131002481422.06. 02:13
r3s8i6866 x 132003849822.06. 01:27
rcs3sx86_​644 x 233005269622.06. 02:22
r7s5sx86_​642 x 133001324805.02. 13:54
r8s7sx86_​642 x 133001324822.06. 02:01
r0s1sx86_​644 x 233005280022.06. 01:10
rcs8sx86_​644 x 233005280022.06. 02:35
r5s1i6864 x 233305318522.06. 01:37
r3s3x86_​646 x 233337999222.06. 01:24
r4s6x86_​644 x 234005431622.06. 01:34
r8s5i6864 x 234005440022.06. 02:01
r0s5sx86_​644 x 234005452822.06. 01:12
r9s5sx86_​644 x 234005455422.06. 02:07
rcs1x86_​646 x 234678337622.06. 02:21
r0s8sx86_​646 x 234708338822.06. 01:15
rcs6x86_​644 x 135002793622.06. 02:32
r8s3x86_​644 x 235005586422.06. 01:59
r0s6x86_​644 x 235005587222.06. 01:13
r0s5x86_​644 x 235005586422.06. 01:12
r3s0i6864 x 235005600022.06. 01:23
rcs0sx86_​648 x 136005779211.05. 14:21
r0s3x86_​646 x 236008647322.06. 01:11
r0s4x86_​642 x 237002953222.06. 01:11
r2s7x86_​644 x 137002960022.06. 01:22
r5s2sx86_​644 x 240006386312.04. 01:34
r0s8x86_​644 x 240006412822.06. 01:14
 

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