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2024-04-25 - 06:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Thu Apr 25, 2024 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
50642810,2sleep275650irq/25-eno1-tx-22:56:552
206952740,0sleep30-21swapper/321:34:413
29862580,0sleep20-21swapper/222:20:262
206132550,0sleep30-21swapper/321:49:463
145932550,0sleep00-21swapper/023:10:110
308812540,0sleep00-21swapper/023:23:530
294312540,2sleep1641799cyclictest22:35:031
259842540,0sleep30-21swapper/323:01:573
244502540,0sleep10-21swapper/100:37:471
198672540,0sleep00-21swapper/023:47:200
313422520,1sleep131339-21sshd22:20:091
210472520,2sleep0641199cyclictest22:40:140
152122520,0sleep30-21swapper/322:12:493
139262520,0sleep30-21swapper/323:49:513
119072500,0sleep30-21swapper/323:40:213
289272490,0sleep1370-21jbd2/sda1-821:23:061
154202490,0sleep00-21swapper/022:54:530
276662480,0sleep10-21swapper/123:26:381
322722460,0sleep00-21swapper/022:11:270
88092450,0sleep0111rcuc/000:01:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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