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2025-04-24 - 14:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Thu Apr 24, 2025 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
166882630,1sleep316693-21crond12:11:593
190512520,0sleep00-21swapper/011:11:020
247282510,2sleep02454499cyclictest11:36:480
19132510,2sleep2321ktimersoftd/209:33:332
2422524925,8sleep70-21swapper/706:59:167
228222490,0sleep20-21swapper/211:27:052
120642490,1sleep52458299cyclictest12:00:165
263722480,0sleep00-21swapper/012:23:420
289012470,1sleep4763-21runrttasks11:44:054
197432470,0sleep519741-21sshd10:44:565
178192470,0sleep40-21swapper/409:48:084
228552460,0sleep60-21swapper/610:39:046
260032450,1sleep449-21ksoftirqd/410:29:414
301012430,0sleep60-21swapper/609:39:456
177512430,0sleep10-21swapper/110:16:081
177512430,0sleep10-21swapper/110:16:081
2435824128,9sleep60-21swapper/607:01:076
2191924129,8sleep40-21swapper/406:57:134
208592410,0sleep10-21swapper/112:01:081
158892410,0sleep30-21swapper/311:26:103
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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