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2024-07-15 - 16:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Mon Jul 15, 2024 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
324752700,0sleep70-21swapper/709:07:397
222702550,2sleep71566799cyclictest11:17:537
1549025227,8sleep40-21swapper/407:05:424
1494425025,8sleep00-21swapper/007:01:450
282612480,0sleep428257-21sshd10:15:434
1532624826,8sleep60-21swapper/607:03:276
195452470,0sleep30-21swapper/312:19:563
70392450,0sleep30-21swapper/310:54:343
39722450,1sleep73969-21sshd10:42:537
259472450,0sleep50-21swapper/510:30:345
217082450,0sleep00-21swapper/010:56:080
176492450,0sleep40-21swapper/409:21:374
71102440,0sleep1241ktimersoftd/112:29:151
290592440,0sleep60-21swapper/609:49:346
290592440,0sleep60-21swapper/609:49:346
295452430,0sleep60-21swapper/612:06:216
242952430,1sleep341-21ksoftirqd/312:13:073
98592420,0sleep50-21swapper/510:58:215
25902420,1sleep09-21ksoftirqd/012:21:290
230812420,0sleep20-21swapper/211:58:322
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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