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2024-04-24 - 05:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot2.osadl.org (updated Wed Apr 24, 2024 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
181692206190,11sleep10-21swapper/119:08:311
182082187171,11sleep00-21swapper/019:09:040
182482186171,11sleep30-21swapper/319:09:343
182522152136,12sleep20-21swapper/219:09:372
198892630,0sleep30-21swapper/321:52:073
235102450,0sleep00-21swapper/023:30:440
209292440,0sleep00-21swapper/023:49:300
288282420,0sleep20-21swapper/221:19:442
57872100,0sleep10-21swapper/123:40:141
56942100,0sleep10-21swapper/122:41:341
118572100,0sleep011859-21grep23:05:140
19224290,0sleep10-21swapper/123:09:531
184829981,6cyclictest0-21swapper/200:25:092
184729981,3cyclictest2823-21munin-run23:00:010
184829971,5cyclictest0-21swapper/223:05:142
184829970,7cyclictest0-21swapper/222:22:402
184729970,3cyclictest1732-21sendmail-msp22:40:010
184879955,0cyclictest21028-21kworker/3:123:54:273
184879955,0cyclictest21028-21kworker/3:122:36:053
184879952,3cyclictest20815-21dump-pmu-power19:15:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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