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2022-06-30 - 21:29

x86 Intel Core i7-E610 @2530 MHz, Linux 4.9.271-rt182 (Profile)

Latency plot of system in rack #5, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a -t3 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rack5slot4.osadl.org (updated Thu Jun 30, 2022 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2591021290,1sleep2301ktimersoftd/207:05:222
20946212161,7sleep00-21swapper/007:05:100
26310210393,7sleep30-21swapper/307:05:563
2650328676,7sleep10-21swapper/107:08:271
42382730,0sleep10-21swapper/109:54:281
153002630,0sleep00-21swapper/007:50:190
116652610,0sleep20-21swapper/210:30:182
297052600,0sleep00-21swapper/008:55:190
20712600,0sleep00-21swapper/007:40:180
284072590,0sleep20-21swapper/209:34:012
254922570,0sleep00-21swapper/012:12:010
278892550,0sleep10-21swapper/108:30:001
304592530,0sleep00-21swapper/009:50:180
233862420,0sleep323394-21kthreadcore09:15:193
249692330,0sleep10-21swapper/110:05:001
2680599301,28cyclictest0-21swapper/207:14:272
2680599280,2cyclictest0-21swapper/207:25:102
2680599280,27cyclictest0-21swapper/210:14:482
2680599280,27cyclictest0-21swapper/209:07:162
2680599280,27cyclictest0-21swapper/208:07:182
2679799280,27cyclictest0-21swapper/010:42:350
26805992723,3cyclictest0-21swapper/209:39:572
26805992723,3cyclictest0-21swapper/209:39:562
26805992723,3cyclictest0-21swapper/207:23:212
2680599270,26cyclictest0-21swapper/211:56:082
2680599270,26cyclictest0-21swapper/211:50:082
2680599270,26cyclictest0-21swapper/208:53:132
2680599260,2cyclictest0-21swapper/208:21:402
2680599260,25cyclictest57-21kswapd010:07:192
2680599260,25cyclictest0-21swapper/210:59:292
2680599260,25cyclictest0-21swapper/209:10:502
2680599260,25cyclictest0-21swapper/208:15:332
2680599260,25cyclictest0-21swapper/208:02:482
2680599260,25cyclictest0-21swapper/207:46:152
2680599260,25cyclictest0-21swapper/207:19:562
26801992622,3cyclictest0-21swapper/108:09:551
2679799260,2cyclictest0-21swapper/012:25:210
2679799260,25cyclictest0-21swapper/010:31:150
2679799260,20cyclictest0-21swapper/008:10:180
26805992522,2cyclictest0-21swapper/212:22:542
26805992521,3cyclictest0-21swapper/212:35:212
2680599250,24cyclictest0-21swapper/212:02:212
2680599250,24cyclictest0-21swapper/210:45:282
26801992521,3cyclictest0-21swapper/110:29:151
2680199250,24cyclictest0-21swapper/112:16:051
2680199250,24cyclictest0-21swapper/109:12:411
26797992512,2cyclictest19402-21kworker/0:011:03:130
2679799251,22cyclictest0-21swapper/010:47:370
2679799250,23cyclictest0-21swapper/009:24:310
2679799250,19cyclictest0-21swapper/011:44:350
2680599243,20cyclictest0-21swapper/211:41:182
26805992422,2cyclictest0-21swapper/208:42:522
26805992422,2cyclictest0-21swapper/208:35:002
2680599241,21cyclictest0-21swapper/207:52:272
2680599240,24cyclictest0-21swapper/209:00:372
2680599240,23cyclictest0-21swapper/210:37:132
2680599240,23cyclictest0-21swapper/209:56:092
2680599240,18cyclictest0-21swapper/210:18:452
2680199247,16cyclictest0-21swapper/110:24:291
2680199242,21cyclictest0-21swapper/110:35:101
2680199240,23cyclictest0-21swapper/112:35:461
2680199240,23cyclictest0-21swapper/112:32:011
2680199240,23cyclictest0-21swapper/109:29:461
2679799242,2cyclictest4758-21basename11:15:000
2679799242,20cyclictest0-21swapper/010:12:510
2679799240,23cyclictest0-21swapper/010:35:090
2679799240,23cyclictest0-21swapper/009:16:180
2679799240,22cyclictest0-21swapper/011:47:590
2679799240,22cyclictest0-21swapper/009:48:100
2679799240,17cyclictest0-21swapper/011:15:190
2680599232,20cyclictest0-21swapper/209:43:002
2680599232,20cyclictest0-21swapper/209:42:592
26805992319,3cyclictest0-21swapper/211:29:232
26805992319,3cyclictest0-21swapper/208:11:162
26805992316,6cyclictest0-21swapper/211:46:262
26805992316,6cyclictest0-21swapper/211:19:002
26805992315,7cyclictest0-21swapper/208:48:082
2680599231,21cyclictest0-21swapper/212:17:512
2680599230,22cyclictest0-21swapper/211:37:102
2680599230,22cyclictest0-21swapper/211:22:142
2680599230,22cyclictest0-21swapper/211:05:522
2680599230,22cyclictest0-21swapper/211:02:282
2680599230,22cyclictest0-21swapper/209:16:332
2680599230,21cyclictest0-21swapper/208:30:102
2680599230,18cyclictest0-21swapper/212:07:302
2680199236,16cyclictest0-21swapper/111:33:471
2680199234,18cyclictest0-21swapper/111:35:021
26801992315,7cyclictest0-21swapper/112:27:541
2680199230,22cyclictest0-21swapper/111:54:111
2680199230,22cyclictest0-21swapper/110:15:471
2680199230,22cyclictest0-21swapper/110:11:021
2680199230,22cyclictest0-21swapper/110:09:261
2680199230,22cyclictest0-21swapper/109:44:531
2680199230,22cyclictest0-21swapper/109:44:531
2680199230,22cyclictest0-21swapper/109:36:131
2680199230,22cyclictest0-21swapper/109:36:121
2680199230,22cyclictest0-21swapper/109:21:211
2680199230,17cyclictest0-21swapper/111:12:121
2680199230,17cyclictest0-21swapper/111:08:201
2680199230,17cyclictest0-21swapper/110:52:521
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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