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2023-01-27 - 15:08

x86 Intel Core i7-E610 @2530 MHz, Linux 4.9.271-rt182 (Profile)

Latency plot of system in rack #5, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a -t3 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rack5slot4.osadl.org (updated Fri Jan 27, 2023 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1482211258,51sleep20-21swapper/207:08:392
15742111101,7sleep00-21swapper/007:09:480
13102110100,7sleep10-21swapper/107:06:241
551210795,7sleep30-21swapper/307:05:233
1617621000,5sleep0176599cyclictest10:40:150
126312730,0sleep00-21swapper/010:52:200
69272660,0sleep20-21swapper/208:30:272
173492610,0sleep10-21swapper/107:45:251
63642590,0sleep10-21swapper/108:30:221
48112590,0sleep20-21swapper/211:05:002
116842590,0sleep30-21swapper/312:37:353
98332580,0sleep00-21swapper/010:20:310
6372580,1sleep30-21swapper/311:31:323
25352580,0sleep10-21swapper/112:34:081
66322570,1sleep20-21swapper/210:05:192
309672570,0sleep30-21swapper/308:00:003
12462570,0sleep00-21swapper/011:32:070
50702560,0sleep30-21swapper/310:04:253
42432540,5sleep1176799cyclictest10:03:381
105752540,0sleep110578-21timerwakeupswit10:50:331
176799331,17cyclictest0-21swapper/108:15:161
1765993013,2cyclictest0-21swapper/011:07:190
309742290,1sleep030981-21kthreadcore09:45:220
176799280,27cyclictest0-21swapper/111:53:191
176799280,27cyclictest0-21swapper/110:42:581
177299271,2cyclictest0-21swapper/209:26:462
177299270,26cyclictest0-21swapper/210:28:592
1767992723,3cyclictest0-21swapper/110:07:331
1767992719,7cyclictest0-21swapper/107:44:341
177299260,25cyclictest0-21swapper/208:14:432
176799261,24cyclictest0-21swapper/111:56:201
176799260,25cyclictest0-21swapper/110:45:401
176799260,25cyclictest0-21swapper/108:03:401
177299250,24cyclictest0-21swapper/212:17:432
177299250,24cyclictest0-21swapper/210:24:042
1767992521,3cyclictest0-21swapper/110:58:371
1767992516,8cyclictest0-21swapper/111:26:531
176799250,24cyclictest0-21swapper/112:29:341
176799250,24cyclictest0-21swapper/112:21:161
176799250,24cyclictest0-21swapper/107:58:431
1765992521,3cyclictest0-21swapper/009:57:300
177299240,23cyclictest0-21swapper/210:11:342
177299240,23cyclictest0-21swapper/209:22:472
177299240,18cyclictest0-21swapper/211:49:402
176799240,23cyclictest0-21swapper/112:01:481
176799240,23cyclictest0-21swapper/111:43:361
176799240,23cyclictest0-21swapper/111:30:291
176799240,23cyclictest0-21swapper/109:54:131
176799240,22cyclictest0-21swapper/111:22:161
176599240,23cyclictest0-21swapper/011:45:540
176599240,23cyclictest0-21swapper/011:38:040
176599240,23cyclictest0-21swapper/010:12:050
176599240,18cyclictest0-21swapper/011:50:240
176599240,18cyclictest0-21swapper/009:43:350
495222318,3sleep30-21swapper/309:34:333
177299232,20cyclictest0-21swapper/211:28:292
177299231,21cyclictest0-21swapper/211:57:442
177299231,21cyclictest0-21swapper/209:43:122
177299231,21cyclictest0-21swapper/209:02:492
177299230,22cyclictest0-21swapper/212:26:202
177299230,22cyclictest0-21swapper/211:13:222
177299230,22cyclictest0-21swapper/210:51:052
177299230,22cyclictest0-21swapper/210:19:292
177299230,22cyclictest0-21swapper/209:49:472
177299230,22cyclictest0-21swapper/208:40:202
176799232,20cyclictest0-21swapper/111:36:441
1767992315,7cyclictest0-21swapper/109:49:241
176799230,22cyclictest0-21swapper/112:17:231
176799230,22cyclictest0-21swapper/112:08:041
176799230,22cyclictest0-21swapper/111:00:591
176799230,22cyclictest0-21swapper/110:32:051
176799230,22cyclictest0-21swapper/110:25:231
176799230,22cyclictest0-21swapper/110:22:251
176799230,22cyclictest0-21swapper/109:42:561
176799230,22cyclictest0-21swapper/109:31:061
176799230,22cyclictest0-21swapper/109:27:331
176799230,22cyclictest0-21swapper/109:12:071
176799230,17cyclictest0-21swapper/112:35:151
176799230,17cyclictest0-21swapper/111:15:331
176799230,17cyclictest0-21swapper/111:11:561
176599232,20cyclictest0-21swapper/011:11:090
176599230,22cyclictest0-21swapper/012:38:440
176599230,22cyclictest0-21swapper/012:09:030
176599230,22cyclictest0-21swapper/011:25:530
176599230,22cyclictest0-21swapper/010:57:000
176599230,22cyclictest0-21swapper/010:02:440
176599230,22cyclictest0-21swapper/009:29:070
176599230,21cyclictest0-21swapper/009:30:180
176599230,17cyclictest0-21swapper/012:21:420
717122218,3sleep30-21swapper/308:31:063
2748422218,3sleep30-21swapper/307:25:543
2550722218,3sleep30-21swapper/308:49:313
177299222,19cyclictest0-21swapper/210:39:262
177299221,20cyclictest0-21swapper/211:05:422
177299221,20cyclictest0-21swapper/209:58:512
177299220,3cyclictest0-21swapper/208:54:232
177299220,21cyclictest0-21swapper/212:39:412
177299220,21cyclictest0-21swapper/212:33:002
177299220,21cyclictest0-21swapper/212:10:172
177299220,21cyclictest0-21swapper/211:50:342
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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