You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-07-10 - 03:19
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jul 09, 2025 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
260021620,6sleep22386999cyclictest09:50:282
219721360,4sleep32387099cyclictest09:50:213
2847191660,4ptp4l0-21swapper/108:55:241
2386999660,26cyclictest3702-21date11:05:012
2847191650,5ptp4l0-21swapper/008:45:190
2847191650,3ptp4l4680-21ntp_states09:55:251
2386999651,30cyclictest26292-21taskset08:25:112
2386999651,30cyclictest15436-21chrt12:39:542
2386999651,30cyclictest12339-21taskset09:03:262
2386999651,25cyclictest11447-21/usr/sbin/munin12:30:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional