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2024-04-20 - 15:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sat Apr 20, 2024 00:46:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1235911750,6ptp4l401ktimersoftd/319:06:253
2288221510,3sleep0106299cyclictest23:20:290
52328911,19sleep00-21swapper/019:07:000
6262785,18sleep10-21swapper/119:08:011
1063997566,5cyclictest25-21ksoftirqd/121:00:111
1063997262,6cyclictest25-21ksoftirqd/100:25:111
123591670,1ptp4l401ktimersoftd/300:35:073
123591660,1ptp4l401ktimersoftd/322:56:553
123591650,1ptp4l401ktimersoftd/320:13:503
116691630,5getstats106599cyclictest22:50:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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