You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-04-26 - 00:44
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Apr 25, 2024 12:46:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1889221510,8sleep11669999cyclictest09:30:181
163862144123,9sleep00-21swapper/007:09:420
1299911210,53ptp4l41-21ksoftirqd/307:07:583
250221170,4sleep21670099cyclictest11:10:332
2478121170,3sleep11669999cyclictest10:50:291
2777321160,7sleep31670199cyclictest08:40:213
16698997938,9cyclictest9-21ksoftirqd/009:35:000
56498740,47rtkit-daemon0-21swapper/107:06:121
16698997332,7cyclictest9-21ksoftirqd/009:05:330
16698997134,6cyclictest9-21ksoftirqd/012:35:000
16698996962,4cyclictest9-21ksoftirqd/011:00:050
1669899695,8cyclictest9-21ksoftirqd/010:15:000
16698996932,5cyclictest9-21ksoftirqd/009:40:320
16698996833,4cyclictest9-21ksoftirqd/008:05:310
16698996733,4cyclictest9-21ksoftirqd/010:50:170
129991670,4ptp4l401ktimersoftd/307:10:013
1669899667,9cyclictest9-21ksoftirqd/012:05:000
16698996659,4cyclictest9-21ksoftirqd/012:20:050
16698996659,4cyclictest9-21ksoftirqd/010:00:050
16698996631,6cyclictest9-21ksoftirqd/007:10:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional