diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2708.dtsi linux/arch/arm/boot/dts/bcm2708.dtsi @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +#define i2c0 i2c0if +#include "bcm2835.dtsi" +#undef i2c0 +#include "bcm270x.dtsi" + +/ { + __overrides__ { + arm_freq; + }; +}; + +&soc { + dma-ranges = <0x80000000 0x00000000 0x20000000>, + <0x7e000000 0x20000000 0x02000000>; +}; + +&vc4 { + status = "disabled"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-b.dts linux/arch/arm/boot/dts/bcm2708-rpi-b.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-b.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2708-rpi-b.dts 2023-12-13 11:50:48.285960534 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; + +#include "bcm2708.dtsi" +#include "bcm2708-rpi.dtsi" +#include "bcm283x-rpi-smsc9512.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" + +/ { + compatible = "raspberrypi,model-b", "brcm,bcm2835"; + model = "Raspberry Pi Model B"; +}; + +&gpio { + /* + * Taken from Raspberry-Pi-Rev-2.0-Model-AB-Schematics.pdf + * RPI00022 sheet 02 + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "CAM_GPIO1", + "LAN_RUN", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "NC", /* GPIO12 */ + "NC", /* GPIO13 */ + /* Serial port */ + "TXD0", + "RXD0", + "STATUS_LED_N", + "GPIO17", + "GPIO18", + "NC", /* GPIO19 */ + "NC", /* GPIO20 */ + "CAM_GPIO0", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "NC", /* GPIO26 */ + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "NC", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "PWM0_OUT", + "NC", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "NC", /* GPIO44 */ + "PWM1_OUT", + "HDMI_HPD_P", + "SD_CARD_DET", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ + }; + + spi0_cs_pins: spi0_cs_pins { + brcm,pins = <8 7>; + brcm,function = <1>; /* output */ + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; + }; + + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; + + i2s_pins: i2s { + brcm,pins = <28 29 30 31>; + brcm,function = <6>; /* alt2 */ + }; + + audio_pins: audio_pins { + brcm,pins = <40 45>; + brcm,function = <4>; + brcm,pull = <0>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "mmc0"; + gpios = <&gpio 16 1>; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +&cam1_reg { + gpio = <&gpio 21 GPIO_ACTIVE_HIGH>; +}; + +cam0_reg: &cam_dummy_reg { +}; + +i2c_arm: &i2c1 { +}; + +i2c_vc: &i2c0 { +}; + +i2c_csi_dsi0: &i2c0 { +}; + +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts linux/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts 2023-12-13 11:50:48.285960534 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; + +#include "bcm2708.dtsi" +#include "bcm2708-rpi.dtsi" +#include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" + +/ { + compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; + model = "Raspberry Pi Model B+"; +}; + +&gpio { + /* + * Taken from Raspberry-Pi-B-Plus-V1.2-Schematics.pdf + * RPI-BPLUS sheet 1 + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "NC", /* GPIO30 */ + "LAN_RUN", /* GPIO31 */ + "CAM_GPIO1", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "PWR_LOW_N", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "USB_LIMIT", /* GPIO38 */ + "NC", /* GPIO39 */ + "PWM0_OUT", /* GPIO40 */ + "CAM_GPIO0", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "ETH_CLK", /* GPIO44 */ + "PWM1_OUT", /* GPIO45 */ + "HDMI_HPD_N", + "STATUS_LED", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ + }; + + spi0_cs_pins: spi0_cs_pins { + brcm,pins = <8 7>; + brcm,function = <1>; /* output */ + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; + }; + + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; + + audio_pins: audio_pins { + brcm,pins = <40 45>; + brcm,function = <4>; + brcm,pull = <0>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "mmc0"; + gpios = <&gpio 47 0>; + }; + + pwr_led: led-pwr { + label = "PWR"; + default-state = "off"; + linux,default-trigger = "input"; + gpios = <&gpio 35 0>; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +&cam1_reg { + gpio = <&gpio 41 GPIO_ACTIVE_HIGH>; +}; + +cam0_reg: &cam_dummy_reg { +}; + +i2c_arm: &i2c1 { +}; + +i2c_vc: &i2c0 { +}; + +i2c_csi_dsi0: &i2c0 { +}; + +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + + pwr_led_gpio = <&pwr_led>,"gpios:4"; + pwr_led_activelow = <&pwr_led>,"gpios:8"; + pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts linux/arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts 2023-12-13 11:50:48.285960534 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; + +#include "bcm2708.dtsi" +#include "bcm2708-rpi.dtsi" +#include "bcm283x-rpi-smsc9512.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" + +/ { + compatible = "raspberrypi,model-b", "brcm,bcm2835"; + model = "Raspberry Pi Model B"; +}; + +&gpio { + /* + * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf + * RPI00021 sheet 02 + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "CAM_GPIO1", + "LAN_RUN", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "NC", /* GPIO12 */ + "NC", /* GPIO13 */ + /* Serial port */ + "TXD0", + "RXD0", + "STATUS_LED_N", + "GPIO17", + "GPIO18", + "NC", /* GPIO19 */ + "NC", /* GPIO20 */ + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "NC", /* GPIO26 */ + "CAM_GPIO0", + /* Binary number representing build/revision */ + "CONFIG0", + "CONFIG1", + "CONFIG2", + "CONFIG3", + "NC", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "PWM0_OUT", + "NC", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "NC", /* GPIO44 */ + "PWM1_OUT", + "HDMI_HPD_P", + "SD_CARD_DET", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ + }; + + spi0_cs_pins: spi0_cs_pins { + brcm,pins = <8 7>; + brcm,function = <1>; /* output */ + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; + }; + + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; + + i2s_pins: i2s { + brcm,pins = <28 29 30 31>; + brcm,function = <6>; /* alt2 */ + }; + + audio_pins: audio_pins { + brcm,pins = <40 45>; + brcm,function = <4>; + brcm,pull = <0>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +/delete-node/ &i2c0mux; + +i2c0: &i2c0if { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; +}; + +i2c_csi_dsi: &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +/ { + aliases { + i2c0 = &i2c0; + }; + + /* Provide an i2c0mux label to avoid undefined symbols in overlays */ + i2c0mux: i2c0mux { + }; + + __overrides__ { + i2c0 = <&i2c0>, "status"; + }; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "mmc0"; + gpios = <&gpio 16 1>; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +&cam1_reg { + gpio = <&gpio 27 GPIO_ACTIVE_HIGH>; +}; + +cam0_reg: &cam_dummy_reg { +}; + +i2c_arm: &i2c0 { +}; + +i2c_vc: &i2c1 { +}; + +i2c_csi_dsi0: &i2c0 { +}; + +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + + i2c = <&i2c0>,"status"; + i2c_arm = <&i2c0>,"status"; + i2c_vc = <&i2c1>,"status"; + i2c_baudrate = <&i2c0>,"clock-frequency:0"; + i2c_arm_baudrate = <&i2c0>,"clock-frequency:0"; + i2c_vc_baudrate = <&i2c1>,"clock-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-bt.dtsi linux/arch/arm/boot/dts/bcm2708-rpi-bt.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-bt.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2708-rpi-bt.dtsi 2023-12-13 11:50:48.285960534 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 + +&uart0 { + bt: bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; + local-bd-address = [ 00 00 00 00 00 00 ]; + fallback-bd-address; // Don't override a valid address + status = "okay"; + }; +}; + +&uart1 { + minibt: bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <230400>; + shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; + local-bd-address = [ 00 00 00 00 00 00 ]; + fallback-bd-address; // Don't override a valid address + status = "disabled"; + }; +}; + +/ { + aliases { + bluetooth = &bt; + }; + + __overrides__ { + bdaddr = <&bt>,"local-bd-address[", + <&bt>,"fallback-bd-address?=0", + <&minibt>,"local-bd-address[", + <&minibt>,"fallback-bd-address?=0"; + krnbt = <&bt>,"status"; + krnbt_baudrate = <&bt>,"max-speed:0", <&minibt>,"max-speed:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-cm.dts linux/arch/arm/boot/dts/bcm2708-rpi-cm.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-cm.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2708-rpi-cm.dts 2023-12-13 11:50:48.286960536 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; + +#include "bcm2708-rpi-cm.dtsi" +#include "bcm283x-rpi-csi0-2lane.dtsi" +#include "bcm283x-rpi-csi1-4lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" + +/ { + compatible = "raspberrypi,compute-module", "brcm,bcm2835"; + model = "Raspberry Pi Compute Module"; +}; + +&cam1_reg { + gpio = <&gpio 3 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +cam0_reg: &cam0_regulator { + gpio = <&gpio 31 GPIO_ACTIVE_HIGH>; +}; + +i2c_csi_dsi0: &i2c0 { +}; + +&uart0 { + status = "okay"; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "GPIO0", + "GPIO1", + "GPIO2", + "GPIO3", + "GPIO4", + "GPIO5", + "GPIO6", + "GPIO7", + "GPIO8", + "GPIO9", + "GPIO10", + "GPIO11", + "GPIO12", + "GPIO13", + "GPIO14", + "GPIO15", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "GPIO32", + "GPIO33", + "GPIO34", + "GPIO35", + "GPIO36", + "GPIO37", + "GPIO38", + "GPIO39", + "GPIO40", + "GPIO41", + "GPIO42", + "GPIO43", + "GPIO44", + "GPIO45", + "HDMI_HPD_N", + /* Also used as ACT LED */ + "EMMC_EN_N", + /* Used by eMMC */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ + }; + + spi0_cs_pins: spi0_cs_pins { + brcm,pins = <8 7>; + brcm,function = <1>; /* output */ + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; + }; + + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; + + audio_pins: audio_pins { + brcm,pins; + brcm,function; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi linux/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi 2023-12-13 11:50:48.286960536 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +#include "bcm2708.dtsi" +#include "bcm2708-rpi.dtsi" + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "mmc0"; + gpios = <&gpio 47 0>; + }; +}; + +i2c_arm: &i2c1 { +}; + +i2c_vc: &i2c0 { +}; + +/ { + __overrides__ { + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + cam0_reg = <&cam0_reg>,"status"; + cam0_reg_gpio = <&cam0_reg>,"gpio:4"; + cam1_reg = <&cam1_reg>,"status"; + cam1_reg_gpio = <&cam1_reg>,"gpio:4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi.dtsi linux/arch/arm/boot/dts/bcm2708-rpi.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2708-rpi.dtsi 2023-12-13 11:50:48.286960536 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* Downstream modifications common to bcm2835, bcm2836, bcm2837 */ + +#define i2c0 i2c0mux +#include "bcm2835-rpi.dtsi" +#undef i2c0 +#include "bcm270x-rpi.dtsi" + +/ { + memory@0 { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + aliases { + i2c2 = &i2c2; + }; + + __overrides__ { + hdmi = <&hdmi>,"status"; + i2c2_iknowwhatimdoing = <&i2c2>,"status"; + i2c2_baudrate = <&i2c2>,"clock-frequency:0"; + sd = <&sdhost>,"status"; + sd_poll_once = <&sdhost>,"non-removable?"; + }; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + status = "okay"; +}; + +&hdmi { + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "disabled"; +}; + +&i2c2 { + status = "disabled"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-zero.dts linux/arch/arm/boot/dts/bcm2708-rpi-zero.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-zero.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2708-rpi-zero.dts 2023-12-13 11:50:48.286960536 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; + +#include "bcm2708.dtsi" +#include "bcm2708-rpi.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" + +/ { + compatible = "raspberrypi,model-zero", "brcm,bcm2835"; + model = "Raspberry Pi Zero"; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "NC", /* GPIO30 */ + "NC", /* GPIO31 */ + "CAM_GPIO1", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "NC", /* GPIO40 */ + "CAM_GPIO0", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "NC", /* GPIO44 */ + "NC", /* GPIO45 */ + "HDMI_HPD_N", + "STATUS_LED_N", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ + }; + + spi0_cs_pins: spi0_cs_pins { + brcm,pins = <8 7>; + brcm,function = <1>; /* output */ + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; + }; + + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; + + audio_pins: audio_pins { + brcm,pins = <>; + brcm,function = <>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "actpwr"; + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +&cam1_reg { + gpio = <&gpio 41 GPIO_ACTIVE_HIGH>; +}; + +cam0_reg: &cam_dummy_reg { +}; + +i2c_arm: &i2c1 {}; +i2c_vc: &i2c0 {}; +i2c_csi_dsi0: &i2c0 {}; + +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts linux/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts 2023-12-13 11:50:48.286960536 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; + +#include "bcm2708.dtsi" +#include "bcm2708-rpi.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" +#include "bcm2708-rpi-bt.dtsi" + +/ { + compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; + model = "Raspberry Pi Zero W"; + + chosen { + bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_headphones=0"; + }; + + aliases { + serial0 = &uart1; + serial1 = &uart0; + mmc1 = &mmcnr; + }; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "CAM_GPIO1", /* GPIO40 */ + "WL_ON", /* GPIO41 */ + "NC", /* GPIO42 */ + "WIFI_CLK", /* GPIO43 */ + "CAM_GPIO0", /* GPIO44 */ + "BT_ON", /* GPIO45 */ + "HDMI_HPD_N", + "STATUS_LED_N", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ + }; + + spi0_cs_pins: spi0_cs_pins { + brcm,pins = <8 7>; + brcm,function = <1>; /* output */ + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; + }; + + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; + + sdio_pins: sdio_pins { + brcm,pins = <34 35 36 37 38 39>; + brcm,function = <7>; /* ALT3 = SD1 */ + brcm,pull = <0 2 2 2 2 2>; + }; + + bt_pins: bt_pins { + brcm,pins = <43>; + brcm,function = <4>; /* alt0:GPCLK2 */ + brcm,pull = <0>; /* none */ + }; + + uart0_pins: uart0_pins { + brcm,pins = <30 31 32 33>; + brcm,function = <7>; /* alt3=UART0 */ + brcm,pull = <2 0 0 2>; /* up none none up */ + }; + + uart1_pins: uart1_pins { + brcm,pins; + brcm,function; + brcm,pull; + }; + + uart1_bt_pins: uart1_bt_pins { + brcm,pins = <32 33 30 31>; + brcm,function = <BCM2835_FSEL_ALT5>; /* alt5=UART1 */ + brcm,pull = <0 2 2 0>; + }; + + audio_pins: audio_pins { + brcm,pins = <>; + brcm,function = <>; + }; +}; + +&mmcnr { + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pins>; + bus-width = <4>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins &bt_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "actpwr"; + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +&cam1_reg { + gpio = <&gpio 44 GPIO_ACTIVE_HIGH>; +}; + +cam0_reg: &cam_dummy_reg { +}; + +i2c_arm: &i2c1 {}; +i2c_vc: &i2c0 {}; +i2c_csi_dsi0: &i2c0 {}; + +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2709.dtsi linux/arch/arm/boot/dts/bcm2709.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm2709.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2709.dtsi 2023-12-13 11:50:48.287960538 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +#define i2c0 i2c0if +#include "bcm2836.dtsi" +#undef i2c0 +#include "bcm270x.dtsi" + +/ { + soc { + ranges = <0x7e000000 0x3f000000 0x01000000>, + <0x40000000 0x40000000 0x00040000>; + + dma-ranges = <0xc0000000 0x00000000 0x3f000000>, + <0x7e000000 0x3f000000 0x01000000>; + }; + + __overrides__ { + arm_freq = <&v7_cpu0>, "clock-frequency:0", + <&v7_cpu1>, "clock-frequency:0", + <&v7_cpu2>, "clock-frequency:0", + <&v7_cpu3>, "clock-frequency:0"; + }; +}; + +&system_timer { + status = "disabled"; +}; + +&vc4 { + status = "disabled"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2709-rpi-2-b.dts linux/arch/arm/boot/dts/bcm2709-rpi-2-b.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2709-rpi-2-b.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2709-rpi-2-b.dts 2023-12-13 11:50:48.287960538 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; + +#include "bcm2709.dtsi" +#include "bcm2709-rpi.dtsi" +#include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" + +/ { + compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; + model = "Raspberry Pi 2 Model B"; +}; + +&gpio { + /* + * Taken from rpi_SCH_2b_1p2_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "NC", /* GPIO30 */ + "LAN_RUN", + "CAM_GPIO1", + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "PWR_LOW_N", + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "USB_LIMIT", + "NC", /* GPIO39 */ + "PWM0_OUT", + "CAM_GPIO0", + "SMPS_SCL", + "SMPS_SDA", + "ETH_CLK", + "PWM1_OUT", + "HDMI_HPD_N", + "STATUS_LED", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ + }; + + spi0_cs_pins: spi0_cs_pins { + brcm,pins = <8 7>; + brcm,function = <1>; /* output */ + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; + }; + + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; + + audio_pins: audio_pins { + brcm,pins = <40 45>; + brcm,function = <4>; + brcm,pull = <0>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "mmc0"; + gpios = <&gpio 47 0>; + }; + + pwr_led: led-pwr { + label = "PWR"; + default-state = "off"; + linux,default-trigger = "input"; + gpios = <&gpio 35 0>; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +&cam1_reg { + gpio = <&gpio 41 GPIO_ACTIVE_HIGH>; +}; + +cam0_reg: &cam_dummy_reg { +}; + +i2c_csi_dsi0: &i2c0 { +}; + +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + + pwr_led_gpio = <&pwr_led>,"gpios:4"; + pwr_led_activelow = <&pwr_led>,"gpios:8"; + pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2709-rpi-cm2.dts linux/arch/arm/boot/dts/bcm2709-rpi-cm2.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2709-rpi-cm2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2709-rpi-cm2.dts 2023-12-13 11:50:48.287960538 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; + +#include "bcm2709.dtsi" +#include "bcm2709-rpi.dtsi" +#include "bcm283x-rpi-csi0-2lane.dtsi" +#include "bcm283x-rpi-csi1-4lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" + +/ { + compatible = "raspberrypi,2-compute-module", "brcm,bcm2836"; + model = "Raspberry Pi Compute Module 2"; +}; + +&cam1_reg { + gpio = <&gpio 2 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +cam0_reg: &cam0_regulator { + gpio = <&gpio 30 GPIO_ACTIVE_HIGH>; +}; + +i2c_csi_dsi0: &i2c0 { +}; + +&uart0 { + status = "okay"; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "GPIO0", + "GPIO1", + "GPIO2", + "GPIO3", + "GPIO4", + "GPIO5", + "GPIO6", + "GPIO7", + "GPIO8", + "GPIO9", + "GPIO10", + "GPIO11", + "GPIO12", + "GPIO13", + "GPIO14", + "GPIO15", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "GPIO32", + "GPIO33", + "GPIO34", + "GPIO35", + "GPIO36", + "GPIO37", + "GPIO38", + "GPIO39", + "GPIO40", + "GPIO41", + "GPIO42", + "GPIO43", + "GPIO44", + "GPIO45", + "SMPS_SCL", + "SMPS_SDA", + /* Used by eMMC */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ + }; + + spi0_cs_pins: spi0_cs_pins { + brcm,pins = <8 7>; + brcm,function = <1>; /* output */ + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; + }; + + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; + + audio_pins: audio_pins { + brcm,pins; + brcm,function; + }; +}; + +&soc { + virtgpio: virtgpio { + compatible = "brcm,bcm2835-virtgpio"; + gpio-controller; + #gpio-cells = <2>; + firmware = <&firmware>; + status = "okay"; + }; + +}; + +&firmware { + expgpio: expgpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "HDMI_HPD_N", + "EMMC_EN_N", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; + status = "okay"; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "mmc0"; + gpios = <&virtgpio 0 0>; + }; +}; + +&hdmi { + hpd-gpios = <&expgpio 0 GPIO_ACTIVE_LOW>; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + cam0_reg = <&cam0_reg>,"status"; + cam0_reg_gpio = <&cam0_reg>,"gpio:4"; + cam1_reg = <&cam1_reg>,"status"; + cam1_reg_gpio = <&cam1_reg>,"gpio:4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2709-rpi.dtsi linux/arch/arm/boot/dts/bcm2709-rpi.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm2709-rpi.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2709-rpi.dtsi 2023-12-13 11:50:48.287960538 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +#include "bcm2708-rpi.dtsi" + +&vchiq { + compatible = "brcm,bcm2836-vchiq", "brcm,bcm2835-vchiq"; +}; + +i2c_arm: &i2c1 {}; +i2c_vc: &i2c0 {}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm270x.dtsi linux/arch/arm/boot/dts/bcm270x.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm270x.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm270x.dtsi 2023-12-13 11:50:48.287960538 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* Downstream bcm283x.dtsi diff */ +#include <dt-bindings/power/raspberrypi-power.h> + +/ { + chosen: chosen { + // Disable audio by default + bootargs = "coherent_pool=1M snd_bcm2835.enable_headphones=0"; + stdout-path = "serial0:115200n8"; + }; + + soc: soc { + watchdog: watchdog@7e100000 { + /* Add label */ + }; + + random: rng@7e104000 { + /* Add label */ + }; + + spi0: spi@7e204000 { + /* Add label */ + }; + +#ifndef BCM2711 + pixelvalve0: pixelvalve@7e206000 { + /* Add label */ + status = "disabled"; + }; + + pixelvalve1: pixelvalve@7e207000 { + /* Add label */ + status = "disabled"; + }; +#endif + + /delete-node/ mmc@7e300000; + + sdhci: mmc: mmc@7e300000 { + compatible = "brcm,bcm2835-mmc", "brcm,bcm2835-sdhci"; + reg = <0x7e300000 0x100>; + interrupts = <2 30>; + clocks = <&clocks BCM2835_CLOCK_EMMC>; + dmas = <&dma 11>; + dma-names = "rx-tx"; + brcm,overclock-50 = <0>; + status = "disabled"; + }; + + /* A clone of mmc but with non-removable set */ + mmcnr: mmcnr@7e300000 { + compatible = "brcm,bcm2835-mmc", "brcm,bcm2835-sdhci"; + reg = <0x7e300000 0x100>; + interrupts = <2 30>; + clocks = <&clocks BCM2835_CLOCK_EMMC>; + dmas = <&dma 11>; + dma-names = "rx-tx"; + brcm,overclock-50 = <0>; + non-removable; + status = "disabled"; + }; + + hvs: hvs@7e400000 { + /* Add label */ + status = "disabled"; + }; + + firmwarekms: firmwarekms@7e600000 { + compatible = "raspberrypi,rpi-firmware-kms"; + /* SMI interrupt reg */ + reg = <0x7e600000 0x100>; + interrupts = <2 16>; + brcm,firmware = <&firmware>; + status = "disabled"; + }; + + smi: smi@7e600000 { + compatible = "brcm,bcm2835-smi"; + reg = <0x7e600000 0x100>; + interrupts = <2 16>; + clocks = <&clocks BCM2835_CLOCK_SMI>; + assigned-clocks = <&clocks BCM2835_CLOCK_SMI>; + assigned-clock-rates = <125000000>; + dmas = <&dma 4>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + csi0: csi@7e800000 { + compatible = "brcm,bcm2835-unicam"; + reg = <0x7e800000 0x800>, + <0x7e802000 0x4>; + interrupts = <2 6>; + clocks = <&clocks BCM2835_CLOCK_CAM0>, + <&firmware_clocks 4>; + clock-names = "lp", "vpu"; + power-domains = <&power RPI_POWER_DOMAIN_UNICAM0>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + status = "disabled"; + }; + + csi1: csi@7e801000 { + compatible = "brcm,bcm2835-unicam"; + reg = <0x7e801000 0x800>, + <0x7e802004 0x4>; + interrupts = <2 7>; + clocks = <&clocks BCM2835_CLOCK_CAM1>, + <&firmware_clocks 4>; + clock-names = "lp", "vpu"; + power-domains = <&power RPI_POWER_DOMAIN_UNICAM1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + status = "disabled"; + }; + +#ifndef BCM2711 + pixelvalve2: pixelvalve@7e807000 { + /* Add label */ + status = "disabled"; + }; +#endif + + hdmi@7e902000 { /* hdmi */ + status = "disabled"; + }; + + usb@7e980000 { /* usb */ + compatible = "brcm,bcm2708-usb"; + reg = <0x7e980000 0x10000>, + <0x7e006000 0x1000>; + interrupt-names = "usb", + "soft"; + interrupts = <1 9>, + <2 0>; + }; + +#ifndef BCM2711 + v3d@7ec00000 { /* vd3 */ + compatible = "brcm,vc4-v3d"; + power-domains = <&power RPI_POWER_DOMAIN_V3D>; + status = "disabled"; + }; +#endif + + axiperf: axiperf { + compatible = "brcm,bcm2835-axiperf"; + reg = <0x7e009800 0x100>, + <0x7ee08000 0x100>; + firmware = <&firmware>; + status = "disabled"; + }; + + i2c0mux: i2c0mux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&i2c0if>; + + status = "disabled"; + + i2c0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_csi_dsi: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + cam1_reg: cam1_regulator { + compatible = "regulator-fixed"; + regulator-name = "cam1-reg"; + enable-active-high; + /* Needs to be enabled, as removing a regulator is very unsafe */ + status = "okay"; + }; + + cam1_clk: cam1_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + status = "disabled"; + }; + + cam0_regulator: cam0_regulator { + compatible = "regulator-fixed"; + regulator-name = "cam0-reg"; + enable-active-high; + status = "disabled"; + }; + + cam0_clk: cam0_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + status = "disabled"; + }; + + cam_dummy_reg: cam_dummy_reg { + compatible = "regulator-fixed"; + regulator-name = "cam-dummy-reg"; + status = "okay"; + }; + + __overrides__ { + cam0-pwdn-ctrl; + cam0-pwdn; + cam0-led-ctrl; + cam0-led; + }; +}; + +&gpio { + interrupts = <2 17>, <2 18>; + + dpi_18bit_cpadhi_gpio0: dpi_18bit_cpadhi_gpio0 { + brcm,pins = <0 1 2 3 4 5 6 7 8 9 + 12 13 14 15 16 17 + 20 21 22 23 24 25>; + brcm,function = <BCM2835_FSEL_ALT2>; + brcm,pull = <0>; /* no pull */ + }; + dpi_18bit_cpadhi_gpio2: dpi_18bit_cpadhi_gpio2 { + brcm,pins = <2 3 4 5 6 7 8 9 + 12 13 14 15 16 17 + 20 21 22 23 24 25>; + brcm,function = <BCM2835_FSEL_ALT2>; + }; + dpi_18bit_gpio0: dpi_18bit_gpio0 { + brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 + 12 13 14 15 16 17 18 19 + 20 21>; + brcm,function = <BCM2835_FSEL_ALT2>; + }; + dpi_18bit_gpio2: dpi_18bit_gpio2 { + brcm,pins = <2 3 4 5 6 7 8 9 10 11 + 12 13 14 15 16 17 18 19 + 20 21>; + brcm,function = <BCM2835_FSEL_ALT2>; + }; + dpi_16bit_gpio0: dpi_16bit_gpio0 { + brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 + 12 13 14 15 16 17 18 19>; + brcm,function = <BCM2835_FSEL_ALT2>; + }; + dpi_16bit_gpio2: dpi_16bit_gpio2 { + brcm,pins = <2 3 4 5 6 7 8 9 10 11 + 12 13 14 15 16 17 18 19>; + brcm,function = <BCM2835_FSEL_ALT2>; + }; + dpi_16bit_cpadhi_gpio0: dpi_16bit_cpadhi_gpio0 { + brcm,pins = <0 1 2 3 4 5 6 7 8 + 12 13 14 15 16 17 + 20 21 22 23 24>; + brcm,function = <BCM2835_FSEL_ALT2>; + }; + dpi_16bit_cpadhi_gpio2: dpi_16bit_cpadhi_gpio2 { + brcm,pins = <2 3 4 5 6 7 8 + 12 13 14 15 16 17 + 20 21 22 23 24>; + brcm,function = <BCM2835_FSEL_ALT2>; + }; +}; + +&uart0 { + /* Enable CTS bug workaround */ + cts-event-workaround; +}; + +&i2s { + #sound-dai-cells = <0>; + dmas = <&dma 2>, <&dma 3>; + dma-names = "tx", "rx"; +}; + +&sdhost { + dmas = <&dma (13|(1<<29))>; + dma-names = "rx-tx"; + bus-width = <4>; + brcm,overclock-50 = <0>; + brcm,pio-limit = <1>; + firmware = <&firmware>; +}; + +&spi0 { + dmas = <&dma 6>, <&dma 7>; + dma-names = "tx", "rx"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm270x-rpi.dtsi linux/arch/arm/boot/dts/bcm270x-rpi.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm270x-rpi.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm270x-rpi.dtsi 2023-12-13 11:50:48.287960538 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* Downstream modifications to bcm2835-rpi.dtsi */ + +/ { + aliases: aliases { + aux = &aux; + sound = &sound; + soc = &soc; + dma = &dma; + intc = &intc; + watchdog = &watchdog; + random = &random; + mailbox = &mailbox; + gpio = &gpio; + uart0 = &uart0; + uart1 = &uart1; + sdhost = &sdhost; + mmc = &mmc; + mmc1 = &mmc; + mmc0 = &sdhost; + i2s = &i2s; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c10 = &i2c_csi_dsi; + i2c = &i2c_arm; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + usb = &usb; + leds = &leds; + fb = &fb; + thermal = &thermal; + axiperf = &axiperf; + }; + + /* Define these notional regulators for use by overlays */ + vdd_3v3_reg: fixedregulator_3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3"; + }; + + vdd_5v0_reg: fixedregulator_5v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "5v0"; + }; + + leds: leds { + compatible = "gpio-leds"; + }; + + soc { + gpiomem { + compatible = "brcm,bcm2835-gpiomem"; + reg = <0x7e200000 0x1000>; + }; + + fb: fb { + compatible = "brcm,bcm2708-fb"; + firmware = <&firmware>; + status = "okay"; + }; + + /* External sound card */ + sound: sound { + status = "disabled"; + }; + }; + + __overrides__ { + cache_line_size; + + uart0 = <&uart0>,"status"; + uart1 = <&uart1>,"status"; + i2s = <&i2s>,"status"; + spi = <&spi0>,"status"; + i2c0 = <&i2c0if>,"status",<&i2c0mux>,"status"; + i2c1 = <&i2c1>,"status"; + i2c = <&i2c1>,"status"; + i2c_arm = <&i2c1>,"status"; + i2c_vc = <&i2c0if>,"status",<&i2c0mux>,"status"; + i2c0_baudrate = <&i2c0if>,"clock-frequency:0"; + i2c1_baudrate = <&i2c1>,"clock-frequency:0"; + i2c_baudrate = <&i2c1>,"clock-frequency:0"; + i2c_arm_baudrate = <&i2c1>,"clock-frequency:0"; + i2c_vc_baudrate = <&i2c0if>,"clock-frequency:0"; + + watchdog = <&watchdog>,"status"; + random = <&random>,"status"; + sd_overclock = <&sdhost>,"brcm,overclock-50:0"; + sd_force_pio = <&sdhost>,"brcm,force-pio?"; + sd_pio_limit = <&sdhost>,"brcm,pio-limit:0"; + sd_debug = <&sdhost>,"brcm,debug"; + sdio_overclock = <&mmc>,"brcm,overclock-50:0", + <&mmcnr>,"brcm,overclock-50:0"; + axiperf = <&axiperf>,"status"; + drm_fb0_vc4 = <&aliases>, "drm-fb0=",&vc4; + drm_fb1_vc4 = <&aliases>, "drm-fb1=",&vc4; + drm_fb2_vc4 = <&aliases>, "drm-fb2=",&vc4; + }; +}; + +&uart0 { + skip-init; +}; + +&uart1 { + skip-init; +}; + +&txp { + status = "disabled"; +}; + +&i2c0if { + status = "disabled"; +}; + +&i2c0mux { + pinctrl-names = "i2c0", "i2c_csi_dsi"; + /delete-property/ clock-frequency; + status = "disabled"; +}; + +&i2c1 { + status = "disabled"; +}; + +i2s_clk_producer: &i2s {}; +i2s_clk_consumer: &i2s {}; + +&clocks { + firmware = <&firmware>; +}; + +&sdhci { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_gpio48>; + bus-width = <4>; +}; + +&cpu_thermal { + // Add some labels + thermal_trips: trips { + cpu-crit { + // Raise upstream limit of 90C + temperature = <110000>; + }; + }; + cooling_maps: cooling-maps { + }; +}; + +&vec { + clocks = <&firmware_clocks 15>; + status = "disabled"; +}; + +&firmware { +#ifndef BCM2711 + firmware_clocks: clocks { + compatible = "raspberrypi,firmware-clocks"; + #clock-cells = <1>; + }; +#endif + + vcio: vcio { + compatible = "raspberrypi,vcio"; + }; +}; + +&vc4 { + raspberrypi,firmware = <&firmware>; +}; + +#ifndef BCM2711 + +&hdmi { + reg-names = "hdmi", + "hd"; + clocks = <&firmware_clocks 9>, + <&firmware_clocks 13>; + dmas = <&dma (17|(1<<27)|(1<<24))>; +}; + +#endif diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2710.dtsi linux/arch/arm/boot/dts/bcm2710.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm2710.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2710.dtsi 2023-12-13 11:50:48.288960541 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +#define i2c0 i2c0if +#include "bcm2837.dtsi" +#undef i2c0 +#include "bcm270x.dtsi" + +/ { + compatible = "brcm,bcm2837", "brcm,bcm2836"; + + arm-pmu { + compatible = "arm,cortex-a53-pmu", "arm,cortex-a7-pmu"; + }; + + soc { + dma-ranges = <0xc0000000 0x00000000 0x3f000000>, + <0x7e000000 0x3f000000 0x01000000>; + }; + + __overrides__ { + arm_freq = <&cpu0>, "clock-frequency:0", + <&cpu1>, "clock-frequency:0", + <&cpu2>, "clock-frequency:0", + <&cpu3>, "clock-frequency:0"; + }; +}; + +&system_timer { + status = "disabled"; +}; + +&vc4 { + status = "disabled"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2710-rpi-2-b.dts linux/arch/arm/boot/dts/bcm2710-rpi-2-b.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2710-rpi-2-b.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2710-rpi-2-b.dts 2023-12-13 11:50:48.287960538 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; + +#include "bcm2710.dtsi" +#include "bcm2709-rpi.dtsi" +#include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" + +/ { + compatible = "raspberrypi,2-model-b-rev2", "brcm,bcm2837"; + model = "Raspberry Pi 2 Model B rev 1.2"; +}; + +&gpio { + /* + * Taken from rpi_SCH_2b_1p2_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "NC", /* GPIO30 */ + "LAN_RUN", + "CAM_GPIO1", + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "PWR_LOW_N", + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "USB_LIMIT", + "NC", /* GPIO39 */ + "PWM0_OUT", + "CAM_GPIO0", + "SMPS_SCL", + "SMPS_SDA", + "ETH_CLK", + "PWM1_OUT", + "HDMI_HPD_N", + "STATUS_LED", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ + }; + + spi0_cs_pins: spi0_cs_pins { + brcm,pins = <8 7>; + brcm,function = <1>; /* output */ + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; + }; + + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; + + audio_pins: audio_pins { + brcm,pins = <40 45>; + brcm,function = <4>; + brcm,pull = <0>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "mmc0"; + gpios = <&gpio 47 0>; + }; + + pwr_led: led-pwr { + label = "PWR"; + default-state = "off"; + linux,default-trigger = "input"; + gpios = <&gpio 35 0>; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +&cam1_reg { + gpio = <&gpio 41 GPIO_ACTIVE_HIGH>; +}; + +cam0_reg: &cam_dummy_reg { +}; + +i2c_csi_dsi0: &i2c0 { +}; + +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + + pwr_led_gpio = <&pwr_led>,"gpios:4"; + pwr_led_activelow = <&pwr_led>,"gpios:8"; + pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2710-rpi-3-b.dts linux/arch/arm/boot/dts/bcm2710-rpi-3-b.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2710-rpi-3-b.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2710-rpi-3-b.dts 2023-12-13 11:50:48.288960541 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; + +#include "bcm2710.dtsi" +#include "bcm2709-rpi.dtsi" +#include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_44.dtsi" +#include "bcm271x-rpi-bt.dtsi" + +/ { + compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; + model = "Raspberry Pi 3 Model B"; + + chosen { + bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_headphones=0"; + }; + + aliases { + serial0 = &uart1; + serial1 = &uart0; + mmc1 = &mmcnr; + }; +}; + +&gpio { + /* + * Taken from rpi_SCH_3b_1p2_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "NC", /* GPIO 28 */ + "LAN_RUN_BOOT", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "PWM0_OUT", + "PWM1_OUT", + "ETH_CLK", + "WIFI_CLK", + "SDA0", + "SCL0", + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ + }; + + spi0_cs_pins: spi0_cs_pins { + brcm,pins = <8 7>; + brcm,function = <1>; /* output */ + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; + }; + + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; + + sdio_pins: sdio_pins { + brcm,pins = <34 35 36 37 38 39>; + brcm,function = <7>; // alt3 = SD1 + brcm,pull = <0 2 2 2 2 2>; + }; + + bt_pins: bt_pins { + brcm,pins = <43>; + brcm,function = <4>; /* alt0:GPCLK2 */ + brcm,pull = <0>; + }; + + uart0_pins: uart0_pins { + brcm,pins = <32 33>; + brcm,function = <7>; /* alt3=UART0 */ + brcm,pull = <0 2>; + }; + + uart1_pins: uart1_pins { + brcm,pins; + brcm,function; + brcm,pull; + }; + + uart1_bt_pins: uart1_bt_pins { + brcm,pins = <32 33>; + brcm,function = <BCM2835_FSEL_ALT5>; /* alt5=UART1 */ + brcm,pull = <0 2>; + }; + + audio_pins: audio_pins { + brcm,pins = <40 41>; + brcm,function = <4>; + brcm,pull = <0>; + }; +}; + +&mmcnr { + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pins>; + bus-width = <4>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&soc { + virtgpio: virtgpio { + compatible = "brcm,bcm2835-virtgpio"; + gpio-controller; + #gpio-cells = <2>; + firmware = <&firmware>; + status = "okay"; + }; + +}; + +&firmware { + expgpio: expgpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "BT_ON", + "WL_ON", + "STATUS_LED", + "LAN_RUN", + "HDMI_HPD_N", + "CAM_GPIO0", + "CAM_GPIO1", + "PWR_LOW_N"; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins &bt_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&bt { + max-speed = <921600>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "mmc0"; + gpios = <&virtgpio 0 0>; + }; + + pwr_led: led-pwr { + label = "PWR"; + default-state = "off"; + linux,default-trigger = "input"; + gpios = <&expgpio 7 0>; + }; +}; + +&hdmi { + hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +&cam1_reg { + gpio = <&expgpio 5 GPIO_ACTIVE_HIGH>; +}; + +cam0_reg: &cam_dummy_reg { +}; + +i2c_csi_dsi0: &i2c0 { +}; + +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + + pwr_led_gpio = <&pwr_led>,"gpios:4"; + pwr_led_activelow = <&pwr_led>,"gpios:8"; + pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts linux/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts 2023-12-13 11:50:48.288960541 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; + +#include "bcm2710.dtsi" +#include "bcm2709-rpi.dtsi" +#include "bcm283x-rpi-lan7515.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_44.dtsi" +#include "bcm271x-rpi-bt.dtsi" + +/ { + compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837"; + model = "Raspberry Pi 3 Model B+"; + + chosen { + bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_headphones=0"; + }; + + aliases { + serial0 = &uart1; + serial1 = &uart0; + mmc1 = &mmcnr; + }; +}; + +&gpio { + /* + * Taken from rpi_SCH_3bplus_1p0_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "HDMI_HPD_N", + "STATUS_LED_G", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "PWM0_OUT", + "PWM1_OUT", + "ETH_CLK", + "WIFI_CLK", + "SDA0", + "SCL0", + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ + }; + + spi0_cs_pins: spi0_cs_pins { + brcm,pins = <8 7>; + brcm,function = <1>; /* output */ + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; + }; + + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; + + sdio_pins: sdio_pins { + brcm,pins = <34 35 36 37 38 39>; + brcm,function = <7>; // alt3 = SD1 + brcm,pull = <0 2 2 2 2 2>; + }; + + bt_pins: bt_pins { + brcm,pins = <43>; + brcm,function = <4>; /* alt0:GPCLK2 */ + brcm,pull = <0>; + }; + + uart0_pins: uart0_pins { + brcm,pins = <32 33>; + brcm,function = <7>; /* alt3=UART0 */ + brcm,pull = <0 2>; + }; + + uart1_pins: uart1_pins { + brcm,pins; + brcm,function; + brcm,pull; + }; + + uart1_bt_pins: uart1_bt_pins { + brcm,pins = <32 33 30 31>; + brcm,function = <BCM2835_FSEL_ALT5>; /* alt5=UART1 */ + brcm,pull = <0 2 2 0>; + }; + + audio_pins: audio_pins { + brcm,pins = <40 41>; + brcm,function = <4>; + brcm,pull = <0>; + }; +}; + +&mmcnr { + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pins>; + bus-width = <4>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&firmware { + expgpio: expgpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "BT_ON", + "WL_ON", + "PWR_LED_R", + "LAN_RUN", + "NC", + "CAM_GPIO0", + "CAM_GPIO1", + "NC"; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins &bt_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "mmc0"; + gpios = <&gpio 29 0>; + }; + + pwr_led: led-pwr { + label = "PWR"; + default-state = "off"; + linux,default-trigger = "default-on"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +ð_phy { + microchip,eee-enabled; + microchip,tx-lpi-timer = <600>; /* non-aggressive*/ + microchip,downshift-after = <2>; +}; + +&cam1_reg { + gpio = <&expgpio 5 GPIO_ACTIVE_HIGH>; +}; + +cam0_reg: &cam_dummy_reg { +}; + +i2c_csi_dsi0: &i2c0 { +}; + +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + + pwr_led_gpio = <&pwr_led>,"gpios:4"; + pwr_led_activelow = <&pwr_led>,"gpios:8"; + pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; + + eee = <ð_phy>,"microchip,eee-enabled?"; + tx_lpi_timer = <ð_phy>,"microchip,tx-lpi-timer:0"; + eth_led0 = <ð_phy>,"microchip,led-modes:0"; + eth_led1 = <ð_phy>,"microchip,led-modes:4"; + eth_downshift_after = <ð_phy>,"microchip,downshift-after:0"; + eth_max_speed = <ð_phy>,"max-speed:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2710-rpi-cm3.dts linux/arch/arm/boot/dts/bcm2710-rpi-cm3.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2710-rpi-cm3.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2710-rpi-cm3.dts 2023-12-13 11:50:48.288960541 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; + +#include "bcm2710.dtsi" +#include "bcm2709-rpi.dtsi" +#include "bcm283x-rpi-csi0-2lane.dtsi" +#include "bcm283x-rpi-csi1-4lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" +/ { + compatible = "raspberrypi,3-compute-module", "brcm,bcm2837"; + model = "Raspberry Pi Compute Module 3"; +}; + +&cam1_reg { + gpio = <&gpio 3 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +cam0_reg: &cam0_regulator { + gpio = <&gpio 31 GPIO_ACTIVE_HIGH>; +}; + +i2c_csi_dsi0: &i2c0 { +}; + +&uart0 { + status = "okay"; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "GPIO0", + "GPIO1", + "GPIO2", + "GPIO3", + "GPIO4", + "GPIO5", + "GPIO6", + "GPIO7", + "GPIO8", + "GPIO9", + "GPIO10", + "GPIO11", + "GPIO12", + "GPIO13", + "GPIO14", + "GPIO15", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "GPIO32", + "GPIO33", + "GPIO34", + "GPIO35", + "GPIO36", + "GPIO37", + "GPIO38", + "GPIO39", + "GPIO40", + "GPIO41", + "GPIO42", + "GPIO43", + "GPIO44", + "GPIO45", + "SMPS_SCL", + "SMPS_SDA", + /* Used by eMMC */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ + }; + + spi0_cs_pins: spi0_cs_pins { + brcm,pins = <8 7>; + brcm,function = <1>; /* output */ + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; + }; + + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; + + audio_pins: audio_pins { + brcm,pins; + brcm,function; + }; +}; + +&soc { + virtgpio: virtgpio { + compatible = "brcm,bcm2835-virtgpio"; + gpio-controller; + #gpio-cells = <2>; + firmware = <&firmware>; + status = "okay"; + }; + +}; + +&firmware { + expgpio: expgpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "HDMI_HPD_N", + "EMMC_EN_N", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; + status = "okay"; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "mmc0"; + gpios = <&virtgpio 0 0>; + }; +}; + +&hdmi { + hpd-gpios = <&expgpio 0 GPIO_ACTIVE_LOW>; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + cam0_reg = <&cam0_reg>,"status"; + cam0_reg_gpio = <&cam0_reg>,"gpio:4"; + cam1_reg = <&cam1_reg>,"status"; + cam1_reg_gpio = <&cam1_reg>,"gpio:4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2710-rpi-zero-2.dts linux/arch/arm/boot/dts/bcm2710-rpi-zero-2.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2710-rpi-zero-2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2710-rpi-zero-2.dts 2023-12-13 11:50:48.288960541 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include "bcm2710-rpi-zero-2-w.dts" diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2710-rpi-zero-2-w.dts linux/arch/arm/boot/dts/bcm2710-rpi-zero-2-w.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2710-rpi-zero-2-w.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2710-rpi-zero-2-w.dts 2023-12-13 11:50:48.288960541 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; + +#include "bcm2710.dtsi" +#include "bcm2709-rpi.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_44.dtsi" +#include "bcm2708-rpi-bt.dtsi" + +/ { + compatible = "raspberrypi,model-zero-2-w", "brcm,bcm2837"; + model = "Raspberry Pi Zero 2 W"; + + chosen { + bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_headphones=0"; + }; + + aliases { + serial0 = &uart1; + serial1 = &uart0; + mmc1 = &mmcnr; + }; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "HDMI_HPD_N", + "STATUS_LED_N", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "CAM_GPIO1", /* GPIO40 */ + "WL_ON", /* GPIO41 */ + "BT_ON", /* GPIO42 */ + "WIFI_CLK", /* GPIO43 */ + "SDA0", /* GPIO44 */ + "SCL0", /* GPIO45 */ + "SMPS_SCL", /* GPIO46 */ + "SMPS_SDA", /* GPIO47 */ + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ + }; + + spi0_cs_pins: spi0_cs_pins { + brcm,pins = <8 7>; + brcm,function = <1>; /* output */ + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; + }; + + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; + + sdio_pins: sdio_pins { + brcm,pins = <34 35 36 37 38 39>; + brcm,function = <7>; // alt3 = SD1 + brcm,pull = <0 2 2 2 2 2>; + }; + + bt_pins: bt_pins { + brcm,pins = <43>; + brcm,function = <4>; /* alt0:GPCLK2 */ + brcm,pull = <0>; + }; + + uart0_pins: uart0_pins { + brcm,pins = <30 31 32 33>; + brcm,function = <7>; /* alt3=UART0 */ + brcm,pull = <2 0 0 2>; /* up none none up */ + }; + + uart1_pins: uart1_pins { + brcm,pins; + brcm,function; + brcm,pull; + }; + + uart1_bt_pins: uart1_bt_pins { + brcm,pins = <32 33 30 31>; + brcm,function = <BCM2835_FSEL_ALT5>; /* alt5=UART1 */ + brcm,pull = <0 2 2 0>; + }; + + audio_pins: audio_pins { + brcm,pins = <>; + brcm,function = <>; + }; +}; + +&mmcnr { + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pins>; + bus-width = <4>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins &bt_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "actpwr"; + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +&bt { + shutdown-gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; +}; + +&minibt { + shutdown-gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; +}; + +&cam1_reg { + gpio = <&gpio 40 GPIO_ACTIVE_HIGH>; +}; + +cam0_reg: &cam_dummy_reg { +}; + +i2c_csi_dsi0: &i2c0 { +}; + +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2711-rpi-400.dts linux/arch/arm/boot/dts/bcm2711-rpi-400.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2711-rpi-400.dts 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2711-rpi-400.dts 2023-12-13 11:50:48.289960543 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -#include "bcm2711-rpi-4-b.dts" +#define BCM2711 +#define i2c0 i2c0if +#include "bcm2711.dtsi" +#include "bcm283x-rpi-wifi-bt.dtsi" +#undef i2c0 +#include "bcm270x.dtsi" +#define i2c0 i2c0mux +#include "bcm2711-rpi.dtsi" +#undef i2c0 +//#include "bcm283x-rpi-usb-peripheral.dtsi" / { compatible = "raspberrypi,400", "brcm,bcm2711"; @ linux/arch/arm/boot/dts/bcm2708.dtsi:24 @ }; leds { - /delete-node/ led-act; + led-act { + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; + }; led-pwr { - gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; }; }; - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&expgpio 5 GPIO_ACTIVE_HIGH>; + sd_io_1v8_reg: sd_io_1v8_reg { + compatible = "regulator-gpio"; + regulator-name = "vdd-sd-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-settling-time-us = <5000>; + gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + status = "okay"; }; + + sd_vcc_reg: sd_vcc_reg { + compatible = "regulator-fixed"; + regulator-name = "vcc-sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&bt { + shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; +}; + +&ddc0 { + status = "okay"; +}; + +&ddc1 { + status = "okay"; }; &expgpio { @ linux/arch/arm/boot/dts/bcm2708.dtsi:84 @ "SHUTDOWN_REQUEST"; }; +&gpio { + /* + * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "RGMII_MDIO", + "RGMIO_MDC", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + /* Shared with SPI flash */ + "PWM0_MISO", + "PWM1_MOSI", + "STATUS_LED_G_CLK", + "SPIFLASH_CE_N", + "SDA0", + "SCL0", + "RGMII_RXCLK", + "RGMII_RXCTL", + "RGMII_RXD0", + "RGMII_RXD1", + "RGMII_RXD2", + "RGMII_RXD3", + "RGMII_TXCLK", + "RGMII_TXCTL", + "RGMII_TXD0", + "RGMII_TXD1", + "RGMII_TXD2", + "RGMII_TXD3"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; +}; + +&pixelvalve0 { + status = "okay"; +}; + +&pixelvalve1 { + status = "okay"; +}; + +&pixelvalve2 { + status = "okay"; +}; + +&pixelvalve4 { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>; + status = "okay"; +}; + +/* EMMC2 is used to drive the SD card */ +&emmc2 { + vqmmc-supply = <&sd_io_1v8_reg>; + vmmc-supply = <&sd_vcc_reg>; + broken-cd; + status = "okay"; +}; + +&genet { + phy-handle = <&phy1>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +&genet_mdio { + phy1: ethernet-phy@1 { + /* No PHY interrupt */ + reg = <0x1>; + }; +}; + +&pcie0 { + pci@0,0 { + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + reg = <0 0 0 0 0>; + + usb@0,0 { + reg = <0 0 0 0 0>; + resets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>; + }; + }; +}; + +/* uart0 communicates with the BT module */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>; + uart-has-rtscts; +}; + +/* uart1 is mapped to the pin header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; + +&vc4 { + status = "okay"; +}; + +&vec { + status = "disabled"; +}; + +&wifi_pwrseq { + reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; +}; + +// ============================================= +// Downstream rpi- changes + +#include "bcm271x-rpi-bt.dtsi" + +/ { + soc { + /delete-node/ pixelvalve@7e807000; + /delete-node/ hdmi@7e902000; + }; +}; + +#include "bcm2711-rpi-ds.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_44.dtsi" + +/ { + chosen { + bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_headphones=0"; + }; + + /delete-node/ wifi-pwrseq; +}; + +&mmcnr { + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pins>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins &bt_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&gpio { + bt_pins: bt_pins { + brcm,pins = "-"; // non-empty to keep btuart happy, //4 = 0 + // to fool pinctrl + brcm,function = <0>; + brcm,pull = <2>; + }; + + uart0_pins: uart0_pins { + brcm,pins = <32 33>; + brcm,function = <BCM2835_FSEL_ALT3>; + brcm,pull = <0 2>; + }; + + uart1_pins: uart1_pins { + brcm,pins; + brcm,function; + brcm,pull; + }; + + uart1_bt_pins: uart1_bt_pins { + brcm,pins = <32 33 30 31>; + brcm,function = <BCM2835_FSEL_ALT5>; /* alt5=UART1 */ + brcm,pull = <0 2 2 0>; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +// ============================================= +// Board specific stuff here + +/ { + power_ctrl: power_ctrl { + compatible = "gpio-poweroff"; + gpios = <&expgpio 5 0>; + force; + }; +}; + +&sdhost { + status = "disabled"; +}; + +&phy1 { + led-modes = <0x00 0x08>; /* link/activity link */ +}; + +&gpio { + audio_pins: audio_pins { + brcm,pins = <>; + brcm,function = <>; + }; +}; + +&leds { + // Declare the LED but leave it disabled, in case a user wants to map it + // to a GPIO on the header + act_led: led-act { + default-state = "off"; + linux,default-trigger = "mmc0"; + gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + pwr_led: led-pwr { + default-state = "off"; + linux,default-trigger = "default-on"; + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; + }; +}; + +&pwm1 { + status = "disabled"; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +cam0_reg: &cam_dummy_reg { +}; + &genet_mdio { clock-frequency = <1950000>; }; -&pm { - /delete-property/ system-power-controller; +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4", + <&act_led>,"status=okay"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + + pwr_led_gpio = <&pwr_led>,"gpios:4"; + pwr_led_activelow = <&pwr_led>,"gpios:8"; + pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; + + eth_led0 = <&phy1>,"led-modes:0"; + eth_led1 = <&phy1>,"led-modes:4"; + }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2711-rpi-4-b.dts linux/arch/arm/boot/dts/bcm2711-rpi-4-b.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2711-rpi-4-b.dts 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2711-rpi-4-b.dts 2023-12-13 11:50:48.288960541 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; +#define BCM2711 +#define i2c0 i2c0if #include "bcm2711.dtsi" -#include "bcm2711-rpi.dtsi" -#include "bcm283x-rpi-usb-peripheral.dtsi" #include "bcm283x-rpi-wifi-bt.dtsi" +#undef i2c0 +#include "bcm270x.dtsi" +#define i2c0 i2c0mux +#include "bcm2711-rpi.dtsi" +#undef i2c0 +//#include "bcm283x-rpi-usb-peripheral.dtsi" / { compatible = "raspberrypi,4-model-b", "brcm,bcm2711"; @ linux/arch/arm/boot/dts/bcm2708.dtsi:81 @ "VDD_SD_IO_SEL", "CAM_GPIO", /* 5 */ "SD_PWR_ON", - ""; + "SD_OC_N"; }; &gpio { @ linux/arch/arm/boot/dts/bcm2708.dtsi:249 @ &wifi_pwrseq { reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; }; + +// ============================================= +// Downstream rpi- changes + +#include "bcm271x-rpi-bt.dtsi" + +/ { + soc { + /delete-node/ pixelvalve@7e807000; + /delete-node/ hdmi@7e902000; + }; +}; + +#include "bcm2711-rpi-ds.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_44.dtsi" + +/ { + chosen { + bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_headphones=0"; + }; + + /delete-node/ wifi-pwrseq; +}; + +&mmcnr { + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pins>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins &bt_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&gpio { + bt_pins: bt_pins { + brcm,pins = "-"; // non-empty to keep btuart happy, //4 = 0 + // to fool pinctrl + brcm,function = <0>; + brcm,pull = <2>; + }; + + uart0_pins: uart0_pins { + brcm,pins = <32 33>; + brcm,function = <BCM2835_FSEL_ALT3>; + brcm,pull = <0 2>; + }; + + uart1_pins: uart1_pins { + brcm,pins; + brcm,function; + brcm,pull; + }; + + uart1_bt_pins: uart1_bt_pins { + brcm,pins = <32 33 30 31>; + brcm,function = <BCM2835_FSEL_ALT5>; /* alt5=UART1 */ + brcm,pull = <0 2 2 0>; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +// ============================================= +// Board specific stuff here + +&sdhost { + status = "disabled"; +}; + +&phy1 { + led-modes = <0x00 0x08>; /* link/activity link */ +}; + +&gpio { + audio_pins: audio_pins { + brcm,pins = <40 41>; + brcm,function = <4>; + brcm,pull = <0>; + }; +}; + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "mmc0"; + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; + }; + + pwr_led: led-pwr { + default-state = "off"; + linux,default-trigger = "default-on"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + }; +}; + +&pwm1 { + status = "disabled"; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +&cam1_reg { + gpio = <&expgpio 5 GPIO_ACTIVE_HIGH>; +}; + +cam0_reg: &cam_dummy_reg { +}; + +i2c_csi_dsi0: &i2c0 { +}; + +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + + pwr_led_gpio = <&pwr_led>,"gpios:4"; + pwr_led_activelow = <&pwr_led>,"gpios:8"; + pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; + + eth_led0 = <&phy1>,"led-modes:0"; + eth_led1 = <&phy1>,"led-modes:4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2711-rpi-cm4.dts linux/arch/arm/boot/dts/bcm2711-rpi-cm4.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2711-rpi-cm4.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2711-rpi-cm4.dts 2023-12-13 11:50:48.289960543 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#define BCM2711 +#define i2c0 i2c0if +#include "bcm2711.dtsi" +#include "bcm283x-rpi-wifi-bt.dtsi" +#undef i2c0 +#include "bcm270x.dtsi" +#define i2c0 i2c0mux +#include "bcm2711-rpi.dtsi" +#undef i2c0 +//#include "bcm283x-rpi-usb-peripheral.dtsi" + +/ { + compatible = "raspberrypi,4-compute-module", "brcm,bcm2711"; + model = "Raspberry Pi Compute Module 4"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + leds { + led-act { + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; + }; + + led-pwr { + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; + }; + + sd_io_1v8_reg: sd_io_1v8_reg { + compatible = "regulator-gpio"; + regulator-name = "vdd-sd-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-settling-time-us = <5000>; + gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + status = "okay"; + }; + + sd_vcc_reg: sd_vcc_reg { + compatible = "regulator-fixed"; + regulator-name = "vcc-sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&bt { + shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; +}; + +&ddc0 { + status = "okay"; +}; + +&ddc1 { + status = "okay"; +}; + +&expgpio { + gpio-line-names = "BT_ON", + "WL_ON", + "PWR_LED_OFF", + "ANT1", + "VDD_SD_IO_SEL", + "CAM_GPIO", + "SD_PWR_ON", + "ANT2"; + + ant1: ant1 { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-high; + }; + + ant2: ant2 { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; + +&gpio { + /* + * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "RGMII_MDIO", + "RGMIO_MDC", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + /* Shared with SPI flash */ + "PWM0_MISO", + "PWM1_MOSI", + "STATUS_LED_G_CLK", + "SPIFLASH_CE_N", + "SDA0", + "SCL0", + "RGMII_RXCLK", + "RGMII_RXCTL", + "RGMII_RXD0", + "RGMII_RXD1", + "RGMII_RXD2", + "RGMII_RXD3", + "RGMII_TXCLK", + "RGMII_TXCTL", + "RGMII_TXD0", + "RGMII_TXD1", + "RGMII_TXD2", + "RGMII_TXD3"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; +}; + +&pixelvalve0 { + status = "okay"; +}; + +&pixelvalve1 { + status = "okay"; +}; + +&pixelvalve2 { + status = "okay"; +}; + +&pixelvalve4 { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>; + status = "okay"; +}; + +/* EMMC2 is used to drive the EMMC card */ +&emmc2 { + bus-width = <8>; + vqmmc-supply = <&sd_io_1v8_reg>; + vmmc-supply = <&sd_vcc_reg>; + broken-cd; + status = "okay"; +}; + +&genet { + phy-handle = <&phy1>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +&genet_mdio { + phy1: ethernet-phy@0 { + /* No PHY interrupt */ + reg = <0x0>; + }; +}; + +&pcie0 { + pci@0,0 { + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + reg = <0 0 0 0 0>; + }; +}; + +/* uart0 communicates with the BT module */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>; + uart-has-rtscts; +}; + +/* uart1 is mapped to the pin header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; + +&vc4 { + status = "okay"; +}; + +&vec { + status = "disabled"; +}; + +&wifi_pwrseq { + reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; +}; + +// ============================================= +// Downstream rpi- changes + +#include "bcm271x-rpi-bt.dtsi" + +/ { + soc { + /delete-node/ pixelvalve@7e807000; + /delete-node/ hdmi@7e902000; + }; +}; + +#include "bcm2711-rpi-ds.dtsi" +#include "bcm283x-rpi-csi0-2lane.dtsi" +#include "bcm283x-rpi-csi1-4lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_44.dtsi" + +/ { + chosen { + bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_headphones=0"; + }; + + /delete-node/ wifi-pwrseq; +}; + +&mmcnr { + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pins>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins &bt_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&gpio { + bt_pins: bt_pins { + brcm,pins = "-"; // non-empty to keep btuart happy, //4 = 0 + // to fool pinctrl + brcm,function = <0>; + brcm,pull = <2>; + }; + + uart0_pins: uart0_pins { + brcm,pins = <32 33>; + brcm,function = <BCM2835_FSEL_ALT3>; + brcm,pull = <0 2>; + }; + + uart1_pins: uart1_pins { + brcm,pins; + brcm,function; + brcm,pull; + }; + + uart1_bt_pins: uart1_bt_pins { + brcm,pins = <32 33 30 31>; + brcm,function = <BCM2835_FSEL_ALT5>; /* alt5=UART1 */ + brcm,pull = <0 2 2 0>; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +// ============================================= +// Board specific stuff here + +&pcie0 { + brcm,enable-l1ss; +}; + +&sdhost { + status = "disabled"; +}; + +&phy1 { + led-modes = <0x00 0x08>; /* link/activity link */ +}; + +&gpio { + audio_pins: audio_pins { + brcm,pins = <>; + brcm,function = <>; + }; +}; + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "mmc0"; + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; + }; + + pwr_led: led-pwr { + default-state = "off"; + linux,default-trigger = "default-on"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + }; +}; + +&pwm1 { + status = "disabled"; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +cam0_reg: &cam1_reg { + gpio = <&expgpio 5 GPIO_ACTIVE_HIGH>; +}; + +i2c_csi_dsi0: &i2c0 { +}; + +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + + pwr_led_gpio = <&pwr_led>,"gpios:4"; + pwr_led_activelow = <&pwr_led>,"gpios:8"; + pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; + + eth_led0 = <&phy1>,"led-modes:0"; + eth_led1 = <&phy1>,"led-modes:4"; + + ant1 = <&ant1>,"output-high?=on", + <&ant1>, "output-low?=off", + <&ant2>, "output-high?=off", + <&ant2>, "output-low?=on"; + ant2 = <&ant1>,"output-high?=off", + <&ant1>, "output-low?=on", + <&ant2>, "output-high?=on", + <&ant2>, "output-low?=off"; + noant = <&ant1>,"output-high?=off", + <&ant1>, "output-low?=on", + <&ant2>, "output-high?=off", + <&ant2>, "output-low?=on"; + + cam0_reg = <&cam0_reg>,"status"; + cam0_reg_gpio = <&cam0_reg>,"gpio:4", + <&cam0_reg>,"gpio:0=", <&gpio>; + cam1_reg = <&cam1_reg>,"status"; + cam1_reg_gpio = <&cam1_reg>,"gpio:4", + <&cam1_reg>,"gpio:0=", <&gpio>; + + pcie_tperst_clk_ms = <&pcie0>,"brcm,tperst-clk-ms:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2711-rpi-cm4s.dts linux/arch/arm/boot/dts/bcm2711-rpi-cm4s.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2711-rpi-cm4s.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2711-rpi-cm4s.dts 2023-12-13 11:50:48.289960543 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#define BCM2711 +#define i2c0 i2c0if +#include "bcm2711.dtsi" +//#include "bcm283x-rpi-wifi-bt.dtsi" +#undef i2c0 +#include "bcm270x.dtsi" +#define i2c0 i2c0mux +#include "bcm2711-rpi.dtsi" +#undef i2c0 + +/ { + compatible = "raspberrypi,4-compute-module-s", "brcm,bcm2711"; + model = "Raspberry Pi Compute Module 4S"; + + leds { + led-act { + gpios = <&virtgpio 0 0>; + }; + }; +}; + +&ddc0 { + status = "okay"; +}; + +&gpio { + /* + * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "GPIO32", + "GPIO33", + "GPIO34", + "GPIO35", + "GPIO36", + "GPIO37", + "GPIO38", + "GPIO39", + "PWM0_MISO", + "PWM1_MOSI", + "GPIO42", + "GPIO43", + "GPIO44", + "GPIO45"; +}; + +&hdmi0 { + status = "okay"; +}; + +&pixelvalve0 { + status = "okay"; +}; + +&pixelvalve1 { + status = "okay"; +}; + +&pixelvalve2 { + status = "okay"; +}; + +&pixelvalve4 { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>; + status = "okay"; +}; + +/* EMMC2 is used to drive the EMMC card */ +&emmc2 { + bus-width = <8>; + broken-cd; + status = "okay"; +}; + +&pcie0 { + status = "disabled"; +}; + +&vchiq { + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; +}; + +&vc4 { + status = "okay"; +}; + +&vec { + status = "disabled"; +}; + +// ============================================= +// Downstream rpi- changes + +#include "bcm2711-rpi-ds.dtsi" + +/ { + soc { + /delete-node/ pixelvalve@7e807000; + /delete-node/ hdmi@7e902000; + + virtgpio: virtgpio { + compatible = "brcm,bcm2835-virtgpio"; + gpio-controller; + #gpio-cells = <2>; + firmware = <&firmware>; + status = "okay"; + }; + }; +}; + +#include "bcm283x-rpi-csi0-2lane.dtsi" +#include "bcm283x-rpi-csi1-4lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" + +/ { + chosen { + bootargs = "coherent_pool=1M snd_bcm2835.enable_headphones=0"; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + /delete-property/ i2c20; + /delete-property/ i2c21; + }; + + /delete-node/ wifi-pwrseq; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +&gpio { + uart0_pins: uart0_pins { + brcm,pins; + brcm,function; + brcm,pull; + }; +}; + +&i2c0if { + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +// ============================================= +// Board specific stuff here + +/* Enable USB in OTG-aware mode */ +&usb { + compatible = "brcm,bcm2835-usb"; + dr_mode = "otg"; + g-np-tx-fifo-size = <32>; + g-rx-fifo-size = <558>; + g-tx-fifo-size = <512 512 512 512 512 256 256>; + status = "okay"; +}; + +&sdhost { + status = "disabled"; +}; + +&gpio { + audio_pins: audio_pins { + brcm,pins = <>; + brcm,function = <>; + }; +}; + +/* Permanently disable HDMI1 */ +&hdmi1 { + compatible = "disabled"; +}; + +/* Permanently disable DDC1 */ +&ddc1 { + compatible = "disabled"; +}; + +&leds { + act_led: led-act { + default-state = "off"; + linux,default-trigger = "mmc0"; + }; +}; + +&pwm1 { + status = "disabled"; +}; + +&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +&cam1_reg { + gpio = <&gpio 3 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +cam0_reg: &cam0_regulator { + gpio = <&gpio 31 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +i2c_csi_dsi0: &i2c0 { +}; + +/ { + __overrides__ { + audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + + cam0_reg = <&cam0_reg>,"status"; + cam0_reg_gpio = <&cam0_reg>,"gpio:4"; + cam1_reg = <&cam1_reg>,"status"; + cam1_reg_gpio = <&cam1_reg>,"gpio:4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2711-rpi-ds.dtsi linux/arch/arm/boot/dts/bcm2711-rpi-ds.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm2711-rpi-ds.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2711-rpi-ds.dtsi 2023-12-13 11:50:48.290960545 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 +#include "bcm270x-rpi.dtsi" + +/ { + chosen: chosen { + }; + + __overrides__ { + arm_freq; + eee = <&chosen>,"bootargs{on='',off='genet.eee=N'}"; + hdmi = <&hdmi0>,"status", + <&hdmi1>,"status"; + pcie = <&pcie0>,"status"; + sd = <&emmc2>,"status"; + + sd_poll_once = <&emmc2>, "non-removable?"; + spi_dma4 = <&spi0>, "dmas:0=", <&dma40>, + <&spi0>, "dmas:8=", <&dma40>; + i2s_dma4 = <&i2s>, "dmas:0=", <&dma40>, + <&i2s>, "dmas:8=", <&dma40>; + }; + + scb: scb { + /* Add a label */ + }; + + soc: soc { + /* Add a label */ + }; + + arm-pmu { + compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3", "arm,cortex-a7-pmu"; + + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + uart2 = &uart2; + uart3 = &uart3; + uart4 = &uart4; + uart5 = &uart5; + serial0 = &uart1; + serial1 = &uart0; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + mmc0 = &emmc2; + mmc1 = &mmcnr; + mmc2 = &sdhost; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c20 = &ddc0; + i2c21 = &ddc1; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &spi5; + spi6 = &spi6; + /delete-property/ intc; + }; + + /* + * Add a node with a dma-ranges value that exists only to be found + * by of_dma_get_max_cpu_address, and hence limit the DMA zone. + */ + zone_dma { + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x0 0x0 0x0 0x40000000>; + }; +}; + +&vc4 { + raspberrypi,firmware = <&firmware>; +}; + +&cma { + /* Limit cma to the lower 768MB to allow room for HIGHMEM on 32-bit */ + alloc-ranges = <0x0 0x00000000 0x30000000>; +}; + +&soc { + /* Add the physical <-> DMA mapping for the I/O space */ + dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>, + <0x7c000000 0x0 0xfc000000 0x03800000>; +}; + +&scb { + #size-cells = <2>; + + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x0 0x03800000>, + <0x0 0x40000000 0x0 0xff800000 0x0 0x00800000>, + <0x6 0x00000000 0x6 0x00000000 0x0 0x40000000>, + <0x0 0x00000000 0x0 0x00000000 0x0 0xfc000000>; + dma-ranges = <0x4 0x7c000000 0x0 0xfc000000 0x0 0x03800000>, + <0x0 0x00000000 0x0 0x00000000 0x4 0x00000000>; + + dma40: dma@7e007b00 { + compatible = "brcm,bcm2711-dma"; + reg = <0x0 0x7e007b00 0x0 0x400>; + interrupts = + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, /* dma4 11 */ + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, /* dma4 12 */ + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, /* dma4 13 */ + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; /* dma4 14 */ + interrupt-names = "dma11", + "dma12", + "dma13", + "dma14"; + #dma-cells = <1>; + brcm,dma-channel-mask = <0x7800>; + }; + + xhci: xhci@7e9c0000 { + compatible = "generic-xhci"; + status = "disabled"; + reg = <0x0 0x7e9c0000 0x0 0x100000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RPI_POWER_DOMAIN_USB>; + }; + + codec@7eb10000 { + compatible = "raspberrypi,rpivid-vid-decoder"; + reg = <0x0 0x7eb10000 0x0 0x1000>, /* INTC */ + <0x0 0x7eb00000 0x0 0x10000>; /* HEVC */ + reg-names = "intc", + "hevc"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&firmware_clocks 11>; + clock-names = "hevc"; + }; +}; + +&pcie0 { + reg = <0x0 0x7d500000 0x0 0x9310>; + ranges = <0x02000000 0x0 0xc0000000 0x6 0x00000000 + 0x0 0x40000000>; +}; + +&genet { + reg = <0x0 0x7d580000 0x0 0x10000>; +}; + +&dma40 { + /* The VPU firmware uses DMA channel 11 for VCHIQ */ + brcm,dma-channel-mask = <0x7000>; +}; + +&vchiq { + compatible = "brcm,bcm2711-vchiq"; +}; + +&firmwarekms { + compatible = "raspberrypi,rpi-firmware-kms-2711"; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; +}; + +&smi { + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mmc { + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mmcnr { + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; +}; + +&csi0 { + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; +}; + +&csi1 { + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; +}; + +&random { + compatible = "brcm,bcm2711-rng200"; + status = "okay"; +}; + +&usb { + /* Enable the FIQ support */ + reg = <0x7e980000 0x10000>, + <0x7e00b200 0x200>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; +}; + +&gpio { + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <BCM2835_FSEL_ALT0>; + }; + + spi0_cs_pins: spi0_cs_pins { + brcm,pins = <8 7>; + brcm,function = <BCM2835_FSEL_GPIO_OUT>; + }; + + spi3_pins: spi3_pins { + brcm,pins = <1 2 3>; + brcm,function = <BCM2835_FSEL_ALT3>; + }; + + spi3_cs_pins: spi3_cs_pins { + brcm,pins = <0 24>; + brcm,function = <BCM2835_FSEL_GPIO_OUT>; + }; + + spi4_pins: spi4_pins { + brcm,pins = <5 6 7>; + brcm,function = <BCM2835_FSEL_ALT3>; + }; + + spi4_cs_pins: spi4_cs_pins { + brcm,pins = <4 25>; + brcm,function = <BCM2835_FSEL_GPIO_OUT>; + }; + + spi5_pins: spi5_pins { + brcm,pins = <13 14 15>; + brcm,function = <BCM2835_FSEL_ALT3>; + }; + + spi5_cs_pins: spi5_cs_pins { + brcm,pins = <12 26>; + brcm,function = <BCM2835_FSEL_GPIO_OUT>; + }; + + spi6_pins: spi6_pins { + brcm,pins = <19 20 21>; + brcm,function = <BCM2835_FSEL_ALT3>; + }; + + spi6_cs_pins: spi6_cs_pins { + brcm,pins = <18 27>; + brcm,function = <BCM2835_FSEL_GPIO_OUT>; + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <BCM2835_FSEL_ALT0>; + brcm,pull = <BCM2835_PUD_UP>; + }; + + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <BCM2835_FSEL_ALT0>; + brcm,pull = <BCM2835_PUD_UP>; + }; + + i2c3_pins: i2c3 { + brcm,pins = <4 5>; + brcm,function = <BCM2835_FSEL_ALT5>; + brcm,pull = <BCM2835_PUD_UP>; + }; + + i2c4_pins: i2c4 { + brcm,pins = <8 9>; + brcm,function = <BCM2835_FSEL_ALT5>; + brcm,pull = <BCM2835_PUD_UP>; + }; + + i2c5_pins: i2c5 { + brcm,pins = <12 13>; + brcm,function = <BCM2835_FSEL_ALT5>; + brcm,pull = <BCM2835_PUD_UP>; + }; + + i2c6_pins: i2c6 { + brcm,pins = <22 23>; + brcm,function = <BCM2835_FSEL_ALT5>; + brcm,pull = <BCM2835_PUD_UP>; + }; + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; + brcm,function = <BCM2835_FSEL_ALT0>; + }; + + sdio_pins: sdio_pins { + brcm,pins = <34 35 36 37 38 39>; + brcm,function = <BCM2835_FSEL_ALT3>; // alt3 = SD1 + brcm,pull = <0 2 2 2 2 2>; + }; + + uart2_pins: uart2_pins { + brcm,pins = <0 1>; + brcm,function = <BCM2835_FSEL_ALT4>; + brcm,pull = <0 2>; + }; + + uart3_pins: uart3_pins { + brcm,pins = <4 5>; + brcm,function = <BCM2835_FSEL_ALT4>; + brcm,pull = <0 2>; + }; + + uart4_pins: uart4_pins { + brcm,pins = <8 9>; + brcm,function = <BCM2835_FSEL_ALT4>; + brcm,pull = <0 2>; + }; + + uart5_pins: uart5_pins { + brcm,pins = <12 13>; + brcm,function = <BCM2835_FSEL_ALT4>; + brcm,pull = <0 2>; + }; +}; + +&emmc2 { + mmc-ddr-3_3v; +}; + +&vc4 { + status = "disabled"; +}; + +&pixelvalve0 { + status = "disabled"; +}; + +&pixelvalve1 { + status = "disabled"; +}; + +&pixelvalve2 { + status = "disabled"; +}; + +&pixelvalve3 { + status = "disabled"; +}; + +&pixelvalve4 { + status = "disabled"; +}; + +&hdmi0 { + reg = <0x7ef00700 0x300>, + <0x7ef00300 0x200>, + <0x7ef00f00 0x80>, + <0x7ef00f80 0x80>, + <0x7ef01b00 0x200>, + <0x7ef01f00 0x400>, + <0x7ef00200 0x80>, + <0x7ef04300 0x100>, + <0x7ef20000 0x100>, + <0x7ef00100 0x30>; + reg-names = "hdmi", + "dvp", + "phy", + "rm", + "packet", + "metadata", + "csc", + "cec", + "hd", + "intr2"; + clocks = <&firmware_clocks 13>, + <&firmware_clocks 14>, + <&dvp 0>, + <&clk_27MHz>; + dmas = <&dma40 (10|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; + status = "disabled"; +}; + +&ddc0 { + status = "disabled"; +}; + +&hdmi1 { + reg = <0x7ef05700 0x300>, + <0x7ef05300 0x200>, + <0x7ef05f00 0x80>, + <0x7ef05f80 0x80>, + <0x7ef06b00 0x200>, + <0x7ef06f00 0x400>, + <0x7ef00280 0x80>, + <0x7ef09300 0x100>, + <0x7ef20000 0x100>, + <0x7ef00100 0x30>; + reg-names = "hdmi", + "dvp", + "phy", + "rm", + "packet", + "metadata", + "csc", + "cec", + "hd", + "intr2"; + clocks = <&firmware_clocks 13>, + <&firmware_clocks 14>, + <&dvp 1>, + <&clk_27MHz>; + dmas = <&dma40 (17|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; + status = "disabled"; +}; + +&ddc1 { + status = "disabled"; +}; + +&dvp { + status = "disabled"; +}; + +&vec { + clocks = <&firmware_clocks 15>; +}; + +&aon_intr { + interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; +}; + +&system_timer { + status = "disabled"; +}; + +&i2c0 { + /delete-property/ compatible; + /delete-property/ interrupts; +}; + +&i2c0if { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; +}; + +i2c_arm: &i2c1 {}; +i2c_vc: &i2c0 {}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; +}; + +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; +}; + +&i2c5 { + pinctrl-0 = <&i2c5_pins>; + pinctrl-names = "default"; +}; + +&i2c6 { + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; +}; + +&spi3 { + pinctrl-0 = <&spi3_pins &spi3_cs_pins>; + pinctrl-names = "default"; +}; + +&spi4 { + pinctrl-0 = <&spi4_pins &spi4_cs_pins>; + pinctrl-names = "default"; +}; + +&spi5 { + pinctrl-0 = <&spi5_pins &spi5_cs_pins>; + pinctrl-names = "default"; +}; + +&spi6 { + pinctrl-0 = <&spi6_pins &spi6_cs_pins>; + pinctrl-names = "default"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; +}; + +&uart3 { + pinctrl-0 = <&uart3_pins>; + pinctrl-names = "default"; +}; + +&uart4 { + pinctrl-0 = <&uart4_pins>; + pinctrl-names = "default"; +}; + +&uart5 { + pinctrl-0 = <&uart5_pins>; + pinctrl-names = "default"; +}; + +/delete-node/ &v3d; + +/ { + v3dbus: v3dbus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <2>; + ranges = <0x7c500000 0x0 0xfc500000 0x0 0x03300000>, + <0x40000000 0x0 0xff800000 0x0 0x00800000>; + dma-ranges = <0x00000000 0x0 0x00000000 0x4 0x00000000>; + + v3d: v3d@7ec04000 { + compatible = "brcm,2711-v3d"; + reg = + <0x7ec00000 0x0 0x4000>, + <0x7ec04000 0x0 0x4000>; + reg-names = "hub", "core0"; + + power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; + resets = <&pm BCM2835_RESET_V3D>; + clocks = <&firmware_clocks 5>; + clocks-names = "v3d"; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2711-rpi.dtsi linux/arch/arm/boot/dts/bcm2711-rpi.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm2711-rpi.dtsi 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2711-rpi.dtsi 2023-12-13 11:50:48.290960545 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:18 @ ethernet0 = &genet; pcie0 = &pcie0; blconfig = &blconfig; + blpubkey = &blpubkey; }; }; @ linux/arch/arm/boot/dts/bcm2708.dtsi:68 @ #address-cells = <1>; #size-cells = <1>; reg = <0x0 0x0 0x0>; + no-map; + status = "disabled"; + }; + /* + * RPi4 will copy the binary public key blob (if present) from the bootloader + * into memory for use by the OS. + */ + blpubkey: nvram@1 { + compatible = "raspberrypi,bootloader-public-key", "nvmem-rmem"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x0>; no-map; status = "disabled"; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2712.dtsi linux/arch/arm/boot/dts/bcm2712.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm2712.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2712.dtsi 2023-12-13 11:50:48.292960550 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/bcm2835-pm.h> +#include <dt-bindings/phy/phy.h> + +/ { + compatible = "brcm,bcm2712", "brcm,bcm2711"; + model = "BCM2712"; + + #address-cells = <2>; + #size-cells = <1>; + + interrupt-parent = <&gicv2>; + + rmem: reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + atf@0 { + reg = <0x0 0x0 0x80000>; + no-map; + }; + + cma: linux,cma { + compatible = "shared-dma-pool"; + size = <0x4000000>; /* 64MB */ + reusable; + linux,cma-default; + + /* + * arm64 reserves the CMA by default somewhere in + * ZONE_DMA32, that's not good enough for the BCM2711 + * as some devices can only address the lower 1G of + * memory (ZONE_DMA). + */ + alloc-ranges = <0x0 0x00000000 0x40000000>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <2000>; + polling-delay = <1000>; + coefficients = <(-550) 450000>; + thermal-sensors = <&thermal>; + + thermal_trips: trips { + cpu_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling_maps: cooling-maps { + }; + }; + }; + + clk_27MHz: clk-27M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "27MHz-clock"; + }; + + clk_108MHz: clk-108M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <108000000>; + clock-output-names = "108MHz-clock"; + }; + + hvs: hvs@107c580000 { + compatible = "brcm,bcm2712-hvs"; + reg = <0x10 0x7c580000 0x1a000>; + interrupt-parent = <&disp_intr>; + interrupts = <2>, <9>, <16>; + interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof"; + //iommus = <&iommu4>; + status = "disabled"; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x7c000000 0x10 0x7c000000 0x04000000>; + /* Emulate a contiguous 30-bit address range for DMA */ + dma-ranges = <0xc0000000 0x00 0x00000000 0x40000000>, + <0x7c000000 0x10 0x7c000000 0x04000000>; + + system_timer: timer@7c003000 { + compatible = "brcm,bcm2835-system-timer"; + reg = <0x7c003000 0x1000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1000000>; + }; + + firmwarekms: firmwarekms@7d503000 { + compatible = "raspberrypi,rpi-firmware-kms-2712"; + /* SUN_L2 interrupt reg */ + reg = <0x7d503000 0x18>; + interrupt-parent = <&cpu_l2_irq>; + interrupts = <19>; + brcm,firmware = <&firmware>; + status = "disabled"; + }; + + mailbox: mailbox@7c013880 { + compatible = "brcm,bcm2835-mbox"; + reg = <0x7c013880 0x40>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <0>; + }; + + pixelvalve0: pixelvalve@7c410000 { + compatible = "brcm,bcm2712-pixelvalve0"; + reg = <0x7c410000 0x100>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pixelvalve1: pixelvalve@7c411000 { + compatible = "brcm,bcm2712-pixelvalve1"; + reg = <0x7c411000 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + mop: mop@7c500000 { + compatible = "brcm,bcm2712-mop"; + reg = <0x7c500000 0x28>; + interrupt-parent = <&disp_intr>; + interrupts = <1>; + status = "disabled"; + }; + + moplet: moplet@7c501000 { + compatible = "brcm,bcm2712-moplet"; + reg = <0x7c501000 0x20>; + interrupt-parent = <&disp_intr>; + interrupts = <0>; + status = "disabled"; + }; + + disp_intr: interrupt-controller@7c502000 { + compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; + reg = <0x7c502000 0x30>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + status = "disabled"; + }; + + dvp: clock@7c700000 { + compatible = "brcm,brcm2711-dvp"; + reg = <0x7c700000 0x10>; + clocks = <&clk_108MHz>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + /* + * This node is the provider for the enable-method for + * bringing up secondary cores. + */ + local_intc: local_intc@7cd00000 { + compatible = "brcm,bcm2836-l1-intc"; + reg = <0x7cd00000 0x100>; + }; + + uart0: serial@7d001000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7d001000 0x200>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_uart>, + <&clk_vpu>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + uart2: serial@7d001400 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7d001400 0x200>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_uart>, + <&clk_vpu>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + uart3: serial@7d001600 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7d001600 0x200>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_uart>, + <&clk_vpu>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + uart4: serial@7d001800 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7d001800 0x200>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_uart>, + <&clk_vpu>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + uart5: serial@7d001a00 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7d001a00 0x200>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_uart>, + <&clk_vpu>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + sdhost: mmc@7d002000 { + compatible = "brcm,bcm2835-sdhost"; + reg = <0x7d002000 0x100>; + //interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vpu>; + status = "disabled"; + }; + + i2s: i2s@7d003000 { + compatible = "brcm,bcm2835-i2s"; + reg = <0x7d003000 0x24>; + //clocks = <&cprman BCM2835_CLOCK_PCM>; + status = "disabled"; + }; + + spi0: spi@7d004000 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7d004000 0x200>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vpu>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@7d004600 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7d004600 0x0200>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vpu>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@7d004800 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7d004800 0x0200>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vpu>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@7d004a00 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7d004a00 0x0200>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vpu>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@7d004c00 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7d004c00 0x0200>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vpu>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@7d005000 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + reg = <0x7d005000 0x20>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vpu>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@7d005600 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + reg = <0x7d005600 0x20>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vpu>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@7d005800 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + reg = <0x7d005800 0x20>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vpu>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@7d005a00 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + reg = <0x7d005a00 0x20>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vpu>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@7d005c00 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + reg = <0x7d005c00 0x20>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vpu>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@7d005e00 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + reg = <0x7d005e00 0x20>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vpu>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm0: pwm@7d00c000 { + compatible = "brcm,bcm2835-pwm"; + reg = <0x7d00c000 0x28>; + assigned-clock-rates = <10000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@7d00c800 { + compatible = "brcm,bcm2835-pwm"; + reg = <0x7d00c800 0x28>; + assigned-clock-rates = <10000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pm: watchdog@7d200000 { + compatible = "brcm,bcm2712-pm"; + reg = <0x7d200000 0x308>; + reg-names = "pm"; + #power-domain-cells = <1>; + #reset-cells = <1>; + //clocks = <&cprman BCM2835_CLOCK_V3D>, + // <&cprman BCM2835_CLOCK_PERI_IMAGE>, + // <&cprman BCM2835_CLOCK_H264>, + // <&cprman BCM2835_CLOCK_ISP>; + clock-names = "v3d", "peri_image", "h264", "isp"; + system-power-controller; + }; + + cprman: cprman@7d202000 { + compatible = "brcm,bcm2711-cprman"; + reg = <0x7d202000 0x2000>; + #clock-cells = <1>; + + /* CPRMAN derives almost everything from the + * platform's oscillator. However, the DSI + * pixel clocks come from the DSI analog PHY. + */ + clocks = <&clk_osc>; + status = "disabled"; + }; + + random: rng@7d208000 { + compatible = "brcm,bcm2711-rng200"; + reg = <0x7d208000 0x28>; + status = "okay"; + }; + + cpu_l2_irq: intc@7d503000 { + compatible = "brcm,l2-intc"; + reg = <0x7d503000 0x18>; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pinctrl: pinctrl@7d504100 { + compatible = "brcm,bcm2712-pinctrl"; + reg = <0x7d504100 0x30>; + + uarta_24_pins: uarta_24_pins { + pin_rts { + function = "uart0"; + pins = "gpio24"; + bias-disable; + }; + pin_cts { + function = "uart0"; + pins = "gpio25"; + bias-pull-up; + }; + pin_txd { + function = "uart0"; + pins = "gpio26"; + bias-disable; + }; + pin_rxd { + function = "uart0"; + pins = "gpio27"; + bias-pull-up; + }; + }; + + sdio2_30_pins: sdio2_30_pins { + pin_clk { + function = "sd2"; + pins = "gpio30"; + bias-disable; + }; + pin_cmd { + function = "sd2"; + pins = "gpio31"; + bias-pull-up; + }; + pins_dat { + function = "sd2"; + pins = "gpio32", "gpio33", "gpio34", "gpio35"; + bias-pull-up; + }; + }; + }; + + ddc0: i2c@7d508200 { + compatible = "brcm,brcmstb-i2c"; + reg = <0x7d508200 0x58>; + interrupt-parent = <&bsc_irq>; + interrupts = <1>; + clock-frequency = <200000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ddc1: i2c@7d508280 { + compatible = "brcm,brcmstb-i2c"; + reg = <0x7d508280 0x58>; + interrupt-parent = <&bsc_irq>; + interrupts = <2>; + clock-frequency = <200000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + bscd: i2c@7d508300 { + compatible = "brcm,brcmstb-i2c"; + reg = <0x7d508300 0x58>; + interrupt-parent = <&bsc_irq>; + interrupts = <0>; + clock-frequency = <200000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + bsc_irq: intc@7d508380 { + compatible = "brcm,bcm7271-l2-intc"; + reg = <0x7d508380 0x10>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + main_irq: intc@7d508400 { + compatible = "brcm,bcm7271-l2-intc"; + reg = <0x7d508400 0x10>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gio: gpio@7d508500 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x7d508500 0x40>; + interrupt-parent = <&main_irq>; + interrupts = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + brcm,gpio-bank-widths = <32 22>; + brcm,gpio-direct; + }; + + uarta: serial@7d50c000 { + compatible = "brcm,bcm7271-uart"; + reg = <0x7d50c000 0x20>; + reg-names = "uart"; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; + skip-init; + status = "disabled"; + }; + + uartb: serial@7d50d000 { + compatible = "brcm,bcm7271-uart"; + reg = <0x7d50d000 0x20>; + reg-names = "uart"; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; + skip-init; + status = "disabled"; + }; + + uartc: serial@7d50e000 { + compatible = "brcm,bcm7271-uart"; + reg = <0x7d50e000 0x20>; + reg-names = "uart"; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; + skip-init; + status = "disabled"; + }; + + aon_intr: interrupt-controller@7d510600 { + compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; + reg = <0x7d510600 0x30>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + status = "disabled"; + }; + + pinctrl_aon: pinctrl@7d510700 { + compatible = "brcm,bcm2712-aon-pinctrl"; + reg = <0x7d510700 0x20>; + + i2c3_m4_agpio0_pins: i2c3_m4_agpio0_pins { + function = "vc_i2c3"; + pins = "aon_gpio0", "aon_gpio1"; + bias-pull-up; + }; + + bsc_m1_agpio13_pins: bsc_m1_agpio13_pins { + function = "bsc_m1"; + pins = "aon_gpio13", "aon_gpio14"; + bias-pull-up; + }; + + bsc_pmu_sgpio4_pins: bsc_pmu_sgpio4_pins { + function = "avs_pmu_bsc"; + pins = "aon_sgpio4", "aon_sgpio5"; + }; + + bsc_m2_sgpio4_pins: bsc_m2_sgpio4_pins { + function = "bsc_m2"; + pins = "aon_sgpio4", "aon_sgpio5"; + }; + + pwm_aon_agpio1_pins: pwm_aon_agpio1_pins { + function = "aon_pwm"; + pins = "aon_gpio1", "aon_gpio2"; + }; + + pwm_aon_agpio4_pins: pwm_aon_agpio4_pins { + function = "vc_pwm0"; + pins = "aon_gpio4", "aon_gpio5"; + }; + + pwm_aon_agpio7_pins: pwm_aon_agpio7_pins { + function = "aon_pwm"; + pins = "aon_gpio7", "aon_gpio9"; + }; + }; + + intc@7d517000 { + compatible = "brcm,bcm7271-l2-intc"; + reg = <0x7d517000 0x10>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + status = "disabled"; + }; + + bscc: i2c@7d517a00 { + compatible = "brcm,brcmstb-i2c"; + reg = <0x7d517a00 0x58>; + interrupt-parent = <&bsc_aon_irq>; + interrupts = <0>; + clock-frequency = <200000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm_aon: pwm@7d517a80 { + compatible = "brcm,bcm7038-pwm"; + reg = <0x7d517a80 0x28>; + #pwm-cells = <2>; + clocks = <&clk_27MHz>; + }; + + main_aon_irq: intc@7d517ac0 { + compatible = "brcm,bcm7271-l2-intc"; + reg = <0x7d517ac0 0x10>; + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + bsc_aon_irq: intc@7d517b00 { + compatible = "brcm,bcm7271-l2-intc"; + reg = <0x7d517b00 0x10>; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gio_aon: gpio@7d517c00 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x7d517c00 0x40>; + interrupt-parent = <&main_aon_irq>; + interrupts = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + brcm,gpio-bank-widths = <17 6>; + brcm,gpio-direct; + }; + + avs_monitor: avs-monitor@7d542000 { + compatible = "brcm,bcm2711-avs-monitor", + "syscon", "simple-mfd"; + reg = <0x7d542000 0xf00>; + status = "okay"; + + thermal: thermal { + compatible = "brcm,bcm2711-thermal"; + #thermal-sensor-cells = <0>; + }; + }; + + bsc_pmu: i2c@7d544000 { + compatible = "brcm,brcmstb-i2c"; + reg = <0x7d544000 0x58>; + interrupt-parent = <&bsc_aon_irq>; + interrupts = <1>; + clock-frequency = <200000>; + status = "disabled"; + }; + + hdmi0: hdmi@7ef00700 { + compatible = "brcm,bcm2712-hdmi0"; + reg = <0x7c701400 0x300>, + <0x7c701000 0x200>, + <0x7c701d00 0x300>, + <0x7c702000 0x80>, + <0x7c703800 0x200>, + <0x7c704000 0x800>, + <0x7c700100 0x80>, + <0x7d510800 0x100>, + <0x7c720000 0x100>; + reg-names = "hdmi", + "dvp", + "phy", + "rm", + "packet", + "metadata", + "csc", + "cec", + "hd"; + resets = <&dvp 1>; + interrupt-parent = <&aon_intr>; + interrupts = <1>, <2>, <3>, + <7>, <8>; + interrupt-names = "cec-tx", "cec-rx", "cec-low", + "hpd-connected", "hpd-removed"; + ddc = <&ddc0>; + dmas = <&dma32 10>; + dma-names = "audio-rx"; + status = "disabled"; + }; + + hdmi1: hdmi@7ef05700 { + compatible = "brcm,bcm2712-hdmi1"; + reg = <0x7c706400 0x300>, + <0x7c706000 0x200>, + <0x7c706d00 0x300>, + <0x7c707000 0x80>, + <0x7c708800 0x200>, + <0x7c709000 0x800>, + <0x7c700180 0x80>, + <0x7d511000 0x100>, + <0x7c720000 0x100>; + reg-names = "hdmi", + "dvp", + "phy", + "rm", + "packet", + "metadata", + "csc", + "cec", + "hd"; + ddc = <&ddc1>; + resets = <&dvp 2>; + interrupt-parent = <&aon_intr>; + interrupts = <11>, <12>, <13>, + <14>, <15>; + interrupt-names = "cec-tx", "cec-rx", "cec-low", + "hpd-connected", "hpd-removed"; + dmas = <&dma32 17>; + dma-names = "audio-rx"; + status = "disabled"; + }; + + sound: sound { + }; + }; + + arm-pmu { + compatible = "arm,cortex-a76-pmu"; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>; + /* This only applies to the ARMv7 stub */ + arm,cpu-registers-not-fw-configured; + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x000>; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x200>; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x300>; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + }; + }; + + psci { + method = "smc"; + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + cpu_on = <0xc4000003>; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + }; + + axi: axi { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, + <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, + <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, + <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, + <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; + + dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, + <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, + <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, + <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, + <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; + + vc4: gpu { + compatible = "brcm,bcm2712-vc6"; + }; + + iommu2: iommu@5100 { + /* IOMMU2 for PISP-BE, HEVC; and (unused) H264 accelerators */ + compatible = "brcm,bcm2712-iommu"; + reg = <0x10 0x5100 0x0 0x80>; + cache = <&iommuc>; + #iommu-cells = <0>; + }; + + iommu4: iommu@5200 { + /* IOMMU4 for HVS, MPL/TXP; and (unused) Unicam, PISP-FE, MiniBVN */ + compatible = "brcm,bcm2712-iommu"; + reg = <0x10 0x5200 0x0 0x80>; + cache = <&iommuc>; + #iommu-cells = <0>; + #interconnect-cells = <0>; + }; + + iommu5: iommu@5280 { + /* IOMMU5 for PCIe2 (RP1); and (unused) BSTM */ + compatible = "brcm,bcm2712-iommu"; + reg = <0x10 0x5280 0x0 0x80>; + cache = <&iommuc>; + #iommu-cells = <0>; + dma-iova-offset = <0x10 0x00000000>; // HACK for RP1 masters over PCIe + }; + + iommuc: iommuc@5b00 { + compatible = "brcm,bcm2712-iommuc"; + reg = <0x10 0x5b00 0x0 0x80>; + }; + + dma32: dma@10000 { + compatible = "brcm,bcm2712-dma"; + reg = <0x10 0x00010000 0 0x600>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma0", + "dma1", + "dma2", + "dma3", + "dma4", + "dma5"; + #dma-cells = <1>; + brcm,dma-channel-mask = <0x0035>; + }; + + dma40: dma@10600 { + compatible = "brcm,bcm2712-dma"; + reg = <0x10 0x00010600 0 0x600>; + interrupts = + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, /* dma4 6 */ + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dma4 7 */ + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* dma4 8 */ + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, /* dma4 9 */ + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, /* dma4 10 */ + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; /* dma4 11 */ + interrupt-names = "dma6", + "dma7", + "dma8", + "dma9", + "dma10", + "dma11"; + #dma-cells = <1>; + brcm,dma-channel-mask = <0x0fc0>; + }; + + // Single-lane Gen3 PCIe + // Outbound window at 0x14_000000-0x17_ffffff + pcie0: pcie@100000 { + compatible = "brcm,bcm2712-pcie"; + reg = <0x10 0x00100000 0x0 0x9310>; + device_type = "pci"; + max-link-speed = <2>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + /* + * Unused interrupts: + * 208: AER + * 215: NMI + * 216: PME + */ + interrupt-parent = <&gicv2>; + interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 + IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 210 + IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 211 + IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 212 + IRQ_TYPE_LEVEL_HIGH>; + resets = <&bcm_reset 5>, <&bcm_reset 42>, <&pcie_rescal>; + reset-names = "swinit", "bridge", "rescal"; + msi-controller; + msi-parent = <&pcie0>; + + ranges = <0x02000000 0x00 0x00000000 + 0x17 0x00000000 + 0x0 0xfffffffc>, + <0x43000000 0x04 0x00000000 + 0x14 0x00000000 + 0x3 0x00000000>; + + dma-ranges = <0x43000000 0x10 0x00000000 + 0x00 0x00000000 + 0x10 0x00000000>; + + status = "disabled"; + }; + + // Single-lane Gen3 PCIe + // Outbound window at 0x18_000000-0x1b_ffffff + pcie1: pcie@110000 { + compatible = "brcm,bcm2712-pcie"; + reg = <0x10 0x00110000 0x0 0x9310>; + device_type = "pci"; + max-link-speed = <2>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + /* + * Unused interrupts: + * 218: AER + * 225: NMI + * 226: PME + */ + interrupt-parent = <&gicv2>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 + IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 220 + IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 221 + IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 222 + IRQ_TYPE_LEVEL_HIGH>; + resets = <&bcm_reset 7>, <&bcm_reset 43>, <&pcie_rescal>; + reset-names = "swinit", "bridge", "rescal"; + msi-controller; + msi-parent = <&mip1>; + + ranges = <0x02000000 0x00 0x00000000 + 0x1b 0x00000000 + 0x00 0xfffffffc>, + <0x43000000 0x04 0x00000000 + 0x18 0x00000000 + 0x03 0x00000000>; + + dma-ranges = <0x03000000 0x10 0x00000000 + 0x00 0x00000000 + 0x10 0x00000000>; + + brcm,enable-l1ss; + status = "disabled"; + }; + + pcie_rescal: reset-controller@119500 { + compatible = "brcm,bcm7216-pcie-sata-rescal"; + reg = <0x10 0x00119500 0x0 0x10>; + #reset-cells = <0>; + }; + + // Quad-lane Gen3 PCIe + // Outbound window at 0x1c_000000-0x1f_ffffff + pcie2: pcie@120000 { + compatible = "brcm,bcm2712-pcie"; + reg = <0x10 0x00120000 0x0 0x9310>; + device_type = "pci"; + max-link-speed = <2>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + /* + * Unused interrupts: + * 228: AER + * 235: NMI + * 236: PME + */ + interrupt-parent = <&gicv2>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 + IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 230 + IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 231 + IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 232 + IRQ_TYPE_LEVEL_HIGH>; + resets = <&bcm_reset 32>, <&bcm_reset 44>, <&pcie_rescal>; + reset-names = "swinit", "bridge", "rescal"; + msi-controller; + msi-parent = <&mip0>; + + // ~4GB, 32-bit, not-prefetchable at PCIe 00_00000000 + ranges = <0x02000000 0x00 0x00000000 + 0x1f 0x00000000 + 0x0 0xfffffffc>, + // 12GB, 64-bit, prefetchable at PCIe 04_00000000 + <0x43000000 0x04 0x00000000 + 0x1c 0x00000000 + 0x03 0x00000000>; + + // 64GB system RAM space at PCIe 10_00000000 + dma-ranges = <0x02000000 0x00 0x00000000 + 0x1f 0x00000000 + 0x00 0x00400000>, + <0x43000000 0x10 0x00000000 + 0x00 0x00000000 + 0x10 0x00000000>; + + brcm,enable-l1ss; + status = "disabled"; + }; + + mip0: msi-controller@130000 { + compatible = "brcm,bcm2712-mip-intc"; + reg = <0x10 0x00130000 0x0 0xc0>; + msi-controller; + interrupt-controller; + #interrupt-cells = <2>; + brcm,msi-base-spi = <128>; + brcm,msi-num-spis = <64>; + brcm,msi-offset = <0>; + brcm,msi-pci-addr = <0xff 0xfffff000>; + }; + + mip1: msi-controller@131000 { + compatible = "brcm,bcm2712-mip-intc"; + reg = <0x10 0x00131000 0x0 0xc0>; + msi-controller; + interrupt-controller; + #interrupt-cells = <2>; + brcm,msi-base-spi = <247>; + /* Actually 20 total, but the others are + * both sparse and non-consecutive */ + brcm,msi-num-spis = <8>; + brcm,msi-offset = <8>; + brcm,msi-pci-addr = <0xff 0xffffe000>; + }; + + genet: ethernet@1300000 { + compatible = "brcm,bcm2711-genet-v5"; + reg = <0x10 0x01300000 0x0 0x20010>; + #address-cells = <0x1>; + #size-cells = <0x0>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + phy-mode = "rgmii"; + fixed-link = <0x0 0x1 0x3e8 0x0 0x0>; + phy-speed = <0x3e8>; + phy-id = <0x101>; + phy-type = <0x6>; + local-mac-address = [ 00 10 18 d8 45 de ]; + device_type = "network"; + + genet_mdio: mdio@e14 { + compatible = "brcm,genet-mdio-v5"; + reg = <0xe14 0x8>; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + }; + + syscon_piarbctl: syscon@400018 { + compatible = "brcm,syscon-piarbctl", "syscon", "simple-mfd"; + reg = <0x10 0x00400018 0x0 0x18>; + }; + + usb: usb@480000 { + compatible = "brcm,bcm2835-usb"; + reg = <0x10 0x00480000 0x0 0x10000>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_usb>; + clock-names = "otg"; + phys = <&usbphy>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + rpivid: codec@800000 { + compatible = "raspberrypi,rpivid-vid-decoder"; + reg = <0x10 0x00800000 0x0 0x10000>, /* HEVC */ + <0x10 0x00840000 0x0 0x1000>; /* INTC */ + reg-names = "hevc", + "intc"; + + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&firmware_clocks 11>; + clock-names = "hevc"; + status = "disabled"; + iommus = <&iommu2>; + }; + + sdio1: mmc@fff000 { + compatible = "brcm,bcm2712-sdhci"; + reg = <0x10 0x00fff000 0x0 0x260>, + <0x10 0x00fff400 0x0 0x200>, + <0x10 0x015040b0 0x0 0x4>, // Bus isolation control + <0x10 0x015200f0 0x0 0x24>; // LCPLL control misc0-8 + reg-names = "host", "cfg", "busisol", "lcpll"; + interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_emmc2>; + sdhci-caps-mask = <0x0000C000 0x0>; + sdhci-caps = <0x0 0x0>; + supports-cqe; + mmc-ddr-3_3v; + }; + + sdio2: mmc@1100000 { + compatible = "brcm,bcm2712-sdhci"; + reg = <0x10 0x01100000 0x0 0x260>, + <0x10 0x01100400 0x0 0x200>; + reg-names = "host", "cfg"; + interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_emmc2>; + sdhci-caps-mask = <0x0000C000 0x0>; + sdhci-caps = <0x0 0x0>; + supports-cqe; + mmc-ddr-3_3v; + status = "disabled"; + }; + + sdio0: mmc@1108000 { + compatible = "brcm,bcm2711-emmc2"; + reg = <0x10 0x01108000 0x0 0x100>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_emmc2>; + mmc-ddr-3_3v; + status = "disabled"; + }; + + bcm_reset: reset-controller@1504318 { + compatible = "brcm,brcmstb-reset"; + reg = <0x10 0x01504318 0x0 0x30>; + #reset-cells = <1>; + }; + + v3d: v3d@2000000 { + compatible = "brcm,2712-v3d"; + reg = <0x10 0x02000000 0x0 0x4000>, + <0x10 0x02008000 0x0 0x6000>; + reg-names = "hub", "core0"; + + power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; + resets = <&pm BCM2835_RESET_V3D>; + clocks = <&firmware_clocks 5>; + clocks-names = "v3d"; + interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + gicv2: interrupt-controller@7fff9000 { + interrupt-controller; + #interrupt-cells = <3>; + compatible = "arm,gic-400"; + reg = <0x10 0x7fff9000 0x0 0x1000>, + <0x10 0x7fffa000 0x0 0x2000>, + <0x10 0x7fffc000 0x0 0x2000>, + <0x10 0x7fffe000 0x0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + pisp_be: pisp_be@880000 { + compatible = "raspberrypi,pispbe"; + reg = <0x10 0x00880000 0x0 0x4000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&firmware_clocks 7>; + clocks-names = "isp_be"; + status = "okay"; + iommus = <&iommu2>; + }; + }; + + clocks { + /* The oscillator is the root of the clock tree. */ + clk_osc: clk-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "osc"; + clock-frequency = <54000000>; + }; + + clk_usb: clk-usb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "otg"; + clock-frequency = <480000000>; + }; + + clk_vpu: clk_vpu { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <750000000>; + clock-output-names = "vpu-clock"; + }; + + clk_uart: clk_uart { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <9216000>; + clock-output-names = "uart-clock"; + }; + + clk_emmc2: clk_emmc2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <54000000>; + clock-output-names = "emmc2-clock"; + }; + }; + + usbphy: phy { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2712-rpi-5-b.dts linux/arch/arm/boot/dts/bcm2712-rpi-5-b.dts --- linux-6.1.66/arch/arm/boot/dts/bcm2712-rpi-5-b.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2712-rpi-5-b.dts 2023-12-13 11:50:48.291960548 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/rp1.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/mfd/rp1.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/reset/raspberrypi,firmware-reset.h> + +#define i2c0 _i2c0 +#define i2c3 _i2c3 +#define i2c4 _i2c4 +#define i2c5 _i2c5 +#define i2c6 _i2c6 +#define i2c8 _i2c8 +#define i2s _i2s +#define pwm0 _pwm0 +#define pwm1 _pwm1 +#define spi0 _spi0 +#define spi3 _spi3 +#define spi4 _spi4 +#define spi5 _spi5 +#define spi6 _spi6 +#define uart0 _uart0 +#define uart2 _uart2 +#define uart3 _uart3 +#define uart4 _uart4 +#define uart5 _uart5 + +#include "bcm2712.dtsi" + +#undef i2c0 +#undef i2c3 +#undef i2c4 +#undef i2c5 +#undef i2c6 +#undef i2c8 +#undef i2s +#undef pwm0 +#undef pwm1 +#undef spi0 +#undef spi3 +#undef spi4 +#undef spi5 +#undef spi6 +#undef uart0 +#undef uart2 +#undef uart3 +#undef uart4 +#undef uart5 + +/ { + compatible = "raspberrypi,5-model-b", "brcm,bcm2712"; + model = "Raspberry Pi 5"; + + /* Will be filled by the bootloader */ + memory@0 { + device_type = "memory"; + reg = <0 0 0x28000000>; + }; + + leds: leds { + compatible = "gpio-leds"; + + pwr_led: led-pwr { + label = "PWR"; + gpios = <&rp1_gpio 44 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "none"; + }; + + act_led: led-act { + label = "ACT"; + gpios = <&gio_aon 9 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + }; + + sd_io_1v8_reg: sd_io_1v8_reg { + compatible = "regulator-gpio"; + regulator-name = "vdd-sd-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-settling-time-us = <5000>; + gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1 + 3300000 0x0>; + status = "okay"; + }; + + sd_vcc_reg: sd_vcc_reg { + compatible = "regulator-fixed"; + regulator-name = "vcc-sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wl_on_reg: wl_on_reg { + compatible = "regulator-fixed"; + regulator-name = "wl-on-regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-0 = <&wl_on_pins>; + pinctrl-names = "default"; + + gpio = <&gio 28 GPIO_ACTIVE_HIGH>; + + startup-delay-us = <150000>; + enable-active-high; + }; + + clocks: clocks { + }; + + cam1_clk: cam1_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + status = "disabled"; + }; + + cam0_clk: cam0_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + status = "disabled"; + }; + + cam0_reg: cam0_reg { + compatible = "regulator-fixed"; + regulator-name = "cam0_reg"; + enable-active-high; + status = "okay"; + gpio = <&rp1_gpio 34 0>; // CD0_IO0_MICCLK, to MIPI 0 connector + }; + + cam1_reg: cam1_reg { + compatible = "regulator-fixed"; + regulator-name = "cam1_reg"; + enable-active-high; + status = "okay"; + gpio = <&rp1_gpio 46 0>; // CD1_IO0_MICCLK, to MIPI 1 connector + }; + + cam_dummy_reg: cam_dummy_reg { + compatible = "regulator-fixed"; + regulator-name = "cam-dummy-reg"; + status = "okay"; + }; + + dummy: dummy { + // A target for unwanted overlay fragments + }; + + + // A few extra labels to keep overlays happy + + i2c0if: i2c0if {}; + i2c0mux: i2c0mux {}; +}; + +rp1_target: &pcie2 { + brcm,enable-mps-rcb; + brcm,vdm-qos-map = <0xbbaa9888>; + aspm-no-l0s; + status = "okay"; +}; + +// Add some labels to 2712 device + +// The system UART +uart10: &_uart0 { status = "okay"; }; + +// The system SPI for the bootloader EEPROM +spi10: &_spi0 { status = "okay"; }; + +i2c_rp1boot: &_i2c3 { }; + +#include "rp1.dtsi" + +&rp1 { + // PCIe address space layout: + // 00_00000000-00_00xxxxxx = RP1 peripherals + // 10_00000000-1x_xxxxxxxx = up to 64GB system RAM + + // outbound access aimed at PCIe 0_00xxxxxx -> RP1 c0_40xxxxxx + // This is the RP1 peripheral space + ranges = <0xc0 0x40000000 + 0x02000000 0x00 0x00000000 + 0x00 0x00400000>; + + dma-ranges = + // inbound RP1 1x_xxxxxxxx -> PCIe 1x_xxxxxxxx + <0x10 0x00000000 + 0x43000000 0x10 0x00000000 + 0x10 0x00000000>, + + // inbound RP1 c0_40xxxxxx -> PCIe 00_00xxxxxx + // This allows the RP1 DMA controller to address RP1 hardware + <0xc0 0x40000000 + 0x02000000 0x0 0x00000000 + 0x0 0x00400000>, + + // inbound RP1 0x_xxxxxxxx -> PCIe 1x_xxxxxxxx + <0x00 0x00000000 + 0x02000000 0x10 0x00000000 + 0x10 0x00000000>; +}; + +// Expose RP1 nodes as system nodes with labels + +&rp1_dma { + status = "okay"; +}; + +&rp1_eth { + status = "okay"; + phy-handle = <&phy1>; + phy-reset-gpios = <&rp1_gpio 32 GPIO_ACTIVE_LOW>; + phy-reset-duration = <5>; + + phy1: ethernet-phy@1 { + reg = <0x1>; + brcm,powerdown-enable; + }; +}; + +gpio: &rp1_gpio { + status = "okay"; +}; + +aux: &dummy {}; + +&rp1_usb0 { + pinctrl-0 = <&usb_vbus_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rp1_usb1 { + status = "okay"; +}; + +#include "bcm2712-rpi.dtsi" + +i2c_csi_dsi0: &i2c6 { // Note: This is for MIPI0 connector only + pinctrl-0 = <&rp1_i2c6_38_39>; + pinctrl-names = "default"; + clock-frequency = <100000>; +}; + +i2c_csi_dsi1: &i2c4 { // Note: This is for MIPI1 connector only + pinctrl-0 = <&rp1_i2c4_40_41>; + pinctrl-names = "default"; + clock-frequency = <100000>; +}; + +i2c_csi_dsi: &i2c_csi_dsi1 { }; // An alias for compatibility + +csi0: &rp1_csi0 { }; +csi1: &rp1_csi1 { }; +dsi0: &rp1_dsi0 { }; +dsi1: &rp1_dsi1 { }; +dpi: &rp1_dpi { }; +vec: &rp1_vec { }; +dpi_gpio0: &rp1_dpi_24bit_gpio0 { }; +dpi_gpio1: &rp1_dpi_24bit_gpio2 { }; +dpi_18bit_cpadhi_gpio0: &rp1_dpi_18bit_cpadhi_gpio0 { }; +dpi_18bit_cpadhi_gpio2: &rp1_dpi_18bit_cpadhi_gpio2 { }; +dpi_18bit_gpio0: &rp1_dpi_18bit_gpio0 { }; +dpi_18bit_gpio2: &rp1_dpi_18bit_gpio2 { }; +dpi_16bit_cpadhi_gpio0: &rp1_dpi_16bit_cpadhi_gpio0 { }; +dpi_16bit_cpadhi_gpio2: &rp1_dpi_16bit_cpadhi_gpio2 { }; +dpi_16bit_gpio0: &rp1_dpi_16bit_gpio0 { }; +dpi_16bit_gpio2: &rp1_dpi_16bit_gpio2 { }; + +/* Add the IOMMUs for some RP1 bus masters */ + +&csi0 { + iommus = <&iommu5>; +}; + +&csi1 { + iommus = <&iommu5>; +}; + +&dsi0 { + iommus = <&iommu5>; +}; + +&dsi1 { + iommus = <&iommu5>; +}; + +&dpi { + iommus = <&iommu5>; +}; + +&vec { + iommus = <&iommu5>; +}; + +&ddc0 { + status = "disabled"; +}; + +&ddc1 { + status = "disabled"; +}; + +&hdmi0 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + status = "disabled"; +}; + +&hdmi1 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + status = "disabled"; +}; + +&hvs { + clocks = <&firmware_clocks 4>, <&firmware_clocks 16>; + clock-names = "core", "disp"; +}; + +&mop { + status = "disabled"; +}; + +&moplet { + status = "disabled"; +}; + +&pixelvalve0 { + status = "disabled"; +}; + +&pixelvalve1 { + status = "disabled"; +}; + +&disp_intr { + status = "disabled"; +}; + +/* SDIO1 is used to drive the SD card */ +&sdio1 { + pinctrl-0 = <&emmc_sd_pulls>, <&emmc_aon_cd_pins>; + pinctrl-names = "default"; + vqmmc-supply = <&sd_io_1v8_reg>; + vmmc-supply = <&sd_vcc_reg>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; + //broken-cd; + //no-1-8-v; + status = "okay"; +}; + +&pinctrl_aon { + emmc_aon_cd_pins: emmc_aon_cd_pins { + function = "sd_card_g"; + pins = "aon_gpio5"; + bias-pull-up; + }; + + /* Slight hack - only one PWM pin (status LED) is usable */ + aon_pwm_1pin: aon_pwm_1pin { + function = "aon_pwm"; + pins = "aon_gpio9"; + }; +}; + +&pinctrl { + pwr_button_pins: pwr_button_pins { + function = "gpio"; + pins = "gpio20"; + bias-pull-up; + }; + + wl_on_pins: wl_on_pins { + function = "gpio"; + pins = "gpio28"; + }; + + bt_shutdown_pins: bt_shutdown_pins { + function = "gpio"; + pins = "gpio29"; + }; + + emmc_sd_pulls: emmc_sd_pulls { + function = "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3"; + bias-pull-up; + }; +}; + +/* uarta communicates with the BT module */ +&uarta { + uart-has-rtscts; + auto-flow-control; + status = "okay"; + clock-frequency = <96000000>; + pinctrl-0 = <&uarta_24_pins &bt_shutdown_pins>; + pinctrl-names = "default"; + + bluetooth: bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gio 29 GPIO_ACTIVE_HIGH>; + local-bd-address = [ 00 00 00 00 00 00 ]; + }; +}; + +&i2c_rp1boot { + clock-frequency = <400000>; + pinctrl-0 = <&i2c3_m4_agpio0_pins>; + pinctrl-names = "default"; +}; + +/ { + chosen: chosen { + bootargs = "reboot=w coherent_pool=1M 8250.nr_uarts=1 pci=pcie_bus_safe snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1"; + stdout-path = "serial10:115200n8"; + }; + + fan: cooling_fan { + status = "disabled"; + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-min-state = <0>; + cooling-max-state = <3>; + cooling-levels = <0 75 125 175 250>; + pwms = <&rp1_pwm1 3 41566 PWM_POLARITY_INVERTED>; + rpm-regmap = <&rp1_pwm1>; + rpm-offset = <0x3c>; + }; + + pwr_button { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pwr_button_pins>; + status = "okay"; + + pwr_key: pwr { + label = "pwr_button"; + // linux,code = <205>; // KEY_SUSPEND + linux,code = <116>; // KEY_POWER + gpios = <&gio 20 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; // ms + }; + }; +}; + +&usb { + power-domains = <&power RPI_POWER_DOMAIN_USB>; +}; + +/* SDIO2 drives the WLAN interface */ +&sdio2 { + pinctrl-0 = <&sdio2_30_pins>; + pinctrl-names = "default"; + bus-width = <4>; + vmmc-supply = <&wl_on_reg>; + sd-uhs-ddr50; + non-removable; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + wifi: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + local-mac-address = [00 00 00 00 00 00]; + }; +}; + +&rpivid { + status = "okay"; +}; + +&pinctrl { + spi10_gpio2: spi10_gpio2 { + function = "vc_spi0"; + pins = "gpio2", "gpio3", "gpio4"; + bias-disable; + }; + + spi10_cs_gpio1: spi10_cs_gpio1 { + function = "gpio"; + pins = "gpio1"; + bias-pull-up; + }; +}; + +spi10_pins: &spi10_gpio2 {}; +spi10_cs_pins: &spi10_cs_gpio1 {}; + +&spi10 { + pinctrl-names = "default"; + cs-gpios = <&gio 1 1>; + pinctrl-0 = <&spi10_pins &spi10_cs_pins>; + + spidev10: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <20000000>; + status = "okay"; + }; +}; + +// ============================================= +// Board specific stuff here + +&gio_aon { + // Don't use GIO_AON as an interrupt controller because it will + // clash with the firmware monitoring the PMIC interrupt via the VPU. + + /delete-property/ interrupt-controller; +}; + +&main_aon_irq { + // Don't use the MAIN_AON_IRQ interrupt controller because it will + // clash with the firmware monitoring the PMIC interrupt via the VPU. + + status = "disabled"; +}; + +&rp1_pwm1 { + status = "disabled"; + pinctrl-0 = <&rp1_pwm1_gpio45>; + pinctrl-names = "default"; +}; + +&thermal_trips { + cpu_tepid: cpu-tepid { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_warm: cpu-warm { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_hot: cpu-hot { + temperature = <67500>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_vhot: cpu-vhot { + temperature = <75000>; + hysteresis = <5000>; + type = "active"; + }; +}; + +&cooling_maps { + tepid { + trip = <&cpu_tepid>; + cooling-device = <&fan 1 1>; + }; + + warm { + trip = <&cpu_warm>; + cooling-device = <&fan 2 2>; + }; + + hot { + trip = <&cpu_hot>; + cooling-device = <&fan 3 3>; + }; + + vhot { + trip = <&cpu_vhot>; + cooling-device = <&fan 4 4>; + }; + + melt { + trip = <&cpu_crit>; + cooling-device = <&fan 4 4>; + }; +}; + +&gio { + // The GPIOs above 35 are not used on Pi 5, so shrink the upper bank + // to reduce the clutter in gpioinfo/pinctrl + brcm,gpio-bank-widths = <32 4>; + + gpio-line-names = + "-", // GPIO_000 + "2712_BOOT_CS_N", // GPIO_001 + "2712_BOOT_MISO", // GPIO_002 + "2712_BOOT_MOSI", // GPIO_003 + "2712_BOOT_SCLK", // GPIO_004 + "-", // GPIO_005 + "-", // GPIO_006 + "-", // GPIO_007 + "-", // GPIO_008 + "-", // GPIO_009 + "-", // GPIO_010 + "-", // GPIO_011 + "-", // GPIO_012 + "-", // GPIO_013 + "PCIE_SDA", // GPIO_014 + "PCIE_SCL", // GPIO_015 + "-", // GPIO_016 + "-", // GPIO_017 + "-", // GPIO_018 + "-", // GPIO_019 + "PWR_GPIO", // GPIO_020 + "2712_G21_FS", // GPIO_021 + "-", // GPIO_022 + "-", // GPIO_023 + "BT_RTS", // GPIO_024 + "BT_CTS", // GPIO_025 + "BT_TXD", // GPIO_026 + "BT_RXD", // GPIO_027 + "WL_ON", // GPIO_028 + "BT_ON", // GPIO_029 + "WIFI_SDIO_CLK", // GPIO_030 + "WIFI_SDIO_CMD", // GPIO_031 + "WIFI_SDIO_D0", // GPIO_032 + "WIFI_SDIO_D1", // GPIO_033 + "WIFI_SDIO_D2", // GPIO_034 + "WIFI_SDIO_D3"; // GPIO_035 +}; + +&gio_aon { + gpio-line-names = + "RP1_SDA", // AON_GPIO_00 + "RP1_SCL", // AON_GPIO_01 + "RP1_RUN", // AON_GPIO_02 + "SD_IOVDD_SEL", // AON_GPIO_03 + "SD_PWR_ON", // AON_GPIO_04 + "SD_CDET_N", // AON_GPIO_05 + "SD_FLG_N", // AON_GPIO_06 + "-", // AON_GPIO_07 + "2712_WAKE", // AON_GPIO_08 + "2712_STAT_LED", // AON_GPIO_09 + "-", // AON_GPIO_10 + "-", // AON_GPIO_11 + "PMIC_INT", // AON_GPIO_12 + "UART_TX_FS", // AON_GPIO_13 + "UART_RX_FS", // AON_GPIO_14 + "-", // AON_GPIO_15 + "-", // AON_GPIO_16 + + // Pad bank0 out to 32 entries + "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", + + "HDMI0_SCL", // AON_SGPIO_00 + "HDMI0_SDA", // AON_SGPIO_01 + "HDMI1_SCL", // AON_SGPIO_02 + "HDMI1_SDA", // AON_SGPIO_03 + "PMIC_SCL", // AON_SGPIO_04 + "PMIC_SDA"; // AON_SGPIO_05 + + rp1_run_hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "RP1 RUN pin"; + }; +}; + +&rp1_gpio { + gpio-line-names = + "ID_SD", // GPIO0 + "ID_SC", // GPIO1 + "PIN3", // GPIO2 + "PIN5", // GPIO3 + "PIN7", // GPIO4 + "PIN29", // GPIO5 + "PIN31", // GPIO6 + "PIN26", // GPIO7 + "PIN24", // GPIO8 + "PIN21", // GPIO9 + "PIN19", // GPIO10 + "PIN23", // GPIO11 + "PIN32", // GPIO12 + "PIN33", // GPIO13 + "PIN8", // GPIO14 + "PIN10", // GPIO15 + "PIN36", // GPIO16 + "PIN11", // GPIO17 + "PIN12", // GPIO18 + "PIN35", // GPIO19 + "PIN38", // GPIO20 + "PIN40", // GPIO21 + "PIN15", // GPIO22 + "PIN16", // GPIO23 + "PIN18", // GPIO24 + "PIN22", // GPIO25 + "PIN37", // GPIO26 + "PIN13", // GPIO27 + + "PCIE_RP1_WAKE", // GPIO28 + "FAN_TACH", // GPIO29 + "HOST_SDA", // GPIO30 + "HOST_SCL", // GPIO31 + "ETH_RST_N", // GPIO32 + "-", // GPIO33 + + "CD0_IO0_MICCLK", // GPIO34 + "CD0_IO0_MICDAT0", // GPIO35 + "RP1_PCIE_CLKREQ_N", // GPIO36 + "-", // GPIO37 + "CD0_SDA", // GPIO38 + "CD0_SCL", // GPIO39 + "CD1_SDA", // GPIO40 + "CD1_SCL", // GPIO41 + "USB_VBUS_EN", // GPIO42 + "USB_OC_N", // GPIO43 + "RP1_STAT_LED", // GPIO44 + "FAN_PWM", // GPIO45 + "CD1_IO0_MICCLK", // GPIO46 + "2712_WAKE", // GPIO47 + "CD1_IO1_MICDAT1", // GPIO48 + "EN_MAX_USB_CUR", // GPIO49 + "-", // GPIO50 + "-", // GPIO51 + "-", // GPIO52 + "-"; // GPIO53 + + usb_vbus_pins: usb_vbus_pins { + function = "vbus1"; + pins = "gpio42", "gpio43"; + }; +}; + +/ { + aliases: aliases { + blconfig = &blconfig; + bluetooth = &bluetooth; + console = &uart10; + ethernet0 = &rp1_eth; + wifi0 = &wifi; + fb = &fb; + mailbox = &mailbox; + mmc0 = &sdio1; + uart0 = &uart0; + uart1 = &uart1; + uart2 = &uart2; + uart3 = &uart3; + uart4 = &uart4; + uart10 = &uart10; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial10 = &uart10; + i2c = &i2c_arm; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c10 = &i2c_rp1boot; + // Bit-bashed i2c_gpios start at 10 + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &spi5; + spi10 = &spi10; + gpio0 = &gpio; + gpio1 = &gio; + gpio2 = &gio_aon; + gpio3 = &pinctrl; + gpio4 = &pinctrl_aon; + usb0 = &rp1_usb0; + usb1 = &rp1_usb1; + drm-dsi1 = &dsi0; + drm-dsi2 = &dsi1; + }; + + __overrides__ { + bdaddr = <&bluetooth>, "local-bd-address["; + button_debounce = <&pwr_key>, "debounce-interval:0"; + cooling_fan = <&fan>, "status", <&rp1_pwm1>, "status"; + uart0_console = <&uart0>,"status", <&aliases>, "console=",&uart0; + i2c0 = <&i2c0>, "status"; + i2c1 = <&i2c1>, "status"; + i2c = <&i2c1>, "status"; + i2c_arm = <&i2c_arm>, "status"; + i2c_vc = <&i2c_vc>, "status"; + i2c_csi_dsi = <&i2c_csi_dsi>, "status"; + i2c_csi_dsi0 = <&i2c_csi_dsi0>, "status"; + i2c_csi_dsi1 = <&i2c_csi_dsi1>, "status"; + i2c0_baudrate = <&i2c0>, "clock-frequency:0"; + i2c1_baudrate = <&i2c1>, "clock-frequency:0"; + i2c_baudrate = <&i2c_arm>, "clock-frequency:0"; + i2c_arm_baudrate = <&i2c_arm>, "clock-frequency:0"; + i2c_vc_baudrate = <&i2c_vc>, "clock-frequency:0"; + krnbt = <&bluetooth>, "status"; + nvme = <&pciex1>, "status"; + pciex1 = <&pciex1>, "status"; + pciex1_gen = <&pciex1> , "max-link-speed:0"; + pciex1_no_l0s = <&pciex1>, "aspm-no-l0s?"; + pciex1_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0"; + pcie_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0"; + random = <&random>, "status"; + rtc_bbat_vchg = <&rpi_rtc>, "trickle-charge-microvolt:0"; + spi = <&spi0>, "status"; + suspend = <&pwr_key>, "linux,code:0=205"; + uart0 = <&uart0>, "status"; + wifiaddr = <&wifi>, "local-mac-address["; + + act_led_activelow = <&act_led>, "active-low?"; + act_led_trigger = <&act_led>, "linux,default-trigger"; + pwr_led_activelow = <&pwr_led>, "gpios:8"; + pwr_led_trigger = <&pwr_led>, "linux,default-trigger"; + drm_fb0_rp1_dsi0 = <&aliases>, "drm-fb0=",&dsi0; + drm_fb0_rp1_dsi1 = <&aliases>, "drm-fb0=",&dsi1; + drm_fb0_rp1_dpi = <&aliases>, "drm-fb0=",&dpi; + drm_fb0_vc4 = <&aliases>, "drm-fb0=",&vc4; + drm_fb1_rp1_dsi0 = <&aliases>, "drm-fb1=",&dsi0; + drm_fb1_rp1_dsi1 = <&aliases>, "drm-fb1=",&dsi1; + drm_fb1_rp1_dpi = <&aliases>, "drm-fb1=",&dpi; + drm_fb1_vc4 = <&aliases>, "drm-fb1=",&vc4; + drm_fb2_rp1_dsi0 = <&aliases>, "drm-fb2=",&dsi0; + drm_fb2_rp1_dsi1 = <&aliases>, "drm-fb2=",&dsi1; + drm_fb2_rp1_dpi = <&aliases>, "drm-fb2=",&dpi; + drm_fb2_vc4 = <&aliases>, "drm-fb2=",&vc4; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm2712-rpi.dtsi linux/arch/arm/boot/dts/bcm2712-rpi.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm2712-rpi.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm2712-rpi.dtsi 2023-12-13 11:50:48.291960548 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/power/raspberrypi-power.h> + +&soc { + firmware: firmware { + compatible = "raspberrypi,bcm2835-firmware", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + mboxes = <&mailbox>; + dma-ranges; + + firmware_clocks: clocks { + compatible = "raspberrypi,firmware-clocks"; + #clock-cells = <1>; + }; + + reset: reset { + compatible = "raspberrypi,firmware-reset"; + #reset-cells = <1>; + }; + + vcio: vcio { + compatible = "raspberrypi,vcio"; + }; + }; + + power: power { + compatible = "raspberrypi,bcm2835-power"; + firmware = <&firmware>; + #power-domain-cells = <1>; + }; + + fb: fb { + compatible = "brcm,bcm2708-fb"; + firmware = <&firmware>; + status = "okay"; + }; + + rpi_rtc: rpi_rtc { + compatible = "raspberrypi,rpi-rtc"; + firmware = <&firmware>; + status = "okay"; + trickle-charge-microvolt = <0>; + }; + + /* Define these notional regulators for use by overlays, etc. */ + vdd_3v3_reg: fixedregulator_3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3"; + }; + + vdd_5v0_reg: fixedregulator_5v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "5v0"; + }; +}; + +/ { + __overrides__ { + arm_freq; + }; +}; + +pciex1: &pcie1 { }; +pciex4: &pcie2 { }; + +&dma32 { + /* The VPU firmware uses DMA channel 11 for VCHIQ */ + brcm,dma-channel-mask = <0x03f>; +}; + +&dma40 { + /* The VPU firmware DMA channel 11 for VCHIQ */ + brcm,dma-channel-mask = <0x07c0>; +}; + +&hdmi0 { + dmas = <&dma40 (10|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; +}; + +&hdmi1 { + dmas = <&dma40 (17|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; +}; + +&spi10 { + dmas = <&dma40 6>, <&dma40 7>; + dma-names = "tx", "rx"; +}; + +&usb { + power-domains = <&power RPI_POWER_DOMAIN_USB>; +}; + +&rmem { + /* + * RPi4's co-processor will copy the board's bootloader configuration + * into memory for the OS to consume. It'll also update this node with + * its placement information. + */ + blconfig: nvram@0 { + compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x0>; + no-map; + status = "disabled"; + }; +}; + +&rp1_adc { + status = "okay"; +}; + +/* Add some gpiomem nodes to make the devices accessible to userspace. + * /dev/gpiomem<n> should expose the registers for the interface with DT alias + * gpio<n>. + */ + +&rp1 { + gpiomem@d0000 { + /* Export IO_BANKs, RIO_BANKs and PADS_BANKs to userspace */ + compatible = "raspberrypi,gpiomem"; + reg = <0xc0 0x400d0000 0x0 0x30000>; + chardev-name = "gpiomem0"; + }; +}; + +&soc { + gpiomem@7d508500 { + compatible = "raspberrypi,gpiomem"; + reg = <0x7d508500 0x40>; + chardev-name = "gpiomem1"; + }; + + gpiomem@7d517c00 { + compatible = "raspberrypi,gpiomem"; + reg = <0x7d517c00 0x40>; + chardev-name = "gpiomem2"; + }; + + gpiomem@7d504100 { + compatible = "raspberrypi,gpiomem"; + reg = <0x7d504100 0x20>; + chardev-name = "gpiomem3"; + }; + + gpiomem@7d510700 { + compatible = "raspberrypi,gpiomem"; + reg = <0x7d510700 0x20>; + chardev-name = "gpiomem4"; + }; +}; + +i2c0: &rp1_i2c0 { }; +i2c1: &rp1_i2c1 { }; +i2c2: &rp1_i2c2 { }; +i2c3: &rp1_i2c3 { }; +i2c4: &rp1_i2c4 { }; +i2c5: &rp1_i2c5 { }; +i2c6: &rp1_i2c6 { }; +i2s: &rp1_i2s0 { }; +i2s_clk_producer: &rp1_i2s0 { }; +i2s_clk_consumer: &rp1_i2s1 { }; +pwm0: &rp1_pwm0 { }; +pwm1: &rp1_pwm1 { }; +pwm: &pwm0 { }; +spi0: &rp1_spi0 { }; +spi1: &rp1_spi1 { }; +spi2: &rp1_spi2 { }; +spi3: &rp1_spi3 { }; +spi4: &rp1_spi4 { }; +spi5: &rp1_spi5 { }; + +uart0_pins: &rp1_uart0_14_15 {}; +uart0_ctsrts_pins: &rp1_uart0_ctsrts_16_17 {}; +uart0: &rp1_uart0 { + pinctrl-0 = <&uart0_pins>; +}; + +uart1_pins: &rp1_uart1_0_1 {}; +uart1_ctsrts_pins: &rp1_uart1_ctsrts_2_3 {}; +uart1: &rp1_uart1 { }; + +uart2_pins: &rp1_uart2_4_5 {}; +uart2_ctsrts_pins: &rp1_uart2_ctsrts_6_7 {}; +uart2: &rp1_uart2 { }; + +uart3_pins: &rp1_uart3_8_9 {}; +uart3_ctsrts_pins: &rp1_uart3_ctsrts_10_11 {}; +uart3: &rp1_uart3 { }; + +uart4_pins: &rp1_uart4_12_13 {}; +uart4_ctsrts_pins: &rp1_uart4_ctsrts_14_15 {}; +uart4: &rp1_uart4 { }; + +i2c_vc: &i2c0 { // This is pins 27,28 on the header (not MIPI) + pinctrl-0 = <&rp1_i2c0_0_1>; + pinctrl-names = "default"; + clock-frequency = <100000>; +}; + +i2c_arm: &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&rp1_i2c1_2_3>; + clock-frequency = <100000>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&rp1_i2c2_4_5>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&rp1_i2c3_6_7>; +}; + +&i2s_clk_producer { + pinctrl-names = "default"; + pinctrl-0 = <&rp1_i2s0_18_21>; +}; + +&i2s_clk_consumer { + pinctrl-names = "default"; + pinctrl-0 = <&rp1_i2s1_18_21>; +}; + +spi0_pins: &rp1_spi0_gpio9 {}; +spi0_cs_pins: &rp1_spi0_cs_gpio7 {}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_pins>; + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + + spidev0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; + + spidev1: spidev@1 { + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + }; +}; + +spi2_pins: &rp1_spi2_gpio1 {}; +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins>; +}; + +spi3_pins: &rp1_spi3_gpio5 {}; +&spi3 { + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins>; +}; + +spi4_pins: &rp1_spi4_gpio9 {}; +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins>; +}; + +spi5_pins: &rp1_spi5_gpio13 {}; +&spi5 { + pinctrl-names = "default"; + pinctrl-0 = <&spi5_pins>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm271x-rpi-bt.dtsi linux/arch/arm/boot/dts/bcm271x-rpi-bt.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm271x-rpi-bt.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm271x-rpi-bt.dtsi 2023-12-13 11:50:48.292960550 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 + +&uart0 { + bt: bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; + local-bd-address = [ 00 00 00 00 00 00 ]; + fallback-bd-address; // Don't override a valid address + status = "okay"; + }; +}; + +&uart1 { + minibt: bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <230400>; + shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; + local-bd-address = [ 00 00 00 00 00 00 ]; + fallback-bd-address; // Don't override a valid address + status = "disabled"; + }; +}; + +/ { + aliases { + bluetooth = &bt; + }; + + __overrides__ { + bdaddr = <&bt>,"local-bd-address[", + <&bt>,"fallback-bd-address?=0", + <&minibt>,"local-bd-address[", + <&minibt>,"fallback-bd-address?=0"; + krnbt = <&bt>,"status"; + krnbt_baudrate = <&bt>,"max-speed:0", <&minibt>,"max-speed:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi linux/arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi 2023-12-13 11:50:48.296960560 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +// SPDX-License-Identifier: GPL-2.0-only +&csi0 { + brcm,num-data-lanes = <2>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi linux/arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi 2023-12-13 11:50:48.296960560 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +// SPDX-License-Identifier: GPL-2.0-only +&csi1 { + brcm,num-data-lanes = <2>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi linux/arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi 2023-12-13 11:50:48.296960560 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +// SPDX-License-Identifier: GPL-2.0-only +&csi1 { + brcm,num-data-lanes = <4>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_28.dtsi linux/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_28.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_28.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_28.dtsi 2023-12-13 11:50:48.296960560 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +&i2c0mux { + pinctrl-0 = <&i2c0_gpio0>; + pinctrl-1 = <&i2c0_gpio28>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_44.dtsi linux/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_44.dtsi --- linux-6.1.66/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_44.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_44.dtsi 2023-12-13 11:50:48.296960560 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +&i2c0mux { + pinctrl-0 = <&i2c0_gpio0>; + pinctrl-1 = <&i2c0_gpio44>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/Makefile linux/arch/arm/boot/dts/Makefile --- linux-6.1.66/arch/arm/boot/dts/Makefile 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/boot/dts/Makefile 2023-12-13 11:50:48.202960338 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ # SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_BCM2835) += \ + bcm2708-rpi-b.dtb \ + bcm2708-rpi-b-rev1.dtb \ + bcm2708-rpi-b-plus.dtb \ + bcm2708-rpi-cm.dtb \ + bcm2708-rpi-zero.dtb \ + bcm2708-rpi-zero-w.dtb \ + bcm2710-rpi-zero-2.dtb \ + bcm2710-rpi-zero-2-w.dtb \ + bcm2709-rpi-2-b.dtb \ + bcm2710-rpi-2-b.dtb \ + bcm2710-rpi-3-b.dtb \ + bcm2710-rpi-3-b-plus.dtb \ + bcm2711-rpi-4-b.dtb \ + bcm2711-rpi-400.dtb \ + bcm2709-rpi-cm2.dtb \ + bcm2710-rpi-cm3.dtb \ + bcm2711-rpi-cm4.dtb \ + bcm2711-rpi-cm4s.dtb \ + bcm2712-rpi-5-b.dtb + dtb-$(CONFIG_ARCH_ALPINE) += \ alpine-db.dtb dtb-$(CONFIG_MACH_ARTPEC6) += \ @ linux/arch/arm/boot/dts/bcm2708.dtsi:1666 @ aspeed-bmc-vegman-n110.dtb \ aspeed-bmc-vegman-rx20.dtb \ aspeed-bmc-vegman-sx20.dtb + +targets += dtbs dtbs_install +targets += $(dtb-y) + +subdir-y := overlays + +# Enable fixups to support overlays on BCM2835 platforms +ifeq ($(CONFIG_ARCH_BCM2835),y) + DTC_FLAGS += -@ +endif diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/act-led-overlay.dts linux/arch/arm/boot/dts/overlays/act-led-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/act-led-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/act-led-overlay.dts 2023-12-13 11:50:48.586961242 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/* Pi3 uses a GPIO expander to drive the LEDs which can only be accessed + from the VPU. There is a special driver for this with a separate DT node, + which has the unfortunate consequence of breaking the act_led_gpio and + act_led_activelow dtparams. + + This overlay changes the GPIO controller back to the standard one and + restores the dtparams. +*/ + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&act_led>; + frag0: __overlay__ { + gpios = <&gpio 0 0>; + }; + }; + + __overrides__ { + gpio = <&frag0>,"gpios:4", + <&frag0>,"status=okay"; + activelow = <&frag0>,"gpios:8"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/adafruit18-overlay.dts linux/arch/arm/boot/dts/overlays/adafruit18-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/adafruit18-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/adafruit18-overlay.dts 2023-12-13 11:50:48.587961245 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for Adafruit 1.8" TFT LCD with ST7735R chip 160x128 + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + af18: adafruit18@0 { + compatible = "fbtft,adafruit18"; + reg = <0>; + pinctrl-names = "default"; + spi-max-frequency = <40000000>; + rotate = <90>; + buswidth = <8>; + fps = <50>; + height = <160>; + width = <128>; + reset-gpios = <&gpio 25 1>; + dc-gpios = <&gpio 24 0>; + led-gpios = <&gpio 18 0>; + debug = <0>; + }; + }; + }; + + __overrides__ { + green = <&af18>, "compatible=fbtft,adafruit18_green"; + speed = <&af18>,"spi-max-frequency:0"; + rotate = <&af18>,"rotate:0"; + fps = <&af18>,"fps:0"; + bgr = <&af18>,"bgr?"; + debug = <&af18>,"debug:0"; + dc_pin = <&af18>,"dc-gpios:4"; + reset_pin = <&af18>,"reset-gpios:4"; + led_pin = <&af18>,"led-gpios:4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/adafruit-st7735r-overlay.dts linux/arch/arm/boot/dts/overlays/adafruit-st7735r-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/adafruit-st7735r-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/adafruit-st7735r-overlay.dts 2023-12-13 11:50:48.586961242 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * adafruit-st7735r-overlay.dts + * + * ST7735R based SPI LCD displays. Either + * Adafruit 1.8" 160x128 + * or + * Okaya 1.44" 128x128 + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + adafruit_pins: adafruit_pins { + brcm,pins = <25 24>; + brcm,function = <1>; /* out */ + }; + backlight_pins: backlight_pins { + brcm,pins = <18>; + brcm,function = <1>; /* out */ + }; + }; + }; + + fragment@2 { + target-path = "/"; + __overlay__ { + af18_backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + }; + }; + }; + + fragment@3 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + af18: adafruit18@0 { + compatible = "jianda,jd-t18003-t01"; + reg = <0>; + spi-max-frequency = <32000000>; + dc-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + rotation = <90>; + pinctrl-names = "default"; + pinctrl-0 = <&adafruit_pins>; + backlight = <&af18_backlight>; + }; + }; + }; + + __overrides__ { + 128x128 = <&af18>, "compatible=okaya,rh128128t"; + speed = <&af18>,"spi-max-frequency:0"; + rotate = <&af18>,"rotation:0"; + dc_pin = <&af18>,"dc-gpios:4", <&adafruit_pins>,"brcm,pins:4"; + reset_pin = <&af18>,"reset-gpios:4", + <&adafruit_pins>,"brcm,pins:0"; + led_pin = <&af18_backlight>,"gpios:4", + <&backlight_pins>,"brcm,pins:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/adau1977-adc-overlay.dts linux/arch/arm/boot/dts/overlays/adau1977-adc-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/adau1977-adc-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/adau1977-adc-overlay.dts 2023-12-13 11:50:48.587961245 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for ADAU1977 ADC +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + adau1977: codec@11 { + compatible = "adi,adau1977"; + reg = <0x11>; + reset-gpios = <&gpio 5 0>; + AVDD-supply = <&vdd_3v3_reg>; + }; + }; + }; + + fragment@1 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "adi,adau1977-adc"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/adau7002-simple-overlay.dts linux/arch/arm/boot/dts/overlays/adau7002-simple-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/adau7002-simple-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/adau7002-simple-overlay.dts 2023-12-13 11:50:48.587961245 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + adau7002_codec: adau7002-codec { + #sound-dai-cells = <0>; + compatible = "adi,adau7002"; +/* IOVDD-supply = <&supply>;*/ + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + sound_overlay: __overlay__ { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "adau7002"; + simple-audio-card,bitclock-slave = <&dailink0_slave>; + simple-audio-card,frame-slave = <&dailink0_slave>; + simple-audio-card,widgets = + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "PDM_DAT", "Microphone Jack"; + status = "okay"; + simple-audio-card,cpu { + sound-dai = <&i2s_clk_producer>; + }; + dailink0_slave: simple-audio-card,codec { + sound-dai = <&adau7002_codec>; + }; + }; + }; + + + __overrides__ { + card-name = <&sound_overlay>,"simple-audio-card,name"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ads1015-overlay.dts linux/arch/arm/boot/dts/overlays/ads1015-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ads1015-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ads1015-overlay.dts 2023-12-13 11:50:48.587961245 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * 2016 - Erik Sejr + */ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + /* ----------- ADS1015 ------------ */ + fragment@0 { + target = <&i2c_arm>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + ads1015: ads1015@48 { + compatible = "ti,ads1015"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x48>; + }; + }; + }; + + fragment@1 { + target = <&ads1015>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + channel_a: channel_a { + reg = <4>; + ti,gain = <2>; + ti,datarate = <4>; + }; + }; + }; + + fragment@2 { + target = <&ads1015>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + channel_b: channel_b { + reg = <5>; + ti,gain = <2>; + ti,datarate = <4>; + }; + }; + }; + + fragment@3 { + target = <&ads1015>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + channel_c: channel_c { + reg = <6>; + ti,gain = <2>; + ti,datarate = <4>; + }; + }; + }; + + fragment@4 { + target = <&ads1015>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + channel_d: channel_d { + reg = <7>; + ti,gain = <2>; + ti,datarate = <4>; + }; + }; + }; + + __overrides__ { + addr = <&ads1015>,"reg:0"; + cha_enable = <0>,"=1"; + cha_cfg = <&channel_a>,"reg:0"; + cha_gain = <&channel_a>,"ti,gain:0"; + cha_datarate = <&channel_a>,"ti,datarate:0"; + chb_enable = <0>,"=2"; + chb_cfg = <&channel_b>,"reg:0"; + chb_gain = <&channel_b>,"ti,gain:0"; + chb_datarate = <&channel_b>,"ti,datarate:0"; + chc_enable = <0>,"=3"; + chc_cfg = <&channel_c>,"reg:0"; + chc_gain = <&channel_c>,"ti,gain:0"; + chc_datarate = <&channel_c>,"ti,datarate:0"; + chd_enable = <0>,"=4"; + chd_cfg = <&channel_d>,"reg:0"; + chd_gain = <&channel_d>,"ti,gain:0"; + chd_datarate = <&channel_d>,"ti,datarate:0"; + }; + +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ads1115-overlay.dts linux/arch/arm/boot/dts/overlays/ads1115-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ads1115-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ads1115-overlay.dts 2023-12-13 11:50:48.587961245 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * TI ADS1115 multi-channel ADC overlay + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&ads1115>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + channel_a: channel_a { + reg = <4>; + ti,gain = <1>; + ti,datarate = <7>; + }; + }; + }; + + fragment@1 { + target = <&ads1115>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + channel_b: channel_b { + reg = <5>; + ti,gain = <1>; + ti,datarate = <7>; + }; + }; + }; + + fragment@2 { + target = <&ads1115>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + channel_c: channel_c { + reg = <6>; + ti,gain = <1>; + ti,datarate = <7>; + }; + }; + }; + + fragment@3 { + target = <&ads1115>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + channel_d: channel_d { + reg = <7>; + ti,gain = <1>; + ti,datarate = <7>; + }; + }; + }; + + fragment@4 { + target = <&i2cbus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ads1115: ads1115@48 { + compatible = "ti,ads1115"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x48>; + }; + }; + }; + + frag100: fragment@100 { + target = <&i2c1>; + i2cbus: __overlay__ { + status = "okay"; + }; + }; + + fragment@101 { + target = <&i2c0if>; + __dormant__ { + status = "okay"; + }; + }; + + fragment@102 { + target = <&i2c0mux>; + __dormant__ { + status = "okay"; + }; + }; + + __overrides__ { + addr = <&ads1115>,"reg:0"; + cha_enable = <0>,"=0"; + cha_cfg = <&channel_a>,"reg:0"; + cha_gain = <&channel_a>,"ti,gain:0"; + cha_datarate = <&channel_a>,"ti,datarate:0"; + chb_enable = <0>,"=1"; + chb_cfg = <&channel_b>,"reg:0"; + chb_gain = <&channel_b>,"ti,gain:0"; + chb_datarate = <&channel_b>,"ti,datarate:0"; + chc_enable = <0>,"=2"; + chc_cfg = <&channel_c>,"reg:0"; + chc_gain = <&channel_c>,"ti,gain:0"; + chc_datarate = <&channel_c>,"ti,datarate:0"; + chd_enable = <0>,"=3"; + chd_cfg = <&channel_d>,"reg:0"; + chd_gain = <&channel_d>,"ti,gain:0"; + chd_datarate = <&channel_d>,"ti,datarate:0"; + i2c0 = <&frag100>, "target:0=",<&i2c0>; + i2c_csi_dsi = <&frag100>, "target:0=",<&i2c_csi_dsi>, + <0>,"+101+102"; + i2c3 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c3"; + i2c4 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c4"; + i2c5 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c5"; + i2c6 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c6"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ads7846-overlay.dts linux/arch/arm/boot/dts/overlays/ads7846-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ads7846-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ads7846-overlay.dts 2023-12-13 11:50:48.587961245 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Generic Device Tree overlay for the ADS7846 touch controller + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + ads7846_pins: ads7846_pins { + brcm,pins = <255>; /* illegal default value */ + brcm,function = <0>; /* in */ + brcm,pull = <0>; /* none */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + ads7846: ads7846@1 { + compatible = "ti,ads7846"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&ads7846_pins>; + + spi-max-frequency = <2000000>; + interrupts = <255 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; + pendown-gpio = <&gpio 255 0>; + + /* driver defaults */ + ti,x-min = /bits/ 16 <0>; + ti,y-min = /bits/ 16 <0>; + ti,x-max = /bits/ 16 <0x0FFF>; + ti,y-max = /bits/ 16 <0x0FFF>; + ti,pressure-min = /bits/ 16 <0>; + ti,pressure-max = /bits/ 16 <0xFFFF>; + ti,x-plate-ohms = /bits/ 16 <400>; + }; + }; + }; + __overrides__ { + cs = <&ads7846>,"reg:0"; + speed = <&ads7846>,"spi-max-frequency:0"; + penirq = <&ads7846_pins>,"brcm,pins:0", /* REQUIRED */ + <&ads7846>,"interrupts:0", + <&ads7846>,"pendown-gpio:4"; + penirq_pull = <&ads7846_pins>,"brcm,pull:0"; + swapxy = <&ads7846>,"ti,swap-xy?"; + xmin = <&ads7846>,"ti,x-min;0"; + ymin = <&ads7846>,"ti,y-min;0"; + xmax = <&ads7846>,"ti,x-max;0"; + ymax = <&ads7846>,"ti,y-max;0"; + pmin = <&ads7846>,"ti,pressure-min;0"; + pmax = <&ads7846>,"ti,pressure-max;0"; + xohms = <&ads7846>,"ti,x-plate-ohms;0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/adv7282m-overlay.dts linux/arch/arm/boot/dts/overlays/adv7282m-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/adv7282m-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/adv7282m-overlay.dts 2023-12-13 11:50:48.587961245 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for Analog Devices ADV7282-M video to CSI2 bridge on VC I2C bus +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + adv728x: adv728x@21 { + compatible = "adi,adv7282-m"; + reg = <0x21>; + status = "okay"; + clock-frequency = <24000000>; + port { + adv728x_0: endpoint { + remote-endpoint = <&csi1_ep>; + clock-lanes = <0>; + data-lanes = <1>; + link-frequencies = + /bits/ 64 <297000000>; + + mclk-frequency = <12000000>; + }; + }; + }; + }; + }; + fragment@1 { + target = <&csi1>; + __overlay__ { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&adv728x_0>; + data-lanes = <1>; + }; + }; + }; + }; + fragment@2 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&csi1>; + __dormant__ { + brcm,media-controller; + }; + }; + + __overrides__ { + addr = <&adv728x>,"reg:0"; + media-controller = <0>,"=4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/adv728x-m-overlay.dts linux/arch/arm/boot/dts/overlays/adv728x-m-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/adv728x-m-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/adv728x-m-overlay.dts 2023-12-13 11:50:48.588961247 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for Analog Devices ADV728[0|1|2]-M video to CSI2 bridges on VC +// I2C bus + +#include "adv7282m-overlay.dts" + +/{ + compatible = "brcm,bcm2835"; + + // Fragment numbers deliberately high to avoid conflicts with the + // included adv7282m overlay file. + + fragment@101 { + target = <&adv728x>; + __dormant__ { + compatible = "adi,adv7280-m"; + }; + }; + fragment@102 { + target = <&adv728x>; + __dormant__ { + compatible = "adi,adv7281-m"; + }; + }; + fragment@103 { + target = <&adv728x>; + __dormant__ { + compatible = "adi,adv7281-ma"; + }; + }; + + __overrides__ { + adv7280m = <0>, "+101"; + adv7281m = <0>, "+102"; + adv7281ma = <0>, "+103"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/akkordion-iqdacplus-overlay.dts linux/arch/arm/boot/dts/overlays/akkordion-iqdacplus-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/akkordion-iqdacplus-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/akkordion-iqdacplus-overlay.dts 2023-12-13 11:50:48.588961247 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for Digital Dreamtime Akkordion using IQaudIO DAC+ or DACZero +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pcm5122@4c { + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + reg = <0x4c>; + AVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + CPVDD-supply = <&vdd_3v3_reg>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + frag2: __overlay__ { + compatible = "iqaudio,iqaudio-dac"; + card_name = "Akkordion"; + dai_name = "IQaudIO DAC"; + dai_stream_name = "IQaudIO DAC HiFi"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; + + __overrides__ { + 24db_digital_gain = <&frag2>,"iqaudio,24db_digital_gain?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/allo-boss2-dac-audio-overlay.dts linux/arch/arm/boot/dts/overlays/allo-boss2-dac-audio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/allo-boss2-dac-audio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/allo-boss2-dac-audio-overlay.dts 2023-12-13 11:50:48.588961247 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* * Definitions for Allo Boss2 DAC boards + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + #sound-dai-cells = <0>; + status = "okay"; + cpu_port: port { + cpu_endpoint: endpoint { + remote-endpoint = <&codec_endpoint>; + bitclock-master = <&codec_endpoint>; + frame-master = <&codec_endpoint>; + dai-format = "i2s"; + }; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + allo-cs43130@30 { + #sound-dai-cells = <0>; + compatible = "allo,allo-cs43198"; + clock44-gpio = <&gpio 5 0>; + clock48-gpio = <&gpio 6 0>; + reg = <0x30>; + port { + codec_endpoint: endpoint { + remote-endpoint = <&cpu_endpoint>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&sound>; + boss2_dac: __overlay__ { + compatible = "audio-graph-card"; + label = "Allo Boss2"; + dais = <&cpu_port>; + status = "okay"; + }; + }; +}; + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/allo-boss-dac-pcm512x-audio-overlay.dts linux/arch/arm/boot/dts/overlays/allo-boss-dac-pcm512x-audio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/allo-boss-dac-pcm512x-audio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/allo-boss-dac-pcm512x-audio-overlay.dts 2023-12-13 11:50:48.588961247 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Definitions for Allo Boss DAC board + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + boss_osc: boss_osc { + compatible = "allo,dac-clk"; + #clock-cells = <0>; + }; + }; + }; + + frag1: fragment@1 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pcm5122@4d { + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + clocks = <&boss_osc>; + reg = <0x4d>; + status = "okay"; + }; + }; + }; + + fragment@3 { + target = <&sound>; + boss_dac: __overlay__ { + compatible = "allo,boss-dac"; + i2s-controller = <&i2s_clk_consumer>; + mute-gpios = <&gpio 6 1>; + status = "okay"; + }; + }; + + __overrides__ { + 24db_digital_gain = <&boss_dac>,"allo,24db_digital_gain?"; + slave = <&boss_dac>,"allo,slave?", + <&frag1>,"target:0=",<&i2s_clk_producer>, + <&boss_dac>,"i2s-controller:0=",<&i2s_clk_producer>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/allo-digione-overlay.dts linux/arch/arm/boot/dts/overlays/allo-digione-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/allo-digione-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/allo-digione-overlay.dts 2023-12-13 11:50:48.588961247 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for Allo DigiOne +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wm8804@3b { + #sound-dai-cells = <0>; + compatible = "wlf,wm8804"; + reg = <0x3b>; + PVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + status = "okay"; + wlf,reset-gpio = <&gpio 17 0>; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "allo,allo-digione"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + clock44-gpio = <&gpio 5 0>; + clock48-gpio = <&gpio 6 0>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/allo-katana-dac-audio-overlay.dts linux/arch/arm/boot/dts/overlays/allo-katana-dac-audio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/allo-katana-dac-audio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/allo-katana-dac-audio-overlay.dts 2023-12-13 11:50:48.588961247 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Definitions for Allo Katana DAC boards + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + #sound-dai-cells = <0>; + status = "okay"; + cpu_port: port { + cpu_endpoint: endpoint { + remote-endpoint = <&codec_endpoint>; + bitclock-master = <&codec_endpoint>; + frame-master = <&codec_endpoint>; + dai-format = "i2s"; + }; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + clock-frequency = <50000>; + + allo-katana-codec@30 { + #sound-dai-cells = <0>; + compatible = "allo,allo-katana-codec"; + reg = <0x30>; + port { + codec_endpoint: endpoint { + remote-endpoint = <&cpu_endpoint>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&sound>; + katana_dac: __overlay__ { + compatible = "audio-graph-card"; + label = "Allo Katana"; + dais = <&cpu_port>; + status = "okay"; + }; + }; +}; + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/allo-piano-dac-pcm512x-audio-overlay.dts linux/arch/arm/boot/dts/overlays/allo-piano-dac-pcm512x-audio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/allo-piano-dac-pcm512x-audio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/allo-piano-dac-pcm512x-audio-overlay.dts 2023-12-13 11:50:48.588961247 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Definitions for Allo Piano DAC (2.0/2.1) boards + * + * NB. The Piano DAC 2.1 board contains 2x TI PCM5142 DAC's. One DAC is stereo + * (left/right) and the other provides a subwoofer output, using DSP on the + * chip for digital high/low pass crossover. + * The initial support for this hardware, that doesn't require any codec driver + * modifications, uses only one DAC chip for stereo (left/right) output, the + * chip with 0x4c slave address. The other chip at 0x4d is currently ignored! + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pcm5142@4c { + #sound-dai-cells = <0>; + compatible = "ti,pcm5142"; + reg = <0x4c>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + piano_dac: __overlay__ { + compatible = "allo,piano-dac"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; + + __overrides__ { + 24db_digital_gain = + <&piano_dac>,"allo,24db_digital_gain?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts linux/arch/arm/boot/dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts 2023-12-13 11:50:48.588961247 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for Piano DAC +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + allo_pcm5122_4c: pcm5122@4c { + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + reg = <0x4c>; + sound-name-prefix = "Main"; + status = "okay"; + }; + allo_pcm5122_4d: pcm5122@4d { + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + reg = <0x4d>; + sound-name-prefix = "Sub"; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + piano_dac: __overlay__ { + compatible = "allo,piano-dac-plus"; + audio-codec = <&allo_pcm5122_4c &allo_pcm5122_4d>; + i2s-controller = <&i2s_clk_producer>; + mute1-gpios = <&gpio 6 1>; + mute2-gpios = <&gpio 25 1>; + status = "okay"; + }; + }; + + __overrides__ { + 24db_digital_gain = + <&piano_dac>,"allo,24db_digital_gain?"; + glb_mclk = + <&piano_dac>,"allo,glb_mclk?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/anyspi-overlay.dts linux/arch/arm/boot/dts/overlays/anyspi-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/anyspi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/anyspi-overlay.dts 2023-12-13 11:50:48.589961249 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Universal device tree overlay for SPI devices + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&spidev1>; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@2 { + target-path = "spi1/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@3 { + target-path = "spi1/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@4 { + target-path = "spi1/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@5 { + target-path = "spi2/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@6 { + target-path = "spi2/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@7 { + target-path = "spi2/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@8 { + target = <&spi0>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + anyspi_00: anyspi@0 { + reg = <0>; + spi-max-frequency = <500000>; + }; + }; + }; + + fragment@9 { + target = <&spi0>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + anyspi_01: anyspi@1 { + reg = <1>; + spi-max-frequency = <500000>; + }; + }; + }; + + fragment@10 { + target = <&spi1>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + anyspi_10: anyspi@0 { + reg = <0>; + spi-max-frequency = <500000>; + }; + }; + }; + + fragment@11 { + target = <&spi1>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + anyspi_11: anyspi@1 { + reg = <1>; + spi-max-frequency = <500000>; + }; + }; + }; + + fragment@12 { + target = <&spi1>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + anyspi_12: anyspi@2 { + reg = <2>; + spi-max-frequency = <500000>; + }; + }; + }; + + fragment@13 { + target = <&spi2>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + anyspi_20: anyspi@0 { + reg = <0>; + spi-max-frequency = <500000>; + }; + }; + }; + + fragment@14 { + target = <&spi2>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + anyspi_21: anyspi@1 { + reg = <1>; + spi-max-frequency = <500000>; + }; + }; + }; + + fragment@15 { + target = <&spi2>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + anyspi_22: anyspi@2 { + reg = <2>; + spi-max-frequency = <500000>; + }; + }; + }; + + __overrides__ { + spi0-0 = <0>, "+0+8"; + spi0-1 = <0>, "+1+9"; + spi1-0 = <0>, "+2+10"; + spi1-1 = <0>, "+3+11"; + spi1-2 = <0>, "+4+12"; + spi2-0 = <0>, "+5+13"; + spi2-1 = <0>, "+6+14"; + spi2-2 = <0>, "+7+15"; + dev = <&anyspi_00>,"compatible", + <&anyspi_01>,"compatible", + <&anyspi_10>,"compatible", + <&anyspi_11>,"compatible", + <&anyspi_12>,"compatible", + <&anyspi_20>,"compatible", + <&anyspi_21>,"compatible", + <&anyspi_22>,"compatible"; + speed = <&anyspi_00>, "spi-max-frequency:0", + <&anyspi_01>, "spi-max-frequency:0", + <&anyspi_10>, "spi-max-frequency:0", + <&anyspi_11>, "spi-max-frequency:0", + <&anyspi_12>, "spi-max-frequency:0", + <&anyspi_20>, "spi-max-frequency:0", + <&anyspi_21>, "spi-max-frequency:0", + <&anyspi_22>, "spi-max-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/apds9960-overlay.dts linux/arch/arm/boot/dts/overlays/apds9960-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/apds9960-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/apds9960-overlay.dts 2023-12-13 11:50:48.589961249 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for APDS-9960 ambient light and gesture sensor + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + apds9960_pins: apds9960_pins@39 { + brcm,pins = <4>; + brcm,function = <0>; + }; + }; + }; + + fragment@2 { + target = <&apds9960>; + apds9960_irq: __overlay__ { + #interrupt-cells = <2>; + interrupt-parent = <&gpio>; + interrupts = <4 1>; + }; + }; + + fragment@3 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + apds9960: apds@39 { + compatible = "avago,apds9960"; + reg = <0x39>; + status = "okay"; + }; + }; + }; + + __overrides__ { + gpiopin = <&apds9960_pins>,"brcm,pins:0", + <&apds9960_irq>,"interrupts:0"; + noints = <0>,"!1!2"; + }; +}; + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/applepi-dac-overlay.dts linux/arch/arm/boot/dts/overlays/applepi-dac-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/applepi-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/applepi-dac-overlay.dts 2023-12-13 11:50:48.589961249 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&sound>; + __overlay__ { + compatible = "simple-audio-card"; + simple-audio-card,name = "ApplePi-DAC"; + + status = "okay"; + + playback_link: simple-audio-card,dai-link@1 { + format = "i2s"; + + p_cpu_dai: cpu { + sound-dai = <&i2s_clk_producer>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + + p_codec_dai: codec { + sound-dai = <&codec_out>; + }; + }; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + codec_out: pcm1794a-codec { + #sound-dai-cells = <0>; + compatible = "ti,pcm1794a"; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&i2s_clk_producer>; + __overlay__ { + #sound-dai-cells = <0>; + status = "okay"; + }; + }; +}; + +/* + Written by: Leonid Ayzenshtat + Company: Orchard Audio (www.orchardaudio.com) + + compile with: + dtc -@ -H epapr -O dtb -o ApplePi-DAC.dtbo -W no-unit_address_vs_reg ApplePi-DAC.dts +*/ diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/arducam-64mp.dtsi linux/arch/arm/boot/dts/overlays/arducam-64mp.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/arducam-64mp.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/arducam-64mp.dtsi 2023-12-13 11:50:48.589961249 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Fragment that configures a Arducam64MP + +cam_node: arducam_64mp@1a { + compatible = "arducam,64mp"; + reg = <0x1a>; + status = "disabled"; + + clocks = <&cam1_clk>; + clock-names = "xclk"; + + VANA-supply = <&cam1_reg>; /* 2.8v */ + VDIG-supply = <&cam_dummy_reg>; /* 1.8v */ + VDDL-supply = <&cam_dummy_reg>; /* 1.2v */ + + rotation = <0>; + orientation = <2>; + + port { + cam_endpoint: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <456000000>; + }; + }; +}; + +vcm_node: dw9817_arducam64mp@c { + compatible = "dongwoon,dw9817-vcm"; + reg = <0x0c>; + status = "disabled"; + VDD-supply = <&cam1_reg>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/arducam-64mp-overlay.dts linux/arch/arm/boot/dts/overlays/arducam-64mp-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/arducam-64mp-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/arducam-64mp-overlay.dts 2023-12-13 11:50:48.589961249 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for Arducam 64MP camera module on VC I2C bus +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + i2c_frag: fragment@0 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + #include "arducam-64mp.dtsi" + }; + }; + + csi_frag: fragment@1 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + brcm,media-controller; + + port{ + csi_ep: endpoint{ + remote-endpoint = <&cam_endpoint>; + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + }; + }; + }; + }; + + fragment@2 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + clk_frag: fragment@3 { + target = <&cam1_clk>; + __overlay__ { + clock-frequency = <24000000>; + status = "okay"; + }; + }; + + fragment@4 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&cam_node>; + __overlay__ { + lens-focus = <&vcm_node>; + }; + }; + + __overrides__ { + rotation = <&cam_node>,"rotation:0"; + orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <&cam_node>, "clocks:0=",<&cam0_clk>, + <&cam_node>, "VANA-supply:0=",<&cam0_reg>, + <&vcm_node>, "VDD-supply:0=", <&cam0_reg>; + vcm = <&vcm_node>, "status", + <0>, "=5"; + }; +}; + +&cam_node { + status = "okay"; +}; + +&cam_endpoint { + remote-endpoint = <&csi_ep>; +}; + +&vcm_node { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/arducam-pivariety-overlay.dts linux/arch/arm/boot/dts/overlays/arducam-pivariety-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/arducam-pivariety-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/arducam-pivariety-overlay.dts 2023-12-13 11:50:48.589961249 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for Arducam Pivariety camera module on VC I2C bus +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + i2c_frag: fragment@0 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + arducam_pivariety: arducam_pivariety@c { + compatible = "arducam,arducam-pivariety"; + reg = <0x0c>; + status = "okay"; + + clocks = <&cam1_clk>; + clock-names = "xclk"; + + VANA-supply = <&cam1_reg>; /* 2.8v */ + VDIG-supply = <&cam_dummy_reg>; /* 1.8v */ + VDDL-supply = <&cam_dummy_reg>; /* 1.2v */ + + rotation = <0>; + orientation = <2>; + + port { + arducam_pivariety_0: endpoint { + remote-endpoint = <&csi1_ep>; + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <493500000>; + }; + }; + }; + }; + }; + + csi_frag: fragment@1 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + brcm,media-controller; + + port{ + csi1_ep: endpoint{ + remote-endpoint = <&arducam_pivariety_0>; + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + }; + }; + }; + }; + + fragment@2 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + clk_frag: fragment@3 { + target = <&cam1_clk>; + __overlay__ { + clock-frequency = <24000000>; + status = "okay"; + }; + }; + + fragment@4 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + __overrides__ { + rotation = <&arducam_pivariety>,"rotation:0"; + orientation = <&arducam_pivariety>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <&arducam_pivariety>, "clocks:0=",<&cam0_clk>, + <&arducam_pivariety>, "VANA-supply:0=",<&cam0_reg>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/at86rf233-overlay.dts linux/arch/arm/boot/dts/overlays/at86rf233-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/at86rf233-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/at86rf233-overlay.dts 2023-12-13 11:50:48.589961249 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/* Overlay for Atmel AT86RF233 IEEE 802.15.4 WPAN transceiver on spi0.0 */ + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + lowpan0: at86rf233@0 { + compatible = "atmel,at86rf233"; + reg = <0>; + interrupt-parent = <&gpio>; + interrupts = <23 4>; /* active high */ + reset-gpio = <&gpio 24 1>; + sleep-gpio = <&gpio 25 1>; + spi-max-frequency = <3000000>; + xtal-trim = /bits/ 8 <0xf>; + }; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + lowpan0_pins: lowpan0_pins { + brcm,pins = <23 24 25>; + brcm,function = <0 1 1>; /* in out out */ + }; + }; + }; + + __overrides__ { + interrupt = <&lowpan0>, "interrupts:0", + <&lowpan0_pins>, "brcm,pins:0"; + reset = <&lowpan0>, "reset-gpio:4", + <&lowpan0_pins>, "brcm,pins:4"; + sleep = <&lowpan0>, "sleep-gpio:4", + <&lowpan0_pins>, "brcm,pins:8"; + speed = <&lowpan0>, "spi-max-frequency:0"; + trim = <&lowpan0>, "xtal-trim.0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts linux/arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts 2023-12-13 11:50:48.590961252 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for audioinjector.net audio add on soundcard +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + cs42448_mclk: codec-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <49152000>; + }; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cs42448: cs42448@48 { + #sound-dai-cells = <0>; + compatible = "cirrus,cs42448"; + reg = <0x48>; + clocks = <&cs42448_mclk>; + clock-names = "mclk"; + status = "okay"; + }; + }; + }; + + fragment@3 { + target = <&sound>; + snd: __overlay__ { + compatible = "ai,audioinjector-octo-soundcard"; + mult-gpios = <&gpio 27 0>, <&gpio 22 0>, <&gpio 23 0>, + <&gpio 24 0>; + reset-gpios = <&gpio 5 0>; + i2s-controller = <&i2s_clk_producer>; + codec = <&cs42448>; + status = "okay"; + }; + }; + + __overrides__ { + non-stop-clocks = <&snd>, "non-stop-clocks?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/audioinjector-bare-i2s-overlay.dts linux/arch/arm/boot/dts/overlays/audioinjector-bare-i2s-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/audioinjector-bare-i2s-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/audioinjector-bare-i2s-overlay.dts 2023-12-13 11:50:48.590961252 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for audioinjector.net audio soundcard +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + codec_bare: codec_bare { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "simple-audio-card"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + + simple-audio-card,name = "audioinjector-bare"; + simple-audio-card,format = "i2s"; + + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + + dailink0_master: simple-audio-card,cpu { + sound-dai = <&i2s_clk_producer>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + + snd_codec: simple-audio-card,codec { + sound-dai = <&codec_bare>; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts linux/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts 2023-12-13 11:50:48.590961252 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for audioinjector.net audio isolated soundcard +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + cs4272_mclk: codec-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cs4272: cs4271@10 { + #sound-dai-cells = <0>; + compatible = "cirrus,cs4271"; + reg = <0x10>; + reset-gpio = <&gpio 5 0>; + clocks = <&cs4272_mclk>; + clock-names = "mclk"; + status = "okay"; + }; + }; + }; + + fragment@3 { + target = <&sound>; + snd: __overlay__ { + compatible = "ai,audioinjector-isolated-soundcard"; + mute-gpios = <&gpio 17 0>; + i2s-controller = <&i2s_clk_consumer>; + codec = <&cs4272>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/audioinjector-ultra-overlay.dts linux/arch/arm/boot/dts/overlays/audioinjector-ultra-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/audioinjector-ultra-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/audioinjector-ultra-overlay.dts 2023-12-13 11:50:48.590961252 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for audioinjector.net audio add on soundcard +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cs4265: cs4265@4e { + #sound-dai-cells = <0>; + compatible = "cirrus,cs4265"; + reg = <0x4e>; + reset-gpios = <&gpio 5 0>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "simple-audio-card"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + + simple-audio-card,name = "audioinjector-ultra"; + + simple-audio-card,widgets = + "Line", "OUTPUTS", + "Line", "INPUTS"; + + simple-audio-card,routing = + "OUTPUTS","LINEOUTL", + "OUTPUTS","LINEOUTR", + "OUTPUTS","SPDIFOUT", + "LINEINL","INPUTS", + "LINEINR","INPUTS", + "MICL","INPUTS", + "MICR","INPUTS"; + + simple-audio-card,format = "i2s"; + + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + + simple-audio-card,cpu { + sound-dai = <&i2s_clk_consumer>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&cs4265>; + system-clock-frequency = <12288000>; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/audioinjector-wm8731-audio-overlay.dts linux/arch/arm/boot/dts/overlays/audioinjector-wm8731-audio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/audioinjector-wm8731-audio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/audioinjector-wm8731-audio-overlay.dts 2023-12-13 11:50:48.590961252 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for audioinjector.net audio add on soundcard +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wm8731@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8731"; + reg = <0x1a>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "ai,audioinjector-pi-soundcard"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/audiosense-pi-overlay.dts linux/arch/arm/boot/dts/overlays/audiosense-pi-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/audiosense-pi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/audiosense-pi-overlay.dts 2023-12-13 11:50:48.590961252 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for audiosense add on soundcard +/dts-v1/; +/plugin/; +#include <dt-bindings/pinctrl/bcm2835.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + codec_reg_1v8: codec-reg-1v8 { + compatible = "regulator-fixed"; + regulator-name = "tlv320aic3204_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* audio external oscillator */ + codec_osc: codec_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; /* 12 MHz */ + }; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + codec_rst: codec-rst { + brcm,pins = <26>; + brcm,function = <BCM2835_FSEL_GPIO_OUT>; + }; + }; + }; + + fragment@3 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + codec: tlv320aic32x4@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + + clocks = <&codec_osc>; + clock-names = "mclk"; + + iov-supply = <&vdd_3v3_reg>; + ldoin-supply = <&vdd_3v3_reg>; + + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&gpio 26 GPIO_ACTIVE_HIGH>; + + status = "okay"; + }; + }; + }; + + fragment@4 { + target = <&sound>; + __overlay__ { + compatible = "as,audiosense-pi"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/audremap-overlay.dts linux/arch/arm/boot/dts/overlays/audremap-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/audremap-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/audremap-overlay.dts 2023-12-13 11:50:48.590961252 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&audio_pins>; + frag0: __overlay__ { + brcm,pins = <12 13>; + brcm,function = <4>; /* alt0 alt0 */ + }; + }; + + fragment@1 { + target = <&chosen>; + __overlay__ { + bootargs = "snd_bcm2835.enable_headphones=1"; + }; + }; + + __overrides__ { + swap_lr = <&frag0>, "swap_lr?"; + enable_jack = <&frag0>, "enable_jack?"; + pins_12_13 = <&frag0>,"brcm,pins:0=12", + <&frag0>,"brcm,pins:4=13", + <&frag0>,"brcm,function:0=4"; + pins_18_19 = <&frag0>,"brcm,pins:0=18", + <&frag0>,"brcm,pins:4=19", + <&frag0>,"brcm,function:0=2"; + pins_40_41 = <&frag0>,"brcm,pins:0=40", + <&frag0>,"brcm,pins:4=41", + <&frag0>,"brcm,function:0=4"; + pins_40_45 = <&frag0>,"brcm,pins:0=40", + <&frag0>,"brcm,pins:4=45", + <&frag0>,"brcm,function:0=4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/balena-fin-overlay.dts linux/arch/arm/boot/dts/overlays/balena-fin-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/balena-fin-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/balena-fin-overlay.dts 2023-12-13 11:50:48.591961254 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&mmcnr>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pins>; + bus-width = <4>; + brcm,overclock-50 = <35>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + sdio_pins: sdio_ovl_pins { + brcm,pins = <34 35 36 37 38 39>; + brcm,function = <7>; /* ALT3 = SD1 */ + brcm,pull = <0 2 2 2 2 2>; + }; + + power_ctrl_pins: power_ctrl_pins { + brcm,pins = <40>; + brcm,function = <1>; // out + }; + }; + }; + + fragment@2 { + target-path = "/"; + __overlay__ { + // We should switch to mmc-pwrseq-sd8787 after making it + // compatible with sd8887 + // Currently that module requires two GPIOs to function since it + // targets a slightly different chip + power_ctrl: power_ctrl { + compatible = "gpio-poweroff"; + gpios = <&gpio 40 1>; + force; + pinctrl-names = "default"; + pinctrl-0 = <&power_ctrl_pins>; + }; + + i2c_soft: i2c@0 { + compatible = "i2c-gpio"; + gpios = <&gpio 43 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */ + &gpio 42 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */>; + i2c-gpio,delay-us = <5>; + i2c-gpio,scl-open-drain; + i2c-gpio,sda-open-drain; + #address-cells = <1>; + #size-cells = <0>; + }; + + sd8xxx-wlan { + drvdbg = <0x6>; + drv_mode = <0x1>; + cfg80211_wext = <0xf>; + sta_name = "wlan"; + wfd_name = "p2p"; + cal_data_cfg = "none"; + }; + }; + }; + + fragment@3 { + target = <&i2c_soft>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + gpio_expander: gpio_expander@20 { + compatible = "nxp,pca9554"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + status = "okay"; + }; + + // rtc clock + ds1307: ds1307@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + status = "okay"; + }; + + // RGB LEDs (>= v1.1.0) + pca9633: pca9633@62 { + compatible = "nxp,pca9633"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + red@0 { + label = "red"; + reg = <0>; + linux,default-trigger = "none"; + }; + green@1 { + label = "green"; + reg = <1>; + linux,default-trigger = "none"; + }; + blue@2 { + label = "blue"; + reg = <2>; + linux,default-trigger = "none"; + }; + unused@3 { + label = "unused"; + reg = <3>; + linux,default-trigger = "none"; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/camera-mux-2port-overlay.dts linux/arch/arm/boot/dts/overlays/camera-mux-2port-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/camera-mux-2port-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/camera-mux-2port-overlay.dts 2023-12-13 11:50:48.591961254 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Overlay to configure a 2 port camera multiplexer +// +// Configuration is based on the Arducam Doubleplexer +// which uses a PCA9543 I2C multiplexer to handle the +// I2C, and GPIO 4 to control the MIPI mux, and GPIO 17 +// to enable the CSI-2 mux output (gpio-hog). + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2835"; + + /* Fragments that complete the individual sensor fragments */ + /* IMX290 */ + fragment@0 { + target = <&imx290_0_ep>; + __overlay__ { + data-lanes = <1 2>; + link-frequencies = + /bits/ 64 <445500000 297000000>; + }; + }; + + fragment@1 { + target = <&imx290_1_ep>; + __overlay__ { + data-lanes = <1 2>; + link-frequencies = + /bits/ 64 <445500000 297000000>; + }; + }; + + /* IMX477 */ + fragment@10 { + target = <&imx477_0>; + __overlay__ { + compatible = "sony,imx477"; + }; + }; + + fragment@11 { + target = <&imx477_1>; + __overlay__ { + compatible = "sony,imx477"; + }; + }; + + /* Additional fragments affecting the mux nodes */ + fragment@100 { + target = <&mux_in0>; + __dormant__ { + data-lanes = <1>; + }; + }; + fragment@101 { + target = <&mux_in0>; + __overlay__ { + data-lanes = <1 2>; + }; + }; + + fragment@102 { + target = <&mux_in1>; + __dormant__ { + data-lanes = <1>; + }; + }; + fragment@103 { + target = <&mux_in1>; + __overlay__ { + data-lanes = <1 2>; + }; + }; + + /* Mux define */ + i2c_frag: fragment@200 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca@70 { + reg = <0x70>; + compatible = "nxp,pca9543"; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + #define cam_node arducam_64mp_0 + #define cam_endpoint arducam_64mp_0_ep + #define vcm_node arducam_64mp_0_vcm + #define cam1_clk clk_24mhz + #include "arducam-64mp.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node imx219_0 + #define cam_endpoint imx219_0_ep + #define cam1_clk clk_24mhz + #include "imx219.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx477_0 + #define cam_endpoint imx477_0_ep + #define cam1_clk clk_24mhz + #include "imx477_378.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx519_0 + #define cam_endpoint imx519_0_ep + #define vcm_node imx519_0_vcm + #define cam1_clk clk_24mhz + #include "imx519.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node imx708_0 + #define cam_endpoint imx708_0_ep + #define vcm_node imx708_0_vcm + #define cam1_clk clk_24mhz + #include "imx708.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node ov5647_0 + #define cam_endpoint ov5647_0_ep + #define cam1_clk clk_25mhz + #include "ov5647.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov7251_0 + #define cam_endpoint ov7251_0_ep + #define cam1_clk clk_24mhz + #include "ov7251.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov9281_0 + #define cam_endpoint ov9281_0_ep + #define cam1_clk clk_24mhz + #include "ov9281.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx258_0 + #define cam_endpoint imx258_0_ep + #define cam1_clk clk_24mhz + #include "imx258.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx290_0 + #define cam_endpoint imx290_0_ep + #define cam1_clk clk_imx290 + #include "imx290_327.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov2311_0 + #define cam_endpoint ov2311_0_ep + #define cam1_clk clk_24mhz + #include "ov2311.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov64a40_0 + #define cam_endpoint ov64a40_0_ep + #define vcm_node ov64a40_0_vcm + #define cam1_clk clk_24mhz + #include "ov64a40.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + #define cam_node arducam_64mp_1 + #define cam_endpoint arducam_64mp_1_ep + #define vcm_node arducam_64mp_1_vcm + #define cam1_clk clk_24mhz + #include "arducam-64mp.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node imx219_1 + #define cam_endpoint imx219_1_ep + #define cam1_clk clk_24mhz + #include "imx219.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx477_1 + #define cam_endpoint imx477_1_ep + #define cam1_clk clk_24mhz + #include "imx477_378.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx519_1 + #define cam_endpoint imx519_1_ep + #define vcm_node imx519_1_vcm + #define cam1_clk clk_24mhz + #include "imx519.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node imx708_1 + #define cam_endpoint imx708_1_ep + #define vcm_node imx708_1_vcm + #define cam1_clk clk_24mhz + #include "imx708.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node ov5647_1 + #define cam_endpoint ov5647_1_ep + #define cam1_clk clk_25mhz + #include "ov5647.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov7251_1 + #define cam_endpoint ov7251_1_ep + #define cam1_clk clk_24mhz + #include "ov7251.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov9281_1 + #define cam_endpoint ov9281_1_ep + #define cam1_clk clk_24mhz + #include "ov9281.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx258_1 + #define cam_endpoint imx258_1_ep + #define cam1_clk clk_24mhz + #include "imx258.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx290_1 + #define cam_endpoint imx290_1_ep + #define cam1_clk clk_imx290 + #include "imx290_327.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov2311_1 + #define cam_endpoint ov2311_1_ep + #define cam1_clk clk_24mhz + #include "ov2311.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov64a40_1 + #define cam_endpoint ov64a40_1_ep + #define vcm_node ov64a40_1_vcm + #define cam1_clk clk_24mhz + #include "ov64a40.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + }; + }; + }; + }; + + csi_frag: fragment@201 { + target = <&csi1>; + __overlay__ { + status = "okay"; + + brcm,media-controller; + + port { + csi1_ep: endpoint { + remote-endpoint = <&mux_out>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + fragment@202 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@203 { + target-path="/"; + __overlay__ { + mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; + }; + + video-mux { + compatible = "video-mux"; + mux-controls = <&mux>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mux_in0: endpoint { + clock-lanes = <0>; + }; + }; + + port@1 { + reg = <1>; + + mux_in1: endpoint { + clock-lanes = <0>; + }; + }; + + port@2 { + reg = <2>; + + mux_out: endpoint { + remote-endpoint = <&csi1_ep>; + clock-lanes = <0>; + }; + }; + }; + + clk_24mhz: clk_24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + + clock-frequency = <24000000>; + status = "okay"; + }; + + clk_25mhz: clk_25mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + + clock-frequency = <25000000>; + status = "okay"; + }; + + clk_imx290: clk_imx290 { + compatible = "fixed-clock"; + #clock-cells = <0>; + + clock-frequency = <37125000>; + status = "okay"; + }; + }; + }; + + fragment@204 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@205 { + target = <&gpio>; + __overlay__ { + mipi_sw_oe_hog { + gpio-hog; + gpios = <17 GPIO_ACTIVE_LOW>; + output-high; + }; + }; + }; + + __overrides__ { + cam0-arducam-64mp = <&mux_in0>, "remote-endpoint:0=",<&arducam_64mp_0_ep>, + <&arducam_64mp_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&mux_in0>, "clock-noncontinuous?", + <&arducam_64mp_0>, "status=okay", + <&arducam_64mp_0_vcm>, "status=okay", + <&arducam_64mp_0>,"lens-focus:0=", <&arducam_64mp_0_vcm>; + cam0-imx219 = <&mux_in0>, "remote-endpoint:0=",<&imx219_0_ep>, + <&imx219_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&mux_in0>, "clock-noncontinuous?", + <&imx219_0>, "status=okay"; + cam0-imx477 = <&mux_in0>, "remote-endpoint:0=",<&imx477_0_ep>, + <&imx477_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&mux_in0>, "clock-noncontinuous?", + <&imx477_0>, "status=okay"; + cam0-imx519 = <&mux_in0>, "remote-endpoint:0=",<&imx519_0_ep>, + <&imx519_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&mux_in0>, "clock-noncontinuous?", + <&imx519_0>, "status=okay", + <&imx519_0_vcm>, "status=okay", + <&imx519_0>,"lens-focus:0=", <&imx519_0_vcm>; + cam0-imx708 = <&mux_in0>, "remote-endpoint:0=",<&imx708_0_ep>, + <&imx708_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&mux_in0>, "clock-noncontinuous?", + <&imx708_0>, "status=okay", + <&imx708_0_vcm>, "status=okay", + <&imx708_0>,"lens-focus:0=", <&imx708_0_vcm>; + cam0-ov5647 = <&mux_in0>, "remote-endpoint:0=",<&ov5647_0_ep>, + <&ov5647_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&ov5647_0>, "status=okay"; + cam0-ov7251 = <&mux_in0>, "remote-endpoint:0=",<&ov7251_0_ep>, + <&ov7251_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&ov7251_0>, "status=okay", + <0>,"+100-101"; + cam0-ov9281 = <&mux_in0>, "remote-endpoint:0=",<&ov9281_0_ep>, + <&ov9281_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&ov9281_0>, "status=okay"; + cam0-imx258 = <&mux_in0>, "remote-endpoint:0=",<&imx258_0_ep>, + <&imx258_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&imx258_0>, "status=okay"; + cam0-imx290 = <&mux_in0>, "remote-endpoint:0=",<&imx290_0_ep>, + <&imx290_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&imx290_0>, "status=okay"; + cam0-ov2311 = <&mux_in0>, "remote-endpoint:0=",<&ov2311_0_ep>, + <&ov2311_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&ov2311_0>, "status=okay"; + cam0-ov64a40 = <&mux_in0>, "remote-endpoint:0=",<&ov64a40_0_ep>, + <&ov64a40_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&mux_in0>, "clock-noncontinuous?", + <&ov64a40_0>, "status=okay", + <&ov64a40_0_vcm>, "status=okay", + <&ov64a40_0>,"lens-focus:0=", <&ov64a40_0_vcm>; + + cam1-arducam-64mp = <&mux_in1>, "remote-endpoint:0=",<&arducam_64mp_1_ep>, + <&arducam_64mp_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&mux_in1>, "clock-noncontinuous?", + <&arducam_64mp_1>, "status=okay", + <&arducam_64mp_1_vcm>, "status=okay", + <&arducam_64mp_1>,"lens-focus:0=", <&arducam_64mp_1_vcm>; + cam1-imx219 = <&mux_in1>, "remote-endpoint:0=",<&imx219_1_ep>, + <&imx219_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&mux_in1>, "clock-noncontinuous?", + <&imx219_1>, "status=okay"; + cam1-imx477 = <&mux_in1>, "remote-endpoint:0=",<&imx477_1_ep>, + <&imx477_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&mux_in1>, "clock-noncontinuous?", + <&imx477_1>, "status=okay"; + cam1-imx519 = <&mux_in1>, "remote-endpoint:0=",<&imx519_1_ep>, + <&imx519_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&mux_in1>, "clock-noncontinuous?", + <&imx519_1>, "status=okay", + <&imx519_1_vcm>, "status=okay", + <&imx519_1>,"lens-focus:0=", <&imx519_1_vcm>; + cam1-imx708 = <&mux_in1>, "remote-endpoint:0=",<&imx708_1_ep>, + <&imx708_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&mux_in1>, "clock-noncontinuous?", + <&imx708_1>, "status=okay", + <&imx708_1_vcm>, "status=okay", + <&imx708_1>,"lens-focus:0=", <&imx708_1_vcm>; + cam1-ov5647 = <&mux_in1>, "remote-endpoint:0=",<&ov5647_1_ep>, + <&ov5647_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&ov5647_1>, "status=okay"; + cam1-ov7251 = <&mux_in1>, "remote-endpoint:0=",<&ov7251_1_ep>, + <&ov7251_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&ov7251_1>, "status=okay", + <0>,"+102-103"; + cam1-ov9281 = <&mux_in1>, "remote-endpoint:0=",<&ov9281_1_ep>, + <&ov9281_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&ov9281_1>, "status=okay"; + cam1-imx258 = <&mux_in1>, "remote-endpoint:0=",<&imx258_1_ep>, + <&imx258_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&imx258_1>, "status=okay"; + cam1-imx290 = <&mux_in1>, "remote-endpoint:0=",<&imx290_1_ep>, + <&imx290_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&imx290_1>, "status=okay"; + cam1-ov2311 = <&mux_in1>, "remote-endpoint:0=",<&ov2311_1_ep>, + <&ov2311_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&ov2311_1>, "status=okay"; + cam1-ov64a40 = <&mux_in1>, "remote-endpoint:0=",<&ov64a40_1_ep>, + <&ov64a40_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&mux_in1>, "clock-noncontinuous?", + <&ov64a40_1>, "status=okay", + <&ov64a40_1_vcm>, "status=okay", + <&ov64a40_1>,"lens-focus:0=", <&ov64a40_1_vcm>; + + cam0-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0", + <&imx290_0>,"clock-frequency:0"; + cam1-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0", + <&imx290_1>,"clock-frequency:0"; + + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/camera-mux-4port-overlay.dts linux/arch/arm/boot/dts/overlays/camera-mux-4port-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/camera-mux-4port-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/camera-mux-4port-overlay.dts 2023-12-13 11:50:48.591961254 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only + +// Overlay to configure a 4 port camera multiplexer +// +// Configuration is based on the Arducam 4 channel multiplexer +// which uses a PCA9543 I2C multiplexer to handle the +// I2C, and GPIOs 4, 17, and 18 to control the MIPI muxes. + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2835"; + + /* Fragments that complete the individual sensor fragments */ + /* IMX290 */ + fragment@0 { + target = <&imx290_0_ep>; + __overlay__ { + data-lanes = <1 2>; + link-frequencies = + /bits/ 64 <445500000 297000000>; + }; + }; + + fragment@1 { + target = <&imx290_1_ep>; + __overlay__ { + data-lanes = <1 2>; + link-frequencies = + /bits/ 64 <445500000 297000000>; + }; + }; + + fragment@2 { + target = <&imx290_2_ep>; + __overlay__ { + data-lanes = <1 2>; + link-frequencies = + /bits/ 64 <445500000 297000000>; + }; + }; + + fragment@3 { + target = <&imx290_3_ep>; + __overlay__ { + data-lanes = <1 2>; + link-frequencies = + /bits/ 64 <445500000 297000000>; + }; + }; + + /* IMX477 */ + fragment@10 { + target = <&imx477_0>; + __overlay__ { + compatible = "sony,imx477"; + }; + }; + + fragment@11 { + target = <&imx477_1>; + __overlay__ { + compatible = "sony,imx477"; + }; + }; + + fragment@12 { + target = <&imx477_2>; + __overlay__ { + compatible = "sony,imx477"; + }; + }; + + fragment@13 { + target = <&imx477_3>; + __overlay__ { + compatible = "sony,imx477"; + }; + }; + + /* Additional fragments affecting the mux nodes */ + fragment@100 { + target = <&mux_in0>; + __dormant__ { + data-lanes = <1>; + }; + }; + fragment@101 { + target = <&mux_in0>; + __overlay__ { + data-lanes = <1 2>; + }; + }; + + fragment@102 { + target = <&mux_in1>; + __dormant__ { + data-lanes = <1>; + }; + }; + fragment@103 { + target = <&mux_in1>; + __overlay__ { + data-lanes = <1 2>; + }; + }; + + fragment@104 { + target = <&mux_in2>; + __dormant__ { + data-lanes = <1>; + }; + }; + fragment@105 { + target = <&mux_in2>; + __overlay__ { + data-lanes = <1 2>; + }; + }; + + fragment@106 { + target = <&mux_in3>; + __dormant__ { + data-lanes = <1>; + }; + }; + fragment@107 { + target = <&mux_in3>; + __overlay__ { + data-lanes = <1 2>; + }; + }; + + /* Mux define */ + i2c_frag: fragment@200 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca@70 { + reg = <0x70>; + compatible = "nxp,pca9544"; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + #define cam_node arducam_64mp_0 + #define cam_endpoint arducam_64mp_0_ep + #define vcm_node arducam_64mp_0_vcm + #define cam1_clk clk_24mhz + #include "arducam-64mp.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node imx219_0 + #define cam_endpoint imx219_0_ep + #define cam1_clk clk_24mhz + #include "imx219.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx477_0 + #define cam_endpoint imx477_0_ep + #define cam1_clk clk_24mhz + #include "imx477_378.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx519_0 + #define cam_endpoint imx519_0_ep + #define vcm_node imx519_0_vcm + #define cam1_clk clk_24mhz + #include "imx519.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node imx708_0 + #define cam_endpoint imx708_0_ep + #define vcm_node imx708_0_vcm + #define cam1_clk clk_24mhz + #include "imx708.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node ov5647_0 + #define cam_endpoint ov5647_0_ep + #define cam1_clk clk_25mhz + #include "ov5647.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov7251_0 + #define cam_endpoint ov7251_0_ep + #define cam1_clk clk_24mhz + #include "ov7251.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov9281_0 + #define cam_endpoint ov9281_0_ep + #define cam1_clk clk_24mhz + #include "ov9281.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx258_0 + #define cam_endpoint imx258_0_ep + #define cam1_clk clk_24mhz + #include "imx258.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx290_0 + #define cam_endpoint imx290_0_ep + #define cam1_clk clk_imx290 + #include "imx290_327.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov2311_0 + #define cam_endpoint ov2311_0_ep + #define cam1_clk clk_24mhz + #include "ov2311.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov64a40_0 + #define cam_endpoint ov64a40_0_ep + #define vcm_node ov64a40_0_vcm + #define cam1_clk clk_24mhz + #include "ov64a40.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + #define cam_node arducam_64mp_1 + #define cam_endpoint arducam_64mp_1_ep + #define vcm_node arducam_64mp_1_vcm + #define cam1_clk clk_24mhz + #include "arducam-64mp.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node imx219_1 + #define cam_endpoint imx219_1_ep + #define cam1_clk clk_24mhz + #include "imx219.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx477_1 + #define cam_endpoint imx477_1_ep + #define cam1_clk clk_24mhz + #include "imx477_378.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx519_1 + #define cam_endpoint imx519_1_ep + #define vcm_node imx519_1_vcm + #define cam1_clk clk_24mhz + #include "imx519.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node imx708_1 + #define cam_endpoint imx708_1_ep + #define vcm_node imx708_1_vcm + #define cam1_clk clk_24mhz + #include "imx708.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node ov5647_1 + #define cam_endpoint ov5647_1_ep + #define cam1_clk clk_25mhz + #include "ov5647.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov7251_1 + #define cam_endpoint ov7251_1_ep + #define cam1_clk clk_24mhz + #include "ov7251.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov9281_1 + #define cam_endpoint ov9281_1_ep + #define cam1_clk clk_24mhz + #include "ov9281.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx258_1 + #define cam_endpoint imx258_1_ep + #define cam1_clk clk_24mhz + #include "imx258.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx290_1 + #define cam_endpoint imx290_1_ep + #define cam1_clk clk_imx290 + #include "imx290_327.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov2311_1 + #define cam_endpoint ov2311_1_ep + #define cam1_clk clk_24mhz + #include "ov2311.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov64a40_1 + #define cam_endpoint ov64a40_1_ep + #define vcm_node ov64a40_1_vcm + #define cam1_clk clk_24mhz + #include "ov64a40.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + #define cam_node arducam_64mp_2 + #define cam_endpoint arducam_64mp_2_ep + #define vcm_node arducam_64mp_2_vcm + #define cam1_clk clk_24mhz + #include "arducam-64mp.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node imx219_2 + #define cam_endpoint imx219_2_ep + #define cam1_clk clk_24mhz + #include "imx219.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx477_2 + #define cam_endpoint imx477_2_ep + #define cam1_clk clk_24mhz + #include "imx477_378.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx519_2 + #define cam_endpoint imx519_2_ep + #define vcm_node imx519_2_vcm + #define cam1_clk clk_24mhz + #include "imx519.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node imx708_2 + #define cam_endpoint imx708_2_ep + #define vcm_node imx708_2_vcm + #define cam1_clk clk_24mhz + #include "imx708.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node ov5647_2 + #define cam_endpoint ov5647_2_ep + #define cam1_clk clk_25mhz + #include "ov5647.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov7251_2 + #define cam_endpoint ov7251_2_ep + #define cam1_clk clk_24mhz + #include "ov7251.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov9281_2 + #define cam_endpoint ov9281_2_ep + #define cam1_clk clk_24mhz + #include "ov9281.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx258_2 + #define cam_endpoint imx258_2_ep + #define cam1_clk clk_24mhz + #include "imx258.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx290_2 + #define cam_endpoint imx290_2_ep + #define cam1_clk clk_imx290 + #include "imx290_327.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov2311_2 + #define cam_endpoint ov2311_2_ep + #define cam1_clk clk_24mhz + #include "ov2311.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov64a40_2 + #define cam_endpoint ov64a40_2_ep + #define vcm_node ov64a40_2_vcm + #define cam1_clk clk_24mhz + #include "ov64a40.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + #define cam_node arducam_64mp_3 + #define cam_endpoint arducam_64mp_3_ep + #define vcm_node arducam_64mp_3_vcm + #define cam1_clk clk_24mhz + #include "arducam-64mp.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node imx219_3 + #define cam_endpoint imx219_3_ep + #define cam1_clk clk_24mhz + #include "imx219.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx477_3 + #define cam_endpoint imx477_3_ep + #define cam1_clk clk_24mhz + #include "imx477_378.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx519_3 + #define cam_endpoint imx519_3_ep + #define vcm_node imx519_3_vcm + #define cam1_clk clk_24mhz + #include "imx519.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node imx708_3 + #define cam_endpoint imx708_3_ep + #define vcm_node imx708_3_vcm + #define cam1_clk clk_24mhz + #include "imx708.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + + #define cam_node ov5647_3 + #define cam_endpoint ov5647_3_ep + #define cam1_clk clk_25mhz + #include "ov5647.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov7251_3 + #define cam_endpoint ov7251_3_ep + #define cam1_clk clk_24mhz + #include "ov7251.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov9281_3 + #define cam_endpoint ov9281_3_ep + #define cam1_clk clk_24mhz + #include "ov9281.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx258_3 + #define cam_endpoint imx258_3_ep + #define cam1_clk clk_24mhz + #include "imx258.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node imx290_3 + #define cam_endpoint imx290_3_ep + #define cam1_clk clk_imx290 + #include "imx290_327.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov2311_3 + #define cam_endpoint ov2311_3_ep + #define cam1_clk clk_24mhz + #include "ov2311.dtsi" + #undef cam_node + #undef cam_endpoint + #undef cam1_clk + + #define cam_node ov64a40_3 + #define cam_endpoint ov64a40_3_ep + #define vcm_node ov64a40_3_vcm + #define cam1_clk clk_24mhz + #include "ov64a40.dtsi" + #undef cam_node + #undef cam_endpoint + #undef vcm_node + #undef cam1_clk + }; + }; + }; + }; + + csi_frag: fragment@201 { + target = <&csi1>; + __overlay__ { + status = "okay"; + + brcm,media-controller; + + port { + csi1_ep: endpoint { + remote-endpoint = <&mux_out>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + fragment@202 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@203 { + target-path="/"; + __overlay__ { + mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + /* SEL, En2, En1 */ + mux-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>, + <&gpio 18 GPIO_ACTIVE_HIGH>, + <&gpio 17 GPIO_ACTIVE_HIGH>; + }; + + video-mux { + compatible = "video-mux"; + mux-controls = <&mux>; + #address-cells = <1>; + #size-cells = <0>; + + /* GPIO mappings settings for selecting the different + * camera connectors are not direct, hence port@ values + * are not straight forward. + */ + port@2 { + /* Port A - GPIO 17 = 0, GPIO 18 = 1,GPIO 4 = 0 */ + reg = <2>; + + mux_in0: endpoint { + clock-lanes = <0>; + }; + }; + + port@3 { + /* Port B - GPIO 17 = 0, GPIO 18 = 1,GPIO 4 = 1 */ + reg = <3>; + + mux_in1: endpoint { + clock-lanes = <0>; + }; + }; + + port@4 { + /* Port C - GPIO 17 = 1, GPIO 18 = 0, GPIO 4 = 0 */ + reg = <4>; + + mux_in2: endpoint { + clock-lanes = <0>; + }; + }; + + port@5 { + /* Port D - GPIO 17 = 1, GPIO 18 = 0, GPIO 4 = 1 */ + reg = <5>; + + mux_in3: endpoint { + clock-lanes = <0>; + }; + }; + + port@6 { + /* Output port needs to be the highest port number */ + reg = <6>; + + mux_out: endpoint { + remote-endpoint = <&csi1_ep>; + clock-lanes = <0>; + }; + }; + }; + + clk_24mhz: clk_24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + + clock-frequency = <24000000>; + status = "okay"; + }; + + clk_25mhz: clk_25mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + + clock-frequency = <25000000>; + status = "okay"; + }; + + clk_imx290: clk_imx290 { + compatible = "fixed-clock"; + #clock-cells = <0>; + + clock-frequency = <37125000>; + status = "okay"; + }; + }; + }; + + fragment@204 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + __overrides__ { + cam0-arducam-64mp = <&mux_in0>, "remote-endpoint:0=",<&arducam_64mp_0_ep>, + <&arducam_64mp_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&mux_in0>, "clock-noncontinuous?", + <&arducam_64mp_0>, "status=okay", + <&arducam_64mp_0_vcm>, "status=okay", + <&arducam_64mp_0>,"lens-focus:0=", <&arducam_64mp_0_vcm>; + cam0-imx219 = <&mux_in0>, "remote-endpoint:0=",<&imx219_0_ep>, + <&imx219_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&mux_in0>, "clock-noncontinuous?", + <&imx219_0>, "status=okay"; + cam0-imx477 = <&mux_in0>, "remote-endpoint:0=",<&imx477_0_ep>, + <&imx477_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&mux_in0>, "clock-noncontinuous?", + <&imx477_0>, "status=okay"; + cam0-imx519 = <&mux_in0>, "remote-endpoint:0=",<&imx519_0_ep>, + <&imx519_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&mux_in0>, "clock-noncontinuous?", + <&imx519_0>, "status=okay", + <&imx519_0_vcm>, "status=okay", + <&imx519_0>,"lens-focus:0=", <&imx519_0_vcm>; + cam0-imx708 = <&mux_in0>, "remote-endpoint:0=",<&imx708_0_ep>, + <&imx708_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&mux_in0>, "clock-noncontinuous?", + <&imx708_0>, "status=okay", + <&imx708_0_vcm>, "status=okay", + <&imx708_0>,"lens-focus:0=", <&imx708_0_vcm>; + cam0-ov5647 = <&mux_in0>, "remote-endpoint:0=",<&ov5647_0_ep>, + <&ov5647_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&ov5647_0>, "status=okay"; + cam0-ov7251 = <&mux_in0>, "remote-endpoint:0=",<&ov7251_0_ep>, + <&ov7251_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&ov7251_0>, "status=okay", + <0>,"+100-101"; + cam0-ov9281 = <&mux_in0>, "remote-endpoint:0=",<&ov9281_0_ep>, + <&ov9281_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&ov9281_0>, "status=okay"; + cam0-imx258 = <&mux_in0>, "remote-endpoint:0=",<&imx258_0_ep>, + <&imx258_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&imx258_0>, "status=okay"; + cam0-imx290 = <&mux_in0>, "remote-endpoint:0=",<&imx290_0_ep>, + <&imx290_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&imx290_0>, "status=okay"; + cam0-ov2311 = <&mux_in0>, "remote-endpoint:0=",<&ov2311_0_ep>, + <&ov2311_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&ov2311_0>, "status=okay"; + cam0-ov64a40 = <&mux_in0>, "remote-endpoint:0=",<&ov64a40_0_ep>, + <&ov64a40_0_ep>, "remote-endpoint:0=",<&mux_in0>, + <&mux_in0>, "clock-noncontinuous?", + <&ov64a40_0>, "status=okay", + <&ov64a40_0_vcm>, "status=okay", + <&ov64a40_0>,"lens-focus:0=", <&ov64a40_0_vcm>; + + cam1-arducam-64mp = <&mux_in1>, "remote-endpoint:0=",<&arducam_64mp_1_ep>, + <&arducam_64mp_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&mux_in1>, "clock-noncontinuous?", + <&arducam_64mp_1>, "status=okay", + <&arducam_64mp_1_vcm>, "status=okay", + <&arducam_64mp_1>,"lens-focus:0=", <&arducam_64mp_1_vcm>; + cam1-imx219 = <&mux_in1>, "remote-endpoint:0=",<&imx219_1_ep>, + <&imx219_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&mux_in1>, "clock-noncontinuous?", + <&imx219_1>, "status=okay"; + cam1-imx477 = <&mux_in1>, "remote-endpoint:0=",<&imx477_1_ep>, + <&imx477_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&mux_in1>, "clock-noncontinuous?", + <&imx477_1>, "status=okay"; + cam1-imx519 = <&mux_in1>, "remote-endpoint:0=",<&imx519_1_ep>, + <&imx519_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&mux_in1>, "clock-noncontinuous?", + <&imx519_1>, "status=okay", + <&imx519_1_vcm>, "status=okay", + <&imx519_1>,"lens-focus:0=", <&imx519_1_vcm>; + cam1-imx708 = <&mux_in1>, "remote-endpoint:0=",<&imx708_1_ep>, + <&imx708_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&mux_in1>, "clock-noncontinuous?", + <&imx708_1>, "status=okay", + <&imx708_1_vcm>, "status=okay", + <&imx708_1>,"lens-focus:0=", <&imx708_1_vcm>; + cam1-ov5647 = <&mux_in1>, "remote-endpoint:0=",<&ov5647_1_ep>, + <&ov5647_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&ov5647_1>, "status=okay"; + cam1-ov7251 = <&mux_in1>, "remote-endpoint:0=",<&ov7251_1_ep>, + <&ov7251_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&ov7251_1>, "status=okay", + <0>,"+102-103"; + cam1-ov9281 = <&mux_in1>, "remote-endpoint:0=",<&ov9281_1_ep>, + <&ov9281_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&ov9281_1>, "status=okay"; + cam1-imx258 = <&mux_in1>, "remote-endpoint:0=",<&imx258_1_ep>, + <&imx258_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&imx258_1>, "status=okay"; + cam1-imx290 = <&mux_in1>, "remote-endpoint:0=",<&imx290_1_ep>, + <&imx290_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&imx290_1>, "status=okay"; + cam1-ov2311 = <&mux_in1>, "remote-endpoint:0=",<&ov2311_1_ep>, + <&ov2311_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&ov2311_1>, "status=okay"; + cam1-ov64a40 = <&mux_in1>, "remote-endpoint:0=",<&ov64a40_1_ep>, + <&ov64a40_1_ep>, "remote-endpoint:0=",<&mux_in1>, + <&mux_in1>, "clock-noncontinuous?", + <&ov64a40_1>, "status=okay", + <&ov64a40_1_vcm>, "status=okay", + <&ov64a40_1>,"lens-focus:0=", <&ov64a40_1_vcm>; + + cam2-arducam-64mp = <&mux_in2>, "remote-endpoint:0=",<&arducam_64mp_2_ep>, + <&arducam_64mp_2_ep>, "remote-endpoint:0=",<&mux_in2>, + <&mux_in2>, "clock-noncontinuous?", + <&arducam_64mp_2>, "status=okay", + <&arducam_64mp_2_vcm>, "status=okay", + <&arducam_64mp_2>,"lens-focus:0=", <&arducam_64mp_2_vcm>; + cam2-imx219 = <&mux_in2>, "remote-endpoint:0=",<&imx219_2_ep>, + <&imx219_2_ep>, "remote-endpoint:0=",<&mux_in2>, + <&mux_in2>, "clock-noncontinuous?", + <&imx219_2>, "status=okay"; + cam2-imx477 = <&mux_in2>, "remote-endpoint:0=",<&imx477_2_ep>, + <&imx477_2_ep>, "remote-endpoint:0=",<&mux_in2>, + <&mux_in2>, "clock-noncontinuous?", + <&imx477_2>, "status=okay"; + cam2-imx519 = <&mux_in2>, "remote-endpoint:0=",<&imx519_2_ep>, + <&imx519_2_ep>, "remote-endpoint:0=",<&mux_in2>, + <&mux_in2>, "clock-noncontinuous?", + <&imx519_2>, "status=okay", + <&imx519_2_vcm>, "status=okay", + <&imx519_2>,"lens-focus:0=", <&imx519_2_vcm>; + cam2-imx708 = <&mux_in2>, "remote-endpoint:0=",<&imx708_2_ep>, + <&imx708_2_ep>, "remote-endpoint:0=",<&mux_in2>, + <&mux_in2>, "clock-noncontinuous?", + <&imx708_2>, "status=okay", + <&imx708_2_vcm>, "status=okay", + <&imx708_2>,"lens-focus:0=", <&imx708_2_vcm>; + cam2-ov5647 = <&mux_in2>, "remote-endpoint:0=",<&ov5647_2_ep>, + <&ov5647_2_ep>, "remote-endpoint:0=",<&mux_in2>, + <&ov5647_2>, "status=okay"; + cam2-ov7251 = <&mux_in2>, "remote-endpoint:0=",<&ov7251_2_ep>, + <&ov7251_2_ep>, "remote-endpoint:0=",<&mux_in2>, + <&ov7251_2>, "status=okay", + <0>,"+104-105"; + cam2-ov9281 = <&mux_in2>, "remote-endpoint:0=",<&ov9281_2_ep>, + <&ov9281_2_ep>, "remote-endpoint:0=",<&mux_in2>, + <&ov9281_2>, "status=okay"; + cam2-imx258 = <&mux_in2>, "remote-endpoint:0=",<&imx258_2_ep>, + <&imx258_2>, "status=okay", + <&imx258_2>, "remote-endpoint:0=",<&mux_in2>; + cam2-imx290 = <&mux_in2>, "remote-endpoint:0=",<&imx290_2_ep>, + <&imx290_2_ep>, "remote-endpoint:0=",<&mux_in2>, + <&imx290_2>, "status=okay"; + cam2-ov2311 = <&mux_in2>, "remote-endpoint:0=",<&ov2311_2_ep>, + <&ov2311_2_ep>, "remote-endpoint:0=",<&mux_in2>, + <&ov2311_2>, "status=okay"; + cam2-ov64a40 = <&mux_in2>, "remote-endpoint:0=",<&ov64a40_2_ep>, + <&ov64a40_2_ep>, "remote-endpoint:0=",<&mux_in2>, + <&mux_in2>, "clock-noncontinuous?", + <&ov64a40_2>, "status=okay", + <&ov64a40_2_vcm>, "status=okay", + <&ov64a40_2>,"lens-focus:0=", <&ov64a40_2_vcm>; + + cam3-arducam-64mp = <&mux_in3>, "remote-endpoint:0=",<&arducam_64mp_3_ep>, + <&arducam_64mp_3_ep>, "remote-endpoint:0=",<&mux_in3>, + <&mux_in3>, "clock-noncontinuous?", + <&arducam_64mp_3>, "status=okay", + <&arducam_64mp_3_vcm>, "status=okay", + <&arducam_64mp_3>,"lens-focus:0=", <&arducam_64mp_3_vcm>; + cam3-imx219 = <&mux_in3>, "remote-endpoint:0=",<&imx219_3_ep>, + <&imx219_3_ep>, "remote-endpoint:0=",<&mux_in3>, + <&mux_in3>, "clock-noncontinuous?", + <&imx219_3>, "status=okay"; + cam3-imx477 = <&mux_in3>, "remote-endpoint:0=",<&imx477_3_ep>, + <&imx477_3_ep>, "remote-endpoint:0=",<&mux_in3>, + <&mux_in3>, "clock-noncontinuous?", + <&imx477_3>, "status=okay"; + cam3-imx519 = <&mux_in3>, "remote-endpoint:0=",<&imx519_3_ep>, + <&imx519_3_ep>, "remote-endpoint:0=",<&mux_in3>, + <&mux_in3>, "clock-noncontinuous?", + <&imx519_3>, "status=okay", + <&imx519_3_vcm>, "status=okay", + <&imx519_3>,"lens-focus:0=", <&imx519_3_vcm>; + cam3-imx708 = <&mux_in3>, "remote-endpoint:0=",<&imx708_3_ep>, + <&imx708_3_ep>, "remote-endpoint:0=",<&mux_in3>, + <&mux_in3>, "clock-noncontinuous?", + <&imx708_3>, "status=okay", + <&imx708_3_vcm>, "status=okay", + <&imx708_3>,"lens-focus:0=", <&imx708_3_vcm>; + cam3-ov5647 = <&mux_in3>, "remote-endpoint:0=",<&ov5647_3_ep>, + <&ov5647_3_ep>, "remote-endpoint:0=",<&mux_in3>, + <&ov5647_3>, "status=okay"; + cam3-ov7251 = <&mux_in3>, "remote-endpoint:0=",<&ov7251_3_ep>, + <&ov7251_3_ep>, "remote-endpoint:0=",<&mux_in3>, + <&ov7251_3>, "status=okay", + <0>,"+106-107"; + cam3-ov9281 = <&mux_in3>, "remote-endpoint:0=",<&ov9281_3_ep>, + <&ov9281_3_ep>, "remote-endpoint:0=",<&mux_in3>, + <&ov9281_3>, "status=okay"; + cam3-imx258 = <&mux_in3>, "remote-endpoint:0=",<&imx258_3_ep>, + <&imx258_3_ep>, "remote-endpoint:0=",<&mux_in3>, + <&imx258_3>, "status=okay"; + cam3-imx290 = <&mux_in3>, "remote-endpoint:0=",<&imx290_3_ep>, + <&imx290_3_ep>, "remote-endpoint:0=",<&mux_in3>, + <&imx290_3>, "status=okay"; + cam3-ov2311 = <&mux_in3>, "remote-endpoint:0=",<&ov2311_3_ep>, + <&ov2311_3_ep>, "remote-endpoint:0=",<&mux_in3>, + <&ov2311_3>, "status=okay"; + cam3-ov64a40 = <&mux_in3>, "remote-endpoint:0=",<&ov64a40_3_ep>, + <&ov64a40_3_ep>, "remote-endpoint:0=",<&mux_in3>, + <&mux_in3>, "clock-noncontinuous?", + <&ov64a40_3>, "status=okay", + <&ov64a40_3_vcm>, "status=okay", + <&ov64a40_3>,"lens-focus:0=", <&ov64a40_3_vcm>; + + cam0-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0", + <&imx290_0>,"clock-frequency:0"; + cam1-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0", + <&imx290_1>,"clock-frequency:0"; + cam2-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0", + <&imx290_2>,"clock-frequency:0"; + cam3-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0", + <&imx290_3>,"clock-frequency:0"; + + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/cap1106-overlay.dts linux/arch/arm/boot/dts/overlays/cap1106-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/cap1106-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/cap1106-overlay.dts 2023-12-13 11:50:48.591961254 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for cap1106 from Microchip Semiconductor +// add CONFIG_KEYBOARD_CAP11XX=y + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + fragment@0 { + target = <&i2c1>; + __overlay__{ + status = "okay"; + cap1106: cap1106@28 { + compatible = "microchip,cap1106"; + pinctrl-0 = <&cap1106_pins>; + pinctrl-names = "default"; + interrupt-parent = <&gpio>; + interrupts = <4 2>; + reg = <0x28>; + autorepeat; + microchip,sensor-gain = <2>; + + linux,keycodes = <2>, /* KEY_1 */ + <3>, /* KEY_2 */ + <4>, /* KEY_3 */ + <5>, /* KEY_4 */ + <6>, /* KEY_5 */ + <7>; /* KEY_6 */ + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + }; + }; + }; + fragment@1 { + target = <&gpio>; + __overlay__ { + cap1106_pins: cap1106_pins { + brcm,pins = <4>; + brcm,function = <0>; /* in */ + brcm,pull = <0>; /* none */ + }; + }; + }; + + __overrides__ { + int_pin = <&cap1106>, "interrupts:0", + <&cap1106_pins>, "brcm,pins:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/chipdip-dac-overlay.dts linux/arch/arm/boot/dts/overlays/chipdip-dac-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/chipdip-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/chipdip-dac-overlay.dts 2023-12-13 11:50:48.591961254 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for ChipDip DAC + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + spdif-transmitter { + #address-cells = <0>; + #size-cells = <0>; + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "chipdip,chipdip-dac"; + i2s-controller = <&i2s_clk_consumer>; + sr0-gpios = <&gpio 5 0>; + sr1-gpios = <&gpio 6 0>; + sr2-gpios = <&gpio 12 0>; + res0-gpios = <&gpio 24 0>; + res1-gpios = <&gpio 27 0>; + mute-gpios = <&gpio 4 0>; + sdwn-gpios = <&gpio 13 0>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/cirrus-wm5102-overlay.dts linux/arch/arm/boot/dts/overlays/cirrus-wm5102-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/cirrus-wm5102-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/cirrus-wm5102-overlay.dts 2023-12-13 11:50:48.592961256 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for the Cirrus Logic Audio Card +/dts-v1/; +/plugin/; +#include <dt-bindings/pinctrl/bcm2835.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/arizona.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + wlf_5102_pins: wlf_5102_pins { + brcm,pins = <17 22 27>; + brcm,function = < + BCM2835_FSEL_GPIO_OUT + BCM2835_FSEL_GPIO_OUT + BCM2835_FSEL_GPIO_IN + >; + }; + wlf_8804_pins: wlf_8804_pins { + brcm,pins = <8>; + brcm,function = <BCM2835_FSEL_GPIO_OUT>; + }; + }; + }; + + fragment@2 { + target = <&spi0_cs_pins>; + __overlay__ { + brcm,pins = <7>; + brcm,function = <BCM2835_FSEL_GPIO_OUT>; + }; + }; + + + fragment@3 { + target-path = "/"; + __overlay__ { + rpi_cirrus_reg_1v8: rpi_cirrus_reg_1v8 { + compatible = "regulator-fixed"; + regulator-name = "RPi-Cirrus 1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; + + fragment@4 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@5 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&spi0>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + cs-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + + wm5102@0{ + compatible = "wlf,wm5102"; + reg = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlf_5102_pins>; + + spi-max-frequency = <500000>; + + interrupt-parent = <&gpio>; + interrupts = <27 8>; + interrupt-controller; + #interrupt-cells = <2>; + + gpio-controller; + #gpio-cells = <2>; + + LDOVDD-supply = <&rpi_cirrus_reg_1v8>; + AVDD-supply = <&rpi_cirrus_reg_1v8>; + DBVDD1-supply = <&rpi_cirrus_reg_1v8>; + DBVDD2-supply = <&vdd_3v3_reg>; + DBVDD3-supply = <&vdd_3v3_reg>; + CPVDD-supply = <&rpi_cirrus_reg_1v8>; + SPKVDDL-supply = <&vdd_5v0_reg>; + SPKVDDR-supply = <&vdd_5v0_reg>; + DCVDD-supply = <&arizona_ldo1>; + + reset-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + wlf,ldoena = <&gpio 22 GPIO_ACTIVE_HIGH>; + wlf,gpio-defaults = < + ARIZONA_GP_DEFAULT + ARIZONA_GP_DEFAULT + ARIZONA_GP_DEFAULT + ARIZONA_GP_DEFAULT + ARIZONA_GP_DEFAULT + >; + wlf,micd-configs = <0 1 0>; + wlf,dmic-ref = < + ARIZONA_DMIC_MICVDD + ARIZONA_DMIC_MICBIAS2 + ARIZONA_DMIC_MICVDD + ARIZONA_DMIC_MICVDD + >; + wlf,inmode = < + ARIZONA_INMODE_DIFF + ARIZONA_INMODE_DMIC + ARIZONA_INMODE_SE + ARIZONA_INMODE_DIFF + >; + status = "okay"; + + arizona_ldo1: ldo1 { + regulator-name = "LDO1"; + // default constraints as in + // arizona-ldo1.c + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; + + fragment@7 { + target = <&i2c1>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + wm8804@3b { + compatible = "wlf,wm8804"; + reg = <0x3b>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlf_8804_pins>; + + PVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + wlf,reset-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; + }; + }; + }; + + fragment@8 { + target = <&sound>; + __overlay__ { + compatible = "wlf,rpi-cirrus"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/cma-overlay.dts linux/arch/arm/boot/dts/overlays/cma-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/cma-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/cma-overlay.dts 2023-12-13 11:50:48.592961256 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * cma.dts + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&cma>; + frag0: __overlay__ { + /* + * The default size when using this overlay is 256 MB + * and should be kept as is for backwards + * compatibility. + */ + size = <0x10000000>; + }; + }; + + __overrides__ { + cma-512 = <&frag0>,"size:0=",<0x20000000>; + cma-448 = <&frag0>,"size:0=",<0x1c000000>; + cma-384 = <&frag0>,"size:0=",<0x18000000>; + cma-320 = <&frag0>,"size:0=",<0x14000000>; + cma-256 = <&frag0>,"size:0=",<0x10000000>; + cma-192 = <&frag0>,"size:0=",<0xC000000>; + cma-128 = <&frag0>,"size:0=",<0x8000000>; + cma-96 = <&frag0>,"size:0=",<0x6000000>; + cma-64 = <&frag0>,"size:0=",<0x4000000>; + cma-size = <&frag0>,"size:0"; /* in bytes, 4MB aligned */ + cma-default = <0>,"-0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/cm-swap-i2c0-overlay.dts linux/arch/arm/boot/dts/overlays/cm-swap-i2c0-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/cm-swap-i2c0-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/cm-swap-i2c0-overlay.dts 2023-12-13 11:50:48.592961256 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for IMX708 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c0mux>; + i2c0mux_frag: __overlay__ { + pinctrl-0 = <&i2c0_gpio28>; + pinctrl-1 = <&i2c0_gpio0>; + }; + }; + + __overrides__ { + i2c0-gpio0 = <&i2c0mux_frag>, "pinctrl-0:0=",<&i2c0_gpio0>; + i2c0-gpio28 = <&i2c0mux_frag>, "pinctrl-0:0=",<&i2c0_gpio28>; + i2c0-gpio44 = <&i2c0mux_frag>, "pinctrl-0:0=",<&i2c0_gpio44>; + i2c10-gpio0 = <&i2c0mux_frag>, "pinctrl-1:0=",<&i2c0_gpio0>; + i2c10-gpio28 = <&i2c0mux_frag>, "pinctrl-1:0=",<&i2c0_gpio28>; + i2c10-gpio44 = <&i2c0mux_frag>, "pinctrl-1:0=",<&i2c0_gpio44>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/crystalfontz-cfa050_pi_m-overlay.dts linux/arch/arm/boot/dts/overlays/crystalfontz-cfa050_pi_m-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/crystalfontz-cfa050_pi_m-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/crystalfontz-cfa050_pi_m-overlay.dts 2023-12-13 11:50:48.592961256 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * crystalfontz-cfa050_pi_m-overlay.dts + * Configures the Crystalfontz CFA050-PI-M series of modules + * using CFAF7201280A0-050TC/TN panels with RaspberryPi CM4 DSI1 + */ +/dts-v1/; +/plugin/; +/{ +// RaspberryPi CM4 + compatible = "brcm,bcm2835"; +// PCF8574 I2C GPIO EXPANDER + fragment@0 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pcf8574a: pcf8574a@38 { + reg = <0x38>; + compatible = "nxp,pcf8574"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + gpio-line-names = "TFT_RESET", "TOUCH_RESET", "EXT_P2", "EXT_P3", + "EXT_P4", "EXT_P5", "EXT_P6", "EXT_P7"; + }; + }; + }; +// LM3630a BACKLIGHT LED CONTROLLER + fragment@1 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + lm3630a: backlight@36 { + reg = <0x36>; + compatible = "ti,lm3630a"; + #address-cells = <1>; + #size-cells = <0>; + led@0 { + reg = <0>; + led-sources = <0 1>; + label = "lcd-backlight"; + default-brightness = <128>; + max-brightness = <255>; + }; + }; + }; + }; +// CFAF7201280A0_050Tx TFT DSI PANEL + fragment@2 { + target = <&dsi1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + dsi_panel: dsi_panel@0 { + compatible = "crystalfontz,cfaf7201280a0_050tx"; + reg = <0>; + reset-gpios = <&pcf8574a 0 1>; + backlight = <&lm3630a>; + fps = <60>; + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + }; +// rPI GPIO INPUT FOR TOUCH IC IRQ + fragment@3 { + target = <&gpio>; + __dormant__ { + gt928intpins: gt928intpins { + brcm,pins = <26>; + brcm,function = <0>; + brcm,pull = <1>; + }; + }; + }; +// GT928 TOUCH CONTROLLER IC + fragment@4 { + target = <&i2c_csi_dsi>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + gt928@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + interrupt-parent = <&gpio>; + interrupts = <26 2>; + irq-gpios = <&gpio 26 0>; + reset-gpios = <&pcf8574a 1 1>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; + }; + }; +// PCF85063A RTC on I2C + fragment@5 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pcf85063a@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + }; + }; + }; +// CAPACITIVE TOUCH OPTION FOR TFT PANEL + __overrides__ { + captouch = <0>,"+3+4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/cutiepi-panel-overlay.dts linux/arch/arm/boot/dts/overlays/cutiepi-panel-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/cutiepi-panel-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/cutiepi-panel-overlay.dts 2023-12-13 11:50:48.592961256 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2711"; + + fragment@0 { + target=<&dsi1>; + + __overlay__ { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + port { + dsi1_out_port: endpoint { + remote-endpoint = <&panel_dsi_in1>; + }; + }; + + display1: panel@0 { + compatible = "nwe,nwe080"; + reg=<0>; + backlight = <&rpi_backlight>; + reset-gpios = <&gpio 20 0>; + port { + panel_dsi_in1: endpoint { + remote-endpoint = <&dsi1_out_port>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + pwm_pins: pwm_pins { + brcm,pins = <12>; + brcm,function = <4>; // ALT0 + }; + }; + }; + + fragment@2 { + target = <&pwm>; + frag1: __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + assigned-clock-rates = <1000000>; + status = "okay"; + }; + }; + + fragment@3 { + target-path = "/"; + __overlay__ { + rpi_backlight: rpi_backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 6 8 12 16 24 32 40 48 64 96 128 160 192 224 255>; + default-brightness-level = <6>; + pwms = <&pwm 0 200000>; + power-supply = <&vdd_3v3_reg>; + status = "okay"; + }; + }; + }; + + fragment@4 { + target = <&i2c6>; + frag0: __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + clock-frequency = <100000>; + }; + }; + + fragment@5 { + target = <&i2c6_pins>; + __overlay__ { + brcm,pins = <22 23>; + }; + }; + + fragment@6 { + target = <&gpio>; + __overlay__ { + goodix_pins: goodix_pins { + brcm,pins = <21 26>; // interrupt and reset + brcm,function = <0 0>; // in + brcm,pull = <2 2>; // pull-up + }; + }; + }; + + fragment@7 { + target = <&i2c6>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + gt9xx: gt9xx@5d { + compatible = "goodix,gt9271"; + reg = <0x5D>; + pinctrl-names = "default"; + pinctrl-0 = <&goodix_pins>; + interrupt-parent = <&gpio>; + interrupts = <21 2>; // high-to-low edge triggered + irq-gpios = <&gpio 21 0>; + reset-gpios = <&gpio 26 0>; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/dacberry400-overlay.dts linux/arch/arm/boot/dts/overlays/dacberry400-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/dacberry400-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/dacberry400-overlay.dts 2023-12-13 11:50:48.592961256 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for DACberry400 +/dts-v1/; +/plugin/; +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + codec_1v8_reg: codec-1v8-reg { + compatible = "regulator-fixed"; + regulator-name = "tlv320aic3104_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + codec_rst: codec-rst { + brcm,pins = <26>; + brcm,function = <1>; + }; + }; + }; + + fragment@3 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + tlv320aic3104@18 { + #sound-dai-cells = <0>; + reg = <0x18>; + + compatible = "ti,tlv320aic3x"; + AVDD-supply = <&vdd_3v3_reg>; + DRVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&codec_1v8_reg>; + IOVDD-supply = <&codec_1v8_reg>; + + gpio-controller; + reset-gpios = <&gpio 26 1>; + status = "okay"; + }; + }; + }; + + fragment@4 { + target = <&sound>; + __overlay__ { + compatible = "osaelectronics,dacberry400"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; +}; + + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/dht11-overlay.dts linux/arch/arm/boot/dts/overlays/dht11-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/dht11-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/dht11-overlay.dts 2023-12-13 11:50:48.593961259 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Overlay for the DHT11/21/22 humidity/temperature sensor modules. + */ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + dht11: dht11@4 { + compatible = "dht11"; + pinctrl-names = "default"; + pinctrl-0 = <&dht11_pins>; + gpios = <&gpio 4 0>; + status = "okay"; + #io-channel-cells = <1>; + }; + + iio: iio-hwmon@4 { + compatible = "iio-hwmon"; + status = "okay"; + io-channels = <&dht11 0>, <&dht11 1>; + }; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + dht11_pins: dht11_pins@4 { + brcm,pins = <4>; + brcm,function = <0>; // in + brcm,pull = <0>; // off + }; + }; + }; + + __overrides__ { + gpiopin = <&dht11_pins>,"brcm,pins:0", + <&dht11_pins>, "reg:0", + <&dht11>,"gpios:4", + <&dht11>,"reg:0", + <&iio>,"reg:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/dionaudio-kiwi-overlay.dts linux/arch/arm/boot/dts/overlays/dionaudio-kiwi-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/dionaudio-kiwi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/dionaudio-kiwi-overlay.dts 2023-12-13 11:50:48.593961259 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for Dion Audio KIWI streamer + +/* + * PCM1794 DAC (in hardware mode). + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + pcm1794a-codec { + #sound-dai-cells = <0>; + compatible = "ti,pcm1794a"; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "dionaudio,dionaudio-kiwi"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/dionaudio-loco-overlay.dts linux/arch/arm/boot/dts/overlays/dionaudio-loco-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/dionaudio-loco-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/dionaudio-loco-overlay.dts 2023-12-13 11:50:48.593961259 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for Dion Audio LOCO DAC-AMP + +/* + * PCM5242 DAC (in hardware mode) and TPA3118 AMP. + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + pcm5102a-codec { + #sound-dai-cells = <0>; + compatible = "ti,pcm5102a"; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "dionaudio,loco-pcm5242-tpa3118"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/dionaudio-loco-v2-overlay.dts linux/arch/arm/boot/dts/overlays/dionaudio-loco-v2-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/dionaudio-loco-v2-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/dionaudio-loco-v2-overlay.dts 2023-12-13 11:50:48.593961259 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Definitions for Dion Audio LOCO-V2 DAC-AMP + * eg. dtoverlay=dionaudio-loco-v2 + * + * PCM5242 DAC (in software mode) and TPA3255 AMP. + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&sound>; + frag0: __overlay__ { + compatible = "dionaudio,dionaudio-loco-v2"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pcm5122@4c { + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + reg = <0x4d>; + status = "okay"; + }; + }; + }; + + __overrides__ { + 24db_digital_gain = <&frag0>,"dionaudio,24db_digital_gain?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/disable-bt-overlay.dts linux/arch/arm/boot/dts/overlays/disable-bt-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/disable-bt-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/disable-bt-overlay.dts 2023-12-13 11:50:48.593961259 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/* Disable Bluetooth and restore UART0/ttyAMA0 over GPIOs 14 & 15. */ + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&uart1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&uart0>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; + }; + + fragment@2 { + target = <&bt>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&uart0_pins>; + __overlay__ { + brcm,pins; + brcm,function; + brcm,pull; + }; + }; + + fragment@4 { + target = <&bt_pins>; + __overlay__ { + brcm,pins; + brcm,function; + brcm,pull; + }; + }; + + fragment@5 { + target-path = "/aliases"; + __overlay__ { + serial0 = "/soc/serial@7e201000"; + serial1 = "/soc/serial@7e215040"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/disable-bt-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/disable-bt-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/disable-bt-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/disable-bt-pi5-overlay.dts 2023-12-13 11:50:48.593961259 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/* Disable Bluetooth */ + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&bluetooth>; + __overlay__ { + status = "disabled"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/disable-emmc2-overlay.dts linux/arch/arm/boot/dts/overlays/disable-emmc2-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/disable-emmc2-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/disable-emmc2-overlay.dts 2023-12-13 11:50:48.593961259 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&emmc2>; + __overlay__ { + status = "disabled"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/disable-wifi-overlay.dts linux/arch/arm/boot/dts/overlays/disable-wifi-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/disable-wifi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/disable-wifi-overlay.dts 2023-12-13 11:50:48.593961259 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&mmc>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&mmcnr>; + __overlay__ { + status = "disabled"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/disable-wifi-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/disable-wifi-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/disable-wifi-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/disable-wifi-pi5-overlay.dts 2023-12-13 11:50:48.594961261 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&sdio2>; + __overlay__ { + status = "disabled"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/dpi18cpadhi-overlay.dts linux/arch/arm/boot/dts/overlays/dpi18cpadhi-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/dpi18cpadhi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/dpi18cpadhi-overlay.dts 2023-12-13 11:50:48.594961261 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * dpi18cpadhi-overlay.dts + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&fb>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&dpi_18bit_cpadhi_gpio0>; + }; + }; + + fragment@1 { + target = <&vc4>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&dpi_18bit_cpadhi_gpio0>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/dpi18-overlay.dts linux/arch/arm/boot/dts/overlays/dpi18-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/dpi18-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/dpi18-overlay.dts 2023-12-13 11:50:48.594961261 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + // There is no DPI driver module, but we need a platform device + // node (that doesn't already use pinctrl) to hang the pinctrl + // reference on - leds will do + + fragment@0 { + target = <&fb>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&dpi18_pins>; + }; + }; + + fragment@1 { + target = <&vc4>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&dpi18_pins>; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + dpi18_pins: dpi18_pins { + brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 + 12 13 14 15 16 17 18 19 20 + 21>; + brcm,function = <6>; /* alt2 */ + brcm,pull = <0>; /* no pull */ + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/dpi24-overlay.dts linux/arch/arm/boot/dts/overlays/dpi24-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/dpi24-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/dpi24-overlay.dts 2023-12-13 11:50:48.594961261 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + // There is no DPI driver module, but we need a platform device + // node (that doesn't already use pinctrl) to hang the pinctrl + // reference on - leds will do + + fragment@0 { + target = <&fb>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&dpi24_pins>; + }; + }; + + fragment@1 { + target = <&vc4>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&dpi24_pins>; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + dpi24_pins: dpi24_pins { + brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 + 12 13 14 15 16 17 18 19 20 + 21 22 23 24 25 26 27>; + brcm,function = <6>; /* alt2 */ + brcm,pull = <0>; /* no pull */ + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/draws-overlay.dts linux/arch/arm/boot/dts/overlays/draws-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/draws-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/draws-overlay.dts 2023-12-13 11:50:48.594961261 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +#include <dt-bindings/clock/bcm2835.h> +/* + * Device tree overlay for the DRAWS Hardware + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + udrc0_ldoin: udrc0_ldoin { + compatible = "regulator-fixed"; + regulator-name = "ldoin"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sc16is752_clk: sc16is752_draws_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1843200>; + }; + }; + + pps: pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pps_pins>; + gpios = <&gpio 7 0>; + status = "okay"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + status = "okay"; + io-channels = <&tla2024 4>, <&tla2024 5>, <&tla2024 6>, + <&tla2024 7>; + }; + }; + }; + + fragment@2 { + target = <&i2c_arm>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + tlv320aic32x4: tlv320aic32x4@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + #sound-dai-cells = <0>; + status = "okay"; + + clocks = <&clocks BCM2835_CLOCK_GP0>; + clock-names = "mclk"; + assigned-clocks = <&clocks BCM2835_CLOCK_GP0>; + assigned-clock-rates = <25000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gpclk0_pin &aic3204_reset>; + + reset-gpios = <&gpio 13 0>; + + iov-supply = <&udrc0_ldoin>; + ldoin-supply = <&udrc0_ldoin>; + }; + + sc16is752: sc16is752@50 { + compatible = "nxp,sc16is752"; + reg = <0x50>; + clocks = <&sc16is752_clk>; + interrupt-parent = <&gpio>; + interrupts = <17 2>; /* IRQ_TYPE_EDGE_FALLING */ + + pinctrl-names = "default"; + pinctrl-0 = <&sc16is752_irq>; + }; + + tla2024: tla2024@48 { + compatible = "ti,ads1015"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc_ch4: channel@4 { + reg = <4>; + ti,gain = <1>; + ti,datarate = <4>; + }; + + adc_ch5: channel@5 { + reg = <5>; + ti,gain = <1>; + ti,datarate = <4>; + }; + + adc_ch6: channel@6 { + reg = <6>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + adc_ch7: channel@7 { + reg = <7>; + ti,gain = <2>; + ti,datarate = <4>; + }; + }; + }; + }; + + fragment@3 { + target = <&sound>; + snd: __overlay__ { + compatible = "simple-audio-card"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + + simple-audio-card,name = "draws"; + simple-audio-card,format = "i2s"; + + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out"; + + simple-audio-card,routing = + "IN1_R", "Line In", + "IN1_L", "Line In", + "CM_L", "Line In", + "CM_R", "Line In", + "Line Out", "LOR", + "Line Out", "LOL"; + + dailink0_master: simple-audio-card,cpu { + sound-dai = <&i2s_clk_producer>; + }; + + simple-audio-card,codec { + sound-dai = <&tlv320aic32x4>; + }; + }; + }; + + fragment@4 { + target = <&gpio>; + __overlay__ { + gpclk0_pin: gpclk0_pin { + brcm,pins = <4>; + brcm,function = <4>; + }; + + aic3204_reset: aic3204_reset { + brcm,pins = <13>; + brcm,function = <1>; + brcm,pull = <1>; + }; + + aic3204_gpio: aic3204_gpio { + brcm,pins = <26>; + }; + + sc16is752_irq: sc16is752_irq { + brcm,pins = <17>; + brcm,function = <0>; + brcm,pull = <2>; + }; + + pps_pins: pps_pins { + brcm,pins = <7>; + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + __overrides__ { + draws_adc_ch4_gain = <&adc_ch4>,"ti,gain:0"; + draws_adc_ch4_datarate = <&adc_ch4>,"ti,datarate:0"; + draws_adc_ch5_gain = <&adc_ch5>,"ti,gain:0"; + draws_adc_ch5_datarate = <&adc_ch5>,"ti,datarate:0"; + draws_adc_ch6_gain = <&adc_ch6>,"ti,gain:0"; + draws_adc_ch6_datarate = <&adc_ch6>,"ti,datarate:0"; + draws_adc_ch7_gain = <&adc_ch7>,"ti,gain:0"; + draws_adc_ch7_datarate = <&adc_ch7>,"ti,datarate:0"; + alsaname = <&snd>, "simple-audio-card,name"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/dwc2-overlay.dts linux/arch/arm/boot/dts/overlays/dwc2-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/dwc2-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/dwc2-overlay.dts 2023-12-13 11:50:48.594961261 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&usb>; + #address-cells = <1>; + #size-cells = <1>; + dwc2_usb: __overlay__ { + compatible = "brcm,bcm2835-usb"; + dr_mode = "otg"; + g-np-tx-fifo-size = <32>; + g-rx-fifo-size = <558>; + g-tx-fifo-size = <512 512 512 512 512 256 256>; + status = "okay"; + }; + }; + + __overrides__ { + dr_mode = <&dwc2_usb>, "dr_mode"; + g-np-tx-fifo-size = <&dwc2_usb>,"g-np-tx-fifo-size:0"; + g-rx-fifo-size = <&dwc2_usb>,"g-rx-fifo-size:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/dwc-otg-overlay.dts linux/arch/arm/boot/dts/overlays/dwc-otg-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/dwc-otg-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/dwc-otg-overlay.dts 2023-12-13 11:50:48.594961261 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&usb>; + __overlay__ { + compatible = "brcm,bcm2708-usb"; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/edt-ft5406.dtsi linux/arch/arm/boot/dts/overlays/edt-ft5406.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/edt-ft5406.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/edt-ft5406.dtsi 2023-12-13 11:50:48.595961263 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for an EDT FT5406 touchscreen + * + * Note that this is included from vc4-kms-dsi-7inch, hence the + * fragment numbers not starting at 0. + */ + +/ { + compatible = "brcm,bcm2835"; + + fragment@10 { + target = <&ft5406>; + __overlay__ { + touchscreen-inverted-x; + }; + }; + + fragment@11 { + target = <&ft5406>; + __overlay__ { + touchscreen-inverted-y; + }; + }; + + ts_i2c_frag: fragment@12 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ft5406: ts@38 { + compatible = "edt,edt-ft5506"; + reg = <0x38>; + + touchscreen-size-x = < 800 >; + touchscreen-size-y = < 480 >; + }; + }; + }; + + __overrides__ { + sizex = <&ft5406>,"touchscreen-size-x:0"; + sizey = <&ft5406>,"touchscreen-size-y:0"; + invx = <0>, "-10"; + invy = <0>, "-11"; + swapxy = <&ft5406>,"touchscreen-swapped-x-y?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/edt-ft5406-overlay.dts linux/arch/arm/boot/dts/overlays/edt-ft5406-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/edt-ft5406-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/edt-ft5406-overlay.dts 2023-12-13 11:50:48.595961263 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for EDT 5406 touchscreen controller, as used on the + * Raspberry Pi 7" panel + * + */ + +/dts-v1/; +/plugin/; + +#include "edt-ft5406.dtsi" + +/ { + fragment@0 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + __overrides__ { + i2c0 = <&ts_i2c_frag>,"target:0=",<&i2c0>; + i2c1 = <&ts_i2c_frag>, "target?=0", + <&ts_i2c_frag>, "target-path=i2c1", + <0>,"-0-1"; + i2c3 = <&ts_i2c_frag>, "target?=0", + <&ts_i2c_frag>, "target-path=i2c3", + <0>,"-0-1"; + i2c4 = <&ts_i2c_frag>, "target?=0", + <&ts_i2c_frag>, "target-path=i2c4", + <0>,"-0-1"; + i2c5 = <&ts_i2c_frag>, "target?=0", + <&ts_i2c_frag>, "target-path=i2c5", + <0>,"-0-1"; + i2c6 = <&ts_i2c_frag>, "target?=0", + <&ts_i2c_frag>, "target-path=i2c6", + <0>,"-0-1"; + addr = <&ft5406>,"reg:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/enc28j60-overlay.dts linux/arch/arm/boot/dts/overlays/enc28j60-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/enc28j60-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/enc28j60-overlay.dts 2023-12-13 11:50:48.595961263 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for the Microchip ENC28J60 Ethernet Controller +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + eth1: enc28j60@0{ + compatible = "microchip,enc28j60"; + reg = <0>; /* CE0 */ + pinctrl-names = "default"; + pinctrl-0 = <ð1_pins>; + interrupt-parent = <&gpio>; + interrupts = <25 0x2>; /* falling edge */ + spi-max-frequency = <12000000>; + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + eth1_pins: eth1_pins { + brcm,pins = <25>; + brcm,function = <0>; /* in */ + brcm,pull = <0>; /* none */ + }; + }; + }; + + __overrides__ { + int_pin = <ð1>, "interrupts:0", + <ð1_pins>, "brcm,pins:0"; + speed = <ð1>, "spi-max-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/enc28j60-spi2-overlay.dts linux/arch/arm/boot/dts/overlays/enc28j60-spi2-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/enc28j60-spi2-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/enc28j60-spi2-overlay.dts 2023-12-13 11:50:48.595961263 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for the Microchip ENC28J60 Ethernet Controller - SPI2 Compute Module +// Interrupt pin: 39 +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi2>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + eth1: enc28j60@0{ + compatible = "microchip,enc28j60"; + reg = <0>; /* CE0 */ + pinctrl-names = "default"; + pinctrl-0 = <ð1_pins>; + interrupt-parent = <&gpio>; + interrupts = <39 0x2>; /* falling edge */ + spi-max-frequency = <12000000>; + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + eth1_pins: eth1_pins { + brcm,pins = <39>; + brcm,function = <0>; /* in */ + brcm,pull = <0>; /* none */ + }; + }; + }; + + __overrides__ { + int_pin = <ð1>, "interrupts:0", + <ð1_pins>, "brcm,pins:0"; + speed = <ð1>, "spi-max-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/exc3000-overlay.dts linux/arch/arm/boot/dts/overlays/exc3000-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/exc3000-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/exc3000-overlay.dts 2023-12-13 11:50:48.595961263 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Device tree overlay for I2C connected EETI EXC3000 multiple touch controller +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + exc3000_pins: exc3000_pins { + brcm,pins = <4>; // interrupt + brcm,function = <0>; // in + brcm,pull = <2>; // pull-up + }; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + exc3000: exc3000@2a { + compatible = "eeti,exc3000"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 = <&exc3000_pins>; + interrupt-parent = <&gpio>; + interrupts = <4 8>; // active low level-sensitive + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; + }; + }; + }; + + __overrides__ { + interrupt = <&exc3000_pins>,"brcm,pins:0", + <&exc3000>,"interrupts:0"; + sizex = <&exc3000>,"touchscreen-size-x:0"; + sizey = <&exc3000>,"touchscreen-size-y:0"; + invx = <&exc3000>,"touchscreen-inverted-x?"; + invy = <&exc3000>,"touchscreen-inverted-y?"; + swapxy = <&exc3000>,"touchscreen-swapped-x-y?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/fbtft-overlay.dts linux/arch/arm/boot/dts/overlays/fbtft-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/fbtft-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/fbtft-overlay.dts 2023-12-13 11:50:48.595961263 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for fbtft drivers + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + /* adafruit18 */ + fragment@0 { + target = <&display>; + __dormant__ { + compatible = "sitronix,st7735r"; + spi-max-frequency = <32000000>; + gamma = "02 1c 07 12 37 32 29 2d 29 25 2B 39 00 01 03 10\n03 1d 07 06 2E 2C 29 2D 2E 2E 37 3F 00 00 02 10"; + }; + }; + + /* adafruit22 */ + fragment@1 { + target = <&display>; + __dormant__ { + compatible = "himax,hx8340bn"; + spi-max-frequency = <32000000>; + buswidth = <9>; + bgr; + }; + }; + + /* adafruit22a */ + fragment@2 { + target = <&display>; + __dormant__ { + compatible = "ilitek,ili9340"; + spi-max-frequency = <32000000>; + bgr; + }; + }; + + /* adafruit28 */ + fragment@3 { + target = <&display>; + __dormant__ { + compatible = "ilitek,ili9341"; + spi-max-frequency = <32000000>; + bgr; + }; + }; + + /* adafruit13m */ + fragment@4 { + target = <&display>; + __dormant__ { + compatible = "solomon,ssd1306"; + spi-max-frequency = <16000000>; + }; + }; + + /* admatec_c-berry28 */ + fragment@5 { + target = <&display>; + __dormant__ { + compatible = "sitronix,st7789v"; + spi-max-frequency = <48000000>; + init = <0x01000011 + 0x02000078 + 0x0100003A 0x05 + 0x010000B2 0x0C 0x0C 0x00 0x33 0x33 + 0x010000B7 0x35 + 0x010000C2 0x01 0xFF + 0x010000C3 0x17 + 0x010000C4 0x20 + 0x010000BB 0x17 + 0x010000C5 0x20 + 0x010000D0 0xA4 0xA1 + 0x01000029>; + gamma = "D0 00 14 15 13 2C 42 43 4E 09 16 14 18 21\nD0 00 14 15 13 0B 43 55 53 0C 17 14 23 20"; + }; + }; + + /* dogs102 */ + fragment@6 { + target = <&display>; + __dormant__ { + compatible = "UltraChip,uc1701"; + spi-max-frequency = <8000000>; + bgr; + }; + }; + + /* er_tftm050_2 */ + fragment@7 { + target = <&display>; + __dormant__ { + compatible = "raio,ra8875"; + spi-max-frequency = <5000000>; + spi-cpha; + spi-cpol; + width = <480>; + height = <272>; + bgr; + }; + }; + + /* er_tftm070_5 */ + fragment@8 { + target = <&display>; + __dormant__ { + compatible = "raio,ra8875"; + spi-max-frequency = <5000000>; + spi-cpha; + spi-cpol; + width = <800>; + height = <480>; + bgr; + }; + }; + + /* ew24ha0 */ + fragment@9 { + target = <&display>; + __dormant__ { + compatible = "ultrachip,uc1611"; + spi-max-frequency = <32000000>; + spi-cpha; + spi-cpol; + }; + }; + + /* ew24ha0_9bit */ + fragment@10 { + target = <&display>; + __dormant__ { + compatible = "ultrachip,uc1611"; + spi-max-frequency = <32000000>; + spi-cpha; + spi-cpol; + buswidth = <9>; + }; + }; + + /* freetronicsoled128 */ + fragment@11 { + target = <&display>; + __dormant__ { + compatible = "solomon,ssd1351"; + spi-max-frequency = <20000000>; + backlight = <2>; /* FBTFT_ONBOARD_BACKLIGHT */ + bgr; + }; + }; + + /* hy28a */ + fragment@12 { + target = <&display>; + __dormant__ { + compatible = "ilitek,ili9320"; + spi-max-frequency = <32000000>; + spi-cpha; + spi-cpol; + startbyte = <0x70>; + bgr; + }; + }; + + /* hy28b */ + fragment@13 { + target = <&display>; + __dormant__ { + compatible = "ilitek,ili9325"; + spi-max-frequency = <48000000>; + spi-cpha; + spi-cpol; + init = <0x010000e7 0x0010 + 0x01000000 0x0001 + 0x01000001 0x0100 + 0x01000002 0x0700 + 0x01000003 0x1030 + 0x01000004 0x0000 + 0x01000008 0x0207 + 0x01000009 0x0000 + 0x0100000a 0x0000 + 0x0100000c 0x0001 + 0x0100000d 0x0000 + 0x0100000f 0x0000 + 0x01000010 0x0000 + 0x01000011 0x0007 + 0x01000012 0x0000 + 0x01000013 0x0000 + 0x02000032 + 0x01000010 0x1590 + 0x01000011 0x0227 + 0x02000032 + 0x01000012 0x009c + 0x02000032 + 0x01000013 0x1900 + 0x01000029 0x0023 + 0x0100002b 0x000e + 0x02000032 + 0x01000020 0x0000 + 0x01000021 0x0000 + 0x02000032 + 0x01000050 0x0000 + 0x01000051 0x00ef + 0x01000052 0x0000 + 0x01000053 0x013f + 0x01000060 0xa700 + 0x01000061 0x0001 + 0x0100006a 0x0000 + 0x01000080 0x0000 + 0x01000081 0x0000 + 0x01000082 0x0000 + 0x01000083 0x0000 + 0x01000084 0x0000 + 0x01000085 0x0000 + 0x01000090 0x0010 + 0x01000092 0x0000 + 0x01000093 0x0003 + 0x01000095 0x0110 + 0x01000097 0x0000 + 0x01000098 0x0000 + 0x01000007 0x0133 + 0x01000020 0x0000 + 0x01000021 0x0000 + 0x02000064>; + startbyte = <0x70>; + bgr; + fps = <50>; + gamma = "04 1F 4 7 7 0 7 7 6 0\n0F 00 1 7 4 0 0 0 6 7"; + }; + }; + + /* itdb28_spi */ + fragment@14 { + target = <&display>; + __dormant__ { + compatible = "ilitek,ili9325"; + spi-max-frequency = <32000000>; + bgr; + }; + }; + + /* mi0283qt-2 */ + fragment@15 { + target = <&display>; + __dormant__ { + compatible = "himax,hx8347d"; + spi-max-frequency = <32000000>; + startbyte = <0x70>; + bgr; + }; + }; + + /* mi0283qt-9a */ + fragment@16 { + target = <&display>; + __dormant__ { + compatible = "ilitek,ili9341"; + spi-max-frequency = <32000000>; + buswidth = <9>; + bgr; + }; + }; + + /* nokia3310 */ + fragment@17 { + target = <&display>; + __dormant__ { + compatible = "philips,pcd8544"; + spi-max-frequency = <400000>; + }; + }; + + /* nokia3310a */ + fragment@18 { + target = <&display>; + __dormant__ { + compatible = "teralane,tls8204"; + spi-max-frequency = <1000000>; + }; + }; + + /* nokia5110 */ + fragment@19 { + target = <&display>; + __dormant__ { + compatible = "ilitek,ili9163"; + spi-max-frequency = <12000000>; + bgr; + }; + }; + + /* piscreen */ + fragment@20 { + target = <&display>; + __dormant__ { + compatible = "ilitek,ili9486"; + spi-max-frequency = <32000000>; + regwidth = <16>; + bgr; + }; + }; + + /* pitft */ + fragment@21 { + target = <&display>; + __dormant__ { + compatible = "ilitek,ili9340"; + spi-max-frequency = <32000000>; + init = <0x01000001 + 0x02000005 + 0x01000028 + 0x010000EF 0x03 0x80 0x02 + 0x010000CF 0x00 0xC1 0x30 + 0x010000ED 0x64 0x03 0x12 0x81 + 0x010000E8 0x85 0x00 0x78 + 0x010000CB 0x39 0x2C 0x00 0x34 0x02 + 0x010000F7 0x20 + 0x010000EA 0x00 0x00 + 0x010000C0 0x23 + 0x010000C1 0x10 + 0x010000C5 0x3E 0x28 + 0x010000C7 0x86 + 0x0100003A 0x55 + 0x010000B1 0x00 0x18 + 0x010000B6 0x08 0x82 0x27 + 0x010000F2 0x00 + 0x01000026 0x01 + 0x010000E0 0x0F 0x31 0x2B 0x0C 0x0E 0x08 0x4E 0xF1 0x37 0x07 0x10 0x03 0x0E 0x09 0x00 + 0x010000E1 0x00 0x0E 0x14 0x03 0x11 0x07 0x31 0xC1 0x48 0x08 0x0F 0x0C 0x31 0x36 0x0F + 0x01000011 + 0x02000064 + 0x01000029 + 0x02000014>; + bgr; + }; + }; + + /* pioled */ + fragment@22 { + target = <&display>; + __dormant__ { + compatible = "solomon,ssd1351"; + spi-max-frequency = <20000000>; + bgr; + gamma = "0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4"; + }; + }; + + /* rpi-display */ + fragment@23 { + target = <&display>; + __dormant__ { + compatible = "ilitek,ili9341"; + spi-max-frequency = <32000000>; + bgr; + }; + }; + + /* sainsmart18 */ + fragment@24 { + target = <&display>; + __dormant__ { + compatible = "sitronix,st7735r"; + spi-max-frequency = <32000000>; + }; + }; + + /* sainsmart32_spi */ + fragment@25 { + target = <&display>; + __dormant__ { + compatible = "solomon,ssd1289"; + spi-max-frequency = <16000000>; + bgr; + }; + }; + + /* tinylcd35 */ + fragment@26 { + target = <&display>; + __dormant__ { + compatible = "neosec,tinylcd"; + spi-max-frequency = <32000000>; + bgr; + }; + }; + + /* tm022hdh26 */ + fragment@27 { + target = <&display>; + __dormant__ { + compatible = "ilitek,ili9341"; + spi-max-frequency = <32000000>; + bgr; + }; + }; + + /* tontec35_9481 - boards before 02 July 2014 */ + fragment@28 { + target = <&display>; + __dormant__ { + compatible = "ilitek,ili9481"; + spi-max-frequency = <128000000>; + spi-cpha; + spi-cpol; + bgr; + }; + }; + + /* tontec35_9486 - boards after 02 July 2014 */ + fragment@29 { + target = <&display>; + __dormant__ { + compatible = "ilitek,ili9486"; + spi-max-frequency = <128000000>; + spi-cpha; + spi-cpol; + bgr; + }; + }; + + /* waveshare32b */ + fragment@30 { + target = <&display>; + __dormant__ { + compatible = "ilitek,ili9340"; + spi-max-frequency = <48000000>; + init = <0x010000CB 0x39 0x2C 0x00 0x34 0x02 + 0x010000CF 0x00 0xC1 0x30 + 0x010000E8 0x85 0x00 0x78 + 0x010000EA 0x00 0x00 + 0x010000ED 0x64 0x03 0x12 0x81 + 0x010000F7 0x20 + 0x010000C0 0x23 + 0x010000C1 0x10 + 0x010000C5 0x3E 0x28 + 0x010000C7 0x86 + 0x01000036 0x28 + 0x0100003A 0x55 + 0x010000B1 0x00 0x18 + 0x010000B6 0x08 0x82 0x27 + 0x010000F2 0x00 + 0x01000026 0x01 + 0x010000E0 0x0F 0x31 0x2B 0x0C 0x0E 0x08 0x4E 0xF1 0x37 0x07 0x10 0x03 0x0E 0x09 0x00 + 0x010000E1 0x00 0x0E 0x14 0x03 0x11 0x07 0x31 0xC1 0x48 0x08 0x0F 0x0C 0x31 0x36 0x0F + 0x01000011 + 0x02000078 + 0x01000029 + 0x0100002C>; + bgr; + }; + }; + + /* waveshare22 */ + fragment@31 { + target = <&display>; + __dormant__ { + compatible = "hitachi,bd663474"; + spi-max-frequency = <32000000>; + spi-cpha; + spi-cpol; + }; + }; + + spidev_fragment: fragment@100 { + target-path = "spi0/spidev@0"; + __overlay__ { + status = "disabled"; + }; + }; + + display_fragment: fragment@101 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + display: display@0{ + reg = <0>; + spi-max-frequency = <32000000>; + fps = <30>; + buswidth = <8>; + }; + }; + }; + + __overrides__ { + spi0-0 = <&display_fragment>, "target:0=",<&spi0>, + <&spidev_fragment>, "target-path=spi0/spidev@0", + <&display>, "reg:0=0"; + spi0-1 = <&display_fragment>, "target:0=",<&spi0>, + <&spidev_fragment>, "target-path=spi0/spidev@1", + <&display>, "reg:0=1"; + spi1-0 = <&display_fragment>, "target:0=",<&spi1>, + <&spidev_fragment>, "target-path=spi1/spidev@0", + <&display>, "reg:0=0"; + spi1-1 = <&display_fragment>, "target:0=",<&spi1>, + <&spidev_fragment>, "target-path=spi1/spidev@1", + <&display>, "reg:0=1"; + spi1-2 = <&display_fragment>, "target:0=",<&spi1>, + <&spidev_fragment>, "target-path=spi1/spidev@2", + <&display>, "reg:0=2"; + spi2-0 = <&display_fragment>, "target:0=",<&spi2>, + <&spidev_fragment>, "target-path=spi2/spidev@0", + <&display>, "reg:0=0"; + spi2-1 = <&display_fragment>, "target:0=",<&spi2>, + <&spidev_fragment>, "target-path=spi2/spidev@1", + <&display>, "reg:0=1"; + spi2-2 = <&display_fragment>, "target:0=",<&spi2>, + <&spidev_fragment>, "target-path=spi2/spidev@2", + <&display>, "reg:0=2"; + + speed = <&display>, "spi-max-frequency:0"; + cpha = <&display>, "spi-cpha?"; + cpol = <&display>, "spi-cpol?"; + + /* Displays */ + adafruit18 = <0>, "+0"; + adafruit22 = <0>, "+1"; + adafruit22a = <0>, "+2"; + adafruit28 = <0>, "+3"; + adafruit13m = <0>, "+4"; + admatec_c-berry28 = <0>, "+5"; + dogs102 = <0>, "+6"; + er_tftm050_2 = <0>, "+7"; + er_tftm070_5 = <0>, "+8"; + ew24ha0 = <0>, "+9"; + ew24ha0_9bit = <0>, "+10"; + freetronicsoled128 = <0>, "+11"; + hy28a = <0>, "+12"; + hy28b = <0>, "+13"; + itdb28_spi = <0>, "+14"; + mi0283qt-2 = <0>, "+15"; + mi0283qt-9a = <0>, "+16"; + nokia3310 = <0>, "+17"; + nokia3310a = <0>, "+18"; + nokia5110 = <0>, "+19"; + piscreen = <0>, "+20"; + pitft = <0>, "+21"; + pioled = <0>, "+22"; + rpi-display = <0>, "+23"; + sainsmart18 = <0>, "+24"; + sainsmart32_spi = <0>, "+25"; + tinylcd35 = <0>, "+26"; + tm022hdh26 = <0>, "+27"; + tontec35_9481 = <0>, "+28"; + tontec35_9486 = <0>, "+29"; + waveshare32b = <0>, "+30"; + waveshare22 = <0>, "+31"; + + /* Controllers */ + bd663474 = <&display>, "compatible=hitachi,bd663474"; + hx8340bn = <&display>, "compatible=himax,hx8340bn"; + hx8347d = <&display>, "compatible=himax,hx8347d"; + hx8353d = <&display>, "compatible=himax,hx8353d"; + hx8357d = <&display>, "compatible=himax,hx8357d"; + ili9163 = <&display>, "compatible=ilitek,ili9163"; + ili9320 = <&display>, "compatible=ilitek,ili9320"; + ili9325 = <&display>, "compatible=ilitek,ili9325"; + ili9340 = <&display>, "compatible=ilitek,ili9340"; + ili9341 = <&display>, "compatible=ilitek,ili9341"; + ili9481 = <&display>, "compatible=ilitek,ili9481"; + ili9486 = <&display>, "compatible=ilitek,ili9486"; + pcd8544 = <&display>, "compatible=philips,pcd8544"; + ra8875 = <&display>, "compatible=raio,ra8875"; + s6d02a1 = <&display>, "compatible=samsung,s6d02a1"; + s6d1121 = <&display>, "compatible=samsung,s6d1121"; + seps525 = <&display>, "compatible=syncoam,seps525"; + sh1106 = <&display>, "compatible=sinowealth,sh1106"; + ssd1289 = <&display>, "compatible=solomon,ssd1289"; + ssd1305 = <&display>, "compatible=solomon,ssd1305"; + ssd1306 = <&display>, "compatible=solomon,ssd1306"; + ssd1325 = <&display>, "compatible=solomon,ssd1325"; + ssd1331 = <&display>, "compatible=solomon,ssd1331"; + ssd1351 = <&display>, "compatible=solomon,ssd1351"; + st7735r = <&display>, "compatible=sitronix,st7735r"; + st7789v = <&display>, "compatible=sitronix,st7789v"; + tls8204 = <&display>, "compatible=teralane,tls8204"; + uc1611 = <&display>, "compatible=ultrachip,uc1611"; + uc1701 = <&display>, "compatible=UltraChip,uc1701"; + upd161704 = <&display>, "compatible=nec,upd161704"; + + width = <&display>, "width:0"; + height = <&display>, "height:0"; + regwidth = <&display>, "regwidth:0"; + buswidth = <&display>, "buswidth:0"; + debug = <&display>, "debug:0"; + rotate = <&display>, "rotate:0"; + bgr = <&display>, "bgr?"; + fps = <&display>, "fps:0"; + txbuflen = <&display>, "txbuflen:0"; + startbyte = <&display>, "startbyte:0"; + gamma = <&display>, "gamma"; + + reset_pin = <&display>, "reset-gpios:0=", <&gpio>, + <&display>, "reset-gpios:4", + <&display>, "reset-gpios:8=1"; /* GPIO_ACTIVE_LOW */ + dc_pin = <&display>, "dc-gpios:0=", <&gpio>, + <&display>, "dc-gpios:4", + <&display>, "dc-gpios:8=0"; /* GPIO_ACTIVE_HIGH */ + led_pin = <&display>, "led-gpios:0=", <&gpio>, + <&display>, "led-gpios:4", + <&display>, "led-gpios:8=0"; /* GPIO_ACTIVE_HIGH */ + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts linux/arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts 2023-12-13 11:50:48.595961263 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for Fe-Pi Audio +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + sgtl5000_mclk: sgtl5000_mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "sgtl5000-mclk"; + }; + }; + }; + + fragment@1 { + target = <&soc>; + __overlay__ { + reg_1v8: reg_1v8@0 { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + sgtl5000@a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sgtl5000_mclk>; + micbias-resistor-k-ohms = <2>; + micbias-voltage-m-volts = <3000>; + VDDA-supply = <&vdd_3v3_reg>; + VDDIO-supply = <&vdd_3v3_reg>; + VDDD-supply = <®_1v8>; + status = "okay"; + }; + }; + }; + + fragment@3 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&sound>; + __overlay__ { + compatible = "fe-pi,fe-pi-audio"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/fsm-demo-overlay.dts linux/arch/arm/boot/dts/overlays/fsm-demo-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/fsm-demo-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/fsm-demo-overlay.dts 2023-12-13 11:50:48.596961266 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Demo overlay for the gpio-fsm driver +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio-fsm.h> + +#define BUTTON1 GF_IP(0) +#define BUTTON2 GF_SW(0) +#define RED GF_OP(0) // GPIO7 +#define AMBER GF_OP(1) // GPIO8 +#define GREEN GF_OP(2) // GPIO25 + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + fsm_demo: fsm-demo { + compatible = "rpi,gpio-fsm"; + + debug = <0>; + gpio-controller; + #gpio-cells = <2>; + num-swgpios = <1>; + gpio-line-names = "button2"; + input-gpios = <&gpio 6 1>; // BUTTON1 (active-low) + output-gpios = <&gpio 7 0>, // RED + <&gpio 8 0>, // AMBER + <&gpio 25 0>; // GREEN + shutdown-timeout-ms = <2000>; + + start { + start_state; + set = <RED 1>, <AMBER 0>, <GREEN 0>; + start2 = <GF_DELAY 250>; + }; + + start2 { + set = <RED 0>, <AMBER 1>; + go = <GF_DELAY 250>; + }; + + go { + set = <RED 0>, <AMBER 0>, <GREEN 1>; + ready_wait = <BUTTON1 0>; + shutdown1 = <GF_SHUTDOWN 0>; + }; + + ready_wait { + // Clear the soft GPIO + set = <BUTTON2 0>; + ready = <GF_DELAY 1000>; + shutdown1 = <GF_SHUTDOWN 0>; + }; + + ready { + stopping = <BUTTON1 1>, <BUTTON2 1>; + shutdown1 = <GF_SHUTDOWN 0>; + }; + + stopping { + set = <GREEN 0>, <AMBER 1>; + stopped = <GF_DELAY 1000>; + }; + + stopped { + set = <AMBER 0>, <RED 1>; + get_set = <GF_DELAY 3000>; + shutdown1 = <GF_SHUTDOWN 0>; + }; + + get_set { + set = <AMBER 1>; + go = <GF_DELAY 1000>; + }; + + shutdown1 { + set = <RED 0>, <AMBER 0>, <GREEN 1>; + shutdown2 = <GF_SHUTDOWN 250>; + }; + + shutdown2 { + set = <AMBER 1>, <GREEN 0>; + shutdown3 = <GF_SHUTDOWN 250>; + }; + + shutdown3 { + set = <RED 1>, <AMBER 0>; + shutdown4 = <GF_SHUTDOWN 250>; + }; + + shutdown4 { + shutdown_state; + set = <RED 0>, <AMBER 0>, <GREEN 0>; + }; + }; + }; + }; + + __overrides__ { + fsm_debug = <&fsm_demo>,"debug:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/gc9a01-overlay.dts linux/arch/arm/boot/dts/overlays/gc9a01-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/gc9a01-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/gc9a01-overlay.dts 2023-12-13 11:50:48.596961266 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + Device Tree overlay for Galaxycore GC9A01A single chip driver + for use on SPI TFT LCD, 240x240 65K RGB + Based on Galaxycore's GC9A01A datasheet Rev.1.0 (2019/07/02) + Copyright (C) 2022, Julianno F. C. Silva (@juliannojungle) + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU Affero General Public License as published + by the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU Affero General Public License for more details. + + You should have received a copy of the GNU Affero General Public License + along with this program. If not, see <https://www.gnu.org/licenses/agpl-3.0.html>. + + Init sequence partially based on Waveshare team's Arduino LCD_Driver V1.0 (2020/12/09). + + Permission is hereby granted, free of UBYTEge, to any person obtaining a copy + of this software and associated documnetation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + gc9a01_pins: gc9a01_pins { + brcm,pins = <25 27>; + brcm,function = <1 1>; /* out */ + brcm,pull = <0 0>; /* none */ + }; + }; + }; + + fragment@2 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + gc9a01: gc9a01@0 { + compatible = "ilitek,ili9340"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&gc9a01_pins>; + reset-gpios = <&gpio 27 1>; + dc-gpios = <&gpio 25 0>; + led-gpios = <&gpio 18 0>; + spi-max-frequency = <40000000>; + buswidth = <8>; + width = <240>; + height = <240>; + rotate = <0>; + fps = <50>; + bgr; + debug = <0>; + init = < + 0x01000011 /* Sleep mode OFF */ + 0x02000078 /* Delay 120ms */ + 0x010000EF /* Inter register enable 2 */ + 0x010000EB 0x14 + /* BEGIN set inter_command HIGH */ + 0x010000FE /* Inter register enable 1 */ + 0x010000EF /* Inter register enable 2 */ + /* END set inter_command HIGH */ + 0x010000EB 0x14 + 0x01000084 0x40 + 0x01000085 0xFF + 0x01000086 0xFF + 0x01000087 0xFF + 0x01000088 0x0A + 0x01000089 0x21 + 0x0100008A 0x00 + 0x0100008B 0x80 + 0x0100008C 0x01 + 0x0100008D 0x01 + 0x0100008E 0xFF + 0x0100008F 0xFF + 0x010000B6 0x00 0x00 /* Display function control */ + 0x01000036 0x08 /* Memory access control */ + 0x0100003A 0x05 /* Pixel format */ + 0x01000090 0x08 0x08 0x08 0x08 + 0x010000BD 0x06 + 0x010000BC 0x00 + 0x010000FF 0x60 0x01 0x04 + 0x010000C3 0x13 /* Voltage regulator 1a */ + 0x010000C4 0x13 /* Voltage regulator 1b */ + 0x010000C9 0x22 /* Voltage regulator 2a */ + 0x010000BE 0x11 + 0x010000E1 0x10 0x0E + 0x010000DF 0x21 0x0c 0x02 + 0x010000F0 0x45 0x09 0x08 0x08 0x26 0x2A /* Set gamma1 */ + 0x010000F1 0x43 0x70 0x72 0x36 0x37 0x6F /* Set gamma2 */ + 0x010000F2 0x45 0x09 0x08 0x08 0x26 0x2A /* Set gamma3 */ + 0x010000F3 0x43 0x70 0x72 0x36 0x37 0x6F /* Set gamma4 */ + 0x010000ED 0x1B 0x0B + 0x010000AE 0x77 + 0x010000CD 0x63 + 0x01000070 0x07 0x07 0x04 0x0E 0x0F 0x09 0x07 0x08 0x03 + 0x010000E8 0x34 /* Frame rate */ + 0x01000062 0x18 0x0D 0x71 0xED 0x70 0x70 0x18 0x0F 0x71 0xEF 0x70 0x70 + 0x01000063 0x18 0x11 0x71 0xF1 0x70 0x70 0x18 0x13 0x71 0xF3 0x70 0x70 + 0x01000064 0x28 0x29 0xF1 0x01 0xF1 0x00 0x07 + 0x01000066 0x3C 0x00 0xCD 0x67 0x45 0x45 0x10 0x00 0x00 0x00 + 0x01000067 0x00 0x3C 0x00 0x00 0x00 0x01 0x54 0x10 0x32 0x98 + 0x01000074 0x10 0x85 0x80 0x00 0x00 0x4E 0x00 + 0x01000098 0x3e 0x07 + 0x01000035 /* Tearing effect ON */ + 0x01000021 /* Display inversion ON */ + 0x01000011 /* Sleep mode OFF */ + 0x0200000C /* Delay 12ms */ + 0x01000029 /* Display ON */ + 0x02000014 /* Delay 20ms */ + >; + }; + }; + }; + + __overrides__ { + speed = <&gc9a01>,"spi-max-frequency:0"; + rotate = <&gc9a01>,"rotate:0"; + width = <&gc9a01>,"width:0"; + height = <&gc9a01>,"height:0"; + fps = <&gc9a01>,"fps:0"; + debug = <&gc9a01>,"debug:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts linux/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts 2023-12-13 11:50:48.596961266 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for the PCM5122-based Ghost amplifier using gpio-fsm +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio-fsm.h> + +#define ENABLE GF_SW(0) +#define FAULT GF_IP(0) // GPIO5 +#define RELAY1 GF_OP(0) // GPIO22 +#define RELAY2 GF_OP(1) // GPIO23 +#define RELAYSSR GF_OP(2) // GPIO24 + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pcm5122@4c { + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + reg = <0x4c>; + AVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + CPVDD-supply = <&vdd_3v3_reg>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + iqaudio_dac: __overlay__ { + compatible = "iqaudio,iqaudio-dac"; + i2s-controller = <&i2s_clk_producer>; + mute-gpios = <& 0 0>; + iqaudio-dac,auto-mute-amp; + status = "okay"; + }; + }; + + fragment@3 { + target-path = "/"; + __overlay__ { + amp: ghost-amp { + compatible = "rpi,gpio-fsm"; + pinctrl-names = "default"; + pinctrl-0 = <&ghost_amp_pins>; + + debug = <0>; + gpio-controller; + #gpio-cells = <2>; + num-swgpios = <1>; + gpio-line-names = "enable"; + input-gpios = <&gpio 5 1>; // FAULT (active low) + output-gpios = <&gpio 22 0>, // RELAY1 + <&gpio 23 0>, // RELAY2 + <&gpio 24 0>; // RELAYSSR + shutdown-timeout-ms = <1000>; + + amp_off { + start_state; + shutdown_state; + + set = <RELAYSSR 0>, + <RELAY2 0>, + <RELAY1 0>; + amp_on_1 = <ENABLE 1>; + fault = <FAULT 1>; + }; + + amp_on_1 { + set = <RELAY1 1>; + amp_on_2 = <GF_DELAY 1000>; + amp_off = <GF_SHUTDOWN 0>; + fault = <FAULT 1>; + }; + + amp_on_2 { + set = <RELAY2 1>; + amp_on_wait = <ENABLE 0>; + amp_on = <GF_DELAY 1>; + fault = <FAULT 1>; + }; + + amp_on { + set = <RELAYSSR 1>; + amp_on_wait = <ENABLE 0>; + fault = <FAULT 1>; + }; + + amp_on_wait { + set = <RELAYSSR 0>; + amp_off_1 = <GF_DELAY (30*60*1000)>, + <GF_SHUTDOWN 0>; + amp_on = <ENABLE 1>; + fault = <FAULT 1>; + }; + + amp_off_1 { + set = <RELAY2 0>; + amp_on = <ENABLE 1>; + amp_off = <GF_DELAY 100>; + fault = <FAULT 1>; + }; + + // Keep this a distinct state to prevent + // changes and for the diagnostic output + fault { + set = <RELAYSSR 0>, + <RELAY2 0>, + <RELAY1 0>; + amp_off = <FAULT 0>; + shutdown_state; + }; + }; + }; + }; + + fragment@4 { + target = <&gpio>; + __overlay__ { + ghost_amp_pins: ghost_amp_pins { + brcm,pins = <5 22 23 24>; + brcm,function = <0 1 1 1>; /* in out out out */ + brcm,pull = <2 0 0 0>; /* up none none none */ + }; + }; + }; + + __overrides__ { + fsm_debug = <&>,"debug:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/goodix-overlay.dts linux/arch/arm/boot/dts/overlays/goodix-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/goodix-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/goodix-overlay.dts 2023-12-13 11:50:48.596961266 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Device tree overlay for I2C connected Goodix gt9271 multiple touch controller +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + goodix_pins: goodix_pins { + brcm,pins = <4 17>; // interrupt and reset + brcm,function = <0 0>; // in + brcm,pull = <2 2>; // pull-up + }; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + gt9271: gt9271@14 { + compatible = "goodix,gt9271"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&goodix_pins>; + interrupt-parent = <&gpio>; + interrupts = <4 2>; // high-to-low edge triggered + irq-gpios = <&gpio 4 0>; // Pin7 on GPIO header + reset-gpios = <&gpio 17 0>; // Pin11 on GPIO header + }; + }; + }; + + __overrides__ { + interrupt = <&goodix_pins>,"brcm,pins:0", + <>9271>,"interrupts:0", + <>9271>,"irq-gpios:4"; + reset = <&goodix_pins>,"brcm,pins:4", + <>9271>,"reset-gpios:4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/googlevoicehat-soundcard-overlay.dts linux/arch/arm/boot/dts/overlays/googlevoicehat-soundcard-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/googlevoicehat-soundcard-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/googlevoicehat-soundcard-overlay.dts 2023-12-13 11:50:48.596961266 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for Google voiceHAT v1 soundcard overlay +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + googlevoicehat_pins: googlevoicehat_pins { + brcm,pins = <16>; + brcm,function = <1>; /* out */ + brcm,pull = <0>; /* up */ + }; + }; + }; + + + fragment@2 { + target-path = "/"; + __overlay__ { + voicehat-codec { + #sound-dai-cells = <0>; + compatible = "google,voicehat"; + pinctrl-names = "default"; + pinctrl-0 = <&googlevoicehat_pins>; + sdmode-gpios= <&gpio 16 0>; + status = "okay"; + }; + }; + }; + + fragment@3 { + target = <&sound>; + __overlay__ { + compatible = "googlevoicehat,googlevoicehat-soundcard"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/gpio-charger-overlay.dts linux/arch/arm/boot/dts/overlays/gpio-charger-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/gpio-charger-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/gpio-charger-overlay.dts 2023-12-13 11:50:48.596961266 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for gpio-charger module +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + // Configure the gpio pin controller + target = <&gpio>; + __overlay__ { + pin_state: charger_pins@0 { + brcm,pins = <4>; // gpio number + brcm,function = <0>; // 0 = input, 1 = output + brcm,pull = <1>; // 0 = none, 1 = pull down, 2 = pull up + }; + }; + }; + fragment@1 { + target-path = "/"; + __overlay__ { + charger: charger@0 { + compatible = "gpio-charger"; + pinctrl-0 = <&pin_state>; + status = "okay"; + gpios = <&gpio 4 0>; + charger-type = "mains"; + }; + }; + }; + + __overrides__ { + gpio = <&charger>,"reg:0", + <&charger>,"gpios:4", + <&pin_state>,"reg:0", + <&pin_state>,"brcm,pins:0"; + type = <&charger>,"charger-type"; + gpio_pull = <&pin_state>,"brcm,pull:0"; + active_low = <&charger>,"gpios:8"; + }; + +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/gpio-fan-overlay.dts linux/arch/arm/boot/dts/overlays/gpio-fan-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/gpio-fan-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/gpio-fan-overlay.dts 2023-12-13 11:50:48.597961268 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Overlay for the Raspberry Pi GPIO Fan @ BCM GPIO12. + * References: + * - https://www.raspberrypi.org/forums/viewtopic.php?f=107&p=1367135#p1365084 + * + * Optional parameters: + * - "gpiopin" - BCM number of the pin driving the fan, default 12 (GPIO12); + * - "temp" - CPU temperature at which fan is started in millicelsius, default 55000; + * + * Requires: + * - kernel configurations: CONFIG_SENSORS_GPIO_FAN=m; + * - kernel rebuild; + * - N-MOSFET connected to gpiopin, 2N7002-[https://en.wikipedia.org/wiki/2N7000]; + * - DC Fan connected to N-MOSFET Drain terminal, a 12V fan is working fine and quite silently; + * [https://www.tme.eu/en/details/ee40101s1-999-a/dc12v-fans/sunon/ee40101s1-1000u-999/] + * + * ┌─────────────────────┐ + * │Fan negative terminal│ + * └┬────────────────────┘ + * │D + * G │──┘ + * [GPIO12]──────┤ │<─┐ 2N7002 + * │──┤ + * │S + * ─┴─ + * GND + * + * Build: + * - `sudo dtc -W no-unit_address_vs_reg -@ -I dts -O dtb -o /boot/overlays/gpio-fan.dtbo gpio-fan-overlay.dts` + * Activate: + * - sudo nano /boot/config.txt add "dtoverlay=gpio-fan" or "dtoverlay=gpio-fan,gpiopin=12,temp=45000" + * or + * - sudo sh -c 'printf "\n# Enable PI GPIO-Fan Default\ndtoverlay=gpio-fan\n" >> /boot/config.txt' + * - sudo sh -c 'printf "\n# Enable PI GPIO-Fan Custom\ndtoverlay=gpio-fan,gpiopin=12,temp=45000\n" >> /boot/config.txt' + * + */ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + fan0: gpio-fan@0 { + compatible = "gpio-fan"; + gpios = <&gpio 12 0>; + gpio-fan,speed-map = <0 0>, + <5000 1>; + #cooling-cells = <2>; + }; + }; + }; + + fragment@1 { + target = <&cpu_thermal>; + __overlay__ { + polling-delay = <2000>; /* milliseconds */ + }; + }; + + fragment@2 { + target = <&thermal_trips>; + __overlay__ { + cpu_hot: trip-point@0 { + temperature = <55000>; /* (millicelsius) Fan started at 55°C */ + hysteresis = <10000>; /* (millicelsius) Fan stopped at 45°C */ + type = "active"; + }; + }; + }; + + fragment@3 { + target = <&cooling_maps>; + __overlay__ { + map0 { + trip = <&cpu_hot>; + cooling-device = <&fan0 1 1>; + }; + }; + }; + + __overrides__ { + gpiopin = <&fan0>,"gpios:4", <&fan0>,"brcm,pins:0"; + temp = <&cpu_hot>,"temperature:0"; + hyst = <&cpu_hot>,"hysteresis:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/gpio-hog-overlay.dts linux/arch/arm/boot/dts/overlays/gpio-hog-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/gpio-hog-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/gpio-hog-overlay.dts 2023-12-13 11:50:48.597961268 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Configure a "hog" on the specified GPIO +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + hog: hog@1a { + gpio-hog; + gpios = <26 GPIO_ACTIVE_HIGH>; + output-high; + }; + }; + }; + + __overrides__ { + gpio = <&hog>,"reg:0", + <&hog>,"gpios:0"; + active_low = <&hog>,"output-high!", + <&hog>,"output-low?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts linux/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts 2023-12-13 11:50:48.597961268 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for ir-gpio module +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + gpio_ir: ir-receiver@12 { + compatible = "gpio-ir-receiver"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_ir_pins>; + + // pin number, high or low + gpios = <&gpio 18 1>; + + // parameter for keymap name + linux,rc-map-name = "rc-rc6-mce"; + + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + gpio_ir_pins: gpio_ir_pins@12 { + brcm,pins = <18>; // pin 18 + brcm,function = <0>; // in + brcm,pull = <2>; // up + }; + }; + }; + + __overrides__ { + // parameters + gpio_pin = <&gpio_ir>,"gpios:4", // pin number + <&gpio_ir>,"reg:0", + <&gpio_ir_pins>,"brcm,pins:0", + <&gpio_ir_pins>,"reg:0"; + gpio_pull = <&gpio_ir_pins>,"brcm,pull:0"; // pull-up/down state + invert = <&gpio_ir>,"gpios:8"; // 0 = active high input + + rc-map-name = <&gpio_ir>,"linux,rc-map-name"; // default rc map + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/gpio-ir-tx-overlay.dts linux/arch/arm/boot/dts/overlays/gpio-ir-tx-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/gpio-ir-tx-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/gpio-ir-tx-overlay.dts 2023-12-13 11:50:48.597961268 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + gpio_ir_tx_pins: gpio_ir_tx_pins@12 { + brcm,pins = <18>; + brcm,function = <1>; // out + }; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + gpio_ir_tx: gpio-ir-transmitter@12 { + compatible = "gpio-ir-tx"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_ir_tx_pins>; + gpios = <&gpio 18 0>; + }; + }; + }; + + __overrides__ { + gpio_pin = <&gpio_ir_tx>, "gpios:4", // pin number + <&gpio_ir_tx>, "reg:0", + <&gpio_ir_tx_pins>, "brcm,pins:0", + <&gpio_ir_tx_pins>, "reg:0"; + invert = <&gpio_ir_tx>, "gpios:8"; // 1 = active low + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/gpio-key-overlay.dts linux/arch/arm/boot/dts/overlays/gpio-key-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/gpio-key-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/gpio-key-overlay.dts 2023-12-13 11:50:48.597961268 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for gpio-key module +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + // Configure the gpio pin controller + target = <&gpio>; + __overlay__ { + pin_state: button_pins@0 { + brcm,pins = <3>; // gpio number + brcm,function = <0>; // 0 = input, 1 = output + brcm,pull = <2>; // 0 = none, 1 = pull down, 2 = pull up + }; + }; + }; + fragment@1 { + target-path = "/"; + __overlay__ { + button: button@0 { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pin_state>; + status = "okay"; + + key: key { + linux,code = <116>; + gpios = <&gpio 3 1>; + label = "KEY_POWER"; + }; + }; + }; + }; + + __overrides__ { + gpio = <&key>,"gpios:4", + <&button>,"reg:0", + <&pin_state>,"brcm,pins:0", + <&pin_state>,"reg:0"; + label = <&key>,"label"; + keycode = <&key>,"linux,code:0"; + gpio_pull = <&pin_state>,"brcm,pull:0"; + active_low = <&key>,"gpios:8"; + }; + +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/gpio-led-overlay.dts linux/arch/arm/boot/dts/overlays/gpio-led-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/gpio-led-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/gpio-led-overlay.dts 2023-12-13 11:50:48.597961268 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * gpio-led - generic connection of kernel's LED framework to the RPI's GPIO. + * Copyright (C) 2021 House Gordon Software Company Ltd. <assafgordon@gmail.com> + * + * Based on information from: + * https://mjoldfield.com/atelier/2017/03/rpi-devicetree.html + * https://www.raspberrypi.org/documentation/configuration/device-tree.md + * https://www.kernel.org/doc/html/latest/leds/index.html + * + * compile with: + * dtc -@ -Hepapr -I dts -O dtb -o gpio-led.dtbo gpio-led-overlay.dts + * + * There will be some warnings (can be ignored): + * Warning (label_is_string): /__overrides__:label: property is not a string + * Warning (unit_address_vs_reg): /fragment@0/__overlay__/led_pins@0: + * node has a unit name, but no reg property + * Warning (unit_address_vs_reg): /fragment@1/__overlay__/leds@0: + * node has a unit name, but no reg property + * Warning (gpios_property): /__overrides__: Missing property + * '#gpio-cells' in node /fragment@1/__overlay__/leds@0/led + * or bad phandle (referred from gpio[0]) + * + * Typical electrical connection is: + * RPI-GPIO.19 -> LED -> 300ohm resister -> RPI-GND + * The GPIO pin number can be changed with the 'gpio=' parameter. + * + * Test from user-space with: + * # if nothing is shown, the overlay file isn't found in /boot/overlays + * dtoverlay -a | grep gpio-led + * + * # Load the overlay + * dtoverlay gpio-led label=moo gpio=19 + * + * # if nothing is shown, the overlay wasn't loaded successfully + * dtoverlay -l | grep gpio-led + * + * echo 1 > /sys/class/leds/moo/brightness + * echo 0 > /sys/class/leds/moo/brightness + * echo cpu > /sys/class/leds/moo/trigger + * echo heartbeat > /sys/class/leds/moo/trigger + * + * # unload the overlay + * dtoverlay -r gpio-led + * + * To load in /boot/config.txt add lines such as: + * dtoverlay=gpio-led,gpio=19,label=heart,trigger=heartbeat + * dtoverlay=gpio-led,gpio=26,label=brain,trigger=cpu + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + // Configure the gpio pin controller + target = <&gpio>; + __overlay__ { + led_pin: led_pins@19 { + brcm,pins = <19>; // gpio number + brcm,function = <1>; // 0 = input, 1 = output + brcm,pull = <0>; // 0 = none, 1 = pull down, 2 = pull up + }; + }; + }; + fragment@1 { + target-path = "/"; + __overlay__ { + leds: leds@0 { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin>; + status = "okay"; + + led: led { + label = "myled1"; + gpios = <&gpio 19 0>; + linux,default-trigger = "none"; + }; + }; + }; + }; + + __overrides__ { + gpio = <&led>,"gpios:4", + <&leds>,"reg:0", + <&led_pin>,"brcm,pins:0", + <&led_pin>,"reg:0"; + label = <&led>,"label"; + active_low = <&led>,"gpios:8"; + trigger = <&led>,"linux,default-trigger"; + }; + +}; + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/gpio-no-bank0-irq-overlay.dts linux/arch/arm/boot/dts/overlays/gpio-no-bank0-irq-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/gpio-no-bank0-irq-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/gpio-no-bank0-irq-overlay.dts 2023-12-13 11:50:48.597961268 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + // Configure the gpio pin controller + target = <&gpio>; + __overlay__ { + interrupts = <255 255>, <2 18>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/gpio-no-irq-overlay.dts linux/arch/arm/boot/dts/overlays/gpio-no-irq-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/gpio-no-irq-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/gpio-no-irq-overlay.dts 2023-12-13 11:50:48.598961271 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + // Configure the gpio pin controller + target = <&gpio>; + __overlay__ { + interrupts; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts linux/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts 2023-12-13 11:50:48.598961271 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for gpio-poweroff module +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + power_ctrl: power_ctrl { + compatible = "gpio-poweroff"; + gpios = <&gpio 26 0>; + force; + }; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + power_ctrl_pins: power_ctrl_pins { + brcm,pins = <26>; + brcm,function = <1>; // out + }; + }; + }; + + __overrides__ { + gpiopin = <&power_ctrl>,"gpios:4", + <&power_ctrl_pins>,"brcm,pins:0"; + active_low = <&power_ctrl>,"gpios:8"; + input = <&power_ctrl>,"input?"; + export = <&power_ctrl>,"export?"; + timeout_ms = <&power_ctrl>,"timeout-ms:0"; + active_delay_ms = <&power_ctrl>,"active-delay-ms:0"; + inactive_delay_ms = <&power_ctrl>,"inactive-delay-ms:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts linux/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts 2023-12-13 11:50:48.598961271 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for gpio-poweroff module +/dts-v1/; +/plugin/; + +// This overlay sets up an input device that generates KEY_POWER events +// when a given GPIO pin changes. It defaults to using GPIO3, which can +// also be used to wake up (start) the Rpi again after shutdown. +// Raspberry Pi 1 Model B rev 1 can be wake up only by GPIO1 pin, so for +// these boards change default GPIO pin to 1 via gpio_pin parameter. Since +// wakeup is active-low, this defaults to active-low with a pullup +// enabled, but all of this can be changed using overlay parameters (but +// note that GPIO3 has an external pullup on at least some boards). + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + // Configure the gpio pin controller + target = <&gpio>; + __overlay__ { + // Define a pinctrl state, that sets up the gpio + // as an input with a pullup enabled. This does + // not take effect by itself, only when referenced + // by a "pinctrl client", as is done below. See: + // https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + // https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt + pin_state: shutdown_button_pins@3 { + brcm,pins = <3>; // gpio number + brcm,function = <0>; // 0 = input, 1 = output + brcm,pull = <2>; // 0 = none, 1 = pull down, 2 = pull up + }; + }; + }; + fragment@1 { + // Add a new device to the /soc devicetree node + target-path = "/soc"; + __overlay__ { + shutdown_button: shutdown_button@3 { + // Let the gpio-keys driver handle this device. See: + // https://www.kernel.org/doc/Documentation/devicetree/bindings/input/gpio-keys.txt + compatible = "gpio-keys"; + + // Declare a single pinctrl state (referencing the one declared above) and name it + // default, so it is activated automatically. + pinctrl-names = "default"; + pinctrl-0 = <&pin_state>; + + // Enable this device + status = "okay"; + + // Define a single key, called "shutdown" that monitors the gpio and sends KEY_POWER + // (keycode 116, see + // https://github.com/torvalds/linux/blob/v4.12/include/uapi/linux/input-event-codes.h#L190) + button: shutdown { + label = "shutdown"; + linux,code = <116>; // KEY_POWER + gpios = <&gpio 3 1>; + debounce-interval = <100>; // ms + }; + }; + }; + }; + + // This defines parameters that can be specified when loading + // the overlay. Each foo = line specifies one parameter, named + // foo. The rest of the specification gives properties where the + // parameter value is inserted into (changing the values above + // or adding new ones). + __overrides__ { + // Allow overriding the GPIO number. + gpio_pin = <&button>,"gpios:4", + <&shutdown_button>,"reg:0", + <&pin_state>,"reg:0", + <&pin_state>,"brcm,pins:0"; + + // Allow changing the internal pullup/down state. 0 = none, 1 = pulldown, 2 = pullup + // Note that GPIO3 and GPIO2 are the I2c pins and have an external pullup (at least + // on some boards). Same applies for GPIO1 on Raspberry Pi 1 Model B rev 1. + gpio_pull = <&pin_state>,"brcm,pull:0"; + + // Allow setting the active_low flag. 0 = active high, 1 = active low + active_low = <&button>,"gpios:8"; + debounce = <&button>,"debounce-interval:0"; + }; + +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hat_map.dts linux/arch/arm/boot/dts/overlays/hat_map.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hat_map.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hat_map.dts 2023-12-13 11:50:48.598961271 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; + +/ { + iqaudio-pi-codecplus { + uuid = [ dc1c9594 c1ab 4c6c acda a88dc59a3c5b ]; + overlay = "iqaudio-codec"; + }; + + pisound { + uuid = [ a7ee5d28 da03 41f5 bbd7 20438a4bec5d ]; + overlay = "pisound"; + }; + + recalbox-rgbdual { + uuid = [ 1c955808 681f 4bbc a2ef b7ea47cd388e ]; + overlay = "recalboxrgbdual"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hd44780-lcd-overlay.dts linux/arch/arm/boot/dts/overlays/hd44780-lcd-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hd44780-lcd-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hd44780-lcd-overlay.dts 2023-12-13 11:50:48.598961271 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + lcd_screen: auxdisplay { + compatible = "hit,hd44780"; + + data-gpios = <&gpio 6 0>, + <&gpio 13 0>, + <&gpio 19 0>, + <&gpio 26 0>; + enable-gpios = <&gpio 21 0>; + rs-gpios = <&gpio 20 0>; + + display-height-chars = <2>; + display-width-chars = <16>; + }; + + }; + }; + + fragment@1 { + target = <&lcd_screen>; + __dormant__ { + backlight-gpios = <&gpio 12 0>; + }; + }; + + __overrides__ { + pin_d4 = <&lcd_screen>,"data-gpios:4"; + pin_d5 = <&lcd_screen>,"data-gpios:16"; + pin_d6 = <&lcd_screen>,"data-gpios:28"; + pin_d7 = <&lcd_screen>,"data-gpios:40"; + pin_en = <&lcd_screen>,"enable-gpios:4"; + pin_rs = <&lcd_screen>,"rs-gpios:4"; + pin_bl = <0>,"+1", <&lcd_screen>,"backlight-gpios:4"; + display_height = <&lcd_screen>,"display-height-chars:0"; + display_width = <&lcd_screen>,"display-width-chars:0"; + }; + +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hdmi-backlight-hwhack-gpio-overlay.dts linux/arch/arm/boot/dts/overlays/hdmi-backlight-hwhack-gpio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hdmi-backlight-hwhack-gpio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hdmi-backlight-hwhack-gpio-overlay.dts 2023-12-13 11:50:48.598961271 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Devicetree overlay for GPIO based backlight on/off capability. + * + * Use this if you have one of those HDMI displays whose backlight cannot be + * controlled via DPMS over HDMI and plan to do a little soldering to use an + * RPi gpio pin for on/off switching. + * + * See: https://www.waveshare.com/wiki/7inch_HDMI_LCD_(C)#Backlight_Control + * + */ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@1 { + target = <&gpio>; + __overlay__ { + hdmi_backlight_hwhack_gpio_pins: hdmi_backlight_hwhack_gpio_pins { + brcm,pins = <17>; + brcm,function = <1>; /* out */ + }; + }; + }; + + fragment@2 { + target-path = "/"; + __overlay__ { + hdmi_backlight_hwhack_gpio: hdmi_backlight_hwhack_gpio { + compatible = "gpio-backlight"; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_backlight_hwhack_gpio_pins>; + + gpios = <&gpio 17 0>; + default-on; + }; + }; + }; + + __overrides__ { + gpio_pin = <&hdmi_backlight_hwhack_gpio>,"gpios:4", + <&hdmi_backlight_hwhack_gpio_pins>,"brcm,pins:0"; + active_low = <&hdmi_backlight_hwhack_gpio>,"gpios:8"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-amp100-overlay.dts linux/arch/arm/boot/dts/overlays/hifiberry-amp100-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-amp100-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hifiberry-amp100-overlay.dts 2023-12-13 11:50:48.598961271 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for HiFiBerry AMP100 +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + dacpro_osc: dacpro_osc { + compatible = "hifiberry,dacpro-clk"; + #clock-cells = <0>; + }; + }; + }; + + frag1: fragment@1 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pcm5122@4d { + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + reg = <0x4d>; + clocks = <&dacpro_osc>; + AVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + CPVDD-supply = <&vdd_3v3_reg>; + status = "okay"; + }; + }; + }; + + fragment@3 { + target = <&sound>; + hifiberry_dacplus: __overlay__ { + compatible = "hifiberry,hifiberry-dacplus"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + mute-gpio = <&gpio 4 0>; + reset-gpio = <&gpio 17 0x11>; + }; + }; + + __overrides__ { + 24db_digital_gain = + <&hifiberry_dacplus>,"hifiberry,24db_digital_gain?"; + slave = <&hifiberry_dacplus>,"hifiberry-dacplus,slave?", + <&frag1>,"target:0=",<&i2s_clk_producer>, + <&hifiberry_dacplus>,"i2s-controller:0=",<&i2s_clk_producer>; + + leds_off = <&hifiberry_dacplus>,"hifiberry-dacplus,leds_off?"; + mute_ext_ctl = <&hifiberry_dacplus>,"hifiberry-dacplus,mute_ext_ctl:0"; + auto_mute = <&hifiberry_dacplus>,"hifiberry-dacplus,auto_mute?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-amp3-overlay.dts linux/arch/arm/boot/dts/overlays/hifiberry-amp3-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-amp3-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hifiberry-amp3-overlay.dts 2023-12-13 11:50:48.599961273 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for HiFiBerry's Amp3 +/dts-v1/; +/plugin/; +#include <dt-bindings/pinctrl/bcm2835.h> +#include <dt-bindings/gpio/gpio.h> + + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + hifiberry_amp3_pins: hifiberry_amp3_pins { + brcm,pins = <23 17>; + brcm,function = <0 1>; + brcm,pull = <2 1>; + }; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hifiberry_amp2: ma120x0p@20 { + #sound-dai-cells = <0>; + compatible = "ma,ma120x0p"; + reg = <0x20>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hifiberry_amp3_pins>; + error_gp-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + }; + }; + }; + + fragment@3 { + target = <&sound>; + __overlay__ { + compatible = "hifiberry,hifiberry-amp3"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts linux/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts 2023-12-13 11:50:48.598961271 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for HiFiBerry Amp/Amp+ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + tas5713@1b { + #sound-dai-cells = <0>; + compatible = "ti,tas5713"; + reg = <0x1b>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "hifiberry,hifiberry-amp"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts linux/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts 2023-12-13 11:50:48.599961273 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for HiFiBerry DAC +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + pcm5102a-codec { + #sound-dai-cells = <0>; + compatible = "ti,pcm5102a"; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "hifiberry,hifiberry-dac"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts linux/arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts 2023-12-13 11:50:48.599961273 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for HiFiBerry DAC+ADC +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + dacpro_osc: dacpro_osc { + compatible = "hifiberry,dacpro-clk"; + #clock-cells = <0>; + }; + }; + }; + + frag1: fragment@1 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pcm_codec: pcm5122@4d { + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + reg = <0x4d>; + clocks = <&dacpro_osc>; + AVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + CPVDD-supply = <&vdd_3v3_reg>; + status = "okay"; + }; + }; + }; + + fragment@3 { + target-path = "/"; + __overlay__ { + dmic { + #sound-dai-cells = <0>; + compatible = "dmic-codec"; + num-channels = <2>; + status = "okay"; + }; + }; + }; + + fragment@4 { + target = <&sound>; + hifiberry_dacplusadc: __overlay__ { + compatible = "hifiberry,hifiberry-dacplusadc"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; + + __overrides__ { + 24db_digital_gain = + <&hifiberry_dacplusadc>,"hifiberry,24db_digital_gain?"; + slave = <&hifiberry_dacplusadc>,"hifiberry-dacplusadc,slave?", + <&frag1>,"target:0=",<&i2s_clk_producer>, + <&hifiberry_dacplusadc>,"i2s-controller:0=",<&i2s_clk_producer>; + leds_off = <&hifiberry_dacplusadc>,"hifiberry-dacplusadc,leds_off?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-dacplusadcpro-overlay.dts linux/arch/arm/boot/dts/overlays/hifiberry-dacplusadcpro-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-dacplusadcpro-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hifiberry-dacplusadcpro-overlay.dts 2023-12-13 11:50:48.599961273 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for HiFiBerry DAC+ADC PRO +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + dacpro_osc: dacpro_osc { + compatible = "hifiberry,dacpro-clk"; + #clock-cells = <0>; + }; + }; + }; + + frag1: fragment@1 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hb_dac: pcm5122@4d { + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + reg = <0x4d>; + clocks = <&dacpro_osc>; + status = "okay"; + }; + hb_adc: pcm186x@4a { + #sound-dai-cells = <0>; + compatible = "ti,pcm1863"; + reg = <0x4a>; + clocks = <&dacpro_osc>; + status = "okay"; + }; + hpamp: hpamp@60 { + compatible = "ti,tpa6130a2"; + reg = <0x60>; + status = "disabled"; + }; + }; + }; + + fragment@3 { + target = <&sound>; + hifiberry_dacplusadcpro: __overlay__ { + compatible = "hifiberry,hifiberry-dacplusadcpro"; + audio-codec = <&hb_dac &hb_adc>; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; + + __overrides__ { + 24db_digital_gain = + <&hifiberry_dacplusadcpro>,"hifiberry-dacplusadcpro,24db_digital_gain?"; + slave = <&hifiberry_dacplusadcpro>,"hifiberry-dacplusadcpro,slave?", + <&frag1>,"target:0=",<&i2s_clk_producer>, + <&hifiberry_dacplusadcpro>,"i2s-controller:0=",<&i2s_clk_producer>; + leds_off = <&hifiberry_dacplusadcpro>,"hifiberry-dacplusadcpro,leds_off?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-dacplusdsp-overlay.dts linux/arch/arm/boot/dts/overlays/hifiberry-dacplusdsp-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-dacplusdsp-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hifiberry-dacplusdsp-overlay.dts 2023-12-13 11:50:48.599961273 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for hifiberry DAC+DSP soundcard overlay +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + dacplusdsp-codec { + #sound-dai-cells = <0>; + compatible = "hifiberry,dacplusdsp"; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "hifiberrydacplusdsp,hifiberrydacplusdsp-soundcard"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-dacplushd-overlay.dts linux/arch/arm/boot/dts/overlays/hifiberry-dacplushd-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-dacplushd-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hifiberry-dacplushd-overlay.dts 2023-12-13 11:50:48.599961273 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for HiFiBerry DAC+ HD +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pcm1792a@4c { + compatible = "ti,pcm1792a"; + #sound-dai-cells = <0>; + #clock-cells = <0>; + reg = <0x4c>; + status = "okay"; + }; + pll: pll@62 { + compatible = "hifiberry,dachd-clk"; + #clock-cells = <0>; + reg = <0x62>; + status = "okay"; + common_pll_regs = [ + 02 53 03 00 07 20 0F 00 + 10 0D 11 1D 12 0D 13 8C + 14 8C 15 8C 16 8C 17 8C + 18 2A 1C 00 1D 0F 1F 00 + 2A 00 2C 00 2F 00 30 00 + 31 00 32 00 34 00 37 00 + 38 00 39 00 3A 00 3B 01 + 3E 00 3F 00 40 00 41 00 + 5A 00 5B 00 95 00 96 00 + 97 00 98 00 99 00 9A 00 + 9B 00 A2 00 A3 00 A4 00 + B7 92 ]; + 192k_pll_regs = [ + 1A 0C 1B 35 1E F0 20 09 + 21 50 2B 02 2D 10 2E 40 + 33 01 35 22 36 80 3C 22 + 3D 46 ]; + 96k_pll_regs = [ + 1A 0C 1B 35 1E F0 20 09 + 21 50 2B 02 2D 10 2E 40 + 33 01 35 47 36 00 3C 32 + 3D 46 ]; + 48k_pll_regs = [ + 1A 0C 1B 35 1E F0 20 09 + 21 50 2B 02 2D 10 2E 40 + 33 01 35 90 36 00 3C 42 + 3D 46 ]; + 176k4_pll_regs = [ + 1A 3D 1B 09 1E F3 20 13 + 21 75 2B 04 2D 11 2E E0 + 33 02 35 25 36 C0 3C 22 + 3D 7A ]; + 88k2_pll_regs = [ + 1A 3D 1B 09 1E F3 20 13 + 21 75 2B 04 2D 11 2E E0 + 33 01 35 4D 36 80 3C 32 + 3D 7A ]; + 44k1_pll_regs = [ + 1A 3D 1B 09 1E F3 20 13 + 21 75 2B 04 2D 11 2E E0 + 33 01 35 9D 36 00 3C 42 + 3D 7A ]; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "hifiberry,hifiberry-dacplushd"; + i2s-controller = <&i2s_clk_consumer>; + clocks = <&pll 0>; + reset-gpio = <&gpio 16 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + }; + +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts linux/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts 2023-12-13 11:50:48.599961273 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for HiFiBerry DAC+ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + dacpro_osc: dacpro_osc { + compatible = "hifiberry,dacpro-clk"; + #clock-cells = <0>; + }; + }; + }; + + frag1: fragment@1 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pcm5122@4d { + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + reg = <0x4d>; + clocks = <&dacpro_osc>; + AVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + CPVDD-supply = <&vdd_3v3_reg>; + status = "okay"; + }; + hpamp: hpamp@60 { + compatible = "ti,tpa6130a2"; + reg = <0x60>; + status = "disabled"; + }; + }; + }; + + fragment@3 { + target = <&sound>; + hifiberry_dacplus: __overlay__ { + compatible = "hifiberry,hifiberry-dacplus"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; + + __overrides__ { + 24db_digital_gain = + <&hifiberry_dacplus>,"hifiberry,24db_digital_gain?"; + slave = <&hifiberry_dacplus>,"hifiberry-dacplus,slave?", + <&frag1>,"target:0=",<&i2s_clk_producer>, + <&hifiberry_dacplus>,"i2s-controller:0=",<&i2s_clk_producer>; + + leds_off = <&hifiberry_dacplus>,"hifiberry-dacplus,leds_off?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts linux/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts 2023-12-13 11:50:48.600961275 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for HiFiBerry Digi +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wm8804@3b { + #sound-dai-cells = <0>; + compatible = "wlf,wm8804"; + reg = <0x3b>; + PVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "hifiberry,hifiberry-digi"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-digi-pro-overlay.dts linux/arch/arm/boot/dts/overlays/hifiberry-digi-pro-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hifiberry-digi-pro-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hifiberry-digi-pro-overlay.dts 2023-12-13 11:50:48.600961275 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for HiFiBerry Digi Pro +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wm8804@3b { + #sound-dai-cells = <0>; + compatible = "wlf,wm8804"; + reg = <0x3b>; + PVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "hifiberry,hifiberry-digi"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + clock44-gpio = <&gpio 5 0>; + clock48-gpio = <&gpio 6 0>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/highperi-overlay.dts linux/arch/arm/boot/dts/overlays/highperi-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/highperi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/highperi-overlay.dts 2023-12-13 11:50:48.600961275 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * highperi.dts + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&soc>; + #address-cells = <2>; + #size-cells = <1>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x7c000000 0x4 0x7c000000 0x04000000>, + <0x40000000 0x4 0xc0000000 0x00800000>; + }; + }; + + fragment@1 { + target = <&scb>; + #address-cells = <2>; + #size-cells = <1>; + + __overlay__ { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x7c000000 0x4 0x7c000000 0x0 0x04000000>, + <0x0 0x40000000 0x4 0xc0000000 0x0 0x00800000>, + <0x6 0x00000000 0x6 0x00000000 0x0 0x40000000>; + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x2 0x00000000>; + }; + }; + + fragment@2 { + target = <&v3dbus>; + #address-cells = <2>; + #size-cells = <1>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <2>; + ranges = <0x7c500000 0x4 0x7c500000 0x0 0x03300000>, + <0x40000000 0x4 0xc0000000 0x0 0x00800000>; + }; + }; + + fragment@3 { + target = <&emmc2bus>; + #address-cells = <2>; + #size-cells = <1>; + + __overlay__ { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x0 0x7e000000 0x4 0x7e000000 0x01800000>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hy28a-overlay.dts linux/arch/arm/boot/dts/overlays/hy28a-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hy28a-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hy28a-overlay.dts 2023-12-13 11:50:48.600961275 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for HY28A display + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + hy28a_pins: hy28a_pins { + brcm,pins = <17 25 18>; + brcm,function = <0 1 1>; /* in out out */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + hy28a: hy28a@0{ + compatible = "ilitek,ili9320"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hy28a_pins>; + + spi-max-frequency = <32000000>; + spi-cpol; + spi-cpha; + rotate = <270>; + bgr; + fps = <50>; + buswidth = <8>; + startbyte = <0x70>; + reset-gpios = <&gpio 25 1>; + led-gpios = <&gpio 18 1>; + debug = <0>; + }; + + hy28a_ts: hy28a-ts@1 { + compatible = "ti,ads7846"; + reg = <1>; + + spi-max-frequency = <2000000>; + interrupts = <17 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; + pendown-gpio = <&gpio 17 0>; + ti,x-plate-ohms = /bits/ 16 <100>; + ti,pressure-max = /bits/ 16 <255>; + }; + }; + }; + __overrides__ { + speed = <&hy28a>,"spi-max-frequency:0"; + rotate = <&hy28a>,"rotate:0"; + fps = <&hy28a>,"fps:0"; + debug = <&hy28a>,"debug:0"; + xohms = <&hy28a_ts>,"ti,x-plate-ohms;0"; + resetgpio = <&hy28a>,"reset-gpios:4", + <&hy28a_pins>, "brcm,pins:4"; + ledgpio = <&hy28a>,"led-gpios:4", + <&hy28a_pins>, "brcm,pins:8"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hy28b-2017-overlay.dts linux/arch/arm/boot/dts/overlays/hy28b-2017-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hy28b-2017-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hy28b-2017-overlay.dts 2023-12-13 11:50:48.600961275 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for HY28b display shield by Texy. + * Modified for 2017 version with ILI9325 D chip + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + hy28b_pins: hy28b_pins { + brcm,pins = <17 25 18>; + brcm,function = <0 1 1>; /* in out out */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + hy28b: hy28b@0{ + compatible = "ilitek,ili9325"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hy28b_pins>; + + spi-max-frequency = <48000000>; + spi-cpol; + spi-cpha; + rotate = <270>; + bgr; + fps = <50>; + buswidth = <8>; + startbyte = <0x70>; + reset-gpios = <&gpio 25 1>; + led-gpios = <&gpio 18 1>; + + init = <0x10000e5 0x78F0 + 0x1000001 0x0100 + 0x1000002 0x0700 + 0x1000003 0x1030 + 0x1000004 0x0000 + 0x1000008 0x0207 + 0x1000009 0x0000 + 0x100000a 0x0000 + 0x100000c 0x0000 + 0x100000d 0x0000 + 0x100000f 0x0000 + 0x1000010 0x0000 + 0x1000011 0x0007 + 0x1000012 0x0000 + 0x1000013 0x0000 + 0x1000007 0x0001 + 0x2000032 + 0x2000032 + 0x2000032 + 0x2000032 + 0x1000010 0x1090 + 0x1000011 0x0227 + 0x2000032 + 0x1000012 0x001f + 0x2000032 + 0x1000013 0x1500 + 0x1000029 0x0027 + 0x100002b 0x000d + 0x2000032 + 0x1000020 0x0000 + 0x1000021 0x0000 + 0x2000032 + 0x1000030 0x0000 + 0x1000031 0x0707 + 0x1000032 0x0307 + 0x1000035 0x0200 + 0x1000036 0x0008 + 0x1000037 0x0004 + 0x1000038 0x0000 + 0x1000039 0x0707 + 0x100003c 0x0002 + 0x100003d 0x1d04 + 0x1000050 0x0000 + 0x1000051 0x00ef + 0x1000052 0x0000 + 0x1000053 0x013f + 0x1000060 0xa700 + 0x1000061 0x0001 + 0x100006a 0x0000 + 0x1000080 0x0000 + 0x1000081 0x0000 + 0x1000082 0x0000 + 0x1000083 0x0000 + 0x1000084 0x0000 + 0x1000085 0x0000 + 0x1000090 0x0010 + 0x1000092 0x0600 + 0x1000007 0x0133>; + debug = <0>; + }; + + hy28b_ts: hy28b-ts@1 { + compatible = "ti,ads7846"; + reg = <1>; + + spi-max-frequency = <2000000>; + interrupts = <17 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; + pendown-gpio = <&gpio 17 0>; + ti,x-plate-ohms = /bits/ 16 <100>; + ti,pressure-max = /bits/ 16 <255>; + }; + }; + }; + __overrides__ { + speed = <&hy28b>,"spi-max-frequency:0"; + rotate = <&hy28b>,"rotate:0"; + fps = <&hy28b>,"fps:0"; + debug = <&hy28b>,"debug:0"; + xohms = <&hy28b_ts>,"ti,x-plate-ohms;0"; + resetgpio = <&hy28b>,"reset-gpios:4", + <&hy28b_pins>, "brcm,pins:4"; + ledgpio = <&hy28b>,"led-gpios:4", + <&hy28b_pins>, "brcm,pins:8"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/hy28b-overlay.dts linux/arch/arm/boot/dts/overlays/hy28b-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/hy28b-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/hy28b-overlay.dts 2023-12-13 11:50:48.600961275 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for HY28b display shield by Texy + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + hy28b_pins: hy28b_pins { + brcm,pins = <17 25 18>; + brcm,function = <0 1 1>; /* in out out */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + hy28b: hy28b@0{ + compatible = "ilitek,ili9325"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hy28b_pins>; + + spi-max-frequency = <48000000>; + spi-cpol; + spi-cpha; + rotate = <270>; + bgr; + fps = <50>; + buswidth = <8>; + startbyte = <0x70>; + reset-gpios = <&gpio 25 1>; + led-gpios = <&gpio 18 1>; + + gamma = "04 1F 4 7 7 0 7 7 6 0\n0F 00 1 7 4 0 0 0 6 7"; + + init = <0x10000e7 0x0010 + 0x1000000 0x0001 + 0x1000001 0x0100 + 0x1000002 0x0700 + 0x1000003 0x1030 + 0x1000004 0x0000 + 0x1000008 0x0207 + 0x1000009 0x0000 + 0x100000a 0x0000 + 0x100000c 0x0001 + 0x100000d 0x0000 + 0x100000f 0x0000 + 0x1000010 0x0000 + 0x1000011 0x0007 + 0x1000012 0x0000 + 0x1000013 0x0000 + 0x2000032 + 0x1000010 0x1590 + 0x1000011 0x0227 + 0x2000032 + 0x1000012 0x009c + 0x2000032 + 0x1000013 0x1900 + 0x1000029 0x0023 + 0x100002b 0x000e + 0x2000032 + 0x1000020 0x0000 + 0x1000021 0x0000 + 0x2000032 + 0x1000050 0x0000 + 0x1000051 0x00ef + 0x1000052 0x0000 + 0x1000053 0x013f + 0x1000060 0xa700 + 0x1000061 0x0001 + 0x100006a 0x0000 + 0x1000080 0x0000 + 0x1000081 0x0000 + 0x1000082 0x0000 + 0x1000083 0x0000 + 0x1000084 0x0000 + 0x1000085 0x0000 + 0x1000090 0x0010 + 0x1000092 0x0000 + 0x1000093 0x0003 + 0x1000095 0x0110 + 0x1000097 0x0000 + 0x1000098 0x0000 + 0x1000007 0x0133 + 0x1000020 0x0000 + 0x1000021 0x0000 + 0x2000064>; + debug = <0>; + }; + + hy28b_ts: hy28b-ts@1 { + compatible = "ti,ads7846"; + reg = <1>; + + spi-max-frequency = <2000000>; + interrupts = <17 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; + pendown-gpio = <&gpio 17 0>; + ti,x-plate-ohms = /bits/ 16 <100>; + ti,pressure-max = /bits/ 16 <255>; + }; + }; + }; + __overrides__ { + speed = <&hy28b>,"spi-max-frequency:0"; + rotate = <&hy28b>,"rotate:0"; + fps = <&hy28b>,"fps:0"; + debug = <&hy28b>,"debug:0"; + xohms = <&hy28b_ts>,"ti,x-plate-ohms;0"; + resetgpio = <&hy28b>,"reset-gpios:4", + <&hy28b_pins>, "brcm,pins:4"; + ledgpio = <&hy28b>,"led-gpios:4", + <&hy28b_pins>, "brcm,pins:8"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c0-overlay.dts linux/arch/arm/boot/dts/overlays/i2c0-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c0-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c0-overlay.dts 2023-12-13 11:50:48.602961280 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + }; + }; + + fragment@1 { + target = <&i2c0_pins>; + pins1: __overlay__ { + brcm,pins = <0 1>; + brcm,function = <4>; /* alt0 */ + }; + }; + + fragment@2 { + target = <&i2c0_pins>; + pins2: __dormant__ { + brcm,pins = <28 29>; + brcm,function = <4>; /* alt0 */ + }; + }; + + fragment@3 { + target = <&i2c0_pins>; + pins3: __dormant__ { + brcm,pins = <44 45>; + brcm,function = <5>; /* alt1 */ + }; + }; + + fragment@4 { + target = <&i2c0_pins>; + pins4: __dormant__ { + brcm,pins = <46 47>; + brcm,function = <4>; /* alt0 */ + }; + }; + + fragment@5 { + target = <&i2c0>; + __dormant__ { + compatible = "brcm,bcm2708-i2c"; + }; + }; + + fragment@6 { + target = <&i2c0mux>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@7 { + target-path = "/aliases"; + __overlay__ { + i2c0 = "/soc/i2c@7e205000"; + }; + }; + + fragment@8 { + target-path = "/__symbols__"; + __overlay__ { + i2c0 = "/soc/i2c@7e205000"; + }; + }; + + __overrides__ { + pins_0_1 = <0>,"+1-2-3-4"; + pins_28_29 = <0>,"-1+2-3-4"; + pins_44_45 = <0>,"-1-2+3-4"; + pins_46_47 = <0>,"-1-2-3+4"; + combine = <0>, "!5"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c0-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/i2c0-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c0-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c0-pi5-overlay.dts 2023-12-13 11:50:48.602961280 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&i2c0>; + frag0: __overlay__ { + status = "okay"; + clock-frequency = <100000>; + }; + }; + + fragment@1 { + target = <&frag0>; + __overlay__ { + pinctrl-0 = <&rp1_i2c0_0_1>; + }; + }; + + fragment@2 { + target = <&frag0>; + __dormant__ { + pinctrl-0 = <&rp1_i2c0_8_9>; + }; + }; + + __overrides__ { + pins_0_1 = <0>,"+1-2"; + pins_8_9 = <0>,"-1+2"; + baudrate = <&frag0>, "clock-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c1-overlay.dts linux/arch/arm/boot/dts/overlays/i2c1-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c1-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c1-overlay.dts 2023-12-13 11:50:48.602961280 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c1>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + }; + }; + + fragment@1 { + target = <&i2c1_pins>; + pins1: __overlay__ { + brcm,pins = <2 3>; + brcm,function = <4>; /* alt 0 */ + }; + }; + + fragment@2 { + target = <&i2c1_pins>; + pins2: __dormant__ { + brcm,pins = <44 45>; + brcm,function = <6>; /* alt 2 */ + }; + }; + + fragment@3 { + target = <&i2c1>; + __dormant__ { + compatible = "brcm,bcm2708-i2c"; + }; + }; + + __overrides__ { + pins_2_3 = <0>,"=1!2"; + pins_44_45 = <0>,"!1=2"; + combine = <0>, "!3"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c1-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/i2c1-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c1-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c1-pi5-overlay.dts 2023-12-13 11:50:48.603961282 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&i2c1>; + frag0: __overlay__ { + status = "okay"; + clock-frequency = <100000>; + }; + }; + + fragment@1 { + target = <&frag0>; + __overlay__ { + pinctrl-0 = <&rp1_i2c1_2_3>; + }; + }; + + fragment@2 { + target = <&frag0>; + __dormant__ { + pinctrl-0 = <&rp1_i2c1_10_11>; + }; + }; + + __overrides__ { + pins_2_3 = <0>,"+1-2"; + pins_10_11 = <0>,"-1+2"; + baudrate = <&frag0>, "clock-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c2-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/i2c2-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c2-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c2-pi5-overlay.dts 2023-12-13 11:50:48.603961282 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&i2c2>; + frag0: __overlay__ { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&rp1_i2c2_4_5>; + }; + }; + + __overrides__ { + pins_4_5 = <&frag0>,"pinctrl-0:0=", <&rp1_i2c2_4_5>; + pins_12_13 = <&frag0>,"pinctrl-0:0=", <&rp1_i2c2_12_13>; + baudrate = <&frag0>, "clock-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c3-overlay.dts linux/arch/arm/boot/dts/overlays/i2c3-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c3-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c3-overlay.dts 2023-12-13 11:50:48.603961282 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&i2c3>; + frag0: __overlay__ { + status = "okay"; + clock-frequency = <100000>; + }; + }; + + fragment@1 { + target = <&i2c3_pins>; + __dormant__ { + brcm,pins = <2 3>; + }; + }; + + fragment@2 { + target = <&i2c3_pins>; + __overlay__ { + brcm,pins = <4 5>; + }; + }; + + __overrides__ { + pins_2_3 = <0>,"=1!2"; + pins_4_5 = <0>,"!1=2"; + baudrate = <&frag0>, "clock-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c3-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/i2c3-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c3-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c3-pi5-overlay.dts 2023-12-13 11:50:48.603961282 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&i2c3>; + frag0: __overlay__ { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&rp1_i2c3_6_7>; + }; + }; + + __overrides__ { + pins_6_7 = <&frag0>,"pinctrl-0:0=", <&rp1_i2c3_6_7>; + pins_14_15 = <&frag0>,"pinctrl-0:0=", <&rp1_i2c3_14_15>; + pins_22_23 = <&frag0>,"pinctrl-0:0=", <&rp1_i2c3_22_23>; + baudrate = <&frag0>, "clock-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c4-overlay.dts linux/arch/arm/boot/dts/overlays/i2c4-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c4-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c4-overlay.dts 2023-12-13 11:50:48.603961282 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&i2c4>; + frag0: __overlay__ { + status = "okay"; + clock-frequency = <100000>; + }; + }; + + fragment@1 { + target = <&i2c4_pins>; + __dormant__ { + brcm,pins = <6 7>; + }; + }; + + fragment@2 { + target = <&i2c4_pins>; + __overlay__ { + brcm,pins = <8 9>; + }; + }; + + __overrides__ { + pins_6_7 = <0>,"=1!2"; + pins_8_9 = <0>,"!1=2"; + baudrate = <&frag0>, "clock-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c5-overlay.dts linux/arch/arm/boot/dts/overlays/i2c5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c5-overlay.dts 2023-12-13 11:50:48.603961282 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&i2c5>; + frag0: __overlay__ { + status = "okay"; + clock-frequency = <100000>; + }; + }; + + fragment@1 { + target = <&i2c5_pins>; + __dormant__ { + brcm,pins = <10 11>; + }; + }; + + fragment@2 { + target = <&i2c5_pins>; + __overlay__ { + brcm,pins = <12 13>; + }; + }; + + __overrides__ { + pins_10_11 = <0>,"=1!2"; + pins_12_13 = <0>,"!1=2"; + baudrate = <&frag0>, "clock-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c6-overlay.dts linux/arch/arm/boot/dts/overlays/i2c6-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c6-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c6-overlay.dts 2023-12-13 11:50:48.603961282 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&i2c6>; + frag0: __overlay__ { + status = "okay"; + clock-frequency = <100000>; + }; + }; + + fragment@1 { + target = <&i2c6_pins>; + __dormant__ { + brcm,pins = <0 1>; + }; + }; + + fragment@2 { + target = <&i2c6_pins>; + __overlay__ { + brcm,pins = <22 23>; + }; + }; + + __overrides__ { + pins_0_1 = <0>,"=1!2"; + pins_22_23 = <0>,"!1=2"; + baudrate = <&frag0>, "clock-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c-bcm2708-overlay.dts linux/arch/arm/boot/dts/overlays/i2c-bcm2708-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c-bcm2708-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c-bcm2708-overlay.dts 2023-12-13 11:50:48.601961278 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c_arm>; + __overlay__ { + compatible = "brcm,bcm2708-i2c"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c-fan-overlay.dts linux/arch/arm/boot/dts/overlays/i2c-fan-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c-fan-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c-fan-overlay.dts 2023-12-13 11:50:48.601961278 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for I2C based sensors using the Industrial IO or HWMON interface. +/dts-v1/; +/plugin/; + +#include <dt-bindings/thermal/thermal.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + emc2301: emc2301@2f { + compatible = "microchip,emc2301"; + reg = <0x2f>; + status = "okay"; + #cooling-cells = <0x02>; + }; + }; + }; + + frag100: fragment@100 { + target = <&i2c_arm>; + i2cbus: __overlay__ { + status = "okay"; + }; + }; + + fragment@101 { + target = <&i2c0if>; + __dormant__ { + status = "okay"; + }; + }; + + fragment@102 { + target = <&i2c0mux>; + __dormant__ { + status = "okay"; + }; + }; + + fragment@103 { + target = <&cpu_thermal>; + __overlay__ { + polling-delay = <2000>; /* milliseconds */ + }; + }; + + fragment@104 { + target = <&thermal_trips>; + __overlay__ { + fanmid0: fanmid0 { + temperature = <50000>; + hysteresis = <2000>; + type = "active"; + }; + fanmax0: fanmax0 { + temperature = <75000>; + hysteresis = <2000>; + type = "active"; + }; + }; + }; + + fragment@105 { + target = <&cooling_maps>; + __overlay__ { + map0: map0 { + trip = <&fanmid0>; + cooling-device = <&emc2301 2 6>; + }; + map1: map1 { + trip = <&fanmax0>; + cooling-device = <&emc2301 7 THERMAL_NO_LIMIT>; + }; + }; + }; + + __overrides__ { + i2c0 = <&frag100>,"target:0=",<&i2c0>; + i2c_csi_dsi = <&frag100>,"target:0=",<&i2c_csi_dsi>, + <0>,"+101+102"; + i2c3 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c3"; + i2c4 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c4"; + i2c5 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c5"; + i2c6 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c6"; + addr = <&emc2301>,"reg:0"; + minpwm = <&emc2301>,"emc2305,pwm-min.0"; + maxpwm = <&emc2301>,"emc2305,pwm-max.0"; + midtemp = <&fanmid0>,"temperature:0"; + midtemp_hyst = <&fanmid0>,"hysteresis:0"; + maxtemp = <&fanmax0>,"temperature:0"; + maxtemp_hyst = <&fanmax0>,"hysteresis:0"; + + emc2301 = <0>,"+0", + <&map0>,"cooling-device:0=",<&emc2301>, + <&map1>,"cooling-device:0=",<&emc2301>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts linux/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts 2023-12-13 11:50:48.601961278 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for i2c_gpio bitbanging host bus. +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + + __overlay__ { + i2c_gpio: i2c@0 { + reg = <0xffffffff>; + compatible = "i2c-gpio"; + gpios = <&gpio 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */ + &gpio 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + fragment@1 { + target-path = "/aliases"; + __overlay__ { + i2c_gpio = "/i2c@0"; + }; + }; + + fragment@2 { + target-path = "/__symbols__"; + __overlay__ { + i2c_gpio = "/i2c@0"; + }; + }; + + __overrides__ { + i2c_gpio_sda = <&i2c_gpio>,"gpios:4"; + i2c_gpio_scl = <&i2c_gpio>,"gpios:16"; + i2c_gpio_delay_us = <&i2c_gpio>,"i2c-gpio,delay-us:0"; + bus = <&i2c_gpio>, "reg:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c-mux-overlay.dts linux/arch/arm/boot/dts/overlays/i2c-mux-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c-mux-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c-mux-overlay.dts 2023-12-13 11:50:48.601961278 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Umbrella I2C Mux overlay + +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca9542: mux@70 { + compatible = "nxp,pca9542"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + }; + + fragment@1 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca9545: mux@70 { + compatible = "nxp,pca9545"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + }; + + fragment@2 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca9548: mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + }; + + frag100: fragment@100 { + target = <&i2c_arm>; + i2cbus: __overlay__ { + status = "okay"; + }; + }; + + fragment@101 { + target = <&i2c0if>; + __dormant__ { + status = "okay"; + }; + }; + + fragment@102 { + target = <&i2c0mux>; + __dormant__ { + status = "okay"; + }; + }; + + __overrides__ { + pca9542 = <0>, "+0"; + pca9545 = <0>, "+1"; + pca9548 = <0>, "+2"; + + addr = <&pca9542>,"reg:0", + <&pca9545>,"reg:0", + <&pca9548>,"reg:0"; + + i2c0 = <&frag100>, "target:0=",<&i2c0>, + <0>,"+101+102"; + i2c_csi_dsi = <&frag100>, "target:0=",<&i2c_csi_dsi>, + <0>,"+101+102"; + i2c3 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c3"; + i2c4 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c4"; + i2c5 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c5"; + i2c6 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c6"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts linux/arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts 2023-12-13 11:50:48.601961278 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for NXP PCA9685A I2C PWM controller on ARM I2C bus. +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2cbus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca: pca@40 { + compatible = "nxp,pca9685-pwm"; + #pwm-cells = <2>; + reg = <0x40>; + status = "okay"; + }; + }; + }; + + + frag100: fragment@100 { + target = <&i2c_arm>; + i2cbus: __overlay__ { + status = "okay"; + }; + }; + + fragment@101 { + target = <&i2c0if>; + __dormant__ { + status = "okay"; + }; + }; + + fragment@102 { + target = <&i2c0mux>; + __dormant__ { + status = "okay"; + }; + }; + + __overrides__ { + addr = <&pca>,"reg:0"; + i2c0 = <&frag100>, "target:0=",<&i2c0>, + <0>,"+101+102"; + i2c_csi_dsi = <&frag100>, "target:0=",<&i2c_csi_dsi>, + <0>,"+101+102"; + i2c3 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c3"; + i2c4 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c4"; + i2c5 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c5"; + i2c6 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c6"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c-rtc-common.dtsi linux/arch/arm/boot/dts/overlays/i2c-rtc-common.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c-rtc-common.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c-rtc-common.dtsi 2023-12-13 11:50:48.601961278 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for several I2C based Real Time Clocks + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + abx80x: abx80x@69 { + compatible = "abracon,abx80x"; + reg = <0x69>; + abracon,tc-diode = "standard"; + abracon,tc-resistor = <0>; + }; + }; + }; + + fragment@1 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + ds1307: ds1307@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; + }; + }; + + fragment@2 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + ds1339: ds1339@68 { + compatible = "dallas,ds1339"; + trickle-resistor-ohms = <0>; + reg = <0x68>; + }; + }; + }; + + fragment@3 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + ds3231: ds3231@68 { + compatible = "maxim,ds3231"; + reg = <0x68>; + }; + }; + }; + + fragment@4 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + mcp7940x: mcp7940x@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + }; + }; + }; + + fragment@5 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + mcp7941x: mcp7941x@6f { + compatible = "microchip,mcp7941x"; + reg = <0x6f>; + }; + }; + }; + + fragment@6 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + pcf2127@51 { + compatible = "nxp,pcf2127"; + reg = <0x51>; + }; + }; + }; + + fragment@7 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + pcf8523: pcf8523@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; + }; + }; + + fragment@8 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + pcf8563: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + }; + + fragment@9 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + m41t62: m41t62@68 { + compatible = "st,m41t62"; + reg = <0x68>; + }; + }; + }; + + fragment@10 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + rv3028: rv3028@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; + }; + }; + + fragment@11 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + pcf2129@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; + }; + }; + + fragment@12 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + pcf85363@51 { + compatible = "nxp,pcf85363"; + reg = <0x51>; + }; + }; + }; + + fragment@13 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + rv1805: rv1805@69 { + compatible = "microcrystal,rv1805"; + reg = <0x69>; + abracon,tc-diode = "standard"; + abracon,tc-resistor = <0>; + }; + }; + }; + + fragment@14 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sd3078: sd3078@32 { + compatible = "whwave,sd3078"; + reg = <0x32>; + }; + }; + }; + + fragment@15 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + pcf85063@51 { + compatible = "nxp,pcf85063"; + reg = <0x51>; + }; + }; + }; + + fragment@16 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + pcf85063a@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + }; + }; + }; + + fragment@17 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + ds1340: ds1340@68 { + compatible = "dallas,ds1340"; + trickle-resistor-ohms = <0>; + reg = <0x68>; + }; + }; + }; + + fragment@18 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + s35390a: s35390a@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + }; + }; + + fragment@19 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + bq32000: bq32000@68 { + compatible = "ti,bq32000"; + trickle-resistor-ohms = <0>; + reg = <0x68>; + }; + }; + }; + + fragment@20 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + rv8803: rv8803@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + }; + }; + + fragment@21 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + rv3032: rv3032@51 { + compatible = "microcrystal,rv3032"; + reg = <0x51>; + }; + }; + }; + + + __overrides__ { + abx80x = <0>,"+0"; + ds1307 = <0>,"+1"; + ds1339 = <0>,"+2"; + ds1340 = <0>,"+17"; + ds3231 = <0>,"+3"; + mcp7940x = <0>,"+4"; + mcp7941x = <0>,"+5"; + pcf2127 = <0>,"+6"; + pcf8523 = <0>,"+7"; + pcf8563 = <0>,"+8"; + m41t62 = <0>,"+9"; + rv3028 = <0>,"+10"; + pcf2129 = <0>,"+11"; + pcf85363 = <0>,"+12"; + rv1805 = <0>,"+13"; + sd3078 = <0>,"+14"; + pcf85063 = <0>,"+15"; + pcf85063a = <0>,"+16"; + s35390a = <0>,"+18"; + bq32000 = <0>,"+19"; + rv8803 = <0>,"+20"; + rv3032 = <0>,"+21"; + + addr = <&abx80x>, "reg:0", + <&ds1307>, "reg:0", + <&ds1339>, "reg:0", + <&ds3231>, "reg:0", + <&mcp7940x>, "reg:0", + <&mcp7941x>, "reg:0", + <&pcf8523>, "reg:0", + <&pcf8563>, "reg:0", + <&m41t62>, "reg:0", + <&rv1805>, "reg:0", + <&s35390a>, "reg:0"; + trickle-diode-disable = <&bq32000>,"trickle-diode-disable?"; + trickle-diode-type = <&abx80x>,"abracon,tc-diode", + <&rv1805>,"abracon,tc-diode"; + trickle-resistor-ohms = <&ds1339>,"trickle-resistor-ohms:0", + <&ds1340>,"trickle-resistor-ohms:0", + <&abx80x>,"abracon,tc-resistor:0", + <&rv3028>,"trickle-resistor-ohms:0", + <&rv3032>,"trickle-resistor-ohms:0", + <&rv1805>,"abracon,tc-resistor:0", + <&bq32000>,"abracon,tc-resistor:0"; + trickle-voltage-mv = <&rv3032>,"trickle-voltage-millivolts:0"; + backup-switchover-mode = <&rv3028>,"backup-switchover-mode:0"; + wakeup-source = <&ds1339>,"wakeup-source?", + <&ds3231>,"wakeup-source?", + <&mcp7940x>,"wakeup-source?", + <&mcp7941x>,"wakeup-source?", + <&m41t62>,"wakeup-source?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts linux/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts 2023-12-13 11:50:48.602961280 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for several I2C based Real Time Clocks +// Available through i2c-gpio +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +#include "i2c-rtc-common.dtsi" + +/ { + fragment@100 { + target-path = "/"; + __overlay__ { + i2cbus: i2c-gpio-rtc@0 { + compatible = "i2c-gpio"; + gpios = <&gpio 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */ + &gpio 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + __overrides__ { + i2c_gpio_sda = <&i2cbus>,"gpios:4"; + i2c_gpio_scl = <&i2cbus>,"gpios:16"; + i2c_gpio_delay_us = <&i2cbus>,"i2c-gpio,delay-us:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts linux/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts 2023-12-13 11:50:48.602961280 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for several I2C based Real Time Clocks +/dts-v1/; +/plugin/; + +#include "i2c-rtc-common.dtsi" + +/ { + frag100: fragment@100 { + target = <&i2c_arm>; + i2cbus: __overlay__ { + status = "okay"; + }; + }; + + fragment@101 { + target = <&i2c0if>; + __dormant__ { + status = "okay"; + }; + }; + + fragment@102 { + target = <&i2c0mux>; + __dormant__ { + status = "okay"; + }; + }; + + __overrides__ { + i2c0 = <&frag100>, "target:0=",<&i2c0>; + i2c_csi_dsi = <&frag100>, "target:0=",<&i2c_csi_dsi>, + <0>,"+101+102"; + i2c3 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c3"; + i2c4 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c4"; + i2c5 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c5"; + i2c6 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c6"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c-sensor-common.dtsi linux/arch/arm/boot/dts/overlays/i2c-sensor-common.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c-sensor-common.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c-sensor-common.dtsi 2023-12-13 11:50:48.602961280 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for I2C based sensors using the Industrial IO or HWMON interface. +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + bme280: bme280@76 { + compatible = "bosch,bme280"; + reg = <0x76>; + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + bmp085: bmp085@77 { + compatible = "bosch,bmp085"; + reg = <0x77>; + default-oversampling = <3>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + bmp180: bmp180@77 { + compatible = "bosch,bmp180"; + reg = <0x77>; + status = "okay"; + }; + }; + }; + + fragment@3 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + bmp280: bmp280@76 { + compatible = "bosch,bmp280"; + reg = <0x76>; + status = "okay"; + }; + }; + }; + + fragment@4 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + htu21: htu21@40 { + compatible = "meas,htu21"; + reg = <0x40>; + status = "okay"; + }; + }; + }; + + fragment@5 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + lm75: lm75@4f { + compatible = "national,lm75"; + reg = <0x4f>; + status = "okay"; + }; + }; + }; + + fragment@6 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + si7020: si7020@40 { + compatible = "silabs,si7020"; + reg = <0x40>; + status = "okay"; + }; + }; + }; + + fragment@7 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + tmp102: tmp102@48 { + compatible = "ti,tmp102"; + reg = <0x48>; + status = "okay"; + }; + }; + }; + + fragment@8 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hdc100x: hdc100x@40 { + compatible = "ti,hdc1000"; + reg = <0x40>; + status = "okay"; + }; + }; + }; + + fragment@9 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + tsl4531: tsl4531@29 { + compatible = "amstaos,tsl4531"; + reg = <0x29>; + status = "okay"; + }; + }; + }; + + fragment@10 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + veml6070: veml6070@38 { + compatible = "vishay,veml6070"; + reg = <0x38>; + status = "okay"; + }; + }; + }; + + fragment@11 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + sht3x: sht3x@44 { + compatible = "sensirion,sht3x"; + reg = <0x44>; + status = "okay"; + }; + }; + }; + + fragment@12 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ds1621: ds1621@48 { + compatible = "dallas,ds1621"; + reg = <0x48>; + status = "okay"; + }; + }; + }; + + fragment@13 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + max17040: max17040@36 { + compatible = "maxim,max17040"; + reg = <0x36>; + status = "okay"; + }; + }; + }; + + fragment@14 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + bme680: bme680@76 { + compatible = "bosch,bme680"; + reg = <0x76>; + status = "okay"; + }; + }; + }; + + fragment@15 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + sps30: sps30@69 { + compatible = "sensirion,sps30"; + reg = <0x69>; + status = "okay"; + }; + }; + }; + + fragment@16 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + sgp30: sgp30@58 { + compatible = "sensirion,sgp30"; + reg = <0x58>; + status = "okay"; + }; + }; + }; + + fragment@17 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ccs811: ccs811@5b { + compatible = "ams,ccs811"; + reg = <0x5b>; + status = "okay"; + }; + }; + }; + + fragment@18 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + bh1750: bh1750@23 { + compatible = "rohm,bh1750"; + reg = <0x23>; + status = "okay"; + }; + }; + }; + + fragment@19 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + max30102: max30102@57 { + compatible = "maxim,max30102"; + reg = <0x57>; + maxim,red-led-current-microamp = <7000>; + maxim,ir-led-current-microamp = <7000>; + interrupt-parent = <&gpio>; + interrupts = <4 2>; + }; + }; + }; + + fragment@20 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + aht10: aht10@38 { + compatible = "aosong,aht10"; + reg = <0x38>; + }; + }; + }; + + fragment@21 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + mcp980x: mcp980x@18 { + compatible = "maxim,mcp980x"; + reg = <0x18>; + }; + }; + }; + + fragment@22 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + jc42: jc42@18 { + compatible = "jedec,jc-42.4-temp"; + reg = <0x18>; + }; + }; + }; + + fragment@23 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ms5637: ms5637@76 { + compatible = "meas,ms5637"; + reg = <0x76>; + }; + }; + }; + + fragment@24 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ms5803: ms5803@76 { + compatible = "meas,ms5803"; + reg = <0x76>; + }; + }; + }; + + fragment@25 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ms5805: ms5805@76 { + compatible = "meas,ms5805"; + reg = <0x76>; + }; + }; + }; + + fragment@26 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ms5837: ms5837@76 { + compatible = "meas,ms5837"; + reg = <0x76>; + }; + }; + }; + + fragment@27 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ms8607: ms8607@76 { + compatible = "meas,ms8607-temppressure"; + reg = <0x76>; + }; + }; + }; + + fragment@28 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + clock-frequency = <400000>; + + mpu6050: mpu6050@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + interrupt-parent = <&gpio>; + interrupts = <4 2>; + }; + }; + }; + + fragment@29 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + clock-frequency = <400000>; + + mpu9250: mpu9250@68 { + compatible = "invensense,mpu9250"; + reg = <0x68>; + interrupt-parent = <&gpio>; + interrupts = <4 2>; + }; + }; + }; + + fragment@30 { + target = <&bno055>; + __dormant__ { + reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + }; + + fragment@31 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + bno055: bno055@29 { + compatible = "bosch,bno055"; + reg = <0x29>; + }; + }; + }; + + fragment@32 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + sht4x: sht4x@44 { + compatible = "sensirion,sht4x"; + reg = <0x44>; + status = "okay"; + }; + }; + }; + + fragment@33 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + bmp380: bmp380@76 { + compatible = "bosch,bmp380"; + reg = <0x76>; + status = "okay"; + }; + }; + }; + + fragment@34 { + target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + adt7410: adt7410@48 { + compatible = "adi,adt7410", "adi,adt7420"; + reg = <0x48>; + status = "okay"; + }; + }; + }; + + __overrides__ { + bme280 = <0>,"+0"; + bmp085 = <0>,"+1"; + bmp180 = <0>,"+2"; + bmp280 = <0>,"+3"; + bmp380 = <0>,"+33"; + htu21 = <0>,"+4"; + lm75 = <0>,"+5"; + lm75addr = <&lm75>,"reg:0"; + si7020 = <0>,"+6"; + tmp102 = <0>,"+7"; + hdc100x = <0>,"+8"; + tsl4531 = <0>,"+9"; + veml6070 = <0>,"+10"; + sht3x = <0>,"+11"; + ds1621 = <0>,"+12"; + max17040 = <0>,"+13"; + bme680 = <0>,"+14"; + sps30 = <0>,"+15"; + sgp30 = <0>,"+16"; + ccs811 = <0>, "+17"; + bh1750 = <0>, "+18"; + max30102 = <0>,"+19"; + aht10 = <0>,"+20"; + mcp980x = <0>,"+21"; + jc42 = <0>,"+22"; + ms5637 = <0>,"+23"; + ms5803 = <0>,"+24"; + ms5805 = <0>,"+25"; + ms5837 = <0>,"+26"; + ms8607 = <0>,"+27"; + mpu6050 = <0>,"+28"; + mpu9250 = <0>,"+29"; + bno055 = <0>,"+31"; + sht4x = <0>,"+32"; + adt7410 = <0>,"+34"; + + addr = <&bme280>,"reg:0", <&bmp280>,"reg:0", <&tmp102>,"reg:0", + <&lm75>,"reg:0", <&hdc100x>,"reg:0", <&sht3x>,"reg:0", + <&ds1621>,"reg:0", <&bme680>,"reg:0", <&ccs811>,"reg:0", + <&bh1750>,"reg:0", <&mcp980x>,"reg:0", <&jc42>,"reg:0", + <&ms5637>,"reg:0", <&ms5803>,"reg:0", <&ms5805>,"reg:0", + <&ms5837>,"reg:0", <&ms8607>,"reg:0", + <&mpu6050>,"reg:0", <&mpu9250>,"reg:0", + <&bno055>,"reg:0", <&sht4x>,"reg:0", + <&bmp380>,"reg:0", <&adt7410>,"reg:0"; + int_pin = <&max30102>, "interrupts:0", + <&mpu6050>, "interrupts:0", + <&mpu9250>, "interrupts:0"; + no_timeout = <&jc42>, "smbus-timeout-disable?"; + reset_pin = <&bno055>,"reset-gpios:4", <0>,"+30"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts linux/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts 2023-12-13 11:50:48.602961280 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for I2C based sensors using the Industrial IO or HWMON interface. +/dts-v1/; +/plugin/; + +#include "i2c-sensor-common.dtsi" + +/ { + frag100: fragment@100 { + target = <&i2c_arm>; + i2cbus: __overlay__ { + status = "okay"; + }; + }; + + fragment@101 { + target = <&i2c0if>; + __dormant__ { + status = "okay"; + }; + }; + + fragment@102 { + target = <&i2c0mux>; + __dormant__ { + status = "okay"; + }; + }; + + __overrides__ { + i2c0 = <&frag100>, "target:0=",<&i2c0>; + i2c_csi_dsi = <&frag100>, "target:0=",<&i2c_csi_dsi>, + <0>,"+101+102"; + i2c3 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c3"; + i2c4 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c4"; + i2c5 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c5"; + i2c6 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c6"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2s-dac-overlay.dts linux/arch/arm/boot/dts/overlays/i2s-dac-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2s-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2s-dac-overlay.dts 2023-12-13 11:50:48.603961282 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for RPi DAC +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + pcm1794a-codec { + #sound-dai-cells = <0>; + compatible = "ti,pcm1794a"; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "rpi,rpi-dac"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i2s-gpio28-31-overlay.dts linux/arch/arm/boot/dts/overlays/i2s-gpio28-31-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i2s-gpio28-31-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i2s-gpio28-31-overlay.dts 2023-12-13 11:50:48.604961285 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device tree overlay to move i2s to gpio 28 to 31 on CM + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_pins>; + __overlay__ { + brcm,pins = <28 29 30 31>; + brcm,function = <6>; /* alt2 */ + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ilitek251x-overlay.dts linux/arch/arm/boot/dts/overlays/ilitek251x-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ilitek251x-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ilitek251x-overlay.dts 2023-12-13 11:50:48.604961285 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Device tree overlay for I2C connected Ilitek multiple touch controller +/dts-v1/; +/plugin/; + + / { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + ili251x_pins: ili251x_pins { + brcm,pins = <4>; // interrupt + brcm,function = <0>; // in + brcm,pull = <2>; // pull-up // + }; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ili251x: ili251x@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&ili251x_pins>; + interrupt-parent = <&gpio>; + interrupts = <4 8>; // high-to-low edge triggered + touchscreen-size-x = <16384>; + touchscreen-size-y = <9600>; + }; + }; + }; + + __overrides__ { + interrupt = <&ili251x_pins>,"brcm,pins:0", + <&ili251x>,"interrupts:0"; + sizex = <&ili251x>,"touchscreen-size-x:0"; + sizey = <&ili251x>,"touchscreen-size-y:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx219.dtsi linux/arch/arm/boot/dts/overlays/imx219.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/imx219.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx219.dtsi 2023-12-13 11:50:48.604961285 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Fragment that configures an imx219 + +cam_node: imx219@10 { + compatible = "sony,imx219"; + reg = <0x10>; + status = "disabled"; + + clocks = <&cam1_clk>; + clock-names = "xclk"; + + VANA-supply = <&cam1_reg>; /* 2.8v */ + VDIG-supply = <&cam_dummy_reg>; /* 1.8v */ + VDDL-supply = <&cam_dummy_reg>; /* 1.2v */ + + rotation = <180>; + orientation = <2>; + + port { + cam_endpoint: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <456000000>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx219-overlay.dts linux/arch/arm/boot/dts/overlays/imx219-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/imx219-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx219-overlay.dts 2023-12-13 11:50:48.604961285 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for IMX219 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + clk_frag: fragment@1 { + target = <&cam1_clk>; + __overlay__ { + status = "okay"; + clock-frequency = <24000000>; + }; + }; + + fragment@2 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + i2c_frag: fragment@100 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + #include "imx219.dtsi" + + vcm: ad5398@c { + compatible = "adi,ad5398"; + reg = <0x0c>; + status = "disabled"; + VANA-supply = <&cam1_reg>; + }; + }; + }; + + csi_frag: fragment@101 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + brcm,media-controller; + + port { + csi_ep: endpoint { + remote-endpoint = <&cam_endpoint>; + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + }; + }; + }; + }; + + __overrides__ { + rotation = <&cam_node>,"rotation:0"; + orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <&cam_node>, "clocks:0=",<&cam0_clk>, + <&cam_node>, "VANA-supply:0=",<&cam0_reg>, + <&vcm>, "VANA-supply:0=", <&cam0_reg>; + vcm = <&vcm>, "status=okay", + <&cam_node>,"lens-focus:0=", <&vcm>; + }; +}; + +&cam_node { + status = "okay"; +}; + +&cam_endpoint { + remote-endpoint = <&csi_ep>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx258.dtsi linux/arch/arm/boot/dts/overlays/imx258.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/imx258.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx258.dtsi 2023-12-13 11:50:48.604961285 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Fragment that configures a Sony IMX258 + +cam_node: imx258@10 { + compatible = "sony,imx258"; + reg = <0x10>; + status = "disabled"; + + clocks = <&cam1_clk>; + clock-names = "xclk"; + + vana-supply = <&cam1_reg>; /* 2.8v */ + vdig-supply = <&cam_dummy_reg>; /* 1.05v */ + vif-supply = <&cam_dummy_reg>; /* 1.8v */ + + rotation = <180>; + orientation = <2>; + + port { + cam_endpoint: endpoint { + clock-lanes = <0>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <633600000 + 320000000>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx258-overlay.dts linux/arch/arm/boot/dts/overlays/imx258-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/imx258-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx258-overlay.dts 2023-12-13 11:50:48.604961285 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for IMX258 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + clk_frag: fragment@1 { + target = <&cam1_clk>; + cam_clk: __overlay__ { + clock-frequency = <24000000>; + status = "okay"; + }; + }; + + fragment@2 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&cam_endpoint>; + __overlay__ { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <633600000 + 320000000>; + }; + }; + + fragment@12 { + target = <&cam_endpoint>; + __dormant__ { + data-lanes = <1 2 3 4>; + link-frequencies = + /bits/ 64 <633600000 320000000>; + }; + }; + + fragment@13 { + target = <&csi_ep>; + __overlay__ { + data-lanes = <1 2>; + }; + }; + + fragment@14 { + target = <&csi_ep>; + __dormant__ { + data-lanes = <1 2 3 4>; + }; + }; + + csi_frag: fragment@101 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + brcm,media-controller; + + port { + csi_ep: endpoint { + remote-endpoint = <&cam_endpoint>; + clock-lanes = <0>; + clock-noncontinuous; + }; + }; + }; + }; + + reg_frag: fragment@5 { + target = <&cam1_reg>; + cam_reg: __overlay__ { + regulator-name = "imx258_vana"; + startup-delay-us = <300000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + }; + + i2c_frag: fragment@100 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + #include "imx258.dtsi" + + vcm: ad5398@c { + compatible = "adi,ad5398"; + reg = <0x0c>; + status = "disabled"; + VANA-supply = <&cam1_reg>; + }; + }; + }; + + __overrides__ { + rotation = <&cam_node>,"rotation:0"; + orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <®_frag>, "target:0=",<&cam0_reg>, + <&cam_node>, "clocks:0=",<&cam0_clk>, + <&cam_node>, "vana-supply:0=",<&cam0_reg>; + vcm = <&vcm>, "status=okay", + <&cam_node>,"lens-focus:0=", <&vcm>; + 4lane = <0>, "-11+12-13+14"; + }; +}; + +&cam_node { + status = "okay"; +}; + +&cam_endpoint { + remote-endpoint = <&csi_ep>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx290_327.dtsi linux/arch/arm/boot/dts/overlays/imx290_327.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/imx290_327.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx290_327.dtsi 2023-12-13 11:50:48.605961287 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Fragment to configure and IMX290 / IMX327 / IMX462 image sensor + +cam_node: imx290@1a { + compatible = "sony,imx290lqr"; + reg = <0x1a>; + status = "disabled"; + + clocks = <&cam1_clk>; + clock-names = "xclk"; + clock-frequency = <37125000>; + + rotation = <0>; + orientation = <2>; + + vdda-supply = <&cam1_reg>; /* 2.8v */ + vdddo-supply = <&cam_dummy_reg>; /* 1.8v */ + vddd-supply = <&cam_dummy_reg>; /* 1.5v */ + + port { + cam_endpoint: endpoint { + clock-lanes = <0>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi linux/arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi 2023-12-13 11:50:48.605961287 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Partial definitions for IMX290 or IMX327 camera module on VC I2C bus +// The compatible string should be set in an overlay that then includes this one +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2835"; + + i2c_frag: fragment@0 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + #include "imx290_327.dtsi" + }; + }; + + csi_frag: fragment@1 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + brcm,media-controller; + + port { + csi_ep: endpoint { + remote-endpoint = <&cam_endpoint>; + }; + }; + }; + }; + + fragment@2 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + clk_frag: fragment@3 { + target = <&cam1_clk>; + cam_clk: __overlay__ { + status = "okay"; + clock-frequency = <37125000>; + }; + }; + + fragment@4 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&cam_endpoint>; + __overlay__ { + data-lanes = <1 2>; + link-frequencies = + /bits/ 64 <445500000 297000000>; + }; + }; + + fragment@7 { + target = <&cam_endpoint>; + __dormant__ { + data-lanes = <1 2 3 4>; + link-frequencies = + /bits/ 64 <222750000 148500000>; + }; + }; + + fragment@8 { + target = <&csi_ep>; + __overlay__ { + data-lanes = <1 2>; + }; + }; + + fragment@9 { + target = <&csi_ep>; + __dormant__ { + data-lanes = <1 2 3 4>; + }; + }; + + __overrides__ { + 4lane = <0>, "-6+7-8+9"; + clock-frequency = <&cam_clk>,"clock-frequency:0", + <&cam_node>,"clock-frequency:0"; + rotation = <&cam_node>,"rotation:0"; + orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <&cam_node>, "clocks:0=",<&cam0_clk>, + <&cam_node>, "vdda-supply:0=",<&cam0_reg>; + }; +}; + +&cam_node { + status = "okay"; +}; + +&cam_endpoint { + remote-endpoint = <&csi_ep>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx290-overlay.dts linux/arch/arm/boot/dts/overlays/imx290-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/imx290-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx290-overlay.dts 2023-12-13 11:50:48.605961287 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for IMX290 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include "imx290_327-overlay.dtsi" + +/{ + compatible = "brcm,bcm2835"; + + // Fragment numbers deliberately high to avoid conflicts with the + // included imx290_327 overlay file. + + fragment@101 { + target = <&cam_node>; + __overlay__ { + compatible = "sony,imx290lqr"; + }; + }; + + fragment@102 { + target = <&cam_node>; + __dormant__ { + compatible = "sony,imx290llr"; + }; + }; + + __overrides__ { + mono = <0>, "-101+102"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx296-overlay.dts linux/arch/arm/boot/dts/overlays/imx296-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/imx296-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx296-overlay.dts 2023-12-13 11:50:48.605961287 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for IMX296 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + clk_frag: fragment@1 { + target = <&cam1_clk>; + clk_over: __overlay__ { + status = "okay"; + clock-frequency = <54000000>; + }; + }; + + fragment@2 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + reg_frag: fragment@5 { + target = <&cam1_reg>; + cam_reg: __overlay__ { + startup-delay-us = <500000>; + }; + }; + + i2c_frag: fragment@100 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + imx296: imx296@1a { + compatible = "sony,imx296"; + reg = <0x1a>; + status = "okay"; + + clocks = <&cam1_clk>; + clock-names = "inck"; + + avdd-supply = <&cam1_reg>; /* 3.3v */ + dvdd-supply = <&cam_dummy_reg>; /* 1.8v */ + ovdd-supply = <&cam_dummy_reg>; /* 1.2v */ + + rotation = <180>; + orientation = <2>; + + port { + imx296_0: endpoint { + remote-endpoint = <&csi_ep>; + clock-lanes = <0>; + data-lanes = <1>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <594000000>; + }; + }; + }; + }; + }; + + csi_frag: fragment@101 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + brcm,media-controller; + + port { + csi_ep: endpoint { + remote-endpoint = <&imx296_0>; + clock-lanes = <0>; + data-lanes = <1>; + clock-noncontinuous; + }; + }; + }; + }; + + __overrides__ { + rotation = <&imx296>,"rotation:0"; + orientation = <&imx296>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <®_frag>, "target:0=",<&cam0_reg>, + <&imx296>, "clocks:0=",<&cam0_clk>, + <&imx296>, "avdd-supply:0=",<&cam0_reg>; + clock-frequency = <&clk_over>, "clock-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx327-overlay.dts linux/arch/arm/boot/dts/overlays/imx327-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/imx327-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx327-overlay.dts 2023-12-13 11:50:48.605961287 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for IMX327 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include "imx290_327-overlay.dtsi" + +/{ + compatible = "brcm,bcm2835"; + + // Fragment numbers deliberately high to avoid conflicts with the + // included imx290_327 overlay file. + + fragment@101 { + target = <&cam_node>; + __overlay__ { + compatible = "sony,imx327lqr"; + }; + }; + + fragment@102 { + target = <&cam_node>; + __dormant__ { + // IMX327 mono is undefined in the binding - use imx290 + compatible = "sony,imx290llr"; + }; + }; + + __overrides__ { + mono = <0>, "-101+102"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx378-overlay.dts linux/arch/arm/boot/dts/overlays/imx378-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/imx378-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx378-overlay.dts 2023-12-13 11:50:48.605961287 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for IMX378 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +#include "imx477_378-overlay.dtsi" + +&cam_node { + compatible = "sony,imx378"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx462-overlay.dts linux/arch/arm/boot/dts/overlays/imx462-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/imx462-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx462-overlay.dts 2023-12-13 11:50:48.605961287 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for IMX462 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include "imx290_327-overlay.dtsi" + +/{ + compatible = "brcm,bcm2835"; + + // Fragment numbers deliberately high to avoid conflicts with the + // included imx290_327 overlay file. + + //IMX462 is not defined in the bindings, so use IMX290 for now. + + fragment@101 { + target = <&cam_node>; + __overlay__ { + compatible = "sony,imx290lqr"; + }; + }; + + fragment@102 { + target = <&cam_node>; + __dormant__ { + compatible = "sony,imx290llr"; + }; + }; + + __overrides__ { + mono = <0>, "-101+102"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx477_378.dtsi linux/arch/arm/boot/dts/overlays/imx477_378.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/imx477_378.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx477_378.dtsi 2023-12-13 11:50:48.606961289 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +cam_node: imx477@1a { + reg = <0x1a>; + status = "disabled"; + + clocks = <&cam1_clk>; + clock-names = "xclk"; + + VANA-supply = <&cam1_reg>; /* 2.8v */ + VDIG-supply = <&cam_dummy_reg>; /* 1.05v */ + VDDL-supply = <&cam_dummy_reg>; /* 1.8v */ + + rotation = <180>; + orientation = <2>; + + port { + cam_endpoint: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <450000000>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx477_378-overlay.dtsi linux/arch/arm/boot/dts/overlays/imx477_378-overlay.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/imx477_378-overlay.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx477_378-overlay.dtsi 2023-12-13 11:50:48.606961289 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for IMX477 camera module on VC I2C bus + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + clk_frag: fragment@1 { + target = <&cam1_clk>; + cam_clk: __overlay__ { + clock-frequency = <24000000>; + status = "okay"; + }; + }; + + fragment@2 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + reg_frag: fragment@3 { + target = <&cam1_reg>; + cam_reg: __overlay__ { + startup-delay-us = <300000>; + }; + }; + + i2c_frag: fragment@100 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + #include "imx477_378.dtsi" + }; + }; + + csi_frag: fragment@101 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + brcm,media-controller; + + port { + csi_ep: endpoint { + remote-endpoint = <&cam_endpoint>; + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + }; + }; + }; + }; + + __overrides__ { + rotation = <&cam_node>,"rotation:0"; + orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <®_frag>, "target:0=",<&cam0_reg>, + <&cam_node>, "clocks:0=",<&cam0_clk>, + <&cam_node>, "VANA-supply:0=",<&cam0_reg>; + }; +}; + +&cam_node { + status = "okay"; +}; + +&cam_endpoint { + remote-endpoint = <&csi_ep>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx477-overlay.dts linux/arch/arm/boot/dts/overlays/imx477-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/imx477-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx477-overlay.dts 2023-12-13 11:50:48.606961289 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for IMX477 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +#include "imx477_378-overlay.dtsi" + +&cam_node { + compatible = "sony,imx477"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx519.dtsi linux/arch/arm/boot/dts/overlays/imx519.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/imx519.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx519.dtsi 2023-12-13 11:50:48.606961289 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Fragment that configures a Sony IMX519 + +cam_node: imx519@1a { + compatible = "sony,imx519"; + reg = <0x1a>; + status = "disabled"; + + clocks = <&cam1_clk>; + clock-names = "xclk"; + + VANA-supply = <&cam1_reg>; /* 2.8v */ + VDIG-supply = <&cam_dummy_reg>; /* 1.8v */ + VDDL-supply = <&cam_dummy_reg>; /* 1.2v */ + + rotation = <0>; + orientation = <2>; + + port { + cam_endpoint: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <408000000>; + }; + }; +}; + +vcm_node: ak7375@c { + compatible = "asahi-kasei,ak7375"; + reg = <0x0c>; + status = "disabled"; + vdd-supply = <&cam1_reg>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx519-overlay.dts linux/arch/arm/boot/dts/overlays/imx519-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/imx519-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx519-overlay.dts 2023-12-13 11:50:48.606961289 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for imx519 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2835"; + + i2c_frag: fragment@0 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + #include "imx519.dtsi" + }; + }; + + csi_frag: fragment@1 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + brcm,media-controller; + + port{ + csi_ep: endpoint{ + remote-endpoint = <&cam_endpoint>; + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + }; + }; + }; + }; + + fragment@2 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + clk_frag: fragment@3 { + target = <&cam1_clk>; + __overlay__ { + clock-frequency = <24000000>; + status = "okay"; + }; + }; + + fragment@4 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&cam_node>; + __overlay__ { + lens-focus = <&vcm_node>; + }; + }; + + __overrides__ { + rotation = <&cam_node>,"rotation:0"; + orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <&cam_node>, "clocks:0=",<&cam0_clk>, + <&cam_node>, "VANA-supply:0=",<&cam0_reg>, + <&vcm_node>, "vdd-supply:0=",<&cam0_reg>; + vcm = <&vcm_node>, "status", + <0>, "=5"; + }; +}; + +&cam_node { + status = "okay"; +}; + +&cam_endpoint { + remote-endpoint = <&csi_ep>; +}; + +&vcm_node { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx708.dtsi linux/arch/arm/boot/dts/overlays/imx708.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/imx708.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx708.dtsi 2023-12-13 11:50:48.606961289 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Fragment that configures a Sony IMX708 + +cam_node: imx708@1a { + compatible = "sony,imx708"; + reg = <0x1a>; + status = "disabled"; + + clocks = <&cam1_clk>; + clock-names = "inclk"; + + vana1-supply = <&cam1_reg>; /* 2.8v */ + vana2-supply = <&cam_dummy_reg>;/* 1.8v */ + vdig-supply = <&cam_dummy_reg>; /* 1.1v */ + vddl-supply = <&cam_dummy_reg>; /* 1.8v */ + + rotation = <180>; + orientation = <2>; + + port { + cam_endpoint: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <450000000>; + }; + }; +}; + +vcm_node: dw9817@c { + compatible = "dongwoon,dw9817-vcm"; + reg = <0x0c>; + status = "disabled"; + VDD-supply = <&cam1_reg>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/imx708-overlay.dts linux/arch/arm/boot/dts/overlays/imx708-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/imx708-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/imx708-overlay.dts 2023-12-13 11:50:48.606961289 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for IMX708 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + clk_frag: fragment@1 { + target = <&cam1_clk>; + __overlay__ { + status = "okay"; + clock-frequency = <24000000>; + }; + }; + + fragment@2 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + reg_frag: fragment@3 { + target = <&cam1_reg>; + cam_reg: __overlay__ { + startup-delay-us = <70000>; + off-on-delay-us = <30000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + }; + + fragment@4 { + target = <&cam_node>; + __overlay__ { + lens-focus = <&vcm_node>; + }; + }; + + i2c_frag: fragment@100 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + #include "imx708.dtsi" + }; + }; + + csi_frag: fragment@101 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + brcm,media-controller; + + port { + csi_ep: endpoint { + remote-endpoint = <&cam_endpoint>; + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + }; + }; + }; + }; + + __overrides__ { + rotation = <&cam_node>,"rotation:0"; + orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <®_frag>, "target:0=",<&cam0_reg>, + <&cam_node>, "clocks:0=",<&cam0_clk>, + <&cam_node>, "vana1-supply:0=",<&cam0_reg>, + <&vcm_node>, "VDD-supply:0=",<&cam0_reg>; + vcm = <&vcm_node>, "status", + <0>, "=4"; + link-frequency = <&cam_endpoint>,"link-frequencies#0"; + }; +}; + +&cam_node { + status = "okay"; +}; + +&cam_endpoint { + remote-endpoint = <&csi_ep>; +}; + +&vcm_node { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/iqaudio-codec-overlay.dts linux/arch/arm/boot/dts/overlays/iqaudio-codec-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/iqaudio-codec-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/iqaudio-codec-overlay.dts 2023-12-13 11:50:48.607961292 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for IQaudIO CODEC +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + da2713@1a { + #sound-dai-cells = <0>; + compatible = "dlg,da7213"; + reg = <0x1a>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + iqaudio_dac: __overlay__ { + compatible = "iqaudio,iqaudio-codec"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; + + __overrides__ { + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts linux/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts 2023-12-13 11:50:48.607961292 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for IQaudIO DAC +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pcm5122@4c { + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + reg = <0x4c>; + AVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + CPVDD-supply = <&vdd_3v3_reg>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + frag2: __overlay__ { + compatible = "iqaudio,iqaudio-dac"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; + + __overrides__ { + 24db_digital_gain = <&frag2>,"iqaudio,24db_digital_gain?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts linux/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts 2023-12-13 11:50:48.607961292 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for IQaudIO DAC+ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pcm5122@4c { + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + reg = <0x4c>; + AVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + CPVDD-supply = <&vdd_3v3_reg>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + iqaudio_dac: __overlay__ { + compatible = "iqaudio,iqaudio-dac"; + i2s-controller = <&i2s_clk_producer>; + mute-gpios = <&gpio 22 0>; + status = "okay"; + }; + }; + + __overrides__ { + 24db_digital_gain = <&iqaudio_dac>,"iqaudio,24db_digital_gain?"; + auto_mute_amp = <&iqaudio_dac>,"iqaudio-dac,auto-mute-amp?"; + unmute_amp = <&iqaudio_dac>,"iqaudio-dac,unmute-amp?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/iqaudio-digi-wm8804-audio-overlay.dts linux/arch/arm/boot/dts/overlays/iqaudio-digi-wm8804-audio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/iqaudio-digi-wm8804-audio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/iqaudio-digi-wm8804-audio-overlay.dts 2023-12-13 11:50:48.607961292 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for IQAudIO Digi WM8804 audio board +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wm8804@3b { + #sound-dai-cells = <0>; + compatible = "wlf,wm8804"; + reg = <0x3b>; + status = "okay"; + DVDD-supply = <&vdd_3v3_reg>; + PVDD-supply = <&vdd_3v3_reg>; + }; + }; + }; + + fragment@2 { + target = <&sound>; + wm8804_digi: __overlay__ { + compatible = "iqaudio,wm8804-digi"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; + + __overrides__ { + card_name = <&wm8804_digi>,"wm8804-digi,card-name"; + dai_name = <&wm8804_digi>,"wm8804-digi,dai-name"; + dai_stream_name = <&wm8804_digi>,"wm8804-digi,dai-stream-name"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/iqs550-overlay.dts linux/arch/arm/boot/dts/overlays/iqs550-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/iqs550-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/iqs550-overlay.dts 2023-12-13 11:50:48.607961292 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-or-later +// Definitions for Azoteq IQS550 trackpad/touchscreen controller +/dts-v1/; +/plugin/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + iqs550: iqs550@74 { + compatible = "azoteq,iqs550"; + reg = <0x74>; + interrupt-parent = <&gpio>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&iqs550_pins>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; + }; + }; + + fragment@1 { + target = <&iqs550>; + iqs550_reset: __dormant__ { + reset-gpios = <&gpio 255 (GPIO_ACTIVE_LOW | + GPIO_PUSH_PULL)>; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + iqs550_pins: iqs550_pins { + brcm,pins = <4>; + brcm,pull = <1>; + }; + }; + }; + + __overrides__ { + interrupt = <&iqs550>,"interrupts:0", + <&iqs550_pins>,"brcm,pins:0"; + reset = <0>,"+1", <&iqs550_reset>,"reset-gpios:4"; + sizex = <&iqs550>,"touchscreen-size-x:0"; + sizey = <&iqs550>,"touchscreen-size-y:0"; + invx = <&iqs550>,"touchscreen-inverted-x?"; + invy = <&iqs550>,"touchscreen-inverted-y?"; + swapxy = <&iqs550>,"touchscreen-swapped-x-y?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/irs1125-overlay.dts linux/arch/arm/boot/dts/overlays/irs1125-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/irs1125-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/irs1125-overlay.dts 2023-12-13 11:50:48.607961292 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for IRS1125 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + i2c_frag: fragment@0 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + irs1125: irs1125@3d { + compatible = "infineon,irs1125"; + reg = <0x3d>; + status = "okay"; + + pwdn-gpios = <&gpio 5 0>; + clocks = <&cam1_clk>; + + port { + irs1125_0: endpoint { + remote-endpoint = <&csi1_ep>; + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <297000000>; + }; + }; + }; + }; + }; + + csi_frag: fragment@1 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&irs1125_0>; + data-lanes = <1 2>; + clock-noncontinuous; + }; + }; + }; + }; + + fragment@2 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target-path="/__overrides__"; + __overlay__ { + cam0-pwdn-ctrl = <&irs1125>,"pwdn-gpios:0"; + cam0-pwdn = <&irs1125>,"pwdn-gpios:4"; + }; + }; + + clk_frag: fragment@5 { + target = <&cam1_clk>; + __overlay__ { + status = "okay"; + clock-frequency = <26000000>; + }; + }; + + __overrides__ { + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <&irs1125>, "clocks:0=",<&cam0_clk>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/i-sabre-q2m-overlay.dts linux/arch/arm/boot/dts/overlays/i-sabre-q2m-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/i-sabre-q2m-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/i-sabre-q2m-overlay.dts 2023-12-13 11:50:48.600961275 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for I-Sabre Q2M +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&sound>; + frag0: __overlay__ { + compatible = "audiophonics,i-sabre-q2m"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i-sabre-codec@48 { + #sound-dai-cells = <0>; + compatible = "audiophonics,i-sabre-codec"; + reg = <0x48>; + status = "okay"; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/jedec-spi-nor-overlay.dts linux/arch/arm/boot/dts/overlays/jedec-spi-nor-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/jedec-spi-nor-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/jedec-spi-nor-overlay.dts 2023-12-13 11:50:48.607961292 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for JEDEC SPI-NOR Flash Devices (aka m25p80) + +// dtparams: +// flash-spi<n>-<m> - Enables flash device on SPI<n>, CS#<m>. +// flash-fastr-spi<n>-<m> - Enables flash device with fast read capability on SPI<n>, CS#<m>. +// speed - Set the SPI clock speed in Hz +// +// If devices are present on SPI1 or SPI2, those interfaces must be enabled with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays. +// +// Example: A single flash device with fast read capability on SPI0, CS#0: +// dtoverlay=jedec-spi-nor:flash-fastr-spi0-0 + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + // disable spi-dev on spi0.0 + fragment@0 { + target = <&spidev0>; + __dormant__ { + status = "disabled"; + }; + }; + + // disable spi-dev on spi0.1 + fragment@1 { + target = <&spidev1>; + __dormant__ { + status = "disabled"; + }; + }; + + // disable spi-dev on spi1.0 + fragment@2 { + target-path = "spi1/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + // disable spi-dev on spi1.1 + fragment@3 { + target-path = "spi1/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + // disable spi-dev on spi1.2 + fragment@4 { + target-path = "spi1/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + // disable spi-dev on spi2.0 + fragment@5 { + target-path = "spi2/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + // disable spi-dev on spi2.1 + fragment@6 { + target-path = "spi2/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + // disable spi-dev on spi2.2 + fragment@7 { + target-path = "spi2/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + // Enable fast read for device + // Use default active low interrupt signalling. + fragment@8 { + target = <&spi_nor>; + __dormant__ { + m25p,fast-read; + }; + }; + + payload: fragment@100 { + target = <&spi0>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + spi_nor: spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <500000>; + }; + }; + }; + + __overrides__ { + spi0-0 = <0>,"+0", <&payload>,"target:0=",<&spi0>, <&spi_nor>,"reg:0=0"; + spi0-1 = <0>,"+1", <&payload>,"target:0=",<&spi0>, <&spi_nor>,"reg:0=1"; + spi1-0 = <0>,"+2", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=0"; + spi1-1 = <0>,"+3", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=1"; + spi1-2 = <0>,"+4", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=2"; + spi2-0 = <0>,"+5", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=0"; + spi2-1 = <0>,"+6", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=1"; + spi2-2 = <0>,"+7", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=2"; + flash-spi0-0 = <0>,"+0", <&payload>,"target:0=",<&spi0>, <&spi_nor>,"reg:0=0"; + flash-spi0-1 = <0>,"+1", <&payload>,"target:0=",<&spi0>, <&spi_nor>,"reg:0=1"; + flash-spi1-0 = <0>,"+2", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=0"; + flash-spi1-1 = <0>,"+3", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=1"; + flash-spi1-2 = <0>,"+4", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=2"; + flash-spi2-0 = <0>,"+5", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=0"; + flash-spi2-1 = <0>,"+6", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=1"; + flash-spi2-2 = <0>,"+7", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=2"; + flash-fastr-spi0-0 = <0>,"+0+8", <&payload>,"target:0=",<&spi0>, <&spi_nor>,"reg:0=0"; + flash-fastr-spi0-1 = <0>,"+1+8", <&payload>,"target:0=",<&spi0>, <&spi_nor>,"reg:0=1"; + flash-fastr-spi1-0 = <0>,"+2+8", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=0"; + flash-fastr-spi1-1 = <0>,"+3+8", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=1"; + flash-fastr-spi1-2 = <0>,"+4+8", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=2"; + flash-fastr-spi2-0 = <0>,"+5+8", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=0"; + flash-fastr-spi2-1 = <0>,"+6+8", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=1"; + flash-fastr-spi2-2 = <0>,"+7+8", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=2"; + fastr = <0>,"+8"; + speed = <&spi_nor>, "spi-max-frequency:0"; + }; +}; + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/justboom-both-overlay.dts linux/arch/arm/boot/dts/overlays/justboom-both-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/justboom-both-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/justboom-both-overlay.dts 2023-12-13 11:50:48.607961292 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 +// Definitions for JustBoom Both (Digi+DAC) +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wm8804@3b { + #sound-dai-cells = <0>; + compatible = "wlf,wm8804"; + reg = <0x3b>; + PVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pcm5122@4d { + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + reg = <0x4d>; + AVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + CPVDD-supply = <&vdd_3v3_reg>; + status = "okay"; + }; + }; + }; + + fragment@3 { + target = <&sound>; + frag3: __overlay__ { + compatible = "justboom,justboom-both"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; + + __overrides__ { + 24db_digital_gain = <&frag3>,"justboom,24db_digital_gain?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/justboom-dac-overlay.dts linux/arch/arm/boot/dts/overlays/justboom-dac-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/justboom-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/justboom-dac-overlay.dts 2023-12-13 11:50:48.608961294 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for JustBoom DAC +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pcm5122@4d { + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + reg = <0x4d>; + AVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + CPVDD-supply = <&vdd_3v3_reg>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + frag2: __overlay__ { + compatible = "justboom,justboom-dac"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; + + __overrides__ { + 24db_digital_gain = <&frag2>,"justboom,24db_digital_gain?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/justboom-digi-overlay.dts linux/arch/arm/boot/dts/overlays/justboom-digi-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/justboom-digi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/justboom-digi-overlay.dts 2023-12-13 11:50:48.608961294 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for JustBoom Digi +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wm8804@3b { + #sound-dai-cells = <0>; + compatible = "wlf,wm8804"; + reg = <0x3b>; + PVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "justboom,justboom-digi"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ltc294x-overlay.dts linux/arch/arm/boot/dts/overlays/ltc294x-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ltc294x-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ltc294x-overlay.dts 2023-12-13 11:50:48.608961294 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c_arm>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ltc2941: ltc2941@64 { + compatible = "lltc,ltc2941"; + reg = <0x64>; + lltc,resistor-sense = <50>; + lltc,prescaler-exponent = <7>; + }; + }; + }; + + fragment@1 { + target = <&i2c_arm>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ltc2942: ltc2942@64 { + compatible = "lltc,ltc2942"; + reg = <0x64>; + lltc,resistor-sense = <50>; + lltc,prescaler-exponent = <7>; + }; + }; + }; + + fragment@2 { + target = <&i2c_arm>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ltc2943: ltc2943@64 { + compatible = "lltc,ltc2943"; + reg = <0x64>; + lltc,resistor-sense = <50>; + lltc,prescaler-exponent = <7>; + }; + }; + }; + + fragment@3 { + target = <&i2c_arm>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ltc2944: ltc2944@64 { + compatible = "lltc,ltc2944"; + reg = <0x64>; + lltc,resistor-sense = <50>; + lltc,prescaler-exponent = <7>; + }; + }; + }; + + __overrides__ { + ltc2941 = <0>,"+0"; + ltc2942 = <0>,"+1"; + ltc2943 = <0>,"+2"; + ltc2944 = <0>,"+3"; + resistor-sense = <<c2941>, "lltc,resistor-sense:0", + <<c2942>, "lltc,resistor-sense:0", + <<c2943>, "lltc,resistor-sense:0", + <<c2944>, "lltc,resistor-sense:0"; + prescaler-exponent = <<c2941>, "lltc,prescaler-exponent:0", + <<c2942>, "lltc,prescaler-exponent:0", + <<c2943>, "lltc,prescaler-exponent:0", + <<c2944>, "lltc,prescaler-exponent:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/Makefile linux/arch/arm/boot/dts/overlays/Makefile --- linux-6.1.66/arch/arm/boot/dts/overlays/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/Makefile 2023-12-13 11:50:48.583961235 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# Overlays for the Raspberry Pi platform + +dtb-$(CONFIG_ARCH_BCM2835) += overlay_map.dtb hat_map.dtb + +dtbo-$(CONFIG_ARCH_BCM2835) += \ + act-led.dtbo \ + adafruit-st7735r.dtbo \ + adafruit18.dtbo \ + adau1977-adc.dtbo \ + adau7002-simple.dtbo \ + ads1015.dtbo \ + ads1115.dtbo \ + ads7846.dtbo \ + adv7282m.dtbo \ + adv728x-m.dtbo \ + akkordion-iqdacplus.dtbo \ + allo-boss-dac-pcm512x-audio.dtbo \ + allo-boss2-dac-audio.dtbo \ + allo-digione.dtbo \ + allo-katana-dac-audio.dtbo \ + allo-piano-dac-pcm512x-audio.dtbo \ + allo-piano-dac-plus-pcm512x-audio.dtbo \ + anyspi.dtbo \ + apds9960.dtbo \ + applepi-dac.dtbo \ + arducam-64mp.dtbo \ + arducam-pivariety.dtbo \ + at86rf233.dtbo \ + audioinjector-addons.dtbo \ + audioinjector-bare-i2s.dtbo \ + audioinjector-isolated-soundcard.dtbo \ + audioinjector-ultra.dtbo \ + audioinjector-wm8731-audio.dtbo \ + audiosense-pi.dtbo \ + audremap.dtbo \ + balena-fin.dtbo \ + camera-mux-2port.dtbo \ + camera-mux-4port.dtbo \ + cap1106.dtbo \ + chipdip-dac.dtbo \ + cirrus-wm5102.dtbo \ + cm-swap-i2c0.dtbo \ + cma.dtbo \ + crystalfontz-cfa050_pi_m.dtbo \ + cutiepi-panel.dtbo \ + dacberry400.dtbo \ + dht11.dtbo \ + dionaudio-kiwi.dtbo \ + dionaudio-loco.dtbo \ + dionaudio-loco-v2.dtbo \ + disable-bt.dtbo \ + disable-bt-pi5.dtbo \ + disable-emmc2.dtbo \ + disable-wifi.dtbo \ + disable-wifi-pi5.dtbo \ + dpi18.dtbo \ + dpi18cpadhi.dtbo \ + dpi24.dtbo \ + draws.dtbo \ + dwc-otg.dtbo \ + dwc2.dtbo \ + edt-ft5406.dtbo \ + enc28j60.dtbo \ + enc28j60-spi2.dtbo \ + exc3000.dtbo \ + fbtft.dtbo \ + fe-pi-audio.dtbo \ + fsm-demo.dtbo \ + gc9a01.dtbo \ + ghost-amp.dtbo \ + goodix.dtbo \ + googlevoicehat-soundcard.dtbo \ + gpio-charger.dtbo \ + gpio-fan.dtbo \ + gpio-hog.dtbo \ + gpio-ir.dtbo \ + gpio-ir-tx.dtbo \ + gpio-key.dtbo \ + gpio-led.dtbo \ + gpio-no-bank0-irq.dtbo \ + gpio-no-irq.dtbo \ + gpio-poweroff.dtbo \ + gpio-shutdown.dtbo \ + hd44780-lcd.dtbo \ + hdmi-backlight-hwhack-gpio.dtbo \ + hifiberry-amp.dtbo \ + hifiberry-amp100.dtbo \ + hifiberry-amp3.dtbo \ + hifiberry-dac.dtbo \ + hifiberry-dacplus.dtbo \ + hifiberry-dacplusadc.dtbo \ + hifiberry-dacplusadcpro.dtbo \ + hifiberry-dacplusdsp.dtbo \ + hifiberry-dacplushd.dtbo \ + hifiberry-digi.dtbo \ + hifiberry-digi-pro.dtbo \ + highperi.dtbo \ + hy28a.dtbo \ + hy28b.dtbo \ + hy28b-2017.dtbo \ + i-sabre-q2m.dtbo \ + i2c-bcm2708.dtbo \ + i2c-fan.dtbo \ + i2c-gpio.dtbo \ + i2c-mux.dtbo \ + i2c-pwm-pca9685a.dtbo \ + i2c-rtc.dtbo \ + i2c-rtc-gpio.dtbo \ + i2c-sensor.dtbo \ + i2c0.dtbo \ + i2c0-pi5.dtbo \ + i2c1.dtbo \ + i2c1-pi5.dtbo \ + i2c2-pi5.dtbo \ + i2c3.dtbo \ + i2c3-pi5.dtbo \ + i2c4.dtbo \ + i2c5.dtbo \ + i2c6.dtbo \ + i2s-dac.dtbo \ + i2s-gpio28-31.dtbo \ + ilitek251x.dtbo \ + imx219.dtbo \ + imx258.dtbo \ + imx290.dtbo \ + imx296.dtbo \ + imx327.dtbo \ + imx378.dtbo \ + imx462.dtbo \ + imx477.dtbo \ + imx519.dtbo \ + imx708.dtbo \ + iqaudio-codec.dtbo \ + iqaudio-dac.dtbo \ + iqaudio-dacplus.dtbo \ + iqaudio-digi-wm8804-audio.dtbo \ + iqs550.dtbo \ + irs1125.dtbo \ + jedec-spi-nor.dtbo \ + justboom-both.dtbo \ + justboom-dac.dtbo \ + justboom-digi.dtbo \ + ltc294x.dtbo \ + max98357a.dtbo \ + maxtherm.dtbo \ + mbed-dac.dtbo \ + mcp23017.dtbo \ + mcp23s17.dtbo \ + mcp2515.dtbo \ + mcp2515-can0.dtbo \ + mcp2515-can1.dtbo \ + mcp251xfd.dtbo \ + mcp3008.dtbo \ + mcp3202.dtbo \ + mcp342x.dtbo \ + media-center.dtbo \ + merus-amp.dtbo \ + midi-uart0.dtbo \ + midi-uart0-pi5.dtbo \ + midi-uart1.dtbo \ + midi-uart1-pi5.dtbo \ + midi-uart2.dtbo \ + midi-uart2-pi5.dtbo \ + midi-uart3.dtbo \ + midi-uart3-pi5.dtbo \ + midi-uart4.dtbo \ + midi-uart4-pi5.dtbo \ + midi-uart5.dtbo \ + minipitft13.dtbo \ + miniuart-bt.dtbo \ + mipi-dbi-spi.dtbo \ + mlx90640.dtbo \ + mmc.dtbo \ + mpu6050.dtbo \ + mz61581.dtbo \ + ov2311.dtbo \ + ov5647.dtbo \ + ov64a40.dtbo \ + ov7251.dtbo \ + ov9281.dtbo \ + papirus.dtbo \ + pca953x.dtbo \ + pcf857x.dtbo \ + pcie-32bit-dma.dtbo \ + pibell.dtbo \ + pifacedigital.dtbo \ + pifi-40.dtbo \ + pifi-dac-hd.dtbo \ + pifi-dac-zero.dtbo \ + pifi-mini-210.dtbo \ + piglow.dtbo \ + piscreen.dtbo \ + piscreen2r.dtbo \ + pisound.dtbo \ + pitft22.dtbo \ + pitft28-capacitive.dtbo \ + pitft28-resistive.dtbo \ + pitft35-resistive.dtbo \ + pps-gpio.dtbo \ + proto-codec.dtbo \ + pwm.dtbo \ + pwm-2chan.dtbo \ + pwm-ir-tx.dtbo \ + pwm1.dtbo \ + qca7000.dtbo \ + qca7000-uart0.dtbo \ + ramoops.dtbo \ + ramoops-pi4.dtbo \ + rotary-encoder.dtbo \ + rpi-backlight.dtbo \ + rpi-codeczero.dtbo \ + rpi-dacplus.dtbo \ + rpi-dacpro.dtbo \ + rpi-digiampplus.dtbo \ + rpi-ft5406.dtbo \ + rpi-poe.dtbo \ + rpi-poe-plus.dtbo \ + rpi-sense.dtbo \ + rpi-sense-v2.dtbo \ + rpi-tv.dtbo \ + rra-digidac1-wm8741-audio.dtbo \ + sainsmart18.dtbo \ + sc16is750-i2c.dtbo \ + sc16is752-i2c.dtbo \ + sc16is752-spi0.dtbo \ + sc16is752-spi1.dtbo \ + sdhost.dtbo \ + sdio.dtbo \ + sdio-pi5.dtbo \ + seeed-can-fd-hat-v1.dtbo \ + seeed-can-fd-hat-v2.dtbo \ + sh1106-spi.dtbo \ + si446x-spi0.dtbo \ + smi.dtbo \ + smi-dev.dtbo \ + smi-nand.dtbo \ + spi-gpio35-39.dtbo \ + spi-gpio40-45.dtbo \ + spi-rtc.dtbo \ + spi0-0cs.dtbo \ + spi0-1cs.dtbo \ + spi0-2cs.dtbo \ + spi1-1cs.dtbo \ + spi1-2cs.dtbo \ + spi1-3cs.dtbo \ + spi2-1cs.dtbo \ + spi2-1cs-pi5.dtbo \ + spi2-2cs.dtbo \ + spi2-2cs-pi5.dtbo \ + spi2-3cs.dtbo \ + spi3-1cs.dtbo \ + spi3-1cs-pi5.dtbo \ + spi3-2cs.dtbo \ + spi3-2cs-pi5.dtbo \ + spi4-1cs.dtbo \ + spi4-2cs.dtbo \ + spi5-1cs.dtbo \ + spi5-1cs-pi5.dtbo \ + spi5-2cs.dtbo \ + spi5-2cs-pi5.dtbo \ + spi6-1cs.dtbo \ + spi6-2cs.dtbo \ + ssd1306.dtbo \ + ssd1306-spi.dtbo \ + ssd1331-spi.dtbo \ + ssd1351-spi.dtbo \ + superaudioboard.dtbo \ + sx150x.dtbo \ + tc358743.dtbo \ + tc358743-audio.dtbo \ + tinylcd35.dtbo \ + tpm-slb9670.dtbo \ + tpm-slb9673.dtbo \ + uart0.dtbo \ + uart0-pi5.dtbo \ + uart1.dtbo \ + uart1-pi5.dtbo \ + uart2.dtbo \ + uart2-pi5.dtbo \ + uart3.dtbo \ + uart3-pi5.dtbo \ + uart4.dtbo \ + uart4-pi5.dtbo \ + uart5.dtbo \ + udrc.dtbo \ + ugreen-dabboard.dtbo \ + upstream.dtbo \ + upstream-pi4.dtbo \ + vc4-fkms-v3d.dtbo \ + vc4-fkms-v3d-pi4.dtbo \ + vc4-kms-dpi-generic.dtbo \ + vc4-kms-dpi-hyperpixel2r.dtbo \ + vc4-kms-dpi-hyperpixel4.dtbo \ + vc4-kms-dpi-hyperpixel4sq.dtbo \ + vc4-kms-dpi-panel.dtbo \ + vc4-kms-dsi-7inch.dtbo \ + vc4-kms-dsi-generic.dtbo \ + vc4-kms-dsi-lt070me05000.dtbo \ + vc4-kms-dsi-lt070me05000-v2.dtbo \ + vc4-kms-dsi-waveshare-panel.dtbo \ + vc4-kms-kippah-7inch.dtbo \ + vc4-kms-v3d.dtbo \ + vc4-kms-v3d-pi4.dtbo \ + vc4-kms-v3d-pi5.dtbo \ + vc4-kms-vga666.dtbo \ + vga666.dtbo \ + vl805.dtbo \ + w1-gpio.dtbo \ + w1-gpio-pullup.dtbo \ + w5500.dtbo \ + watterott-display.dtbo \ + waveshare-can-fd-hat-mode-a.dtbo \ + waveshare-can-fd-hat-mode-b.dtbo \ + wittypi.dtbo \ + wm8960-soundcard.dtbo + +targets += dtbs dtbs_install +targets += $(dtbo-y) + +always-y := $(dtbo-y) +clean-files := *.dtbo diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/max98357a-overlay.dts linux/arch/arm/boot/dts/overlays/max98357a-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/max98357a-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/max98357a-overlay.dts 2023-12-13 11:50:48.608961294 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for Maxim MAX98357A audio DAC + +// dtparams: +// no-sdmode - SD_MODE pin not managed by driver. +// sdmode-pin - Specify GPIO pin to which SD_MODE is connected (default 4). + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + /* Enable I2S */ + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + /* DAC whose SD_MODE pin is managed by driver (via GPIO pin) */ + fragment@1 { + target-path = "/"; + __overlay__ { + max98357a_dac: max98357a { + compatible = "maxim,max98357a"; + #sound-dai-cells = <0>; + sdmode-gpios = <&gpio 4 0>; /* 2nd word overwritten by sdmode-pin parameter */ + status = "okay"; + }; + }; + }; + + /* DAC whose SD_MODE pin is not managed by driver */ + fragment@2 { + target-path = "/"; + __dormant__ { + max98357a_nsd: max98357a { + compatible = "maxim,max98357a"; + #sound-dai-cells = <0>; + status = "okay"; + }; + }; + }; + + /* Soundcard connecting I2S to DAC with SD_MODE */ + fragment@3 { + target = <&sound>; + __overlay__ { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "MAX98357A"; + status = "okay"; + simple-audio-card,cpu { + sound-dai = <&i2s_clk_producer>; + }; + simple-audio-card,codec { + sound-dai = <&max98357a_dac>; + }; + }; + }; + + /* Soundcard connecting I2S to DAC without SD_MODE */ + fragment@4 { + target = <&sound>; + __dormant__ { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "MAX98357A"; + status = "okay"; + simple-audio-card,cpu { + sound-dai = <&i2s_clk_producer>; + }; + simple-audio-card,codec { + sound-dai = <&max98357a_nsd>; + }; + }; + }; + + __overrides__ { + no-sdmode = <0>,"-1+2-3+4"; + sdmode-pin = <&max98357a_dac>,"sdmode-gpios:4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/maxtherm-overlay.dts linux/arch/arm/boot/dts/overlays/maxtherm-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/maxtherm-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/maxtherm-overlay.dts 2023-12-13 11:50:48.608961294 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Universal device tree overlay for SPI devices + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/iio/temperature/thermocouple.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&spidev1>; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@2 { + target-path = "spi1/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@3 { + target-path = "spi1/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@4 { + target-path = "spi1/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@5 { + target-path = "spi2/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@6 { + target-path = "spi2/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@7 { + target-path = "spi2/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + maxfrag: fragment@8 { + target = <&spi0>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + max: maxtherm@0 { + compatible = "maxim,max6675"; + reg = <0>; + spi-max-frequency = <500000>; + }; + }; + }; + + fragment@9 { + target = <&max>; + __dormant__ { + compatible = "maxim,max31855e", "maxim,max31855"; + }; + }; + + fragment@10 { + target = <&max>; + __dormant__ { + compatible = "maxim,max31855j", "maxim,max31855"; + }; + }; + + fragment@11 { + target = <&max>; + __dormant__ { + compatible = "maxim,max31855k", "maxim,max31855"; + }; + }; + + fragment@12 { + target = <&max>; + __dormant__ { + compatible = "maxim,max31855n", "maxim,max31855"; + }; + }; + + fragment@13 { + target = <&max>; + __dormant__ { + compatible = "maxim,max31855r", "maxim,max31855"; + }; + }; + + fragment@14 { + target = <&max>; + __dormant__ { + compatible = "maxim,max31855s", "maxim,max31855"; + }; + }; + + fragment@15 { + target = <&max>; + __dormant__ { + compatible = "maxim,max31855t", "maxim,max31855"; + }; + }; + + fragment@16 { + target = <&max>; + __dormant__ { + compatible = "maxim,max31856"; + spi-cpha; + thermocouple-type = <THERMOCOUPLE_TYPE_K>; + }; + }; + + __overrides__ { + spi0-0 = <0>, "+0", + <&maxfrag>,"target:0=",<&spi0>, + <&max>,"reg:0=0"; + spi0-1 = <0>, "+1", + <&maxfrag>,"target:0=",<&spi0>, + <&max>,"reg:0=1"; + spi1-0 = <0>, "+2", + <&maxfrag>,"target:0=",<&spi1>, + <&max>,"reg:0=0"; + spi1-1 = <0>, "+3", + <&maxfrag>,"target:0=",<&spi1>, + <&max>,"reg:0=1"; + spi1-2 = <0>, "+4", + <&maxfrag>,"target:0=",<&spi1>, + <&max>,"reg:0=2"; + spi2-0 = <0>, "+5", + <&maxfrag>,"target:0=",<&spi2>, + <&max>,"reg:0=0"; + spi2-1 = <0>, "+6", + <&maxfrag>,"target:0=",<&spi2>, + <&max>,"reg:0=1"; + spi2-2 = <0>, "+7", + <&maxfrag>,"target:0=",<&spi2>, + <&max>,"reg:0=2"; + max6675 = <&max>,"compatible=maxim,max6675"; + max31855 = <&max>,"compatible=maxim,max31855"; + max31855e = <0>,"+9"; + max31855j = <0>,"+10"; + max31855k = <0>,"+11"; + max31855n = <0>,"+12"; + max31855r = <0>,"+13"; + max31855s = <0>,"+14"; + max31855t = <0>,"+15"; + max31856 = <0>,"+16"; + type_b = <&max>,"thermocouple-type:0=",<THERMOCOUPLE_TYPE_B>; + type_e = <&max>,"thermocouple-type:0=",<THERMOCOUPLE_TYPE_E>; + type_j = <&max>,"thermocouple-type:0=",<THERMOCOUPLE_TYPE_J>; + type_k = <&max>,"thermocouple-type:0=",<THERMOCOUPLE_TYPE_K>; + type_n = <&max>,"thermocouple-type:0=",<THERMOCOUPLE_TYPE_N>; + type_r = <&max>,"thermocouple-type:0=",<THERMOCOUPLE_TYPE_R>; + type_s = <&max>,"thermocouple-type:0=",<THERMOCOUPLE_TYPE_S>; + type_t = <&max>,"thermocouple-type:0=",<THERMOCOUPLE_TYPE_T>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/mbed-dac-overlay.dts linux/arch/arm/boot/dts/overlays/mbed-dac-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/mbed-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/mbed-dac-overlay.dts 2023-12-13 11:50:48.608961294 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for mbed DAC +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + tlv320aic23: codec@1a { + #sound-dai-cells = <0>; + reg = <0x1a>; + compatible = "ti,tlv320aic23"; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "simple-audio-card"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + + simple-audio-card,name = "mbed-DAC"; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Headphone", "Headphone Jack"; + + simple-audio-card,routing = + "Headphone Jack", "LHPOUT", + "Headphone Jack", "RHPOUT", + "LLINEIN", "Line In", + "RLINEIN", "Line In", + "MICIN", "Mic Jack"; + + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&i2s_clk_producer>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic23>; + system-clock-frequency = <12288000>; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/mcp23017-overlay.dts linux/arch/arm/boot/dts/overlays/mcp23017-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/mcp23017-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/mcp23017-overlay.dts 2023-12-13 11:50:48.608961294 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for MCP23017 Gpio Extender from Microchip Semiconductor + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2cbus>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + mcp23017_pins: mcp23017_pins@20 { + brcm,pins = <4>; + brcm,function = <0>; + }; + }; + }; + + fragment@2 { + target = <&mcp23017>; + __dormant__ { + compatible = "microchip,mcp23008"; + }; + }; + + fragment@3 { + target = <&mcp23017>; + mcp23017_irq: __overlay__ { + #interrupt-cells=<2>; + interrupt-parent = <&gpio>; + interrupts = <4 2>; + interrupt-controller; + microchip,irq-mirror; + }; + }; + + fragment@4 { + target = <&i2cbus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + mcp23017: mcp@20 { + compatible = "microchip,mcp23017"; + pinctrl-name = "default"; + pinctrl-0 = <&mcp23017_pins>; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + status = "okay"; + }; + }; + }; + + frag100: fragment@100 { + target = <&i2c1>; + i2cbus: __overlay__ { + status = "okay"; + }; + }; + + fragment@101 { + target = <&i2c0if>; + __dormant__ { + status = "okay"; + }; + }; + + fragment@102 { + target = <&i2c0mux>; + __dormant__ { + status = "okay"; + }; + }; + + __overrides__ { + gpiopin = <&mcp23017_pins>,"brcm,pins:0", + <&mcp23017_irq>,"interrupts:0"; + addr = <&mcp23017>,"reg:0", <&mcp23017_pins>,"reg:0"; + mcp23008 = <0>,"=2"; + noints = <0>,"!1!3"; + i2c0 = <&frag100>, "target:0=",<&i2c0>; + i2c_csi_dsi = <&frag100>, "target:0=",<&i2c_csi_dsi>, + <0>,"+101+102"; + i2c3 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c3"; + i2c4 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c4"; + i2c5 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c5"; + i2c6 = <&frag100>, "target?=0", + <&frag100>, "target-path=i2c6"; + }; +}; + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/mcp23s17-overlay.dts linux/arch/arm/boot/dts/overlays/mcp23s17-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/mcp23s17-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/mcp23s17-overlay.dts 2023-12-13 11:50:48.609961297 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for MCP23S08/17 GPIO Extenders from Microchip Semiconductor + +// dtparams: +// s08-spi<n>-<m>-present - 4-bit integer, bitmap indicating MCP23S08 devices present on SPI<n>, CS#<m>. +// s17-spi<n>-<m>-present - 8-bit integer, bitmap indicating MCP23S17 devices present on SPI<n>, CS#<m>. +// s08-spi<n>-<m>-int-gpio - integer, enables interrupts on a single MCP23S08 device on SPI<n>, CS#<m>, specifies the GPIO pin to which INT output is connected. +// s17-spi<n>-<m>-int-gpio - integer, enables mirrored interrupts on a single MCP23S17 device on SPI<n>, CS#<m>, specifies the GPIO pin to which either INTA or INTB output is connected. +// +// If devices are present on SPI1 or SPI2, those interfaces must be enabled with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays. +// If interrupts are enabled for a device on a given CS# on a SPI bus, that device must be the only one present on that SPI bus/CS#. +// +// Example 1: A single MCP23S17 device on SPI0, CS#0 with its SPI addr set to 0 and INTA output connected to GPIO25: +// dtoverlay=mcp23s17:s17-spi0-0-present=1,s17-spi0-0-int-gpio=25 +// +// Example 2: Two MCP23S08 devices on SPI1, CS#0 with their addrs set to 2 and 3. Three MCP23S17 devices on SPI1, CS#1 with their addrs set to 0, 1 and 7: +// dtoverlay=spi1-2cs +// dtoverlay=mcp23s17:s08-spi1-0-present=12,s17-spi1-1-present=131 + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + // disable spi-dev on spi0.0 + fragment@0 { + target = <&spidev0>; + __dormant__ { + status = "disabled"; + }; + }; + + // disable spi-dev on spi0.1 + fragment@1 { + target = <&spidev1>; + __dormant__ { + status = "disabled"; + }; + }; + + // disable spi-dev on spi1.0 + fragment@2 { + target-path = "spi1/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + // disable spi-dev on spi1.1 + fragment@3 { + target-path = "spi1/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + // disable spi-dev on spi1.2 + fragment@4 { + target-path = "spi1/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + // disable spi-dev on spi2.0 + fragment@5 { + target-path = "spi2/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + // disable spi-dev on spi2.1 + fragment@6 { + target-path = "spi2/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + // disable spi-dev on spi2.2 + fragment@7 { + target-path = "spi2/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + // enable one or more mcp23s08s on spi0.0 + fragment@8 { + target = <&spi0>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s08_00: mcp23s08@0 { + compatible = "microchip,mcp23s08"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi0-0-present parameter */ + reg = <0>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi0-0-int-gpio parameter */ + }; + }; + }; + + // enable one or more mcp23s08s on spi0.1 + fragment@9 { + target = <&spi0>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s08_01: mcp23s08@1 { + compatible = "microchip,mcp23s08"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi0-1-present parameter */ + reg = <1>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi0-1-int-gpio parameter */ + }; + }; + }; + + // enable one or more mcp23s08s on spi1.0 + fragment@10 { + target = <&spi1>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s08_10: mcp23s08@0 { + compatible = "microchip,mcp23s08"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi1-0-present parameter */ + reg = <0>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi1-0-int-gpio parameter */ + }; + }; + }; + + // enable one or more mcp23s08s on spi1.1 + fragment@11 { + target = <&spi1>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s08_11: mcp23s08@1 { + compatible = "microchip,mcp23s08"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi1-1-present parameter */ + reg = <1>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi1-1-int-gpio parameter */ + }; + }; + }; + + // enable one or more mcp23s08s on spi1.2 + fragment@12 { + target = <&spi1>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s08_12: mcp23s08@2 { + compatible = "microchip,mcp23s08"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi1-2-present parameter */ + reg = <2>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi1-2-int-gpio parameter */ + }; + }; + }; + + // enable one or more mcp23s08s on spi2.0 + fragment@13 { + target = <&spi2>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s08_20: mcp23s08@0 { + compatible = "microchip,mcp23s08"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi2-0-present parameter */ + reg = <0>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi2-0-int-gpio parameter */ + }; + }; + }; + + // enable one or more mcp23s08s on spi2.1 + fragment@14 { + target = <&spi2>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s08_21: mcp23s08@1 { + compatible = "microchip,mcp23s08"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi2-1-present parameter */ + reg = <1>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi2-1-int-gpio parameter */ + }; + }; + }; + + // enable one or more mcp23s08s on spi2.2 + fragment@15 { + target = <&spi2>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s08_22: mcp23s08@2 { + compatible = "microchip,mcp23s08"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi2-2-present parameter */ + reg = <2>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi2-2-int-gpio parameter */ + }; + }; + }; + + // enable one or more mcp23s17s on spi0.0 + fragment@16 { + target = <&spi0>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s17_00: mcp23s17@0 { + compatible = "microchip,mcp23s17"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi0-0-present parameter */ + reg = <0>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi0-0-int-gpio parameter */ + }; + }; + }; + + // enable one or more mcp23s17s on spi0.1 + fragment@17 { + target = <&spi0>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s17_01: mcp23s17@1 { + compatible = "microchip,mcp23s17"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi0-1-present parameter */ + reg = <1>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi0-1-int-gpio parameter */ + }; + }; + }; + + // enable one or more mcp23s17s on spi1.0 + fragment@18 { + target = <&spi1>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s17_10: mcp23s17@0 { + compatible = "microchip,mcp23s17"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi1-0-present parameter */ + reg = <0>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi1-0-int-gpio parameter */ + }; + }; + }; + + // enable one or more mcp23s17s on spi1.1 + fragment@19 { + target = <&spi1>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s17_11: mcp23s17@1 { + compatible = "microchip,mcp23s17"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi1-1-present parameter */ + reg = <1>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi1-1-int-gpio parameter */ + }; + }; + }; + + // enable one or more mcp23s17s on spi1.2 + fragment@20 { + target = <&spi1>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s17_12: mcp23s17@2 { + compatible = "microchip,mcp23s17"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi1-2-present parameter */ + reg = <2>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi1-2-int-gpio parameter */ + }; + }; + }; + + // enable one or more mcp23s17s on spi2.0 + fragment@21 { + target = <&spi2>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s17_20: mcp23s17@0 { + compatible = "microchip,mcp23s17"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi2-0-present parameter */ + reg = <0>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi2-0-int-gpio parameter */ + }; + }; + }; + + // enable one or more mcp23s17s on spi2.1 + fragment@22 { + target = <&spi2>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s17_21: mcp23s17@1 { + compatible = "microchip,mcp23s17"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi2-1-present parameter */ + reg = <1>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi2-1-int-gpio parameter */ + }; + }; + }; + + // enable one or more mcp23s17s on spi2.2 + fragment@23 { + target = <&spi2>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp23s17_22: mcp23s17@2 { + compatible = "microchip,mcp23s17"; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi2-2-present parameter */ + reg = <2>; + spi-max-frequency = <500000>; + status = "okay"; + #interrupt-cells=<2>; + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi2-2-int-gpio parameter */ + }; + }; + }; + + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi0.0 as a input with no pull-up/down + fragment@24 { + target = <&gpio>; + __dormant__ { + spi0_0_int_pins: spi0_0_int_pins { + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi0-0-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi0.1 as a input with no pull-up/down + fragment@25 { + target = <&gpio>; + __dormant__ { + spi0_1_int_pins: spi0_1_int_pins { + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi0-1-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi1.0 as a input with no pull-up/down + fragment@26 { + target = <&gpio>; + __dormant__ { + spi1_0_int_pins: spi1_0_int_pins { + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi1-0-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi1.1 as a input with no pull-up/down + fragment@27 { + target = <&gpio>; + __dormant__ { + spi1_1_int_pins: spi1_1_int_pins { + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi1-1-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi1.2 as a input with no pull-up/down + fragment@28 { + target = <&gpio>; + __dormant__ { + spi1_2_int_pins: spi1_2_int_pins { + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi1-2-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi2.0 as a input with no pull-up/down + fragment@29 { + target = <&gpio>; + __dormant__ { + spi2_0_int_pins: spi2_0_int_pins { + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi2-0-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi2.1 as a input with no pull-up/down + fragment@30 { + target = <&gpio>; + __dormant__ { + spi2_1_int_pins: spi2_1_int_pins { + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi2-1-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi2.2 as a input with no pull-up/down + fragment@31 { + target = <&gpio>; + __dormant__ { + spi2_2_int_pins: spi2_2_int_pins { + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi2-2-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Enable interrupts for a mcp23s08 on spi0.0. + // Use default active low interrupt signalling. + fragment@32 { + target = <&mcp23s08_00>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + }; + }; + + // Enable interrupts for a mcp23s08 on spi0.1. + // Use default active low interrupt signalling. + fragment@33 { + target = <&mcp23s08_01>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + }; + }; + + // Enable interrupts for a mcp23s08 on spi1.0. + // Use default active low interrupt signalling. + fragment@34 { + target = <&mcp23s08_10>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + }; + }; + + // Enable interrupts for a mcp23s08 on spi1.1. + // Use default active low interrupt signalling. + fragment@35 { + target = <&mcp23s08_11>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + }; + }; + + // Enable interrupts for a mcp23s08 on spi1.2. + // Use default active low interrupt signalling. + fragment@36 { + target = <&mcp23s08_12>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + }; + }; + + // Enable interrupts for a mcp23s08 on spi2.0. + // Use default active low interrupt signalling. + fragment@37 { + target = <&mcp23s08_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + }; + }; + + // Enable interrupts for a mcp23s08 on spi2.1. + // Use default active low interrupt signalling. + fragment@38 { + target = <&mcp23s08_21>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + }; + }; + + // Enable interrupts for a mcp23s08 on spi2.2. + // Use default active low interrupt signalling. + fragment@39 { + target = <&mcp23s08_22>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + }; + }; + + // Enable interrupts for a mcp23s17 on spi0.0. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin. + // Use default active low interrupt signalling. + fragment@40 { + target = <&mcp23s17_00>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + microchip,irq-mirror; + }; + }; + + // Enable interrupts for a mcp23s17 on spi0.1. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin. + // Configure INTA/B outputs of mcp23s08/17 as active low. + fragment@41 { + target = <&mcp23s17_01>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + microchip,irq-mirror; + }; + }; + + // Enable interrupts for a mcp23s17 on spi1.0. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin. + // Configure INTA/B outputs of mcp23s08/17 as active low. + fragment@42 { + target = <&mcp23s17_10>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + microchip,irq-mirror; + }; + }; + + // Enable interrupts for a mcp23s17 on spi1.1. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin. + // Configure INTA/B outputs of mcp23s08/17 as active low. + fragment@43 { + target = <&mcp23s17_11>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + microchip,irq-mirror; + }; + }; + + // Enable interrupts for a mcp23s17 on spi1.2. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin. + // Configure INTA/B outputs of mcp23s08/17 as active low. + fragment@44 { + target = <&mcp23s17_12>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + microchip,irq-mirror; + }; + }; + + // Enable interrupts for a mcp23s17 on spi2.0. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin. + // Configure INTA/B outputs of mcp23s08/17 as active low. + fragment@45 { + target = <&mcp23s17_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + microchip,irq-mirror; + }; + }; + + // Enable interrupts for a mcp23s17 on spi2.1. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin. + // Configure INTA/B outputs of mcp23s08/17 as active low. + fragment@46 { + target = <&mcp23s17_21>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + microchip,irq-mirror; + }; + }; + + // Enable interrupts for a mcp23s17 on spi2.2. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin. + // Configure INTA/B outputs of mcp23s08/17 as active low. + fragment@47 { + target = <&mcp23s17_22>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + microchip,irq-mirror; + }; + }; + + __overrides__ { + s08-spi0-0-present = <0>,"+0+8", <&mcp23s08_00>,"microchip,spi-present-mask:0"; + s08-spi0-1-present = <0>,"+1+9", <&mcp23s08_01>,"microchip,spi-present-mask:0"; + s08-spi1-0-present = <0>,"+2+10", <&mcp23s08_10>,"microchip,spi-present-mask:0"; + s08-spi1-1-present = <0>,"+3+11", <&mcp23s08_11>,"microchip,spi-present-mask:0"; + s08-spi1-2-present = <0>,"+4+12", <&mcp23s08_12>,"microchip,spi-present-mask:0"; + s08-spi2-0-present = <0>,"+5+13", <&mcp23s08_20>,"microchip,spi-present-mask:0"; + s08-spi2-1-present = <0>,"+6+14", <&mcp23s08_21>,"microchip,spi-present-mask:0"; + s08-spi2-2-present = <0>,"+7+15", <&mcp23s08_22>,"microchip,spi-present-mask:0"; + s17-spi0-0-present = <0>,"+0+16", <&mcp23s17_00>,"microchip,spi-present-mask:0"; + s17-spi0-1-present = <0>,"+1+17", <&mcp23s17_01>,"microchip,spi-present-mask:0"; + s17-spi1-0-present = <0>,"+2+18", <&mcp23s17_10>,"microchip,spi-present-mask:0"; + s17-spi1-1-present = <0>,"+3+19", <&mcp23s17_11>,"microchip,spi-present-mask:0"; + s17-spi1-2-present = <0>,"+4+20", <&mcp23s17_12>,"microchip,spi-present-mask:0"; + s17-spi2-0-present = <0>,"+5+21", <&mcp23s17_20>,"microchip,spi-present-mask:0"; + s17-spi2-1-present = <0>,"+6+22", <&mcp23s17_21>,"microchip,spi-present-mask:0"; + s17-spi2-2-present = <0>,"+7+23", <&mcp23s17_22>,"microchip,spi-present-mask:0"; + s08-spi0-0-int-gpio = <0>,"+24+32", <&spi0_0_int_pins>,"brcm,pins:0", <&mcp23s08_00>,"interrupts:0"; + s08-spi0-1-int-gpio = <0>,"+25+33", <&spi0_1_int_pins>,"brcm,pins:0", <&mcp23s08_01>,"interrupts:0"; + s08-spi1-0-int-gpio = <0>,"+26+34", <&spi1_0_int_pins>,"brcm,pins:0", <&mcp23s08_10>,"interrupts:0"; + s08-spi1-1-int-gpio = <0>,"+27+35", <&spi1_1_int_pins>,"brcm,pins:0", <&mcp23s08_11>,"interrupts:0"; + s08-spi1-2-int-gpio = <0>,"+28+36", <&spi1_2_int_pins>,"brcm,pins:0", <&mcp23s08_12>,"interrupts:0"; + s08-spi2-0-int-gpio = <0>,"+29+37", <&spi2_0_int_pins>,"brcm,pins:0", <&mcp23s08_20>,"interrupts:0"; + s08-spi2-1-int-gpio = <0>,"+30+38", <&spi2_1_int_pins>,"brcm,pins:0", <&mcp23s08_21>,"interrupts:0"; + s08-spi2-2-int-gpio = <0>,"+31+39", <&spi2_2_int_pins>,"brcm,pins:0", <&mcp23s08_22>,"interrupts:0"; + s17-spi0-0-int-gpio = <0>,"+24+40", <&spi0_0_int_pins>,"brcm,pins:0", <&mcp23s17_00>,"interrupts:0"; + s17-spi0-1-int-gpio = <0>,"+25+41", <&spi0_1_int_pins>,"brcm,pins:0", <&mcp23s17_01>,"interrupts:0"; + s17-spi1-0-int-gpio = <0>,"+26+42", <&spi1_0_int_pins>,"brcm,pins:0", <&mcp23s17_10>,"interrupts:0"; + s17-spi1-1-int-gpio = <0>,"+27+43", <&spi1_1_int_pins>,"brcm,pins:0", <&mcp23s17_11>,"interrupts:0"; + s17-spi1-2-int-gpio = <0>,"+28+44", <&spi1_2_int_pins>,"brcm,pins:0", <&mcp23s17_12>,"interrupts:0"; + s17-spi2-0-int-gpio = <0>,"+29+45", <&spi2_0_int_pins>,"brcm,pins:0", <&mcp23s17_20>,"interrupts:0"; + s17-spi2-1-int-gpio = <0>,"+30+46", <&spi2_1_int_pins>,"brcm,pins:0", <&mcp23s17_21>,"interrupts:0"; + s17-spi2-2-int-gpio = <0>,"+31+47", <&spi2_2_int_pins>,"brcm,pins:0", <&mcp23s17_22>,"interrupts:0"; + }; +}; + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts linux/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts 2023-12-13 11:50:48.609961297 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device tree overlay for mcp251x/can0 on spi0.0 + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + /* disable spi-dev for spi0.0 */ + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + /* the interrupt pin of the can-controller */ + fragment@2 { + target = <&gpio>; + __overlay__ { + can0_pins: can0_pins { + brcm,pins = <25>; + brcm,function = <0>; /* input */ + }; + }; + }; + + /* the clock/oscillator of the can-controller */ + fragment@3 { + target-path = "/"; + __overlay__ { + /* external oscillator of mcp2515 on SPI0.0 */ + can0_osc: can0_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + }; + }; + + /* the spi config of the can-controller itself binding everything together */ + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + can0: mcp2515@0 { + reg = <0>; + compatible = "microchip,mcp2515"; + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins>; + spi-max-frequency = <10000000>; + interrupt-parent = <&gpio>; + interrupts = <25 8>; /* IRQ_TYPE_LEVEL_LOW */ + clocks = <&can0_osc>; + }; + }; + }; + __overrides__ { + oscillator = <&can0_osc>,"clock-frequency:0"; + spimaxfrequency = <&can0>,"spi-max-frequency:0"; + interrupt = <&can0_pins>,"brcm,pins:0",<&can0>,"interrupts:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts linux/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts 2023-12-13 11:50:48.609961297 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device tree overlay for mcp251x/can1 on spi0.1 edited by petit_miner + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + /* disable spi-dev for spi0.1 */ + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + /* the interrupt pin of the can-controller */ + fragment@2 { + target = <&gpio>; + __overlay__ { + can1_pins: can1_pins { + brcm,pins = <25>; + brcm,function = <0>; /* input */ + }; + }; + }; + + /* the clock/oscillator of the can-controller */ + fragment@3 { + target-path = "/"; + __overlay__ { + /* external oscillator of mcp2515 on spi0.1 */ + can1_osc: can1_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + }; + }; + + /* the spi config of the can-controller itself binding everything together */ + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + can1: mcp2515@1 { + reg = <1>; + compatible = "microchip,mcp2515"; + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins>; + spi-max-frequency = <10000000>; + interrupt-parent = <&gpio>; + interrupts = <25 8>; /* IRQ_TYPE_LEVEL_LOW */ + clocks = <&can1_osc>; + }; + }; + }; + __overrides__ { + oscillator = <&can1_osc>,"clock-frequency:0"; + spimaxfrequency = <&can1>,"spi-max-frequency:0"; + interrupt = <&can1_pins>,"brcm,pins:0",<&can1>,"interrupts:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/mcp2515-overlay.dts linux/arch/arm/boot/dts/overlays/mcp2515-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/mcp2515-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/mcp2515-overlay.dts 2023-12-13 11:50:48.609961297 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/bcm2835.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&spidev1>; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@2 { + target-path = "spi1/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@3 { + target-path = "spi1/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@4 { + target-path = "spi1/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@5 { + target-path = "spi2/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@6 { + target-path = "spi2/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@7 { + target-path = "spi2/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@8 { + target = <&gpio>; + __overlay__ { + mcp2515_pins: mcp2515_pins { + brcm,pins = <25>; + brcm,function = <BCM2835_FSEL_GPIO_IN>; + }; + }; + }; + + fragment@9 { + target-path = "/clocks"; + __overlay__ { + clk_mcp2515_osc: mcp2515-osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + }; + }; + }; + + mcp2515_frag: fragment@10 { + target = <&spi0>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp2515: mcp2515@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp2515_pins>; + spi-max-frequency = <10000000>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk_mcp2515_osc>; + }; + }; + }; + + __overrides__ { + spi0-0 = <0>, "+0", + <&mcp2515_frag>, "target:0=", <&spi0>, + <&mcp2515>, "reg:0=0", + <&mcp2515_pins>, "name=mcp2515_spi0_0_pins", + <&clk_mcp2515_osc>, "name=mcp2515-spi0-0-osc"; + spi0-1 = <0>, "+1", + <&mcp2515_frag>, "target:0=", <&spi0>, + <&mcp2515>, "reg:0=1", + <&mcp2515_pins>, "name=mcp2515_spi0_1_pins", + <&clk_mcp2515_osc>, "name=mcp2515-spi0-1-osc"; + spi1-0 = <0>, "+2", + <&mcp2515_frag>, "target:0=", <&spi1>, + <&mcp2515>, "reg:0=0", + <&mcp2515_pins>, "name=mcp2515_spi1_0_pins", + <&clk_mcp2515_osc>, "name=mcp2515-spi1-0-osc"; + spi1-1 = <0>, "+3", + <&mcp2515_frag>, "target:0=", <&spi1>, + <&mcp2515>, "reg:0=1", + <&mcp2515_pins>, "name=mcp2515_spi1_1_pins", + <&clk_mcp2515_osc>, "name=mcp2515-spi1-1-osc"; + spi1-2 = <0>, "+4", + <&mcp2515_frag>, "target:0=", <&spi1>, + <&mcp2515>, "reg:0=2", + <&mcp2515_pins>, "name=mcp2515_spi1_2_pins", + <&clk_mcp2515_osc>, "name=mcp2515-spi1-2-osc"; + spi2-0 = <0>, "+5", + <&mcp2515_frag>, "target:0=", <&spi2>, + <&mcp2515>, "reg:0=0", + <&mcp2515_pins>, "name=mcp2515_spi2_0_pins", + <&clk_mcp2515_osc>, "name=mcp2515-spi2-0-osc"; + spi2-1 = <0>, "+6", + <&mcp2515_frag>, "target:0=", <&spi2>, + <&mcp2515>, "reg:0=1", + <&mcp2515_pins>, "name=mcp2515_spi2_1_pins", + <&clk_mcp2515_osc>, "name=mcp2515-spi2-1-osc"; + spi2-2 = <0>, "+7", + <&mcp2515_frag>, "target:0=", <&spi2>, + <&mcp2515>, "reg:0=2", + <&mcp2515_pins>, "name=mcp2515_spi2_2_pins", + <&clk_mcp2515_osc>, "name=mcp2515-spi2-2-osc"; + oscillator = <&clk_mcp2515_osc>, "clock-frequency:0"; + speed = <&mcp2515>, "spi-max-frequency:0"; + interrupt = <&mcp2515_pins>, "brcm,pins:0", + <&mcp2515>, "interrupts:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/mcp251xfd-overlay.dts linux/arch/arm/boot/dts/overlays/mcp251xfd-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/mcp251xfd-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/mcp251xfd-overlay.dts 2023-12-13 11:50:48.609961297 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/bcm2835.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&spidev1>; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@2 { + target-path = "spi1/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@3 { + target-path = "spi1/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@4 { + target-path = "spi1/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@5 { + target-path = "spi2/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@6 { + target-path = "spi2/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@7 { + target-path = "spi2/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@8 { + target = <&gpio>; + __overlay__ { + mcp251xfd_pins: mcp251xfd_pins { + brcm,pins = <25>; + brcm,function = <BCM2835_FSEL_GPIO_IN>; + }; + }; + }; + + fragment@9 { + target-path = "/clocks"; + __overlay__ { + clk_mcp251xfd_osc: mcp251xfd-osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + }; + }; + + mcp251xfd_frag: fragment@10 { + target = <&spi0>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp251xfd: mcp251xfd@0 { + compatible = "microchip,mcp251xfd"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp251xfd_pins>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk_mcp251xfd_osc>; + }; + }; + }; + + fragment@11 { + target = <&mcp251xfd>; + mcp251xfd_rx_int_gpios: __dormant__ { + microchip,rx-int-gpios = <&gpio 255 GPIO_ACTIVE_LOW>; + }; + }; + + fragment@12 { + target = <&gpio>; + __dormant__ { + mcp251xfd_xceiver_pins: mcp251xfd_xceiver_pins { + brcm,pins = <255>; + brcm,function = <BCM2835_FSEL_GPIO_OUT>; + }; + }; + }; + + fragment@13 { + target-path = "/"; + __dormant__ { + reg_mcp251xfd_xceiver: reg_mcp251xfd_xceiver { + compatible = "regulator-fixed"; + regulator-name = "mcp251xfd_xceiver"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp251xfd_xceiver_pins>; + }; + }; + }; + + fragment@14 { + target = <&mcp251xfd>; + __dormant__ { + xceiver-supply = <®_mcp251xfd_xceiver>; + }; + }; + + __overrides__ { + spi0-0 = <0>, "+0", + <&mcp251xfd_frag>, "target:0=", <&spi0>, + <&mcp251xfd>, "reg:0=0", + <&mcp251xfd_pins>, "name=mcp251xfd_spi0_0_pins", + <&clk_mcp251xfd_osc>, "name=mcp251xfd-spi0-0-osc", + <&mcp251xfd_xceiver_pins>, "name=mcp251xfd_spi0_0_xceiver_pins", + <®_mcp251xfd_xceiver>, "name=reg-mcp251xfd-spi0-0-xceiver", + <®_mcp251xfd_xceiver>, "regulator-name=mcp251xfd-spi0-0-xceiver"; + spi0-1 = <0>, "+1", + <&mcp251xfd_frag>, "target:0=", <&spi0>, + <&mcp251xfd>, "reg:0=1", + <&mcp251xfd_pins>, "name=mcp251xfd_spi0_1_pins", + <&clk_mcp251xfd_osc>, "name=mcp251xfd-spi0-1-osc", + <&mcp251xfd_xceiver_pins>, "name=mcp251xfd_spi0_1_xceiver_pins", + <®_mcp251xfd_xceiver>, "name=reg-mcp251xfd-spi0-1-xceiver", + <®_mcp251xfd_xceiver>, "regulator-name=mcp251xfd-spi0-1-xceiver"; + spi1-0 = <0>, "+2", + <&mcp251xfd_frag>, "target:0=", <&spi1>, + <&mcp251xfd>, "reg:0=0", + <&mcp251xfd_pins>, "name=mcp251xfd_spi1_0_pins", + <&clk_mcp251xfd_osc>, "name=mcp251xfd-spi1-0-osc", + <&mcp251xfd_xceiver_pins>, "name=mcp251xfd_spi1_0_xceiver_pins", + <®_mcp251xfd_xceiver>, "name=reg-mcp251xfd-spi1-0-xceiver", + <®_mcp251xfd_xceiver>, "regulator-name=mcp251xfd-spi1-0-xceiver"; + spi1-1 = <0>, "+3", + <&mcp251xfd_frag>, "target:0=", <&spi1>, + <&mcp251xfd>, "reg:0=1", + <&mcp251xfd_pins>, "name=mcp251xfd_spi1_1_pins", + <&clk_mcp251xfd_osc>, "name=mcp251xfd-spi1-1-osc", + <&mcp251xfd_xceiver_pins>, "name=mcp251xfd_spi1_1_xceiver_pins", + <®_mcp251xfd_xceiver>, "name=reg-mcp251xfd-spi1-1-xceiver", + <®_mcp251xfd_xceiver>, "regulator-name=mcp251xfd-spi1-1-xceiver"; + spi1-2 = <0>, "+4", + <&mcp251xfd_frag>, "target:0=", <&spi1>, + <&mcp251xfd>, "reg:0=2", + <&mcp251xfd_pins>, "name=mcp251xfd_spi1_2_pins", + <&clk_mcp251xfd_osc>, "name=mcp251xfd-spi1-2-osc", + <&mcp251xfd_xceiver_pins>, "name=mcp251xfd_spi1_2_xceiver_pins", + <®_mcp251xfd_xceiver>, "name=reg-mcp251xfd-spi1-2-xceiver", + <®_mcp251xfd_xceiver>, "regulator-name=mcp251xfd-spi1-2-xceiver"; + spi2-0 = <0>, "+5", + <&mcp251xfd_frag>, "target:0=", <&spi2>, + <&mcp251xfd>, "reg:0=0", + <&mcp251xfd_pins>, "name=mcp251xfd_spi2_0_pins", + <&clk_mcp251xfd_osc>, "name=mcp251xfd-spi2-0-osc", + <&mcp251xfd_xceiver_pins>, "name=mcp251xfd_spi2_0_xceiver_pins", + <®_mcp251xfd_xceiver>, "name=reg-mcp251xfd-spi2-0-xceiver", + <®_mcp251xfd_xceiver>, "regulator-name=mcp251xfd-spi2-0-xceiver"; + spi2-1 = <0>, "+6", + <&mcp251xfd_frag>, "target:0=", <&spi2>, + <&mcp251xfd>, "reg:0=1", + <&mcp251xfd_pins>, "name=mcp251xfd_spi2_1_pins", + <&clk_mcp251xfd_osc>, "name=mcp251xfd-spi2-1-osc", + <&mcp251xfd_xceiver_pins>, "name=mcp251xfd_spi2_1_xceiver_pins", + <®_mcp251xfd_xceiver>, "name=reg-mcp251xfd-spi2-1-xceiver", + <®_mcp251xfd_xceiver>, "regulator-name=mcp251xfd-spi2-1-xceiver"; + spi2-2 = <0>, "+7", + <&mcp251xfd_frag>, "target:0=", <&spi2>, + <&mcp251xfd>, "reg:0=2", + <&mcp251xfd_pins>, "name=mcp251xfd_spi2_2_pins", + <&clk_mcp251xfd_osc>, "name=mcp251xfd-spi2-2-osc", + <&mcp251xfd_xceiver_pins>, "name=mcp251xfd_spi2_2_xceiver_pins", + <®_mcp251xfd_xceiver>, "name=reg-mcp251xfd-spi2-2-xceiver", + <®_mcp251xfd_xceiver>, "regulator-name=mcp251xfd-spi2-2-xceiver"; + oscillator = <&clk_mcp251xfd_osc>, "clock-frequency:0"; + speed = <&mcp251xfd>, "spi-max-frequency:0"; + interrupt = <&mcp251xfd_pins>, "brcm,pins:0", + <&mcp251xfd>, "interrupts:0"; + rx_interrupt = <0>, "+11", + <&mcp251xfd_pins>, "brcm,pins:4", + <&mcp251xfd_rx_int_gpios>, "microchip,rx-int-gpios:4"; + xceiver_enable = <0>, "+12+13+14", + <&mcp251xfd_xceiver_pins>, "brcm,pins:0", + <®_mcp251xfd_xceiver>, "gpio:4"; + xceiver_active_high = <®_mcp251xfd_xceiver>, "enable-active-high?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/mcp3008-overlay.dts linux/arch/arm/boot/dts/overlays/mcp3008-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/mcp3008-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/mcp3008-overlay.dts 2023-12-13 11:50:48.610961299 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device tree overlay for Microchip mcp3008 10-Bit A/D Converters + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&spidev1>; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@2 { + target-path = "spi1/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@3 { + target-path = "spi1/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@4 { + target-path = "spi1/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@5 { + target-path = "spi2/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@6 { + target-path = "spi2/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@7 { + target-path = "spi2/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@8 { + target = <&spi0>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3008_00: mcp3008@0 { + compatible = "microchip,mcp3008"; + reg = <0>; + spi-max-frequency = <1600000>; + }; + }; + }; + + fragment@9 { + target = <&spi0>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3008_01: mcp3008@1 { + compatible = "microchip,mcp3008"; + reg = <1>; + spi-max-frequency = <1600000>; + }; + }; + }; + + fragment@10 { + target = <&spi1>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3008_10: mcp3008@0 { + compatible = "microchip,mcp3008"; + reg = <0>; + spi-max-frequency = <1600000>; + }; + }; + }; + + fragment@11 { + target = <&spi1>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3008_11: mcp3008@1 { + compatible = "microchip,mcp3008"; + reg = <1>; + spi-max-frequency = <1600000>; + }; + }; + }; + + fragment@12 { + target = <&spi1>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3008_12: mcp3008@2 { + compatible = "microchip,mcp3008"; + reg = <2>; + spi-max-frequency = <1600000>; + }; + }; + }; + + fragment@13 { + target = <&spi2>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3008_20: mcp3008@0 { + compatible = "microchip,mcp3008"; + reg = <0>; + spi-max-frequency = <1600000>; + }; + }; + }; + + fragment@14 { + target = <&spi2>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3008_21: mcp3008@1 { + compatible = "microchip,mcp3008"; + reg = <1>; + spi-max-frequency = <1600000>; + }; + }; + }; + + fragment@15 { + target = <&spi2>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3008_22: mcp3008@2 { + compatible = "microchip,mcp3008"; + reg = <2>; + spi-max-frequency = <1600000>; + }; + }; + }; + + __overrides__ { + spi0-0-present = <0>, "+0+8"; + spi0-1-present = <0>, "+1+9"; + spi1-0-present = <0>, "+2+10"; + spi1-1-present = <0>, "+3+11"; + spi1-2-present = <0>, "+4+12"; + spi2-0-present = <0>, "+5+13"; + spi2-1-present = <0>, "+6+14"; + spi2-2-present = <0>, "+7+15"; + spi0-0-speed = <&mcp3008_00>, "spi-max-frequency:0"; + spi0-1-speed = <&mcp3008_01>, "spi-max-frequency:0"; + spi1-0-speed = <&mcp3008_10>, "spi-max-frequency:0"; + spi1-1-speed = <&mcp3008_11>, "spi-max-frequency:0"; + spi1-2-speed = <&mcp3008_12>, "spi-max-frequency:0"; + spi2-0-speed = <&mcp3008_20>, "spi-max-frequency:0"; + spi2-1-speed = <&mcp3008_21>, "spi-max-frequency:0"; + spi2-2-speed = <&mcp3008_22>, "spi-max-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/mcp3202-overlay.dts linux/arch/arm/boot/dts/overlays/mcp3202-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/mcp3202-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/mcp3202-overlay.dts 2023-12-13 11:50:48.610961299 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device tree overlay for Microchip mcp3202 12-Bit A/D Converters + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&spidev1>; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@2 { + target-path = "spi1/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@3 { + target-path = "spi1/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@4 { + target-path = "spi1/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@5 { + target-path = "spi2/spidev@0"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@6 { + target-path = "spi2/spidev@1"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@7 { + target-path = "spi2/spidev@2"; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@8 { + target = <&spi0>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3202_00: mcp3202@0 { + compatible = "mcp3202"; + reg = <0>; + spi-max-frequency = <1600000>; + }; + }; + }; + + fragment@9 { + target = <&spi0>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3202_01: mcp3202@1 { + compatible = "mcp3202"; + reg = <1>; + spi-max-frequency = <1600000>; + }; + }; + }; + + fragment@10 { + target = <&spi1>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3202_10: mcp3202@0 { + compatible = "mcp3202"; + reg = <0>; + spi-max-frequency = <1600000>; + }; + }; + }; + + fragment@11 { + target = <&spi1>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3202_11: mcp3202@1 { + compatible = "mcp3202"; + reg = <1>; + spi-max-frequency = <1600000>; + }; + }; + }; + + fragment@12 { + target = <&spi1>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3202_12: mcp3202@2 { + compatible = "mcp3202"; + reg = <2>; + spi-max-frequency = <1600000>; + }; + }; + }; + + fragment@13 { + target = <&spi2>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3202_20: mcp3202@0 { + compatible = "mcp3202"; + reg = <0>; + spi-max-frequency = <1600000>; + }; + }; + }; + + fragment@14 { + target = <&spi2>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3202_21: mcp3202@1 { + compatible = "mcp3202"; + reg = <1>; + spi-max-frequency = <1600000>; + }; + }; + }; + + fragment@15 { + target = <&spi2>; + __dormant__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp3202_22: mcp3202@2 { + compatible = "mcp3202"; + reg = <2>; + spi-max-frequency = <1600000>; + }; + }; + }; + + __overrides__ { + spi0-0-present = <0>, "+0+8"; + spi0-1-present = <0>, "+1+9"; + spi1-0-present = <0>, "+2+10"; + spi1-1-present = <0>, "+3+11"; + spi1-2-present = <0>, "+4+12"; + spi2-0-present = <0>, "+5+13"; + spi2-1-present = <0>, "+6+14"; + spi2-2-present = <0>, "+7+15"; + spi0-0-speed = <&mcp3202_00>, "spi-max-frequency:0"; + spi0-1-speed = <&mcp3202_01>, "spi-max-frequency:0"; + spi1-0-speed = <&mcp3202_10>, "spi-max-frequency:0"; + spi1-1-speed = <&mcp3202_11>, "spi-max-frequency:0"; + spi1-2-speed = <&mcp3202_12>, "spi-max-frequency:0"; + spi2-0-speed = <&mcp3202_20>, "spi-max-frequency:0"; + spi2-1-speed = <&mcp3202_21>, "spi-max-frequency:0"; + spi2-2-speed = <&mcp3202_22>, "spi-max-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/mcp342x-overlay.dts linux/arch/arm/boot/dts/overlays/mcp342x-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/mcp342x-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/mcp342x-overlay.dts 2023-12-13 11:50:48.610961299 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for MCP3421-8 ADCs from Microchip Semiconductor + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + mcp3421: mcp@68 { + reg = <0x68>; + compatible = "microchip,mcp3421"; + + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + mcp3422: mcp@68 { + reg = <0x68>; + compatible = "microchip,mcp3422"; + + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + mcp3423: mcp@68 { + reg = <0x68>; + compatible = "microchip,mcp3423"; + + status = "okay"; + }; + }; + }; + + fragment@3 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + mcp3424: mcp@68 { + reg = <0x68>; + compatible = "microchip,mcp3424"; + + status = "okay"; + }; + }; + }; + + fragment@4 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + mcp3425: mcp@68 { + reg = <0x68>; + compatible = "microchip,mcp3425","mcp3425"; + + status = "okay"; + }; + }; + }; + + fragment@5 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + mcp3426: mcp@68 { + reg = <0x68>; + compatible = "microchip,mcp3426"; + + status = "okay"; + }; + }; + }; + + fragment@6 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + mcp3427: mcp@68 { + reg = <0x68>; + compatible = "microchip,mcp3427"; + + status = "okay"; + }; + }; + }; + + fragment@7 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + mcp3428: mcp@68 { + reg = <0x68>; + compatible = "microchip,mcp3428"; + + status = "okay"; + }; + }; + }; + + __overrides__ { + addr = <&mcp3421>,"reg:0", + <&mcp3422>,"reg:0", + <&mcp3423>,"reg:0", + <&mcp3424>,"reg:0", + <&mcp3425>,"reg:0", + <&mcp3426>,"reg:0", + <&mcp3427>,"reg:0", + <&mcp3428>,"reg:0"; + mcp3421 = <0>,"=0"; + mcp3422 = <0>,"=1"; + mcp3423 = <0>,"=2"; + mcp3424 = <0>,"=3"; + mcp3425 = <0>,"=4"; + mcp3426 = <0>,"=5"; + mcp3427 = <0>,"=6"; + mcp3428 = <0>,"=7"; + }; +}; + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/media-center-overlay.dts linux/arch/arm/boot/dts/overlays/media-center-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/media-center-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/media-center-overlay.dts 2023-12-13 11:50:48.610961299 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for Media Center HAT by Pi Supply + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + rpi_display_pins: rpi_display_pins { + brcm,pins = <12 23 24 25>; + brcm,function = <1 1 1 0>; /* out out out in */ + brcm,pull = <0 0 0 2>; /* - - - up */ + }; + }; + }; + + fragment@3 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + rpidisplay: rpi-display@0{ + compatible = "ilitek,ili9341"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_display_pins>; + + spi-max-frequency = <32000000>; + rotate = <90>; + bgr; + fps = <30>; + buswidth = <8>; + reset-gpios = <&gpio 23 1>; + dc-gpios = <&gpio 24 0>; + led-gpios = <&gpio 12 0>; + debug = <0>; + }; + + rpidisplay_ts: rpi-display-ts@1 { + compatible = "ti,ads7846"; + reg = <1>; + + spi-max-frequency = <2000000>; + interrupts = <25 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; + pendown-gpio = <&gpio 25 1>; + ti,x-plate-ohms = /bits/ 16 <60>; + ti,pressure-max = /bits/ 16 <255>; + }; + }; + }; + + __overrides__ { + speed = <&rpidisplay>,"spi-max-frequency:0"; + rotate = <&rpidisplay>,"rotate:0"; + fps = <&rpidisplay>,"fps:0"; + debug = <&rpidisplay>,"debug:0"; + xohms = <&rpidisplay_ts>,"ti,x-plate-ohms;0"; + swapxy = <&rpidisplay_ts>,"ti,swap-xy?"; + backlight = <&rpidisplay>,"led-gpios:4", + <&rpi_display_pins>,"brcm,pins:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/merus-amp-overlay.dts linux/arch/arm/boot/dts/overlays/merus-amp-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/merus-amp-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/merus-amp-overlay.dts 2023-12-13 11:50:48.610961299 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for Infineon Merus-Amp +/dts-v1/; +/plugin/; +#include <dt-bindings/pinctrl/bcm2835.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + merus_amp_pins: merus_amp_pins { + brcm,pins = <23 8>; + brcm,function = <0 0>; + brcm,pull = <2 0>; + }; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + merus_amp: ma120x0p@20 { + #sound-dai-cells = <0>; + compatible = "ma,ma120x0p"; + reg = <0x20>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&merus_amp_pins>; + enable_gp-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; + mute_gp-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + booster_gp-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + error_gp-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + }; + }; + }; + + fragment@3 { + target = <&sound>; + __overlay__ { + compatible = "merus,merus-amp"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart0-overlay.dts linux/arch/arm/boot/dts/overlays/midi-uart0-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart0-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/midi-uart0-overlay.dts 2023-12-13 11:50:48.610961299 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/bcm2835.h> + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower + * baudrate. The real clock is 48MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * + * 48000000*38400/31250 = 58982400 + */ + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + midi_clk: midi_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "uart0_pclk"; + clock-frequency = <58982400>; + }; + }; + }; + + fragment@1 { + target = <&uart0>; + __overlay__ { + clocks = <&midi_clk>, + <&clocks BCM2835_CLOCK_VPU>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart0-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/midi-uart0-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart0-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/midi-uart0-pi5-overlay.dts 2023-12-13 11:50:48.610961299 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/rp1.h> + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower + * baudrate. The real clock is 100MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * + * 100000000*38400/31250 = 122880000 + */ + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target-path = "/"; + __overlay__ { + midi_clk: midi_clk0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "uart0_pclk"; + clock-frequency = <122880000>; + }; + }; + }; + + fragment@1 { + target = <&uart0>; + __overlay__ { + clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart1-overlay.dts linux/arch/arm/boot/dts/overlays/midi-uart1-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart1-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/midi-uart1-overlay.dts 2023-12-13 11:50:48.611961301 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/bcm2835-aux.h> + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower + * baudrate. The real clock is 48MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * + * 48000000*38400/31250 = 58982400 + */ + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/clocks"; + __overlay__ { + midi_clk: clock@5 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&aux BCM2835_AUX_CLOCK_UART>; + clock-mult = <38400>; + clock-div = <31250>; + }; + }; + }; + + fragment@1 { + target = <&uart1>; + __overlay__ { + clocks = <&midi_clk>; + }; + }; + + fragment@2 { + target = <&aux>; + __overlay__ { + clock-output-names = "aux_uart", "aux_spi1", "aux_spi2"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart1-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/midi-uart1-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart1-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/midi-uart1-pi5-overlay.dts 2023-12-13 11:50:48.611961301 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/rp1.h> + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower + * baudrate. The real clock is 100MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * + * 100000000*38400/31250 = 122880000 + */ + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target-path = "/"; + __overlay__ { + midi_clk: midi_clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "uart1_pclk"; + clock-frequency = <122880000>; + }; + }; + }; + + fragment@1 { + target = <&uart1>; + __overlay__ { + clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart2-overlay.dts linux/arch/arm/boot/dts/overlays/midi-uart2-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart2-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/midi-uart2-overlay.dts 2023-12-13 11:50:48.611961301 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/bcm2835.h> + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower + * baudrate. The real clock is 48MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * + * 48000000*38400/31250 = 58982400 + */ + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + midi_clk: midi_clk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "uart2_pclk"; + clock-frequency = <58982400>; + }; + }; + }; + + fragment@1 { + target = <&uart2>; + __overlay__ { + clocks = <&midi_clk>, + <&clocks BCM2835_CLOCK_VPU>; + }; + }; +}; + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart2-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/midi-uart2-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart2-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/midi-uart2-pi5-overlay.dts 2023-12-13 11:50:48.611961301 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/rp1.h> + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower + * baudrate. The real clock is 100MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * + * 100000000*38400/31250 = 122880000 + */ + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target-path = "/"; + __overlay__ { + midi_clk: midi_clk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "uart2_pclk"; + clock-frequency = <122880000>; + }; + }; + }; + + fragment@1 { + target = <&uart2>; + __overlay__ { + clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart3-overlay.dts linux/arch/arm/boot/dts/overlays/midi-uart3-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart3-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/midi-uart3-overlay.dts 2023-12-13 11:50:48.611961301 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/bcm2835.h> + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower + * baudrate. The real clock is 48MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * + * 48000000*38400/31250 = 58982400 + */ + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + midi_clk: midi_clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "uart3_pclk"; + clock-frequency = <58982400>; + }; + }; + }; + + fragment@1 { + target = <&uart3>; + __overlay__ { + clocks = <&midi_clk>, + <&clocks BCM2835_CLOCK_VPU>; + }; + }; +}; + + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart3-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/midi-uart3-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart3-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/midi-uart3-pi5-overlay.dts 2023-12-13 11:50:48.611961301 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/rp1.h> + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower + * baudrate. The real clock is 100MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * + * 100000000*38400/31250 = 122880000 + */ + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target-path = "/"; + __overlay__ { + midi_clk: midi_clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "uart3_pclk"; + clock-frequency = <122880000>; + }; + }; + }; + + fragment@1 { + target = <&uart3>; + __overlay__ { + clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart4-overlay.dts linux/arch/arm/boot/dts/overlays/midi-uart4-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart4-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/midi-uart4-overlay.dts 2023-12-13 11:50:48.611961301 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/bcm2835.h> + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower + * baudrate. The real clock is 48MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * + * 48000000*38400/31250 = 58982400 + */ + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + midi_clk: midi_clk4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "uart4_pclk"; + clock-frequency = <58982400>; + }; + }; + }; + + fragment@1 { + target = <&uart4>; + __overlay__ { + clocks = <&midi_clk>, + <&clocks BCM2835_CLOCK_VPU>; + }; + }; +}; + + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart4-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/midi-uart4-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart4-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/midi-uart4-pi5-overlay.dts 2023-12-13 11:50:48.611961301 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/rp1.h> + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower + * baudrate. The real clock is 100MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * + * 100000000*38400/31250 = 122880000 + */ + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target-path = "/"; + __overlay__ { + midi_clk: midi_clk4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "uart4_pclk"; + clock-frequency = <122880000>; + }; + }; + }; + + fragment@1 { + target = <&uart4>; + __overlay__ { + clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart5-overlay.dts linux/arch/arm/boot/dts/overlays/midi-uart5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/midi-uart5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/midi-uart5-overlay.dts 2023-12-13 11:50:48.612961304 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/bcm2835.h> + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower + * baudrate. The real clock is 48MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * + * 48000000*38400/31250 = 58982400 + */ + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + midi_clk: midi_clk5 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "uart5_pclk"; + clock-frequency = <58982400>; + }; + }; + }; + + fragment@1 { + target = <&uart5>; + __overlay__ { + clocks = <&midi_clk>, + <&clocks BCM2835_CLOCK_VPU>; + }; + }; +}; + + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/minipitft13-overlay.dts linux/arch/arm/boot/dts/overlays/minipitft13-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/minipitft13-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/minipitft13-overlay.dts 2023-12-13 11:50:48.612961304 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for Adafruit Mini PiTFT 1.3" and 1.5" 240x240 Display + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + pitft_pins: pitft_pins { + brcm,pins = <25>; + brcm,function = <1>; /* out */ + brcm,pull = <0>; /* none */ + }; + }; + }; + + fragment@3 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pitft: pitft@0 { + compatible = "fbtft,minipitft13"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pitft_pins>; + spi-max-frequency = <32000000>; + rotate = <0>; + width = <240>; + height = <240>; + buswidth = <8>; + dc-gpios = <&gpio 25 0>; + led-gpios = <&gpio 26 0>; + debug = <0>; + }; + }; + }; + + __overrides__ { + speed = <&pitft>,"spi-max-frequency:0"; + rotate = <&pitft>,"rotate:0"; + width = <&pitft>,"width:0"; + height = <&pitft>,"height:0"; + fps = <&pitft>,"fps:0"; + debug = <&pitft>,"debug:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/miniuart-bt-overlay.dts linux/arch/arm/boot/dts/overlays/miniuart-bt-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/miniuart-bt-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/miniuart-bt-overlay.dts 2023-12-13 11:50:48.612961304 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/* Switch Pi3 Bluetooth function to use the mini-UART (ttyS0) and restore + UART0/ttyAMA0 over GPIOs 14 & 15. Note that this may reduce the maximum + usable baudrate. + + It is also necessary to edit /lib/systemd/system/hciuart.service and + replace ttyAMA0 with ttyS0, unless you have a system with udev rules + that create /dev/serial0 and /dev/serial1, in which case use /dev/serial1 + instead because it will always be correct. + + If cmdline.txt uses the alias serial0 to refer to the user-accessable port + then the firmware will replace with the appropriate port whether or not + this overlay is used. +*/ + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&uart0>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&bt>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&uart1>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; + }; + }; + + fragment@3 { + target = <&uart0_pins>; + __overlay__ { + brcm,pins; + brcm,function; + brcm,pull; + }; + }; + + fragment@4 { + target = <&uart1>; + __overlay__ { + pinctrl-0 = <&uart1_bt_pins>; + }; + }; + + fragment@5 { + target-path = "/aliases"; + __overlay__ { + serial0 = "/soc/serial@7e201000"; + serial1 = "/soc/serial@7e215040"; + bluetooth = "/soc/serial@7e215040/bluetooth"; + }; + }; + + fragment@6 { + target = <&minibt>; + minibt_frag: __overlay__ { + status = "okay"; + }; + }; + + __overrides__ { + krnbt = <&minibt_frag>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/mipi-dbi-spi-overlay.dts linux/arch/arm/boot/dts/overlays/mipi-dbi-spi-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/mipi-dbi-spi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/mipi-dbi-spi-overlay.dts 2023-12-13 11:50:48.612961304 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * mipi-dbi-spi-overlay.dts + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + spidev_fragment: fragment@0 { + target-path = "spi0/spidev@0"; + __overlay__ { + status = "disabled"; + }; + }; + + panel_fragment: fragment@1 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + panel: panel@0 { + compatible = "panel", "panel-mipi-dbi-spi"; + reg = <0>; + spi-max-frequency = <32000000>; + + width-mm = <0>; + height-mm = <0>; + + timing: panel-timing { + hactive = <320>; + vactive = <240>; + hback-porch = <0>; + vback-porch = <0>; + + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; + }; + }; + + fragment@10 { + target = <&panel>; + __dormant__ { + backlight = <&backlight_gpio>; + }; + }; + + fragment@11 { + target-path = "/"; + __dormant__ { + backlight_gpio: backlight_gpio { + compatible = "gpio-backlight"; + gpios = <&gpio 255 GPIO_ACTIVE_HIGH>; + }; + }; + }; + + fragment@20 { + target = <&panel>; + __dormant__ { + backlight = <&backlight_pwm>; + }; + }; + + fragment@21 { + target-path = "/"; + __dormant__ { + backlight_pwm: backlight_pwm { + compatible = "pwm-backlight"; + brightness-levels = <0 6 8 12 16 24 32 40 48 64 96 128 160 192 224 255>; + default-brightness-level = <15>; + pwms = <&pwm 0 200000>; + }; + }; + }; + + fragment@22 { + target = <&pwm>; + __dormant__ { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + assigned-clock-rates = <1000000>; + status = "okay"; + }; + }; + + fragment@23 { + target = <&gpio>; + __dormant__ { + pwm_pins: pwm_pins { + brcm,pins = <18>; + brcm,function = <2>; /* Alt5 */ + }; + }; + }; + + fragment@24 { + target = <&chosen>; + __dormant__ { + bootargs = "snd_bcm2835.enable_headphones=0"; + }; + }; + + __overrides__ { + compatible = <&panel>, "compatible"; + + spi0-0 = <&panel_fragment>, "target:0=",<&spi0>, + <&spidev_fragment>, "target-path=spi0/spidev@0", + <&panel>, "reg:0=0"; + spi0-1 = <&panel_fragment>, "target:0=",<&spi0>, + <&spidev_fragment>, "target-path=spi0/spidev@1", + <&panel>, "reg:0=1"; + spi1-0 = <&panel_fragment>, "target:0=",<&spi1>, + <&spidev_fragment>, "target-path=spi1/spidev@0", + <&panel>, "reg:0=0"; + spi1-1 = <&panel_fragment>, "target:0=",<&spi1>, + <&spidev_fragment>, "target-path=spi1/spidev@1", + <&panel>, "reg:0=1"; + spi1-2 = <&panel_fragment>, "target:0=",<&spi1>, + <&spidev_fragment>, "target-path=spi1/spidev@2", + <&panel>, "reg:0=2"; + spi2-0 = <&panel_fragment>, "target:0=",<&spi2>, + <&spidev_fragment>, "target-path=spi2/spidev@0", + <&panel>, "reg:0=0"; + spi2-1 = <&panel_fragment>, "target:0=",<&spi2>, + <&spidev_fragment>, "target-path=spi2/spidev@1", + <&panel>, "reg:0=1"; + spi2-2 = <&panel_fragment>, "target:0=",<&spi2>, + <&spidev_fragment>, "target-path=spi2/spidev@2", + <&panel>, "reg:0=2"; + + speed = <&panel>, "spi-max-frequency:0"; + cpha = <&panel>, "spi-cpha?"; + cpol = <&panel>, "spi-cpol?"; + + write-only = <&panel>, "write-only?"; + + width = <&timing>, "hactive:0"; + height = <&timing>, "vactive:0"; + x-offset = <&timing>, "hback-porch:0"; + y-offset = <&timing>, "vback-porch:0"; + clock-frequency = <&timing>, "clock-frequency:0"; + + width-mm = <&panel>, "width-mm:0"; + height-mm = <&panel>, "height-mm:0"; + + /* optional gpios */ + reset-gpio = <&panel>, "reset-gpios:0=", <&gpio>, + <&panel>, "reset-gpios:4", + <&panel>, "reset-gpios:8=0"; /* GPIO_ACTIVE_HIGH */ + dc-gpio = <&panel>, "dc-gpios:0=", <&gpio>, + <&panel>, "dc-gpios:4", + <&panel>, "dc-gpios:8=0"; /* GPIO_ACTIVE_HIGH */ + + backlight-gpio = <0>, "+10+11", + <&backlight_gpio>, "gpios:4"; + backlight-pwm = <0>, "+20+21+22+23+24"; + backlight-pwm-chan = <&backlight_pwm>, "pwms:4"; + backlight-pwm-gpio = <&pwm_pins>, "brcm,pins:0"; + backlight-pwm-func = <&pwm_pins>, "brcm,function:0"; + backlight-def-brightness = <&backlight_pwm>, "default-brightness-level:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/mlx90640-overlay.dts linux/arch/arm/boot/dts/overlays/mlx90640-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/mlx90640-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/mlx90640-overlay.dts 2023-12-13 11:50:48.612961304 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c_arm>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + clock-frequency = <400000>; + + mlx90640: mlx90640@33 { + compatible = "melexis,mlx90640"; + reg = <0x33>; + status = "okay"; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/mmc-overlay.dts linux/arch/arm/boot/dts/overlays/mmc-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/mmc-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/mmc-overlay.dts 2023-12-13 11:50:48.612961304 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&mmc>; + frag0: __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pins>; + bus-width = <4>; + brcm,overclock-50 = <0>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + mmc_pins: mmc_pins { + brcm,pins = <48 49 50 51 52 53>; + brcm,function = <7>; /* alt3 */ + brcm,pull = <0 2 2 2 2 2>; + }; + }; + }; + + fragment@2 { + target = <&sdhost>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&mmcnr>; + __overlay__ { + status = "disabled"; + }; + }; + + __overrides__ { + overclock_50 = <&frag0>,"brcm,overclock-50:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/mpu6050-overlay.dts linux/arch/arm/boot/dts/overlays/mpu6050-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/mpu6050-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/mpu6050-overlay.dts 2023-12-13 11:50:48.613961306 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for MPU6050 +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + clock-frequency = <400000>; + + mpu6050: mpu6050@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + interrupt-parent = <&gpio>; + interrupts = <4 1>; + }; + }; + }; + + __overrides__ { + interrupt = <&mpu6050>,"interrupts:0"; + addr = <&mpu6050>,"reg:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/mz61581-overlay.dts linux/arch/arm/boot/dts/overlays/mz61581-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/mz61581-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/mz61581-overlay.dts 2023-12-13 11:50:48.613961306 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for MZ61581-PI-EXT 2014.12.28 by Tontec + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + mz61581_pins: mz61581_pins { + brcm,pins = <4 15 18 25>; + brcm,function = <0 1 1 1>; /* in out out out */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + mz61581: mz61581@0{ + compatible = "samsung,s6d02a1"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mz61581_pins>; + + spi-max-frequency = <128000000>; + spi-cpol; + spi-cpha; + + width = <320>; + height = <480>; + rotate = <270>; + bgr; + fps = <30>; + buswidth = <8>; + txbuflen = <32768>; + + reset-gpios = <&gpio 15 1>; + dc-gpios = <&gpio 25 0>; + led-gpios = <&gpio 18 0>; + + init = <0x10000b0 00 + 0x1000011 + 0x20000ff + 0x10000b3 0x02 0x00 0x00 0x00 + 0x10000c0 0x13 0x3b 0x00 0x02 0x00 0x01 0x00 0x43 + 0x10000c1 0x08 0x16 0x08 0x08 + 0x10000c4 0x11 0x07 0x03 0x03 + 0x10000c6 0x00 + 0x10000c8 0x03 0x03 0x13 0x5c 0x03 0x07 0x14 0x08 0x00 0x21 0x08 0x14 0x07 0x53 0x0c 0x13 0x03 0x03 0x21 0x00 + 0x1000035 0x00 + 0x1000036 0xa0 + 0x100003a 0x55 + 0x1000044 0x00 0x01 + 0x10000d0 0x07 0x07 0x1d 0x03 + 0x10000d1 0x03 0x30 0x10 + 0x10000d2 0x03 0x14 0x04 + 0x1000029 + 0x100002c>; + + /* This is a workaround to make sure the init sequence slows down and doesn't fail */ + debug = <3>; + }; + + mz61581_ts: mz61581_ts@1 { + compatible = "ti,ads7846"; + reg = <1>; + + spi-max-frequency = <2000000>; + interrupts = <4 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; + pendown-gpio = <&gpio 4 0>; + + ti,x-plate-ohms = /bits/ 16 <60>; + ti,pressure-max = /bits/ 16 <255>; + }; + }; + }; + __overrides__ { + speed = <&mz61581>, "spi-max-frequency:0"; + rotate = <&mz61581>, "rotate:0"; + fps = <&mz61581>, "fps:0"; + txbuflen = <&mz61581>, "txbuflen:0"; + debug = <&mz61581>, "debug:0"; + xohms = <&mz61581_ts>,"ti,x-plate-ohms;0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ov2311.dtsi linux/arch/arm/boot/dts/overlays/ov2311.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/ov2311.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ov2311.dtsi 2023-12-13 11:50:48.613961306 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Fragment that configures an ov2311 + +cam_node: ov2311@60 { + compatible = "ovti,ov2311"; + reg = <0x60>; + status = "disabled"; + + clocks = <&cam1_clk>; + clock-names = "xvclk"; + + avdd-supply = <&cam1_reg>; + dovdd-supply = <&cam_dummy_reg>; + dvdd-supply = <&cam_dummy_reg>; + + rotation = <0>; + orientation = <2>; + + port { + cam_endpoint: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = + /bits/ 64 <400000000>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ov2311-overlay.dts linux/arch/arm/boot/dts/overlays/ov2311-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ov2311-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ov2311-overlay.dts 2023-12-13 11:50:48.613961306 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for OV2311 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2835"; + + i2c_frag: fragment@0 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + #include "ov2311.dtsi" + }; + }; + + csi_frag: fragment@1 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + brcm,media-controller; + + port { + csi_ep: endpoint { + remote-endpoint = <&cam_endpoint>; + data-lanes = <1 2>; + }; + }; + }; + }; + + fragment@2 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + clk_frag: fragment@4{ + target = <&cam1_clk>; + __overlay__ { + status = "okay"; + clock-frequency = <24000000>; + }; + }; + + __overrides__ { + rotation = <&cam_node>,"rotation:0"; + orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <&cam_node>, "clocks:0=",<&cam0_clk>, + <&cam_node>, "avdd-supply:0=",<&cam0_reg>; + }; +}; + +&cam_node { + status = "okay"; +}; + +&cam_endpoint { + remote-endpoint = <&csi_ep>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ov5647.dtsi linux/arch/arm/boot/dts/overlays/ov5647.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/ov5647.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ov5647.dtsi 2023-12-13 11:50:48.613961306 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +cam_node: ov5647@36 { + compatible = "ovti,ov5647"; + reg = <0x36>; + status = "disabled"; + + clocks = <&cam1_clk>; + + avdd-supply = <&cam1_reg>; + dovdd-supply = <&cam_dummy_reg>; + dvdd-supply = <&cam_dummy_reg>; + + rotation = <0>; + orientation = <2>; + + port { + cam_endpoint: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <297000000>; + }; + }; +}; + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ov5647-overlay.dts linux/arch/arm/boot/dts/overlays/ov5647-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ov5647-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ov5647-overlay.dts 2023-12-13 11:50:48.613961306 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for OV5647 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + i2c_frag: fragment@0 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + #include "ov5647.dtsi" + + vcm_node: ad5398@c { + compatible = "adi,ad5398"; + reg = <0x0c>; + status = "disabled"; + VANA-supply = <&cam1_reg>; + }; + }; + }; + + csi_frag: fragment@1 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + brcm,media-controller; + + port { + csi_ep: endpoint { + remote-endpoint = <&cam_endpoint>; + data-lanes = <1 2>; + }; + }; + }; + }; + + fragment@2 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + reg_frag: fragment@4 { + target = <&cam1_reg>; + __overlay__ { + startup-delay-us = <20000>; + }; + }; + + clk_frag: fragment@5 { + target = <&cam1_clk>; + __overlay__ { + status = "okay"; + clock-frequency = <25000000>; + }; + }; + + __overrides__ { + rotation = <&cam_node>,"rotation:0"; + orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <®_frag>, "target:0=",<&cam0_reg>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <&cam_node>, "clocks:0=",<&cam0_clk>, + <&cam_node>, "avdd-supply:0=",<&cam0_reg>, + <&vcm_node>, "VANA-supply:0=",<&cam0_reg>; + vcm = <&vcm_node>, "status=okay", + <&cam_node>,"lens-focus:0=", <&vcm_node>; + }; +}; + +&cam_node { + status = "okay"; +}; + +&cam_endpoint { + remote-endpoint = <&csi_ep>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ov64a40.dtsi linux/arch/arm/boot/dts/overlays/ov64a40.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/ov64a40.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ov64a40.dtsi 2023-12-13 11:50:48.614961308 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Fragment that configures an OV64A40 + +cam_node: ov64a40@36 { + compatible = "ovti,ov64a40"; + reg = <0x36>; + status = "disabled"; + + clocks = <&cam1_clk>; + clock-names = "xclk"; + + avdd-supply = <&cam1_reg>; /* 2.8v */ + dovdd-supply = <&cam_dummy_reg>;/* 1.8v */ + dvdd-supply = <&cam_dummy_reg>; /* 1.1v */ + + rotation = <180>; + orientation = <2>; + + port { + cam_endpoint: endpoint { + bus-type = <4>; + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = + /bits/ 64 <456000000>; + }; + }; +}; + +vcm_node: bu64754@76 { + compatible = "rohm,bu64754"; + reg = <0x76>; + status = "disabled"; + vdd-supply = <&cam1_reg>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ov64a40-overlay.dts linux/arch/arm/boot/dts/overlays/ov64a40-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ov64a40-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ov64a40-overlay.dts 2023-12-13 11:50:48.614961308 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for OV64A40 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + i2c_frag: fragment@0 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + #include "ov64a40.dtsi" + }; + }; + + csi_frag: fragment@1 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + brcm,media-controller; + + port{ + csi_ep: endpoint{ + remote-endpoint = <&cam_endpoint>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + fragment@2 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + clk_frag: fragment@3 { + target = <&cam1_clk>; + __overlay__ { + clock-frequency = <24000000>; + status = "okay"; + }; + }; + + fragment@4 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&cam_node>; + __overlay__ { + lens-focus = <&vcm_node>; + }; + }; + + __overrides__ { + rotation = <&cam_node>,"rotation:0"; + orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <&cam_node>, "clocks:0=",<&cam0_clk>, + <&cam_node>, "avdd-supply:0=",<&cam0_reg>, + <&vcm_node>, "vdd-supply:0=",<&cam0_reg>; + vcm = <&vcm_node>, "status", + <0>, "=5"; + link-frequency = <&cam_endpoint>,"link-frequencies#0"; + }; +}; + +&cam_node { + status = "okay"; +}; + +&cam_endpoint { + remote-endpoint = <&csi_ep>; +}; + +&vcm_node { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ov7251.dtsi linux/arch/arm/boot/dts/overlays/ov7251.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/ov7251.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ov7251.dtsi 2023-12-13 11:50:48.614961308 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Fragment that configures an ov7251 + +cam_node: ov7251@60 { + compatible = "ovti,ov7251"; + reg = <0x60>; + status = "disabled"; + + clocks = <&cam1_clk>; + clock-names = "xclk"; + clock-frequency = <24000000>; + + vdddo-supply = <&cam_dummy_reg>; + vdda-supply = <&cam1_reg>; + vddd-supply = <&cam_dummy_reg>; + + rotation = <0>; + orientation = <2>; + + port { + cam_endpoint: endpoint { + clock-lanes = <0>; + data-lanes = <1>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <240000000>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ov7251-overlay.dts linux/arch/arm/boot/dts/overlays/ov7251-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ov7251-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ov7251-overlay.dts 2023-12-13 11:50:48.614961308 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for OV7251 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2835"; + + i2c_frag: fragment@0 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + #include "ov7251.dtsi" + }; + }; + + csi_frag: fragment@1 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + brcm,media-controller; + + port { + csi_ep: endpoint { + remote-endpoint = <&cam_endpoint>; + data-lanes = <1>; + }; + }; + }; + }; + + fragment@2 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + clk_frag: fragment@4 { + target = <&cam1_clk>; + __overlay__ { + status = "okay"; + clock-frequency = <24000000>; + }; + }; + + __overrides__ { + rotation = <&cam_node>,"rotation:0"; + orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <&cam_node>, "clocks:0=",<&cam0_clk>, + <&cam_node>, "vdda-supply:0=",<&cam0_reg>; + }; +}; + +&cam_node { + status = "okay"; +}; + +&cam_endpoint { + remote-endpoint = <&csi_ep>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ov9281.dtsi linux/arch/arm/boot/dts/overlays/ov9281.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/ov9281.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ov9281.dtsi 2023-12-13 11:50:48.614961308 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Fragment that configures an ov9281 + +cam_node: ov9281@60 { + compatible = "ovti,ov9281"; + reg = <0x60>; + status = "disabled"; + + clocks = <&cam1_clk>; + clock-names = "xvclk"; + + avdd-supply = <&cam1_reg>; + dovdd-supply = <&cam_dummy_reg>; + dvdd-supply = <&cam_dummy_reg>; + + rotation = <0>; + orientation = <2>; + + port { + cam_endpoint: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <400000000>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ov9281-overlay.dts linux/arch/arm/boot/dts/overlays/ov9281-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ov9281-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ov9281-overlay.dts 2023-12-13 11:50:48.614961308 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for OV9281 camera module on VC I2C bus +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/{ + compatible = "brcm,bcm2835"; + + i2c_frag: fragment@0 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + #include "ov9281.dtsi" + }; + }; + + csi_frag: fragment@1 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + brcm,media-controller; + + port { + csi_ep: endpoint { + remote-endpoint = <&cam_endpoint>; + data-lanes = <1 2>; + clock-noncontinuous; + }; + }; + }; + }; + + fragment@2 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + clk_frag: fragment@4 { + target = <&cam1_clk>; + __overlay__ { + status = "okay"; + clock-frequency = <24000000>; + }; + }; + + __overrides__ { + rotation = <&cam_node>,"rotation:0"; + orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <&cam_node>, "clocks:0=",<&cam0_clk>, + <&cam_node>, "avdd-supply:0=",<&cam0_reg>; + }; +}; + +&cam_node { + status = "okay"; +}; + +&cam_endpoint { + remote-endpoint = <&csi_ep>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/overlay_map.dts linux/arch/arm/boot/dts/overlays/overlay_map.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/overlay_map.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/overlay_map.dts 2023-12-13 11:50:48.614961308 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; + +/ { + audremap { + bcm2835; + bcm2711; + }; + + balena-fin { + bcm2835; + bcm2711; + }; + + bmp085_i2c-sensor { + deprecated = "use i2c-sensor,bmp085"; + }; + + cm-swap-i2c0 { + bcm2835; + bcm2711; + }; + + cutiepi-panel { + bcm2711; + }; + + disable-bt { + bcm2835; + bcm2711; + bcm2712 = "disable-bt-pi5"; + }; + + disable-bt-pi5 { + bcm2712; + }; + + disable-emmc2 { + bcm2711; + }; + + disable-wifi { + bcm2835; + bcm2711; + bcm2712 = "disable-wifi-pi5"; + }; + + disable-wifi-pi5 { + bcm2712; + }; + + highperi { + bcm2711; + }; + + i2c0 { + bcm2835; + bcm2711; + bcm2712 = "i2c0-pi5"; + }; + + i2c0-bcm2708 { + deprecated = "use i2c0"; + }; + + i2c0-pi5 { + bcm2712; + }; + + i2c1 { + bcm2835; + bcm2711; + bcm2712 = "i2c1-pi5"; + }; + + i2c1-bcm2708 { + deprecated = "use i2c1"; + }; + + i2c1-pi5 { + bcm2712; + }; + + i2c2 { + bcm2712 = "i2c2-pi5"; + }; + + i2c2-pi5 { + bcm2712; + }; + + i2c3 { + bcm2711; + bcm2712 = "i2c3-pi5"; + }; + + i2c3-pi5 { + bcm2712; + }; + + i2c4 { + bcm2711; + }; + + i2c5 { + bcm2711; + }; + + i2c6 { + bcm2711; + }; + + i2s-gpio28-31 { + bcm2835; + bcm2711; + }; + + lirc-rpi { + deprecated = "use gpio-ir"; + }; + + midi-uart0 { + bcm2835; + bcm2711; + bcm2712 = "midi-uart0-pi5"; + }; + + midi-uart0-pi5 { + bcm2712; + }; + + midi-uart1 { + bcm2835; + bcm2711; + bcm2712 = "midi-uart1-pi5"; + }; + + midi-uart1-pi5 { + bcm2712; + }; + + midi-uart2 { + bcm2711; + bcm2712 = "midi-uart2-pi5"; + }; + + midi-uart2-pi5 { + bcm2712; + }; + + midi-uart3 { + bcm2711; + bcm2712 = "midi-uart3-pi5"; + }; + + midi-uart3-pi5 { + bcm2712; + }; + + midi-uart4 { + bcm2711; + bcm2712 = "midi-uart4-pi5"; + }; + + midi-uart4-pi5 { + bcm2712; + }; + + midi-uart5 { + bcm2711; + }; + + miniuart-bt { + bcm2835; + bcm2711; + }; + + mmc { + bcm2835; + bcm2711; + }; + + mpu6050 { + deprecated = "use i2c-sensor,mpu6050"; + }; + + pcie-32bit-dma { + bcm2711; + }; + + pi3-act-led { + renamed = "act-led"; + }; + + pi3-disable-bt { + renamed = "disable-bt"; + }; + + pi3-disable-wifi { + renamed = "disable-wifi"; + }; + + pi3-miniuart-bt { + renamed = "miniuart-bt"; + }; + + pwm1 { + bcm2711; + }; + + ramoops { + bcm2835; + bcm2711 = "ramoops-pi4"; + }; + + ramoops-pi4 { + bcm2711; + }; + + rpi-cirrus-wm5102 { + renamed = "cirrus-wm5102"; + }; + + rpi-dac { + renamed = "i2s-dac"; + }; + + rpi-display { + renamed = "watterott-display"; + }; + + rpi-proto { + renamed = "proto-codec"; + }; + + rpivid-v4l2 { + deprecated = "no longer necessary"; + }; + + sdhost { + bcm2835; + bcm2711; + }; + + sdio { + bcm2835; + bcm2711; + }; + + sdio-1bit { + deprecated = "use sdio,bus_width=1,gpios_22_25"; + }; + + sdio-pi5 { + bcm2712; + }; + + sdtweak { + deprecated = "use 'dtparam=sd_poll_once' etc."; + }; + + smi { + bcm2835; + bcm2711; + }; + + smi-dev { + bcm2835; + bcm2711; + }; + + smi-nand { + bcm2835; + bcm2711; + }; + + spi0-cs { + renamed = "spi0-2cs"; + }; + + spi0-hw-cs { + deprecated = "no longer necessary"; + }; + + spi2-1cs { + bcm2835; + bcm2711; + bcm2712 = "spi2-1cs-pi5"; + }; + + spi2-1cs-pi5 { + bcm2712; + }; + + spi2-2cs { + bcm2835; + bcm2711; + bcm2712 = "spi2-2cs-pi5"; + }; + + spi2-2cs-pi5 { + bcm2712; + }; + + spi3-1cs { + bcm2711; + bcm2712 = "spi3-1cs-pi5"; + }; + + spi3-1cs-pi5 { + bcm2712; + }; + + spi3-2cs { + bcm2711; + bcm2712 = "spi3-2cs-pi5"; + }; + + spi3-2cs-pi5 { + bcm2712; + }; + + spi4-1cs { + bcm2711; + }; + + spi4-2cs { + bcm2711; + }; + + spi5-1cs { + bcm2711; + bcm2712 = "spi5-1cs-pi5"; + }; + + spi5-1cs-pi5 { + bcm2712; + }; + + spi5-2cs { + bcm2711; + bcm2712 = "spi5-2cs-pi5"; + }; + + spi5-2cs-pi5 { + bcm2712; + }; + + spi6-1cs { + bcm2711; + }; + + spi6-2cs { + bcm2711; + }; + + uart0 { + bcm2835; + bcm2711; + bcm2712 = "uart0-pi5"; + }; + + uart0-pi5 { + bcm2712; + }; + + uart1 { + bcm2835; + bcm2711; + bcm2712 = "uart1-pi5"; + }; + + uart1-pi5 { + bcm2712; + }; + + uart2 { + bcm2711; + bcm2712 = "uart2-pi5"; + }; + + uart2-pi5 { + bcm2712; + }; + + uart3 { + bcm2711; + bcm2712 = "uart3-pi5"; + }; + + uart3-pi5 { + bcm2712; + }; + + uart4 { + bcm2711; + bcm2712 = "uart4-pi5"; + }; + + uart4-pi5 { + bcm2712; + }; + + uart5 { + bcm2711; + }; + + upstream { + bcm2835; + bcm2711 = "upstream-pi4"; + }; + + upstream-aux-interrupt { + deprecated = "no longer necessary"; + }; + + upstream-pi4 { + bcm2711; + }; + + vc4-fkms-v3d { + bcm2835; + bcm2711 = "vc4-fkms-v3d-pi4"; + bcm2712 = "vc4-fkms-v3d-pi4"; + }; + + vc4-fkms-v3d-pi4 { + bcm2711; + bcm2712; + }; + + vc4-kms-dpi-at056tn53v1 { + deprecated = "use vc4-kms-dpi-panel,at056tn53v1"; + }; + + vc4-kms-v3d { + bcm2835; + bcm2711 = "vc4-kms-v3d-pi4"; + bcm2712 = "vc4-kms-v3d-pi5"; + }; + + vc4-kms-v3d-pi4 { + bcm2711; + bcm2712 = "vc4-kms-v3d-pi5"; + }; + + vc4-kms-v3d-pi5 { + bcm2712; + }; + + vl805 { + bcm2711; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/papirus-overlay.dts linux/arch/arm/boot/dts/overlays/papirus-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/papirus-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/papirus-overlay.dts 2023-12-13 11:50:48.615961311 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* PaPiRus ePaper Screen by Pi Supply */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c_arm>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + display_temp: lm75@48 { + compatible = "national,lm75b"; + reg = <0x48>; + status = "okay"; + #thermal-sensor-cells = <0>; + }; + }; + }; + + fragment@1 { + target-path = "/thermal-zones"; + __overlay__ { + display { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&display_temp>; + }; + }; + }; + + fragment@2 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + repaper_pins: repaper_pins { + brcm,pins = <14 15 23 24 25>; + brcm,function = <1 1 1 1 0>; /* out out out out in */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + repaper: repaper@0{ + compatible = "not_set"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&repaper_pins>; + + spi-max-frequency = <8000000>; + + panel-on-gpios = <&gpio 23 0>; + border-gpios = <&gpio 14 0>; + discharge-gpios = <&gpio 15 0>; + reset-gpios = <&gpio 24 0>; + busy-gpios = <&gpio 25 0>; + + repaper-thermal-zone = "display"; + }; + }; + }; + + __overrides__ { + panel = <&repaper>, "compatible"; + speed = <&repaper>, "spi-max-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pca953x-overlay.dts linux/arch/arm/boot/dts/overlays/pca953x-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pca953x-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pca953x-overlay.dts 2023-12-13 11:50:48.615961311 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for NXP PCA953x family of I2C GPIO controllers on ARM I2C bus. +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c_arm>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca: pca@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pca6416"; + }; + }; + fragment@2 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pca9505"; + }; + }; + fragment@3 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pca9535"; + }; + }; + fragment@4 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pca9536"; + }; + }; + fragment@5 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pca9537"; + }; + }; + fragment@6 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pca9538"; + }; + }; + fragment@7 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pca9539"; + }; + }; + fragment@8 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pca9554"; + }; + }; + fragment@9 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pca9555"; + }; + }; + fragment@10 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pca9556"; + }; + }; + fragment@11 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pca9557"; + }; + }; + fragment@12 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pca9574"; + }; + }; + fragment@13 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pca9575"; + }; + }; + fragment@14 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pca9698"; + }; + }; + fragment@15 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pcal6416"; + }; + }; + fragment@16 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pcal6524"; + }; + }; + fragment@17 { + target = <&pca>; + __dormant__ { + compatible = "nxp,pcal9555a"; + }; + }; + fragment@18 { + target = <&pca>; + __dormant__ { + compatible = "maxim,max7310"; + }; + }; + fragment@19 { + target = <&pca>; + __dormant__ { + compatible = "maxim,max7312"; + }; + }; + fragment@20 { + target = <&pca>; + __dormant__ { + compatible = "maxim,max7313"; + }; + }; + fragment@21 { + target = <&pca>; + __dormant__ { + compatible = "maxim,max7315"; + }; + }; + fragment@22 { + target = <&pca>; + __dormant__ { + compatible = "ti,pca6107"; + }; + }; + fragment@23 { + target = <&pca>; + __dormant__ { + compatible = "ti,tca6408"; + }; + }; + fragment@24 { + target = <&pca>; + __dormant__ { + compatible = "ti,tca6416"; + }; + }; + fragment@25 { + target = <&pca>; + __dormant__ { + compatible = "ti,tca6424"; + }; + }; + fragment@26 { + target = <&pca>; + __dormant__ { + compatible = "ti,tca9539"; + }; + }; + fragment@27 { + target = <&pca>; + __dormant__ { + compatible = "ti,tca9554"; + }; + }; + fragment@28 { + target = <&pca>; + __dormant__ { + compatible = "onnn,cat9554"; + }; + }; + fragment@29 { + target = <&pca>; + __dormant__ { + compatible = "onnn,pca9654"; + }; + }; + fragment@30 { + target = <&pca>; + __dormant__ { + compatible = "exar,xra1202"; + }; + }; + + __overrides__ { + addr = <&pca>,"reg:0"; + pca6416 = <0>, "+1"; + pca9505 = <0>, "+2"; + pca9535 = <0>, "+3"; + pca9536 = <0>, "+4"; + pca9537 = <0>, "+5"; + pca9538 = <0>, "+6"; + pca9539 = <0>, "+7"; + pca9554 = <0>, "+8"; + pca9555 = <0>, "+9"; + pca9556 = <0>, "+10"; + pca9557 = <0>, "+11"; + pca9574 = <0>, "+12"; + pca9575 = <0>, "+13"; + pca9698 = <0>, "+14"; + pcal6416 = <0>, "+15"; + pcal6524 = <0>, "+16"; + pcal9555a = <0>, "+17"; + max7310 = <0>, "+18"; + max7312 = <0>, "+19"; + max7313 = <0>, "+20"; + max7315 = <0>, "+21"; + pca6107 = <0>, "+22"; + tca6408 = <0>, "+23"; + tca6416 = <0>, "+24"; + tca6424 = <0>, "+25"; + tca9539 = <0>, "+26"; + tca9554 = <0>, "+27"; + cat9554 = <0>, "+28"; + pca9654 = <0>, "+29"; + xra1202 = <0>, "+30"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pcf857x-overlay.dts linux/arch/arm/boot/dts/overlays/pcf857x-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pcf857x-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pcf857x-overlay.dts 2023-12-13 11:50:48.615961311 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for PCF857X GPIO Extender from NXP + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c_arm>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + pcf857x: pcf857x@0 { + compatible = ""; + reg = <0x00>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + }; + }; + + __overrides__ { + pcf8574 = <&pcf857x>,"compatible=nxp,pcf8574", <&pcf857x>,"reg:0=0x20"; + pcf8574a = <&pcf857x>,"compatible=nxp,pcf8574a", <&pcf857x>,"reg:0=0x38"; + pcf8575 = <&pcf857x>,"compatible=nxp,pcf8575", <&pcf857x>,"reg:0=0x20"; + pca8574 = <&pcf857x>,"compatible=nxp,pca8574", <&pcf857x>,"reg:0=0x20"; + addr = <&pcf857x>,"reg:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pcie-32bit-dma-overlay.dts linux/arch/arm/boot/dts/overlays/pcie-32bit-dma-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pcie-32bit-dma-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pcie-32bit-dma-overlay.dts 2023-12-13 11:50:48.615961311 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * pcie-32bit-dma-overlay.dts + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2711"; + + fragment@0 { + target-path = "/aliases"; + __overlay__ { + /* + * Removing this alias stops the firmware patching the + * PCIE DT dma-ranges based on the detected chip + * revision. + */ + pcie0 = ""; + }; + }; + + fragment@1 { + target = <&pcie0>; + __overlay__ { + /* + * The size of the range is rounded up to a power of 2, + * so the range ends up being 0-4GB, and the MSI vector + * gets pushed beyond 4GB. + */ + #address-cells = <3>; + #size-cells = <2>; + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 + 0x0 0x80000000>; + }; + }; + +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pibell-overlay.dts linux/arch/arm/boot/dts/overlays/pibell-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pibell-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pibell-overlay.dts 2023-12-13 11:50:48.615961311 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + codec_out: spdif-transmitter { + #address-cells = <0>; + #size-cells = <0>; + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + }; + + codec_in: card-codec { + #sound-dai-cells = <0>; + compatible = "invensense,ics43432"; + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&i2s_clk_producer>; + __overlay__ { + #sound-dai-cells = <0>; + status = "okay"; + }; + }; + + fragment@2 { + target = <&sound>; + snd: __overlay__ { + compatible = "simple-audio-card"; + simple-audio-card,name = "PiBell"; + + status="okay"; + + capture_link: simple-audio-card,dai-link@0 { + format = "i2s"; + + r_cpu_dai: cpu { + sound-dai = <&i2s_clk_producer>; + +/* example TDM slot configuration + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; +*/ + }; + + r_codec_dai: codec { + sound-dai = <&codec_in>; + }; + }; + + playback_link: simple-audio-card,dai-link@1 { + format = "i2s"; + + p_cpu_dai: cpu { + sound-dai = <&i2s_clk_producer>; + +/* example TDM slot configuration + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; +*/ + }; + + p_codec_dai: codec { + sound-dai = <&codec_out>; + }; + }; + }; + }; + + __overrides__ { + alsaname = <&snd>, "simple-audio-card,name"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pifacedigital-overlay.dts linux/arch/arm/boot/dts/overlays/pifacedigital-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pifacedigital-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pifacedigital-overlay.dts 2023-12-13 11:50:48.615961311 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PiFace Digital, Device Tree Overlay. + * Copyright (C) 2020 Thomas Preston <thomas.preston@codethink.co.uk> + * + * The PiFace Digital is a convenient breakout board for the Microchip mcp23s17 + * SPI GPIO port expander. + * + * The first eight GPIOs 0..7 (bank A) are connected to eight output terminals + * and LEDs, plus two relays on the first two outputs. These output loads are + * active-high. + * + * The next eight GPIOs 8..15 (bank B) are connected to eight input terminals + * with four on-board switches connecting them to ground. Inputs devices are + * therefore expected to bridge terminals to ground, so the mcp23s17 pullups are + * activated for GPIO bank B. + * + * On PiFace Digital, the mcp23s17 is connected to the Raspberry Pi's SPI0 CS0 + * bus. Each SPI bus supports up to eight addressable child devices. The PiFace + * Digital only supports addresses 0-4, which can be configured by jumpers JP1 + * and JP2. + * + * You can tell the driver about these jumper configurations with the + * spi-present-mask bitmask: + * + * | JP1 | JP2 | dtoverlay line in /boot/config.txt | + * | --- | --- | ------------------------------------------ | + * | 0 | 0 | dtoverlay=pifacedigital | + * | 0 | 0 | dtoverlay=pifacedigital:spi-present-mask=1 | + * | 0 | 1 | dtoverlay=pifacedigital:spi-present-mask=2 | + * | 1 | 0 | dtoverlay=pifacedigital:spi-present-mask=4 | + * | 1 | 1 | dtoverlay=pifacedigital:spi-present-mask=8 | + * + * # Example + * Set the dtoverlay config in /boot/config.txt and power off the Raspberry Pi: + * + * $ grep pifacedigital /boot/config.txt + * dtoverlay=pifacedigital + * $ sudo systemctl poweroff + * + * Attach the PiFace Digital and power on the Raspberry Pi. + * Then use the libgpiod tools to query the device: + * + * $ sudo apt install gpiod + * $ gpiodetect | grep mcp23s17 + * gpiochip2 [mcp23s17.0] (16 lines) + * + * Set GPIO outputs 0, 2 and 5: + * + * $ gpioset gpiochip2 0=1 2=1 5=1 + * + * Get GPIO status (input GPIO 8..15 are high, because they are active-low): + * + * $ gpioget gpiochip2 {8..15} + * 1 1 1 1 1 1 1 1 + * + * And even monitor interrupts: + * + * $ gpiomon gpiochip2 {8..15} + * event: FALLING EDGE offset: 11 timestamp: [1597361662.926741667] + * event: RISING EDGE offset: 11 timestamp: [1597361663.062555051] + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + /* Disable exposing /dev/spidev0.0 */ + fragment@0 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + /* Add the PiFace Digital device node to the spi0.0 device. */ + fragment@1 { + target = <&spi0>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfdigital: pifacedigital@0 { + compatible = "microchip,mcp23s17"; + reg = <0>; + + /* Set devices present with 8-bit mask. */ + microchip,spi-present-mask = <0x01>; + spi-max-frequency = <500000>; + + gpio-controller; + #gpio-cells = <2>; + + /* This device can pass through interrupts. */ + interrupt-controller; + #interrupt-cells = <2>; + + /* INTB is connected to GPIO 25. + * 0x8 active-low level-sensitive + */ + interrupts = <25 0x8>; + interrupt-parent = <&gpio>; + + /* Configure pull-ups on bank B GPIOs */ + pinctrl-0 = <&pfdigital_irq &pfdigital_pullups>; + pinctrl-names = "default"; + pfdigital_pullups: pinmux { + pins = + "gpio8", + "gpio9", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gpio15"; + bias-pull-up; + }; + }; + }; + }; + + /* PiFace Digital mcp23s17 INTB pin is connected to GPIO 25. The INTB + * pin is configured active-low (0 on interrupt), so expect to see + * FALLING_EDGE when inputs are bridged to ground (switch is pressed). + */ + fragment@3 { + target = <&gpio>; + __overlay__ { + pfdigital_irq: pifacedigital_irq { + brcm,pins = <25>; + brcm,function = <0>; /* input */ + }; + }; + }; + + __overrides__ { + spi-present-mask = <&pfdigital>, "microchip,spi-present-mask:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pifi-40-overlay.dts linux/arch/arm/boot/dts/overlays/pifi-40-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pifi-40-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pifi-40-overlay.dts 2023-12-13 11:50:48.616961313 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for PiFi-40 Amp +/dts-v1/; +/plugin/; +#include <dt-bindings/gpio/gpio.h> +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + tas5711l: audio-codec@1a { + compatible = "ti,tas5711"; + reg = <0x1a>; + #sound-dai-cells = <0>; + sound-name-prefix = "Left"; + status = "okay"; + }; + + tas5711r: audio-codec@1b { + compatible = "ti,tas5711"; + reg = <0x1b>; + #sound-dai-cells = <0>; + sound-name-prefix = "Right"; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + pifi_40: __overlay__ { + compatible = "pifi,pifi-40"; + audio-codec = <&tas5711l &tas5711r>; + i2s-controller = <&i2s_clk_producer>; + pdn-gpios = <&gpio 23 1>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pifi-dac-hd-overlay.dts linux/arch/arm/boot/dts/overlays/pifi-dac-hd-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pifi-dac-hd-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pifi-dac-hd-overlay.dts 2023-12-13 11:50:48.616961313 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for PiFi-DAC-HD +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells =<0>; + + pcm5142: pcm5142@4c { + #sound-dai-cells = <0>; + compatible = "ti,pcm5142"; + reg = <0x4c>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "simple-audio-card"; + simple-audio-card,name = "PiFi-DAC-HD"; + status = "okay"; + + simple-audio-card,dai-link@1 { + format = "i2s"; + cpu { + sound-dai = <&i2s_clk_producer>; + }; + codec { + sound-dai = <&pcm5142>; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pifi-dac-zero-overlay.dts linux/arch/arm/boot/dts/overlays/pifi-dac-zero-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pifi-dac-zero-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pifi-dac-zero-overlay.dts 2023-12-13 11:50:48.616961313 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for PiFi-DAC-Zero +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&sound>; + __overlay__ { + compatible = "simple-audio-card"; + simple-audio-card,name = "PiFi-DAC-Zero"; + status = "okay"; + + simple-audio-card,dai-link@1 { + format = "i2s"; + + cpu { + sound-dai = <&i2s_clk_producer>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + + codec { + sound-dai = <&codec_out>; + }; + }; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + codec_out: pcm5102a-codec { + #sound-dai-cells = <0>; + compatible = "ti,pcm5102a"; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&i2s_clk_producer>; + __overlay__ { + #sound-dai-cells = <0>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pifi-mini-210-overlay.dts linux/arch/arm/boot/dts/overlays/pifi-mini-210-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pifi-mini-210-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pifi-mini-210-overlay.dts 2023-12-13 11:50:48.616961313 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for PiFi Mini 210 +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + tas5711@1a { + #sound-dai-cells = <0>; + compatible = "ti,tas5711"; + reg = <0x1a>; + status = "okay"; + pdn-gpios = <&gpio 23 1>; + reset-gpios = <&gpio 24 1>; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "pifi,pifi-mini-210"; + i2s-controller = <&i2s_clk_producer>; + + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/piglow-overlay.dts linux/arch/arm/boot/dts/overlays/piglow-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/piglow-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/piglow-overlay.dts 2023-12-13 11:50:48.616961313 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for SN3218 LED driver from Si-En Technology on PiGlow +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c_arm>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + sn3218@54 { + compatible = "si-en,sn3218"; + reg = <0x54>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + led@1 { + reg = <1>; + label = "piglow:red:led1"; + }; + led@2 { + reg = <2>; + label = "piglow:orange:led2"; + }; + led@3 { + reg = <3>; + label = "piglow:yellow:led3"; + }; + led@4 { + reg = <4>; + label = "piglow:green:led4"; + }; + led@5 { + reg = <5>; + label = "piglow:blue:led5"; + }; + led@6 { + reg = <6>; + label = "piglow:green:led6"; + }; + led@7 { + reg = <7>; + label = "piglow:red:led7"; + }; + led@8 { + reg = <8>; + label = "piglow:orange:led8"; + }; + led@9 { + reg = <9>; + label = "piglow:yellow:led9"; + }; + led@10 { + reg = <10>; + label = "piglow:white:led10"; + }; + led@11 { + reg = <11>; + label = "piglow:white:led11"; + }; + led@12 { + reg = <12>; + label = "piglow:blue:led12"; + }; + led@13 { + reg = <13>; + label = "piglow:white:led13"; + }; + led@14 { + reg = <14>; + label = "piglow:green:led14"; + }; + led@15 { + reg = <15>; + label = "piglow:blue:led15"; + }; + led@16 { + reg = <16>; + label = "piglow:yellow:led16"; + }; + led@17 { + reg = <17>; + label = "piglow:orange:led17"; + }; + led@18 { + reg = <18>; + label = "piglow:red:led18"; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts linux/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts 2023-12-13 11:50:48.617961315 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ + /* + * Device Tree overlay for PiScreen2 3.5" TFT with resistive touch by Ozzmaker.com + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + piscreen2_pins: piscreen2_pins { + brcm,pins = <17 25 24 22>; + brcm,function = <0 1 1 1>; /* in out out out */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + piscreen2: piscreen2@0{ + compatible = "ilitek,ili9486"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&piscreen2_pins>; + bgr; + spi-max-frequency = <64000000>; + rotate = <90>; + fps = <30>; + buswidth = <8>; + regwidth = <16>; + txbuflen = <32768>; + reset-gpios = <&gpio 25 1>; + dc-gpios = <&gpio 24 0>; + led-gpios = <&gpio 22 0>; + debug = <0>; + + init = <0x10000b0 0x00 + 0x1000011 + 0x20000ff + 0x100003a 0x55 + 0x1000036 0x28 + 0x10000c0 0x11 0x09 + 0x10000c1 0x41 + 0x10000c5 0x00 0x00 0x00 0x00 + 0x10000b6 0x00 0x02 + 0x10000f7 0xa9 0x51 0x2c 0x2 + 0x10000be 0x00 0x04 + 0x10000e9 0x00 + 0x1000011 + 0x1000029>; + + }; + + piscreen2_ts: piscreen2-ts@1 { + compatible = "ti,ads7846"; + reg = <1>; + + spi-max-frequency = <2000000>; + interrupts = <17 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; + pendown-gpio = <&gpio 17 0>; + ti,swap-xy; + ti,x-plate-ohms = /bits/ 16 <100>; + ti,pressure-max = /bits/ 16 <255>; + }; + }; + }; + __overrides__ { + speed = <&piscreen2>,"spi-max-frequency:0"; + rotate = <&piscreen2>,"rotate:0"; + fps = <&piscreen2>,"fps:0"; + debug = <&piscreen2>,"debug:0"; + xohms = <&piscreen2_ts>,"ti,x-plate-ohms;0"; + }; +}; + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/piscreen-overlay.dts linux/arch/arm/boot/dts/overlays/piscreen-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/piscreen-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/piscreen-overlay.dts 2023-12-13 11:50:48.616961313 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for PiScreen 3.5" display shield by Ozzmaker + * + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + piscreen_pins: piscreen_pins { + brcm,pins = <17 25 24 22>; + brcm,function = <0 1 1 1>; /* in out out out */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + piscreen: piscreen@0{ + compatible = "ilitek,ili9486"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&piscreen_pins>; + + spi-max-frequency = <24000000>; + rotate = <270>; + bgr; + fps = <30>; + buswidth = <8>; + regwidth = <16>; + reset-gpios = <&gpio 25 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + led-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + debug = <0>; + + init = <0x10000b0 0x00 + 0x1000011 + 0x20000ff + 0x100003a 0x55 + 0x1000036 0x28 + 0x10000c2 0x44 + 0x10000c5 0x00 0x00 0x00 0x00 + 0x10000e0 0x0f 0x1f 0x1c 0x0c 0x0f 0x08 0x48 0x98 0x37 0x0a 0x13 0x04 0x11 0x0d 0x00 + 0x10000e1 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00 + 0x10000e2 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00 + 0x1000011 + 0x1000029>; + }; + + piscreen_ts: piscreen-ts@1 { + compatible = "ti,ads7846"; + reg = <1>; + + spi-max-frequency = <2000000>; + interrupts = <17 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; + pendown-gpio = <&gpio 17 0>; + ti,swap-xy; + ti,x-plate-ohms = /bits/ 16 <100>; + ti,pressure-max = /bits/ 16 <255>; + }; + }; + }; + __overrides__ { + speed = <&piscreen>,"spi-max-frequency:0"; + rotate = <&piscreen>,"rotate:0"; + fps = <&piscreen>,"fps:0"; + debug = <&piscreen>,"debug:0"; + xohms = <&piscreen_ts>,"ti,x-plate-ohms;0"; + drm = <&piscreen>,"compatible=waveshare,rpi-lcd-35", + <&piscreen>,"reset-gpios:8=",<GPIO_ACTIVE_HIGH>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pisound-overlay.dts linux/arch/arm/boot/dts/overlays/pisound-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pisound-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pisound-overlay.dts 2023-12-13 11:50:48.617961315 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Pisound Linux kernel module. + * Copyright (C) 2016-2017 Vilniaus Blokas UAB, https://blokas.io/pisound + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&spi0>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + pisound_spi: pisound_spi@0{ + compatible = "blokaslabs,pisound-spi"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + fragment@4 { + target-path = "/"; + __overlay__ { + pcm5102a-codec { + #sound-dai-cells = <0>; + compatible = "ti,pcm5102a"; + status = "okay"; + }; + }; + }; + + fragment@5 { + target = <&sound>; + __overlay__ { + compatible = "blokaslabs,pisound"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pisound_button_pins>; + + osr-gpios = + <&gpio 13 GPIO_ACTIVE_HIGH>, + <&gpio 26 GPIO_ACTIVE_HIGH>, + <&gpio 16 GPIO_ACTIVE_HIGH>; + + reset-gpios = + <&gpio 12 GPIO_ACTIVE_HIGH>, + <&gpio 24 GPIO_ACTIVE_HIGH>; + + data_available-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + + button-gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + }; + }; + + fragment@6 { + target = <&gpio>; + __overlay__ { + pisound_button_pins: pisound_button_pins { + brcm,pins = <17>; + brcm,function = <0>; // Input + brcm,pull = <2>; // Pull-Up + }; + }; + }; + + fragment@7 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pitft22-overlay.dts linux/arch/arm/boot/dts/overlays/pitft22-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pitft22-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pitft22-overlay.dts 2023-12-13 11:50:48.617961315 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for pitft by Adafruit + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + pitft_pins: pitft_pins { + brcm,pins = <25>; + brcm,function = <1>; /* out */ + brcm,pull = <0>; /* none */ + }; + }; + }; + + fragment@3 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pitft: pitft@0{ + compatible = "ilitek,ili9340"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pitft_pins>; + + spi-max-frequency = <32000000>; + rotate = <90>; + fps = <25>; + bgr; + buswidth = <8>; + dc-gpios = <&gpio 25 0>; + debug = <0>; + }; + + }; + }; + + __overrides__ { + speed = <&pitft>,"spi-max-frequency:0"; + rotate = <&pitft>,"rotate:0"; + fps = <&pitft>,"fps:0"; + debug = <&pitft>,"debug:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts linux/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts 2023-12-13 11:50:48.617961315 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for Adafruit PiTFT 2.8" capacitive touch screen + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + pitft_pins: pitft_pins { + brcm,pins = <24 25>; + brcm,function = <0 1>; /* in out */ + brcm,pull = <2 0>; /* pullup none */ + }; + }; + }; + + fragment@3 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + pitft: pitft@0{ + compatible = "ilitek,ili9340"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pitft_pins>; + + spi-max-frequency = <32000000>; + rotate = <90>; + fps = <25>; + bgr; + buswidth = <8>; + dc-gpios = <&gpio 25 0>; + debug = <0>; + }; + }; + }; + + fragment@4 { + target = <&i2c1>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + ft6236: ft6236@38 { + compatible = "focaltech,ft6236"; + reg = <0x38>; + + interrupt-parent = <&gpio>; + interrupts = <24 2>; + touchscreen-size-x = <240>; + touchscreen-size-y = <320>; + }; + }; + }; + + __overrides__ { + speed = <&pitft>,"spi-max-frequency:0"; + rotate = <&pitft>,"rotate:0"; + fps = <&pitft>,"fps:0"; + debug = <&pitft>,"debug:0"; + touch-sizex = <&ft6236>,"touchscreen-size-x?"; + touch-sizey = <&ft6236>,"touchscreen-size-y?"; + touch-invx = <&ft6236>,"touchscreen-inverted-x?"; + touch-invy = <&ft6236>,"touchscreen-inverted-y?"; + touch-swapxy = <&ft6236>,"touchscreen-swapped-x-y?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts linux/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts 2023-12-13 11:50:48.617961315 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for Adafruit PiTFT 2.8" resistive touch screen + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + pitft_pins: pitft_pins { + brcm,pins = <24 25>; + brcm,function = <0 1>; /* in out */ + brcm,pull = <2 0>; /* pullup none */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + pitft: pitft@0{ + compatible = "ilitek,ili9340", "multi-inno,mi0283qt"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pitft_pins>; + + spi-max-frequency = <32000000>; + rotate = <90>; + fps = <25>; + bgr; + buswidth = <8>; + dc-gpios = <&gpio 25 0>; + debug = <0>; + }; + + pitft_ts@1 { + compatible = "st,stmpe610"; + reg = <1>; + + spi-max-frequency = <500000>; + interrupts = <24 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; + interrupt-controller; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <2>; + st,ave-ctrl = <3>; + st,touch-det-delay = <4>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <0>; + }; + + stmpe_gpio: stmpe_gpio { + #gpio-cells = <2>; + compatible = "st,stmpe-gpio"; + /* + * only GPIO2 is wired/available + * and it is wired to the backlight + */ + st,norequest-mask = <0x7b>; + }; + }; + }; + }; + + fragment@5 { + target-path = "/soc"; + __overlay__ { + backlight { + compatible = "gpio-backlight"; + gpios = <&stmpe_gpio 2 0>; + default-on; + }; + }; + }; + + __overrides__ { + speed = <&pitft>,"spi-max-frequency:0"; + rotate = <&pitft>,"rotate:0", /* fbtft */ + <&pitft>,"rotation:0"; /* drm */ + fps = <&pitft>,"fps:0"; + debug = <&pitft>,"debug:0"; + drm = <&pitft>,"compatible=multi-inno,mi0283qt"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pitft35-resistive-overlay.dts linux/arch/arm/boot/dts/overlays/pitft35-resistive-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pitft35-resistive-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pitft35-resistive-overlay.dts 2023-12-13 11:50:48.617961315 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for Adafruit PiTFT 3.5" resistive touch screen + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + pitft_pins: pitft_pins { + brcm,pins = <24 25>; + brcm,function = <0 1>; /* in out */ + brcm,pull = <2 0>; /* pullup none */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + pitft: pitft@0{ + compatible = "himax,hx8357d", "adafruit,yx350hv15"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pitft_pins>; + + spi-max-frequency = <32000000>; + rotate = <90>; + fps = <25>; + bgr; + buswidth = <8>; + dc-gpios = <&gpio 25 0>; + debug = <0>; + }; + + pitft_ts@1 { + compatible = "st,stmpe610"; + reg = <1>; + + spi-max-frequency = <500000>; + interrupts = <24 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; + interrupt-controller; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <2>; + st,ave-ctrl = <3>; + st,touch-det-delay = <4>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <0>; + }; + + stmpe_gpio: stmpe_gpio { + #gpio-cells = <2>; + compatible = "st,stmpe-gpio"; + /* + * only GPIO2 is wired/available + * and it is wired to the backlight + */ + st,norequest-mask = <0x7b>; + }; + }; + }; + }; + + fragment@5 { + target-path = "/soc"; + __overlay__ { + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&stmpe_gpio 2 0>; + default-on; + }; + }; + }; + + __overrides__ { + speed = <&pitft>,"spi-max-frequency:0"; + rotate = <&pitft>,"rotate:0", /* fbtft */ + <&pitft>,"rotation:0"; /* drm */ + fps = <&pitft>,"fps:0"; + debug = <&pitft>,"debug:0"; + drm = <&pitft>,"compatible=adafruit,yx350hv15", + <&pitft>,"backlight:0=",<&backlight>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts linux/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts 2023-12-13 11:50:48.618961318 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + fragment@0 { + target-path = "/"; + __overlay__ { + pps: pps@12 { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pps_pins>; + gpios = <&gpio 18 0>; + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + pps_pins: pps_pins@12 { + brcm,pins = <18>; + brcm,function = <0>; // in + brcm,pull = <0>; // off + }; + }; + }; + + __overrides__ { + gpiopin = <&pps>,"gpios:4", + <&pps>,"reg:0", + <&pps_pins>,"brcm,pins:0", + <&pps_pins>,"reg:0"; + assert_falling_edge = <&pps>,"assert-falling-edge?"; + capture_clear = <&pps>,"capture-clear?"; + pull = <&pps_pins>,"brcm,pull:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/proto-codec-overlay.dts linux/arch/arm/boot/dts/overlays/proto-codec-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/proto-codec-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/proto-codec-overlay.dts 2023-12-13 11:50:48.618961318 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for Rpi-Proto +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wm8731@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8731"; + reg = <0x1a>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "rpi,rpi-proto"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pwm1-overlay.dts linux/arch/arm/boot/dts/overlays/pwm1-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pwm1-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pwm1-overlay.dts 2023-12-13 11:50:48.618961318 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +#include <dt-bindings/pinctrl/bcm2835.h> + +/ { + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&pins>; + __overlay__ { + brcm,pins = <40 41>; + }; + }; + + fragment@1 { + target = <&pins>; + __dormant__ { + brcm,pins = <40>; + }; + }; + + fragment@2 { + target = <&pins>; + __dormant__ { + brcm,pins = <41>; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + pins: pwm1_overlay_pins { + brcm,pins = <40 41>; + brcm,function = <BCM2835_FSEL_ALT0>; + brcm,pull = <BCM2835_PUD_UP>; + }; + }; + }; + + fragment@4 { + target = <&pwm1>; + pwm: __overlay__ { + status = "okay"; + assigned-clock-rates = <100000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pins>; + }; + }; + + __overrides__ { + clock = <&pwm>, "assigned-clock-rates:0"; + pins_40_41 = <0>,"+0-1-2"; + pins_40 = <0>,"-0+1-2"; + pins_41 = <0>,"-0-1+2"; + pull_up = <&pins>, "brcm,pull:0=", <BCM2835_PUD_UP>; + pull_down = <&pins>, "brcm,pull:0=", <BCM2835_PUD_DOWN>; + pull_off = <&pins>, "brcm,pull:0=", <BCM2835_PUD_OFF>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts linux/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts 2023-12-13 11:50:48.618961318 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/* +This is the 2-channel overlay - only use it if you need both channels. + +Legal pin,function combinations for each channel: + PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) + PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) + +N.B.: + 1) Pin 18 is the only one available on all platforms, and + it is the one used by the I2S audio interface. + Pins 12 and 13 might be better choices on an A+, B+ or Pi2. + 2) The onboard analogue audio output uses both PWM channels. + 3) So be careful mixing audio and PWM. +*/ + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + pwm_pins: pwm_pins { + brcm,pins = <18 19>; + brcm,function = <2 2>; /* Alt5 */ + }; + }; + }; + + fragment@1 { + target = <&pwm>; + frag1: __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + assigned-clock-rates = <100000000>; + status = "okay"; + }; + }; + + __overrides__ { + pin = <&pwm_pins>,"brcm,pins:0"; + pin2 = <&pwm_pins>,"brcm,pins:4"; + func = <&pwm_pins>,"brcm,function:0"; + func2 = <&pwm_pins>,"brcm,function:4"; + clock = <&frag1>,"assigned-clock-rates:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pwm-ir-tx-overlay.dts linux/arch/arm/boot/dts/overlays/pwm-ir-tx-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pwm-ir-tx-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pwm-ir-tx-overlay.dts 2023-12-13 11:50:48.618961318 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + pwm0_pins: pwm0_pins { + brcm,pins = <18>; + brcm,function = <2>; /* Alt5 */ + }; + }; + }; + + fragment@1 { + target = <&pwm>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins>; + status = "okay"; + }; + }; + + fragment@2 { + target-path = "/"; + __overlay__ { + pwm-ir-transmitter { + compatible = "pwm-ir-tx"; + pwms = <&pwm 0 100>; + }; + }; + }; + + __overrides__ { + gpio_pin = <&pwm0_pins>, "brcm,pins:0"; + func = <&pwm0_pins>,"brcm,function:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/pwm-overlay.dts linux/arch/arm/boot/dts/overlays/pwm-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/pwm-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/pwm-overlay.dts 2023-12-13 11:50:48.618961318 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/* +Legal pin,function combinations for each channel: + PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) + PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) + +N.B.: + 1) Pin 18 is the only one available on all platforms, and + it is the one used by the I2S audio interface. + Pins 12 and 13 might be better choices on an A+, B+ or Pi2. + 2) The onboard analogue audio output uses both PWM channels. + 3) So be careful mixing audio and PWM. +*/ + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + pwm_pins: pwm_pins { + brcm,pins = <18>; + brcm,function = <2>; /* Alt5 */ + }; + }; + }; + + fragment@1 { + target = <&pwm>; + frag1: __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + assigned-clock-rates = <100000000>; + status = "okay"; + }; + }; + + __overrides__ { + pin = <&pwm_pins>,"brcm,pins:0"; + func = <&pwm_pins>,"brcm,function:0"; + clock = <&frag1>,"assigned-clock-rates:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/qca7000-overlay.dts linux/arch/arm/boot/dts/overlays/qca7000-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/qca7000-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/qca7000-overlay.dts 2023-12-13 11:50:48.619961320 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for the Qualcomm Atheros QCA7000 on PLC Stamp micro EVK +// Visit: https://in-tech-smartcharging.com/products/evaluation-tools/plc-stamp-micro-2-evaluation-board for details + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + eth1: qca7000@0 { + compatible = "qca,qca7000"; + reg = <0>; /* CE0 */ + pinctrl-names = "default"; + pinctrl-0 = <ð1_pins>; + interrupt-parent = <&gpio>; + interrupts = <23 0x1>; /* rising edge */ + spi-max-frequency = <12000000>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + eth1_pins: eth1_pins { + brcm,pins = <23>; + brcm,function = <0>; /* in */ + brcm,pull = <0>; /* none */ + }; + }; + }; + + __overrides__ { + int_pin = <ð1>, "interrupts:0", + <ð1_pins>, "brcm,pins:0"; + speed = <ð1>, "spi-max-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/qca7000-uart0-overlay.dts linux/arch/arm/boot/dts/overlays/qca7000-uart0-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/qca7000-uart0-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/qca7000-uart0-overlay.dts 2023-12-13 11:50:48.619961320 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for the Qualcomm Atheros QCA7000 on PLC Stamp micro EVK +// Visit: https://in-tech-smartcharging.com/products/evaluation-tools/plc-stamp-micro-2-evaluation-board for details + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&uart0>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + + eth2: qca7000 { + compatible = "qca,qca7000"; + current-speed = <115200>; + }; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + uart0_pins: uart0_ovl_pins { + brcm,pins = <14 15>; + brcm,function = <4>; /* alt0 */ + brcm,pull = <0 2>; + }; + }; + }; + + fragment@2 { + target-path = "/aliases"; + __overlay__ { + serial0 = "/soc/serial@7e201000"; + serial1 = "/soc/serial@7e215040"; + }; + }; + + __overrides__ { + baudrate = <ð2>, "current-speed:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ramoops-overlay.dts linux/arch/arm/boot/dts/overlays/ramoops-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ramoops-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ramoops-overlay.dts 2023-12-13 11:50:48.619961320 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&rmem>; + __overlay__ { + ramoops: ramoops@b000000 { + compatible = "ramoops"; + reg = <0x0b000000 0x10000>; /* 64kB */ + record-size = <0x4000>; /* 16kB */ + console-size = <0>; /* disabled by default */ + }; + }; + }; + + __overrides__ { + base-addr = <&ramoops>,"reg:0"; + total-size = <&ramoops>,"reg:4"; + record-size = <&ramoops>,"record-size:0"; + console-size = <&ramoops>,"console-size:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ramoops-pi4-overlay.dts linux/arch/arm/boot/dts/overlays/ramoops-pi4-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ramoops-pi4-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ramoops-pi4-overlay.dts 2023-12-13 11:50:48.619961320 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&rmem>; + __overlay__ { + ramoops: ramoops@b000000 { + compatible = "ramoops"; + reg = <0x0 0x0b000000 0x10000>; /* 64kB */ + record-size = <0x4000>; /* 16kB */ + console-size = <0>; /* disabled by default */ + }; + }; + }; + + __overrides__ { + base-addr = <&ramoops>,"reg#0"; + total-size = <&ramoops>,"reg:8"; + record-size = <&ramoops>,"record-size:0"; + console-size = <&ramoops>,"console-size:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/README linux/arch/arm/boot/dts/overlays/README --- linux-6.1.66/arch/arm/boot/dts/overlays/README 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/README 2023-12-13 11:50:48.586961242 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +Introduction +============ + +This directory contains Device Tree overlays. Device Tree makes it possible +to support many hardware configurations with a single kernel and without the +need to explicitly load or blacklist kernel modules. Note that this isn't a +"pure" Device Tree configuration (c.f. MACH_BCM2835) - some on-board devices +are still configured by the board support code, but the intention is to +eventually reach that goal. + +On Raspberry Pi, Device Tree usage is controlled from /boot/config.txt. By +default, the Raspberry Pi kernel boots with device tree enabled. You can +completely disable DT usage (for now) by adding: + + device_tree= + +to your config.txt, which should cause your Pi to revert to the old way of +doing things after a reboot. + +In /boot you will find a .dtb for each base platform. This describes the +hardware that is part of the Raspberry Pi board. The loader (start.elf and its +siblings) selects the .dtb file appropriate for the platform by name, and reads +it into memory. At this point, all of the optional interfaces (i2c, i2s, spi) +are disabled, but they can be enabled using Device Tree parameters: + + dtparam=i2c=on,i2s=on,spi=on + +However, this shouldn't be necessary in many use cases because loading an +overlay that requires one of those interfaces will cause it to be enabled +automatically, and it is advisable to only enable interfaces if they are +needed. + +Configuring additional, optional hardware is done using Device Tree overlays +(see below). + +GPIO numbering uses the hardware pin numbering scheme (aka BCM scheme) and +not the physical pin numbers. + +raspi-config +============ + +The Advanced Options section of the raspi-config utility can enable and disable +Device Tree use, as well as toggling the I2C and SPI interfaces. Note that it +is possible to both enable an interface and blacklist the driver, if for some +reason you should want to defer the loading. + +Modules +======= + +As well as describing the hardware, Device Tree also gives enough information +to allow suitable driver modules to be located and loaded, with the corollary +that unneeded modules are not loaded. As a result it should be possible to +remove lines from /etc/modules, and /etc/modprobe.d/raspi-blacklist.conf can +have its contents deleted (or commented out). + +Using Overlays +============== + +Overlays are loaded using the "dtoverlay" config.txt setting. As an example, +consider I2C Real Time Clock drivers. In the pre-DT world these would be loaded +by writing a magic string comprising a device identifier and an I2C address to +a special file in /sys/class/i2c-adapter, having first loaded the driver for +the I2C interface and the RTC device - something like this: + + modprobe i2c-bcm2835 + modprobe rtc-ds1307 + echo ds1307 0x68 > /sys/class/i2c-adapter/i2c-1/new_device + +With DT enabled, this becomes a line in config.txt: + + dtoverlay=i2c-rtc,ds1307 + +This causes the file /boot/overlays/i2c-rtc.dtbo to be loaded and a "node" +describing the DS1307 I2C device to be added to the Device Tree for the Pi. By +default it usees address 0x68, but this can be modified with an additional DT +parameter: + + dtoverlay=i2c-rtc,ds1307,addr=0x68 + +Parameters usually have default values, although certain parameters are +mandatory. See the list of overlays below for a description of the parameters +and their defaults. + +Making new Overlays based on existing Overlays +============================================== + +Recent overlays have been designed in a more general way, so that they can be +adapted to hardware by changing their parameters. When you have additional +hardware with more than one device of a kind, you end up using the same overlay +multiple times with other parameters, e.g. + + # 2 CAN FD interfaces on spi but with different pins + dtoverlay=mcp251xfd,spi0-0,interrupt=25 + dtoverlay=mcp251xfd,spi0-1,interrupt=24 + + # a realtime clock on i2c + dtoverlay=i2c-rtc,pcf85063 + +While this approach does work, it requires knowledge about the hardware design. +It is more feasible to simplify things for the end user by providing a single +overlay as it is done the traditional way. + +A new overlay can be generated by using ovmerge utility. +https://github.com/raspberrypi/utils/blob/master/ovmerge/ovmerge + +To generate an overlay for the above configuration we pass the configuration +to ovmerge and add the -c flag. + + ovmerge -c mcp251xfd-overlay.dts,spi0-0,interrupt=25 \ + mcp251xfd-overlay.dts,spi0-1,interrupt=24 \ + i2c-rtc-overlay.dts,pcf85063 \ + >> merged-overlay.dts + +The -c option writes the command above as a comment into the overlay as +a marker that this overlay is generated and how it was generated. +After compiling the overlay it can be loaded in a single line. + + dtoverlay=merged + +It does the same as the original configuration but without parameters. + +The Overlay and Parameter Reference +=================================== + +N.B. When editing this file, please preserve the indentation levels to make it +simple to parse programmatically. NO HARD TABS. + + +Name: <The base DTB> +Info: Configures the base Raspberry Pi hardware +Load: <loaded automatically> +Params: + ant1 Select antenna 1 (default). CM4 only. + + ant2 Select antenna 2. CM4 only. + + noant Disable both antennas. CM4 only. + + audio Set to "on" to enable the onboard ALSA audio + interface (default "off") + + axiperf Set to "on" to enable the AXI bus performance + monitors. + See /sys/kernel/debug/raspberrypi_axi_monitor + for the results. + + bdaddr Set an alternative Bluetooth address (BDADDR). + The value should be a 6-byte hexadecimal value, + with or without colon separators, written least- + significant-byte first. For example, + bdaddr=06:05:04:03:02:01 + will set the BDADDR to 01:02:03:04:05:06. + + button_debounce Set the debounce delay (in ms) on the power/ + shutdown button (default 50ms) + + cam0_reg Enables CAM 0 regulator. + Only required on CM1 & 3. + + cam0_reg_gpio Set GPIO for CAM 0 regulator. + Default 31 on CM1, 3, and 4S. + Default of GPIO expander 5 on CM4, but override + switches to normal GPIO. + + cam1_reg Enables CAM 1 regulator. + Only required on CM1 & 3. + + cam1_reg_gpio Set GPIO for CAM 1 regulator. + Default 3 on CM1, 3, and 4S. + Default of GPIO expander 5 on CM4, but override + switches to normal GPIO. + + cooling_fan Enables the Pi 5 cooling fan (enabled + automatically by the firmware) + + drm_fb0_rp1_dpi Assign /dev/fb0 to the RP1 DPI output + + drm_fb0_rp1_dsi0 Assign /dev/fb0 to the RP1 DSI0 output + + drm_fb0_rp1_dsi1 Assign /dev/fb0 to the RP1 DSI1 output + + drm_fb0_vc4 Assign /dev/fb0 to the vc4 outputs + + drm_fb1_rp1_dpi Assign /dev/fb1 to the RP1 DPI output + + drm_fb1_rp1_dsi0 Assign /dev/fb1 to the RP1 DSI0 output + + drm_fb1_rp1_dsi1 Assign /dev/fb1 to the RP1 DSI1 output + + drm_fb1_vc4 Assign /dev/fb1 to the vc4 outputs + + drm_fb2_rp1_dpi Assign /dev/fb2 to the RP1 DPI output + + drm_fb2_rp1_dsi0 Assign /dev/fb2 to the RP1 DSI0 output + + drm_fb2_rp1_dsi1 Assign /dev/fb2 to the RP1 DSI1 output + + drm_fb2_vc4 Assign /dev/fb2 to the vc4 outputs + + eee Enable Energy Efficient Ethernet support for + compatible devices (default "on"). See also + "tx_lpi_timer". Pi3B+ only. + + eth_downshift_after Set the number of auto-negotiation failures + after which the 1000Mbps modes are disabled. + Legal values are 2, 3, 4, 5 and 0, where + 0 means never downshift (default 2). Pi3B+ only. + + eth_led0 Set mode of LED0 - amber on Pi3B+ (default "1"), + green on Pi4 (default "0"). + The legal values are: + + Pi3B+ + + 0=link/activity 1=link1000/activity + 2=link100/activity 3=link10/activity + 4=link100/1000/activity 5=link10/1000/activity + 6=link10/100/activity 14=off 15=on + + Pi4 + + 0=Speed/Activity 1=Speed + 2=Flash activity 3=FDX + 4=Off 5=On + 6=Alt 7=Speed/Flash + 8=Link 9=Activity + + eth_led1 Set mode of LED1 - green on Pi3B+ (default "6"), + amber on Pi4 (default "8"). See eth_led0 for + legal values. + + eth_max_speed Set the maximum speed a link is allowed + to negotiate. Legal values are 10, 100 and + 1000 (default 1000). Pi3B+ only. + + hdmi Set to "off" to disable the HDMI interface + (default "on") + + i2c An alias for i2c_arm + + i2c_arm Set to "on" to enable the ARM's i2c interface + (default "off") + + i2c_arm_baudrate Set the baudrate of the ARM's i2c interface + (default "100000") + + i2c_baudrate An alias for i2c_arm_baudrate + + i2c_csi_dsi Set to "on" to enable the i2c_csi_dsi interface + + i2c_csi_dsi0 Set to "on" to enable the i2c_csi_dsi0 interface + + i2c_csi_dsi1 Set to "on" to enable the i2c_csi_dsi1 interface + + i2c_vc Set to "on" to enable the i2c interface + usually reserved for the VideoCore processor + (default "off") + + i2c_vc_baudrate Set the baudrate of the VideoCore i2c interface + (default "100000") + + i2s Set to "on" to enable the i2s interface + (default "off") + + i2s_dma4 Use to enable 40-bit DMA on the i2s interface + (the assigned value doesn't matter) + (2711 only) + + krnbt Set to "off" to disable autoprobing of Bluetooth + driver without need of hciattach/btattach + (default "on") + + krnbt_baudrate Set the baudrate of the PL011 UART when used + with krnbt=on + + nvme Alias for "pciex1" (2712 only) + + pcie Set to "off" to disable the PCIe interface + (default "on") + (2711 only, but not applicable on CM4S) + N.B. USB-A ports on 4B are subsequently disabled + + pcie_tperst_clk_ms Add N milliseconds between PCIe reference clock + activation and PERST# deassertion + (CM4 and 2712, default "0") + + pciex1 Set to "on" to enable the external PCIe link + (2712 only, default "off") + + pciex1_gen Sets the PCIe "GEN"/speed for the external PCIe + link (2712 only, default "2") + + pciex1_no_l0s Set to "on" to disable ASPM L0s on the external + PCIe link for devices that have broken + implementations (2712 only, default "off") + + pciex1_tperst_clk_ms Alias for pcie_tperst_clk_ms + (2712 only, default "0") + + spi Set to "on" to enable the spi interfaces + (default "off") + + spi_dma4 Use to enable 40-bit DMA on spi interfaces + (the assigned value doesn't matter) + (2711 only) + + random Set to "on" to enable the hardware random + number generator (default "on") + + rtc_bbat_vchg Set the RTC backup battery charging voltage in + microvolts. If set to 0 or not specified, the + trickle charger is disabled. + (2712 only, default "0") + + sd Set to "off" to disable the SD card (or eMMC on + non-lite SKU of CM4). + (default "on") + + sd_overclock Clock (in MHz) to use when the MMC framework + requests 50MHz + + sd_poll_once Looks for a card once after booting. Useful + for network booting scenarios to avoid the + overhead of continuous polling. N.B. Using + this option restricts the system to using a + single card per boot (or none at all). + (default off) + + sd_force_pio Disable DMA support for SD driver (default off) + + sd_pio_limit Number of blocks above which to use DMA for + SD card (default 1) + + sd_debug Enable debug output from SD driver (default off) + + sdio_overclock Clock (in MHz) to use when the MMC framework + requests 50MHz for the SDIO/WLAN interface. + + suspend Make the power button trigger a suspend rather + than a power-off (2712 only, default "off") + + tx_lpi_timer Set the delay in microseconds between going idle + and entering the low power state (default 600). + Requires EEE to be enabled - see "eee". + + uart0 Set to "off" to disable uart0 (default "on") + + uart0_console Move the kernel boot console to UART0 on pins + 6, 8 and 10 of the 40-way header (2712 only, + default "off") + + uart1 Set to "on" or "off" to enable or disable uart1 + (default varies) + + watchdog Set to "on" to enable the hardware watchdog + (default "off") + + wifiaddr Set an alternative WiFi MAC address. + The value should be a 6-byte hexadecimal value, + with or without colon separators, written in the + natural (big-endian) order. + + act_led_trigger Choose which activity the LED tracks. + Use "heartbeat" for a nice load indicator. + (default "mmc") + + act_led_activelow Set to "on" to invert the sense of the LED + (default "off") + N.B. For Pi 3B, 3B+, 3A+ and 4B, use the act-led + overlay. + + act_led_gpio Set which GPIO to use for the activity LED + (in case you want to connect it to an external + device) + (default "16" on a non-Plus board, "47" on a + Plus or Pi 2) + N.B. For Pi 3B, 3B+, 3A+ and 4B, use the act-led + overlay. + + pwr_led_trigger + pwr_led_activelow + pwr_led_gpio + As for act_led_*, but using the PWR LED. + Not available on Model A/B boards. + + N.B. It is recommended to only enable those interfaces that are needed. + Leaving all interfaces enabled can lead to unwanted behaviour (i2c_vc + interfering with Pi Camera, I2S and SPI hogging GPIO pins, etc.) + Note also that i2c, i2c_arm and i2c_vc are aliases for the physical + interfaces i2c0 and i2c1. Use of the numeric variants is still possible + but deprecated because the ARM/VC assignments differ between board + revisions. The same board-specific mapping applies to i2c_baudrate, + and the other i2c baudrate parameters. + + +Name: act-led +Info: Pi 3B, 3B+, 3A+ and 4B use a GPIO expander to drive the LEDs which can + only be accessed from the VPU. There is a special driver for this with a + separate DT node, which has the unfortunate consequence of breaking the + act_led_gpio and act_led_activelow dtparams. + This overlay changes the GPIO controller back to the standard one and + restores the dtparams. +Load: dtoverlay=act-led,<param>=<val> +Params: activelow Set to "on" to invert the sense of the LED + (default "off") + + gpio Set which GPIO to use for the activity LED + (in case you want to connect it to an external + device) + REQUIRED + + +Name: adafruit-st7735r +Info: Overlay for the SPI-connected Adafruit 1.8" 160x128 or 128x128 displays, + based on the ST7735R chip. + This overlay uses the newer DRM/KMS "Tiny" driver. +Load: dtoverlay=adafruit-st7735r,<param>=<val> +Params: 128x128 Select the 128x128 driver (default 160x128) + rotate Display rotation {0,90,180,270} (default 90) + speed SPI bus speed in Hz (default 4000000) + dc_pin GPIO pin for D/C (default 24) + reset_pin GPIO pin for RESET (default 25) + led_pin GPIO used to control backlight (default 18) + + +Name: adafruit18 +Info: Overlay for the SPI-connected Adafruit 1.8" display (based on the + ST7735R chip). It includes support for the "green tab" version. + This overlay uses the older fbtft driver. +Load: dtoverlay=adafruit18,<param>=<val> +Params: green Use the adafruit18_green variant. + rotate Display rotation {0,90,180,270} + speed SPI bus speed in Hz (default 4000000) + fps Display frame rate in Hz + bgr Enable BGR mode (default off) + debug Debug output level {0-7} + dc_pin GPIO pin for D/C (default 24) + reset_pin GPIO pin for RESET (default 25) + led_pin GPIO used to control backlight (default 18) + + +Name: adau1977-adc +Info: Overlay for activation of ADAU1977 ADC codec over I2C for control + and I2S for data. +Load: dtoverlay=adau1977-adc +Params: <None> + + +Name: adau7002-simple +Info: Overlay for the activation of ADAU7002 stereo PDM to I2S converter. +Load: dtoverlay=adau7002-simple,<param>=<val> +Params: card-name Override the default, "adau7002", card name. + + +Name: ads1015 +Info: Overlay for activation of Texas Instruments ADS1015 ADC over I2C +Load: dtoverlay=ads1015,<param>=<val> +Params: addr I2C bus address of device. Set based on how the + addr pin is wired. (default=0x48 assumes addr + is pulled to GND) + cha_enable Enable virtual channel a. (default=true) + cha_cfg Set the configuration for virtual channel a. + (default=4 configures this channel for the + voltage at A0 with respect to GND) + cha_datarate Set the datarate (samples/sec) for this channel. + (default=4 sets 1600 sps) + cha_gain Set the gain of the Programmable Gain + Amplifier for this channel. (default=2 sets the + full scale of the channel to 2.048 Volts) + + Channel (ch) parameters can be set for each enabled channel. + A maximum of 4 channels can be enabled (letters a thru d). + For more information refer to the device datasheet at: + http://www.ti.com/lit/ds/symlink/ads1015.pdf + + +Name: ads1115 +Info: Texas Instruments ADS1115 ADC +Load: dtoverlay=ads1115,<param>[=<val>] +Params: addr I2C bus address of device. Set based on how the + addr pin is wired. (default=0x48 assumes addr + is pulled to GND) + cha_enable Enable virtual channel a. + cha_cfg Set the configuration for virtual channel a. + (default=4 configures this channel for the + voltage at A0 with respect to GND) + cha_datarate Set the datarate (samples/sec) for this channel. + (default=7 sets 860 sps) + cha_gain Set the gain of the Programmable Gain + Amplifier for this channel. (Default 1 sets the + full scale of the channel to 4.096 Volts) + i2c0 Choose the I2C0 bus on GPIOs 0&1 + i2c_csi_dsi Choose the I2C0 bus on GPIOs 44&45 + i2c3 Choose the I2C3 bus (configure with the i2c3 + overlay - BCM2711 only) + i2c4 Choose the I2C4 bus (configure with the i2c4 + overlay - BCM2711 only) + i2c5 Choose the I2C5 bus (configure with the i2c5 + overlay - BCM2711 only) + i2c6 Choose the I2C6 bus (configure with the i2c6 + overlay - BCM2711 only) + + Channel parameters can be set for each enabled channel. + A maximum of 4 channels can be enabled (letters a thru d). + For more information refer to the device datasheet at: + http://www.ti.com/lit/ds/symlink/ads1115.pdf + + +Name: ads7846 +Info: ADS7846 Touch controller +Load: dtoverlay=ads7846,<param>=<val> +Params: cs SPI bus Chip Select (default 1) + speed SPI bus speed (default 2MHz, max 3.25MHz) + penirq GPIO used for PENIRQ. REQUIRED + penirq_pull Set GPIO pull (default 0=none, 2=pullup) + swapxy Swap x and y axis + xmin Minimum value on the X axis (default 0) + ymin Minimum value on the Y axis (default 0) + xmax Maximum value on the X axis (default 4095) + ymax Maximum value on the Y axis (default 4095) + pmin Minimum reported pressure value (default 0) + pmax Maximum reported pressure value (default 65535) + xohms Touchpanel sensitivity (X-plate resistance) + (default 400) + + penirq is required and usually xohms (60-100) has to be set as well. + Apart from that, pmax (255) and swapxy are also common. + The rest of the calibration can be done with xinput-calibrator. + See: github.com/notro/fbtft/wiki/FBTFT-on-Raspian + Device Tree binding document: + www.kernel.org/doc/Documentation/devicetree/bindings/input/ads7846.txt + + +Name: adv7282m +Info: Analog Devices ADV7282M analogue video to CSI2 bridge. + Uses Unicam1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=adv7282m,<param>=<val> +Params: addr Overrides the I2C address (default 0x21) + media-controller Configure use of Media Controller API for + configuring the sensor (default off) + + +Name: adv728x-m +Info: Analog Devices ADV728[0|1|2]-M analogue video to CSI2 bridges. + This is a wrapper for adv7282m, and defaults to ADV7282M. +Load: dtoverlay=adv728x-m,<param>=<val> +Params: addr Overrides the I2C address (default 0x21) + adv7280m Select ADV7280-M. + adv7281m Select ADV7281-M. + adv7281ma Select ADV7281-MA. + media-controller Configure use of Media Controller API for + configuring the sensor (default off) + + +Name: akkordion-iqdacplus +Info: Configures the Digital Dreamtime Akkordion Music Player (based on the + OEM IQAudIO DAC+ or DAC Zero module). +Load: dtoverlay=akkordion-iqdacplus,<param>=<val> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + Digital volume control. Enable with + dtoverlay=akkordion-iqdacplus,24db_digital_gain + (The default behaviour is that the Digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24db_digital_gain parameter, the Digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) + + +Name: allo-boss-dac-pcm512x-audio +Info: Configures the Allo Boss DAC audio cards. +Load: dtoverlay=allo-boss-dac-pcm512x-audio,<param> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + Digital volume control. Enable with + "dtoverlay=allo-boss-dac-pcm512x-audio, + 24db_digital_gain" + (The default behaviour is that the Digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24db_digital_gain parameter, the Digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) + slave Force Boss DAC into slave mode, using Pi a + master for bit clock and frame clock. Enable + with "dtoverlay=allo-boss-dac-pcm512x-audio, + slave" + + +Name: allo-boss2-dac-audio +Info: Configures the Allo Boss2 DAC audio card +Load: dtoverlay=allo-boss2-dac-audio +Params: <None> + + +Name: allo-digione +Info: Configures the Allo Digione audio card +Load: dtoverlay=allo-digione +Params: <None> + + +Name: allo-katana-dac-audio +Info: Configures the Allo Katana DAC audio card +Load: dtoverlay=allo-katana-dac-audio +Params: <None> + + +Name: allo-piano-dac-pcm512x-audio +Info: Configures the Allo Piano DAC (2.0/2.1) audio cards. + (NB. This initial support is for 2.0 channel audio ONLY! ie. stereo. + The subwoofer outputs on the Piano 2.1 are not currently supported!) +Load: dtoverlay=allo-piano-dac-pcm512x-audio,<param> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + Digital volume control. + (The default behaviour is that the Digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24db_digital_gain parameter, the Digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) + + +Name: allo-piano-dac-plus-pcm512x-audio +Info: Configures the Allo Piano DAC (2.1) audio cards. +Load: dtoverlay=allo-piano-dac-plus-pcm512x-audio,<param> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + Digital volume control. + (The default behaviour is that the Digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24db_digital_gain parameter, the Digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) + glb_mclk This option is only with Kali board. If enabled, + MCLK for Kali is used and PLL is disabled for + better voice quality. (default Off) + + +Name: anyspi +Info: Universal device tree overlay for SPI devices + + Just specify the SPI address and device name ("compatible" property). + This overlay lacks any device-specific parameter support! + + For devices on spi1 or spi2, the interfaces should be enabled + with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays. + + Examples: + 1. SPI NOR flash on spi0.1, maximum SPI clock frequency 45MHz: + dtoverlay=anyspi:spi0-1,dev="jedec,spi-nor",speed=45000000 + 2. MCP3204 ADC on spi1.2, maximum SPI clock frequency 500kHz: + dtoverlay=anyspi:spi1-2,dev="microchip,mcp3204" +Load: dtoverlay=anyspi,<param>=<val> +Params: spi<n>-<m> Configure device at spi<n>, cs<m> + (boolean, required) + dev Set device name to search compatible module + (string, required) + speed Set SPI clock frequency in Hz + (integer, optional, default 500000) + + +Name: apds9960 +Info: Configures the AVAGO APDS9960 digital proximity, ambient light, RGB and + gesture sensor +Load: dtoverlay=apds9960,<param>=<val> +Params: gpiopin GPIO used for INT (default 4) + noints Disable the interrupt GPIO line. + + +Name: applepi-dac +Info: Configures the Orchard Audio ApplePi-DAC audio card +Load: dtoverlay=applepi-dac +Params: <None> + + +Name: arducam-64mp +Info: Arducam 64MP camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=arducam-64mp,<param>=<val> +Params: rotation Mounting rotation of the camera sensor (0 or + 180, default 0) + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + vcm Select lens driver state. Default is enabled, + but vcm=off will disable. + + +Name: arducam-pivariety +Info: Arducam Pivariety camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=arducam-pivariety,<param>=<val> +Params: rotation Mounting rotation of the camera sensor (0 or + 180, default 0) + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + + +Name: at86rf233 +Info: Configures the Atmel AT86RF233 802.15.4 low-power WPAN transceiver, + connected to spi0.0 +Load: dtoverlay=at86rf233,<param>=<val> +Params: interrupt GPIO used for INT (default 23) + reset GPIO used for Reset (default 24) + sleep GPIO used for Sleep (default 25) + speed SPI bus speed in Hz (default 3000000) + trim Fine tuning of the internal capacitance + arrays (0=+0pF, 15=+4.5pF, default 15) + + +Name: audioinjector-addons +Info: Configures the audioinjector.net audio add on soundcards +Load: dtoverlay=audioinjector-addons,<param>=<val> +Params: non-stop-clocks Keeps the clocks running even when the stream + is paused or stopped (default off) + + +Name: audioinjector-bare-i2s +Info: Configures the audioinjector.net audio bare i2s soundcard +Load: dtoverlay=audioinjector-bare-i2s +Params: <None> + + +Name: audioinjector-isolated-soundcard +Info: Configures the audioinjector.net isolated soundcard +Load: dtoverlay=audioinjector-isolated-soundcard +Params: <None> + + +Name: audioinjector-ultra +Info: Configures the audioinjector.net ultra soundcard +Load: dtoverlay=audioinjector-ultra +Params: <None> + + +Name: audioinjector-wm8731-audio +Info: Configures the audioinjector.net audio add on soundcard +Load: dtoverlay=audioinjector-wm8731-audio +Params: <None> + + +Name: audiosense-pi +Info: Configures the audiosense-pi add on soundcard + For more information refer to + https://gitlab.com/kakar0t/audiosense-pi +Load: dtoverlay=audiosense-pi +Params: <None> + + +Name: audremap +Info: Switches PWM sound output to GPIOs on the 40-pin header +Load: dtoverlay=audremap,<param>=<val> +Params: swap_lr Reverse the channel allocation, which will also + swap the audio jack outputs (default off) + enable_jack Don't switch off the audio jack output. Does + nothing on BCM2711 (default off) + pins_12_13 Select GPIOs 12 & 13 (default) + pins_18_19 Select GPIOs 18 & 19 + pins_40_41 Select GPIOs 40 & 41 (not available on CM4, used + for other purposes) + pins_40_45 Select GPIOs 40 & 45 (don't use on BCM2711 - the + pins are on different controllers) + + +Name: balena-fin +Info: Overlay that enables WLAN, Bluetooth and the GPIO expander on the + balenaFin carrier board for the Raspberry Pi Compute Module 3/3+ Lite. +Load: dtoverlay=balena-fin +Params: <None> + + +Name: bmp085_i2c-sensor +Info: This overlay is now deprecated - see i2c-sensor +Load: <Deprecated> + + +Name: camera-mux-2port +Info: Configures a 2 port camera multiplexer + Note that currently ALL IMX290 modules share a common clock, therefore + all modules will need to have the same clock frequency. +Load: dtoverlay=camera-mux-2port,<param>=<val> +Params: cam0-arducam-64mp Select Arducam64MP for camera on port 0 + cam0-imx219 Select IMX219 for camera on port 0 + cam0-imx258 Select IMX258 for camera on port 0 + cam0-imx290 Select IMX290 for camera on port 0 + cam0-imx477 Select IMX477 for camera on port 0 + cam0-imx519 Select IMX519 for camera on port 0 + cam0-imx708 Select IMX708 for camera on port 0 + cam0-ov2311 Select OV2311 for camera on port 0 + cam0-ov5647 Select OV5647 for camera on port 0 + cam0-ov64a40 Select OV64A40 for camera on port 0 + cam0-ov7251 Select OV7251 for camera on port 0 + cam0-ov9281 Select OV9281 for camera on port 0 + cam0-imx290-clk-freq Set clock frequency for an IMX290 on port 0 + cam1-arducam-64mp Select Arducam64MP for camera on port 1 + cam1-imx219 Select IMX219 for camera on port 1 + cam1-imx258 Select IMX258 for camera on port 1 + cam1-imx290 Select IMX290 for camera on port 1 + cam1-imx477 Select IMX477 for camera on port 1 + cam1-imx519 Select IMX519 for camera on port 1 + cam1-imx708 Select IMX708 for camera on port 1 + cam1-ov2311 Select OV2311 for camera on port 1 + cam1-ov5647 Select OV5647 for camera on port 1 + cam1-ov64a40 Select OV64A40 for camera on port 1 + cam1-ov7251 Select OV7251 for camera on port 1 + cam1-ov9281 Select OV9281 for camera on port 1 + cam1-imx290-clk-freq Set clock frequency for an IMX290 on port 1 + + cam0 Connect the mux to CAM0 port (default is CAM1) + + +Name: camera-mux-4port +Info: Configures a 4 port camera multiplexer + Note that currently ALL IMX290 modules share a common clock, therefore + all modules will need to have the same clock frequency. +Load: dtoverlay=camera-mux-4port,<param>=<val> +Params: cam0-arducam-64mp Select Arducam64MP for camera on port 0 + cam0-imx219 Select IMX219 for camera on port 0 + cam0-imx258 Select IMX258 for camera on port 0 + cam0-imx290 Select IMX290 for camera on port 0 + cam0-imx477 Select IMX477 for camera on port 0 + cam0-imx519 Select IMX519 for camera on port 0 + cam0-imx708 Select IMX708 for camera on port 0 + cam0-ov2311 Select OV2311 for camera on port 0 + cam0-ov5647 Select OV5647 for camera on port 0 + cam0-ov64a40 Select OV64A40 for camera on port 0 + cam0-ov7251 Select OV7251 for camera on port 0 + cam0-ov9281 Select OV9281 for camera on port 0 + cam0-imx290-clk-freq Set clock frequency for an IMX290 on port 0 + cam1-arducam-64mp Select Arducam64MP for camera on port 1 + cam1-imx219 Select IMX219 for camera on port 1 + cam1-imx258 Select IMX258 for camera on port 1 + cam1-imx290 Select IMX290 for camera on port 1 + cam1-imx477 Select IMX477 for camera on port 1 + cam1-imx519 Select IMX519 for camera on port 1 + cam1-imx708 Select IMX708 for camera on port 1 + cam1-ov2311 Select OV2311 for camera on port 1 + cam1-ov5647 Select OV5647 for camera on port 1 + cam1-ov64a40 Select OV64A40 for camera on port 1 + cam1-ov7251 Select OV7251 for camera on port 1 + cam1-ov9281 Select OV9281 for camera on port 1 + cam1-imx290-clk-freq Set clock frequency for an IMX290 on port 1 + cam2-arducam-64mp Select Arducam64MP for camera on port 2 + cam2-imx219 Select IMX219 for camera on port 2 + cam2-imx258 Select IMX258 for camera on port 2 + cam2-imx290 Select IMX290 for camera on port 2 + cam2-imx477 Select IMX477 for camera on port 2 + cam2-imx519 Select IMX519 for camera on port 2 + cam2-imx708 Select IMX708 for camera on port 2 + cam2-ov2311 Select OV2311 for camera on port 2 + cam2-ov5647 Select OV5647 for camera on port 2 + cam2-ov64a40 Select OV64A40 for camera on port 2 + cam2-ov7251 Select OV7251 for camera on port 2 + cam2-ov9281 Select OV9281 for camera on port 2 + cam2-imx290-clk-freq Set clock frequency for an IMX290 on port 2 + cam3-arducam-64mp Select Arducam64MP for camera on port 3 + cam3-imx219 Select IMX219 for camera on port 3 + cam3-imx258 Select IMX258 for camera on port 3 + cam3-imx290 Select IMX290 for camera on port 3 + cam3-imx477 Select IMX477 for camera on port 3 + cam3-imx519 Select IMX519 for camera on port 3 + cam3-imx708 Select IMX708 for camera on port 3 + cam3-ov2311 Select OV2311 for camera on port 3 + cam3-ov5647 Select OV5647 for camera on port 3 + cam3-ov64a40 Select OV64A40 for camera on port 3 + cam3-ov7251 Select OV7251 for camera on port 3 + cam3-ov9281 Select OV9281 for camera on port 3 + cam3-imx290-clk-freq Set clock frequency for an IMX290 on port 3 + + cam0 Connect the mux to CAM0 port (default is CAM1) + + +Name: cap1106 +Info: Enables the ability to use the cap1106 touch sensor as a keyboard +Load: dtoverlay=cap1106,<param>=<val> +Params: int_pin GPIO pin for interrupt signal (default 23) + + +Name: chipdip-dac +Info: Configures Chip Dip audio cards. +Load: dtoverlay=chipdip-dac +Params: <None> + + +Name: cirrus-wm5102 +Info: Configures the Cirrus Logic Audio Card +Load: dtoverlay=cirrus-wm5102 +Params: <None> + + +Name: cm-swap-i2c0 +Info: Largely for Compute Modules 1&3 where the original instructions for + adding a camera used GPIOs 0&1 for CAM1 and 28&29 for CAM0, whilst all + other platforms use 28&29 (or 44&45) for CAM1. + The default assignment through using this overlay is for + i2c0 to use 28&29, and i2c10 (aka i2c_csi_dsi) to use 28&29, but the + overrides allow this to be changed. +Load: dtoverlay=cm-swap-i2c0,<param>=<val> +Params: i2c0-gpio0 Use GPIOs 0&1 for i2c0 + i2c0-gpio28 Use GPIOs 28&29 for i2c0 (default) + i2c0-gpio44 Use GPIOs 44&45 for i2c0 + i2c10-gpio0 Use GPIOs 0&1 for i2c0 (default) + i2c10-gpio28 Use GPIOs 28&29 for i2c0 + i2c10-gpio44 Use GPIOs 44&45 for i2c0 + + +Name: cma +Info: Set custom CMA sizes, only use if you know what you are doing, might + clash with other overlays like vc4-fkms-v3d and vc4-kms-v3d. +Load: dtoverlay=cma,<param>=<val> +Params: cma-512 CMA is 512MB (needs 1GB) + cma-448 CMA is 448MB (needs 1GB) + cma-384 CMA is 384MB (needs 1GB) + cma-320 CMA is 320MB (needs 1GB) + cma-256 CMA is 256MB (needs 1GB) + cma-192 CMA is 192MB (needs 1GB) + cma-128 CMA is 128MB + cma-96 CMA is 96MB + cma-64 CMA is 64MB + cma-size CMA size in bytes, 4MB aligned + cma-default Use upstream's default value + + +Name: crystalfontz-cfa050_pi_m +Info: Configures the Crystalfontz CFA050-PI-M series of Raspberry Pi CM4 + based modules using the CFA7201280A0_050Tx 7" TFT LCD displays, + with or without capacitive touch screen. + Requires use of vc4-kms-v3d. +Load: dtoverlay=crystalfontz-cfa050_pi_m,<param>=<val> +Params: captouch Enable capacitive touch display + + +Name: cutiepi-panel +Info: 8" TFT LCD display and touch panel used by cutiepi.io +Load: dtoverlay=cutiepi-panel +Params: <None> + + +Name: dacberry400 +Info: Configures the dacberry400 add on soundcard +Load: dtoverlay=dacberry400 +Params: <None> + + +Name: dht11 +Info: Overlay for the DHT11/DHT21/DHT22 humidity/temperature sensors + Also sometimes found with the part number(s) AM230x. +Load: dtoverlay=dht11,<param>=<val> +Params: gpiopin GPIO connected to the sensor's DATA output. + (default 4) + + +Name: dionaudio-kiwi +Info: Configures the Dion Audio KIWI STREAMER +Load: dtoverlay=dionaudio-kiwi +Params: <None> + + +Name: dionaudio-loco +Info: Configures the Dion Audio LOCO DAC-AMP +Load: dtoverlay=dionaudio-loco +Params: <None> + + +Name: dionaudio-loco-v2 +Info: Configures the Dion Audio LOCO-V2 DAC-AMP +Load: dtoverlay=dionaudio-loco-v2,<param>=<val> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + Digital volume control. Enable with + "dtoverlay=hifiberry-dacplus,24db_digital_gain" + (The default behaviour is that the Digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24dB_digital_gain parameter, the Digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) + + +Name: disable-bt +Info: Disable onboard Bluetooth on Bluetooth-capable Raspberry Pis. On Pis + prior to Pi 5 this restores UART0/ttyAMA0 over GPIOs 14 & 15. +Load: dtoverlay=disable-bt +Params: <None> + + +Name: disable-bt-pi5 +Info: See disable-bt + + +Name: disable-emmc2 +Info: Disable EMMC2 controller on BCM2711. + The allows the onboard EMMC storage on Compute Module 4 to be disabled + e.g. if a fault has occurred. +Load: dtoverlay=disable-emmc2 +Params: <None> + + +Name: disable-wifi +Info: Disable onboard WLAN on WiFi-capable Raspberry Pis. +Load: dtoverlay=disable-wifi +Params: <None> + + +Name: disable-wifi-pi5 +Info: See disable-wifi + + +Name: dpi18 +Info: Overlay for a generic 18-bit DPI display + This uses GPIOs 0-21 (so no I2C, uart etc.), and activates the output + 2-3 seconds after the kernel has started. +Load: dtoverlay=dpi18 +Params: <None> + + +Name: dpi18cpadhi +Info: Overlay for a generic 18-bit DPI display (in 'mode 6' connection scheme) + This uses GPIOs 0-9,12-17,20-25 (so no I2C, uart etc.), and activates + the output 3-3 seconds after the kernel has started. +Load: dtoverlay=dpi18cpadhi +Params: <None> + + +Name: dpi24 +Info: Overlay for a generic 24-bit DPI display + This uses GPIOs 0-27 (so no I2C, uart etc.), and activates the output + 2-3 seconds after the kernel has started. +Load: dtoverlay=dpi24 +Params: <None> + + +Name: draws +Info: Configures the NW Digital Radio DRAWS Hat + + The board includes an ADC to measure various board values and also + provides two analog user inputs on the expansion header. The ADC + can be configured for various sample rates and gain values to adjust + the input range. Tables describing the two parameters follow. + + ADC Gain Values: + 0 = +/- 6.144V + 1 = +/- 4.096V + 2 = +/- 2.048V + 3 = +/- 1.024V + 4 = +/- 0.512V + 5 = +/- 0.256V + 6 = +/- 0.256V + 7 = +/- 0.256V + + ADC Datarate Values: + 0 = 128sps + 1 = 250sps + 2 = 490sps + 3 = 920sps + 4 = 1600sps (default) + 5 = 2400sps + 6 = 3300sps + 7 = 3300sps +Load: dtoverlay=draws,<param>=<val> +Params: draws_adc_ch4_gain Sets the full scale resolution of the ADCs + input voltage sensor (default 1) + + draws_adc_ch4_datarate Sets the datarate of the ADCs input voltage + sensor + + draws_adc_ch5_gain Sets the full scale resolution of the ADCs + 5V rail voltage sensor (default 1) + + draws_adc_ch5_datarate Sets the datarate of the ADCs 4V rail voltage + sensor + + draws_adc_ch6_gain Sets the full scale resolution of the ADCs + AIN2 input (default 2) + + draws_adc_ch6_datarate Sets the datarate of the ADCs AIN2 input + + draws_adc_ch7_gain Sets the full scale resolution of the ADCs + AIN3 input (default 2) + + draws_adc_ch7_datarate Sets the datarate of the ADCs AIN3 input + + alsaname Name of the ALSA audio device (default "draws") + + +Name: dwc-otg +Info: Selects the dwc_otg USB controller driver which has fiq support. This + is the default on all except the Pi Zero which defaults to dwc2. +Load: dtoverlay=dwc-otg +Params: <None> + + +Name: dwc2 +Info: Selects the dwc2 USB controller driver +Load: dtoverlay=dwc2,<param>=<val> +Params: dr_mode Dual role mode: "host", "peripheral" or "otg" + + g-rx-fifo-size Size of rx fifo size in gadget mode + + g-np-tx-fifo-size Size of non-periodic tx fifo size in gadget + mode + + +[ The ds1307-rtc overlay has been deleted. See i2c-rtc. ] + + +Name: edt-ft5406 +Info: Overlay for the EDT FT5406 touchscreen. + This works with the Raspberry Pi 7" touchscreen when not being polled + by the firmware. + By default the overlay uses the i2c_csi_dsi I2C interface, but this + can be overridden + You MUST use either "disable_touchscreen=1" or "ignore_lcd=1" in + config.txt to stop the firmware polling the touchscreen. +Load: dtoverlay=edt-ft5406,<param>=<val> +Params: sizex Touchscreen size x (default 800) + sizey Touchscreen size y (default 480) + invx Touchscreen inverted x axis + invy Touchscreen inverted y axis + swapxy Touchscreen swapped x y axis + i2c0 Choose the I2C0 bus on GPIOs 0&1 + i2c1 Choose the I2C1 bus on GPIOs 2&3 + i2c3 Choose the I2C3 bus (configure with the i2c3 + overlay - BCM2711 only) + i2c4 Choose the I2C4 bus (configure with the i2c4 + overlay - BCM2711 only) + i2c5 Choose the I2C5 bus (configure with the i2c5 + overlay - BCM2711 only) + i2c6 Choose the I2C6 bus (configure with the i2c6 + overlay - BCM2711 only) + addr Sets the address for the touch controller. Note + that the device must be configured to use the + specified address. + + +Name: enc28j60 +Info: Overlay for the Microchip ENC28J60 Ethernet Controller on SPI0 +Load: dtoverlay=enc28j60,<param>=<val> +Params: int_pin GPIO used for INT (default 25) + + speed SPI bus speed (default 12000000) + + +Name: enc28j60-spi2 +Info: Overlay for the Microchip ENC28J60 Ethernet Controller on SPI2 +Load: dtoverlay=enc28j60-spi2,<param>=<val> +Params: int_pin GPIO used for INT (default 39) + + speed SPI bus speed (default 12000000) + + +Name: exc3000 +Info: Enables I2C connected EETI EXC3000 multiple touch controller using + GPIO 4 (pin 7 on GPIO header) for interrupt. +Load: dtoverlay=exc3000,<param>=<val> +Params: interrupt GPIO used for interrupt (default 4) + sizex Touchscreen size x (default 4096) + sizey Touchscreen size y (default 4096) + invx Touchscreen inverted x axis + invy Touchscreen inverted y axis + swapxy Touchscreen swapped x y axis + + +Name: fbtft +Info: Overlay for SPI-connected displays using the fbtft drivers. + + This overlay seeks to replace the functionality provided by fbtft_device + which is now gone from the kernel. + + Most displays from fbtft_device have been ported over. + Example: + dtoverlay=fbtft,spi0-0,rpi-display,reset_pin=23,dc_pin=24,led_pin=18,rotate=270 + + It is also possible to specify the controller (this will use the default + init sequence in the driver). + Example: + dtoverlay=fbtft,spi0-0,ili9341,bgr,reset_pin=23,dc_pin=24,led_pin=18,rotate=270 + + For devices on spi1 or spi2, the interfaces should be enabled + with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays. + + The following features of fbtft_device have not been ported over: + - parallel bus is not supported + - the init property which overrides the controller initialization + sequence is not supported as a parameter due to memory limitations in + the bootloader responsible for applying the overlay. + + See https://github.com/notro/fbtft/wiki/FBTFT-RPI-overlays for how to + create an overlay. + +Load: dtoverlay=fbtft,<param>=<val> +Params: + spi<n>-<m> Configure device at spi<n>, cs<m> + (boolean, required) + speed SPI bus speed in Hz (default 32000000) + cpha Shifted clock phase (CPHA) mode + cpol Inverse clock polarity (CPOL) mode + + adafruit18 Adafruit 1.8 + adafruit22 Adafruit 2.2 (old) + adafruit22a Adafruit 2.2 + adafruit28 Adafruit 2.8 + adafruit13m Adafruit 1.3 OLED + admatec_c-berry28 C-Berry28 + dogs102 EA DOGS102 + er_tftm050_2 ER-TFTM070-2 + er_tftm070_5 ER-TFTM070-5 + ew24ha0 EW24HA0 + ew24ha0_9bit EW24HA0 in 9-bit mode + freetronicsoled128 Freetronics OLED128 + hy28a HY28A + hy28b HY28B + itdb28_spi ITDB02-2.8 with SPI interface circuit + mi0283qt-2 Watterott MI0283QT-2 + mi0283qt-9a Watterott MI0283QT-9A + nokia3310 Nokia 3310 + nokia3310a Nokia 3310a + nokia5110 Nokia 5110 + piscreen PiScreen + pitft Adafruit PiTFT 2.8 + pioled ILSoft OLED + rpi-display Watterott rpi-display + sainsmart18 Sainsmart 1.8 + sainsmart32_spi Sainsmart 3.2 with SPI interfce circuit + tinylcd35 TinyLCD 3.5 + tm022hdh26 Tianma TM022HDH26 + tontec35_9481 Tontect 3.5 with ILI9481 controller + tontec35_9486 Tontect 3.5 with ILI9486 controller + waveshare32b Waveshare 3.2 + waveshare22 Waveshare 2.2 + + bd663474 BD663474 display controller + hx8340bn HX8340BN display controller + hx8347d HX8347D display controller + hx8353d HX8353D display controller + hx8357d HX8357D display controller + ili9163 ILI9163 display controller + ili9320 ILI9320 display controller + ili9325 ILI9325 display controller + ili9340 ILI9340 display controller + ili9341 ILI9341 display controller + ili9481 ILI9481 display controller + ili9486 ILI9486 display controller + pcd8544 PCD8544 display controller + ra8875 RA8875 display controller + s6d02a1 S6D02A1 display controller + s6d1121 S6D1121 display controller + seps525 SEPS525 display controller + sh1106 SH1106 display controller + ssd1289 SSD1289 display controller + ssd1305 SSD1305 display controller + ssd1306 SSD1306 display controller + ssd1325 SSD1325 display controller + ssd1331 SSD1331 display controller + ssd1351 SSD1351 display controller + st7735r ST7735R display controller + st7789v ST7789V display controller + tls8204 TLS8204 display controller + uc1611 UC1611 display controller + uc1701 UC1701 display controller + upd161704 UPD161704 display controller + + width Display width in pixels + height Display height in pixels + regwidth Display controller register width (default is + driver specific) + buswidth Display bus interface width (default 8) + debug Debug output level {0-7} + rotate Display rotation {0, 90, 180, 270} (counter + clockwise). Not supported by all drivers. + bgr Enable BGR mode (default off). Use if Red and + Blue are swapped. Not supported by all drivers. + fps Frames per second (default 30). In effect this + states how long the driver will wait after video + memory has been changed until display update + transfer is started. + txbuflen Length of the FBTFT transmit buffer + (default 4096) + startbyte Sets the Start byte used by fb_ili9320, + fb_ili9325 and fb_hx8347d. Common value is 0x70. + gamma String representation of Gamma Curve(s). Driver + specific. Not supported by all drivers. + reset_pin GPIO pin for RESET + dc_pin GPIO pin for D/C + led_pin GPIO pin for LED backlight + + +Name: fe-pi-audio +Info: Configures the Fe-Pi Audio Sound Card +Load: dtoverlay=fe-pi-audio +Params: <None> + + +Name: fsm-demo +Info: A demonstration of the gpio-fsm driver. The GPIOs are chosen to work + nicely with a "traffic-light" display of red, amber and green LEDs on + GPIOs 7, 8 and 25 respectively. +Load: dtoverlay=fsm-demo,<param>=<val> +Params: fsm_debug Enable debug logging (default off) + + +Name: gc9a01 +Info: Enables GalaxyCore's GC9A01 single chip driver based displays on + SPI0 as fb1, using GPIOs DC=25, RST=27 and BL=18 (physical + GPIO header pins 22, 13 and 12 respectively) in addition to the + SPI0 pins DIN=10, CLK=11 and CS=8 (physical GPIO header pins 19, + 23 and 24 respectively). +Load: dtoverlay=gc9a01,<param>=<val> +Params: speed Display SPI bus speed + + rotate Display rotation {0,90,180,270} + + width Width of the display + + height Height of the display + + fps Delay between frame updates + + debug Debug output level {0-7} + + +Name: ghost-amp +Info: An overlay for the Ghost amplifier. +Load: dtoverlay=ghost-amp,<param>=<val> +Params: fsm_debug Enable debug logging of the GPIO FSM (default + off) + + +Name: goodix +Info: Enables I2C connected Goodix gt9271 multiple touch controller using + GPIOs 4 and 17 (pins 7 and 11 on GPIO header) for interrupt and reset. +Load: dtoverlay=goodix,<param>=<val> +Params: interrupt GPIO used for interrupt (default 4) + reset GPIO used for reset (default 17) + + +Name: googlevoicehat-soundcard +Info: Configures the Google voiceHAT soundcard +Load: dtoverlay=googlevoicehat-soundcard +Params: <None> + + +Name: gpio-charger +Info: This is a generic overlay for detecting charger with GPIO. +Load: dtoverlay=gpio-charger,<param>=<val> +Params: gpio GPIO pin to trigger on (default 4) + active_low When this is 1 (active low), a falling + edge generates a charging event and a + rising edge generates a discharging event. + When this is 0 (active high), this is + reversed. The default is 0 (active high) + gpio_pull Desired pull-up/down state (off, down, up) + Default is "down". + type Set a charger type for the pin. (Default: mains) + + +Name: gpio-fan +Info: Configure a GPIO pin to control a cooling fan. +Load: dtoverlay=gpio-fan,<param>=<val> +Params: gpiopin GPIO used to control the fan (default 12) + temp Temperature at which the fan switches on, in + millicelcius (default 55000) + hyst Temperature delta (in millicelcius) below + temp at which the fan will drop to minrpm + (default 10000) + + +Name: gpio-hog +Info: Activate a "hog" for a GPIO - request that the kernel configures it as + an output, driven low or high as indicated by the presence or absence + of the active_low parameter. Note that a hogged GPIO is not available + to other drivers or for gpioset/gpioget. +Load: dtoverlay=gpio-hog,<param>=<val> +Params: gpio GPIO pin to hog (default 26) + active_low If set, the hog drives the GPIO low (defaults + to off - the GPIO is driven high) + + +Name: gpio-ir +Info: Use GPIO pin as rc-core style infrared receiver input. The rc-core- + based gpio_ir_recv driver maps received keys directly to a + /dev/input/event* device, all decoding is done by the kernel - LIRC is + not required! The key mapping and other decoding parameters can be + configured by "ir-keytable" tool. +Load: dtoverlay=gpio-ir,<param>=<val> +Params: gpio_pin Input pin number. Default is 18. + + gpio_pull Desired pull-up/down state (off, down, up) + Default is "up". + + invert "1" = invert the input (active-low signalling). + "0" = non-inverted input (active-high + signalling). Default is "1". + + rc-map-name Default rc keymap (can also be changed by + ir-keytable), defaults to "rc-rc6-mce" + + +Name: gpio-ir-tx +Info: Use GPIO pin as bit-banged infrared transmitter output. + This is an alternative to "pwm-ir-tx". gpio-ir-tx doesn't require + a PWM so it can be used together with onboard analog audio. +Load: dtoverlay=gpio-ir-tx,<param>=<val> +Params: gpio_pin Output GPIO (default 18) + + invert "1" = invert the output (make it active-low). + Default is "0" (active-high). + + +Name: gpio-key +Info: This is a generic overlay for activating GPIO keypresses using + the gpio-keys library and this dtoverlay. Multiple keys can be + set up using multiple calls to the overlay for configuring + additional buttons or joysticks. You can see available keycodes + at https://github.com/torvalds/linux/blob/v4.12/include/uapi/ + linux/input-event-codes.h#L64 +Load: dtoverlay=gpio-key,<param>=<val> +Params: gpio GPIO pin to trigger on (default 3) + active_low When this is 1 (active low), a falling + edge generates a key down event and a + rising edge generates a key up event. + When this is 0 (active high), this is + reversed. The default is 1 (active low) + gpio_pull Desired pull-up/down state (off, down, up) + Default is "up". Note that the default pin + (GPIO3) has an external pullup + label Set a label for the key + keycode Set the key code for the button + + + +Name: gpio-led +Info: This is a generic overlay for activating LEDs (or any other component) + by a GPIO pin. Multiple LEDs can be set up using multiple calls to the + overlay. While there are many existing methods to activate LEDs on the + RPi, this method offers some advantages: + 1) Does not require any userspace programs. + 2) LEDs can be connected to the kernel's led-trigger framework, + and drive the LED based on triggers such as cpu load, heartbeat, + kernel panic, key input, timers and others. + 3) LED can be tied to the input state of another GPIO pin. + 4) The LED is setup early during the kernel boot process (useful + for cpu/heartbeat/panic triggers). + + Typical electrical connection is: + RPI-GPIO.19 -> LED -> 300ohm resister -> RPI-GND + The GPIO pin number can be changed with the 'gpio=' parameter. + + To control an LED from userspace, write a 0 or 1 value: + echo 1 > /sys/class/leds/myled1/brightness + The 'myled1' name can be changed with the 'label=' parameter. + + To connect the LED to a kernel trigger from userspace: + echo cpu > /sys/class/leds/myled1/trigger + echo heartbeat > /sys/class/leds/myled1/trigger + echo none > /sys/class/leds/myled1/trigger + To connect the LED to GPIO.26 pin (physical pin 37): + echo gpio > /sys/class/leds/myled1/trigger + echo 26 > /sys/class/leds/myled1/gpio + Available triggers: + cat /sys/class/leds/myled1/trigger + + More information about the Linux kernel LED/Trigger system: + https://www.kernel.org/doc/Documentation/leds/leds-class.rst + https://www.kernel.org/doc/Documentation/leds/ledtrig-oneshot.rst +Load: dtoverlay=gpio-led,<param>=<val> +Params: gpio GPIO pin connected to the LED (default 19) + label The label for this LED. It will appear under + /sys/class/leds/<label> . Default 'myled1'. + trigger Set the led-trigger to connect to this LED. + default 'none' (LED is user-controlled). + Some possible triggers: + cpu - CPU load (all CPUs) + cpu0 - CPU load of first CPU. + mmc - disk activity (all disks) + panic - turn on on kernel panic + heartbeat - indicate system health + gpio - connect to a GPIO input pin (note: + currently the GPIO PIN can not be set + using overlay parameters, must be + done in userspace, see examples above. + active_low Set to 1 to turn invert the LED control + (writing 0 to /sys/class/leds/XXX/brightness + will turn on the GPIO/LED). Default '0'. + + +Name: gpio-no-bank0-irq +Info: Use this overlay to disable GPIO interrupts for GPIOs in bank 0 (0-27), + which can be useful for UIO drivers. + N.B. Using this overlay will trigger a kernel WARN during booting, but + this can safely be ignored - the system should work as expected. +Load: dtoverlay=gpio-no-bank0-irq +Params: <None> + + +Name: gpio-no-irq +Info: Use this overlay to disable all GPIO interrupts, which can be useful + for user-space GPIO edge detection systems. +Load: dtoverlay=gpio-no-irq +Params: <None> + + +Name: gpio-poweroff +Info: Drives a GPIO high or low on poweroff (including halt). Using this + overlay interferes with the normal power-down sequence, preventing the + kernel from resetting the SoC (a necessary step in a normal power-off + or reboot). This also disables the ability to trigger a boot by driving + GPIO3 low. + + The GPIO starts in an inactive state. At poweroff time it is driven + active for 100ms, then inactive for 100ms, then active again. It is + safe to remove the power at any point after the initial activation of + the GPIO. + + Users of this overlay are required to provide an external mechanism to + switch off the power supply when signalled - failure to do so results + in a kernel BUG, increased power consumption and undefined behaviour. +Load: dtoverlay=gpio-poweroff,<param>=<val> +Params: gpiopin GPIO for signalling (default 26) + + active_low Set if the power control device requires a + high->low transition to trigger a power-down. + Note that this will require the support of a + custom dt-blob.bin to prevent a power-down + during the boot process, and that a reboot + will also cause the pin to go low. + input Set if the gpio pin should be configured as + an input. + export Set to export the configured pin to sysfs + active_delay_ms Initial GPIO active period (default 100) + inactive_delay_ms Subsequent GPIO inactive period (default 100) + timeout_ms Specify (in ms) how long the kernel waits for + power-down before issuing a WARN (default 3000). + + +Name: gpio-shutdown +Info: Initiates a shutdown when GPIO pin changes. The given GPIO pin + is configured as an input key that generates KEY_POWER events. + + This event is handled by systemd-logind by initiating a + shutdown. Systemd versions older than 225 need an udev rule + enable listening to the input device: + + ACTION!="REMOVE", SUBSYSTEM=="input", KERNEL=="event*", \ + SUBSYSTEMS=="platform", DRIVERS=="gpio-keys", \ + ATTRS{keys}=="116", TAG+="power-switch" + + Alternatively this event can be handled also on systems without + systemd, just by traditional SysV init daemon. KEY_POWER event + (keycode 116) needs to be mapped to KeyboardSignal on console + and then kb::kbrequest inittab action which is triggered by + KeyboardSignal from console can be configured to issue system + shutdown. Steps for this configuration are: + + Add following lines to the /etc/console-setup/remap.inc file: + + # Key Power as special keypress + keycode 116 = KeyboardSignal + + Then add following lines to /etc/inittab file: + + # Action on special keypress (Key Power) + kb::kbrequest:/sbin/shutdown -t1 -a -h -P now + + And finally reload configuration by calling following commands: + + # dpkg-reconfigure console-setup + # service console-setup reload + # init q + + This overlay only handles shutdown. After shutdown, the system + can be powered up again by driving GPIO3 low. The default + configuration uses GPIO3 with a pullup, so if you connect a + button between GPIO3 and GND (pin 5 and 6 on the 40-pin header), + you get a shutdown and power-up button. Please note that + Raspberry Pi 1 Model B rev 1 uses GPIO1 instead of GPIO3. +Load: dtoverlay=gpio-shutdown,<param>=<val> +Params: gpio_pin GPIO pin to trigger on (default 3) + For Raspberry Pi 1 Model B rev 1 set this + explicitly to value 1, e.g.: + + dtoverlay=gpio-shutdown,gpio_pin=1 + + active_low When this is 1 (active low), a falling + edge generates a key down event and a + rising edge generates a key up event. + When this is 0 (active high), this is + reversed. The default is 1 (active low). + + gpio_pull Desired pull-up/down state (off, down, up) + Default is "up". + + Note that the default pin (GPIO3) has an + external pullup. Same applies for GPIO1 + on Raspberry Pi 1 Model B rev 1. + + debounce Specify the debounce interval in milliseconds + (default 100) + + +Name: hd44780-lcd +Info: Configures an HD44780 compatible LCD display. Uses 4 gpio pins for + data, 2 gpio pins for enable and register select and 1 optional pin + for enabling/disabling the backlight display. +Load: dtoverlay=hd44780-lcd,<param>=<val> +Params: pin_d4 GPIO pin for data pin D4 (default 6) + + pin_d5 GPIO pin for data pin D5 (default 13) + + pin_d6 GPIO pin for data pin D6 (default 19) + + pin_d7 GPIO pin for data pin D7 (default 26) + + pin_en GPIO pin for "Enable" (default 21) + + pin_rs GPIO pin for "Register Select" (default 20) + + pin_bl Optional pin for enabling/disabling the + display backlight. (default disabled) + + display_height Height of the display in characters + + display_width Width of the display in characters + + +Name: hdmi-backlight-hwhack-gpio +Info: Devicetree overlay for GPIO based backlight on/off capability. + Use this if you have one of those HDMI displays whose backlight cannot + be controlled via DPMS over HDMI and plan to do a little soldering to + use an RPi gpio pin for on/off switching. See: + https://www.waveshare.com/wiki/7inch_HDMI_LCD_(C)#Backlight_Control +Load: dtoverlay=hdmi-backlight-hwhack-gpio,<param>=<val> +Params: gpio_pin GPIO pin used (default 17) + active_low Set this to 1 if the display backlight is + switched on when the wire goes low. + Leave the default (value 0) if the backlight + expects a high to switch it on. + + +Name: hifiberry-amp +Info: Configures the HifiBerry Amp and Amp+ audio cards +Load: dtoverlay=hifiberry-amp +Params: <None> + + +Name: hifiberry-amp100 +Info: Configures the HifiBerry AMP100 audio card +Load: dtoverlay=hifiberry-amp100,<param>=<val> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + Digital volume control. Enable with + "dtoverlay=hifiberry-amp100,24db_digital_gain" + (The default behaviour is that the Digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24dB_digital_gain parameter, the Digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) + slave Force AMP100 into slave mode, using Pi as + master for bit clock and frame clock. + leds_off If set to 'true' the onboard indicator LEDs + are switched off at all times. + auto_mute If set to 'true' the amplifier is automatically + muted when the DAC is not playing. + mute_ext_ctl The amplifier's HW mute control is enabled + in ALSA mixer and set to <val>. + Will be overwritten by ALSA user settings. + + +Name: hifiberry-amp3 +Info: Configures the HifiBerry Amp3 audio card +Load: dtoverlay=hifiberry-amp3 +Params: <None> + + +Name: hifiberry-dac +Info: Configures the HifiBerry DAC audio cards +Load: dtoverlay=hifiberry-dac +Params: <None> + + +Name: hifiberry-dacplus +Info: Configures the HifiBerry DAC+ audio card +Load: dtoverlay=hifiberry-dacplus,<param>=<val> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + Digital volume control. Enable with + "dtoverlay=hifiberry-dacplus,24db_digital_gain" + (The default behaviour is that the Digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24dB_digital_gain parameter, the Digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) + slave Force DAC+ into slave mode, using Pi as + master for bit clock and frame clock. + leds_off If set to 'true' the onboard indicator LEDs + are switched off at all times. + + +Name: hifiberry-dacplusadc +Info: Configures the HifiBerry DAC+ADC audio card +Load: dtoverlay=hifiberry-dacplusadc,<param>=<val> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + Digital volume control. Enable with + "dtoverlay=hifiberry-dacplus,24db_digital_gain" + (The default behaviour is that the Digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24dB_digital_gain parameter, the Digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) + slave Force DAC+ADC into slave mode, using Pi as + master for bit clock and frame clock. + leds_off If set to 'true' the onboard indicator LEDs + are switched off at all times. + + +Name: hifiberry-dacplusadcpro +Info: Configures the HifiBerry DAC+ADC PRO audio card +Load: dtoverlay=hifiberry-dacplusadcpro,<param>=<val> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + Digital volume control. Enable with + "dtoverlay=hifiberry-dacplusadcpro,24db_digital_gain" + (The default behaviour is that the Digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24dB_digital_gain parameter, the Digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) + slave Force DAC+ADC Pro into slave mode, using Pi as + master for bit clock and frame clock. + leds_off If set to 'true' the onboard indicator LEDs + are switched off at all times. + + +Name: hifiberry-dacplusdsp +Info: Configures the HifiBerry DAC+DSP audio card +Load: dtoverlay=hifiberry-dacplusdsp +Params: <None> + + +Name: hifiberry-dacplushd +Info: Configures the HifiBerry DAC+ HD audio card +Load: dtoverlay=hifiberry-dacplushd +Params: <None> + + +Name: hifiberry-digi +Info: Configures the HifiBerry Digi and Digi+ audio card +Load: dtoverlay=hifiberry-digi +Params: <None> + + +Name: hifiberry-digi-pro +Info: Configures the HifiBerry Digi+ Pro and Digi2 Pro audio card +Load: dtoverlay=hifiberry-digi-pro +Params: <None> + + +Name: highperi +Info: Enables "High Peripheral" mode +Load: dtoverlay=highperi +Params: <None> + + +Name: hy28a +Info: HY28A - 2.8" TFT LCD Display Module by HAOYU Electronics + Default values match Texy's display shield +Load: dtoverlay=hy28a,<param>=<val> +Params: speed Display SPI bus speed + + rotate Display rotation {0,90,180,270} + + fps Delay between frame updates + + debug Debug output level {0-7} + + xohms Touchpanel sensitivity (X-plate resistance) + + resetgpio GPIO used to reset controller + + ledgpio GPIO used to control backlight + + +Name: hy28b +Info: HY28B - 2.8" TFT LCD Display Module by HAOYU Electronics + Default values match Texy's display shield +Load: dtoverlay=hy28b,<param>=<val> +Params: speed Display SPI bus speed + + rotate Display rotation {0,90,180,270} + + fps Delay between frame updates + + debug Debug output level {0-7} + + xohms Touchpanel sensitivity (X-plate resistance) + + resetgpio GPIO used to reset controller + + ledgpio GPIO used to control backlight + + +Name: hy28b-2017 +Info: HY28B 2017 version - 2.8" TFT LCD Display Module by HAOYU Electronics + Default values match Texy's display shield +Load: dtoverlay=hy28b-2017,<param>=<val> +Params: speed Display SPI bus speed + + rotate Display rotation {0,90,180,270} + + fps Delay between frame updates + + debug Debug output level {0-7} + + xohms Touchpanel sensitivity (X-plate resistance) + + resetgpio GPIO used to reset controller + + ledgpio GPIO used to control backlight + + +Name: i-sabre-q2m +Info: Configures the Audiophonics I-SABRE Q2M DAC +Load: dtoverlay=i-sabre-q2m +Params: <None> + + +Name: i2c-bcm2708 +Info: Fall back to the i2c_bcm2708 driver for the i2c_arm bus. +Load: dtoverlay=i2c-bcm2708 +Params: <None> + + +Name: i2c-fan +Info: Adds support for a number of I2C fan controllers +Load: dtoverlay=i2c-fan,<param>=<val> +Params: addr Sets the address for the fan controller. Note + that the device must be configured to use the + specified address. + + i2c0 Choose the I2C0 bus on GPIOs 0&1 + + i2c_csi_dsi Choose the I2C0 bus on GPIOs 44&45 + + i2c3 Choose the I2C3 bus (configure with the i2c3 + overlay - BCM2711 only) + + i2c4 Choose the I2C4 bus (configure with the i2c4 + overlay - BCM2711 only) + + i2c5 Choose the I2C5 bus (configure with the i2c5 + overlay - BCM2711 only) + + i2c6 Choose the I2C6 bus (configure with the i2c6 + overlay - BCM2711 only) + + minpwm PWM setting for the fan when the SoC is below + mintemp (range 0-255. default 0) + maxpwm PWM setting for the fan when the SoC is above + maxtemp (range 0-255. default 255) + midtemp Temperature (in millicelcius) at which the fan + begins to speed up (default 50000) + + midtemp_hyst Temperature delta (in millicelcius) below + mintemp at which the fan will drop to minrpm + (default 2000) + + maxtemp Temperature (in millicelcius) at which the fan + will be held at maxrpm (default 70000) + + maxtemp_hyst Temperature delta (in millicelcius) below + maxtemp at which the fan begins to slow down + (default 2000) + + emc2301 Select the Microchip EMC230x controller family + - EMC2301, EMC2302, EMC2303, EMC2305. + + +Name: i2c-gpio +Info: Adds support for software i2c controller on gpio pins +Load: dtoverlay=i2c-gpio,<param>=<val> +Params: i2c_gpio_sda GPIO used for I2C data (default "23") + + i2c_gpio_scl GPIO used for I2C clock (default "24") + + i2c_gpio_delay_us Clock delay in microseconds + (default "2" = ~100kHz) + + bus Set to a unique, non-zero value if wanting + multiple i2c-gpio busses. If set, will be used + as the preferred bus number (/dev/i2c-<n>). If + not set, the default value is 0, but the bus + number will be dynamically assigned - probably + 3. + + +Name: i2c-mux +Info: Adds support for a number of I2C bus multiplexers on i2c_arm +Load: dtoverlay=i2c-mux,<param>=<val> +Params: pca9542 Select the NXP PCA9542 device + + pca9545 Select the NXP PCA9545 device + + pca9548 Select the NXP PCA9548 device + + addr Change I2C address of the device (default 0x70) + + i2c0 Choose the I2C0 bus on GPIOs 0&1 + + i2c_csi_dsi Choose the I2C0 bus on GPIOs 44&45 + + i2c3 Choose the I2C3 bus (configure with the i2c3 + overlay - BCM2711 only) + + i2c4 Choose the I2C3 bus (configure with the i2c3 + overlay - BCM2711 only) + + i2c5 Choose the I2C5 bus (configure with the i2c4 + overlay - BCM2711 only) + + i2c6 Choose the I2C6 bus (configure with the i2c6 + overlay - BCM2711 only) + + +[ The i2c-mux-pca9548a overlay has been deleted. See i2c-mux. ] + + +Name: i2c-pwm-pca9685a +Info: Adds support for an NXP PCA9685A I2C PWM controller on i2c_arm +Load: dtoverlay=i2c-pwm-pca9685a,<param>=<val> +Params: addr I2C address of PCA9685A (default 0x40) + i2c0 Choose the I2C0 bus on GPIOs 0&1 + i2c_csi_dsi Choose the I2C0 bus on GPIOs 44&45 + i2c3 Choose the I2C3 bus (configure with the i2c3 + overlay - BCM2711 only) + i2c4 Choose the I2C3 bus (configure with the i2c3 + overlay - BCM2711 only) + i2c5 Choose the I2C5 bus (configure with the i2c4 + overlay - BCM2711 only) + i2c6 Choose the I2C6 bus (configure with the i2c6 + overlay - BCM2711 only) + + +Name: i2c-rtc +Info: Adds support for a number of I2C Real Time Clock devices +Load: dtoverlay=i2c-rtc,<param>=<val> +Params: abx80x Select one of the ABx80x family: + AB0801, AB0803, AB0804, AB0805, + AB1801, AB1803, AB1804, AB1805 + + bq32000 Select the TI BQ32000 device + + ds1307 Select the DS1307 device + + ds1339 Select the DS1339 device + + ds1340 Select the DS1340 device + + ds3231 Select the DS3231 device + + m41t62 Select the M41T62 device + + mcp7940x Select the MCP7940x device + + mcp7941x Select the MCP7941x device + + pcf2127 Select the PCF2127 device + + pcf2129 Select the PCF2129 device + + pcf85063 Select the PCF85063 device + + pcf85063a Select the PCF85063A device + + pcf8523 Select the PCF8523 device + + pcf85363 Select the PCF85363 device + + pcf8563 Select the PCF8563 device + + rv1805 Select the Micro Crystal RV1805 device + + rv3028 Select the Micro Crystal RV3028 device + + rv3032 Select the Micro Crystal RV3032 device + + rv8803 Select the Micro Crystal RV8803 device + + sd3078 Select the ZXW Shenzhen whwave SD3078 device + + s35390a Select the ABLIC S35390A device + + i2c0 Choose the I2C0 bus on GPIOs 0&1 + + i2c_csi_dsi Choose the I2C0 bus on GPIOs 44&45 + + i2c3 Choose the I2C3 bus (configure with the i2c3 + overlay - BCM2711 only) + + i2c4 Choose the I2C3 bus (configure with the i2c3 + overlay - BCM2711 only) + + i2c5 Choose the I2C5 bus (configure with the i2c4 + overlay - BCM2711 only) + + i2c6 Choose the I2C6 bus (configure with the i2c6 + overlay - BCM2711 only) + + addr Sets the address for the RTC. Note that the + device must be configured to use the specified + address. + + trickle-diode-disable Do not use the internal trickle charger diode + (BQ32000 only) + + trickle-diode-type Diode type for trickle charge - "standard" or + "schottky" (ABx80x and RV1805 only) + + trickle-resistor-ohms Resistor value for trickle charge (DS1339, + ABx80x, BQ32000, RV1805, RV3028, RV3032) + + trickle-voltage-mv Charge pump voltage for trickle charge (RV3032) + + wakeup-source Specify that the RTC can be used as a wakeup + source + + backup-switchover-mode Backup power supply switch mode. Must be 0 for + off or 1 for Vdd < VBackup (RV3028, RV3032) + + +Name: i2c-rtc-gpio +Info: Adds support for a number of I2C Real Time Clock devices + using the software i2c controller +Load: dtoverlay=i2c-rtc-gpio,<param>=<val> +Params: abx80x Select one of the ABx80x family: + AB0801, AB0803, AB0804, AB0805, + AB1801, AB1803, AB1804, AB1805 + + bq32000 Select the TI BQ32000 device + + ds1307 Select the DS1307 device + + ds1339 Select the DS1339 device + + ds1340 Select the DS1340 device + + ds3231 Select the DS3231 device + + m41t62 Select the M41T62 device + + mcp7940x Select the MCP7940x device + + mcp7941x Select the MCP7941x device + + pcf2127 Select the PCF2127 device + + pcf2129 Select the PCF2129 device + + pcf85063 Select the PCF85063 device + + pcf85063a Select the PCF85063A device + + pcf8523 Select the PCF8523 device + + pcf85363 Select the PCF85363 device + + pcf8563 Select the PCF8563 device + + rv1805 Select the Micro Crystal RV1805 device + + rv3028 Select the Micro Crystal RV3028 device + + rv3032 Select the Micro Crystal RV3032 device + + rv8803 Select the Micro Crystal RV8803 device + + sd3078 Select the ZXW Shenzhen whwave SD3078 device + + s35390a Select the ABLIC S35390A device + + addr Sets the address for the RTC. Note that the + device must be configured to use the specified + address. + + trickle-diode-disable Do not use the internal trickle charger diode + (BQ32000 only) + + trickle-diode-type Diode type for trickle charge - "standard" or + "schottky" (ABx80x and RV1805 only) + + trickle-resistor-ohms Resistor value for trickle charge (DS1339, + ABx80x, BQ32000, RV1805, RV3028, RV3032) + + trickle-voltage-mv Charge pump voltage for trickle charge (RV3032) + + wakeup-source Specify that the RTC can be used as a wakeup + source + + backup-switchover-mode Backup power supply switch mode. Must be 0 for + off or 1 for Vdd < VBackup (RV3028, RV3032) + + i2c_gpio_sda GPIO used for I2C data (default "23") + + i2c_gpio_scl GPIO used for I2C clock (default "24") + + i2c_gpio_delay_us Clock delay in microseconds + (default "2" = ~100kHz) + + +Name: i2c-sensor +Info: Adds support for a number of I2C barometric pressure, temperature, + light level and chemical sensors on i2c_arm +Load: dtoverlay=i2c-sensor,<param>=<val> +Params: addr Set the address for the ADT7410, BH1750, BME280, + BME680, BMP280, BMP380, CCS811, DS1621, HDC100X, + JC42, LM75, MCP980x, MPU6050, MPU9250, MS5637, + MS5803, MS5805, MS5837, MS8607, SHT3x or TMP102 + + adt7410 Select the Analog Devices ADT7410 and ADT7420 + temperature sensors + Valid address 0x48-0x4b, default 0x48 + + aht10 Select the Aosong AHT10 temperature and humidity + sensor + + bh1750 Select the Rohm BH1750 ambient light sensor + Valid addresses 0x23 or 0x5c, default 0x23 + + bme280 Select the Bosch Sensortronic BME280 + Valid addresses 0x76-0x77, default 0x76 + + bme680 Select the Bosch Sensortronic BME680 + Valid addresses 0x76-0x77, default 0x76 + + bmp085 Select the Bosch Sensortronic BMP085 + + bmp180 Select the Bosch Sensortronic BMP180 + + bmp280 Select the Bosch Sensortronic BMP280 + Valid addresses 0x76-0x77, default 0x76 + + bmp380 Select the Bosch Sensortronic BMP380 + Valid addresses 0x76-0x77, default 0x76 + + bno055 Select the Bosch Sensortronic BNO055 IMU + Valid address 0x28-0x29, default 0x29 + + ccs811 Select the AMS CCS811 digital gas sensor + Valid addresses 0x5a-0x5b, default 0x5b + + ds1621 Select the Dallas Semiconductors DS1621 temp + sensor. Valid addresses 0x48-0x4f, default 0x48 + + hdc100x Select the Texas Instruments HDC100x temp sensor + Valid addresses 0x40-0x43, default 0x40 + + htu21 Select the HTU21 temperature and humidity sensor + + int_pin Set the GPIO to use for interrupts (max30102, + mpu6050 and mpu9250 only) + + jc42 Select any of the many JEDEC JC42.4-compliant + temperature sensors, including: + ADT7408, AT30TS00, CAT34TS02, CAT6095, + MAX6604, MCP9804, MCP9805, MCP9808, + MCP98242, MCP98243, MCP98244, MCP9843, + SE97, SE98, STTS424(E), STTS2002, STTS3000, + TSE2002, TSE2004, TS3000, and TS3001. + The default address is 0x18. + + lm75 Select the Maxim LM75 temperature sensor + Valid addresses 0x48-0x4f, default 0x4f + + lm75addr Deprecated - use addr parameter instead + + max17040 Select the Maxim Integrated MAX17040 battery + monitor + + max30102 Select the Maxim Integrated MAX30102 heart-rate + and blood-oxygen sensor + + mcp980x Select the Maxim MCP980x range of temperature + sensors (i.e. MCP9800, MCP9801, MCP9802 and + MCP9803). N.B. For MCP9804, MCP9805 and MCP9808, + use the "jc42" option. + Valid addresses are 0x18-0x1f (default 0x18) + + mpu6050 Select the InvenSense MPU6050 IMU. Valid + valid addresses are 0x68 and 0x69 (default 0x68) + + mpu9250 Select the InvenSense MPU9250 IMU. Valid + valid addresses are 0x68 and 0x69 (default 0x68) + + ms5637 Select the Measurement Specialities MS5637 + pressure and temperature sensor. + + ms5803 Select the Measurement Specialities MS5803 + pressure and temperature sensor. + + ms5805 Select the Measurement Specialities MS5805 + pressure and temperature sensor. + + ms5837 Select the Measurement Specialities MS5837 + pressure and temperature sensor. + + ms8607 Select the Measurement Specialities MS8607 + pressure and temperature sensor. + + no_timeout Disable the SMBUS timeout. N.B. Only supported + by some jc42 devices - using with an + incompatible device can stop it from being + activated. + + reset_pin GPIO to be used to reset the device (bno055 + only, disabled by default) + + sht3x Select the Sensirion SHT3x temperature and + humidity sensors. Valid addresses 0x44-0x45, + default 0x44 + + sht4x Select the Sensirion SHT4x temperature and + humidity sensors. Valid addresses 0x44-0x45, + default 0x44 + + si7020 Select the Silicon Labs Si7013/20/21 humidity/ + temperature sensor + + sps30 Select the Sensirion SPS30 particulate matter + sensor. Fixed address 0x69. + + sgp30 Select the Sensirion SGP30 VOC sensor. + Fixed address 0x58. + + tmp102 Select the Texas Instruments TMP102 temp sensor + Valid addresses 0x48-0x4b, default 0x48 + + tsl4531 Select the AMS TSL4531 digital ambient light + sensor + + veml6070 Select the Vishay VEML6070 ultraviolet light + sensor + + i2c0 Choose the I2C0 bus on GPIOs 0&1 + + i2c_csi_dsi Choose the I2C0 bus on GPIOs 44&45 + + i2c3 Choose the I2C3 bus (configure with the i2c3 + overlay - BCM2711 only) + + i2c4 Choose the I2C3 bus (configure with the i2c3 + overlay - BCM2711 only) + + i2c5 Choose the I2C5 bus (configure with the i2c4 + overlay - BCM2711 only) + + i2c6 Choose the I2C6 bus (configure with the i2c6 + overlay - BCM2711 only) + + +Name: i2c0 +Info: Change i2c0 pin usage. Not all pin combinations are usable on all + platforms - platforms other then Compute Modules can only use this + to disable transaction combining. + Do NOT use in conjunction with dtparam=i2c_vc=on. From the 5.4 kernel + onwards the base DT includes the use of i2c_mux_pinctrl to expose two + muxings of BSC0 - GPIOs 0&1, and whichever combination is used for the + camera and display connectors. This overlay disables that mux and + configures /dev/i2c0 to point at whichever set of pins is requested. + dtparam=i2c_vc=on will try and enable the mux, so combining the two + will cause conflicts. +Load: dtoverlay=i2c0,<param>=<val> +Params: pins_0_1 Use pins 0 and 1 (default) + pins_28_29 Use pins 28 and 29 + pins_44_45 Use pins 44 and 45 + pins_46_47 Use pins 46 and 47 + combine Allow transactions to be combined (default + "yes") + + +Name: i2c0-bcm2708 +Info: Deprecated, legacy version of i2c0. +Load: <Deprecated> + + +Name: i2c0-pi5 +Info: Enable i2c0 (Pi 5 only) +Load: dtoverlay=i2c0-pi5,<param>=<val> +Params: pins_0_1 Use GPIOs 0 and 1 (default) + pins_8_9 Use GPIOs 8 and 9 + baudrate Set the baudrate for the interface (default + "100000") + + +Name: i2c1 +Info: Change i2c1 pin usage. Not all pin combinations are usable on all + platforms - platforms other then Compute Modules can only use this + to disable transaction combining. +Load: dtoverlay=i2c1,<param>=<val> +Params: pins_2_3 Use pins 2 and 3 (default) + pins_44_45 Use pins 44 and 45 + combine Allow transactions to be combined (default + "yes") + + +Name: i2c1-bcm2708 +Info: Deprecated, legacy version of i2c1. +Load: <Deprecated> + + +Name: i2c1-pi5 +Info: Enable i2c1 (Pi 5 only) +Load: dtoverlay=i2c1-pi5,<param>=<val> +Params: pins_2_3 Use GPIOs 2 and 3 (default) + pins_10_11 Use GPIOs 10 and 11 + baudrate Set the baudrate for the interface (default + "100000") + + +Name: i2c2-pi5 +Info: Enable i2c2 (Pi 5 only) +Load: dtoverlay=i2c2-pi5,<param>=<val> +Params: pins_4_5 Use GPIOs 4 and 5 (default) + pins_12_13 Use GPIOs 12 and 13 + baudrate Set the baudrate for the interface (default + "100000") + + +Name: i2c3 +Info: Enable the i2c3 bus. BCM2711 only. +Load: dtoverlay=i2c3,<param> +Params: pins_2_3 Use GPIOs 2 and 3 + pins_4_5 Use GPIOs 4 and 5 (default) + baudrate Set the baudrate for the interface (default + "100000") + + +Name: i2c3-pi5 +Info: Enable i2c3 (Pi 5 only) +Load: dtoverlay=i2c3-pi5,<param>=<val> +Params: pins_6_7 Use GPIOs 6 and 7 (default) + pins_14_15 Use GPIOs 14 and 15 + pins_22_23 Use GPIOs 22 and 23 + baudrate Set the baudrate for the interface (default + "100000") + + +Name: i2c4 +Info: Enable the i2c4 bus. BCM2711 only. +Load: dtoverlay=i2c4,<param> +Params: pins_6_7 Use GPIOs 6 and 7 + pins_8_9 Use GPIOs 8 and 9 (default) + baudrate Set the baudrate for the interface (default + "100000") + + +Name: i2c5 +Info: Enable the i2c5 bus. BCM2711 only. +Load: dtoverlay=i2c5,<param> +Params: pins_10_11 Use GPIOs 10 and 11 + pins_12_13 Use GPIOs 12 and 13 (default) + baudrate Set the baudrate for the interface (default + "100000") + + +Name: i2c6 +Info: Enable the i2c6 bus. BCM2711 only. +Load: dtoverlay=i2c6,<param> +Params: pins_0_1 Use GPIOs 0 and 1 + pins_22_23 Use GPIOs 22 and 23 (default) + baudrate Set the baudrate for the interface (default + "100000") + + +Name: i2s-dac +Info: Configures any passive I2S DAC soundcard. +Load: dtoverlay=i2s-dac +Params: <None> + + +Name: i2s-gpio28-31 +Info: move I2S function block to GPIO 28 to 31 +Load: dtoverlay=i2s-gpio28-31 +Params: <None> + + +Name: ilitek251x +Info: Enables I2C connected Ilitek 251x multiple touch controller using + GPIO 4 (pin 7 on GPIO header) for interrupt. +Load: dtoverlay=ilitek251x,<param>=<val> +Params: interrupt GPIO used for interrupt (default 4) + sizex Touchscreen size x, horizontal resolution of + touchscreen (in pixels) + sizey Touchscreen size y, vertical resolution of + touchscreen (in pixels) + + +Name: imx219 +Info: Sony IMX219 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=imx219,<param>=<val> +Params: rotation Mounting rotation of the camera sensor (0 or + 180, default 180) + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + vcm Configure a VCM focus drive on the sensor. + + +Name: imx258 +Info: Sony IMX258 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=imx258,<param>=<val> +Params: rotation Mounting rotation of the camera sensor (0 or + 180, default 180) + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + vcm Configure a VCM focus drive on the sensor. + 4lane Enable 4 CSI2 lanes. This requires a Compute + Module (1, 3, or 4). + + +Name: imx290 +Info: Sony IMX290 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=imx290,<param> +Params: 4lane Enable 4 CSI2 lanes. This requires a Compute + Module (1, 3, or 4). + clock-frequency Sets the clock frequency to match that used on + the board. + Modules from Vision Components use 37.125MHz + (the default), whilst those from Innomaker use + 74.25MHz. + mono Denote that the module is a mono sensor. + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + rotation Mounting rotation of the camera sensor (0 or + 180, default 0) + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + + +Name: imx296 +Info: Sony IMX296 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=imx296,<param>=<val> +Params: rotation Mounting rotation of the camera sensor (0 or + 180, default 180) + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + clock-frequency Sets the clock frequency to match that used on + the board, which should be one of 54000000 + (the default), 37125000 or 74250000. + + +Name: imx327 +Info: Sony IMX327 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=imx327,<param> +Params: 4lane Enable 4 CSI2 lanes. This requires a Compute + Module (1, 3, or 4). + clock-frequency Sets the clock frequency to match that used on + the board. + Modules from Vision Components use 37.125MHz + (the default), whilst those from Innomaker use + 74.25MHz. + mono Denote that the module is a mono sensor. + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + rotation Mounting rotation of the camera sensor (0 or + 180, default 0) + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + + +Name: imx378 +Info: Sony IMX378 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=imx378,<param>=<val> +Params: rotation Mounting rotation of the camera sensor (0 or + 180, default 180) + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + + +Name: imx462 +Info: Sony IMX462 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=imx462,<param> +Params: 4lane Enable 4 CSI2 lanes. This requires a Compute + Module (1, 3, or 4). + clock-frequency Sets the clock frequency to match that used on + the board. + Modules from Vision Components use 37.125MHz + (the default), whilst those from Innomaker use + 74.25MHz. + mono Denote that the module is a mono sensor. + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + rotation Mounting rotation of the camera sensor (0 or + 180, default 0) + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + + +Name: imx477 +Info: Sony IMX477 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=imx477,<param>=<val> +Params: rotation Mounting rotation of the camera sensor (0 or + 180, default 180) + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + + +Name: imx519 +Info: Sony IMX519 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=imx519,<param>=<val> +Params: rotation Mounting rotation of the camera sensor (0 or + 180, default 0) + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + vcm Select lens driver state. Default is enabled, + but vcm=off will disable. + + +Name: imx708 +Info: Sony IMX708 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=imx708,<param>=<val> +Params: rotation Mounting rotation of the camera sensor (0 or + 180, default 180) + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + vcm Select lens driver state. Default is enabled, + but vcm=off will disable. + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + link-frequency Allowable link frequency values to use in Hz: + 450000000 (default), 447000000, 453000000. + + +Name: iqaudio-codec +Info: Configures the IQaudio Codec audio card +Load: dtoverlay=iqaudio-codec +Params: <None> + + +Name: iqaudio-dac +Info: Configures the IQaudio DAC audio card +Load: dtoverlay=iqaudio-dac,<param> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + Digital volume control. Enable with + "dtoverlay=iqaudio-dac,24db_digital_gain" + (The default behaviour is that the Digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24db_digital_gain parameter, the Digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) + + +Name: iqaudio-dacplus +Info: Configures the IQaudio DAC+ audio card +Load: dtoverlay=iqaudio-dacplus,<param>=<val> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + Digital volume control. Enable with + "dtoverlay=iqaudio-dacplus,24db_digital_gain" + (The default behaviour is that the Digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24db_digital_gain parameter, the Digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) + auto_mute_amp If specified, unmute/mute the IQaudIO amp when + starting/stopping audio playback. + unmute_amp If specified, unmute the IQaudIO amp once when + the DAC driver module loads. + + +Name: iqaudio-digi-wm8804-audio +Info: Configures the IQAudIO Digi WM8804 audio card +Load: dtoverlay=iqaudio-digi-wm8804-audio,<param>=<val> +Params: card_name Override the default, "IQAudIODigi", card name. + dai_name Override the default, "IQAudIO Digi", dai name. + dai_stream_name Override the default, "IQAudIO Digi HiFi", + dai stream name. + + +Name: iqs550 +Info: Enables I2C connected Azoteq IQS550 trackpad/touchscreen controller + using GPIO 4 (pin 7 on GPIO header) for interrupt. +Load: dtoverlay=iqs550,<param>=<val> +Params: interrupt GPIO used for interrupt (default 4) + reset GPIO used for reset (optional) + sizex Touchscreen size x (default 800) + sizey Touchscreen size y (default 480) + invx Touchscreen inverted x axis + invy Touchscreen inverted y axis + swapxy Touchscreen swapped x y axis + + +Name: irs1125 +Info: Infineon irs1125 TOF camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=irs1125,<param>=<val> +Params: media-controller Configure use of Media Controller API for + configuring the sensor (default off) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + + +Name: jedec-spi-nor +Info: Adds support for JEDEC-compliant SPI NOR flash devices. (Note: The + "jedec,spi-nor" kernel driver was formerly known as "m25p80".) +Load: dtoverlay=jedec-spi-nor,<param>=<val> +Params: spi<n>-<m> Enable flash device on SPI<n>, CS#<m> + fastr Add fast read capability to the flash device + speed Maximum SPI frequency (Hz) + flash-spi<n>-<m> Same as spi<n>-<m> (deprecated) + flash-fastr-spi<n>-<m> Same as spi<n>->m>,fastr (deprecated) + + +Name: justboom-both +Info: Simultaneous usage of an justboom-dac and justboom-digi based + card +Load: dtoverlay=justboom-both,<param>=<val> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + Digital volume control. Enable with + "dtoverlay=justboom-dac,24db_digital_gain" + (The default behaviour is that the Digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24dB_digital_gain parameter, the Digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) + + +Name: justboom-dac +Info: Configures the JustBoom DAC HAT, Amp HAT, DAC Zero and Amp Zero audio + cards +Load: dtoverlay=justboom-dac,<param>=<val> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + Digital volume control. Enable with + "dtoverlay=justboom-dac,24db_digital_gain" + (The default behaviour is that the Digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24dB_digital_gain parameter, the Digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) + + +Name: justboom-digi +Info: Configures the JustBoom Digi HAT and Digi Zero audio cards +Load: dtoverlay=justboom-digi +Params: <None> + + +Name: lirc-rpi +Info: This overlay has been deprecated and removed - see gpio-ir +Load: <Deprecated> + + +Name: ltc294x +Info: Adds support for the ltc294x family of battery gauges +Load: dtoverlay=ltc294x,<param>=<val> +Params: ltc2941 Select the ltc2941 device + + ltc2942 Select the ltc2942 device + + ltc2943 Select the ltc2943 device + + ltc2944 Select the ltc2944 device + + resistor-sense The sense resistor value in milli-ohms. + Can be a 32-bit negative value when the battery + has been connected to the wrong end of the + resistor. + + prescaler-exponent Range and accuracy of the gauge. The value is + programmed into the chip only if it differs + from the current setting. + For LTC2941 only: + - Default value is 128 + - the exponent is in the range 0-7 (default 7) + See the datasheet for more information. + + +Name: max98357a +Info: Configures the Maxim MAX98357A I2S DAC +Load: dtoverlay=max98357a,<param>=<val> +Params: no-sdmode Driver does not manage the state of the DAC's + SD_MODE pin (i.e. chip is always on). + sdmode-pin integer, GPIO pin connected to the SD_MODE input + of the DAC (default GPIO4 if parameter omitted). + + +Name: maxtherm +Info: Configure a MAX6675, MAX31855 or MAX31856 thermocouple as an IIO device. + + For devices on spi1 or spi2, the interfaces should be enabled + with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays. + The overlay expects to disable the relevant spidev node, so also using + e.g. cs0_spidev=off is unnecessary. + + Example: + MAX31855 on /dev/spidev0.0 + dtoverlay=maxtherm,spi0-0,max31855 + MAX31856 using a type J thermocouple on /dev/spidev2.1 + dtoverlay=spi2-2cs + dtoverlay=maxtherm,spi2-1,max31856,type_j + +Load: dtoverlay=maxtherm,<param>=<val> +Params: spi<n>-<m> Configure device at spi<n>, cs<m> + (boolean, required) + max6675 Enable support for the MAX6675 (default) + max31855 Enable support for the MAX31855 + max31855e Enable support for the MAX31855E + max31855j Enable support for the MAX31855J + max31855k Enable support for the MAX31855K + max31855n Enable support for the MAX31855N + max31855r Enable support for the MAX31855R + max31855s Enable support for the MAX31855S + max31855t Enable support for the MAX31855T + max31856 Enable support for the MAX31856 (with type K) + type_b Select a type B sensor for max31856 + type_e Select a type E sensor for max31856 + type_j Select a type J sensor for max31856 + type_k Select a type K sensor for max31856 + type_n Select a type N sensor for max31856 + type_r Select a type R sensor for max31856 + type_s Select a type S sensor for max31856 + type_t Select a type T sensor for max31856 + + +Name: mbed-dac +Info: Configures the mbed AudioCODEC (TLV320AIC23B) +Load: dtoverlay=mbed-dac +Params: <None> + + +Name: mcp23017 +Info: Configures the MCP23017 I2C GPIO expander +Load: dtoverlay=mcp23017,<param>=<val> +Params: gpiopin Gpio pin connected to the INTA output of the + MCP23017 (default: 4) + + addr I2C address of the MCP23017 (default: 0x20) + + mcp23008 Configure an MCP23008 instead. + noints Disable the interrupt GPIO line. + i2c0 Choose the I2C0 bus on GPIOs 0&1 + i2c_csi_dsi Choose the I2C0 bus on GPIOs 44&45 + i2c3 Choose the I2C3 bus (configure with the i2c3 + overlay - BCM2711 only) + i2c4 Choose the I2C4 bus (configure with the i2c4 + overlay - BCM2711 only) + i2c5 Choose the I2C5 bus (configure with the i2c5 + overlay - BCM2711 only) + i2c6 Choose the I2C6 bus (configure with the i2c6 + overlay - BCM2711 only) + + +Name: mcp23s17 +Info: Configures the MCP23S08/17 SPI GPIO expanders. + If devices are present on SPI1 or SPI2, those interfaces must be enabled + with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays. + If interrupts are enabled for a device on a given CS# on a SPI bus, that + device must be the only one present on that SPI bus/CS#. +Load: dtoverlay=mcp23s17,<param>=<val> +Params: s08-spi<n>-<m>-present 4-bit integer, bitmap indicating MCP23S08 + devices present on SPI<n>, CS#<m> + + s17-spi<n>-<m>-present 8-bit integer, bitmap indicating MCP23S17 + devices present on SPI<n>, CS#<m> + + s08-spi<n>-<m>-int-gpio integer, enables interrupts on a single + MCP23S08 device on SPI<n>, CS#<m>, specifies + the GPIO pin to which INT output of MCP23S08 + is connected. + + s17-spi<n>-<m>-int-gpio integer, enables mirrored interrupts on a + single MCP23S17 device on SPI<n>, CS#<m>, + specifies the GPIO pin to which either INTA + or INTB output of MCP23S17 is connected. + + +Name: mcp2515 +Info: Configures the MCP2515 CAN controller on spi0/1/2 + For devices on spi1 or spi2, the interfaces should be enabled + with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays. +Load: dtoverlay=mcp2515,<param>=<val> +Params: spi<n>-<m> Configure device at spi<n>, cs<m> + (boolean, required) + + oscillator Clock frequency for the CAN controller (Hz) + + speed Maximum SPI frequence (Hz) + + interrupt GPIO for interrupt signal + + +Name: mcp2515-can0 +Info: Configures the MCP2515 CAN controller on spi0.0 +Load: dtoverlay=mcp2515-can0,<param>=<val> +Params: oscillator Clock frequency for the CAN controller (Hz) + + spimaxfrequency Maximum SPI frequence (Hz) + + interrupt GPIO for interrupt signal + + +Name: mcp2515-can1 +Info: Configures the MCP2515 CAN controller on spi0.1 +Load: dtoverlay=mcp2515-can1,<param>=<val> +Params: oscillator Clock frequency for the CAN controller (Hz) + + spimaxfrequency Maximum SPI frequence (Hz) + + interrupt GPIO for interrupt signal + + +Name: mcp251xfd +Info: Configures the MCP251XFD CAN controller family + For devices on spi1 or spi2, the interfaces should be enabled + with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays. +Load: dtoverlay=mcp251xfd,<param>=<val> +Params: spi<n>-<m> Configure device at spi<n>, cs<m> + (boolean, required) + + oscillator Clock frequency for the CAN controller (Hz) + + speed Maximum SPI frequence (Hz) + + interrupt GPIO for interrupt signal + + rx_interrupt GPIO for RX interrupt signal (nINT1) (optional) + + xceiver_enable GPIO for CAN transceiver enable (optional) + + xceiver_active_high specifiy if CAN transceiver enable pin is + active high (optional, default: active low) + + +Name: mcp3008 +Info: Configures MCP3008 A/D converters + For devices on spi1 or spi2, the interfaces should be enabled + with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays. +Load: dtoverlay=mcp3008,<param>[=<val>] +Params: spi<n>-<m>-present boolean, configure device at spi<n>, cs<m> + spi<n>-<m>-speed integer, set the spi bus speed for this device + + +Name: mcp3202 +Info: Configures MCP3202 A/D converters + For devices on spi1 or spi2, the interfaces should be enabled + with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays. +Load: dtoverlay=mcp3202,<param>[=<val>] +Params: spi<n>-<m>-present boolean, configure device at spi<n>, cs<m> + spi<n>-<m>-speed integer, set the spi bus speed for this device + + +Name: mcp342x +Info: Overlay for activation of Microchip MCP3421-3428 ADCs over I2C +Load: dtoverlay=mcp342x,<param>=<val> +Params: addr I2C bus address of device, for devices with + addresses that are configurable, e.g. by + hardware links (default=0x68) + mcp3421 The device is an MCP3421 + mcp3422 The device is an MCP3422 + mcp3423 The device is an MCP3423 + mcp3424 The device is an MCP3424 + mcp3425 The device is an MCP3425 + mcp3426 The device is an MCP3426 + mcp3427 The device is an MCP3427 + mcp3428 The device is an MCP3428 + + +Name: media-center +Info: Media Center HAT - 2.83" Touch Display + extras by Pi Supply +Load: dtoverlay=media-center,<param>=<val> +Params: speed Display SPI bus speed + rotate Display rotation {0,90,180,270} + fps Delay between frame updates + xohms Touchpanel sensitivity (X-plate resistance) + swapxy Swap x and y axis + backlight Change backlight GPIO pin {e.g. 12, 18} + debug "on" = enable additional debug messages + (default "off") + + +Name: merus-amp +Info: Configures the merus-amp audio card +Load: dtoverlay=merus-amp +Params: <None> + + +Name: midi-uart0 +Info: Configures UART0 (ttyAMA0) so that a requested 38.4kbaud actually gets + 31.25kbaud, the frequency required for MIDI +Load: dtoverlay=midi-uart0 +Params: <None> + + +Name: midi-uart0-pi5 +Info: See midi-uart0 (this is the Pi 5 version) + + +Name: midi-uart1 +Info: Configures UART1 (ttyS0) so that a requested 38.4kbaud actually gets + 31.25kbaud, the frequency required for MIDI +Load: dtoverlay=midi-uart1 +Params: <None> + + +Name: midi-uart1-pi5 +Info: See midi-uart1 (this is the Pi 5 version) + + +Name: midi-uart2 +Info: Configures UART2 (ttyAMA2) so that a requested 38.4kbaud actually gets + 31.25kbaud, the frequency required for MIDI +Load: dtoverlay=midi-uart2 +Params: <None> + + +Name: midi-uart2-pi5 +Info: See midi-uart2 (this is the Pi 5 version) + + +Name: midi-uart3 +Info: Configures UART3 (ttyAMA3) so that a requested 38.4kbaud actually gets + 31.25kbaud, the frequency required for MIDI +Load: dtoverlay=midi-uart3 +Params: <None> + + +Name: midi-uart3-pi5 +Info: See midi-uart3 (this is the Pi 5 version) + + +Name: midi-uart4 +Info: Configures UART4 (ttyAMA4) so that a requested 38.4kbaud actually gets + 31.25kbaud, the frequency required for MIDI +Load: dtoverlay=midi-uart4 +Params: <None> + + +Name: midi-uart4-pi5 +Info: See midi-uart4 (this is the Pi 5 version) + + +Name: midi-uart5 +Info: Configures UART5 (ttyAMA5) so that a requested 38.4kbaud actually gets + 31.25kbaud, the frequency required for MIDI +Load: dtoverlay=midi-uart5 +Params: <None> + + +Name: minipitft13 +Info: Overlay for AdaFruit Mini Pi 1.3" TFT via SPI using fbtft driver. +Load: dtoverlay=minipitft13,<param>=<val> +Params: speed SPI bus speed (default 32000000) + rotate Display rotation (0, 90, 180 or 270; default 0) + width Display width (default 240) + height Display height (default 240) + fps Delay between frame updates (default 25) + debug Debug output level (0-7; default 0) + + +Name: miniuart-bt +Info: Switch the onboard Bluetooth function of a BT-equipped Raspberry Pi + to use the mini-UART (ttyS0) and restore UART0/ttyAMA0 over GPIOs 14 & + 15. Note that this option uses a lower baudrate, and should only be used + with low-bandwidth peripherals. +Load: dtoverlay=miniuart-bt,<param>=<val> +Params: krnbt Set to "off" to disable autoprobing of Bluetooth + driver without need of hciattach/btattach + + +Name: mipi-dbi-spi +Info: Overlay for SPI-connected MIPI DBI displays using the panel-mipi-dbi + driver. The driver will load a file /lib/firmware/panel.bin containing + the initialisation commands. + + Example: + dtoverlay=mipi-dbi-spi,spi0-0,speed=70000000 + dtparam=width=320,height=240 + dtparam=reset-gpio=23,dc-gpio=24 + dtparam=backlight-gpio=18 + + Compared to fbtft panel-mipi-dbi runs pixel data at spi-max-frequency + and init commands at 10MHz. This makes it possible to push the envelope + without messing up the controller configuration due to command + transmission errors. + + For devices on spi1 or spi2, the interfaces should be enabled + with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays. + + See https://github.com/notro/panel-mipi-dbi/wiki for more info. + +Load: dtoverlay=mipi-dbi-spi,<param>=<val> +Params: + compatible Set the compatible string to load a different + firmware file. Both the panel compatible value + used to load the firmware file and the value + used to load the driver has to be set having a + NUL (\0) separator between them. + Example: + dtparam=compatible=mypanel\0panel-mipi-dbi-spi + spi<n>-<m> Configure device at spi<n>, cs<m> + (boolean, required) + speed SPI bus speed in Hz (default 32000000) + cpha Shifted SPI clock phase (CPHA) mode + cpol Inverse SPI clock polarity (CPOL) mode + write-only Controller is not readable + (ie. MISO is not wired up). + + width Panel width in pixels (required) + height Panel height in pixels (required) + width-mm Panel width in mm + height-mm Panel height in mm + x-offset Panel x-offset in controller RAM + y-offset Panel y-offset in controller RAM + + clock-frequency Panel clock frequency in Hz + (optional, just informational). + + reset-gpio GPIO pin to be used for RESET + dc-gpio GPIO pin to be used for D/C + + backlight-gpio GPIO pin to be used for backlight control + (default of none). + backlight-pwm PWM channel to be used for backlight control + (default of none). NB Disables audio headphone + output as that also uses PWM. + backlight-pwm-chan Choose channel on &pwm node for backlight + control (default 0). + backlight-pwm-gpio GPIO pin to be used for the PWM backlight. See + pwm-2chan for valid options (default 18). + backlight-pwm-func Pin function of GPIO used for the PWM backlight. + See pwm-2chan for valid options (default 2). + backlight-def-brightness + Set the default brightness. Normal range 1-16. + (default 16). + + +Name: mlx90640 +Info: Overlay for i2c connected mlx90640 thermal camera +Load: dtoverlay=mlx90640 +Params: <None> + + +Name: mmc +Info: Selects the bcm2835-mmc SD/MMC driver, optionally with overclock +Load: dtoverlay=mmc,<param>=<val> +Params: overclock_50 Clock (in MHz) to use when the MMC framework + requests 50MHz + + +Name: mpu6050 +Info: This overlay has been deprecated - use "dtoverlay=i2c-sensor,mpu6050" + instead. Note that "int_pin" is the new name for the "interrupt" + parameter. +Load: <Deprecated> + + +Name: mz61581 +Info: MZ61581 display by Tontec +Load: dtoverlay=mz61581,<param>=<val> +Params: speed Display SPI bus speed + + rotate Display rotation {0,90,180,270} + + fps Delay between frame updates + + txbuflen Transmit buffer length (default 32768) + + debug Debug output level {0-7} + + xohms Touchpanel sensitivity (X-plate resistance) + + +Name: ov2311 +Info: Omnivision OV2311 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=ov2311,<param>=<val> +Params: rotation Mounting rotation of the camera sensor (0 or + 180, default 0) + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + + +Name: ov5647 +Info: Omnivision OV5647 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=ov5647,<param>=<val> +Params: rotation Mounting rotation of the camera sensor (0 or + 180, default 0) + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + vcm Configure a VCM focus drive on the sensor. + + +Name: ov64a40 +Info: Arducam OV64A40 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=ov64a40,<param>=<val> +Params: rotation Mounting rotation of the camera sensor (0 or + 180, default 0) + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + vcm Select lens driver state. Default is enabled, + but vcm=off will disable. + link-frequency Allowable link frequency values to use in Hz: + 456000000 (default), 360000000 + + +Name: ov7251 +Info: Omnivision OV7251 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=ov7251,<param>=<val> +Params: rotation Mounting rotation of the camera sensor (0 or + 180, default 0) + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + media-controller Configure use of Media Controller API for + configuring the sensor (default off) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + + +Name: ov9281 +Info: Omnivision OV9281 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=ov9281,<param>=<val> +Params: rotation Mounting rotation of the camera sensor (0 or + 180, default 0) + orientation Sensor orientation (0 = front, 1 = rear, + 2 = external, default external) + media-controller Configure use of Media Controller API for + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + + +Name: papirus +Info: PaPiRus ePaper Screen by Pi Supply (both HAT and pHAT) +Load: dtoverlay=papirus,<param>=<val> +Params: panel Display panel (required): + 1.44": e1144cs021 + 2.0": e2200cs021 + 2.7": e2271cs021 + + speed Display SPI bus speed + + +Name: pca953x +Info: TI PCA953x family of I2C GPIO expanders. Default is for NXP PCA9534. +Load: dtoverlay=pca953x,<param>=<val> +Params: addr I2C address of expander. Default 0x20. + pca6416 Select the NXP PCA6416 (16 bit) + pca9505 Select the NXP PCA9505 (40 bit) + pca9535 Select the NXP PCA9535 (16 bit) + pca9536 Select the NXP PCA9536 or TI PCA9536 (4 bit) + pca9537 Select the NXP PCA9537 (4 bit) + pca9538 Select the NXP PCA9538 (8 bit) + pca9539 Select the NXP PCA9539 (16 bit) + pca9554 Select the NXP PCA9554 (8 bit) + pca9555 Select the NXP PCA9555 (16 bit) + pca9556 Select the NXP PCA9556 (8 bit) + pca9557 Select the NXP PCA9557 (8 bit) + pca9574 Select the NXP PCA9574 (8 bit) + pca9575 Select the NXP PCA9575 (16 bit) + pca9698 Select the NXP PCA9698 (40 bit) + pcal6416 Select the NXP PCAL6416 (16 bit) + pcal6524 Select the NXP PCAL6524 (24 bit) + pcal9555a Select the NXP PCAL9555A (16 bit) + max7310 Select the Maxim MAX7310 (8 bit) + max7312 Select the Maxim MAX7312 (16 bit) + max7313 Select the Maxim MAX7313 (16 bit) + max7315 Select the Maxim MAX7315 (8 bit) + pca6107 Select the TI PCA6107 (8 bit) + tca6408 Select the TI TCA6408 (8 bit) + tca6416 Select the TI TCA6416 (16 bit) + tca6424 Select the TI TCA6424 (24 bit) + tca9539 Select the TI TCA9539 (16 bit) + tca9554 Select the TI TCA9554 (8 bit) + cat9554 Select the Onnn CAT9554 (8 bit) + pca9654 Select the Onnn PCA9654 (8 bit) + xra1202 Select the Exar XRA1202 (8 bit) + + +Name: pcf857x +Info: NXP PCF857x family of I2C GPIO expanders. +Load: dtoverlay=pcf857x,<param>=<val> +Params: addr I2C address of expander. Default + depends on model selected. + pcf8574 Select the NXP PCF8574 (8 bit) + pcf8574a Select the NXP PCF8574A (8 bit) + pcf8575 Select the NXP PCF8575 (16 bit) + pca8574 Select the NXP PCA8574 (8 bit) + + +Name: pcie-32bit-dma +Info: Force PCIe config to support 32bit DMA addresses at the expense of + having to bounce buffers. +Load: dtoverlay=pcie-32bit-dma +Params: <None> + + +[ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ] + + +[ The pcf8523-rtc overlay has been deleted. See i2c-rtc. ] + + +[ The pcf8563-rtc overlay has been deleted. See i2c-rtc. ] + + +Name: pi3-act-led +Info: This overlay has been renamed act-led, keeping pi3-act-led as an alias + for backwards compatibility. +Load: <Deprecated> + + +Name: pi3-disable-bt +Info: This overlay has been renamed disable-bt, keeping pi3-disable-bt as an + alias for backwards compatibility. +Load: <Deprecated> + + +Name: pi3-disable-wifi +Info: This overlay has been renamed disable-wifi, keeping pi3-disable-wifi as + an alias for backwards compatibility. +Load: <Deprecated> + + +Name: pi3-miniuart-bt +Info: This overlay has been renamed miniuart-bt, keeping pi3-miniuart-bt as + an alias for backwards compatibility. +Load: <Deprecated> + + +Name: pibell +Info: Configures the pibell audio card. +Load: dtoverlay=pibell,<param>=<val> +Params: alsaname Set the name as it appears in ALSA (default + "PiBell") + + +Name: pifacedigital +Info: Configures the PiFace Digital mcp23s17 GPIO port expander. +Load: dtoverlay=pifacedigital,<param>=<val> +Params: spi-present-mask 8-bit integer, bitmap indicating MCP23S17 SPI0 + CS0 address. PiFace Digital supports addresses + 0-3, which can be configured with JP1 and JP2. + + +Name: pifi-40 +Info: Configures the PiFi 40W stereo amplifier +Load: dtoverlay=pifi-40 +Params: <None> + + +Name: pifi-dac-hd +Info: Configures the PiFi DAC HD +Load: dtoverlay=pifi-dac-hd +Params: <None> + + +Name: pifi-dac-zero +Info: Configures the PiFi DAC Zero +Load: dtoverlay=pifi-dac-zero +Params: <None> + + +Name: pifi-mini-210 +Info: Configures the PiFi Mini stereo amplifier +Load: dtoverlay=pifi-mini-210 +Params: <None> + + +Name: piglow +Info: Configures the PiGlow by pimoroni.com +Load: dtoverlay=piglow +Params: <None> + + +Name: piscreen +Info: PiScreen display by OzzMaker.com +Load: dtoverlay=piscreen,<param>=<val> +Params: speed Display SPI bus speed + + rotate Display rotation {0,90,180,270} + + fps Delay between frame updates + + debug Debug output level {0-7} + + xohms Touchpanel sensitivity (X-plate resistance) + + drm Select the DRM/KMS driver instead of the FBTFT + one + + +Name: piscreen2r +Info: PiScreen 2 with resistive TP display by OzzMaker.com +Load: dtoverlay=piscreen2r,<param>=<val> +Params: speed Display SPI bus speed + + rotate Display rotation {0,90,180,270} + + fps Delay between frame updates + + debug Debug output level {0-7} + + xohms Touchpanel sensitivity (X-plate resistance) + + +Name: pisound +Info: Configures the Blokas Labs pisound card +Load: dtoverlay=pisound +Params: <None> + + +Name: pitft22 +Info: Adafruit PiTFT 2.2" screen +Load: dtoverlay=pitft22,<param>=<val> +Params: speed Display SPI bus speed + + rotate Display rotation {0,90,180,270} + + fps Delay between frame updates + + debug Debug output level {0-7} + + +Name: pitft28-capacitive +Info: Adafruit PiTFT 2.8" capacitive touch screen +Load: dtoverlay=pitft28-capacitive,<param>=<val> +Params: speed Display SPI bus speed + + rotate Display rotation {0,90,180,270} + + fps Delay between frame updates + + debug Debug output level {0-7} + + touch-sizex Touchscreen size x (default 240) + + touch-sizey Touchscreen size y (default 320) + + touch-invx Touchscreen inverted x axis + + touch-invy Touchscreen inverted y axis + + touch-swapxy Touchscreen swapped x y axis + + +Name: pitft28-resistive +Info: Adafruit PiTFT 2.8" resistive touch screen +Load: dtoverlay=pitft28-resistive,<param>=<val> +Params: speed Display SPI bus speed + + rotate Display rotation {0,90,180,270} + + fps Delay between frame updates + + debug Debug output level {0-7} + + drm Force the use of the mi0283qt DRM driver (by + default the ili9340 framebuffer driver will + be used in preference if available) + + +Name: pitft35-resistive +Info: Adafruit PiTFT 3.5" resistive touch screen +Load: dtoverlay=pitft35-resistive,<param>=<val> +Params: speed Display SPI bus speed + + rotate Display rotation {0,90,180,270} + + fps Delay between frame updates + + debug Debug output level {0-7} + + drm Force the use of the hx8357d DRM driver (by + default the fb_hx8357d framebuffer driver will + be used in preference if available) + + +Name: pps-gpio +Info: Configures the pps-gpio (pulse-per-second time signal via GPIO). +Load: dtoverlay=pps-gpio,<param>=<val> +Params: gpiopin Input GPIO (default "18") + assert_falling_edge When present, assert is indicated by a falling + edge, rather than by a rising edge (default + off) + capture_clear Generate clear events on the trailing edge + (default off) + pull Desired pull-up/down state (off, down, up) + Default is "off". + + +Name: proto-codec +Info: Configures the PROTO Audio Codec card +Load: dtoverlay=proto-codec +Params: <None> + + +Name: pwm +Info: Configures a single PWM channel + Legal pin,function combinations for each channel: + PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) + PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) + N.B.: + 1) Pin 18 is the only one available on all platforms, and + it is the one used by the I2S audio interface. + Pins 12 and 13 might be better choices on an A+, B+ or Pi2. + 2) The onboard analogue audio output uses both PWM channels. + 3) So be careful mixing audio and PWM. + 4) Currently the clock must have been enabled and configured + by other means. +Load: dtoverlay=pwm,<param>=<val> +Params: pin Output pin (default 18) - see table + func Pin function (default 2 = Alt5) - see above + clock PWM clock frequency (informational) + + +Name: pwm-2chan +Info: Configures both PWM channels + Legal pin,function combinations for each channel: + PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) + PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) + N.B.: + 1) Pin 18 is the only one available on all platforms, and + it is the one used by the I2S audio interface. + Pins 12 and 13 might be better choices on an A+, B+ or Pi2. + 2) The onboard analogue audio output uses both PWM channels. + 3) So be careful mixing audio and PWM. + 4) Currently the clock must have been enabled and configured + by other means. +Load: dtoverlay=pwm-2chan,<param>=<val> +Params: pin Output pin (default 18) - see table + pin2 Output pin for other channel (default 19) + func Pin function (default 2 = Alt5) - see above + func2 Function for pin2 (default 2 = Alt5) + clock PWM clock frequency (informational) + + +Name: pwm-ir-tx +Info: Use GPIO pin as pwm-assisted infrared transmitter output. + This is an alternative to "gpio-ir-tx". pwm-ir-tx makes use + of PWM0 to reduce the CPU load during transmission compared to + gpio-ir-tx which uses bit-banging. + Legal pin,function combinations are: + 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) +Load: dtoverlay=pwm-ir-tx,<param>=<val> +Params: gpio_pin Output GPIO (default 18) + + func Pin function (default 2 = Alt5) + + +Name: pwm1 +Info: Configures one or two PWM channel on PWM1 (BCM2711 only) + N.B.: + 1) The onboard analogue audio output uses both PWM channels. + 2) So be careful mixing audio and PWM. + Note that even when only one pin is enabled, both channels are available + from the PWM driver, so be careful to use the correct one. +Load: dtoverlay=pwm1,<param>=<val> +Params: clock PWM clock frequency (informational) + pins_40 Enable channel 0 (PWM1_0) on GPIO 40 + pins_41 Enable channel 1 (PWM1_1) on GPIO 41 + pins_40_41 Enable channels 0 (PWM1_0) and 1 (PW1_1) on + GPIOs 40 and 41 (default) + pull_up Enable pull-ups on the PWM pins (default) + pull_down Enable pull-downs on the PWM pins + pull_off Disable pulls on the PWM pins + + +Name: qca7000 +Info: in-tech's Evaluation Board for PLC Stamp micro + This uses spi0 and a separate GPIO interrupt to connect the QCA7000. +Load: dtoverlay=qca7000,<param>=<val> +Params: int_pin GPIO pin for interrupt signal (default 23) + + speed SPI bus speed (default 12 MHz) + + +Name: qca7000-uart0 +Info: in-tech's Evaluation Board for PLC Stamp micro (UART) + This uses uart0/ttyAMA0 over GPIOs 14 & 15 to connect the QCA7000. + But it requires disabling of onboard Bluetooth on + Pi 3B, 3B+, 3A+, 4B and Zero W. +Load: dtoverlay=qca7000-uart0,<param>=<val> +Params: baudrate Set the baudrate for the UART (default + "115200") + + +Name: ramoops +Info: Enable the preservation of crash logs across a reboot. With + systemd-pstore enabled (as it is on Raspberry Pi OS) the crash logs + are moved to /var/lib/systemd/pstore/ on reboot. +Load: dtoverlay=ramoops,<param>=<val> +Params: base-addr Where to place the capture buffer (default + 0x0b000000) + total-size How much memory to allocate altogether (in + bytes - default 64kB) + record-size How much space to use for each capture, i.e. + total-size / record-size = number of captures + (default 16kB) + console-size Size of non-panic dmesg captures (default 0) + + +Name: ramoops-pi4 +Info: The version of the ramoops overlay for the Pi 4 family. It should be + loaded automatically if dtoverlay=ramoops is specified on a Pi 4. +Load: dtoverlay=ramoops-pi4,<param>=<val> +Params: base-addr Where to place the capture buffer (default + 0x0b000000) + total-size How much memory to allocate altogether (in + bytes - default 64kB) + record-size How much space to use for each capture, i.e. + total-size / record-size = number of captures + (default 16kB) + console-size Size of non-panic dmesg captures (default 0) + + +Name: rotary-encoder +Info: Overlay for GPIO connected rotary encoder. +Load: dtoverlay=rotary-encoder,<param>=<val> +Params: pin_a GPIO connected to rotary encoder channel A + (default 4). + pin_b GPIO connected to rotary encoder channel B + (default 17). + relative_axis register a relative axis rather than an + absolute one. Relative axis will only + generate +1/-1 events on the input device, + hence no steps need to be passed. + linux_axis the input subsystem axis to map to this + rotary encoder. Defaults to 0 (ABS_X / REL_X) + rollover Automatic rollover when the rotary value + becomes greater than the specified steps or + smaller than 0. For absolute axis only. + steps-per-period Number of steps (stable states) per period. + The values have the following meaning: + 1: Full-period mode (default) + 2: Half-period mode + 4: Quarter-period mode + steps Number of steps in a full turnaround of the + encoder. Only relevant for absolute axis. + Defaults to 24 which is a typical value for + such devices. + wakeup Boolean, rotary encoder can wake up the + system. + encoding String, the method used to encode steps. + Supported are "gray" (the default and more + common) and "binary". + + +Name: rpi-backlight +Info: Raspberry Pi official display backlight driver +Load: dtoverlay=rpi-backlight +Params: <None> + + +Name: rpi-cirrus-wm5102 +Info: This overlay has been renamed to cirrus-wm5102 +Load: <Deprecated> + + +Name: rpi-codeczero +Info: Configures the Raspberry Pi Codec Zero sound card +Load: dtoverlay=rpi-codeczero +Params: <None> + + +Name: rpi-dac +Info: This overlay has been renamed to i2s-dac. +Load: <Deprecated> + + +Name: rpi-dacplus +Info: Configures the Raspberry Pi DAC+ card +Load: dtoverlay=rpi-dacplus,<param>=<val> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + digital volume control. Enable by adding + "dtparam=24db_digital_gain" to config.txt + before any "dtoverlay" lines. + The default behaviour is that the digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24db_digital_gain parameter, the digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the digital volume control is set to a value + that does not result in clipping/distortion! + + +Name: rpi-dacpro +Info: Configures the Raspberry Pi DAC Pro sound card +Load: dtoverlay=rpi-dacpro,<param>=<val> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + digital volume control. Enable by adding + "dtparam=24db_digital_gain" to config.txt + before any "dtoverlay" lines. + The default behaviour is that the digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24db_digital_gain parameter, the digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the digital volume control is set to a value + that does not result in clipping/distortion! + + +Name: rpi-digiampplus +Info: Configures the Raspberry Pi DigiAMP+ sound card +Load: dtoverlay=rpi-digiampplus,<param>=<val> +Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec + digital volume control. Enable by adding + "dtparam=24db_digital_gain" to config.txt + before any "dtoverlay" lines. + The default behaviour is that the digital + volume control is limited to a maximum of + 0dB. ie. it can attenuate but not provide + gain. For most users, this will be desired + as it will prevent clipping. By appending + the 24db_digital_gain parameter, the digital + volume control will allow up to 24dB of + gain. If this parameter is enabled, it is the + responsibility of the user to ensure that + the digital volume control is set to a value + that does not result in clipping/distortion! + auto_mute_amp If specified, unmute/mute the DigiAMP+ when + starting/stopping audio playback (default "on"). + unmute_amp If specified, unmute the DigiAMP+ amp once when + the DAC driver module loads (default "off"). + + +Name: rpi-display +Info: This overlay has been renamed to watterott-display +Load: <Deprecated> + + +Name: rpi-ft5406 +Info: Official Raspberry Pi display touchscreen +Load: dtoverlay=rpi-ft5406,<param>=<val> +Params: touchscreen-size-x Touchscreen X resolution (default 800) + touchscreen-size-y Touchscreen Y resolution (default 480); + touchscreen-inverted-x Invert touchscreen X coordinates (default 0); + touchscreen-inverted-y Invert touchscreen Y coordinates (default 0); + touchscreen-swapped-x-y Swap X and Y cordinates (default 0); + + +Name: rpi-poe +Info: Raspberry Pi PoE HAT fan +Load: dtoverlay=rpi-poe,<param>[=<val>] +Params: poe_fan_temp0 Temperature (in millicelcius) at which the fan + turns on (default 40000) + poe_fan_temp0_hyst Temperature delta (in millicelcius) at which + the fan turns off (default 2000) + poe_fan_temp1 Temperature (in millicelcius) at which the fan + speeds up (default 45000) + poe_fan_temp1_hyst Temperature delta (in millicelcius) at which + the fan slows down (default 2000) + poe_fan_temp2 Temperature (in millicelcius) at which the fan + speeds up (default 50000) + poe_fan_temp2_hyst Temperature delta (in millicelcius) at which + the fan slows down (default 2000) + poe_fan_temp3 Temperature (in millicelcius) at which the fan + speeds up (default 55000) + poe_fan_temp3_hyst Temperature delta (in millicelcius) at which + the fan slows down (default 5000) + i2c Control the fan via Linux I2C drivers instead of + the firmware. + + +Name: rpi-poe-plus +Info: Raspberry Pi PoE+ HAT fan +Load: dtoverlay=rpi-poe-plus,<param>[=<val>] +Params: poe_fan_temp0 Temperature (in millicelcius) at which the fan + turns on (default 40000) + poe_fan_temp0_hyst Temperature delta (in millicelcius) at which + the fan turns off (default 2000) + poe_fan_temp1 Temperature (in millicelcius) at which the fan + speeds up (default 45000) + poe_fan_temp1_hyst Temperature delta (in millicelcius) at which + the fan slows down (default 2000) + poe_fan_temp2 Temperature (in millicelcius) at which the fan + speeds up (default 50000) + poe_fan_temp2_hyst Temperature delta (in millicelcius) at which + the fan slows down (default 2000) + poe_fan_temp3 Temperature (in millicelcius) at which the fan + speeds up (default 55000) + poe_fan_temp3_hyst Temperature delta (in millicelcius) at which + the fan slows down (default 5000) + i2c Control the fan via Linux I2C drivers instead of + the firmware. + + +Name: rpi-proto +Info: This overlay has been renamed to proto-codec. +Load: <Deprecated> + + +Name: rpi-sense +Info: Raspberry Pi Sense HAT +Load: dtoverlay=rpi-sense +Params: <None> + + +Name: rpi-sense-v2 +Info: Raspberry Pi Sense HAT v2 +Load: dtoverlay=rpi-sense-v2 +Params: <None> + + +Name: rpi-tv +Info: Raspberry Pi TV HAT +Load: dtoverlay=rpi-tv +Params: <None> + + +Name: rpivid-v4l2 +Info: This overlay has been deprecated and deleted as the V4L2 stateless + video decoder driver is enabled by default. +Load: <Deprecated> + + +Name: rra-digidac1-wm8741-audio +Info: Configures the Red Rocks Audio DigiDAC1 soundcard +Load: dtoverlay=rra-digidac1-wm8741-audio +Params: <None> + + +Name: sainsmart18 +Info: Overlay for the SPI-connected Sainsmart 1.8" display (based on the + ST7735R chip). +Load: dtoverlay=sainsmart18,<param>=<val> +Params: rotate Display rotation {0,90,180,270} + speed SPI bus speed in Hz (default 4000000) + fps Display frame rate in Hz + bgr Enable BGR mode (default off) + debug Debug output level {0-7} + dc_pin GPIO pin for D/C (default 24) + reset_pin GPIO pin for RESET (default 25) + + +Name: sc16is750-i2c +Info: Overlay for the NXP SC16IS750 UART with I2C Interface + Enables the chip on I2C1 at 0x48 (or the "addr" parameter value). To + select another address, please refer to table 10 in reference manual. +Load: dtoverlay=sc16is750-i2c,<param>=<val> +Params: int_pin GPIO used for IRQ (default 24) + addr Address (default 0x48) + xtal On-board crystal frequency (default 14745600) + + +Name: sc16is752-i2c +Info: Overlay for the NXP SC16IS752 dual UART with I2C Interface + Enables the chip on I2C1 at 0x48 (or the "addr" parameter value). To + select another address, please refer to table 10 in reference manual. +Load: dtoverlay=sc16is752-i2c,<param>=<val> +Params: int_pin GPIO used for IRQ (default 24) + addr Address (default 0x48) + xtal On-board crystal frequency (default 14745600) + + +Name: sc16is752-spi0 +Info: Overlay for the NXP SC16IS752 Dual UART with SPI Interface + Enables the chip on SPI0. +Load: dtoverlay=sc16is752-spi0,<param>=<val> +Params: int_pin GPIO used for IRQ (default 24) + xtal On-board crystal frequency (default 14745600) + + +Name: sc16is752-spi1 +Info: Overlay for the NXP SC16IS752 Dual UART with SPI Interface + Enables the chip on SPI1. + N.B.: spi1 is only accessible on devices with a 40pin header, eg: + A+, B+, Zero and PI2 B; as well as the Compute Module. + +Load: dtoverlay=sc16is752-spi1,<param>=<val> +Params: int_pin GPIO used for IRQ (default 24) + xtal On-board crystal frequency (default 14745600) + + +Name: sdhost +Info: Selects the bcm2835-sdhost SD/MMC driver, optionally with overclock. + N.B. This overlay is designed for situations where the mmc driver is + the default, so it disables the other (mmc) interface - this will kill + WLAN on a Pi3. If this isn't what you want, either use the sdtweak + overlay or the new sd_* dtparams of the base DTBs. +Load: dtoverlay=sdhost,<param>=<val> +Params: overclock_50 Clock (in MHz) to use when the MMC framework + requests 50MHz + + force_pio Disable DMA support (default off) + + pio_limit Number of blocks above which to use DMA + (default 1) + + debug Enable debug output (default off) + + +Name: sdio +Info: Selects the bcm2835-sdhost SD/MMC driver, optionally with overclock, + and enables SDIO via GPIOs 22-27. An example of use in 1-bit mode is + "dtoverlay=sdio,bus_width=1,gpios_22_25" +Load: dtoverlay=sdio,<param>=<val> +Params: sdio_overclock SDIO Clock (in MHz) to use when the MMC + framework requests 50MHz + + poll_once Disable SDIO-device polling every second + (default on: polling once at boot-time) + + bus_width Set the SDIO host bus width (default 4 bits) + + gpios_22_25 Select GPIOs 22-25 for 1-bit mode. Must be used + with bus_width=1. This replaces the sdio-1bit + overlay, which is now deprecated. + + gpios_34_37 Select GPIOs 34-37 for 1-bit mode. Must be used + with bus_width=1. + + gpios_34_39 Select GPIOs 34-39 for 4-bit mode. Must be used + with bus_width=4 (the default). + + +Name: sdio-1bit +Info: This overlay is now deprecated. Use + "dtoverlay=sdio,bus_width=1,gpios_22_25" instead. +Load: <Deprecated> + + +Name: sdio-pi5 +Info: Selects the rp1_mmc0 interface and enables it on GPIOs 22-27. + Pi 5 only. +Load: dtoverlay=sdio-pi5 +Params: <None> + + +Name: sdtweak +Info: This overlay is now deprecated. Use the sd_* dtparams in the + base DTB, e.g. "dtoverlay=sdtweak,poll_once" becomes + "dtparam=sd_poll_once". +Load: <Deprecated> + + +Name: seeed-can-fd-hat-v1 +Info: Overlay for Seeed Studio CAN BUS FD HAT with two CAN FD + channels without RTC. Use this overlay if your HAT has no + battery holder. + https://www.seeedstudio.com/2-Channel-CAN-BUS-FD-Shield-for-Raspberry-Pi-p-4072.html +Load: dtoverlay=seeed-can-fd-hat-v1 +Params: <None> + + +Name: seeed-can-fd-hat-v2 +Info: Overlay for Seeed Studio CAN BUS FD HAT with two CAN FD + channels and an RTC. Use this overlay if your HAT has a + battery holder. + https://www.seeedstudio.com/CAN-BUS-FD-HAT-for-Raspberry-Pi-p-4742.html +Load: dtoverlay=seeed-can-fd-hat-v2 +Params: <None> + + +Name: sh1106-spi +Info: Overlay for SH1106 OLED via SPI using fbtft staging driver. +Load: dtoverlay=sh1106-spi,<param>=<val> +Params: speed SPI bus speed (default 4000000) + rotate Display rotation (0, 90, 180 or 270; default 0) + fps Delay between frame updates (default 25) + debug Debug output level (0-7; default 0) + dc_pin GPIO pin for D/C (default 24) + reset_pin GPIO pin for RESET (default 25) + height Display height (32 or 64; default 64) + + +Name: si446x-spi0 +Info: Overlay for Si446x UHF Transceiver via SPI using si446x driver. + The driver is currently out-of-tree at + https://github.com/sunipkmukherjee/silabs.git +Load: dtoverlay=si446x-spi0,<param>=<val> +Params: speed SPI bus speed (default 4000000) + int_pin GPIO pin for interrupts (default 17) + reset_pin GPIO pin for RESET (default 27) + + +Name: smi +Info: Enables the Secondary Memory Interface peripheral. Uses GPIOs 2-25! +Load: dtoverlay=smi +Params: <None> + + +Name: smi-dev +Info: Enables the userspace interface for the SMI driver +Load: dtoverlay=smi-dev +Params: <None> + + +Name: smi-nand +Info: Enables access to NAND flash via the SMI interface +Load: dtoverlay=smi-nand +Params: <None> + + +Name: spi-gpio35-39 +Info: Move SPI function block to GPIO 35 to 39 +Load: dtoverlay=spi-gpio35-39 +Params: <None> + + +Name: spi-gpio40-45 +Info: Move SPI function block to GPIOs 40 to 45 +Load: dtoverlay=spi-gpio40-45 +Params: <None> + + +Name: spi-rtc +Info: Adds support for a number of SPI Real Time Clock devices +Load: dtoverlay=spi-rtc,<param>=<val> +Params: ds3232 Select the DS3232 device + ds3234 Select the DS3234 device + pcf2123 Select the PCF2123 device + + spi0_0 Use spi0.0 (default) + spi0_1 Use spi0.1 + spi1_0 Use spi1.0 + spi1_1 Use spi1.1 + spi2_0 Use spi2.0 + spi2_1 Use spi2.1 + cs_high This device requires an active-high CS + + +Name: spi0-0cs +Info: Don't claim any CS pins for SPI0. Requires a device with its chip + select permanently enabled, but frees a GPIO for e.g. a DPI display. +Load: dtoverlay=spi0-0cs,<param>=<val> +Params: no_miso Don't claim and use the MISO pin (9), freeing + it for other uses. + + +Name: spi0-1cs +Info: Only use one CS pin for SPI0 +Load: dtoverlay=spi0-1cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 8) + no_miso Don't claim and use the MISO pin (9), freeing + it for other uses. + + +Name: spi0-2cs +Info: Change the CS pins for SPI0 +Load: dtoverlay=spi0-2cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 8) + cs1_pin GPIO pin for CS1 (default 7) + no_miso Don't claim and use the MISO pin (9), freeing + it for other uses. + + +Name: spi0-cs +Info: This overlay has been renamed spi0-2cs, keeping spi0-cs as an + alias for backwards compatibility. +Load: <Deprecated> + + +Name: spi0-hw-cs +Info: This overlay has been deprecated and removed because it is no longer + necessary and has been seen to prevent spi0 from working. +Load: <Deprecated> + + +Name: spi1-1cs +Info: Enables spi1 with a single chip select (CS) line and associated spidev + dev node. The gpio pin number for the CS line and spidev device node + creation are configurable. + N.B.: spi1 is not accessible on old Pis without a 40-pin header. +Load: dtoverlay=spi1-1cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 18 - BCM SPI1_CE0). + cs0_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev1.0 (default + is 'on' or enabled). + + +Name: spi1-2cs +Info: Enables spi1 with two chip select (CS) lines and associated spidev + dev nodes. The gpio pin numbers for the CS lines and spidev device node + creation are configurable. + N.B.: spi1 is not accessible on old Pis without a 40-pin header. +Load: dtoverlay=spi1-2cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 18 - BCM SPI1_CE0). + cs1_pin GPIO pin for CS1 (default 17 - BCM SPI1_CE1). + cs0_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev1.0 (default + is 'on' or enabled). + cs1_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev1.1 (default + is 'on' or enabled). + + +Name: spi1-3cs +Info: Enables spi1 with three chip select (CS) lines and associated spidev + dev nodes. The gpio pin numbers for the CS lines and spidev device node + creation are configurable. + N.B.: spi1 is not accessible on old Pis without a 40-pin header. +Load: dtoverlay=spi1-3cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 18 - BCM SPI1_CE0). + cs1_pin GPIO pin for CS1 (default 17 - BCM SPI1_CE1). + cs2_pin GPIO pin for CS2 (default 16 - BCM SPI1_CE2). + cs0_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev1.0 (default + is 'on' or enabled). + cs1_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev1.1 (default + is 'on' or enabled). + cs2_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev1.2 (default + is 'on' or enabled). + + +Name: spi2-1cs +Info: Enables spi2 on GPIOs 40-42 with a single chip select (CS) line and + associated spidev dev node. The gpio pin number for the CS line and + spidev device node creation are configurable. spi2-2cs-pi5 is + substituted on a Pi 5. + N.B.: spi2 is only accessible with the Compute Module or Pi 5. +Load: dtoverlay=spi2-1cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 43 - BCM SPI2_CE0). + cs0_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev2.0 (default + is 'on' or enabled). + + +Name: spi2-1cs-pi5 +Info: Enables spi2 on GPIOs 1-3 with a single chip select (CS) line and + associated spidev dev node. The gpio pin number for the CS line and + spidev device node creation are configurable. Pi 5 only. +Load: dtoverlay=spi2-1cs-pi5,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 0). + cs0_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev2.0 (default + is 'on' or enabled). + + +Name: spi2-2cs +Info: Enables spi2 on GPIOs 40-42 with two chip select (CS) lines and + associated spidev dev nodes. The gpio pin numbers for the CS lines and + spidev device node creation are configurable. spi2-2cs-pi5 is + substituted on a Pi 5. + N.B.: spi2 is only accessible with the Compute Module or Pi 5. +Load: dtoverlay=spi2-2cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 43 - BCM SPI2_CE0). + cs1_pin GPIO pin for CS1 (default 44 - BCM SPI2_CE1). + cs0_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev2.0 (default + is 'on' or enabled). + cs1_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev2.1 (default + is 'on' or enabled). + + +Name: spi2-2cs-pi5 +Info: Enables spi2 on GPIOs 1-3 with two chip select (CS) lines and + associated spidev dev nodes. The gpio pin numbers for the CS lines and + spidev device node creation are configurable. Pi 5 only. +Load: dtoverlay=spi2-2cs-pi5,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 0). + cs1_pin GPIO pin for CS1 (default 24). + cs0_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev2.0 (default + is 'on' or enabled). + cs1_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev2.1 (default + is 'on' or enabled). + + +Name: spi2-3cs +Info: Enables spi2 on GPIOs 40-42 with three chip select (CS) lines and + associated spidev dev nodes. The gpio pin numbers for the CS lines and + spidev device node creation are configurable. + N.B.: spi2 is only accessible with the Compute Module or Pi 5. +Load: dtoverlay=spi2-3cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 43 - BCM SPI2_CE0). + cs1_pin GPIO pin for CS1 (default 44 - BCM SPI2_CE1). + cs2_pin GPIO pin for CS2 (default 45 - BCM SPI2_CE2). + cs0_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev2.0 (default + is 'on' or enabled). + cs1_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev2.1 (default + is 'on' or enabled). + cs2_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev2.2 (default + is 'on' or enabled). + + +Name: spi3-1cs +Info: Enables spi3 on GPIOs 1-3 with a single chip select (CS) line and + associated spidev dev node. The gpio pin number for the CS line and + spidev device node creation are configurable. BCM2711 only, + spi3-1cs-pi5 is substituted on Pi 5. +Load: dtoverlay=spi3-1cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 0 - BCM SPI3_CE0). + cs0_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev3.0 (default + is 'on' or enabled). + + +Name: spi3-1cs-pi5 +Info: Enables spi3 on GPIOs 5-7 with a single chip select (CS) line and + associated spidev dev node. The gpio pin number for the CS line and + spidev device node creation are configurable. Pi 5 only. +Load: dtoverlay=spi3-1cs-pi5,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 4). + cs0_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev3.0 (default + is 'on' or enabled). + + +Name: spi3-2cs +Info: Enables spi3 on GPIO2 1-3 with two chip select (CS) lines and + associated spidev dev nodes. The gpio pin numbers for the CS lines and + spidev device node creation are configurable. BCM2711 only, + spi3-2cs-pi5 is substituted on Pi 5. +Load: dtoverlay=spi3-2cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 0 - BCM SPI3_CE0). + cs1_pin GPIO pin for CS1 (default 24 - BCM SPI3_CE1). + cs0_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev3.0 (default + is 'on' or enabled). + cs1_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev3.1 (default + is 'on' or enabled). + + +Name: spi3-2cs-pi5 +Info: Enables spi3 on GPIOs 5-7 with two chip select (CS) lines and + associated spidev dev nodes. The gpio pin numbers for the CS lines and + spidev device node creation are configurable. Pi 5 only. +Load: dtoverlay=spi3-2cs-pi5,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 4). + cs1_pin GPIO pin for CS1 (default 25). + cs0_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev3.0 (default + is 'on' or enabled). + cs1_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev3.1 (default + is 'on' or enabled). + + +Name: spi4-1cs +Info: Enables spi4 on GPIOs 5-7 with a single chip select (CS) line and + associated spidev dev node. The gpio pin number for the CS line and + spidev device node creation are configurable. BCM2711 only. +Load: dtoverlay=spi4-1cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 4 - BCM SPI4_CE0). + cs0_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev4.0 (default + is 'on' or enabled). + + +Name: spi4-2cs +Info: Enables spi4 on GPIOs 5-6 with two chip select (CS) lines and + associated spidev dev nodes. The gpio pin numbers for the CS lines and + spidev device node creation are configurable. BCM2711 only. +Load: dtoverlay=spi4-2cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 4 - BCM SPI4_CE0). + cs1_pin GPIO pin for CS1 (default 25 - BCM SPI4_CE1). + cs0_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev4.0 (default + is 'on' or enabled). + cs1_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev4.1 (default + is 'on' or enabled). + + +Name: spi5-1cs +Info: Enables spi5 on GPIOs 13-15 with a single chip select (CS) line and + associated spidev dev node. The gpio pin numbers for the CS lines and + spidev device node creation are configurable. BCM2711 and Pi 5. +Load: dtoverlay=spi5-1cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 12). + cs0_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev5.0 (default + is 'on' or enabled). + + +Name: spi5-1cs-pi5 +Info: See spi5-1cs + + +Name: spi5-2cs +Info: Enables spi5 on GPIOs 13-15 with two chip select (CS) lines and + associated spidev dev nodes. The gpio pin numbers for the CS lines and + spidev device node creation are configurable. BCM2711 and Pi 5. +Load: dtoverlay=spi5-2cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 12). + cs1_pin GPIO pin for CS1 (default 26). + cs0_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev5.0 (default + is 'on' or enabled). + cs1_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev5.1 (default + is 'on' or enabled). + + +Name: spi5-2cs-pi5 +Info: See spi5-2cs + + +Name: spi6-1cs +Info: Enables spi6 with a single chip select (CS) line and associated spidev + dev node. The gpio pin number for the CS line and spidev device node + creation are configurable. BCM2711 only. +Load: dtoverlay=spi6-1cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 18 - BCM SPI6_CE0). + cs0_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev6.0 (default + is 'on' or enabled). + + +Name: spi6-2cs +Info: Enables spi6 with two chip select (CS) lines and associated spidev + dev nodes. The gpio pin numbers for the CS lines and spidev device node + creation are configurable. BCM2711 only. +Load: dtoverlay=spi6-2cs,<param>=<val> +Params: cs0_pin GPIO pin for CS0 (default 18 - BCM SPI6_CE0). + cs1_pin GPIO pin for CS1 (default 27 - BCM SPI6_CE1). + cs0_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev6.0 (default + is 'on' or enabled). + cs1_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev6.1 (default + is 'on' or enabled). + + +Name: ssd1306 +Info: Overlay for activation of SSD1306 over I2C OLED display framebuffer. +Load: dtoverlay=ssd1306,<param>=<val> +Params: address Location in display memory of first character. + (default=0) + width Width of display. (default=128) + height Height of display. (default=64) + offset virtual channel a. (default=0) + normal Has no effect on displays tested. (default=not + set) + sequential Set this if every other scan line is missing. + (default=not set) + remapped Set this if display is garbled. (default=not + set) + inverted Set this if display is inverted and mirrored. + (default=not set) + + Examples: + Typical usage for 128x64 display: dtoverlay=ssd1306,inverted + + Typical usage for 128x32 display: dtoverlay=ssd1306,inverted,sequential + + i2c_baudrate=400000 will speed up the display. + + i2c_baudrate=1000000 seems to work even though it's not officially + supported by the hardware, and is faster still. + + For more information refer to the device datasheet at: + https://cdn-shop.adafruit.com/datasheets/SSD1306.pdf + + +Name: ssd1306-spi +Info: Overlay for SSD1306 OLED via SPI using fbtft staging driver. +Load: dtoverlay=ssd1306-spi,<param>=<val> +Params: speed SPI bus speed (default 10000000) + rotate Display rotation (0, 90, 180 or 270; default 0) + fps Delay between frame updates (default 25) + debug Debug output level (0-7; default 0) + dc_pin GPIO pin for D/C (default 24) + reset_pin GPIO pin for RESET (default 25) + height Display height (32 or 64; default 64) + inverted Set this if display is inverted and mirrored. + (default=not set) + + +Name: ssd1331-spi +Info: Overlay for SSD1331 OLED via SPI using fbtft staging driver. +Load: dtoverlay=ssd1331-spi,<param>=<val> +Params: speed SPI bus speed (default 4500000) + rotate Display rotation (0, 90, 180 or 270; default 0) + fps Delay between frame updates (default 25) + debug Debug output level (0-7; default 0) + dc_pin GPIO pin for D/C (default 24) + reset_pin GPIO pin for RESET (default 25) + + +Name: ssd1351-spi +Info: Overlay for SSD1351 OLED via SPI using fbtft staging driver. +Load: dtoverlay=ssd1351-spi,<param>=<val> +Params: speed SPI bus speed (default 4500000) + rotate Display rotation (0, 90, 180 or 270; default 0) + fps Delay between frame updates (default 25) + debug Debug output level (0-7; default 0) + dc_pin GPIO pin for D/C (default 24) + reset_pin GPIO pin for RESET (default 25) + + +Name: superaudioboard +Info: Configures the SuperAudioBoard sound card +Load: dtoverlay=superaudioboard,<param>=<val> +Params: gpiopin GPIO pin for codec reset + + +Name: sx150x +Info: Configures the Semtech SX150X I2C GPIO expanders. +Load: dtoverlay=sx150x,<param>=<val> +Params: sx150<x>-<n>-<m> Enables SX150X device on I2C#<n> with slave + address <m>. <x> may be 1-9. <n> may be 0 or 1. + Permissible values of <m> (which is denoted in + hex) depend on the device variant. For SX1501, + SX1502, SX1504 and SX1505, <m> may be 20 or 21. + For SX1503 and SX1506, <m> may be 20. For + SX1507 and SX1509, <m> may be 3E, 3F, 70 or 71. + For SX1508, <m> may be 20, 21, 22 or 23. + + sx150<x>-<n>-<m>-int-gpio + Integer, enables interrupts on SX150X device on + I2C#<n> with slave address <m>, specifies + the GPIO pin to which NINT output of SX150X is + connected. + + +Name: tc358743 +Info: Toshiba TC358743 HDMI to CSI-2 bridge chip. + Uses Unicam 1, which is the standard camera connector on most Pi + variants. +Load: dtoverlay=tc358743,<param>=<val> +Params: 4lane Use 4 lanes (only applicable to Compute Modules + CAM1 connector). + + link-frequency Set the link frequency. Only values of 297000000 + (574Mbit/s) and 486000000 (972Mbit/s - default) + are supported by the driver. + media-controller Configure use of Media Controller API for + configuring the sensor (default off) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). + + +Name: tc358743-audio +Info: Used in combination with the tc358743-fast overlay to route the audio + from the TC358743 over I2S to the Pi. + Wiring is LRCK/WFS to GPIO 19, BCK/SCK to GPIO 18, and DATA/SD to GPIO + 20. +Load: dtoverlay=tc358743-audio,<param>=<val> +Params: card-name Override the default, "tc358743", card name. + + +Name: tinylcd35 +Info: 3.5" Color TFT Display by www.tinylcd.com + Options: Touch, RTC, keypad +Load: dtoverlay=tinylcd35,<param>=<val> +Params: speed Display SPI bus speed + + rotate Display rotation {0,90,180,270} + + fps Delay between frame updates + + debug Debug output level {0-7} + + touch Enable touch panel + + touchgpio Touch controller IRQ GPIO + + xohms Touchpanel: Resistance of X-plate in ohms + + rtc-pcf PCF8563 Real Time Clock + + rtc-ds DS1307 Real Time Clock + + keypad Enable keypad + + Examples: + Display with touchpanel, PCF8563 RTC and keypad: + dtoverlay=tinylcd35,touch,rtc-pcf,keypad + Old touch display: + dtoverlay=tinylcd35,touch,touchgpio=3 + + +Name: tpm-slb9670 +Info: Enables support for Infineon SLB9670 Trusted Platform Module add-on + boards, which can be used as a secure key storage and hwrng, + available as "Iridium SLB9670" by Infineon and "LetsTrust TPM" by pi3g. +Load: dtoverlay=tpm-slb9670 +Params: <None> + + +Name: tpm-slb9673 +Info: Enables support for Infineon SLB9673 Trusted Platform Module add-on + boards, which can be used as a secure key storage and hwrng + via the I2C protocol. +Load: dtoverlay=tpm-slb9673 +Params: <None> + + +Name: uart0 +Info: Change the pin usage of uart0 +Load: dtoverlay=uart0,<param>=<val> +Params: txd0_pin GPIO pin for TXD0 (14, 32 or 36 - default 14) + + rxd0_pin GPIO pin for RXD0 (15, 33 or 37 - default 15) + + pin_func Alternative pin function - 4(Alt0) for 14&15, + 7(Alt3) for 32&33, 6(Alt2) for 36&37 + + +Name: uart0-pi5 +Info: Enable uart 0 on GPIOs 14-15. Pi 5 only. +Load: dtoverlay=uart0-pi5,<param> +Params: ctsrts Enable CTS/RTS on GPIOs 16-17 (default off) + + +Name: uart1 +Info: Change the pin usage of uart1 +Load: dtoverlay=uart1,<param>=<val> +Params: txd1_pin GPIO pin for TXD1 (14, 32 or 40 - default 14) + + rxd1_pin GPIO pin for RXD1 (15, 33 or 41 - default 15) + + +Name: uart1-pi5 +Info: Enable uart 1 on GPIOs 0-1. Pi 5 only. +Load: dtoverlay=uart1-pi5,<param> +Params: ctsrts Enable CTS/RTS on GPIOs 2-3 (default off) + + +Name: uart2 +Info: Enable uart 2 on GPIOs 0-3. BCM2711 only. +Load: dtoverlay=uart2,<param> +Params: ctsrts Enable CTS/RTS on GPIOs 2-3 (default off) + + +Name: uart2-pi5 +Info: Enable uart 2 on GPIOs 4-5. Pi 5 only. +Load: dtoverlay=uart2-pi5,<param> +Params: ctsrts Enable CTS/RTS on GPIOs 6-7 (default off) + + +Name: uart3 +Info: Enable uart 3 on GPIOs 4-7. BCM2711 only. +Load: dtoverlay=uart3,<param> +Params: ctsrts Enable CTS/RTS on GPIOs 6-7 (default off) + + +Name: uart3-pi5 +Info: Enable uart 3 on GPIOs 8-9. Pi 5 only. +Load: dtoverlay=uart3-pi5,<param> +Params: ctsrts Enable CTS/RTS on GPIOs 10-11 (default off) + + +Name: uart4 +Info: Enable uart 4 on GPIOs 8-11. BCM2711 only. +Load: dtoverlay=uart4,<param> +Params: ctsrts Enable CTS/RTS on GPIOs 10-11 (default off) + + +Name: uart4-pi5 +Info: Enable uart 4 on GPIOs 12-13. Pi 5 only. +Load: dtoverlay=uart4-pi5,<param> +Params: ctsrts Enable CTS/RTS on GPIOs 14-15 (default off) + + +Name: uart5 +Info: Enable uart 5 on GPIOs 12-15. BCM2711 only. +Load: dtoverlay=uart5,<param> +Params: ctsrts Enable CTS/RTS on GPIOs 14-15 (default off) + + +Name: udrc +Info: Configures the NW Digital Radio UDRC Hat +Load: dtoverlay=udrc,<param>=<val> +Params: alsaname Name of the ALSA audio device (default "udrc") + + +Name: ugreen-dabboard +Info: Configures the ugreen-dabboard I2S overlay + This is a simple overlay based on the simple-audio-card and the dmic + codec. It has the speciality that it is configured to use the codec + as a master I2S device. It works for example with the Si468x DAB + receiver on the uGreen DABBoard. +Load: dtoverlay=ugreen-dabboard,<param>=<val> +Params: card-name Override the default, "dabboard", card name. + + +Name: upstream +Info: Allow usage of downstream .dtb with upstream kernel. Comprises the + vc4-kms-v3d and dwc2 overlays. +Load: dtoverlay=upstream +Params: <None> + + +Name: upstream-aux-interrupt +Info: This overlay has been deprecated and removed because it is no longer + necessary. +Load: <Deprecated> + + +Name: upstream-pi4 +Info: Allow usage of downstream .dtb with upstream kernel on Pi 4. Comprises + the vc4-kms-v3d-pi4 and dwc2 overlays. +Load: dtoverlay=upstream-pi4 +Params: <None> + + +Name: vc4-fkms-v3d +Info: Enable Eric Anholt's DRM VC4 V3D driver on top of the dispmanx + display stack. +Load: dtoverlay=vc4-fkms-v3d,<param> +Params: cma-512 CMA is 512MB (needs 1GB) + cma-448 CMA is 448MB (needs 1GB) + cma-384 CMA is 384MB (needs 1GB) + cma-320 CMA is 320MB (needs 1GB) + cma-256 CMA is 256MB (needs 1GB) + cma-192 CMA is 192MB (needs 1GB) + cma-128 CMA is 128MB + cma-96 CMA is 96MB + cma-64 CMA is 64MB + cma-size CMA size in bytes, 4MB aligned + cma-default Use upstream's default value + + +Name: vc4-fkms-v3d-pi4 +Info: Enable Eric Anholt's DRM VC4 V3D driver on top of the dispmanx + display stack. +Load: dtoverlay=vc4-fkms-v3d-pi4,<param> +Params: cma-512 CMA is 512MB (needs 1GB) + cma-448 CMA is 448MB (needs 1GB) + cma-384 CMA is 384MB (needs 1GB) + cma-320 CMA is 320MB (needs 1GB) + cma-256 CMA is 256MB (needs 1GB) + cma-192 CMA is 192MB (needs 1GB) + cma-128 CMA is 128MB + cma-96 CMA is 96MB + cma-64 CMA is 64MB + cma-size CMA size in bytes, 4MB aligned + cma-default Use upstream's default value + + +Name: vc4-kms-dpi-at056tn53v1 +Info: This overlay is now deprecated - see vc4-kms-dpi-panel,at056tn53v1 +Load: <Deprecated> + + +Name: vc4-kms-dpi-generic +Info: Enable a generic DPI display under KMS. Default timings are for the + Adafruit Kippah with 800x480 panel and RGB666 (GPIOs 0-21) + Requires vc4-kms-v3d to be loaded. +Load: dtoverlay=vc4-kms-dpi-generic,<param>=<val> +Params: clock-frequency Display clock frequency (Hz) + hactive Horizontal active pixels + hfp Horizontal front porch + hsync Horizontal sync pulse width + hbp Horizontal back porch + vactive Vertical active lines + vfp Vertical front porch + vsync Vertical sync pulse width + vbp Vertical back porch + hsync-invert Horizontal sync active low + vsync-invert Vertical sync active low + de-invert Data Enable active low + pixclk-invert Negative edge pixel clock + width-mm Define the screen width in mm + height-mm Define the screen height in mm + rgb565 Change to RGB565 output on GPIOs 0-19 + rgb565-padhi Change to RGB565 output on GPIOs 0-8, 12-17, and + 20-24 + bgr666 Change to BGR666 output on GPIOs 0-21. + bgr666-padhi Change to BGR666 output on GPIOs 0-9, 12-17, and + 20-25 + rgb666-padhi Change to RGB666 output on GPIOs 0-9, 12-17, and + 20-25 + bgr888 Change to BGR888 output on GPIOs 0-27 + rgb888 Change to RGB888 output on GPIOs 0-27 + bus-format Override the bus format for a MEDIA_BUS_FMT_* + value. NB also overridden by rgbXXX overrides. + backlight-gpio Defines a GPIO to be used for backlight control + (default of none). + backlight-pwm Defines a PWM channel to be used for backlight + control (default of none). NB Disables audio + headphone output as that also uses PWM. + backlight-pwm-chan Choose channel on &pwm node for backlight + control. + (default 0). + backlight-pwm-gpio GPIO pin to be used for the PWM backlight. See + pwm-2chan for valid options. + (default 18 - note this can only work with + rgb666-padhi). + backlight-pwm-func Pin function of GPIO used for the PWM + backlight. + See pwm-2chan for valid options. + (default 2). + backlight-def-brightness + Set the default brightness. Normal range 1-16. + (default 16). + rotate Display rotation {0,90,180,270} (default 0) + + +Name: vc4-kms-dpi-hyperpixel2r +Info: Enable the KMS drivers for the Pimoroni HyperPixel2 Round DPI display. + Requires vc4-kms-v3d to be loaded. +Load: dtoverlay=vc4-kms-dpi-hyperpixel2r,<param>=<val> +Params: disable-touch Disables the touch controller + touchscreen-inverted-x Inverts X direction of touch controller + touchscreen-inverted-y Inverts Y direction of touch controller + touchscreen-swapped-x-y Swaps X & Y axes of touch controller + rotate Display rotation {0,90,180,270} (default 0) + + +Name: vc4-kms-dpi-hyperpixel4 +Info: Enable the KMS drivers for the Pimoroni HyperPixel4 DPI display. + Requires vc4-kms-v3d to be loaded. +Load: dtoverlay=vc4-kms-dpi-hyperpixel4,<param>=<val> +Params: disable-touch Disables the touch controller + touchscreen-inverted-x Inverts X direction of touch controller + touchscreen-inverted-y Inverts Y direction of touch controller + touchscreen-swapped-x-y Swaps X & Y axes of touch controller + rotate Display rotation {0,90,180,270} (default 0) + + +Name: vc4-kms-dpi-hyperpixel4sq +Info: Enable the KMS drivers for the Pimoroni HyperPixel4 Square DPI display. + Requires vc4-kms-v3d to be loaded. +Load: dtoverlay=vc4-kms-dpi-hyperpixel4sq,<param>=<val> +Params: disable-touch Disables the touch controller + touchscreen-inverted-x Inverts X direction of touch controller + touchscreen-inverted-y Inverts Y direction of touch controller + touchscreen-swapped-x-y Swaps X & Y axes of touch controller + rotate Display rotation {0,90,180,270} (default 0) + + +Name: vc4-kms-dpi-panel +Info: Enable a preconfigured KMS DPI panel. + Requires vc4-kms-v3d to be loaded. +Load: dtoverlay=vc4-kms-dpi-panel,<param>=<val> +Params: at056tn53v1 Enable an Innolux 5.6in VGA TFT + kippah-7inch Enable an Adafruit Kippah with 7inch panel. + mzp280 Enable a Geekworm MZP280 panel. + backlight-gpio Defines a GPIO to be used for backlight control + (default of none). + backlight-pwm Defines a PWM channel to be used for backlight + control (default of none). NB Disables audio + headphone output as that also uses PWM. + backlight-pwm-chan Choose channel on &pwm node for backlight + control. + (default 0). + backlight-pwm-gpio GPIO pin to be used for the PWM backlight. See + pwm-2chan for valid options. + (default 18 - note this can only work with + rgb666-padhi). + backlight-pwm-func Pin function of GPIO used for the PWM + backlight. + See pwm-2chan for valid options. + (default 2). + backlight-def-brightness + Set the default brightness. Normal range 1-16. + (default 16). + rotate Display rotation {0,90,180,270} (default 0) + + +Name: vc4-kms-dsi-7inch +Info: Enable the Raspberry Pi DSI 7" screen. + Includes the edt-ft5406 for the touchscreen element. + Requires vc4-kms-v3d to be loaded. +Load: dtoverlay=vc4-kms-dsi-7inch,<param>=<val> +Params: sizex Touchscreen size x (default 800) + sizey Touchscreen size y (default 480) + invx Touchscreen inverted x axis + invy Touchscreen inverted y axis + swapxy Touchscreen swapped x y axis + disable_touch Disables the touch screen overlay driver + dsi0 Use DSI0 and i2c_csi_dsi0 (rather than + the default DSI1 and i2c_csi_dsi). + + +Name: vc4-kms-dsi-generic +Info: Enable a generic DSI display under KMS. + Default timings are for a 840x480 RGB888 panel. + Requires vc4-kms-v3d to be loaded. +Load: dtoverlay=vc4-kms-dsi-generic,<param>=<val> +Params: clock-frequency Display clock frequency (Hz) + hactive Horizontal active pixels + hfp Horizontal front porch + hsync Horizontal sync pulse width + hbp Horizontal back porch + vactive Vertical active lines + vfp Vertical front porch + vsync Vertical sync pulse width + vbp Vertical back porch + width-mm Define the screen width in mm + height-mm Define the screen height in mm + rgb565 Change to RGB565 output + rgb666 Change to RGB666 output + rgb666p Change to RGB666 output with pixel packing + rgb888 Change to RGB888 output, this is the default + one-lane Use one DSI lane for data transmission + This is the default + two-lane Use two DSI lanes for data transmission + three-lane Use three DSI lanes for data transmission + Only supported on Pi5 and CM + four-lane Use four DSI lanes for data transmission + Only supported on Pi5 and CM + dsi0 Switch DSI port to DSI0 + Only supported on Pi5 and CM + + +Name: vc4-kms-dsi-lt070me05000 +Info: Enable a JDI LT070ME05000 DSI display on DSI1. + Note that this is a 4 lane DSI device, so it will only work on a Compute + Module. + Requires vc4-kms-v3d to be loaded. +Load: dtoverlay=vc4-kms-dsi-lt070me05000,<param> +Params: reset GPIO for the reset signal (default 17) + enable GPIO for the enable signal (default 4) + dcdc-en GPIO for the DC-DC converter enable (default 5) + + +Name: vc4-kms-dsi-lt070me05000-v2 +Info: Enable a JDI LT070ME05000 DSI display on DSI1 using Harlab's V2 + interface board. + Note that this is a 4 lane DSI device, so it will only work on a Compute + Module. + Requires vc4-kms-v3d to be loaded. +Load: dtoverlay=vc4-kms-dsi-lt070me05000-v2 +Params: <None> + + +Name: vc4-kms-dsi-waveshare-panel +Info: Enable a Waveshare DSI touchscreen + Includes the Goodix driver for the touchscreen element. + The default is for the display to be using the I2C0 option for control. + Use the i2c1 override if using the I2C1 wiring with jumper wires from + GPIOs 2&3 (pins 3&5). + invx/invy/swapxy should be used with caution as the panel specifier will + set the default inversions for that panel. Always use them after the + panel specifier, and be aware that you may need to set them as =0, not + just adding it. + Requires vc4-kms-v3d to be loaded. +Load: dtoverlay=vc4-kms-dsi-waveshare-panel,<param>=<val> +Params: 2_8_inch 2.8" 480x640 + 3_4_inch 3.4" 800x800 round + 4_0_inch 4.0" 480x800 + 7_0_inchC 7.0" C 1024x600 + 7_9_inch 7.9" 400x1280 + 8_0_inch 8.0" 1280x800 + 10_1_inch 10.1" 1280x800 + 11_9_inch 11.9" 320x1480 + i2c1 Use i2c-1 with jumper wires from GPIOs 2&3 + disable_touch Disable the touch controller + rotation Set the panel orientation property + invx Touchscreen inverted x axis + invy Touchscreen inverted y axis + swapxy Touchscreen swapped x y axis + dsi0 Use DSI0 and i2c_csi_dsi0 (rather than + the default DSI1 and i2c_csi_dsi). + + +Name: vc4-kms-kippah-7inch +Info: This overlay is now deprecated - see vc4-kms-dpi-panel,kippah-7inch +Load: <Deprecated> + + +Name: vc4-kms-v3d +Info: Enable Eric Anholt's DRM VC4 HDMI/HVS/V3D driver. +Load: dtoverlay=vc4-kms-v3d,<param> +Params: cma-512 CMA is 512MB (needs 1GB) + cma-448 CMA is 448MB (needs 1GB) + cma-384 CMA is 384MB (needs 1GB) + cma-320 CMA is 320MB (needs 1GB) + cma-256 CMA is 256MB (needs 1GB) + cma-192 CMA is 192MB (needs 1GB) + cma-128 CMA is 128MB + cma-96 CMA is 96MB + cma-64 CMA is 64MB + cma-size CMA size in bytes, 4MB aligned + cma-default Use upstream's default value + audio Enable or disable audio over HDMI (default "on") + noaudio Disable all HDMI audio (default "off") + composite Enable the composite output (default "off") + N.B. Disables all other outputs on a Pi 4. + nohdmi Disable HDMI output + + +Name: vc4-kms-v3d-pi4 +Info: Enable Eric Anholt's DRM VC4 HDMI/HVS/V3D driver for Pi4. +Load: dtoverlay=vc4-kms-v3d-pi4,<param> +Params: cma-512 CMA is 512MB + cma-448 CMA is 448MB + cma-384 CMA is 384MB + cma-320 CMA is 320MB + cma-256 CMA is 256MB + cma-192 CMA is 192MB + cma-128 CMA is 128MB + cma-96 CMA is 96MB + cma-64 CMA is 64MB + cma-size CMA size in bytes, 4MB aligned + cma-default Use upstream's default value + audio Enable or disable audio over HDMI0 (default + "on") + audio1 Enable or disable audio over HDMI1 (default + "on") + noaudio Disable all HDMI audio (default "off") + composite Enable the composite output (disables all other + outputs) + nohdmi Disable both HDMI 0 & 1 outputs + nohdmi0 Disable HDMI 0 output + nohdmi1 Disable HDMI 1 output + + +Name: vc4-kms-v3d-pi5 +Info: See vc4-kms-v3d-pi4 (this is the Pi 5 version) + + +Name: vc4-kms-vga666 +Info: Enable the VGA666 (resistor ladder ADC) for the vc4-kms-v3d driver. + Requires vc4-kms-v3d to be loaded. +Load: dtoverlay=vc4-kms-vga666,<param> +Params: ddc Enables GPIOs 0&1 as the I2C to read the EDID + from the display. NB These are NOT 5V tolerant + GPIOs, therefore level shifters are required. + + +Name: vga666 +Info: Overlay for the Fen Logic VGA666 board + This uses GPIOs 2-21 (so no I2C), and activates the output 2-3 seconds + after the kernel has started. + NOT for use with vc4-kms-v3d. +Load: dtoverlay=vga666 +Params: <None> + + +Name: vl805 +Info: Overlay to enable a VIA VL805 USB3 controller on CM4 carriers + Will be loaded automatically by up-to-date firmware if "VL805=1" is + set in the EEPROM config. +Load: dtoverlay=vl805 +Params: <None> + + +Name: w1-gpio +Info: Configures the w1-gpio Onewire interface module. + Use this overlay if you *don't* need a GPIO to drive an external pullup. +Load: dtoverlay=w1-gpio,<param>=<val> +Params: gpiopin GPIO for I/O (default "4") + pullup Now enabled by default (ignored) + + +Name: w1-gpio-pullup +Info: Configures the w1-gpio Onewire interface module. + Use this overlay if you *do* need a GPIO to drive an external pullup. +Load: dtoverlay=w1-gpio-pullup,<param>=<val> +Params: gpiopin GPIO for I/O (default "4") + extpullup GPIO for external pullup (default "5") + pullup Now enabled by default (ignored) + + +Name: w5500 +Info: Overlay for the Wiznet W5500 Ethernet Controller on SPI0 +Load: dtoverlay=w5500,<param>=<val> +Params: int_pin GPIO used for INT (default 25) + + speed SPI bus speed (default 30000000) + + cs SPI bus Chip Select (default 0) + + +Name: watterott-display +Info: Watterott RPi-Display - 2.8" Touch Display + Linux has 2 drivers that support this display and this overlay supports + both. + + Examples: + fbtft/fb_ili9341: dtoverlay=watterott-display + drm/mi0283qt: dtoverlay=watterott-display,drm,backlight-pwm,rotate=180 + + Some notable differences with the DRM driver compared to fbtft: + - The display is turned on when it's first used and not on driver load + as with fbtft. So if nothing uses the display it stays off. + - Can run with a higher SPI clock increasing framerate. This is possible + since the driver avoids messing up the controller configuration due to + transmission errors by running config commands at 10MHz and only pixel + data at full speed (occasional pixel glitch might occur). + - PWM backlight is supported. + +Load: dtoverlay=watterott-display,<param>=<val> +Params: speed Display SPI bus speed + rotate Display rotation {0,90,180,270} + fps Delay between frame updates (fbtft only) + debug Debug output level {0-7} (fbtft only) + xohms Touchpanel sensitivity (X-plate resistance) + swapxy Swap x and y axis + backlight Change backlight GPIO pin {e.g. 12, 18} + (fbtft only) + drm Use DRM/KMS driver mi0283qt instead of fbtft. + Set the SPI clock to 70MHz. + This has to be the first parameter. + backlight-pwm Use pwm for backlight (drm only). NB: Disables + audio headphone output as that also uses PWM. + + +Name: waveshare-can-fd-hat-mode-a +Info: Overlay for the Waveshare 2-Channel Isolated CAN FD Expansion HAT + for Raspberry Pi, Multi Protections. Use this overlay when the + HAT is configured in Mode A (Default), with can0 on spi0.0 + and can1 on spi1.0. + https://www.waveshare.com/2-ch-can-fd-hat.htm +Load: dtoverlay=waveshare-can-fd-hat-mode-a +Params: <None> + + +Name: waveshare-can-fd-hat-mode-b +Info: Overlay for the Waveshare 2-Channel Isolated CAN FD Expansion HAT + for Raspberry Pi, Multi Protections. Use this overlay when the + HAT is configured in Mode B (requires hardware modification), with + can0 on spi0.0 and can1 on spi0.1. + https://www.waveshare.com/2-ch-can-fd-hat.htm +Load: dtoverlay=waveshare-can-fd-hat-mode-b +Params: <None> + + +Name: wittypi +Info: Configures the wittypi RTC module. +Load: dtoverlay=wittypi,<param>=<val> +Params: led_gpio GPIO for LED (default "17") + led_trigger Choose which activity the LED tracks (default + "default-on") + + +Name: wm8960-soundcard +Info: Overlay for the Waveshare wm8960 soundcard +Load: dtoverlay=wm8960-soundcard,<param>=<val> +Params: alsaname Changes the card name in ALSA + compatible Changes the codec compatibility + + +Troubleshooting +=============== + +If you are experiencing problems that you think are DT-related, enable DT +diagnostic output by adding this to /boot/config.txt: + + dtdebug=on + +and rebooting. Then run: + + sudo vcdbg log msg + +and look for relevant messages. + +Further reading +=============== + +This is only meant to be a quick introduction to the subject of Device Tree on +Raspberry Pi. There is a more complete explanation here: + +http://www.raspberrypi.org/documentation/configuration/device-tree.md diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts linux/arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts 2023-12-13 11:50:48.619961320 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Device tree overlay for GPIO connected rotary encoder. +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + rotary_pins: rotary_pins@4 { + brcm,pins = <4 17>; /* gpio 4 17 */ + brcm,function = <0 0>; /* input */ + brcm,pull = <2 2>; /* pull-up */ + }; + + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + rotary: rotary@4 { + compatible = "rotary-encoder"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rotary_pins>; + gpios = <&gpio 4 0>, <&gpio 17 0>; + linux,axis = <0>; /* REL_X */ + rotary-encoder,encoding = "gray"; + rotary-encoder,steps = <24>; /* 24 default */ + rotary-encoder,steps-per-period = <1>; /* corresponds to full period mode. See README */ + }; + }; + + }; + + __overrides__ { + pin_a = <&rotary>,"gpios:4", + <&rotary_pins>,"brcm,pins:0", + /* modify reg values to allow multiple instantiation */ + <&rotary>,"reg:0", + <&rotary_pins>,"reg:0"; + pin_b = <&rotary>,"gpios:16", + <&rotary_pins>,"brcm,pins:4"; + relative_axis = <&rotary>,"rotary-encoder,relative-axis?"; + linux_axis = <&rotary>,"linux,axis:0"; + rollover = <&rotary>,"rotary-encoder,rollover?"; + steps-per-period = <&rotary>,"rotary-encoder,steps-per-period:0"; + steps = <&rotary>,"rotary-encoder,steps:0"; + wakeup = <&rotary>,"wakeup-source?"; + encoding = <&rotary>,"rotary-encoder,encoding"; + /* legacy parameters*/ + rotary0_pin_a = <&rotary>,"gpios:4", + <&rotary_pins>,"brcm,pins:0"; + rotary0_pin_b = <&rotary>,"gpios:16", + <&rotary_pins>,"brcm,pins:4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts linux/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts 2023-12-13 11:50:48.619961320 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Devicetree overlay for mailbox-driven Raspberry Pi DSI Display + * backlight controller + */ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + rpi_backlight: rpi_backlight { + compatible = "raspberrypi,rpi-backlight"; + firmware = <&firmware>; + status = "okay"; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/rpi-codeczero-overlay.dts linux/arch/arm/boot/dts/overlays/rpi-codeczero-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/rpi-codeczero-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/rpi-codeczero-overlay.dts 2023-12-13 11:50:48.619961320 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for the Raspberry Pi Codec Zero soundcard + +#include "iqaudio-codec-overlay.dts" + +&iqaudio_dac { + card_name = "RPi Codec Zero"; + dai_name = "Raspberry Pi Codec Zero"; + dai_stream_name = "Raspberry Pi Codec Zero HiFi"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/rpi-dacplus-overlay.dts linux/arch/arm/boot/dts/overlays/rpi-dacplus-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/rpi-dacplus-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/rpi-dacplus-overlay.dts 2023-12-13 11:50:48.619961320 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for the Raspberry Pi DAC Plus soundcard + +#include "iqaudio-dacplus-overlay.dts" + +&iqaudio_dac { + card_name = "RPi DAC+"; + dai_name = "Raspberry Pi DAC+"; + dai_stream_name = "Raspberry Pi DAC+ HiFi"; + /delete-property/ mute-gpios; +}; + +/ { + __overrides__ { + /delete-property/ auto_mute_amp; + /delete-property/ unmute_amp; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/rpi-dacpro-overlay.dts linux/arch/arm/boot/dts/overlays/rpi-dacpro-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/rpi-dacpro-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/rpi-dacpro-overlay.dts 2023-12-13 11:50:48.619961320 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for the Raspberry Pi DAC Pro soundcard + +#include "iqaudio-dacplus-overlay.dts" + +&iqaudio_dac { + card_name = "RPi DAC Pro"; + dai_name = "Raspberry Pi DAC Pro"; + dai_stream_name = "Raspberry Pi DAC Pro HiFi"; + /delete-property/ mute-gpios; +}; + +/ { + __overrides__ { + /delete-property/ auto_mute_amp; + /delete-property/ unmute_amp; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/rpi-digiampplus-overlay.dts linux/arch/arm/boot/dts/overlays/rpi-digiampplus-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/rpi-digiampplus-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/rpi-digiampplus-overlay.dts 2023-12-13 11:50:48.620961322 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for the Raspberry Pi DAC Plus soundcard + +#include "iqaudio-dacplus-overlay.dts" + +&iqaudio_dac { + card_name = "RPi DigiAMP+"; + dai_name = "Raspberry Pi DigiAMP+"; + dai_stream_name = "Raspberry Pi DigiAMP+ HiFi"; + iqaudio-dac,auto-mute-amp; +}; + +/ { + __overrides__ { + unmute_amp = <&iqaudio_dac>,"iqaudio-dac,unmute-amp?", + <&iqaudio_dac>,"iqaudio-dac,auto-mute-amp!"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts linux/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts 2023-12-13 11:50:48.620961322 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/soc/firmware"; + __overlay__ { + ts: touchscreen { + compatible = "raspberrypi,firmware-ts"; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; + }; + }; + + __overrides__ { + touchscreen-size-x = <&ts>,"touchscreen-size-x:0"; + touchscreen-size-y = <&ts>,"touchscreen-size-y:0"; + touchscreen-inverted-x = <&ts>,"touchscreen-inverted-x?"; + touchscreen-inverted-y = <&ts>,"touchscreen-inverted-y?"; + touchscreen-swapped-x-y = <&ts>,"touchscreen-swapped-x-y?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts linux/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts 2023-12-13 11:50:48.620961322 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Overlay for the Raspberry Pi POE HAT. + */ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 1 10 100 255>; + #cooling-cells = <2>; + pwms = <&fwpwm 0 80000>; + }; + }; + }; + + fragment@1 { + target = <&cpu_thermal>; + __overlay__ { + polling-delay = <2000>; /* milliseconds */ + }; + }; + + fragment@2 { + target = <&thermal_trips>; + __overlay__ { + trip0: trip0 { + temperature = <40000>; + hysteresis = <2000>; + type = "active"; + }; + trip1: trip1 { + temperature = <45000>; + hysteresis = <2000>; + type = "active"; + }; + trip2: trip2 { + temperature = <50000>; + hysteresis = <2000>; + type = "active"; + }; + trip3: trip3 { + temperature = <55000>; + hysteresis = <5000>; + type = "active"; + }; + }; + }; + + fragment@3 { + target = <&cooling_maps>; + __overlay__ { + map0 { + trip = <&trip0>; + cooling-device = <&fan 0 1>; + }; + map1 { + trip = <&trip1>; + cooling-device = <&fan 1 2>; + }; + map2 { + trip = <&trip2>; + cooling-device = <&fan 2 3>; + }; + map3 { + trip = <&trip3>; + cooling-device = <&fan 3 4>; + }; + }; + }; + + fragment@4 { + target-path = "/__overrides__"; + params: __overlay__ { + poe_fan_temp0 = <&trip0>,"temperature:0"; + poe_fan_temp0_hyst = <&trip0>,"hysteresis:0"; + poe_fan_temp1 = <&trip1>,"temperature:0"; + poe_fan_temp1_hyst = <&trip1>,"hysteresis:0"; + poe_fan_temp2 = <&trip2>,"temperature:0"; + poe_fan_temp2_hyst = <&trip2>,"hysteresis:0"; + poe_fan_temp3 = <&trip3>,"temperature:0"; + poe_fan_temp3_hyst = <&trip3>,"hysteresis:0"; + poe_fan_i2c = <&fwpwm>,"status=disabled", + <&poe_mfd>,"status=okay", + <&fan>,"pwms:0=",<&poe_mfd_pwm>; + }; + }; + + fragment@5 { + target = <&firmware>; + __overlay__ { + fwpwm: pwm { + compatible = "raspberrypi,firmware-poe-pwm"; + #pwm-cells = <2>; + }; + }; + }; + + fragment@6 { + target = <&i2c0>; + i2c_bus: __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + poe_mfd: poe@51 { + compatible = "raspberrypi,poe-core"; + reg = <0x51>; + status = "disabled"; + + poe_mfd_pwm: poe_pwm@f0 { + compatible = "raspberrypi,poe-pwm"; + reg = <0xf0>; + status = "okay"; + #pwm-cells = <2>; + }; + }; + }; + }; + + fragment@7 { + target = <&i2c0if>; + __dormant__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&i2c0mux>; + __dormant__ { + status = "okay"; + }; + }; + + __overrides__ { + poe_fan_temp0 = <&trip0>,"temperature:0"; + poe_fan_temp0_hyst = <&trip0>,"hysteresis:0"; + poe_fan_temp1 = <&trip1>,"temperature:0"; + poe_fan_temp1_hyst = <&trip1>,"hysteresis:0"; + poe_fan_temp2 = <&trip2>,"temperature:0"; + poe_fan_temp2_hyst = <&trip2>,"hysteresis:0"; + poe_fan_temp3 = <&trip3>,"temperature:0"; + poe_fan_temp3_hyst = <&trip3>,"hysteresis:0"; + i2c = <0>, "+5+6", + <&fwpwm>,"status=disabled", + <&i2c_bus>,"status=okay", + <&poe_mfd>,"status=okay", + <&fan>,"pwms:0=",<&poe_mfd_pwm>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts linux/arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts 2023-12-13 11:50:48.620961322 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Overlay for the Raspberry Pi PoE+ HAT. + +#include "rpi-poe-overlay.dts" + +/ { + compatible = "brcm,bcm2835"; + + fragment@10 { + target-path = "/"; + __overlay__ { + rpi_poe_power_supply: rpi-poe-power-supply { + compatible = "raspberrypi,rpi-poe-power-supply"; + firmware = <&firmware>; + status = "okay"; + }; + }; + }; + fragment@11 { + target = <&poe_mfd>; + __overlay__ { + rpi-poe-power-supply@f2 { + compatible = "raspberrypi,rpi-poe-power-supply"; + reg = <0xf2>; + status = "okay"; + }; + }; + }; + + __overrides__ { + i2c = <0>, "+5+6", + <&fwpwm>,"status=disabled", + <&rpi_poe_power_supply>,"status=disabled", + <&i2c_bus>,"status=okay", + <&poe_mfd>,"status=okay", + <&fan>,"pwms:0=",<&poe_mfd_pwm>; + }; +}; + +&fan { + cooling-levels = <0 32 64 128 255>; +}; + +¶ms { + poe_fan_i2c = <&fwpwm>,"status=disabled", + <&rpi_poe_power_supply>,"status=disabled", + <&poe_mfd>,"status=okay", + <&fan>,"pwms:0=",<&poe_mfd_pwm>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts linux/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts 2023-12-13 11:50:48.620961322 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// rpi-sense HAT +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + rpi-sense@46 { + compatible = "rpi,rpi-sense"; + reg = <0x46>; + keys-int-gpios = <&gpio 23 1>; + status = "okay"; + }; + + lsm9ds1-magn@1c { + compatible = "st,lsm9ds1-magn"; + reg = <0x1c>; + status = "okay"; + }; + + lsm9ds1-accel6a { + compatible = "st,lsm9ds1-accel"; + reg = <0x6a>; + status = "okay"; + }; + + lps25h-press@5c { + compatible = "st,lps25h-press"; + reg = <0x5c>; + status = "okay"; + }; + + hts221-humid@5f { + compatible = "st,hts221-humid", "st,hts221"; + reg = <0x5f>; + status = "okay"; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/rpi-sense-v2-overlay.dts linux/arch/arm/boot/dts/overlays/rpi-sense-v2-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/rpi-sense-v2-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/rpi-sense-v2-overlay.dts 2023-12-13 11:50:48.620961322 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// rpi-sense HAT +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + rpi-sense@46 { + compatible = "rpi,rpi-sense"; + reg = <0x46>; + keys-int-gpios = <&gpio 23 1>; + status = "okay"; + }; + + lsm9ds1-magn@1c { + compatible = "st,lsm9ds1-magn"; + reg = <0x1c>; + status = "okay"; + }; + + lps25h-press@5c { + compatible = "st,lps25h-press"; + reg = <0x5c>; + status = "okay"; + }; + + hts221-humid@5f { + compatible = "st,hts221-humid", "st,hts221"; + reg = <0x5f>; + status = "okay"; + }; + + lsm9ds1-accel@6a { + compatible = "st,lsm9ds1-accel"; + reg = <0x6a>; + status = "okay"; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/rpi-tv-overlay.dts linux/arch/arm/boot/dts/overlays/rpi-tv-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/rpi-tv-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/rpi-tv-overlay.dts 2023-12-13 11:50:48.621961325 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// rpi-tv HAT + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + cxd2880@0 { + compatible = "sony,cxd2880"; + reg = <0>; /* CE0 */ + spi-max-frequency = <50000000>; + status = "okay"; + }; + }; + }; + +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/rra-digidac1-wm8741-audio-overlay.dts linux/arch/arm/boot/dts/overlays/rra-digidac1-wm8741-audio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/rra-digidac1-wm8741-audio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/rra-digidac1-wm8741-audio-overlay.dts 2023-12-13 11:50:48.621961325 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for RRA DigiDAC1 Audio card +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wm8804@3b { + #sound-dai-cells = <0>; + compatible = "wlf,wm8804"; + reg = <0x3b>; + status = "okay"; + PVDD-supply = <&vdd_3v3_reg>; + DVDD-supply = <&vdd_3v3_reg>; + }; + + wm8742: wm8741@1a { + compatible = "wlf,wm8741"; + reg = <0x1a>; + status = "okay"; + AVDD-supply = <&vdd_5v0_reg>; + DVDD-supply = <&vdd_3v3_reg>; + }; + }; + }; + + fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "rra,digidac1-soundcard"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/sainsmart18-overlay.dts linux/arch/arm/boot/dts/overlays/sainsmart18-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/sainsmart18-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/sainsmart18-overlay.dts 2023-12-13 11:50:48.621961325 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for the Sainsmart 1.8" TFT LCD with ST7735R chip 160x128 + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ss18: sainsmart18@0 { + compatible = "fbtft,sainsmart18"; + reg = <0>; + pinctrl-names = "default"; + spi-max-frequency = <40000000>; + rotate = <90>; + buswidth = <8>; + fps = <50>; + height = <160>; + width = <128>; + reset-gpios = <&gpio 25 1>; + dc-gpios = <&gpio 24 0>; + debug = <0>; + }; + }; + }; + + __overrides__ { + speed = <&ss18>,"spi-max-frequency:0"; + rotate = <&ss18>,"rotate:0"; + fps = <&ss18>,"fps:0"; + bgr = <&ss18>,"bgr?"; + debug = <&ss18>,"debug:0"; + dc_pin = <&ss18>,"dc-gpios:4"; + reset_pin = <&ss18>,"reset-gpios:4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/sc16is750-i2c-overlay.dts linux/arch/arm/boot/dts/overlays/sc16is750-i2c-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/sc16is750-i2c-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/sc16is750-i2c-overlay.dts 2023-12-13 11:50:48.621961325 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c_arm>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + sc16is750: sc16is750@48 { + compatible = "nxp,sc16is750"; + reg = <0x48>; /* i2c address */ + clocks = <&sc16is750_clk>; + interrupt-parent = <&gpio>; + interrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */ + gpio-controller; + #gpio-cells = <2>; + i2c-max-frequency = <400000>; + }; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + sc16is750_clk: sc16is750_i2c_clk@48 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <14745600>; + }; + }; + }; + + __overrides__ { + int_pin = <&sc16is750>,"interrupts:0"; + addr = <&sc16is750>,"reg:0", <&sc16is750_clk>,"name"; + xtal = <&sc16is750_clk>,"clock-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/sc16is752-i2c-overlay.dts linux/arch/arm/boot/dts/overlays/sc16is752-i2c-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/sc16is752-i2c-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/sc16is752-i2c-overlay.dts 2023-12-13 11:50:48.621961325 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c_arm>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + sc16is752: sc16is752@48 { + compatible = "nxp,sc16is752"; + reg = <0x48>; /* i2c address */ + clocks = <&sc16is752_clk>; + interrupt-parent = <&gpio>; + interrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */ + gpio-controller; + #gpio-cells = <2>; + i2c-max-frequency = <400000>; + }; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + sc16is752_clk: sc16is752_i2c_clk@48 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <14745600>; + }; + }; + }; + + __overrides__ { + int_pin = <&sc16is752>,"interrupts:0"; + addr = <&sc16is752>,"reg:0",<&sc16is752_clk>,"name"; + xtal = <&sc16is752_clk>,"clock-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts linux/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts 2023-12-13 11:50:48.621961325 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + sc16is752: sc16is752@0 { + compatible = "nxp,sc16is752"; + reg = <0>; /* CE0 */ + clocks = <&sc16is752_clk>; + interrupt-parent = <&gpio>; + interrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */ + gpio-controller; + #gpio-cells = <2>; + spi-max-frequency = <4000000>; + }; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target-path = "/"; + __overlay__ { + sc16is752_clk: sc16is752_spi0_0_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <14745600>; + }; + }; + }; + + __overrides__ { + int_pin = <&sc16is752>,"interrupts:0"; + xtal = <&sc16is752_clk>,"clock-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts linux/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts 2023-12-13 11:50:48.621961325 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + spi1_pins: spi1_pins { + brcm,pins = <19 20 21>; + brcm,function = <3>; /* alt4 */ + }; + + spi1_cs_pins: spi1_cs_pins { + brcm,pins = <18>; + brcm,function = <1>; /* output */ + }; + }; + }; + + fragment@1 { + target = <&spi1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins &spi1_cs_pins>; + cs-gpios = <&gpio 18 1>; + status = "okay"; + + sc16is752: sc16is752@0 { + compatible = "nxp,sc16is752"; + reg = <0>; /* CE0 */ + clocks = <&sc16is752_clk>; + interrupt-parent = <&gpio>; + interrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */ + gpio-controller; + #gpio-cells = <2>; + spi-max-frequency = <4000000>; + }; + }; + }; + + fragment@2 { + target = <&aux>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target-path = "/"; + __overlay__ { + sc16is752_clk: sc16is752_spi1_0_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <14745600>; + }; + }; + }; + + __overrides__ { + int_pin = <&sc16is752>,"interrupts:0"; + xtal = <&sc16is752_clk>,"clock-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/sdhost-overlay.dts linux/arch/arm/boot/dts/overlays/sdhost-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/sdhost-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/sdhost-overlay.dts 2023-12-13 11:50:48.622961327 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/* Provide backwards compatible aliases for the old sdhost dtparams. */ + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&sdhost>; + frag0: __overlay__ { + brcm,overclock-50 = <0>; + brcm,pio-limit = <1>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&mmc>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&mmcnr>; + __overlay__ { + status = "disabled"; + }; + }; + + __overrides__ { + overclock_50 = <&frag0>,"brcm,overclock-50:0"; + force_pio = <&frag0>,"brcm,force-pio?"; + pio_limit = <&frag0>,"brcm,pio-limit:0"; + debug = <&frag0>,"brcm,debug?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/sdio-overlay.dts linux/arch/arm/boot/dts/overlays/sdio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/sdio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/sdio-overlay.dts 2023-12-13 11:50:48.622961327 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/* Enable SDIO from MMC interface via various GPIO groups */ + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&mmcnr>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&mmc>; + sdio_ovl: __overlay__ { + pinctrl-0 = <&sdio_ovl_pins>; + pinctrl-names = "default"; + non-removable; + bus-width = <4>; + status = "okay"; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + sdio_ovl_pins: sdio_ovl_pins { + brcm,pins = <22 23 24 25 26 27>; + brcm,function = <7>; /* ALT3 = SD1 */ + brcm,pull = <0 2 2 2 2 2>; + }; + }; + }; + + fragment@3 { + target = <&sdio_ovl_pins>; + __dormant__ { + brcm,pins = <22 23 24 25>; + brcm,pull = <0 2 2 2>; + }; + }; + + fragment@4 { + target = <&sdio_ovl_pins>; + __dormant__ { + brcm,pins = <34 35 36 37>; + brcm,pull = <0 2 2 2>; + }; + }; + + fragment@5 { + target = <&sdio_ovl_pins>; + __dormant__ { + brcm,pins = <34 35 36 37 38 39>; + brcm,pull = <0 2 2 2 2 2>; + }; + }; + + fragment@6 { + target-path = "/aliases"; + __overlay__ { + mmc1 = "/soc/mmc@7e300000"; + }; + }; + + __overrides__ { + poll_once = <&sdio_ovl>,"non-removable?"; + bus_width = <&sdio_ovl>,"bus-width:0"; + sdio_overclock = <&sdio_ovl>,"brcm,overclock-50:0"; + gpios_22_25 = <0>,"=3"; + gpios_34_37 = <0>,"=4"; + gpios_34_39 = <0>,"=5"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/sdio-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/sdio-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/sdio-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/sdio-pi5-overlay.dts 2023-12-13 11:50:48.622961327 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/* SDIO/SD/MMC on RP1 bank 0 */ + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&rp1_mmc0>; + frag0: __overlay__ { + status = "okay"; + pinctrl-0 = <&rp1_sdio0_22_27>; + pinctrl-names = "default"; + }; + }; + + fragment@1 { + target = <&rp1_sdio_clk0>; + frag1: __overlay__ { + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/seeed-can-fd-hat-v1-overlay.dts linux/arch/arm/boot/dts/overlays/seeed-can-fd-hat-v1-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/seeed-can-fd-hat-v1-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/seeed-can-fd-hat-v1-overlay.dts 2023-12-13 11:50:48.622961327 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// redo: ovmerge -c spi1-1cs-overlay.dts,cs0_pin=18,cs0_spidev=false mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi1-0,interrupt=24 + +// Device tree overlay for https://www.seeedstudio.com/2-Channel-CAN-BUS-FD-Shield-for-Raspberry-Pi-p-4072.html + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/bcm2835.h> + +/ { + compatible = "brcm,bcm2835"; + fragment@0 { + target = <&gpio>; + __overlay__ { + spi1_pins: spi1_pins { + brcm,pins = <19 20 21>; + brcm,function = <3>; + }; + spi1_cs_pins: spi1_cs_pins { + brcm,pins = <18>; + brcm,function = <1>; + }; + }; + }; + fragment@1 { + target = <&spi1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins &spi1_cs_pins>; + cs-gpios = <&gpio 18 1>; + status = "okay"; + spidev@0 { + compatible = "spidev"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "disabled"; + }; + }; + }; + fragment@2 { + target = <&aux>; + __overlay__ { + status = "okay"; + }; + }; + fragment@3 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + fragment@4 { + target = <&gpio>; + __overlay__ { + mcp251xfd_pins: mcp251xfd_spi0_0_pins { + brcm,pins = <25>; + brcm,function = <BCM2835_FSEL_GPIO_IN>; + }; + }; + }; + fragment@5 { + target-path = "/clocks"; + __overlay__ { + clk_mcp251xfd_osc: mcp251xfd-spi0-0-osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + }; + }; + fragment@6 { + target = <&spi0>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp251xfd@0 { + compatible = "microchip,mcp251xfd"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp251xfd_pins>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk_mcp251xfd_osc>; + }; + }; + }; + fragment@7 { + target-path = "spi1/spidev@0"; + __overlay__ { + status = "disabled"; + }; + }; + fragment@8 { + target = <&gpio>; + __overlay__ { + mcp251xfd_pins_1: mcp251xfd_spi1_0_pins { + brcm,pins = <24>; + brcm,function = <BCM2835_FSEL_GPIO_IN>; + }; + }; + }; + fragment@9 { + target-path = "/clocks"; + __overlay__ { + clk_mcp251xfd_osc_1: mcp251xfd-spi1-0-osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + }; + }; + fragment@10 { + target = <&spi1>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp251xfd@0 { + compatible = "microchip,mcp251xfd"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp251xfd_pins_1>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk_mcp251xfd_osc_1>; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/seeed-can-fd-hat-v2-overlay.dts linux/arch/arm/boot/dts/overlays/seeed-can-fd-hat-v2-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/seeed-can-fd-hat-v2-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/seeed-can-fd-hat-v2-overlay.dts 2023-12-13 11:50:48.622961327 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// redo: ovmerge -c mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi0-1,interrupt=24 i2c-rtc-overlay.dts,pcf85063 + +// Device tree overlay for https://www.seeedstudio.com/CAN-BUS-FD-HAT-for-Raspberry-Pi-p-4742.html + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/bcm2835.h> + +/ { + compatible = "brcm,bcm2835"; + fragment@0 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + fragment@1 { + target = <&gpio>; + __overlay__ { + mcp251xfd_pins: mcp251xfd_spi0_0_pins { + brcm,pins = <25>; + brcm,function = <BCM2835_FSEL_GPIO_IN>; + }; + }; + }; + fragment@2 { + target-path = "/clocks"; + __overlay__ { + clk_mcp251xfd_osc: mcp251xfd-spi0-0-osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + }; + }; + fragment@3 { + target = <&spi0>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp251xfd@0 { + compatible = "microchip,mcp251xfd"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp251xfd_pins>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk_mcp251xfd_osc>; + }; + }; + }; + fragment@4 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + fragment@5 { + target = <&gpio>; + __overlay__ { + mcp251xfd_pins_1: mcp251xfd_spi0_1_pins { + brcm,pins = <24>; + brcm,function = <BCM2835_FSEL_GPIO_IN>; + }; + }; + }; + fragment@6 { + target-path = "/clocks"; + __overlay__ { + clk_mcp251xfd_osc_1: mcp251xfd-spi0-1-osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + }; + }; + fragment@7 { + target = <&spi0>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp251xfd@1 { + compatible = "microchip,mcp251xfd"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp251xfd_pins_1>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk_mcp251xfd_osc_1>; + }; + }; + }; + fragment@8 { + target = <&i2cbus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + pcf85063@51 { + compatible = "nxp,pcf85063"; + reg = <0x51>; + }; + }; + }; + fragment@9 { + target = <&i2c_arm>; + i2cbus: __overlay__ { + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/sh1106-spi-overlay.dts linux/arch/arm/boot/dts/overlays/sh1106-spi-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/sh1106-spi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/sh1106-spi-overlay.dts 2023-12-13 11:50:48.622961327 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for SH1106 based SPI OLED display + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + sh1106_pins: sh1106_pins { + brcm,pins = <25 24>; + brcm,function = <1 1>; /* out out */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + sh1106: sh1106@0{ + compatible = "sinowealth,sh1106"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&sh1106_pins>; + + spi-max-frequency = <4000000>; + bgr = <0>; + bpp = <1>; + rotate = <0>; + fps = <25>; + buswidth = <8>; + reset-gpios = <&gpio 25 1>; + dc-gpios = <&gpio 24 0>; + debug = <0>; + + sinowealth,height = <64>; + sinowealth,width = <128>; + sinowealth,page-offset = <0>; + }; + }; + }; + + __overrides__ { + speed = <&sh1106>,"spi-max-frequency:0"; + rotate = <&sh1106>,"rotate:0"; + fps = <&sh1106>,"fps:0"; + debug = <&sh1106>,"debug:0"; + dc_pin = <&sh1106>,"dc-gpios:4", + <&sh1106_pins>,"brcm,pins:4"; + reset_pin = <&sh1106>,"reset-gpios:4", + <&sh1106_pins>,"brcm,pins:0"; + height = <&sh1106>,"sinowealth,height:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/si446x-spi0-overlay.dts linux/arch/arm/boot/dts/overlays/si446x-spi0-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/si446x-spi0-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/si446x-spi0-overlay.dts 2023-12-13 11:50:48.622961327 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for the SiLabs Si446X Controller - SPI0 +// Default Interrupt Pin: 17 +// Default SDN Pin: 27 +/dts-v1/; +/plugin/; + + / { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + // needed to avoid dtc warning + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + uhf0: si446x@0{ + compatible = "silabs,si446x"; + reg = <0>; // CE0 + pinctrl-names = "default"; + pinctrl-0 = <&uhf0_pins>; + interrupt-parent = <&gpio>; + interrupts = <17 0x2>; // falling edge + spi-max-frequency = <4000000>; + sdn_pin = <27>; + irq_pin = <17>; + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + uhf0_pins: uhf0_pins { + brcm,pins = <17 27>; + brcm,function = <0 1>; // in, out + brcm,pull = <2 0>; // high, none + }; + }; + }; + + __overrides__ { + int_pin = <&uhf0>, "interrupts:0", + <&uhf0>, "irq_pin:0", + <&uhf0_pins>, "brcm,pins:0"; + reset_pin = <&uhf0>, "sdn_pin:0", + <&uhf0_pins>, "brcm,pins:4"; + speed = <&uhf0>, "spi-max-frequency:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/smi-dev-overlay.dts linux/arch/arm/boot/dts/overlays/smi-dev-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/smi-dev-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/smi-dev-overlay.dts 2023-12-13 11:50:48.623961330 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Description: Overlay to enable character device interface for SMI. +// Author: Luke Wren <luke@raspberrypi.org> + +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&soc>; + __overlay__ { + smi_dev { + compatible = "brcm,bcm2835-smi-dev"; + smi_handle = <&smi>; + status = "okay"; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/smi-nand-overlay.dts linux/arch/arm/boot/dts/overlays/smi-nand-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/smi-nand-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/smi-nand-overlay.dts 2023-12-13 11:50:48.623961330 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Description: Overlay to enable NAND flash through +// the secondary memory interface +// Author: Luke Wren + +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&smi>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&smi_pins>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&soc>; + __overlay__ { + nand: flash@0 { + compatible = "brcm,bcm2835-smi-nand"; + smi_handle = <&smi>; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + partition@0 { + label = "stage2"; + // 128k + reg = <0 0x20000>; + read-only; + }; + partition@1 { + label = "firmware"; + // 16M + reg = <0x20000 0x1000000>; + read-only; + }; + partition@2 { + label = "root"; + // 2G (will need to use 64 bit for >=4G) + reg = <0x1020000 0x80000000>; + }; + }; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + smi_pins: smi_pins { + brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 + 12 13 14 15>; + /* Alt 1: SMI */ + brcm,function = <5 5 5 5 5 5 5 5 5 5 5 + 5 5 5 5 5>; + /* /CS, /WE and /OE are pulled high, as they are + generally active low signals */ + brcm,pull = <2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0>; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/smi-overlay.dts linux/arch/arm/boot/dts/overlays/smi-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/smi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/smi-overlay.dts 2023-12-13 11:50:48.623961330 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Description: Overlay to enable the secondary memory interface peripheral +// Author: Luke Wren + +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&smi>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&smi_pins>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + smi_pins: smi_pins { + /* Don't configure the top two address bits, as + these are already used as ID_SD and ID_SC */ + brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25>; + /* Alt 1: SMI */ + brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 + 5 5 5 5 5 5 5 5 5>; + /* /CS, /WE and /OE are pulled high, as they are + generally active low signals */ + brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0>; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi0-0cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi0-0cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi0-0cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi0-0cs-overlay.dts 2023-12-13 11:50:48.623961330 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0_cs_pins>; + frag0: __overlay__ { + brcm,pins; + }; + }; + + fragment@1 { + target = <&spi0>; + __overlay__ { + cs-gpios; + status = "okay"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&spi0_pins>; + __dormant__ { + brcm,pins = <10 11>; + }; + }; + + __overrides__ { + no_miso = <0>,"=3"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi0-1cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi0-1cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi0-1cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi0-1cs-overlay.dts 2023-12-13 11:50:48.624961332 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0_cs_pins>; + frag0: __overlay__ { + brcm,pins = <8>; + }; + }; + + fragment@1 { + target = <&spi0>; + frag1: __overlay__ { + cs-gpios = <&gpio 8 1>; + status = "okay"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&spi0_pins>; + __dormant__ { + brcm,pins = <10 11>; + }; + }; + + __overrides__ { + cs0_pin = <&frag0>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + no_miso = <0>,"=3"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi0-2cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi0-2cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi0-2cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi0-2cs-overlay.dts 2023-12-13 11:50:48.624961332 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0_cs_pins>; + frag0: __overlay__ { + brcm,pins = <8 7>; + }; + }; + + fragment@1 { + target = <&spi0>; + frag1: __overlay__ { + cs-gpios = <&gpio 8 1>, <&gpio 7 1>; + status = "okay"; + }; + }; + + fragment@2 { + target = <&spi0_pins>; + __dormant__ { + brcm,pins = <10 11>; + }; + }; + + __overrides__ { + cs0_pin = <&frag0>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + cs1_pin = <&frag0>,"brcm,pins:4", + <&frag1>,"cs-gpios:16"; + no_miso = <0>,"=2"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi1-1cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi1-1cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi1-1cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi1-1cs-overlay.dts 2023-12-13 11:50:48.624961332 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + spi1_pins: spi1_pins { + brcm,pins = <19 20 21>; + brcm,function = <3>; /* alt4 */ + }; + + spi1_cs_pins: spi1_cs_pins { + brcm,pins = <18>; + brcm,function = <1>; /* output */ + }; + }; + }; + + fragment@1 { + target = <&spi1>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins &spi1_cs_pins>; + cs-gpios = <&gpio 18 1>; + status = "okay"; + + spidev1_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&aux>; + __overlay__ { + status = "okay"; + }; + }; + + __overrides__ { + cs0_pin = <&spi1_cs_pins>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + cs0_spidev = <&spidev1_0>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi1-2cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi1-2cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi1-2cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi1-2cs-overlay.dts 2023-12-13 11:50:48.624961332 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + spi1_pins: spi1_pins { + brcm,pins = <19 20 21>; + brcm,function = <3>; /* alt4 */ + }; + + spi1_cs_pins: spi1_cs_pins { + brcm,pins = <18 17>; + brcm,function = <1>; /* output */ + }; + }; + }; + + fragment@1 { + target = <&spi1>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins &spi1_cs_pins>; + cs-gpios = <&gpio 18 1>, <&gpio 17 1>; + status = "okay"; + + spidev1_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + + spidev1_1: spidev@1 { + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&aux>; + __overlay__ { + status = "okay"; + }; + }; + + __overrides__ { + cs0_pin = <&spi1_cs_pins>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + cs1_pin = <&spi1_cs_pins>,"brcm,pins:4", + <&frag1>,"cs-gpios:16"; + cs0_spidev = <&spidev1_0>,"status"; + cs1_spidev = <&spidev1_1>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi1-3cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi1-3cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi1-3cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi1-3cs-overlay.dts 2023-12-13 11:50:48.624961332 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + spi1_pins: spi1_pins { + brcm,pins = <19 20 21>; + brcm,function = <3>; /* alt4 */ + }; + + spi1_cs_pins: spi1_cs_pins { + brcm,pins = <18 17 16>; + brcm,function = <1>; /* output */ + }; + }; + }; + + fragment@1 { + target = <&spi1>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins &spi1_cs_pins>; + cs-gpios = <&gpio 18 1>, <&gpio 17 1>, <&gpio 16 1>; + status = "okay"; + + spidev1_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + + spidev1_1: spidev@1 { + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + + spidev1_2: spidev@2 { + compatible = "spidev"; + reg = <2>; /* CE2 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&aux>; + __overlay__ { + status = "okay"; + }; + }; + + __overrides__ { + cs0_pin = <&spi1_cs_pins>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + cs1_pin = <&spi1_cs_pins>,"brcm,pins:4", + <&frag1>,"cs-gpios:16"; + cs2_pin = <&spi1_cs_pins>,"brcm,pins:8", + <&frag1>,"cs-gpios:28"; + cs0_spidev = <&spidev1_0>,"status"; + cs1_spidev = <&spidev1_1>,"status"; + cs2_spidev = <&spidev1_2>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi2-1cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi2-1cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi2-1cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi2-1cs-overlay.dts 2023-12-13 11:50:48.624961332 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + spi2_pins: spi2_pins { + brcm,pins = <40 41 42>; + brcm,function = <3>; /* alt4 */ + }; + + spi2_cs_pins: spi2_cs_pins { + brcm,pins = <43>; + brcm,function = <1>; /* output */ + }; + }; + }; + + fragment@1 { + target = <&spi2>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins &spi2_cs_pins>; + cs-gpios = <&gpio 43 1>; + status = "okay"; + + spidev2_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&aux>; + __overlay__ { + status = "okay"; + }; + }; + + __overrides__ { + cs0_pin = <&spi2_cs_pins>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + cs0_spidev = <&spidev2_0>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi2-1cs-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/spi2-1cs-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi2-1cs-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi2-1cs-pi5-overlay.dts 2023-12-13 11:50:48.624961332 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&spi2>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio 0 1>; + status = "okay"; + + spidev2_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + __overrides__ { + cs0_pin = <&frag1>,"cs-gpios:4"; + cs0_spidev = <&spidev2_0>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi2-2cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi2-2cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi2-2cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi2-2cs-overlay.dts 2023-12-13 11:50:48.624961332 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + spi2_pins: spi2_pins { + brcm,pins = <40 41 42>; + brcm,function = <3>; /* alt4 */ + }; + + spi2_cs_pins: spi2_cs_pins { + brcm,pins = <43 44>; + brcm,function = <1>; /* output */ + }; + }; + }; + + fragment@1 { + target = <&spi2>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins &spi2_cs_pins>; + cs-gpios = <&gpio 43 1>, <&gpio 44 1>; + status = "okay"; + + spidev2_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + + spidev2_1: spidev@1 { + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&aux>; + __overlay__ { + status = "okay"; + }; + }; + + __overrides__ { + cs0_pin = <&spi2_cs_pins>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + cs1_pin = <&spi2_cs_pins>,"brcm,pins:4", + <&frag1>,"cs-gpios:16"; + cs0_spidev = <&spidev2_0>,"status"; + cs1_spidev = <&spidev2_1>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi2-2cs-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/spi2-2cs-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi2-2cs-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi2-2cs-pi5-overlay.dts 2023-12-13 11:50:48.625961334 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&spi2>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio 0 1>, <&gpio 24 1>; + status = "okay"; + + spidev2_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + + spidev2_1: spidev@1 { + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + __overrides__ { + cs0_pin = <&frag1>,"cs-gpios:4"; + cs1_pin = <&frag1>,"cs-gpios:16"; + cs0_spidev = <&spidev2_0>,"status"; + cs1_spidev = <&spidev2_1>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi2-3cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi2-3cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi2-3cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi2-3cs-overlay.dts 2023-12-13 11:50:48.625961334 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&gpio>; + __overlay__ { + spi2_pins: spi2_pins { + brcm,pins = <40 41 42>; + brcm,function = <3>; /* alt4 */ + }; + + spi2_cs_pins: spi2_cs_pins { + brcm,pins = <43 44 45>; + brcm,function = <1>; /* output */ + }; + }; + }; + + fragment@1 { + target = <&spi2>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins &spi2_cs_pins>; + cs-gpios = <&gpio 43 1>, <&gpio 44 1>, <&gpio 45 1>; + status = "okay"; + + spidev2_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + + spidev2_1: spidev@1 { + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + + spidev2_2: spidev@2 { + compatible = "spidev"; + reg = <2>; /* CE2 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&aux>; + __overlay__ { + status = "okay"; + }; + }; + + __overrides__ { + cs0_pin = <&spi2_cs_pins>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + cs1_pin = <&spi2_cs_pins>,"brcm,pins:4", + <&frag1>,"cs-gpios:16"; + cs2_pin = <&spi2_cs_pins>,"brcm,pins:8", + <&frag1>,"cs-gpios:28"; + cs0_spidev = <&spidev2_0>,"status"; + cs1_spidev = <&spidev2_1>,"status"; + cs2_spidev = <&spidev2_2>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi3-1cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi3-1cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi3-1cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi3-1cs-overlay.dts 2023-12-13 11:50:48.625961334 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&spi3_cs_pins>; + frag0: __overlay__ { + brcm,pins = <0>; + brcm,function = <1>; /* output */ + }; + }; + + fragment@1 { + target = <&spi3>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio 0 1>; + status = "okay"; + + spidev3_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + __overrides__ { + cs0_pin = <&frag0>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + cs0_spidev = <&spidev3_0>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi3-1cs-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/spi3-1cs-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi3-1cs-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi3-1cs-pi5-overlay.dts 2023-12-13 11:50:48.625961334 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&spi3>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio 4 1>; + status = "okay"; + + spidev3_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + __overrides__ { + cs0_pin = <&frag1>,"cs-gpios:4"; + cs0_spidev = <&spidev3_0>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi3-2cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi3-2cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi3-2cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi3-2cs-overlay.dts 2023-12-13 11:50:48.625961334 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&spi3_cs_pins>; + frag0: __overlay__ { + brcm,pins = <0 24>; + brcm,function = <1>; /* output */ + }; + }; + + fragment@1 { + target = <&spi3>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio 0 1>, <&gpio 24 1>; + status = "okay"; + + spidev3_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + + spidev3_1: spidev@1 { + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + __overrides__ { + cs0_pin = <&frag0>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + cs1_pin = <&frag0>,"brcm,pins:4", + <&frag1>,"cs-gpios:16"; + cs0_spidev = <&spidev3_0>,"status"; + cs1_spidev = <&spidev3_1>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi3-2cs-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/spi3-2cs-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi3-2cs-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi3-2cs-pi5-overlay.dts 2023-12-13 11:50:48.625961334 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&spi3>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio 4 1>, <&gpio 25 1>; + status = "okay"; + + spidev3_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + + spidev3_1: spidev@1 { + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + __overrides__ { + cs0_pin = <&frag1>,"cs-gpios:4"; + cs1_pin = <&frag1>,"cs-gpios:16"; + cs0_spidev = <&spidev3_0>,"status"; + cs1_spidev = <&spidev3_1>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi4-1cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi4-1cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi4-1cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi4-1cs-overlay.dts 2023-12-13 11:50:48.625961334 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&spi4_cs_pins>; + frag0: __overlay__ { + brcm,pins = <4>; + brcm,function = <1>; /* output */ + }; + }; + + fragment@1 { + target = <&spi4>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio 4 1>; + status = "okay"; + + spidev4_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + __overrides__ { + cs0_pin = <&frag0>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + cs0_spidev = <&spidev4_0>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi4-2cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi4-2cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi4-2cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi4-2cs-overlay.dts 2023-12-13 11:50:48.625961334 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&spi4_cs_pins>; + frag0: __overlay__ { + brcm,pins = <4 25>; + brcm,function = <1>; /* output */ + }; + }; + + fragment@1 { + target = <&spi4>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio 4 1>, <&gpio 25 1>; + status = "okay"; + + spidev4_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + + spidev4_1: spidev@1 { + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + __overrides__ { + cs0_pin = <&frag0>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + cs1_pin = <&frag0>,"brcm,pins:4", + <&frag1>,"cs-gpios:16"; + cs0_spidev = <&spidev4_0>,"status"; + cs1_spidev = <&spidev4_1>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi5-1cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi5-1cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi5-1cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi5-1cs-overlay.dts 2023-12-13 11:50:48.625961334 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&spi5_cs_pins>; + frag0: __overlay__ { + brcm,pins = <12>; + brcm,function = <1>; /* output */ + }; + }; + + fragment@1 { + target = <&spi5>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio 12 1>; + status = "okay"; + + spidev5_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + __overrides__ { + cs0_pin = <&frag0>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + cs0_spidev = <&spidev5_0>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi5-1cs-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/spi5-1cs-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi5-1cs-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi5-1cs-pi5-overlay.dts 2023-12-13 11:50:48.626961336 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&spi5>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio 12 1>; + status = "okay"; + + spidev5_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + __overrides__ { + cs0_pin = <&frag1>,"cs-gpios:4"; + cs0_spidev = <&spidev5_0>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi5-2cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi5-2cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi5-2cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi5-2cs-overlay.dts 2023-12-13 11:50:48.626961336 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&spi5_cs_pins>; + frag0: __overlay__ { + brcm,pins = <12 26>; + brcm,function = <1>; /* output */ + }; + }; + + fragment@1 { + target = <&spi5>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio 12 1>, <&gpio 26 1>; + status = "okay"; + + spidev5_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + + spidev5_1: spidev@1 { + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + __overrides__ { + cs0_pin = <&frag0>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + cs1_pin = <&frag0>,"brcm,pins:4", + <&frag1>,"cs-gpios:16"; + cs0_spidev = <&spidev5_0>,"status"; + cs1_spidev = <&spidev5_1>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi5-2cs-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/spi5-2cs-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi5-2cs-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi5-2cs-pi5-overlay.dts 2023-12-13 11:50:48.626961336 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&spi5>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio 12 1>, <&gpio 26 1>; + status = "okay"; + + spidev5_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + + spidev5_1: spidev@1 { + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + __overrides__ { + cs0_pin = <&frag1>,"cs-gpios:4"; + cs1_pin = <&frag1>,"cs-gpios:16"; + cs0_spidev = <&spidev5_0>,"status"; + cs1_spidev = <&spidev5_1>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi6-1cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi6-1cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi6-1cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi6-1cs-overlay.dts 2023-12-13 11:50:48.626961336 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&spi6_cs_pins>; + frag0: __overlay__ { + brcm,pins = <18>; + brcm,function = <1>; /* output */ + }; + }; + + fragment@1 { + target = <&spi6>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio 18 1>; + status = "okay"; + + spidev6_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + __overrides__ { + cs0_pin = <&frag0>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + cs0_spidev = <&spidev6_0>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi6-2cs-overlay.dts linux/arch/arm/boot/dts/overlays/spi6-2cs-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi6-2cs-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi6-2cs-overlay.dts 2023-12-13 11:50:48.626961336 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + + +/ { + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&spi6_cs_pins>; + frag0: __overlay__ { + brcm,pins = <18 27>; + brcm,function = <1>; /* output */ + }; + }; + + fragment@1 { + target = <&spi6>; + frag1: __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio 18 1>, <&gpio 27 1>; + status = "okay"; + + spidev6_0: spidev@0 { + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + + spidev6_1: spidev@1 { + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "okay"; + }; + }; + }; + + __overrides__ { + cs0_pin = <&frag0>,"brcm,pins:0", + <&frag1>,"cs-gpios:4"; + cs1_pin = <&frag0>,"brcm,pins:4", + <&frag1>,"cs-gpios:16"; + cs0_spidev = <&spidev6_0>,"status"; + cs1_spidev = <&spidev6_1>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi-gpio35-39-overlay.dts linux/arch/arm/boot/dts/overlays/spi-gpio35-39-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi-gpio35-39-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi-gpio35-39-overlay.dts 2023-12-13 11:50:48.623961330 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device tree overlay to move spi0 to gpio 35 to 39 on CM + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + cs-gpios = <&gpio 36 1>, <&gpio 35 1>; + }; + }; + + fragment@1 { + target = <&spi0_cs_pins>; + __overlay__ { + brcm,pins = <36 35>; + }; + }; + + fragment@2 { + target = <&spi0_pins>; + __overlay__ { + brcm,pins = <37 38 39>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi-gpio40-45-overlay.dts linux/arch/arm/boot/dts/overlays/spi-gpio40-45-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi-gpio40-45-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi-gpio40-45-overlay.dts 2023-12-13 11:50:48.623961330 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Boot EEPROM overlay + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + cs-gpios = <&gpio 43 1>, <&gpio 44 1>, <&gpio 45 1>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&spi0_cs_pins>; + __overlay__ { + brcm,pins = <45 44 43>; + brcm,function = <1>; /* output */ + status = "okay"; + }; + }; + + fragment@2 { + target = <&spi0_pins>; + __overlay__ { + brcm,pins = <40 41 42>; + brcm,function = <3>; /* alt4 */ + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/spi-rtc-overlay.dts linux/arch/arm/boot/dts/overlays/spi-rtc-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/spi-rtc-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/spi-rtc-overlay.dts 2023-12-13 11:50:48.623961330 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for several SPI-based Real Time Clocks +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&rtc>; + __dormant__ { + compatible = "dallas,ds3232"; + }; + }; + + fragment@1 { + target = <&rtc>; + __dormant__ { + compatible = "dallas,ds3234"; + }; + }; + + fragment@2 { + target = <&rtc>; + __dormant__ { + compatible = "nxp,rtc-pcf2123"; + }; + }; + + spidev: fragment@100 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + frag101: fragment@101 { + target = <&spi0>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + rtc: rtc@0 { + reg = <0>; + spi-max-frequency = <5000000>; + }; + }; + }; + + __overrides__ { + spi0_0 = <&spidev>, "target:0=",<&spidev0>, + <&frag101>, "target:0=",<&spi0>, + <&rtc>, "reg:0=0"; + spi0_1 = <&spidev>, "target:0=",<&spidev1>, + <&frag101>, "target:0=",<&spi0>, + <&rtc>, "reg:0=1"; + spi1_0 = <0>,"-100", + <&frag101>, "target:0=",<&spi1>, + <&rtc>, "reg:0=0"; + spi1_1 = <0>,"-100", + <&frag101>, "target:0=",<&spi1>, + <&rtc>, "reg:0=1"; + spi2_0 = <0>,"-100", + <&frag101>, "target:0=",<&spi2>, + <&rtc>, "reg:0=0"; + spi2_1 = <0>,"-100", + <&frag101>, "target:0=",<&spi2>, + <&rtc>, "reg:0=1"; + cs_high = <&rtc>, "spi-cs-high?"; + + ds3232 = <0>,"+0"; + ds3234 = <0>,"+1"; + pcf2123 = <0>,"+2"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ssd1306-overlay.dts linux/arch/arm/boot/dts/overlays/ssd1306-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ssd1306-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ssd1306-overlay.dts 2023-12-13 11:50:48.626961336 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for SSD1306 128x64 and 128x32 OLED displays +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c1>; + __overlay__ { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + ssd1306: oled@3c{ + compatible = "solomon,ssd1306fb-i2c"; + reg = <0x3c>; + solomon,width = <128>; + solomon,height = <64>; + solomon,page-offset = <0>; + }; + }; + }; + + __overrides__ { + address = <&ssd1306>,"reg:0"; + width = <&ssd1306>,"solomon,width:0"; + height = <&ssd1306>,"solomon,height:0"; + offset = <&ssd1306>,"solomon,page-offset:0"; + normal = <&ssd1306>,"solomon,segment-no-remap?"; + sequential = <&ssd1306>,"solomon,com-seq?"; + remapped = <&ssd1306>,"solomon,com-lrremap?"; + inverted = <&ssd1306>,"solomon,com-invdir?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts linux/arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts 2023-12-13 11:50:48.626961336 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for SSD1306 based SPI OLED display + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + ssd1306_pins: ssd1306_pins { + brcm,pins = <25 24>; + brcm,function = <1 1>; /* out out */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + ssd1306: ssd1306@0{ + compatible = "solomon,ssd1306"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&ssd1306_pins>; + + spi-max-frequency = <10000000>; + bgr = <0>; + bpp = <1>; + rotate = <0>; + fps = <25>; + buswidth = <8>; + reset-gpios = <&gpio 25 1>; + dc-gpios = <&gpio 24 0>; + debug = <0>; + + solomon,height = <64>; + solomon,width = <128>; + solomon,page-offset = <0>; + }; + }; + }; + + __overrides__ { + speed = <&ssd1306>,"spi-max-frequency:0"; + rotate = <&ssd1306>,"rotate:0"; + fps = <&ssd1306>,"fps:0"; + debug = <&ssd1306>,"debug:0"; + dc_pin = <&ssd1306>,"dc-gpios:4", + <&ssd1306_pins>,"brcm,pins:4"; + reset_pin = <&ssd1306>,"reset-gpios:4", + <&ssd1306_pins>,"brcm,pins:0"; + height = <&ssd1306>,"solomon,height:0"; + inverted = <&ssd1306>,"solomon,com-invdir?"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ssd1331-spi-overlay.dts linux/arch/arm/boot/dts/overlays/ssd1331-spi-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ssd1331-spi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ssd1331-spi-overlay.dts 2023-12-13 11:50:48.627961339 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for SSD1331 based SPI OLED display + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + ssd1331_pins: ssd1331_pins { + brcm,pins = <25 24>; + brcm,function = <1 1>; /* out out */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + ssd1331: ssd1331@0{ + compatible = "solomon,ssd1331"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&ssd1331_pins>; + + spi-max-frequency = <4500000>; + bgr = <0>; + bpp = <16>; + rotate = <0>; + fps = <25>; + buswidth = <8>; + reset-gpios = <&gpio 25 1>; + dc-gpios = <&gpio 24 0>; + debug = <0>; + + solomon,height = <64>; + solomon,width = <96>; + solomon,page-offset = <0>; + }; + }; + }; + + __overrides__ { + speed = <&ssd1331>,"spi-max-frequency:0"; + rotate = <&ssd1331>,"rotate:0"; + fps = <&ssd1331>,"fps:0"; + debug = <&ssd1331>,"debug:0"; + dc_pin = <&ssd1331>,"dc-gpios:4", + <&ssd1331_pins>,"brcm,pins:4"; + reset_pin = <&ssd1331>,"reset-gpios:4", + <&ssd1331_pins>,"brcm,pins:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ssd1351-spi-overlay.dts linux/arch/arm/boot/dts/overlays/ssd1351-spi-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ssd1351-spi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ssd1351-spi-overlay.dts 2023-12-13 11:50:48.627961339 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for SSD1351 based SPI OLED display + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + ssd1351_pins: ssd1351_pins { + brcm,pins = <25 24>; + brcm,function = <1 1>; /* out out */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + ssd1351: ssd1351@0{ + compatible = "solomon,ssd1351"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&ssd1351_pins>; + + spi-max-frequency = <4500000>; + bgr = <0>; + bpp = <16>; + rotate = <0>; + fps = <25>; + buswidth = <8>; + reset-gpios = <&gpio 25 1>; + dc-gpios = <&gpio 24 0>; + debug = <0>; + + solomon,height = <128>; + solomon,width = <128>; + solomon,page-offset = <0>; + }; + }; + }; + + __overrides__ { + speed = <&ssd1351>,"spi-max-frequency:0"; + rotate = <&ssd1351>,"rotate:0"; + fps = <&ssd1351>,"fps:0"; + debug = <&ssd1351>,"debug:0"; + dc_pin = <&ssd1351>,"dc-gpios:4", + <&ssd1351_pins>,"brcm,pins:4"; + reset_pin = <&ssd1351>,"reset-gpios:4", + <&ssd1351_pins>,"brcm,pins:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/superaudioboard-overlay.dts linux/arch/arm/boot/dts/overlays/superaudioboard-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/superaudioboard-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/superaudioboard-overlay.dts 2023-12-13 11:50:48.627961339 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for SuperAudioBoard +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&sound>; + __overlay__ { + compatible = "simple-audio-card"; + i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + + simple-audio-card,name = "SuperAudioBoard"; + + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out"; + + simple-audio-card,routing = + "Line Out","AOUTA+", + "Line Out","AOUTA-", + "Line Out","AOUTB+", + "Line Out","AOUTB-", + "AINA","Line In", + "AINB","Line In"; + + simple-audio-card,format = "i2s"; + + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + + simple-audio-card,cpu { + sound-dai = <&i2s_clk_consumer>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&cs4271>; + system-clock-frequency = <24576000>; + }; + }; + }; + + fragment@1 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cs4271: cs4271@10 { + #sound-dai-cells = <0>; + compatible = "cirrus,cs4271"; + reg = <0x10>; + status = "okay"; + reset-gpio = <&gpio 26 0>; /* Pin 26, active high */ + }; + }; + }; + __overrides__ { + gpiopin = <&cs4271>,"reset-gpio:4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/sx150x-overlay.dts linux/arch/arm/boot/dts/overlays/sx150x-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/sx150x-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/sx150x-overlay.dts 2023-12-13 11:50:48.627961339 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for SX150x I2C GPIO Expanders from Semtech + +// dtparams: +// sx150<x>-<n>-<m> - Enables SX150X device on I2C#<n> with slave address <m>. <x> may be 1-9. +// <n> may be 0 or 1. Permissible values of <m> (which is denoted in hex) +// depend on the device variant. +// For SX1501, SX1502, SX1504 and SX1505, <m> may be 20 or 21. +// For SX1503 and SX1506, <m> may be 20. +// For SX1507 and SX1509, <m> may be 3E, 3F, 70 or 71. +// For SX1508, <m> may be 20, 21, 22 or 23. +// sx150<x>-<n>-<m>-int-gpio - Integer, enables interrupts on SX150X device on I2C#<n> with slave address <m>, +// specifies the GPIO pin to which NINT output of SX150X is connected. +// +// +// Example 1: A single SX1505 device on I2C#1 with its slave address set to 0x20 and NINT output connected to GPIO25: +// dtoverlay=sx150x:sx1505-1-20,sx1505-1-20-int-gpio=25 +// +// Example 2: Two SX1507 devices on I2C#0 with their slave addresses set to 0x3E and 0x70 (interrupts not used): +// dtoverlay=sx150x:sx1507-0-3E,sx1507-0-70 + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + // Enable I2C#0 interface + fragment@0 { + target = <&i2c0>; + __dormant__ { + status = "okay"; + }; + }; + + // Enable I2C#1 interface + fragment@1 { + target = <&i2c1>; + __dormant__ { + status = "okay"; + }; + }; + + // Enable a SX1501 on I2C#0 at slave addr 0x20 + fragment@2 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1501_0_20: sx150x@20 { + compatible = "semtech,sx1501q"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1501-0-20-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1501 on I2C#1 at slave addr 0x20 + fragment@3 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1501_1_20: sx150x@20 { + compatible = "semtech,sx1501q"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1501-1-20-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1501 on I2C#0 at slave addr 0x21 + fragment@4 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1501_0_21: sx150x@21 { + compatible = "semtech,sx1501q"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1501-0-21-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1501 on I2C#1 at slave addr 0x21 + fragment@5 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1501_1_21: sx150x@21 { + compatible = "semtech,sx1501q"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1501-1-21-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1502 on I2C#0 at slave addr 0x20 + fragment@6 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1502_0_20: sx150x@20 { + compatible = "semtech,sx1502q"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1502-0-20-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1502 on I2C#1 at slave addr 0x20 + fragment@7 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1502_1_20: sx150x@20 { + compatible = "semtech,sx1502q"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1502-1-20-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1502 on I2C#0 at slave addr 0x21 + fragment@8 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1502_0_21: sx150x@21 { + compatible = "semtech,sx1502q"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1502-0-21-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1502 on I2C#1 at slave addr 0x21 + fragment@9 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1502_1_21: sx150x@21 { + compatible = "semtech,sx1502q"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1501-1-21-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1503 on I2C#0 at slave addr 0x20 + fragment@10 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1503_0_20: sx150x@20 { + compatible = "semtech,sx1503q"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1503-0-20-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1503 on I2C#1 at slave addr 0x20 + fragment@11 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1503_1_20: sx150x@20 { + compatible = "semtech,sx1503q"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1503-1-20-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1504 on I2C#0 at slave addr 0x20 + fragment@12 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1504_0_20: sx150x@20 { + compatible = "semtech,sx1504q"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1504-0-20-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1504 on I2C#1 at slave addr 0x20 + fragment@13 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1504_1_20: sx150x@20 { + compatible = "semtech,sx1504q"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1504-1-20-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1504 on I2C#0 at slave addr 0x21 + fragment@14 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1504_0_21: sx150x@21 { + compatible = "semtech,sx1504q"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1504-0-21-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1504 on I2C#1 at slave addr 0x21 + fragment@15 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1504_1_21: sx150x@21 { + compatible = "semtech,sx1504q"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1504-1-20-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1505 on I2C#0 at slave addr 0x20 + fragment@16 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1505_0_20: sx150x@20 { + compatible = "semtech,sx1505q"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1505-0-20-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1505 on I2C#1 at slave addr 0x20 + fragment@17 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1505_1_20: sx150x@20 { + compatible = "semtech,sx1505q"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1505-1-20-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1505 on I2C#0 at slave addr 0x21 + fragment@18 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1505_0_21: sx150x@21 { + compatible = "semtech,sx1505q"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1505-0-21-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1505 on I2C#1 at slave addr 0x21 + fragment@19 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1505_1_21: sx150x@21 { + compatible = "semtech,sx1505q"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1505-1-21-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1506 on I2C#0 at slave addr 0x20 + fragment@20 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1506_0_20: sx150x@20 { + compatible = "semtech,sx1506q"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1506-0-20-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1506 on I2C#1 at slave addr 0x20 + fragment@21 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1506_1_20: sx150x@20 { + compatible = "semtech,sx1506q"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1506-1-20-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1507 on I2C#0 at slave addr 0x3E + fragment@22 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1507_0_3E: sx150x@3E { + compatible = "semtech,sx1507q"; + reg = <0x3E>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1507_0_3E-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1507 on I2C#1 at slave addr 0x3E + fragment@23 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1507_1_3E: sx150x@3E { + compatible = "semtech,sx1507q"; + reg = <0x3E>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1507_1_3E-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1507 on I2C#0 at slave addr 0x3F + fragment@24 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1507_0_3F: sx150x@3F { + compatible = "semtech,sx1507q"; + reg = <0x3F>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1507_0_3F-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1507 on I2C#1 at slave addr 0x3F + fragment@25 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1507_1_3F: sx150x@3F { + compatible = "semtech,sx1507q"; + reg = <0x3F>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1507_1_3F-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1507 on I2C#0 at slave addr 0x70 + fragment@26 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1507_0_70: sx150x@70 { + compatible = "semtech,sx1507q"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1507-0-70-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1507 on I2C#1 at slave addr 0x70 + fragment@27 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1507_1_70: sx150x@70 { + compatible = "semtech,sx1507q"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1507-1-70-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1507 on I2C#0 at slave addr 0x71 + fragment@28 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1507_0_71: sx150x@71 { + compatible = "semtech,sx1507q"; + reg = <0x71>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1507-0-71-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1507 on I2C#1 at slave addr 0x71 + fragment@29 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1507_1_71: sx150x@71 { + compatible = "semtech,sx1507q"; + reg = <0x71>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1507-1-71-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1508 on I2C#0 at slave addr 0x20 + fragment@30 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1508_0_20: sx150x@20 { + compatible = "semtech,sx1508q"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1508-0-20-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1508 on I2C#1 at slave addr 0x20 + fragment@31 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1508_1_20: sx150x@20 { + compatible = "semtech,sx1508q"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1508-1-20-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1508 on I2C#0 at slave addr 0x21 + fragment@32 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1508_0_21: sx150x@21 { + compatible = "semtech,sx1508q"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1508-0-21-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1508 on I2C#1 at slave addr 0x21 + fragment@33 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1508_1_21: sx150x@21 { + compatible = "semtech,sx1508q"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1508-1-21-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1508 on I2C#0 at slave addr 0x22 + fragment@34 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1508_0_22: sx150x@22 { + compatible = "semtech,sx1508q"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1508-0-22-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1508 on I2C#1 at slave addr 0x22 + fragment@35 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1508_1_22: sx150x@22 { + compatible = "semtech,sx1508q"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1508-1-22-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1508 on I2C#0 at slave addr 0x23 + fragment@36 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1508_0_23: sx150x@23 { + compatible = "semtech,sx1508q"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1508-0-23-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1508 on I2C#1 at slave addr 0x23 + fragment@37 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1508_1_23: sx150x@23 { + compatible = "semtech,sx1508q"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1508-1-23-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1509 on I2C#0 at slave addr 0x3E + fragment@38 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1509_0_3E: sx150x@3E { + compatible = "semtech,sx1509q"; + reg = <0x3E>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1509_0_3E-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1509 on I2C#1 at slave addr 0x3E + fragment@39 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1509_1_3E: sx150x@3E { + compatible = "semtech,sx1509q"; + reg = <0x3E>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1509_1_3E-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1509 on I2C#0 at slave addr 0x3F + fragment@40 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1509_0_3F: sx150x@3F { + compatible = "semtech,sx1509q"; + reg = <0x3F>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1509_0_3F-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1509 on I2C#1 at slave addr 0x3F + fragment@41 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1509_1_3F: sx150x@3F { + compatible = "semtech,sx1509q"; + reg = <0x3F>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1509_1_3F-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1509 on I2C#0 at slave addr 0x70 + fragment@42 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1509_0_70: sx150x@70 { + compatible = "semtech,sx1509q"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1509-0-70-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1509 on I2C#1 at slave addr 0x70 + fragment@43 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1509_1_70: sx150x@70 { + compatible = "semtech,sx1509q"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1509-1-70-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1509 on I2C#0 at slave addr 0x71 + fragment@44 { + target = <&i2c0>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1509_0_71: sx150x@71 { + compatible = "semtech,sx1509q"; + reg = <0x71>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1509-0-71-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable a SX1509 on I2C#1 at slave addr 0x71 + fragment@45 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + sx1509_1_71: sx150x@71 { + compatible = "semtech,sx1509q"; + reg = <0x71>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <25 2>; /* 1st word overwritten by sx1509-1-71-int-gpio parameter + 2nd word is 2 for falling-edge triggered */ + status = "okay"; + }; + }; + }; + + // Enable interrupts for a SX1501 on I2C#0 at slave addr 0x20 + fragment@46 { + target = <&sx1501_0_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_20_pins>; + }; + }; + + // Enable interrupts for a SX1501 on I2C#1 at slave addr 0x20 + fragment@47 { + target = <&sx1501_1_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_20_pins>; + }; + }; + + // Enable interrupts for a SX1501 on I2C#0 at slave addr 0x21 + fragment@48 { + target = <&sx1501_0_21>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_21_pins>; + }; + }; + + // Enable interrupts for a SX1501 on I2C#1 at slave addr 0x21 + fragment@49 { + target = <&sx1501_1_21>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_21_pins>; + }; + }; + + // Enable interrupts for a SX1502 on I2C#0 at slave addr 0x20 + fragment@50 { + target = <&sx1502_0_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_20_pins>; + }; + }; + + // Enable interrupts for a SX1502 on I2C#1 at slave addr 0x20 + fragment@51 { + target = <&sx1502_1_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_20_pins>; + }; + }; + + // Enable interrupts for a SX1502 on I2C#0 at slave addr 0x21 + fragment@52 { + target = <&sx1502_0_21>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_21_pins>; + }; + }; + + // Enable interrupts for a SX1502 on I2C#1 at slave addr 0x21 + fragment@53 { + target = <&sx1502_1_21>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_21_pins>; + }; + }; + + // Enable interrupts for a SX1503 on I2C#0 at slave addr 0x20 + fragment@54 { + target = <&sx1503_0_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_20_pins>; + }; + }; + + // Enable interrupts for a SX1503 on I2C#1 at slave addr 0x20 + fragment@55 { + target = <&sx1503_1_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_20_pins>; + }; + }; + + // Enable interrupts for a SX1504 on I2C#0 at slave addr 0x20 + fragment@56 { + target = <&sx1504_0_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_20_pins>; + }; + }; + + // Enable interrupts for a SX1504 on I2C#1 at slave addr 0x20 + fragment@57 { + target = <&sx1504_1_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_20_pins>; + }; + }; + + // Enable interrupts for a SX1504 on I2C#0 at slave addr 0x21 + fragment@58 { + target = <&sx1504_0_21>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_21_pins>; + }; + }; + + // Enable interrupts for a SX1504 on I2C#1 at slave addr 0x21 + fragment@59 { + target = <&sx1504_1_21>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_21_pins>; + }; + }; + + // Enable interrupts for a SX1505 on I2C#0 at slave addr 0x20 + fragment@60 { + target = <&sx1505_0_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_20_pins>; + }; + }; + + // Enable interrupts for a SX1505 on I2C#1 at slave addr 0x20 + fragment@61 { + target = <&sx1505_1_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_20_pins>; + }; + }; + + // Enable interrupts for a SX1505 on I2C#0 at slave addr 0x21 + fragment@62 { + target = <&sx1505_0_21>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_21_pins>; + }; + }; + + // Enable interrupts for a SX1505 on I2C#1 at slave addr 0x21 + fragment@63 { + target = <&sx1505_1_21>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_21_pins>; + }; + }; + + // Enable interrupts for a SX1506 on I2C#0 at slave addr 0x20 + fragment@64 { + target = <&sx1506_0_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_20_pins>; + }; + }; + + // Enable interrupts for a SX1506 on I2C#1 at slave addr 0x20 + fragment@65 { + target = <&sx1506_1_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_20_pins>; + }; + }; + + // Enable interrupts for a SX1507 on I2C#0 at slave addr 0x3E + fragment@66 { + target = <&sx1507_0_3E>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_3E_pins>; + }; + }; + + // Enable interrupts for a SX1507 on I2C#1 at slave addr 0x3E + fragment@67 { + target = <&sx1507_1_3E>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_3E_pins>; + }; + }; + + // Enable interrupts for a SX1507 on I2C#0 at slave addr 0x3F + fragment@68 { + target = <&sx1507_0_3F>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_3F_pins>; + }; + }; + + // Enable interrupts for a SX1507 on I2C#1 at slave addr 0x3F + fragment@69 { + target = <&sx1507_1_3F>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_3F_pins>; + }; + }; + + // Enable interrupts for a SX1507 on I2C#0 at slave addr 0x70 + fragment@70 { + target = <&sx1507_0_70>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_70_pins>; + }; + }; + + // Enable interrupts for a SX1507 on I2C#1 at slave addr 0x70 + fragment@71 { + target = <&sx1507_1_70>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_70_pins>; + }; + }; + + // Enable interrupts for a SX1507 on I2C#0 at slave addr 0x71 + fragment@72 { + target = <&sx1507_0_71>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_71_pins>; + }; + }; + + // Enable interrupts for a SX1507 on I2C#1 at slave addr 0x71 + fragment@73 { + target = <&sx1507_1_71>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_71_pins>; + }; + }; + + // Enable interrupts for a SX1508 on I2C#0 at slave addr 0x20 + fragment@74 { + target = <&sx1508_0_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_20_pins>; + }; + }; + + // Enable interrupts for a SX1508 on I2C#1 at slave addr 0x20 + fragment@75 { + target = <&sx1508_1_20>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_20_pins>; + }; + }; + + // Enable interrupts for a SX1508 on I2C#0 at slave addr 0x21 + fragment@76 { + target = <&sx1508_0_21>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_21_pins>; + }; + }; + + // Enable interrupts for a SX1508 on I2C#1 at slave addr 0x21 + fragment@77 { + target = <&sx1508_1_21>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_21_pins>; + }; + }; + + // Enable interrupts for a SX1508 on I2C#0 at slave addr 0x22 + fragment@78 { + target = <&sx1508_0_22>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_22_pins>; + }; + }; + + // Enable interrupts for a SX1508 on I2C#1 at slave addr 0x22 + fragment@79 { + target = <&sx1508_1_22>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_22_pins>; + }; + }; + + // Enable interrupts for a SX1508 on I2C#0 at slave addr 0x23 + fragment@80 { + target = <&sx1508_0_23>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_23_pins>; + }; + }; + + // Enable interrupts for a SX1508 on I2C#1 at slave addr 0x23 + fragment@81 { + target = <&sx1508_1_23>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_23_pins>; + }; + }; + + // Enable interrupts for a SX1509 on I2C#0 at slave addr 0x3E + fragment@82 { + target = <&sx1509_0_3E>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_3E_pins>; + }; + }; + + // Enable interrupts for a SX1509 on I2C#1 at slave addr 0x3E + fragment@83 { + target = <&sx1509_1_3E>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_3E_pins>; + }; + }; + + // Enable interrupts for a SX1509 on I2C#0 at slave addr 0x3F + fragment@84 { + target = <&sx1509_0_3F>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_3F_pins>; + }; + }; + + // Enable interrupts for a SX1509 on I2C#1 at slave addr 0x3F + fragment@85 { + target = <&sx1509_1_3F>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_3F_pins>; + }; + }; + + // Enable interrupts for a SX1509 on I2C#0 at slave addr 0x70 + fragment@86 { + target = <&sx1509_0_70>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_70_pins>; + }; + }; + + // Enable interrupts for a SX1509 on I2C#1 at slave addr 0x70 + fragment@87 { + target = <&sx1509_1_70>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_70_pins>; + }; + }; + + // Enable interrupts for a SX1509 on I2C#0 at slave addr 0x71 + fragment@88 { + target = <&sx1509_0_71>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_0_71_pins>; + }; + }; + + // Enable interrupts for a SX1509 on I2C#1 at slave addr 0x71 + fragment@89 { + target = <&sx1509_1_71>; + __dormant__ { + interrupt-parent = <&gpio>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&sx150x_1_71_pins>; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x20 + // Configure as a input with no pull-up/down + fragment@90 { + target = <&gpio>; + __dormant__ { + sx150x_0_20_pins: sx150x_0_20_pins { + brcm,pins = <0>; /* overwritten by sx150x-0-20-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x20 + // Configure as a input with no pull-up/down + fragment@91 { + target = <&gpio>; + __dormant__ { + sx150x_1_20_pins: sx150x_1_20_pins { + brcm,pins = <0>; /* overwritten by sx150x-1-20-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x21 + // Configure as a input with no pull-up/down + fragment@92 { + target = <&gpio>; + __dormant__ { + sx150x_0_21_pins: sx150x_0_21_pins { + brcm,pins = <0>; /* overwritten by sx150x-0-21-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x21 + // Configure as a input with no pull-up/down + fragment@93 { + target = <&gpio>; + __dormant__ { + sx150x_1_21_pins: sx150x_1_21_pins { + brcm,pins = <0>; /* overwritten by sx150x-1-21-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x22 + // Configure as a input with no pull-up/down + fragment@94 { + target = <&gpio>; + __dormant__ { + sx150x_0_22_pins: sx150x_0_22_pins { + brcm,pins = <0>; /* overwritten by sx150x-0-22-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x22 + // Configure as a input with no pull-up/down + fragment@95 { + target = <&gpio>; + __dormant__ { + sx150x_1_22_pins: sx150x_1_22_pins { + brcm,pins = <0>; /* overwritten by sx150x-1-22-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x23 + // Configure as a input with no pull-up/down + fragment@96 { + target = <&gpio>; + __dormant__ { + sx150x_0_23_pins: sx150x_0_23_pins { + brcm,pins = <0>; /* overwritten by sx150x-0-23-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x23 + // Configure as a input with no pull-up/down + fragment@97 { + target = <&gpio>; + __dormant__ { + sx150x_1_23_pins: sx150x_1_23_pins { + brcm,pins = <0>; /* overwritten by sx150x-1-23-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x3E + // Configure as a input with no pull-up/down + fragment@98 { + target = <&gpio>; + __dormant__ { + sx150x_0_3E_pins: sx150x_0_3E_pins { + brcm,pins = <0>; /* overwritten by sx150x-0-3E-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x3E + // Configure as a input with no pull-up/down + fragment@99 { + target = <&gpio>; + __dormant__ { + sx150x_1_3E_pins: sx150x_1_3E_pins { + brcm,pins = <0>; /* overwritten by sx150x-1-3E-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x3F + // Configure as a input with no pull-up/down + fragment@100 { + target = <&gpio>; + __dormant__ { + sx150x_0_3F_pins: sx150x_0_3F_pins { + brcm,pins = <0>; /* overwritten by sx150x-0-3F-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x3F + // Configure as a input with no pull-up/down + fragment@101 { + target = <&gpio>; + __dormant__ { + sx150x_1_3F_pins: sx150x_1_3F_pins { + brcm,pins = <0>; /* overwritten by sx150x-1-3F-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x70 + // Configure as a input with no pull-up/down + fragment@102 { + target = <&gpio>; + __dormant__ { + sx150x_0_70_pins: sx150x_0_70_pins { + brcm,pins = <0>; /* overwritten by sx150x-0-70-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x70 + // Configure as a input with no pull-up/down + fragment@103 { + target = <&gpio>; + __dormant__ { + sx150x_1_70_pins: sx150x_1_70_pins { + brcm,pins = <0>; /* overwritten by sx150x-1-70-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x71 + // Configure as a input with no pull-up/down + fragment@104 { + target = <&gpio>; + __dormant__ { + sx150x_0_71_pins: sx150x_0_71_pins { + brcm,pins = <0>; /* overwritten by sx150x-0-71-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + // Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x71 + // Configure as a input with no pull-up/down + fragment@105 { + target = <&gpio>; + __dormant__ { + sx150x_1_71_pins: sx150x_1_71_pins { + brcm,pins = <0>; /* overwritten by sx150x-1-71-int-gpio parameter */ + brcm,function = <0>; + brcm,pull = <0>; + }; + }; + }; + + __overrides__ { + sx1501-0-20 = <0>,"+0+2"; + sx1501-1-20 = <0>,"+1+3"; + sx1501-0-21 = <0>,"+0+4"; + sx1501-1-21 = <0>,"+1+5"; + sx1502-0-20 = <0>,"+0+6"; + sx1502-1-20 = <0>,"+1+7"; + sx1502-0-21 = <0>,"+0+8"; + sx1502-1-21 = <0>,"+1+9"; + sx1503-0-20 = <0>,"+0+10"; + sx1503-1-20 = <0>,"+1+11"; + sx1504-0-20 = <0>,"+0+12"; + sx1504-1-20 = <0>,"+1+13"; + sx1504-0-21 = <0>,"+0+14"; + sx1504-1-21 = <0>,"+1+15"; + sx1505-0-20 = <0>,"+0+16"; + sx1505-1-20 = <0>,"+1+17"; + sx1505-0-21 = <0>,"+0+18"; + sx1505-1-21 = <0>,"+1+19"; + sx1506-0-20 = <0>,"+0+20"; + sx1506-1-20 = <0>,"+1+21"; + sx1507-0-3E = <0>,"+0+22"; + sx1507-1-3E = <0>,"+1+23"; + sx1507-0-3F = <0>,"+0+24"; + sx1507-1-3F = <0>,"+1+25"; + sx1507-0-70 = <0>,"+0+26"; + sx1507-1-70 = <0>,"+1+27"; + sx1507-0-71 = <0>,"+0+28"; + sx1507-1-71 = <0>,"+1+29"; + sx1508-0-20 = <0>,"+0+30"; + sx1508-1-20 = <0>,"+1+31"; + sx1508-0-21 = <0>,"+0+32"; + sx1508-1-21 = <0>,"+1+33"; + sx1508-0-22 = <0>,"+0+34"; + sx1508-1-22 = <0>,"+1+35"; + sx1508-0-23 = <0>,"+0+36"; + sx1508-1-23 = <0>,"+1+37"; + sx1509-0-3E = <0>,"+0+38"; + sx1509-1-3E = <0>,"+1+39"; + sx1509-0-3F = <0>,"+0+40"; + sx1509-1-3F = <0>,"+1+41"; + sx1509-0-70 = <0>,"+0+42"; + sx1509-1-70 = <0>,"+1+43"; + sx1509-0-71 = <0>,"+0+44"; + sx1509-1-71 = <0>,"+1+45"; + sx1501-0-20-int-gpio = <0>,"+46+90", <&sx150x_0_20_pins>,"brcm,pins:0", <&sx1501_0_20>,"interrupts:0"; + sx1501-1-20-int-gpio = <0>,"+47+91", <&sx150x_1_20_pins>,"brcm,pins:0", <&sx1501_1_20>,"interrupts:0"; + sx1501-0-21-int-gpio = <0>,"+48+92", <&sx150x_0_21_pins>,"brcm,pins:0", <&sx1501_0_21>,"interrupts:0"; + sx1501-1-21-int-gpio = <0>,"+49+93", <&sx150x_1_21_pins>,"brcm,pins:0", <&sx1501_1_21>,"interrupts:0"; + sx1502-0-20-int-gpio = <0>,"+50+90", <&sx150x_0_20_pins>,"brcm,pins:0", <&sx1502_0_20>,"interrupts:0"; + sx1502-1-20-int-gpio = <0>,"+51+91", <&sx150x_1_20_pins>,"brcm,pins:0", <&sx1502_1_20>,"interrupts:0"; + sx1502-0-21-int-gpio = <0>,"+52+92", <&sx150x_0_21_pins>,"brcm,pins:0", <&sx1502_0_21>,"interrupts:0"; + sx1502-1-21-int-gpio = <0>,"+53+93", <&sx150x_1_21_pins>,"brcm,pins:0", <&sx1502_1_21>,"interrupts:0"; + sx1503-0-20-int-gpio = <0>,"+54+90", <&sx150x_0_20_pins>,"brcm,pins:0", <&sx1503_0_20>,"interrupts:0"; + sx1503-1-20-int-gpio = <0>,"+55+91", <&sx150x_1_20_pins>,"brcm,pins:0", <&sx1503_1_20>,"interrupts:0"; + sx1504-0-20-int-gpio = <0>,"+56+90", <&sx150x_0_20_pins>,"brcm,pins:0", <&sx1504_0_20>,"interrupts:0"; + sx1504-1-20-int-gpio = <0>,"+57+91", <&sx150x_1_20_pins>,"brcm,pins:0", <&sx1504_1_20>,"interrupts:0"; + sx1504-0-21-int-gpio = <0>,"+58+92", <&sx150x_0_21_pins>,"brcm,pins:0", <&sx1504_0_21>,"interrupts:0"; + sx1504-1-21-int-gpio = <0>,"+59+93", <&sx150x_1_21_pins>,"brcm,pins:0", <&sx1504_1_21>,"interrupts:0"; + sx1505-0-20-int-gpio = <0>,"+60+90", <&sx150x_0_20_pins>,"brcm,pins:0", <&sx1505_0_20>,"interrupts:0"; + sx1505-1-20-int-gpio = <0>,"+61+91", <&sx150x_1_20_pins>,"brcm,pins:0", <&sx1505_1_20>,"interrupts:0"; + sx1505-0-21-int-gpio = <0>,"+62+92", <&sx150x_0_21_pins>,"brcm,pins:0", <&sx1505_0_21>,"interrupts:0"; + sx1505-1-21-int-gpio = <0>,"+63+93", <&sx150x_1_21_pins>,"brcm,pins:0", <&sx1505_1_21>,"interrupts:0"; + sx1506-0-20-int-gpio = <0>,"+64+90", <&sx150x_0_20_pins>,"brcm,pins:0", <&sx1506_0_20>,"interrupts:0"; + sx1506-1-20-int-gpio = <0>,"+65+91", <&sx150x_1_20_pins>,"brcm,pins:0", <&sx1506_1_20>,"interrupts:0"; + sx1507-0-3E-int-gpio = <0>,"+66+98", <&sx150x_0_3E_pins>,"brcm,pins:0", <&sx1507_0_3E>,"interrupts:0"; + sx1507-1-3E-int-gpio = <0>,"+67+99", <&sx150x_1_3E_pins>,"brcm,pins:0", <&sx1507_1_3E>,"interrupts:0"; + sx1507-0-3F-int-gpio = <0>,"+68+100", <&sx150x_0_3F_pins>,"brcm,pins:0", <&sx1507_0_3F>,"interrupts:0"; + sx1507-1-3F-int-gpio = <0>,"+69+101", <&sx150x_1_3F_pins>,"brcm,pins:0", <&sx1507_1_3F>,"interrupts:0"; + sx1507-0-70-int-gpio = <0>,"+60+102", <&sx150x_0_70_pins>,"brcm,pins:0", <&sx1507_0_70>,"interrupts:0"; + sx1507-1-70-int-gpio = <0>,"+71+103", <&sx150x_1_70_pins>,"brcm,pins:0", <&sx1507_1_70>,"interrupts:0"; + sx1507-0-71-int-gpio = <0>,"+72+104", <&sx150x_0_71_pins>,"brcm,pins:0", <&sx1507_0_71>,"interrupts:0"; + sx1507-1-71-int-gpio = <0>,"+73+105", <&sx150x_1_71_pins>,"brcm,pins:0", <&sx1507_1_71>,"interrupts:0"; + sx1508-0-20-int-gpio = <0>,"+74+90", <&sx150x_0_20_pins>,"brcm,pins:0", <&sx1508_0_20>,"interrupts:0"; + sx1508-1-20-int-gpio = <0>,"+75+91", <&sx150x_1_20_pins>,"brcm,pins:0", <&sx1508_1_20>,"interrupts:0"; + sx1508-0-21-int-gpio = <0>,"+76+92", <&sx150x_0_21_pins>,"brcm,pins:0", <&sx1508_0_21>,"interrupts:0"; + sx1508-1-21-int-gpio = <0>,"+77+93", <&sx150x_1_21_pins>,"brcm,pins:0", <&sx1508_1_21>,"interrupts:0"; + sx1508-0-22-int-gpio = <0>,"+78+94", <&sx150x_0_22_pins>,"brcm,pins:0", <&sx1508_0_22>,"interrupts:0"; + sx1508-1-22-int-gpio = <0>,"+79+95", <&sx150x_1_22_pins>,"brcm,pins:0", <&sx1508_1_22>,"interrupts:0"; + sx1508-0-23-int-gpio = <0>,"+80+96", <&sx150x_0_23_pins>,"brcm,pins:0", <&sx1508_0_23>,"interrupts:0"; + sx1508-1-23-int-gpio = <0>,"+81+97", <&sx150x_1_23_pins>,"brcm,pins:0", <&sx1508_1_23>,"interrupts:0"; + sx1509-0-3E-int-gpio = <0>,"+82+98", <&sx150x_0_3E_pins>,"brcm,pins:0", <&sx1509_0_3E>,"interrupts:0"; + sx1509-1-3E-int-gpio = <0>,"+83+99", <&sx150x_1_3E_pins>,"brcm,pins:0", <&sx1509_1_3E>,"interrupts:0"; + sx1509-0-3F-int-gpio = <0>,"+84+100", <&sx150x_0_3F_pins>,"brcm,pins:0", <&sx1509_0_3F>,"interrupts:0"; + sx1509-1-3F-int-gpio = <0>,"+85+101", <&sx150x_1_3F_pins>,"brcm,pins:0", <&sx1509_1_3F>,"interrupts:0"; + sx1509-0-70-int-gpio = <0>,"+86+102", <&sx150x_0_70_pins>,"brcm,pins:0", <&sx1509_0_70>,"interrupts:0"; + sx1509-1-70-int-gpio = <0>,"+87+103", <&sx150x_1_70_pins>,"brcm,pins:0", <&sx1509_1_70>,"interrupts:0"; + sx1509-0-71-int-gpio = <0>,"+88+104", <&sx150x_0_71_pins>,"brcm,pins:0", <&sx1509_0_71>,"interrupts:0"; + sx1509-1-71-int-gpio = <0>,"+89+105", <&sx150x_1_71_pins>,"brcm,pins:0", <&sx1509_1_71>,"interrupts:0"; + }; +}; + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/tc358743-audio-overlay.dts linux/arch/arm/boot/dts/overlays/tc358743-audio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/tc358743-audio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/tc358743-audio-overlay.dts 2023-12-13 11:50:48.628961341 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions to add I2S audio from the Toshiba TC358743 HDMI to CSI2 bridge. +// Requires tc358743 overlay to have been loaded to actually function. +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + tc358743_codec: tc358743-codec { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dir"; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + sound_overlay: __overlay__ { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "tc358743"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + status = "okay"; + + simple-audio-card,cpu { + sound-dai = <&i2s_clk_consumer>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + dailink0_master: simple-audio-card,codec { + sound-dai = <&tc358743_codec>; + }; + }; + }; + + __overrides__ { + card-name = <&sound_overlay>,"simple-audio-card,name"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/tc358743-overlay.dts linux/arch/arm/boot/dts/overlays/tc358743-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/tc358743-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/tc358743-overlay.dts 2023-12-13 11:50:48.628961341 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for Toshiba TC358743 HDMI to CSI2 bridge on VC I2C bus +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + i2c_frag: fragment@0 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + tc358743: tc358743@f { + compatible = "toshiba,tc358743"; + reg = <0x0f>; + status = "okay"; + + clocks = <&cam1_clk>; + clock-names = "refclk"; + + port { + tc358743_0: endpoint { + remote-endpoint = <&csi1_ep>; + clock-lanes = <0>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <486000000>; + }; + }; + }; + }; + }; + + csi_frag: fragment@1 { + target = <&csi1>; + csi: __overlay__ { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&tc358743_0>; + }; + }; + }; + }; + + fragment@2 { + target = <&tc358743_0>; + __overlay__ { + data-lanes = <1 2>; + }; + }; + + fragment@3 { + target = <&tc358743_0>; + __dormant__ { + data-lanes = <1 2 3 4>; + }; + }; + + fragment@4 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + clk_frag: fragment@6 { + target = <&cam1_clk>; + __overlay__ { + status = "okay"; + clock-frequency = <27000000>; + }; + }; + + fragment@7 { + target = <&csi1_ep>; + __overlay__ { + data-lanes = <1 2>; + }; + }; + + fragment@8 { + target = <&csi1_ep>; + __dormant__ { + data-lanes = <1 2 3 4>; + }; + }; + + __overrides__ { + 4lane = <0>, "-2+3-7+8"; + link-frequency = <&tc358743_0>,"link-frequencies#0"; + media-controller = <&csi>,"brcm,media-controller?"; + cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <&tc358743>, "clocks:0=",<&cam0_clk>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts linux/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts 2023-12-13 11:50:48.628961341 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * tinylcd35-overlay.dts + * + * ------------------------------------------------- + * www.tinlylcd.com + * ------------------------------------------------- + * Device---Driver-----BUS GPIO's + * display tinylcd35 spi0.0 25 24 18 + * touch ads7846 spi0.1 5 + * rtc ds1307 i2c1-0068 + * rtc pcf8563 i2c1-0051 + * keypad gpio-keys --------- 17 22 27 23 28 + * + * + * TinyLCD.com 3.5 inch TFT + * + * Version 001 + * 5/3/2015 -- Noralf Trønnes Initial Device tree framework + * 10/3/2015 -- tinylcd@gmail.com added ds1307 support. + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + tinylcd35_pins: tinylcd35_pins { + brcm,pins = <25 24 18>; + brcm,function = <1>; /* out */ + }; + tinylcd35_ts_pins: tinylcd35_ts_pins { + brcm,pins = <5>; + brcm,function = <0>; /* in */ + }; + keypad_pins: keypad_pins { + brcm,pins = <4 17 22 23 27>; + brcm,function = <0>; /* in */ + brcm,pull = <1>; /* down */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + tinylcd35: tinylcd35@0{ + compatible = "neosec,tinylcd"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&tinylcd35_pins>, + <&tinylcd35_ts_pins>; + + spi-max-frequency = <48000000>; + rotate = <270>; + fps = <20>; + bgr; + buswidth = <8>; + reset-gpios = <&gpio 25 1>; + dc-gpios = <&gpio 24 0>; + led-gpios = <&gpio 18 0>; + debug = <0>; + + init = <0x10000B0 0x80 + 0x10000C0 0x0A 0x0A + 0x10000C1 0x01 0x01 + 0x10000C2 0x33 + 0x10000C5 0x00 0x42 0x80 + 0x10000B1 0xD0 0x11 + 0x10000B4 0x02 + 0x10000B6 0x00 0x22 0x3B + 0x10000B7 0x07 + 0x1000036 0x58 + 0x10000F0 0x36 0xA5 0xD3 + 0x10000E5 0x80 + 0x10000E5 0x01 + 0x10000B3 0x00 + 0x10000E5 0x00 + 0x10000F0 0x36 0xA5 0x53 + 0x10000E0 0x00 0x35 0x33 0x00 0x00 0x00 0x00 0x35 0x33 0x00 0x00 0x00 + 0x100003A 0x55 + 0x1000011 + 0x2000001 + 0x1000029>; + }; + + tinylcd35_ts: tinylcd35_ts@1 { + compatible = "ti,ads7846"; + reg = <1>; + status = "disabled"; + + spi-max-frequency = <2000000>; + interrupts = <5 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; + pendown-gpio = <&gpio 5 0>; + ti,x-plate-ohms = /bits/ 16 <100>; + ti,pressure-max = /bits/ 16 <255>; + }; + }; + }; + + /* RTC */ + + fragment@5 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + pcf8563: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + status = "okay"; + }; + }; + }; + + fragment@6 { + target = <&i2c1>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + ds1307: ds1307@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + status = "okay"; + }; + }; + }; + + /* + * Values for input event code is found under the + * 'Keys and buttons' heading in include/uapi/linux/input.h + */ + fragment@7 { + target-path = "/soc"; + __overlay__ { + keypad: keypad { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&keypad_pins>; + status = "disabled"; + autorepeat; + + button@17 { + label = "GPIO KEY_UP"; + linux,code = <103>; + gpios = <&gpio 17 0>; + }; + button@22 { + label = "GPIO KEY_DOWN"; + linux,code = <108>; + gpios = <&gpio 22 0>; + }; + button@27 { + label = "GPIO KEY_LEFT"; + linux,code = <105>; + gpios = <&gpio 27 0>; + }; + button@23 { + label = "GPIO KEY_RIGHT"; + linux,code = <106>; + gpios = <&gpio 23 0>; + }; + button@4 { + label = "GPIO KEY_ENTER"; + linux,code = <28>; + gpios = <&gpio 4 0>; + }; + }; + }; + }; + + __overrides__ { + speed = <&tinylcd35>,"spi-max-frequency:0"; + rotate = <&tinylcd35>,"rotate:0"; + fps = <&tinylcd35>,"fps:0"; + debug = <&tinylcd35>,"debug:0"; + touch = <&tinylcd35_ts>,"status"; + touchgpio = <&tinylcd35_ts_pins>,"brcm,pins:0", + <&tinylcd35_ts>,"interrupts:0", + <&tinylcd35_ts>,"pendown-gpio:4"; + xohms = <&tinylcd35_ts>,"ti,x-plate-ohms;0"; + rtc-pcf = <0>,"=5"; + rtc-ds = <0>,"=6"; + keypad = <&keypad>,"status"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/tpm-slb9670-overlay.dts linux/arch/arm/boot/dts/overlays/tpm-slb9670-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/tpm-slb9670-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/tpm-slb9670-overlay.dts 2023-12-13 11:50:48.628961341 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for the Infineon SLB9670 Trusted Platform Module add-on + * boards, which can be used as a secure key storage and hwrng. + * available as "Iridium SLB9670" by Infineon and "LetsTrust TPM" by pi3g. + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + slb9670: slb9670@1 { + compatible = "infineon,slb9670"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <32000000>; + status = "okay"; + }; + + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/tpm-slb9673-overlay.dts linux/arch/arm/boot/dts/overlays/tpm-slb9673-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/tpm-slb9673-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/tpm-slb9673-overlay.dts 2023-12-13 11:50:48.628961341 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for the Infineon SLB9673 Trusted Platform Module add-on + * boards, which can be used as a secure key storage and hwrng. + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + /* Due to issue https://github.com/raspberrypi/linux/issues/4884 the + hardware I2C needs to be disabled and software I2C enabled */ + fragment@0 { + target = <&i2c_arm>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + i2c1: i2c-gpio@1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + gpios = <&gpio 2 6>, /* SDA GPIO_OPEN_DRAIN */ + <&gpio 3 6>; /* CLK GPIO_OPEN_DRAIN */ + clock-frequency = <400000>; + status = "okay"; + }; + }; + }; + + /* Add the TPM */ + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slb9673: slb9673@2e { + compatible = "infineon,slb9673", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + status = "okay"; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/uart0-overlay.dts linux/arch/arm/boot/dts/overlays/uart0-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/uart0-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/uart0-overlay.dts 2023-12-13 11:50:48.628961341 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&uart0>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + uart0_pins: uart0_ovl_pins { + brcm,pins = <14 15>; + brcm,function = <4>; /* alt0 */ + brcm,pull = <0 2>; + }; + }; + }; + + __overrides__ { + txd0_pin = <&uart0_pins>,"brcm,pins:0"; + rxd0_pin = <&uart0_pins>,"brcm,pins:4"; + pin_func = <&uart0_pins>,"brcm,function:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/uart0-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/uart0-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/uart0-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/uart0-pi5-overlay.dts 2023-12-13 11:50:48.628961341 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&uart0>; + frag0: __overlay__ { + status = "okay"; + pinctrl-0 = <&uart0_pins>; + }; + }; + + __overrides__ { + ctsrts = <&frag0>,"pinctrl-0:4=",<&uart0_ctsrts_pins>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/uart1-overlay.dts linux/arch/arm/boot/dts/overlays/uart1-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/uart1-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/uart1-overlay.dts 2023-12-13 11:50:48.629961343 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&uart1>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + uart1_pins: uart1_ovl_pins { + brcm,pins = <14 15>; + brcm,function = <2>; /* alt5 */ + brcm,pull = <0 2>; + }; + }; + }; + + fragment@2 { + target-path = "/chosen"; + __overlay__ { + bootargs = "8250.nr_uarts=1"; + }; + }; + + __overrides__ { + txd1_pin = <&uart1_pins>,"brcm,pins:0"; + rxd1_pin = <&uart1_pins>,"brcm,pins:4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/uart1-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/uart1-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/uart1-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/uart1-pi5-overlay.dts 2023-12-13 11:50:48.629961343 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&uart1>; + frag0: __overlay__ { + status = "okay"; + pinctrl-0 = <&uart1_pins>; + }; + }; + + __overrides__ { + ctsrts = <&frag0>,"pinctrl-0:4=",<&uart1_ctsrts_pins>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/uart2-overlay.dts linux/arch/arm/boot/dts/overlays/uart2-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/uart2-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/uart2-overlay.dts 2023-12-13 11:50:48.629961343 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&uart2>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&uart2_pins>; + __dormant__ { + brcm,pins = <0 1 2 3>; + brcm,pull = <0 2 2 0>; + }; + }; + + __overrides__ { + ctsrts = <0>,"=1"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/uart2-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/uart2-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/uart2-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/uart2-pi5-overlay.dts 2023-12-13 11:50:48.629961343 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&uart2>; + frag0: __overlay__ { + status = "okay"; + pinctrl-0 = <&uart2_pins>; + }; + }; + + __overrides__ { + ctsrts = <&frag0>,"pinctrl-0:4=",<&uart2_ctsrts_pins>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/uart3-overlay.dts linux/arch/arm/boot/dts/overlays/uart3-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/uart3-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/uart3-overlay.dts 2023-12-13 11:50:48.629961343 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&uart3>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&uart3_pins>; + __dormant__ { + brcm,pins = <4 5 6 7>; + brcm,pull = <0 2 2 0>; + }; + }; + + __overrides__ { + ctsrts = <0>,"=1"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/uart3-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/uart3-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/uart3-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/uart3-pi5-overlay.dts 2023-12-13 11:50:48.629961343 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&uart3>; + frag0: __overlay__ { + status = "okay"; + pinctrl-0 = <&uart3_pins>; + }; + }; + + __overrides__ { + ctsrts = <&frag0>,"pinctrl-0:4=",<&uart3_ctsrts_pins>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/uart4-overlay.dts linux/arch/arm/boot/dts/overlays/uart4-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/uart4-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/uart4-overlay.dts 2023-12-13 11:50:48.629961343 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&uart4>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&uart4_pins>; + __dormant__ { + brcm,pins = <8 9 10 11>; + brcm,pull = <0 2 2 0>; + }; + }; + + __overrides__ { + ctsrts = <0>,"=1"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/uart4-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/uart4-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/uart4-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/uart4-pi5-overlay.dts 2023-12-13 11:50:48.630961346 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2712"; + + fragment@0 { + target = <&uart4>; + frag0: __overlay__ { + status = "okay"; + pinctrl-0 = <&uart4_pins>; + }; + }; + + __overrides__ { + ctsrts = <&frag0>,"pinctrl-0:4=",<&uart4_ctsrts_pins>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/uart5-overlay.dts linux/arch/arm/boot/dts/overlays/uart5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/uart5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/uart5-overlay.dts 2023-12-13 11:50:48.630961346 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2711"; + + fragment@0 { + target = <&uart5>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&uart5_pins>; + __dormant__ { + brcm,pins = <12 13 14 15>; + brcm,pull = <0 2 2 0>; + }; + }; + + __overrides__ { + ctsrts = <0>,"=1"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/udrc-overlay.dts linux/arch/arm/boot/dts/overlays/udrc-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/udrc-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/udrc-overlay.dts 2023-12-13 11:50:48.630961346 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +#include <dt-bindings/clock/bcm2835.h> +/* + * Device tree overlay for the Universal Digital Radio Controller + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + clocks = <&clocks BCM2835_CLOCK_PCM>; + clock-names = "pcm"; + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + udrc0_ldoin: udrc0_ldoin { + compatible = "regulator-fixed"; + regulator-name = "ldoin"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + clocks = <&clocks BCM2835_CLOCK_VPU>; + clock-frequency = <400000>; + + tlv320aic32x4: tlv320aic32x4@18 { + compatible = "ti,tlv320aic32x4"; + #sound-dai-cells = <0>; + reg = <0x18>; + status = "okay"; + + clocks = <&clocks BCM2835_CLOCK_GP0>; + clock-names = "mclk"; + assigned-clocks = <&clocks BCM2835_CLOCK_GP0>; + assigned-clock-rates = <25000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gpclk0_pin &aic3204_reset>; + + reset-gpios = <&gpio 13 0>; + + iov-supply = <&udrc0_ldoin>; + ldoin-supply = <&udrc0_ldoin>; + }; + }; + }; + + fragment@3 { + target = <&sound>; + snd: __overlay__ { + compatible = "simple-audio-card"; + i2s-controller = <&i2s_clk_producer>; + status = "okay"; + + simple-audio-card,name = "udrc"; + simple-audio-card,format = "i2s"; + + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out"; + + simple-audio-card,routing = + "IN1_R", "Line In", + "IN1_L", "Line In", + "CM_L", "Line In", + "CM_R", "Line In", + "Line Out", "LOR", + "Line Out", "LOL"; + + dailink0_master: simple-audio-card,cpu { + sound-dai = <&i2s_clk_producer>; + }; + + simple-audio-card,codec { + sound-dai = <&tlv320aic32x4>; + }; + }; + }; + + fragment@4 { + target = <&gpio>; + __overlay__ { + gpclk0_pin: gpclk0_pin { + brcm,pins = <4>; + brcm,function = <4>; + }; + + aic3204_reset: aic3204_reset { + brcm,pins = <13>; + brcm,function = <1>; + brcm,pull = <1>; + }; + + aic3204_gpio: aic3204_gpio { + brcm,pins = <26>; + }; + }; + }; + + __overrides__ { + alsaname = <&snd>, "simple-audio-card,name"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/ugreen-dabboard-overlay.dts linux/arch/arm/boot/dts/overlays/ugreen-dabboard-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/ugreen-dabboard-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/ugreen-dabboard-overlay.dts 2023-12-13 11:50:48.630961346 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for the ugreen dabboard I2S +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + dmic_codec: dmic-codec { + #sound-dai-cells = <0>; + compatible = "dmic-codec"; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&sound>; + sound_overlay: __overlay__ { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "dabboard"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + simple-audio-card,widgets = "Microphone", "Microphone Jack"; + status = "okay"; + simple-audio-card,cpu { + sound-dai = <&i2s_clk_consumer>; + }; + dailink0_master: simple-audio-card,codec { + #sound-dai-cells = <0>; + sound-dai = <&dmic_codec>; + }; + }; + }; + + __overrides__ { + card-name = <&sound_overlay>,"simple-audio-card,name"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/upstream-overlay.dts linux/arch/arm/boot/dts/overlays/upstream-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/upstream-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/upstream-overlay.dts 2023-12-13 11:50:48.630961346 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// redo: ovmerge -c vc4-kms-v3d-overlay.dts,cma-default,composite dwc2-overlay.dts,dr_mode=otg + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/bcm2835.h> + +/ { + compatible = "brcm,bcm2835"; + fragment@0 { + target = <&i2c2>; + __overlay__ { + status = "okay"; + }; + }; + fragment@1 { + target = <&fb>; + __overlay__ { + status = "disabled"; + }; + }; + fragment@2 { + target = <&pixelvalve0>; + __overlay__ { + status = "okay"; + }; + }; + fragment@3 { + target = <&pixelvalve1>; + __overlay__ { + status = "okay"; + }; + }; + fragment@4 { + target = <&pixelvalve2>; + __overlay__ { + status = "okay"; + }; + }; + fragment@5 { + target = <&hvs>; + __overlay__ { + status = "okay"; + }; + }; + fragment@6 { + target = <&hdmi>; + __overlay__ { + status = "okay"; + }; + }; + fragment@7 { + target = <&v3d>; + __overlay__ { + status = "okay"; + }; + }; + fragment@8 { + target = <&vc4>; + __overlay__ { + status = "okay"; + }; + }; + fragment@9 { + target = <&clocks>; + __overlay__ { + claim-clocks = <BCM2835_PLLD_DSI0 BCM2835_PLLD_DSI1 BCM2835_PLLH_AUX BCM2835_PLLH_PIX>; + }; + }; + fragment@10 { + target = <&vec>; + __overlay__ { + status = "okay"; + }; + }; + fragment@11 { + target = <&txp>; + __overlay__ { + status = "okay"; + }; + }; + fragment@12 { + target = <&chosen>; + __overlay__ { + bootargs = "snd_bcm2835.enable_hdmi=0"; + }; + }; + fragment@13 { + target = <&usb>; + #address-cells = <1>; + #size-cells = <1>; + __overlay__ { + compatible = "brcm,bcm2835-usb"; + dr_mode = "otg"; + g-np-tx-fifo-size = <32>; + g-rx-fifo-size = <558>; + g-tx-fifo-size = <512 512 512 512 512 256 256>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts linux/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts 2023-12-13 11:50:48.630961346 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// redo: ovmerge -c vc4-kms-v3d-pi4-overlay.dts,cma-default dwc2-overlay.dts,dr_mode=otg + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/bcm2835.h> + +/ { + compatible = "brcm,bcm2711"; + fragment@0 { + target = <&ddc0>; + __overlay__ { + status = "okay"; + }; + }; + fragment@1 { + target = <&ddc1>; + __overlay__ { + status = "okay"; + }; + }; + fragment@2 { + target = <&hdmi0>; + __overlay__ { + status = "okay"; + }; + }; + fragment@3 { + target = <&hdmi1>; + __overlay__ { + status = "okay"; + }; + }; + fragment@4 { + target = <&hvs>; + __overlay__ { + status = "okay"; + }; + }; + fragment@5 { + target = <&pixelvalve0>; + __overlay__ { + status = "okay"; + }; + }; + fragment@6 { + target = <&pixelvalve1>; + __overlay__ { + status = "okay"; + }; + }; + fragment@7 { + target = <&pixelvalve2>; + __overlay__ { + status = "okay"; + }; + }; + fragment@8 { + target = <&pixelvalve3>; + __overlay__ { + status = "okay"; + }; + }; + fragment@9 { + target = <&pixelvalve4>; + __overlay__ { + status = "okay"; + }; + }; + fragment@10 { + target = <&v3d>; + __overlay__ { + status = "okay"; + }; + }; + fragment@11 { + target = <&vc4>; + __overlay__ { + status = "okay"; + }; + }; + fragment@12 { + target = <&txp>; + __overlay__ { + status = "okay"; + }; + }; + fragment@13 { + target = <&fb>; + __overlay__ { + status = "disabled"; + }; + }; + fragment@14 { + target = <&firmwarekms>; + __overlay__ { + status = "disabled"; + }; + }; + fragment@15 { + target = <&vec>; + __overlay__ { + status = "disabled"; + }; + }; + fragment@16 { + target-path = "/chosen"; + __overlay__ { + bootargs = "snd_bcm2835.enable_hdmi=0"; + }; + }; + fragment@17 { + target = <&dvp>; + __overlay__ { + status = "okay"; + }; + }; + fragment@18 { + target = <&aon_intr>; + __overlay__ { + status = "okay"; + }; + }; + fragment@19 { + target = <&usb>; + #address-cells = <1>; + #size-cells = <1>; + __overlay__ { + compatible = "brcm,bcm2835-usb"; + dr_mode = "otg"; + g-np-tx-fifo-size = <32>; + g-rx-fifo-size = <558>; + g-tx-fifo-size = <512 512 512 512 512 256 256>; + status = "okay"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts 2023-12-13 11:50:48.630961346 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * vc4-fkms-v3d-overlay.dts + */ + +/dts-v1/; +/plugin/; + +#include "cma-overlay.dts" + +/ { + compatible = "brcm,bcm2835"; + + fragment@1 { + target = <&fb>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&firmwarekms>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&v3d>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&vc4>; + __overlay__ { + status = "okay"; + }; + }; + fragment@5 { + target-path = "/chosen"; + __overlay__ { + bootargs = "clk_ignore_unused"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-fkms-v3d-pi4-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-fkms-v3d-pi4-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-fkms-v3d-pi4-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-fkms-v3d-pi4-overlay.dts 2023-12-13 11:50:48.631961348 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * vc4-fkms-v3d-overlay.dts + */ + +/dts-v1/; +/plugin/; + +#include "cma-overlay.dts" + +&frag0 { + size = <((512-4)*1024*1024)>; +}; + +/ { + compatible = "brcm,bcm2711"; + + fragment@1 { + target = <&fb>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&firmwarekms>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&v3d>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&vc4>; + __overlay__ { + status = "okay"; + }; + }; + fragment@5 { + target-path = "/chosen"; + __overlay__ { + bootargs = "clk_ignore_unused"; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dpi.dtsi linux/arch/arm/boot/dts/overlays/vc4-kms-dpi.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dpi.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-dpi.dtsi 2023-12-13 11:50:48.632961351 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * vc4-kms-dpi.dtsi + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/bcm2835.h> + +/ { + fragment@100 { + target-path = "/"; + __overlay__ { + panel: panel { + rotation = <0>; + port { + panel_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + }; + }; + + fragment@101 { + target = <&dpi>; + dpi_node: __overlay__ { + status = "okay"; + + pinctrl-names = "default"; + + port { + dpi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + fragment@102 { + target = <&panel>; + __dormant__ { + backlight = <&backlight>; + }; + }; + + fragment@103 { + target-path = "/"; + __dormant__ { + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpio 255 GPIO_ACTIVE_HIGH>; + }; + }; + }; + + fragment@104 { + target = <&panel>; + __dormant__ { + backlight = <&backlight_pwm>; + }; + }; + + fragment@105 { + target-path = "/"; + __dormant__ { + backlight_pwm: backlight_pwm { + compatible = "pwm-backlight"; + brightness-levels = <0 6 8 12 16 24 32 40 48 64 96 128 160 192 224 255>; + default-brightness-level = <16>; + pwms = <&pwm 0 200000>; + }; + }; + }; + + fragment@106 { + target = <&pwm>; + __dormant__ { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + assigned-clock-rates = <1000000>; + status = "okay"; + }; + }; + + fragment@107 { + target = <&gpio>; + __dormant__ { + pwm_pins: pwm_pins { + brcm,pins = <18>; + brcm,function = <2>; /* Alt5 */ + }; + }; + }; + + fragment@108 { + target = <&chosen>; + __dormant__ { + bootargs = "snd_bcm2835.enable_headphones=0"; + }; + }; + + __overrides__ { + backlight-gpio = <0>, "+102+103", + <&backlight>, "gpios:4"; + backlight-pwm = <0>, "+104+105+106+107+108"; + backlight-pwm-chan = <&backlight_pwm>, "pwms:4"; + backlight-pwm-gpio = <&pwm_pins>, "brcm,pins:0"; + backlight-pwm-func = <&pwm_pins>, "brcm,function:0"; + backlight-def-brightness = <&backlight_pwm>, "default-brightness-level:0"; + rotate = <&panel>, "rotation:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dpi-generic-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-kms-dpi-generic-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dpi-generic-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-dpi-generic-overlay.dts 2023-12-13 11:50:48.631961348 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * vc4-kms-dpi-generic-overlay.dts + */ + +/dts-v1/; +/plugin/; + +#include "vc4-kms-dpi.dtsi" + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&panel>; + panel_generic: __overlay__ { + compatible = "panel-dpi"; + + width-mm = <154>; + height-mm = <83>; + bus-format = <0x1009>; + + timing: panel-timing { + clock-frequency = <29500000>; + hactive = <800>; + hfront-porch = <24>; + hsync-len = <72>; + hback-porch = <96>; + hsync-active = <1>; + vactive = <480>; + vfront-porch = <3>; + vsync-len = <10>; + vback-porch = <7>; + vsync-active = <1>; + + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + + fragment@1 { + target = <&dpi>; + dpi_node_generic: __overlay__ { + pinctrl-0 = <&dpi_18bit_gpio0>; + }; + }; + + __overrides__ { + clock-frequency = <&timing>, "clock-frequency:0"; + hactive = <&timing>, "hactive:0"; + hfp = <&timing>, "hfront-porch:0"; + hsync = <&timing>, "hsync-len:0"; + hbp = <&timing>, "hback-porch:0"; + vactive = <&timing>, "vactive:0"; + vfp = <&timing>, "vfront-porch:0"; + vsync = <&timing>, "vsync-len:0"; + vbp = <&timing>, "vback-porch:0"; + hsync-invert = <&timing>, "hsync-active:0=0"; + vsync-invert = <&timing>, "vsync-active:0=0"; + de-invert = <&timing>, "de-active:0=0"; + pixclk-invert = <&timing>, "pixelclk-active:0=0"; + + width-mm = <&panel>, "width-mm:0"; + height-mm = <&panel>, "height-mm:0"; + + rgb565 = <&panel_generic>, "bus-format:0=0x1017", + <&dpi_node_generic>, "pinctrl-0:0=",<&dpi_16bit_gpio0>; + rgb565-padhi = <&panel_generic>, "bus-format:0=0x1022", + <&dpi_node_generic>, "pinctrl-0:0=",<&dpi_16bit_cpadhi_gpio0>; + bgr666 = <&panel_generic>, "bus-format:0=0x1023"; + bgr666-padhi = <&panel_generic>, "bus-format:0=0x1024", + <&dpi_node_generic>, "pinctrl-0:0=",<&dpi_18bit_cpadhi_gpio0>; + rgb666-padhi = <&panel_generic>, "bus-format:0=0x1015", + <&dpi_node_generic>, "pinctrl-0:0=",<&dpi_18bit_cpadhi_gpio0>; + bgr888 = <&panel_generic>, "bus-format:0=0x1013", + <&dpi_node_generic>, "pinctrl-0:0=",<&dpi_gpio0>; + rgb888 = <&panel_generic>, "bus-format:0=0x100a", + <&dpi_node_generic>, "pinctrl-0:0=",<&dpi_gpio0>; + bus-format = <&panel_generic>, "bus-format:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel2r-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel2r-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel2r-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel2r-overlay.dts 2023-12-13 11:50:48.631961348 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * vc4-kms-dpi-hyperpixel2r-overlay.dts + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/bcm2835.h> + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + sck-gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + panel: display@0 { + compatible = "pimoroni,hyperpixel2round"; + reg = <0>; + /* 100 kHz */ + spi-max-frequency = <100000>; + backlight = <&backlight>; + rotation = <0>; + + port { + panel_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpio 19 0>; + }; + }; + }; + + fragment@1 { + target = <&dpi>; + __overlay__ { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dpi_18bit_cpadhi_gpio0>; + + port { + dpi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + spi_pins: hyperpixel4_spi_pins { + brcm,pins = <27 18 26>; + brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_UP BCM2835_PUD_OFF>; + brcm,function = <0>; + }; + }; + }; + + fragment@3 { + target-path = "/"; + __overlay__ { + i2c_gpio: i2c@0 { + compatible = "i2c-gpio"; + status = "disabled"; + + gpios = <&gpio 10 GPIO_ACTIVE_HIGH /* sda */ + &gpio 11 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,delay-us = <4>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + + polytouch: edt-ft5x06@15 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "edt,edt-ft5406"; + reg = <0x15>; + interrupt-parent = <&gpio>; + interrupts = <27 0x02>; + touchscreen-size-x = <240>; + touchscreen-size-y = <240>; + }; + }; + }; + }; + + __overrides__ { + disable-touch = <0>,"-3"; + touchscreen-inverted-x = <&polytouch>,"touchscreen-inverted-x?"; + touchscreen-inverted-y = <&polytouch>,"touchscreen-inverted-y!"; + touchscreen-swapped-x-y = <&polytouch>,"touchscreen-swapped-x-y!"; + rotate = <&panel>, "rotation:0"; + }; + +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4-overlay.dts 2023-12-13 11:50:48.631961348 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * vc4-kms-dpi-hyperpixel4sq-overlay.dts + */ + +/dts-v1/; +/plugin/; + +#include "vc4-kms-dpi-hyperpixel.dtsi" + +&panel { + compatible = "pimoroni,hyperpixel4"; +}; + +/ { + fragment@11 { + target = <&i2c_gpio>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + ft6236_14: ft6236@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&gpio>; + interrupts = <27 2>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + touchscreen-x-mm = <51>; + touchscreen-y-mm = <85>; + touchscreen-inverted-y; + touchscreen-swapped-x-y; + }; + ft6236_5d: ft6236@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&gpio>; + interrupts = <27 2>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + touchscreen-x-mm = <51>; + touchscreen-y-mm = <85>; + touchscreen-inverted-y; + touchscreen-swapped-x-y; + }; + }; + }; + + __overrides__ { + disable-touch = <0>,"-3-11"; + touchscreen-inverted-x = <&ft6236_14>,"touchscreen-inverted-x?", + <&ft6236_5d>,"touchscreen-inverted-x?"; + touchscreen-inverted-y = <&ft6236_14>,"touchscreen-inverted-y!", + <&ft6236_5d>,"touchscreen-inverted-y!"; + touchscreen-swapped-x-y = <&ft6236_14>,"touchscreen-swapped-x-y!", + <&ft6236_5d>,"touchscreen-swapped-x-y!"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4sq-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4sq-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4sq-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4sq-overlay.dts 2023-12-13 11:50:48.631961348 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * vc4-kms-dpi-hyperpixel4-overlay.dts + */ + +/dts-v1/; +/plugin/; + +#include "vc4-kms-dpi-hyperpixel.dtsi" + +&panel { + compatible = "pimoroni,hyperpixel4square"; +}; + +/ { + fragment@11 { + target = <&i2c_gpio>; + __overlay__ { + polytouch: edt-ft5x06@48 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "edt,edt-ft5406"; + reg = <0x48>; + interrupt-parent = <&gpio>; + interrupts = <27 0x02>; + touchscreen-size-x = <720>; + touchscreen-size-y = <720>; + }; + }; + }; + __overrides__ { + disable-touch = <0>,"-3-11"; + touchscreen-inverted-x = <&polytouch>,"touchscreen-inverted-x?"; + touchscreen-inverted-y = <&polytouch>,"touchscreen-inverted-y!"; + touchscreen-swapped-x-y = <&polytouch>,"touchscreen-swapped-x-y!"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel.dtsi linux/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel.dtsi --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel.dtsi 2023-12-13 11:50:48.631961348 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * vc4-kms-dpi-hyperpixel4.dtsi + * Commmon initialisation for HyperPixel DPI displays + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/bcm2835.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + sck-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio 26 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + sck-idle-input; + + panel: display@0 { + reg = <0>; + /* 100 kHz */ + spi-max-frequency = <100000>; + backlight = <&backlight>; + rotation = <0>; + + port { + panel_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpio 19 0>; + }; + }; + }; + + fragment@1 { + target = <&dpi>; + __overlay__ { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dpi_18bit_cpadhi_gpio0>; + + port { + dpi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + fragment@2 { + target = <&gpio>; + __overlay__ { + spi_pins: hyperpixel4_spi_pins { + brcm,pins = <27 18 26>; + brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_UP BCM2835_PUD_OFF>; + brcm,function = <0>; + }; + }; + }; + + fragment@3 { + target-path = "/"; + __overlay__ { + i2c_gpio: i2c@0 { + compatible = "i2c-gpio"; + gpios = <&gpio 10 0 /* sda */ + &gpio 11 0>; /* scl */ + i2c-gpio,delay-us = <4>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + __overrides__ { + rotate = <&panel>, "rotation:0"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dpi-panel-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-kms-dpi-panel-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dpi-panel-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-dpi-panel-overlay.dts 2023-12-13 11:50:48.631961348 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * vc4-kms-dpi-panel-overlay.dts + * Support for any predefined DPI panel. + */ + +/dts-v1/; +/plugin/; + +#include "vc4-kms-dpi.dtsi" + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&panel>; + __dormant__ { + compatible = "innolux,at056tn53v1", "simple-panel"; + }; + }; + fragment@1 { + target = <&panel>; + __dormant__ { + compatible = "ontat,yx700wv03", "simple-panel"; + }; + }; + fragment@2 { + target = <&panel>; + __dormant__ { + compatible = "geekworm,mzp280", "simple-panel"; + }; + }; + + fragment@90 { + target = <&dpi>; + __dormant__ { + pinctrl-0 = <&dpi_18bit_cpadhi_gpio0>; + }; + }; + fragment@91 { + target = <&dpi>; + __dormant__ { + pinctrl-0 = <&dpi_18bit_gpio0>; + }; + }; + fragment@92 { + target = <&dpi>; + __dormant__ { + pinctrl-0 = <&dpi_gpio0>; + }; + }; + fragment@93 { + target = <&dpi>; + __dormant__ { + pinctrl-0 = <&dpi_16bit_cpadhi_gpio0>; + }; + }; + fragment@94 { + target = <&dpi>; + __dormant__ { + pinctrl-0 = <&dpi_16bit_gpio0>; + }; + }; + + __overrides__ { + at056tn53v1 = <0>, "+0+90"; + kippah-7inch = <0>, "+1+91"; + mzp280 = <0>, "+2+93"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dsi-7inch-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-kms-dsi-7inch-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dsi-7inch-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-dsi-7inch-overlay.dts 2023-12-13 11:50:48.632961351 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for RaspberryPi 7" Touchscreen panel + * + */ + +/dts-v1/; +/plugin/; + +#include "edt-ft5406.dtsi" + +/ { + /* No compatible as it will have come from edt-ft5406.dtsi */ + + dsi_frag: fragment@0 { + target = <&dsi1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + dsi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + bridge@0 { + reg = <0>; + compatible = "toshiba,tc358762"; + vddc-supply = <®_bridge>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + panel_disp: panel_disp@1 { + reg = <1>; + compatible = "raspberrypi,7inch-dsi", "simple-panel"; + backlight = <®_display>; + power-supply = <®_display>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; + + reg_bridge: reg_bridge@1 { + reg = <1>; + compatible = "regulator-fixed"; + regulator-name = "bridge_reg"; + gpio = <®_display 0 0>; + vin-supply = <®_display>; + enable-active-high; + }; + }; + }; + + i2c_frag: fragment@2 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + reg_display: reg_display@45 { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; + + fragment@3 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + fragment@5 { + target = <&ft5406>; + __overlay__ { + vcc-supply = <®_display>; + reset-gpio = <®_display 1 1>; + }; + }; + + __overrides__ { + dsi0 = <&dsi_frag>, "target:0=",<&dsi0>, + <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&ts_i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&panel_disp>, "reg:0=0", + <®_bridge>, "reg:0=0", + <®_bridge>, "regulator-name=bridge_reg_0"; + disable_touch = <&ft5406>, "status=disabled"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dsi-generic-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-kms-dsi-generic-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dsi-generic-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-dsi-generic-overlay.dts 2023-12-13 11:50:48.632961351 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + dsi_frag: fragment@0 { + target = <&dsi1>; + __overlay__{ + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + port { + dsi_out:endpoint { + remote-endpoint = <&panel_dsi_port>; + }; + }; + panel: panel-dsi-generic@0 { + // See panel-dsi.yaml binding + // Using dummy name for panel model + compatible = "Generic,panel-dsi","panel-dsi"; + reg = <0>; + power-supply = <0>; + backlight = <0>; + dsi-color-format = "RGB888"; + mode = "MODE_VIDEO"; + width-mm = <0>; + height-mm = <0>; + + port { + panel_dsi_port: endpoint { + data-lanes = <1>; + remote-endpoint = <&dsi_out>; + }; + }; + + timing: panel-timing { + clock-frequency = <30000000>; + hactive = <840>; + vactive = <480>; + hback-porch = <44>; + hfront-porch = <46>; + hsync-len = <2>; + vback-porch = <18>; + vfront-porch = <16>; + vsync-len = <2>; + }; + }; + }; + }; + + fragment@1 { + target = <&panel_dsi_port>; + __dormant__ { + data-lanes = <1>; + }; + }; + + fragment@2 { + target = <&panel_dsi_port>; + __dormant__ { + data-lanes = <1 2>; + }; + }; + + fragment@3 { + target = <&panel_dsi_port>; + __dormant__ { + data-lanes = <1 2 3>; + }; + }; + + fragment@4 { + target = <&panel_dsi_port>; + __dormant__ { + data-lanes = <1 2 3 4>; + }; + }; + + __overrides__ { + dsi0 = <&dsi_frag>, "target:0=",<&dsi0>; + + clock-frequency = <&timing>, "clock-frequency:0"; + hactive = <&timing>, "hactive:0"; + hfp = <&timing>, "hfront-porch:0"; + hsync = <&timing>, "hsync-len:0"; + hbp = <&timing>, "hback-porch:0"; + vactive = <&timing>, "vactive:0"; + vfp = <&timing>, "vfront-porch:0"; + vsync = <&timing>, "vsync-len:0"; + vbp = <&timing>, "vback-porch:0"; + + width-mm = <&panel>, "width-mm:0"; + height-mm = <&panel>, "height-mm:0"; + + rgb565 = <&panel>, "dsi-color-format=RGB565"; + rgb666p = <&panel>, "dsi-color-format=RGB666_PACKED"; + rgb666 = <&panel>, "dsi-color-format=RGB666"; + rgb888 = <&panel>, "dsi-color-format=RGB888"; + one-lane = <0>,"+1"; + two-lane = <0>,"+2"; + three-lane = <0>,"+3"; + four-lane = <0>,"+4"; + }; + +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-overlay.dts 2023-12-13 11:50:48.632961351 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay to connect a JDI LT070ME05000 DSI panel to DSI1. + * This uses 4 DSI data lanes, so can only be used with a Compute Module. + * + * Credit to forum user gizmomouse on + * https://www.raspberrypi.org/forums/viewtopic.php?f=98&t=253912 and + * Andrey Vostrukhin of Harlab for the overlay. + * + * Refer to https://github.com/harlab/CM4_LCD_LT070ME05000 for schematics and + * other documentation. + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&dsi1>; + __overlay__{ + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + port { + dsi_out_port:endpoint { + remote-endpoint = <&panel_dsi_port>; + }; + }; + + lt070me05000:lt070me05000@0 { + compatible = "jdi,lt070me05000"; + status = "okay"; + reg = <0>; + reset-gpios = <&gpio 17 1>; // LCD RST + enable-gpios = <&gpio 4 0>; // LCD Enable + dcdc-en-gpios = <&gpio 5 0>; // LCD DC-DC Enable + port { + panel_dsi_port: endpoint { + remote-endpoint = <&dsi_out_port>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + lt070me05000_pins: lt070me05000_pins { + brcm,pins = <4 5 17>; + brcm,function = <1 1 1>; // out + brcm,pull = <0 0 0>; // off + }; + }; + + }; + + __overrides__ { + reset = <<070me05000_pins>,"brcm,pins:8", + <<070me05000>,"reset-gpios:4"; + + enable = <<070me05000_pins>,"brcm,pins:0", + <<070me05000>,"enable-gpios:4"; + + dcdc-en = <<070me05000_pins>,"brcm,pins:4", + <<070me05000>,"dcdc-en-gpios:4"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-v2-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-v2-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-v2-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-v2-overlay.dts 2023-12-13 11:50:48.632961351 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay to connect a JDI LT070ME05000 DSI panel to DSI1. + * This uses 4 DSI data lanes, so can only be used with a Compute Module. + * + * The overlay is for V2 of Harlab's interface board that uses a PCA9536 to + * handle the panel's control GPIOs instead of wiring it back to Pi GPIOs. + * + * Credit to Andrey Vostrukhin of Harlab for the overlay. + * + * Refer to https://github.com/harlab/CM4_LCD_LT070ME05000 for schematics and + * other documentation. + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca: pca@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&dsi1>; + __overlay__{ + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + port { + dsi_out_port:endpoint { + remote-endpoint = <&panel_dsi_port>; + }; + }; + + lt070me05000:lt070me05000@0 { + compatible = "jdi,lt070me05000"; + status = "okay"; + reg = <0>; + reset-gpios = <&pca 0 1>; + enable-gpios = <&pca 2 0>; + dcdc-en-gpios = <&pca 1 0>; + port { + panel_dsi_port: endpoint { + remote-endpoint = <&dsi_out_port>; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dsi-waveshare-panel-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-kms-dsi-waveshare-panel-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-dsi-waveshare-panel-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-dsi-waveshare-panel-overlay.dts 2023-12-13 11:50:48.632961351 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for Waveshare DSI Touchscreens + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + dsi_frag: fragment@0 { + target = <&dsi1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + }; + }; + + i2c_frag: fragment@2 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel: panel_disp1@45 { + reg = <0x45>; + compatible = "waveshare,10.1inch-panel"; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + + touch: goodix@14 { + reg = <0x14>; + compatible = "goodix,gt911"; + }; + }; + }; + + fragment@3 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&i2c_arm>; + __dormant__ { + status = "okay"; + }; + }; + + __overrides__ { + 2_8_inch = <&panel>, "compatible=waveshare,2.8inch-panel", + <&touch>, "touchscreen-size-x:0=640", + <&touch>, "touchscreen-size-y:0=480", + <&touch>, "touchscreen-inverted-y?", + <&touch>, "touchscreen-swapped-x-y?"; + 3_4_inch = <&panel>, "compatible=waveshare,3.4inch-panel", + <&touch>, "touchscreen-size-x:0=800", + <&touch>, "touchscreen-size-y:0=800"; + 4_0_inch = <&panel>, "compatible=waveshare,4.0inch-panel", + <&touch>, "touchscreen-size-x:0=800", + <&touch>, "touchscreen-size-y:0=480", + <&touch>, "touchscreen-inverted-x?", + <&touch>, "touchscreen-swapped-x-y?"; + 7_0_inchC = <&panel>, "compatible=waveshare,7.0inch-c-panel", + <&touch>, "touchscreen-size-x:0=800", + <&touch>, "touchscreen-size-y:0=480"; + 7_9_inch = <&panel>, "compatible=waveshare,7.9inch-panel", + <&touch>, "touchscreen-size-x:0=4096", + <&touch>, "touchscreen-size-y:0=4096", + <&touch>, "touchscreen-inverted-x?", + <&touch>, "touchscreen-swapped-x-y?"; + 8_0_inch = <&panel>, "compatible=waveshare,8.0inch-panel", + <&touch>, "touchscreen-size-x:0=800", + <&touch>, "touchscreen-size-y:0=1280", + <&touch>, "touchscreen-inverted-x?", + <&touch>, "touchscreen-swapped-x-y?"; + 10_1_inch = <&panel>, "compatible=waveshare,10.1inch-panel", + <&touch>, "touchscreen-size-x:0=800", + <&touch>, "touchscreen-size-y:0=1280", + <&touch>, "touchscreen-inverted-x?", + <&touch>, "touchscreen-swapped-x-y?"; + 11_9_inch = <&panel>, "compatible=waveshare,11.9inch-panel", + <&touch>, "touchscreen-size-x:0=320", + <&touch>, "touchscreen-size-y:0=1480", + <&touch>, "touchscreen-inverted-x?", + <&touch>, "touchscreen-swapped-x-y?"; + i2c1 = <&i2c_frag>, "target:0=",<&i2c1>, + <0>, "-3-4+5"; + disable_touch = <&touch>, "status=disabled"; + rotation = <&panel>, "rotation:0"; + invx = <&touch>,"touchscreen-inverted-x?"; + invy = <&touch>,"touchscreen-inverted-y?"; + swapxy = <&touch>,"touchscreen-swapped-x-y?"; + dsi0 = <&dsi_frag>, "target:0=",<&dsi0>, + <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-kippah-7inch-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-kms-kippah-7inch-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-kippah-7inch-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-kippah-7inch-overlay.dts 2023-12-13 11:50:48.633961353 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * vc4-kms-kippah-7inch-overlay.dts + */ + +/dts-v1/; +/plugin/; + +#include "vc4-kms-dpi.dtsi" + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&panel>; + __overlay__ { + compatible = "ontat,yx700wv03", "simple-panel"; + }; + }; + + fragment@1 { + target = <&dpi>; + __overlay__ { + pinctrl-0 = <&dpi_18bit_gpio0>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts 2023-12-13 11:50:48.633961353 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * vc4-kms-v3d-overlay.dts + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/bcm2835.h> + +#include "cma-overlay.dts" + +/ { + compatible = "brcm,bcm2835"; + + fragment@1 { + target = <&i2c2>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&fb>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&pixelvalve0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&pixelvalve1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&pixelvalve2>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&hvs>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&hdmi>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&v3d>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&vc4>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&clocks>; + __overlay__ { + claim-clocks = < + BCM2835_PLLD_DSI0 + BCM2835_PLLD_DSI1 + BCM2835_PLLH_AUX + BCM2835_PLLH_PIX + >; + }; + }; + + fragment@11 { + target = <&vec>; + __dormant__ { + status = "okay"; + }; + }; + + fragment@12 { + target = <&txp>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@13 { + target = <&hdmi>; + __dormant__ { + dmas; + }; + }; + + fragment@14 { + target = <&chosen>; + __overlay__ { + bootargs = "snd_bcm2835.enable_hdmi=0"; + }; + }; + + __overrides__ { + audio = <0>,"!13"; + noaudio = <0>,"=13"; + composite = <0>, "=11"; + nohdmi = <0>, "-1-7"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts 2023-12-13 11:50:48.633961353 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * vc4-kms-v3d-pi4-overlay.dts + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/bcm2835.h> + +#include "cma-overlay.dts" + +&frag0 { + size = <((512-4)*1024*1024)>; +}; + +/ { + compatible = "brcm,bcm2711"; + + fragment@1 { + target = <&ddc0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@2 { + target = <&ddc1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&hdmi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&hdmi1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&hvs>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&pixelvalve0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&pixelvalve1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&pixelvalve2>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&pixelvalve3>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&pixelvalve4>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&v3d>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@12 { + target = <&vc4>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@13 { + target = <&txp>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@14 { + target = <&fb>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@15 { + target = <&firmwarekms>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@16 { + target = <&vec>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@17 { + target = <&hdmi0>; + __dormant__ { + dmas; + }; + }; + + fragment@18 { + target = <&hdmi1>; + __dormant__ { + dmas; + }; + }; + + fragment@19 { + target-path = "/chosen"; + __overlay__ { + bootargs = "snd_bcm2835.enable_hdmi=0"; + }; + }; + + fragment@20 { + target = <&dvp>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@21 { + target = <&pixelvalve3>; + __dormant__ { + status = "okay"; + }; + }; + + fragment@22 { + target = <&vec>; + __dormant__ { + status = "okay"; + }; + }; + + fragment@23 { + target = <&aon_intr>; + __overlay__ { + status = "okay"; + }; + }; + + __overrides__ { + audio = <0>,"!17"; + audio1 = <0>,"!18"; + noaudio = <0>,"=17", <0>,"=18"; + composite = <0>, "!1", + <0>, "!2", + <0>, "!3", + <0>, "!4", + <0>, "!6", + <0>, "!7", + <0>, "!8", + <0>, "!9", + <0>, "!10", + <0>, "!16", + <0>, "=21", + <0>, "=22"; + nohdmi0 = <0>, "-1-3-8"; + nohdmi1 = <0>, "-2-4-10"; + nohdmi = <0>, "-1-2-3-4-8-10"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi5-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi5-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi5-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi5-overlay.dts 2023-12-13 11:50:48.633961353 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 + +#include "cma-overlay.dts" + +&frag0 { + size = <((320-4)*1024*1024)>; +}; + +/ { + compatible = "brcm,bcm2712"; + + fragment@1 { + target = <&fb>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&aon_intr>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&ddc0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&ddc1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&hdmi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&hdmi1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&hvs>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&mop>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&moplet>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&pixelvalve0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&pixelvalve1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@12 { + target = <&v3d>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@13 { + target = <&vec>; + frag13: __overlay__ { + status = "disabled"; + }; + }; + + fragment@14 { + target = <&hdmi0>; + __dormant__ { + dmas; + }; + }; + + fragment@15 { + target = <&hdmi1>; + __dormant__ { + dmas; + }; + }; + + fragment@16 { + target = <&disp_intr>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@17 { + target = <&vc4>; + __overlay__ { + /* IOMMU attaches here, where we allocate DMA buffers */ + iommus = <&iommu4>; + }; + }; + + __overrides__ { + audio = <0>,"!14"; + audio1 = <0>,"!15"; + noaudio = <0>,"=14", <0>,"=15"; + composite = <0>, "!3", + <0>, "!4", + <0>, "!5", + <0>, "!6", + <0>, "!10", + <0>, "!11", + <&frag13>, "status"; + nohdmi0 = <0>, "-3-5-10"; + nohdmi1 = <0>, "-4-6-11"; + nohdmi = <0>, "-3-4-5-6-10-11"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-vga666-overlay.dts linux/arch/arm/boot/dts/overlays/vc4-kms-vga666-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vc4-kms-vga666-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vc4-kms-vga666-overlay.dts 2023-12-13 11:50:48.633961353 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * vc4-kms-vga666-overlay.dts + * Configures a FenLogic or similar VGA666 DPI adapter when using the + * vc4-kms-v3d driver. + * If a suitable I2C level shifter is connected to GPIOs 0&1 and the VGA + * ID1/SDA (pin 12) and ID3/SCL (pin 15) lines, then there is the option to + * enable reading the EDID from the display. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/pinctrl/bcm2835.h> + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + vga_connector: vga_connector { + compatible = "vga-connector"; + label = "vga"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga666_out>; + }; + }; + }; + + vga_dac { + compatible = "dumb-vga-dac"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga666_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + vga666_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + }; + }; + + fragment@1 { + target = <&dpi>; + __overlay__ { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dpi_18bit_gpio2>; + + port { + dpi_out: endpoint@0 { + remote-endpoint = <&vga666_in>; + }; + }; + }; + }; + + fragment@2 { + target = <&vga_connector>; + __dormant__ { + ddc-i2c-bus = <&i2c_vc>; + }; + }; + + fragment@3 { + target = <&i2c0if>; + __dormant__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&i2c0mux>; + __dormant__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&i2c_vc>; + __dormant__ { + status = "okay"; + }; + }; + + __overrides__ { + ddc = <0>,"=2", <0>,"=3", <0>,"=4", <0>,"=5"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vga666-overlay.dts linux/arch/arm/boot/dts/overlays/vga666-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vga666-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vga666-overlay.dts 2023-12-13 11:50:48.633961353 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +/{ + compatible = "brcm,bcm2835"; + + // There is no VGA driver module, but we need a platform device + // node (that doesn't already use pinctrl) to hang the pinctrl + // reference on - leds will do + + fragment@0 { + target = <&leds>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&vga666_pins>; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + vga666_pins: vga666_pins { + brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 + 13 14 15 16 17 18 19 20 21>; + brcm,function = <6>; /* alt2 */ + brcm,pull = <0>; /* no pull */ + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/vl805-overlay.dts linux/arch/arm/boot/dts/overlays/vl805-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/vl805-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/vl805-overlay.dts 2023-12-13 11:50:48.633961353 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/dts-v1/; +/plugin/; + +#include <dt-bindings/reset/raspberrypi,firmware-reset.h> + +/ { + compatible = "brcm,bcm2711"; + + fragment@0 { + target-path = "pcie0/pci@0,0"; + __overlay__ { + usb@0,0 { + reg = <0 0 0 0 0>; + resets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts linux/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts 2023-12-13 11:50:48.633961353 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for w1-gpio module (without external pullup) +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + + w1: onewire@0 { + compatible = "w1-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&w1_pins>; + gpios = <&gpio 4 0>; + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + w1_pins: w1_pins@0 { + brcm,pins = <4>; + brcm,function = <0>; // in (initially) + brcm,pull = <0>; // off + }; + }; + }; + + __overrides__ { + gpiopin = <&w1>,"gpios:4", + <&w1>,"reg:0", + <&w1_pins>,"brcm,pins:0", + <&w1_pins>,"reg:0"; + pullup; // Silently ignore unneeded parameter + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts linux/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts 2023-12-13 11:50:48.634961355 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for w1-gpio module (with external pullup) +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target-path = "/"; + __overlay__ { + + w1: onewire@0 { + compatible = "w1-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&w1_pins>; + gpios = <&gpio 4 0>, <&gpio 5 1>; + status = "okay"; + }; + }; + }; + + fragment@1 { + target = <&gpio>; + __overlay__ { + w1_pins: w1_pins@0 { + brcm,pins = <4 5>; + brcm,function = <0 1>; // in out + brcm,pull = <0 0>; // off off + }; + }; + }; + + __overrides__ { + gpiopin = <&w1>,"gpios:4", + <&w1>,"reg:0", + <&w1_pins>,"brcm,pins:0", + <&w1_pins>,"reg:0"; + extpullup = <&w1>,"gpios:16", + <&w1_pins>,"brcm,pins:4"; + pullup; // Silently ignore unneeded parameter + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/w5500-overlay.dts linux/arch/arm/boot/dts/overlays/w5500-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/w5500-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/w5500-overlay.dts 2023-12-13 11:50:48.634961355 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Overlay for the Wiznet w5500 Ethernet Controller +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&spidev1>; + __dormant__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + eth1: w5500@0{ + compatible = "wiznet,w5500"; + reg = <0>; /* CE0 */ + pinctrl-names = "default"; + pinctrl-0 = <ð1_pins>; + interrupt-parent = <&gpio>; + interrupts = <25 0x8>; + spi-max-frequency = <30000000>; +// local-mac-address = [aa bb cc dd ee ff]; + status = "okay"; + }; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + eth1_pins: eth1_pins { + brcm,pins = <25>; + brcm,function = <0>; /* in */ + brcm,pull = <0>; /* none */ + }; + }; + }; + + __overrides__ { + int_pin = <ð1>, "interrupts:0", + <ð1_pins>, "brcm,pins:0"; + speed = <ð1>, "spi-max-frequency:0"; + cs = <ð1>, "reg:0", + <0>, "!0=1"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/watterott-display-overlay.dts linux/arch/arm/boot/dts/overlays/watterott-display-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/watterott-display-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/watterott-display-overlay.dts 2023-12-13 11:50:48.634961355 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for rpi-display by Watterott + * + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@3 { + target = <&gpio>; + __overlay__ { + rpi_display_pins: rpi_display_pins { + brcm,pins = <18 23 24 25>; + brcm,function = <1 1 1 0>; /* out out out in */ + brcm,pull = <0 0 0 2>; /* - - - up */ + }; + }; + }; + + fragment@4 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; + + rpidisplay: rpi-display@0{ + compatible = "ilitek,ili9341"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_display_pins>; + + spi-max-frequency = <32000000>; + rotate = <270>; + bgr; + fps = <30>; + buswidth = <8>; + reset-gpios = <&gpio 23 1>; + dc-gpios = <&gpio 24 0>; + led-gpios = <&gpio 18 0>; + debug = <0>; + }; + + rpidisplay_ts: rpi-display-ts@1 { + compatible = "ti,ads7846"; + reg = <1>; + + spi-max-frequency = <2000000>; + interrupts = <25 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; + pendown-gpio = <&gpio 25 1>; + ti,x-plate-ohms = /bits/ 16 <60>; + ti,pressure-max = /bits/ 16 <255>; + }; + }; + }; + + fragment@10 { + target = <&rpidisplay>; + __dormant__ { + backlight = <&backlight_gpio>; + }; + }; + + fragment@11 { + target-path = "/"; + __dormant__ { + backlight_gpio: backlight_gpio { + compatible = "gpio-backlight"; + gpios = <&gpio 18 0>; /* GPIO_ACTIVE_HIGH */ + }; + }; + }; + + fragment@20 { + target = <&rpidisplay>; + __dormant__ { + backlight = <&backlight_pwm>; + }; + }; + + fragment@21 { + target-path = "/"; + __dormant__ { + backlight_pwm: backlight_pwm { + compatible = "pwm-backlight"; + brightness-levels = <0 6 8 12 16 24 32 40 48 64 96 128 160 192 224 255>; + default-brightness-level = <16>; + pwms = <&pwm 0 200000>; + }; + }; + }; + + fragment@22 { + target = <&pwm>; + __dormant__ { + assigned-clock-rates = <1000000>; + status = "okay"; + }; + }; + + fragment@23 { + target = <&chosen>; + __dormant__ { + bootargs = "snd_bcm2835.enable_headphones=0"; + }; + }; + + __overrides__ { + speed = <&rpidisplay>,"spi-max-frequency:0"; + rotate = <&rpidisplay>,"rotate:0", /* fbtft */ + <&rpidisplay>,"rotation:0"; /* drm */ + fps = <&rpidisplay>,"fps:0"; + debug = <&rpidisplay>,"debug:0"; + xohms = <&rpidisplay_ts>,"ti,x-plate-ohms;0"; + swapxy = <&rpidisplay_ts>,"ti,swap-xy?"; + backlight = <&rpidisplay>,"led-gpios:4", + <&rpi_display_pins>,"brcm,pins:0"; + drm = <&rpidisplay>, "compatible=multi-inno,mi0283qt", + <&rpidisplay>, "spi-max-frequency:0=70000000", + <&rpidisplay>, "reset-gpios:8=0", /* GPIO_ACTIVE_HIGH */ + <0>, "+10+11"; + backlight-pwm = <0>, "-10-11+20+21+22+23", + <&rpi_display_pins>, "brcm,function:0=2"; /* Alt5 */ + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-a-overlay.dts linux/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-a-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-a-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-a-overlay.dts 2023-12-13 11:50:48.634961355 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// redo: ovmerge -c spi1-1cs-overlay.dts,cs0_pin=26,cs0_spidev=false mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi1-0,interrupt=16 + +// Device tree overlay for https://www.waveshare.com/2-ch-can-fd-hat.htm +// in "Mode A" (default) configuration +// for details see https://www.waveshare.com/wiki/2-CH_CAN_FD_HAT + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/bcm2835.h> + +/ { + compatible = "brcm,bcm2835"; + fragment@0 { + target = <&gpio>; + __overlay__ { + spi1_pins: spi1_pins { + brcm,pins = <19 20 21>; + brcm,function = <3>; + }; + spi1_cs_pins: spi1_cs_pins { + brcm,pins = <26>; + brcm,function = <1>; + }; + }; + }; + fragment@1 { + target = <&spi1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins &spi1_cs_pins>; + cs-gpios = <&gpio 26 1>; + status = "okay"; + spidev@0 { + compatible = "spidev"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <125000000>; + status = "disabled"; + }; + }; + }; + fragment@2 { + target = <&aux>; + __overlay__ { + status = "okay"; + }; + }; + fragment@3 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + fragment@4 { + target = <&gpio>; + __overlay__ { + mcp251xfd_pins: mcp251xfd_spi0_0_pins { + brcm,pins = <25>; + brcm,function = <BCM2835_FSEL_GPIO_IN>; + }; + }; + }; + fragment@5 { + target-path = "/clocks"; + __overlay__ { + clk_mcp251xfd_osc: mcp251xfd-spi0-0-osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + }; + }; + fragment@6 { + target = <&spi0>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp251xfd@0 { + compatible = "microchip,mcp251xfd"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp251xfd_pins>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk_mcp251xfd_osc>; + }; + }; + }; + fragment@7 { + target-path = "spi1/spidev@0"; + __overlay__ { + status = "disabled"; + }; + }; + fragment@8 { + target = <&gpio>; + __overlay__ { + mcp251xfd_pins_1: mcp251xfd_spi1_0_pins { + brcm,pins = <16>; + brcm,function = <BCM2835_FSEL_GPIO_IN>; + }; + }; + }; + fragment@9 { + target-path = "/clocks"; + __overlay__ { + clk_mcp251xfd_osc_1: mcp251xfd-spi1-0-osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + }; + }; + fragment@10 { + target = <&spi1>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp251xfd@0 { + compatible = "microchip,mcp251xfd"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp251xfd_pins_1>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk_mcp251xfd_osc_1>; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-b-overlay.dts linux/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-b-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-b-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-b-overlay.dts 2023-12-13 11:50:48.634961355 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// redo: ovmerge -c mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi0-1,interrupt=16 + +// Device tree overlay for https://www.waveshare.com/2-ch-can-fd-hat.htm +// in "Mode B" (requried hardware modification) configuration +// for details see https://www.waveshare.com/wiki/2-CH_CAN_FD_HAT + + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/bcm2835.h> + +/ { + compatible = "brcm,bcm2835"; + fragment@0 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + fragment@1 { + target = <&gpio>; + __overlay__ { + mcp251xfd_pins: mcp251xfd_spi0_0_pins { + brcm,pins = <25>; + brcm,function = <BCM2835_FSEL_GPIO_IN>; + }; + }; + }; + fragment@2 { + target-path = "/clocks"; + __overlay__ { + clk_mcp251xfd_osc: mcp251xfd-spi0-0-osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + }; + }; + fragment@3 { + target = <&spi0>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp251xfd@0 { + compatible = "microchip,mcp251xfd"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp251xfd_pins>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk_mcp251xfd_osc>; + }; + }; + }; + fragment@4 { + target = <&spidev1>; + __overlay__ { + status = "disabled"; + }; + }; + fragment@5 { + target = <&gpio>; + __overlay__ { + mcp251xfd_pins_1: mcp251xfd_spi0_1_pins { + brcm,pins = <16>; + brcm,function = <BCM2835_FSEL_GPIO_IN>; + }; + }; + }; + fragment@6 { + target-path = "/clocks"; + __overlay__ { + clk_mcp251xfd_osc_1: mcp251xfd-spi0-1-osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + }; + }; + fragment@7 { + target = <&spi0>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + mcp251xfd@1 { + compatible = "microchip,mcp251xfd"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp251xfd_pins_1>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk_mcp251xfd_osc_1>; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/wittypi-overlay.dts linux/arch/arm/boot/dts/overlays/wittypi-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/wittypi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/wittypi-overlay.dts 2023-12-13 11:50:48.634961355 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Device Tree overlay for Witty Pi extension board by UUGear + * + */ + +/dts-v1/; +/plugin/; + +/ { + + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&leds>; + __overlay__ { + compatible = "gpio-leds"; + wittypi_led: wittypi_led { + label = "wittypi_led"; + linux,default-trigger = "default-on"; + gpios = <&gpio 17 0>; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + rtc: ds1337@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + wakeup-source; + }; + }; + }; + + __overrides__ { + led_gpio = <&wittypi_led>,"gpios:4"; + led_trigger = <&wittypi_led>,"linux,default-trigger"; + }; + +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/overlays/wm8960-soundcard-overlay.dts linux/arch/arm/boot/dts/overlays/wm8960-soundcard-overlay.dts --- linux-6.1.66/arch/arm/boot/dts/overlays/wm8960-soundcard-overlay.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/overlays/wm8960-soundcard-overlay.dts 2023-12-13 11:50:48.635961358 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// Definitions for Waveshare WM8960 https://github.com/waveshare/WM8960-Audio-HAT +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path="/"; + __overlay__ { + wm8960_mclk: wm8960_mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; + }; + }; + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wm8960: wm8960 { + compatible = "wlf,wm8960"; + reg = <0x1a>; + #sound-dai-cells = <0>; + AVDD-supply = <&vdd_5v0_reg>; + DVDD-supply = <&vdd_3v3_reg>; + }; + }; + }; + + + fragment@3 { + target = <&sound>; + slave_overlay: __overlay__ { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "wm8960-soundcard"; + status = "okay"; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Speaker", "SPK_LP", + "Speaker", "SPK_LN", + "LINPUT1", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Mic Jack", + "RINPUT2", "Mic Jack"; + + simple-audio-card,cpu { + sound-dai = <&i2s_clk_producer>; + }; + dailink0_slave: simple-audio-card,codec { + sound-dai = <&wm8960>; + clocks = <&wm8960_mclk>; + clock-names = "mclk"; + }; + }; + }; + + __overrides__ { + alsaname = <&slave_overlay>,"simple-audio-card,name"; + compatible = <&wm8960>,"compatible"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/boot/dts/rp1.dtsi linux/arch/arm/boot/dts/rp1.dtsi --- linux-6.1.66/arch/arm/boot/dts/rp1.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/boot/dts/rp1.dtsi 2023-12-14 11:44:51.540148848 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +#include <dt-bindings/clock/rp1.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/mfd/rp1.h> + +&rp1_target { + rp1: rp1 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&rp1>; + + // ranges and dma-ranges must be provided by the includer + + rp1_clocks: clocks@18000 { + compatible = "raspberrypi,rp1-clocks"; + #clock-cells = <1>; + reg = <0xc0 0x40018000 0x0 0x10038>; + clocks = <&clk_xosc>; + + assigned-clocks = <&rp1_clocks RP1_PLL_SYS_CORE>, + <&rp1_clocks RP1_PLL_AUDIO_CORE>, + // RP1_PLL_VIDEO_CORE and dividers are now managed by VEC,DPI drivers + <&rp1_clocks RP1_PLL_SYS>, + <&rp1_clocks RP1_PLL_SYS_SEC>, + <&rp1_clocks RP1_PLL_AUDIO>, + <&rp1_clocks RP1_PLL_AUDIO_SEC>, + <&rp1_clocks RP1_CLK_SYS>, + <&rp1_clocks RP1_PLL_SYS_PRI_PH>, + // RP1_CLK_SLOW_SYS is used for the frequency counter (FC0) + <&rp1_clocks RP1_CLK_SLOW_SYS>, + <&rp1_clocks RP1_CLK_SDIO_TIMER>, + <&rp1_clocks RP1_CLK_SDIO_ALT_SRC>, + <&rp1_clocks RP1_CLK_ETH_TSU>; + + assigned-clock-rates = <1000000000>, // RP1_PLL_SYS_CORE + <1536000000>, // RP1_PLL_AUDIO_CORE + <200000000>, // RP1_PLL_SYS + <125000000>, // RP1_PLL_SYS_SEC + <61440000>, // RP1_PLL_AUDIO + <192000000>, // RP1_PLL_AUDIO_SEC + <200000000>, // RP1_CLK_SYS + <100000000>, // RP1_PLL_SYS_PRI_PH + // Must match the XOSC frequency + <50000000>, // RP1_CLK_SLOW_SYS + <1000000>, // RP1_CLK_SDIO_TIMER + <200000000>, // RP1_CLK_SDIO_ALT_SRC + <50000000>; // RP1_CLK_ETH_TSU + }; + + rp1_uart0: serial@30000 { + compatible = "arm,pl011-axi"; + reg = <0xc0 0x40030000 0x0 0x100>; + interrupts = <RP1_INT_UART0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_UART &rp1_clocks RP1_PLL_SYS_PRI_PH>; + clock-names = "uartclk", "apb_pclk"; + dmas = <&rp1_dma RP1_DMA_UART0_TX>, + <&rp1_dma RP1_DMA_UART0_RX>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + arm,primecell-periphid = <0x00541011>; + uart-has-rtscts; + cts-event-workaround; + skip-init; + status = "disabled"; + }; + + rp1_uart1: serial@34000 { + compatible = "arm,pl011-axi"; + reg = <0xc0 0x40034000 0x0 0x100>; + interrupts = <RP1_INT_UART1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_UART &rp1_clocks RP1_PLL_SYS_PRI_PH>; + clock-names = "uartclk", "apb_pclk"; + // dmas = <&rp1_dma RP1_DMA_UART1_TX>, + // <&rp1_dma RP1_DMA_UART1_RX>; + // dma-names = "tx", "rx"; + pinctrl-names = "default"; + arm,primecell-periphid = <0x00541011>; + uart-has-rtscts; + cts-event-workaround; + skip-init; + status = "disabled"; + }; + + rp1_uart2: serial@38000 { + compatible = "arm,pl011-axi"; + reg = <0xc0 0x40038000 0x0 0x100>; + interrupts = <RP1_INT_UART2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_UART &rp1_clocks RP1_PLL_SYS_PRI_PH>; + clock-names = "uartclk", "apb_pclk"; + // dmas = <&rp1_dma RP1_DMA_UART2_TX>, + // <&rp1_dma RP1_DMA_UART2_RX>; + // dma-names = "tx", "rx"; + pinctrl-names = "default"; + arm,primecell-periphid = <0x00541011>; + uart-has-rtscts; + cts-event-workaround; + skip-init; + status = "disabled"; + }; + + rp1_uart3: serial@3c000 { + compatible = "arm,pl011-axi"; + reg = <0xc0 0x4003c000 0x0 0x100>; + interrupts = <RP1_INT_UART3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_UART &rp1_clocks RP1_PLL_SYS_PRI_PH>; + clock-names = "uartclk", "apb_pclk"; + // dmas = <&rp1_dma RP1_DMA_UART3_TX>, + // <&rp1_dma RP1_DMA_UART3_RX>; + // dma-names = "tx", "rx"; + pinctrl-names = "default"; + arm,primecell-periphid = <0x00541011>; + uart-has-rtscts; + cts-event-workaround; + skip-init; + status = "disabled"; + }; + + rp1_uart4: serial@40000 { + compatible = "arm,pl011-axi"; + reg = <0xc0 0x40040000 0x0 0x100>; + interrupts = <RP1_INT_UART4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_UART &rp1_clocks RP1_PLL_SYS_PRI_PH>; + clock-names = "uartclk", "apb_pclk"; + // dmas = <&rp1_dma RP1_DMA_UART4_TX>, + // <&rp1_dma RP1_DMA_UART4_RX>; + // dma-names = "tx", "rx"; + pinctrl-names = "default"; + arm,primecell-periphid = <0x00541011>; + uart-has-rtscts; + cts-event-workaround; + skip-init; + status = "disabled"; + }; + + rp1_uart5: serial@44000 { + compatible = "arm,pl011-axi"; + reg = <0xc0 0x40044000 0x0 0x100>; + interrupts = <RP1_INT_UART5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_UART &rp1_clocks RP1_PLL_SYS_PRI_PH>; + clock-names = "uartclk", "apb_pclk"; + // dmas = <&rp1_dma RP1_DMA_UART5_TX>, + // <&rp1_dma RP1_DMA_UART5_RX>; + // dma-names = "tx", "rx"; + pinctrl-names = "default"; + arm,primecell-periphid = <0x00541011>; + uart-has-rtscts; + cts-event-workaround; + skip-init; + status = "disabled"; + }; + + rp1_spi8: spi@4c000 { + reg = <0xc0 0x4004c000 0x0 0x130>; + compatible = "snps,dw-apb-ssi"; + interrupts = <RP1_INT_SPI8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + clock-names = "ssi_clk"; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <2>; + dmas = <&rp1_dma RP1_DMA_SPI8_TX>, + <&rp1_dma RP1_DMA_SPI8_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + rp1_spi0: spi@50000 { + reg = <0xc0 0x40050000 0x0 0x130>; + compatible = "snps,dw-apb-ssi"; + interrupts = <RP1_INT_SPI0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + clock-names = "ssi_clk"; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <2>; + dmas = <&rp1_dma RP1_DMA_SPI0_TX>, + <&rp1_dma RP1_DMA_SPI0_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + rp1_spi1: spi@54000 { + reg = <0xc0 0x40054000 0x0 0x130>; + compatible = "snps,dw-apb-ssi"; + interrupts = <RP1_INT_SPI1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + clock-names = "ssi_clk"; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <2>; + dmas = <&rp1_dma RP1_DMA_SPI1_TX>, + <&rp1_dma RP1_DMA_SPI1_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + rp1_spi2: spi@58000 { + reg = <0xc0 0x40058000 0x0 0x130>; + compatible = "snps,dw-apb-ssi"; + interrupts = <RP1_INT_SPI2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + clock-names = "ssi_clk"; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <2>; + dmas = <&rp1_dma RP1_DMA_SPI2_TX>, + <&rp1_dma RP1_DMA_SPI2_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + rp1_spi3: spi@5c000 { + reg = <0xc0 0x4005c000 0x0 0x130>; + compatible = "snps,dw-apb-ssi"; + interrupts = <RP1_INT_SPI3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + clock-names = "ssi_clk"; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <2>; + dmas = <&rp1_dma RP1_DMA_SPI3_TX>, + <&rp1_dma RP1_DMA_SPI3_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + // SPI4 is a target/slave interface + rp1_spi4: spi@60000 { + reg = <0xc0 0x40060000 0x0 0x130>; + compatible = "snps,dw-apb-ssi"; + interrupts = <RP1_INT_SPI4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + clock-names = "ssi_clk"; + #address-cells = <0>; + #size-cells = <0>; + num-cs = <1>; + spi-slave; + dmas = <&rp1_dma RP1_DMA_SPI4_TX>, + <&rp1_dma RP1_DMA_SPI4_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + + slave { + compatible = "spidev"; + spi-max-frequency = <1000000>; + }; + }; + + rp1_spi5: spi@64000 { + reg = <0xc0 0x40064000 0x0 0x130>; + compatible = "snps,dw-apb-ssi"; + interrupts = <RP1_INT_SPI5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + clock-names = "ssi_clk"; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <2>; + dmas = <&rp1_dma RP1_DMA_SPI5_TX>, + <&rp1_dma RP1_DMA_SPI5_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + rp1_spi6: spi@68000 { + reg = <0xc0 0x40068000 0x0 0x130>; + compatible = "snps,dw-apb-ssi"; + interrupts = <RP1_INT_SPI6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + clock-names = "ssi_clk"; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <2>; + dmas = <&rp1_dma RP1_DMA_SPI6_TX>, + <&rp1_dma RP1_DMA_SPI6_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + // SPI7 is a target/slave interface + rp1_spi7: spi@6c000 { + reg = <0xc0 0x4006c000 0x0 0x130>; + compatible = "snps,dw-apb-ssi"; + interrupts = <RP1_INT_SPI7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + clock-names = "ssi_clk"; + #address-cells = <0>; + #size-cells = <0>; + num-cs = <1>; + spi-slave; + dmas = <&rp1_dma RP1_DMA_SPI7_TX>, + <&rp1_dma RP1_DMA_SPI7_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + + slave { + compatible = "spidev"; + spi-max-frequency = <1000000>; + }; + }; + + rp1_i2c0: i2c@70000 { + reg = <0xc0 0x40070000 0x0 0x1000>; + compatible = "snps,designware-i2c"; + interrupts = <RP1_INT_I2C0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + status = "disabled"; + }; + + rp1_i2c1: i2c@74000 { + reg = <0xc0 0x40074000 0x0 0x1000>; + compatible = "snps,designware-i2c"; + interrupts = <RP1_INT_I2C1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + status = "disabled"; + }; + + rp1_i2c2: i2c@78000 { + reg = <0xc0 0x40078000 0x0 0x1000>; + compatible = "snps,designware-i2c"; + interrupts = <RP1_INT_I2C2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + status = "disabled"; + }; + + rp1_i2c3: i2c@7c000 { + reg = <0xc0 0x4007c000 0x0 0x1000>; + compatible = "snps,designware-i2c"; + interrupts = <RP1_INT_I2C3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + status = "disabled"; + }; + + rp1_i2c4: i2c@80000 { + reg = <0xc0 0x40080000 0x0 0x1000>; + compatible = "snps,designware-i2c"; + interrupts = <RP1_INT_I2C4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + status = "disabled"; + }; + + rp1_i2c5: i2c@84000 { + reg = <0xc0 0x40084000 0x0 0x1000>; + compatible = "snps,designware-i2c"; + interrupts = <RP1_INT_I2C5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + status = "disabled"; + }; + + rp1_i2c6: i2c@88000 { + reg = <0xc0 0x40088000 0x0 0x1000>; + compatible = "snps,designware-i2c"; + interrupts = <RP1_INT_I2C6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + status = "disabled"; + }; + + rp1_pwm0: pwm@98000 { + compatible = "raspberrypi,rp1-pwm"; + reg = <0xc0 0x40098000 0x0 0x100>; + #pwm-cells = <3>; + clocks = <&rp1_clocks RP1_CLK_PWM0>; + assigned-clocks = <&rp1_clocks RP1_CLK_PWM0>; + assigned-clock-rates = <6144000>; + status = "disabled"; + }; + + rp1_pwm1: pwm@9c000 { + compatible = "raspberrypi,rp1-pwm"; + reg = <0xc0 0x4009c000 0x0 0x100>; + #pwm-cells = <3>; + clocks = <&rp1_clocks RP1_CLK_PWM1>; + assigned-clocks = <&rp1_clocks RP1_CLK_PWM1>; + assigned-clock-rates = <6144000>; + status = "disabled"; + }; + + rp1_i2s0: i2s@a0000 { + reg = <0xc0 0x400a0000 0x0 0x1000>; + compatible = "snps,designware-i2s"; + // Providing an interrupt disables DMA + // interrupts = <RP1_INT_I2S0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_I2S>; + clock-names = "i2sclk"; + #sound-dai-cells = <0>; + dmas = <&rp1_dma RP1_DMA_I2S0_TX>,<&rp1_dma RP1_DMA_I2S0_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + rp1_i2s1: i2s@a4000 { + reg = <0xc0 0x400a4000 0x0 0x1000>; + compatible = "snps,designware-i2s"; + // Providing an interrupt disables DMA + // interrupts = <RP1_INT_I2S1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_I2S>; + clock-names = "i2sclk"; + #sound-dai-cells = <0>; + dmas = <&rp1_dma RP1_DMA_I2S1_TX>,<&rp1_dma RP1_DMA_I2S1_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + rp1_i2s2: i2s@a8000 { + reg = <0xc0 0x400a8000 0x0 0x1000>; + compatible = "snps,designware-i2s"; + // Providing an interrupt disables DMA + // interrupts = <RP1_INT_I2S2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_I2S>; + status = "disabled"; + }; + + rp1_sdio_clk0: sdio_clk0@b0004 { + compatible = "raspberrypi,rp1-sdio-clk"; + reg = <0xc0 0x400b0004 0x0 0x1c>; + clocks = <&sdio_src &sdhci_core>; + clock-names = "src", "base"; + #clock-cells = <0>; + status = "disabled"; + }; + + rp1_sdio_clk1: sdio_clk1@b4004 { + compatible = "raspberrypi,rp1-sdio-clk"; + reg = <0xc0 0x400b4004 0x0 0x1c>; + clocks = <&sdio_src &sdhci_core>; + clock-names = "src", "base"; + #clock-cells = <0>; + status = "disabled"; + }; + + rp1_adc: adc@c8000 { + compatible = "raspberrypi,rp1-adc"; + reg = <0xc0 0x400c8000 0x0 0x4000>; + clocks = <&rp1_clocks RP1_CLK_ADC>; + clock-names = "adcclk"; + #clock-cells = <0>; + vref-supply = <&rp1_vdd_3v3>; + status = "disabled"; + }; + + rp1_gpio: gpio@d0000 { + reg = <0xc0 0x400d0000 0x0 0xc000>, + <0xc0 0x400e0000 0x0 0xc000>, + <0xc0 0x400f0000 0x0 0xc000>; + compatible = "raspberrypi,rp1-gpio"; + interrupts = <RP1_INT_IO_BANK0 IRQ_TYPE_LEVEL_HIGH>, + <RP1_INT_IO_BANK1 IRQ_TYPE_LEVEL_HIGH>, + <RP1_INT_IO_BANK2 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + rp1_uart0_14_15: rp1_uart0_14_15 { + pin_txd { + function = "uart0"; + pins = "gpio14"; + bias-disable; + }; + pin_rxd { + function = "uart0"; + pins = "gpio15"; + bias-pull-up; + }; + }; + rp1_uart0_ctsrts_16_17: rp1_uart0_ctsrts_16_17 { + pin_cts { + function = "uart0"; + pins = "gpio16"; + bias-pull-up; + }; + pin_rts { + function = "uart0"; + pins = "gpio17"; + bias-disable; + }; + }; + rp1_uart1_0_1: rp1_uart1_0_1 { + pin_txd { + function = "uart1"; + pins = "gpio0"; + bias-disable; + }; + pin_rxd { + function = "uart1"; + pins = "gpio1"; + bias-pull-up; + }; + }; + rp1_uart1_ctsrts_2_3: rp1_uart1_ctsrts_2_3 { + pin_cts { + function = "uart1"; + pins = "gpio2"; + bias-pull-up; + }; + pin_rts { + function = "uart1"; + pins = "gpio3"; + bias-disable; + }; + }; + rp1_uart2_4_5: rp1_uart2_4_5 { + pin_txd { + function = "uart2"; + pins = "gpio4"; + bias-disable; + }; + pin_rxd { + function = "uart2"; + pins = "gpio5"; + bias-pull-up; + }; + }; + rp1_uart2_ctsrts_6_7: rp1_uart2_ctsrts_6_7 { + pin_cts { + function = "uart2"; + pins = "gpio6"; + bias-pull-up; + }; + pin_rts { + function = "uart2"; + pins = "gpio7"; + bias-disable; + }; + }; + rp1_uart3_8_9: rp1_uart3_8_9 { + pin_txd { + function = "uart3"; + pins = "gpio8"; + bias-disable; + }; + pin_rxd { + function = "uart3"; + pins = "gpio9"; + bias-pull-up; + }; + }; + rp1_uart3_ctsrts_10_11: rp1_uart3_ctsrts_10_11 { + pin_cts { + function = "uart3"; + pins = "gpio10"; + bias-pull-up; + }; + pin_rts { + function = "uart3"; + pins = "gpio11"; + bias-disable; + }; + }; + rp1_uart4_12_13: rp1_uart4_12_13 { + pin_txd { + function = "uart4"; + pins = "gpio12"; + bias-disable; + }; + pin_rxd { + function = "uart4"; + pins = "gpio13"; + bias-pull-up; + }; + }; + rp1_uart4_ctsrts_14_15: rp1_uart4_ctsrts_14_15 { + pin_cts { + function = "uart4"; + pins = "gpio14"; + bias-pull-up; + }; + pin_rts { + function = "uart4"; + pins = "gpio15"; + bias-disable; + }; + }; + + rp1_sdio0_22_27: rp1_sdio0_22_27 { + pin_clk { + function = "sd0"; + pins = "gpio22"; + bias-disable; + drive-strength = <12>; + slew-rate = <1>; + }; + pin_cmd { + function = "sd0"; + pins = "gpio23"; + bias-pull-up; + drive-strength = <12>; + slew-rate = <1>; + }; + pins_dat { + function = "sd0"; + pins = "gpio24", "gpio25", "gpio26", "gpio27"; + bias-pull-up; + drive-strength = <12>; + slew-rate = <1>; + }; + }; + + rp1_sdio1_28_33: rp1_sdio1_28_33 { + pin_clk { + function = "sd1"; + pins = "gpio28"; + bias-disable; + drive-strength = <12>; + slew-rate = <1>; + }; + pin_cmd { + function = "sd1"; + pins = "gpio29"; + bias-pull-up; + drive-strength = <12>; + slew-rate = <1>; + }; + pins_dat { + function = "sd1"; + pins = "gpio30", "gpio31", "gpio32", "gpio33"; + bias-pull-up; + drive-strength = <12>; + slew-rate = <1>; + }; + }; + + rp1_i2s0_18_21: rp1_i2s0_18_21 { + function = "i2s0"; + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + bias-disable; + }; + + rp1_i2s1_18_21: rp1_i2s1_18_21 { + function = "i2s1"; + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + bias-disable; + }; + + rp1_i2c4_34_35: rp1_i2c4_34_35 { + function = "i2c4"; + pins = "gpio34", "gpio35"; + bias-pull-up; + }; + rp1_i2c6_38_39: rp1_i2c6_38_39 { + function = "i2c6"; + pins = "gpio38", "gpio39"; + bias-pull-up; + }; + rp1_i2c4_40_41: rp1_i2c4_40_41 { + function = "i2c4"; + pins = "gpio40", "gpio41"; + bias-pull-up; + }; + rp1_i2c5_44_45: rp1_i2c5_44_45 { + function = "i2c5"; + pins = "gpio44", "gpio45"; + bias-pull-up; + }; + rp1_i2c0_0_1: rp1_i2c0_0_1 { + function = "i2c0"; + pins = "gpio0", "gpio1"; + bias-pull-up; + }; + rp1_i2c0_8_9: rp1_i2c0_8_9 { + function = "i2c0"; + pins = "gpio8", "gpio9"; + bias-pull-up; + }; + rp1_i2c1_2_3: rp1_i2c1_2_3 { + function = "i2c1"; + pins = "gpio2", "gpio3"; + bias-pull-up; + }; + rp1_i2c1_10_11: rp1_i2c1_10_11 { + function = "i2c1"; + pins = "gpio10", "gpio11"; + bias-pull-up; + }; + rp1_i2c2_4_5: rp1_i2c2_4_5 { + function = "i2c2"; + pins = "gpio4", "gpio5"; + bias-pull-up; + }; + rp1_i2c2_12_13: rp1_i2c2_12_13 { + function = "i2c2"; + pins = "gpio12", "gpio13"; + bias-pull-up; + }; + rp1_i2c3_6_7: rp1_i2c3_6_7 { + function = "i2c3"; + pins = "gpio6", "gpio7"; + bias-pull-up; + }; + rp1_i2c3_14_15: rp1_i2c3_14_15 { + function = "i2c3"; + pins = "gpio14", "gpio15"; + bias-pull-up; + }; + rp1_i2c3_22_23: rp1_i2c3_22_23 { + function = "i2c3"; + pins = "gpio22", "gpio23"; + bias-pull-up; + }; + + // DPI mappings with HSYNC,VSYNC but without PIXCLK,DE + rp1_dpi_16bit_gpio2: rp1_dpi_16bit_gpio2 { /* Mode 2, not fully supported by RP1 */ + function = "dpi"; + pins = "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", + "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19"; + bias-disable; + }; + rp1_dpi_16bit_cpadhi_gpio2: rp1_dpi_16bit_cpadhi_gpio2 { /* Mode 3 */ + function = "dpi"; + pins = "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", + "gpio12", "gpio13", "gpio14", "gpio15", + "gpio16", "gpio17", + "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24"; + bias-disable; + }; + rp1_dpi_16bit_pad666_gpio2: rp1_dpi_16bit_pad666_gpio2 { /* Mode 4 */ + function = "dpi"; + pins = "gpio2", "gpio3", + "gpio5", "gpio6", "gpio7", "gpio8", + "gpio9", + "gpio12", "gpio13", "gpio14", "gpio15", + "gpio16", "gpio17", + "gpio21", "gpio22", "gpio23", "gpio24", + "gpio25"; + bias-disable; + }; + rp1_dpi_18bit_gpio2: rp1_dpi_18bit_gpio2 { /* Mode 5, not fully supported by RP1 */ + function = "dpi"; + pins = "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", + "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21"; + bias-disable; + }; + rp1_dpi_18bit_cpadhi_gpio2: rp1_dpi_18bit_cpadhi_gpio2 { /* Mode 6 */ + function = "dpi"; + pins = "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", + "gpio12", "gpio13", "gpio14", "gpio15", + "gpio16", "gpio17", + "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25"; + bias-disable; + }; + rp1_dpi_24bit_gpio2: rp1_dpi_24bit_gpio2 { /* Mode 7 */ + function = "dpi"; + pins = "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", + "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", + "gpio26", "gpio27"; + bias-disable; + }; + rp1_dpi_hvsync: rp1_dpi_hvsync { /* Sync only, for use with int VDAC */ + function = "dpi"; + pins = "gpio2", "gpio3"; + bias-disable; + }; + + // More DPI mappings, including PIXCLK,DE on GPIOs 0,1 + rp1_dpi_16bit_gpio0: rp1_dpi_16bit_gpio0 { /* Mode 2, not fully supported by RP1 */ + function = "dpi"; + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", + "gpio16", "gpio17", "gpio18", "gpio19"; + bias-disable; + }; + rp1_dpi_16bit_cpadhi_gpio0: rp1_dpi_16bit_cpadhi_gpio0 { /* Mode 3 */ + function = "dpi"; + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", + "gpio12", "gpio13", "gpio14", "gpio15", + "gpio16", "gpio17", + "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24"; + bias-disable; + }; + rp1_dpi_16bit_pad666_gpio0: rp1_dpi_16bit_pad666_gpio0 { /* Mode 4 */ + function = "dpi"; + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio5", "gpio6", "gpio7", "gpio8", + "gpio9", + "gpio12", "gpio13", "gpio14", "gpio15", + "gpio16", "gpio17", + "gpio21", "gpio22", "gpio23", "gpio24", + "gpio25"; + bias-disable; + }; + rp1_dpi_18bit_gpio0: rp1_dpi_18bit_gpio0 { /* Mode 5, not fully supported by RP1 */ + function = "dpi"; + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", + "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21"; + bias-disable; + }; + rp1_dpi_18bit_cpadhi_gpio0: rp1_dpi_18bit_cpadhi_gpio0 { /* Mode 6 */ + function = "dpi"; + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", + "gpio12", "gpio13", "gpio14", "gpio15", + "gpio16", "gpio17", + "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25"; + bias-disable; + }; + rp1_dpi_24bit_gpio0: rp1_dpi_24bit_gpio0 { /* Mode 7 -- All GPIOs used! */ + function = "dpi"; + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", + "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27"; + bias-disable; + }; + + rp1_pwm1_gpio45: rp1_pwm1_gpio45 { + function = "pwm1"; + pins = "gpio45"; + bias-pull-down; + }; + + rp1_spi0_gpio9: rp1_spi0_gpio9 { + function = "spi0"; + pins = "gpio9", "gpio10", "gpio11"; + bias-disable; + drive-strength = <12>; + slew-rate = <1>; + }; + + rp1_spi0_cs_gpio7: rp1_spi0_cs_gpio7 { + function = "spi0"; + pins = "gpio7", "gpio8"; + bias-pull-up; + }; + + rp1_spi1_gpio19: rp1_spi1_gpio19 { + function = "spi1"; + pins = "gpio19", "gpio20", "gpio21"; + bias-disable; + drive-strength = <12>; + slew-rate = <1>; + }; + + rp1_spi2_gpio1: rp1_spi2_gpio1 { + function = "spi2"; + pins = "gpio1", "gpio2", "gpio3"; + bias-disable; + drive-strength = <12>; + slew-rate = <1>; + }; + + rp1_spi3_gpio5: rp1_spi3_gpio5 { + function = "spi3"; + pins = "gpio5", "gpio6", "gpio7"; + bias-disable; + drive-strength = <12>; + slew-rate = <1>; + }; + + rp1_spi4_gpio9: rp1_spi4_gpio9 { + function = "spi4"; + pins = "gpio9", "gpio10", "gpio11"; + bias-disable; + drive-strength = <12>; + slew-rate = <1>; + }; + + rp1_spi5_gpio13: rp1_spi5_gpio13 { + function = "spi5"; + pins = "gpio13", "gpio14", "gpio15"; + bias-disable; + drive-strength = <12>; + slew-rate = <1>; + }; + + rp1_spi8_gpio49: rp1_spi8_gpio49 { + function = "spi8"; + pins = "gpio49", "gpio50", "gpio51"; + bias-disable; + drive-strength = <12>; + slew-rate = <1>; + }; + + rp1_spi8_cs_gpio52: rp1_spi8_cs_gpio52 { + function = "spi0"; + pins = "gpio52", "gpio53"; + bias-pull-up; + }; + }; + + rp1_eth: ethernet@100000 { + reg = <0xc0 0x40100000 0x0 0x4000>; + compatible = "cdns,macb"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <RP1_INT_ETH IRQ_TYPE_LEVEL_HIGH>; + clocks = <&macb_pclk &macb_hclk &rp1_clocks RP1_CLK_ETH_TSU>; + clock-names = "pclk", "hclk", "tsu_clk"; + phy-mode = "rgmii-id"; + cdns,aw2w-max-pipe = /bits/ 8 <8>; + cdns,ar2r-max-pipe = /bits/ 8 <8>; + cdns,use-aw2b-fill; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + }; + + rp1_csi0: csi@110000 { + compatible = "raspberrypi,rp1-cfe"; + reg = <0xc0 0x40110000 0x0 0x100>, // CSI2 DMA address + <0xc0 0x40114000 0x0 0x100>, // PHY/CSI Host address + <0xc0 0x40120000 0x0 0x100>, // MIPI CFG address + <0xc0 0x40124000 0x0 0x1000>; // PiSP FE address + + // interrupts must match rp1_pisp_fe setup + interrupts = <RP1_INT_MIPI0 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>; + assigned-clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>; + assigned-clock-rates = <25000000>; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rp1_csi1: csi@128000 { + compatible = "raspberrypi,rp1-cfe"; + reg = <0xc0 0x40128000 0x0 0x100>, // CSI2 DMA address + <0xc0 0x4012c000 0x0 0x100>, // PHY/CSI Host address + <0xc0 0x40138000 0x0 0x100>, // MIPI CFG address + <0xc0 0x4013c000 0x0 0x1000>; // PiSP FE address + + // interrupts must match rp1_pisp_fe setup + interrupts = <RP1_INT_MIPI1 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>; + assigned-clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>; + assigned-clock-rates = <25000000>; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rp1_mmc0: mmc@180000 { + reg = <0xc0 0x40180000 0x0 0x100>; + compatible = "raspberrypi,rp1-dwcmshc"; + interrupts = <RP1_INT_SDIO0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS &sdhci_core + &rp1_clocks RP1_CLK_SDIO_TIMER + &rp1_sdio_clk0>; + clock-names = "bus", "core", "timeout", "sdio"; + /* Bank 0 VDDIO is fixed */ + no-1-8-v; + bus-width = <4>; + vmmc-supply = <&rp1_vdd_3v3>; + broken-cd; + status = "disabled"; + }; + + rp1_mmc1: mmc@184000 { + reg = <0xc0 0x40184000 0x0 0x100>; + compatible = "raspberrypi,rp1-dwcmshc"; + interrupts = <RP1_INT_SDIO1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS &sdhci_core + &rp1_clocks RP1_CLK_SDIO_TIMER + &rp1_sdio_clk1>; + clock-names = "bus", "core", "timeout", "sdio"; + bus-width = <4>; + vmmc-supply = <&rp1_vdd_3v3>; + /* Nerf SDR speeds */ + sdhci-caps-mask = <0x3 0x0>; + broken-cd; + status = "disabled"; + }; + + rp1_dma: dma@188000 { + reg = <0xc0 0x40188000 0x0 0x1000>; + compatible = "snps,axi-dma-1.01a"; + interrupts = <RP1_INT_DMA IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sdhci_core &rp1_clocks RP1_CLK_SYS>; + clock-names = "core-clk", "cfgr-clk"; + + #dma-cells = <1>; + dma-channels = <8>; + snps,dma-masters = <1>; + snps,dma-targets = <64>; + snps,data-width = <4>; // (8 << 4) == 128 bits + snps,block-size = <0x40000 0x40000 0x40000 0x40000 0x40000 0x40000 0x40000 0x40000>; + snps,priority = <0 1 2 3 4 5 6 7>; + snps,axi-max-burst-len = <8>; + status = "disabled"; + }; + + rp1_usb0: usb@200000 { + reg = <0xc0 0x40200000 0x0 0x100000>; + compatible = "snps,dwc3"; + dr_mode = "host"; + usb3-lpm-capable; + snps,axi-pipe-limit = /bits/ 8 <8>; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-ss-quirk; + snps,tx-max-burst-prd = <8>; + snps,tx-thr-num-pkt-prd = <2>; + interrupts = <RP1_INT_USBHOST0_0 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + rp1_usb1: usb@300000 { + reg = <0xc0 0x40300000 0x0 0x100000>; + compatible = "snps,dwc3"; + dr_mode = "host"; + usb3-lpm-capable; + snps,axi-pipe-limit = /bits/ 8 <8>; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-ss-quirk; + snps,tx-max-burst-prd = <8>; + snps,tx-thr-num-pkt-prd = <2>; + interrupts = <RP1_INT_USBHOST1_0 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + rp1_dsi0: dsi@110000 { + compatible = "raspberrypi,rp1dsi"; + status = "disabled"; + reg = <0xc0 0x40118000 0x0 0x1000>, // MIPI0 DSI DMA (ArgonDPI) + <0xc0 0x4011c000 0x0 0x1000>, // MIPI0 DSI Host (SNPS) + <0xc0 0x40120000 0x0 0x1000>; // MIPI0 CFG + + interrupts = <RP1_INT_MIPI0 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>, // required, config bus clock + <&rp1_clocks RP1_CLK_MIPI0_DPI>, // required, pixel clock + <&clksrc_mipi0_dsi_byteclk>, // internal, parent for divide + <&clk_xosc>; // hardwired to DSI "refclk" + clock-names = "cfgclk", "dpiclk", "byteclk", "refclk"; + + assigned-clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>, + <&rp1_clocks RP1_CLK_MIPI0_DPI>; + assigned-clock-rates = <25000000>; + assigned-clock-parents = <0>, <&clksrc_mipi0_dsi_byteclk>; + }; + + rp1_dsi1: dsi@128000 { + compatible = "raspberrypi,rp1dsi"; + status = "disabled"; + reg = <0xc0 0x40130000 0x0 0x1000>, // MIPI1 DSI DMA (ArgonDPI) + <0xc0 0x40134000 0x0 0x1000>, // MIPI1 DSI Host (SNPS) + <0xc0 0x40138000 0x0 0x1000>; // MIPI1 CFG + + interrupts = <RP1_INT_MIPI1 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>, // required, config bus clock + <&rp1_clocks RP1_CLK_MIPI1_DPI>, // required, pixel clock + <&clksrc_mipi1_dsi_byteclk>, // internal, parent for divide + <&clk_xosc>; // hardwired to DSI "refclk" + clock-names = "cfgclk", "dpiclk", "byteclk", "refclk"; + + assigned-clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>, + <&rp1_clocks RP1_CLK_MIPI1_DPI>; + assigned-clock-rates = <25000000>; + assigned-clock-parents = <0>, <&clksrc_mipi1_dsi_byteclk>; + }; + + /* VEC and DPI both need to control PLL_VIDEO and cannot work together; */ + /* config.txt should enable one or other using dtparam=vec or an overlay. */ + rp1_vec: vec@144000 { + compatible = "raspberrypi,rp1vec"; + status = "disabled"; + reg = <0xc0 0x40144000 0x0 0x1000>, // VIDEO_OUT_VEC + <0xc0 0x40140000 0x0 0x1000>; // VIDEO_OUT_CFG + + interrupts = <RP1_INT_VIDEO_OUT IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&rp1_clocks RP1_CLK_VEC>; + + assigned-clocks = <&rp1_clocks RP1_PLL_VIDEO_CORE>, + <&rp1_clocks RP1_PLL_VIDEO_SEC>, + <&rp1_clocks RP1_CLK_VEC>; + assigned-clock-rates = <1188000000>, + <108000000>, + <108000000>; + assigned-clock-parents = <0>, + <&rp1_clocks RP1_PLL_VIDEO_CORE>, + <&rp1_clocks RP1_PLL_VIDEO_SEC>; + }; + + rp1_dpi: dpi@148000 { + compatible = "raspberrypi,rp1dpi"; + status = "disabled"; + reg = <0xc0 0x40148000 0x0 0x1000>, // VIDEO_OUT DPI + <0xc0 0x40140000 0x0 0x1000>; // VIDEO_OUT_CFG + + interrupts = <RP1_INT_VIDEO_OUT IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&rp1_clocks RP1_CLK_DPI>, // DPI pixel clock + <&rp1_clocks RP1_PLL_VIDEO>, // PLL primary divider, and + <&rp1_clocks RP1_PLL_VIDEO_CORE>; // VCO, which we also control + clock-names = "dpiclk", "plldiv", "pllcore"; + + assigned-clocks = <&rp1_clocks RP1_CLK_DPI>; + assigned-clock-parents = <&rp1_clocks RP1_PLL_VIDEO>; + }; + }; +}; + +&clocks { + clk_xosc: clk_xosc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "xosc"; + clock-frequency = <50000000>; + }; + macb_pclk: macb_pclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "pclk"; + clock-frequency = <200000000>; + }; + macb_hclk: macb_hclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "hclk"; + clock-frequency = <200000000>; + }; + sdio_src: sdio_src { + // 400 MHz on FPGA. PLL sys VCO on asic + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "src"; + clock-frequency = <1000000000>; + }; + sdhci_core: sdhci_core { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "core"; + clock-frequency = <50000000>; + }; + clksrc_mipi0_dsi_byteclk: clksrc_mipi0_dsi_byteclk { + // This clock is synthesized by MIPI0 D-PHY, when DSI is running. + // Its frequency is not known a priori (until a panel driver attaches) + // so assign a made-up frequency of 72MHz so it can be divided for DPI. + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "clksrc_mipi0_dsi_byteclk"; + clock-frequency = <72000000>; + }; + clksrc_mipi1_dsi_byteclk: clksrc_mipi1_dsi_byteclk { + // This clock is synthesized by MIPI1 D-PHY, when DSI is running. + // Its frequency is not known a priori (until a panel driver attaches) + // so assign a made-up frequency of 72MHz so it can be divided for DPI. + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "clksrc_mipi1_dsi_byteclk"; + clock-frequency = <72000000>; + }; +}; + +/ { + rp1_vdd_3v3: rp1_vdd_3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/configs/bcm2709_defconfig linux/arch/arm/configs/bcm2709_defconfig --- linux-6.1.66/arch/arm/configs/bcm2709_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/configs/bcm2709_defconfig 2023-12-13 11:50:48.833961824 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +CONFIG_LOCALVERSION="-v7" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCM2835=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +# CONFIG_CPU_SW_DOMAIN_PAN is not set +CONFIG_UACCESS_WITH_MEMCPY=y +# CONFIG_ATAGS is not set +CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_RASPBERRYPI_CPUFREQ=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +# CONFIG_SUSPEND is not set +CONFIG_PM=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_COMPRESS_XZ=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y +CONFIG_BINFMT_MISC=m +CONFIG_ZSWAP=y +CONFIG_Z3FOLD=m +# CONFIG_COMPAT_BRK is not set +CONFIG_CMA=y +CONFIG_LRU_GEN=y +CONFIG_LRU_GEN_ENABLED=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU=m +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BBR=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_ATM=m +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_BATMAN_ADV=m +CONFIG_OPENVSWITCH=m +CONFIG_CGROUP_NET_PRIO=y +CONFIG_NET_PKTGEN=m +CONFIG_HAMRADIO=y +CONFIG_AX25=m +CONFIG_NETROM=m +CONFIG_ROSE=m +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_YAM=m +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_6LOWPAN=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_NET_9P=m +CONFIG_NFC=m +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_MTD=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK2MTD=m +CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_UBI=m +CONFIG_OF_CONFIGFS=y +CONFIG_ZRAM=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_TI_ST=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_ISCSI_ATTRS=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_ATA=m +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_DELAY=m +CONFIG_DM_INTEGRITY=m +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_IFB=m +CONFIG_MACVLAN=m +CONFIG_IPVLAN=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_TUN=m +CONFIG_VETH=m +CONFIG_NET_VRF=m +CONFIG_ENC28J60=m +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5100_SPI=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_MCP251X=m +CONFIG_CAN_MCP251XFD=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_MDIO_BITBANG=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=y +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_AQC111=m +CONFIG_ATH9K=m +CONFIG_ATH9K_HTC=m +CONFIG_CARL9170=m +CONFIG_ATH6KL=m +CONFIG_ATH6KL_USB=m +CONFIG_AR5523=m +CONFIG_AT76C50X_USB=m +CONFIG_B43=m +# CONFIG_B43_PHY_N is not set +CONFIG_B43LEGACY=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMDBG=y +CONFIG_HOSTAP=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x2U=m +CONFIG_MT7921U=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8187=m +CONFIG_RTL8192CU=m +CONFIG_RTL8XXXU=m +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_TCA6416=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_CAP11XX=m +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_RPISENSE=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_EGALAX=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_STMPE=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_CMA3000=m +CONFIG_SERIO=m +CONFIG_SERIO_RAW=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_BRCM_CHAR_DRIVERS=y +CONFIG_BCM_VCIO=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DMA is not set +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=0 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_BCM2835AUX=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_SPI=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=y +CONFIG_HW_RANDOM=y +CONFIG_TCG_TPM=m +CONFIG_TCG_TIS_SPI=m +CONFIG_TCG_TIS_I2C=m +CONFIG_RASPBERRYPI_GPIOMEM=m +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_PCA954x=m +CONFIG_I2C_MUX_PINCTRL=m +CONFIG_I2C_BCM2708=m +CONFIG_I2C_BCM2835=m +# CONFIG_I2C_BRCMSTB is not set +CONFIG_I2C_GPIO=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_TINY_USB=m +CONFIG_SPI=y +CONFIG_SPI_BCM2835=m +CONFIG_SPI_BCM2835AUX=m +CONFIG_SPI_GPIO=m +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SLAVE=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_BCM_VIRT=y +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_ARIZONA=m +CONFIG_GPIO_FSM=m +CONFIG_GPIO_STMPE=y +CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MOCKUP=m +CONFIG_W1=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_RPI_POE_POWER=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_MAX17040=m +CONFIG_CHARGER_GPIO=m +CONFIG_BATTERY_GAUGE_LTC2941=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_AHT10=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_RASPBERRYPI_HWMON=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_TMP102=m +CONFIG_BCM2835_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_GPIO_WATCHDOG=m +CONFIG_BCM2835_WDT=y +CONFIG_MFD_RASPBERRYPI_POE_HAT=m +CONFIG_MFD_STMPE=y +CONFIG_STMPE_SPI=y +CONFIG_MFD_ARIZONA_I2C=m +CONFIG_MFD_ARIZONA_SPI=m +CONFIG_MFD_WM5102=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=m +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m +CONFIG_RC_CORE=y +CONFIG_BPF_LIRC_MODE2=y +CONFIG_LIRC=y +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_LOOPBACK=m +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_DVB_AS102=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m +CONFIG_USB_DSBR=m +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_MR800=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_I2C_SI4713=m +CONFIG_RADIO_WL128X=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MUX=m +CONFIG_VIDEO_BCM2835_UNICAM=m +CONFIG_VIDEO_ARDUCAM_64MP=m +CONFIG_VIDEO_ARDUCAM_PIVARIETY=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX296=m +CONFIG_VIDEO_IMX477=m +CONFIG_VIDEO_IMX519=m +CONFIG_VIDEO_IMX708=m +CONFIG_VIDEO_MT9V011=m +CONFIG_VIDEO_OV2311=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV64A40=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV7640=m +CONFIG_VIDEO_AD5398=m +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_BU64754=m +CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_OV9281=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m +CONFIG_VIDEO_IRS1125=m +CONFIG_VIDEO_I2C=m +CONFIG_DRM=m +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_UDL=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +CONFIG_DRM_PANEL_SITRONIX_ST7701=m +CONFIG_DRM_PANEL_TPO_Y17P=m +CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_VC4=m +CONFIG_DRM_VC4_HDMI_CEC=y +CONFIG_DRM_PANEL_MIPI_DBI=m +CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m +CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m +CONFIG_TINYDRM_ST7735R=m +CONFIG_DRM_GUD=m +CONFIG_FB=y +CONFIG_FB_BCM2708=y +CONFIG_FB_SIMPLE=y +CONFIG_FB_SSD1307=m +CONFIG_FB_RPISENSE=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_RPI=m +CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_GPIO=m +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_PCM_OSS=m +CONFIG_SND_HRTIMER=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_MPU401=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_SOC=m +CONFIG_SND_BCM2835_SOC_I2S=m +CONFIG_SND_BCM2708_SOC_CHIPDIP_DAC=m +CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSHD=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADC=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADCPRO=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSDSP=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m +CONFIG_SND_BCM2708_SOC_PIFI_40=m +CONFIG_SND_BCM2708_SOC_RPI_CIRRUS=m +CONFIG_SND_BCM2708_SOC_RPI_DAC=m +CONFIG_SND_BCM2708_SOC_RPI_PROTO=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_BOTH=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_CODEC=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI=m +CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m +CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m +CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m +CONFIG_SND_AUDIOSENSE_PI=m +CONFIG_SND_DIGIDAC1_SOUNDCARD=m +CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m +CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO_V2=m +CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS=m +CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_BOSS2_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE=m +CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC=m +CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO=m +CONFIG_SND_PISOUND=m +CONFIG_SND_DACBERRY400=m +CONFIG_SND_SOC_AD193X_SPI=m +CONFIG_SND_SOC_AD193X_I2C=m +CONFIG_SND_SOC_ADAU1701=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_AK4554=m +CONFIG_SND_SOC_CS4265=m +CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_APPLE=m +CONFIG_HID_ASUS=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_HOLTEK=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_GYRATION=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_NINTENDO_FF=y +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PLAYSTATION=m +CONFIG_PLAYSTATION_FF=y +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_GREENASIA=m +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_MON=m +CONFIG_USB_DWCOTG=y +CONFIG_USB_PRINTER=m +CONFIG_USB_TMC=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VUDC=m +CONFIG_USB_DWC2=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_TEST=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_HID=m +CONFIG_USB_G_WEBCAM=m +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_BCM2835_MMC=y +CONFIG_MMC_BCM2835_DMA=y +CONFIG_MMC_BCM2835_SDHOST=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SPI=m +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA955X=m +CONFIG_LEDS_PCA963X=m +CONFIG_LEDS_PWM=y +CONFIG_LEDS_IS31FL32XX=m +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_INPUT=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_ACTPWR=y +CONFIG_ACCESSIBILITY=y +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_ISL12022=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_BQ32K=m +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_DS1302=m +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_RX4581=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_DMADEVICES=y +CONFIG_DMA_BCM2835=y +CONFIG_DMA_BCM2708=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_AUXDISPLAY=y +CONFIG_HD44780=m +CONFIG_UIO=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_R8712U=m +CONFIG_R8188EU=m +CONFIG_VT6656=m +CONFIG_STAGING_MEDIA=y +CONFIG_STAGING_MEDIA_DEPRECATED=y +CONFIG_VIDEO_CPIA2=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_USB_ZR364XX=m +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m +CONFIG_FB_TFT_HX8340BN=m +CONFIG_FB_TFT_HX8347D=m +CONFIG_FB_TFT_HX8353D=m +CONFIG_FB_TFT_HX8357D=m +CONFIG_FB_TFT_ILI9163=m +CONFIG_FB_TFT_ILI9320=m +CONFIG_FB_TFT_ILI9325=m +CONFIG_FB_TFT_ILI9340=m +CONFIG_FB_TFT_ILI9341=m +CONFIG_FB_TFT_ILI9481=m +CONFIG_FB_TFT_ILI9486=m +CONFIG_FB_TFT_PCD8544=m +CONFIG_FB_TFT_RA8875=m +CONFIG_FB_TFT_S6D02A1=m +CONFIG_FB_TFT_S6D1121=m +CONFIG_FB_TFT_SH1106=m +CONFIG_FB_TFT_SSD1289=m +CONFIG_FB_TFT_SSD1306=m +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m +CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m +CONFIG_BCM2835_VCHIQ=y +CONFIG_SND_BCM2835=m +CONFIG_VIDEO_BCM2835=m +CONFIG_VIDEO_CODEC_BCM2835=m +CONFIG_VIDEO_ISP_BCM2835=m +CONFIG_CLK_RASPBERRYPI=y +CONFIG_MAILBOX=y +CONFIG_BCM2835_MBOX=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RASPBERRYPI_POWER=y +CONFIG_IIO=m +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m +CONFIG_TI_ADS1015=m +CONFIG_BME680=m +CONFIG_CCS811=m +CONFIG_SENSIRION_SGP30=m +CONFIG_SPS30_I2C=m +CONFIG_MAX30102=m +CONFIG_DHT11=m +CONFIG_HDC100X=m +CONFIG_HTU21=m +CONFIG_SI7020=m +CONFIG_BOSCH_BNO055_I2C=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_APDS9960=m +CONFIG_BH1750=m +CONFIG_TSL4531=m +CONFIG_VEML6070=m +CONFIG_IIO_HRTIMER_TRIGGER=m +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_BMP280=m +CONFIG_MS5637=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_MAX31856=m +CONFIG_PWM=y +CONFIG_PWM_BCM2835=m +CONFIG_PWM_PCA9685=m +CONFIG_PWM_RASPBERRYPI_POE=m +CONFIG_RPI_AXIPERF=m +CONFIG_MUX_GPIO=m +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_REISERFS_FS=m +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +CONFIG_JFS_STATISTICS=y +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_GFS2_FS=m +CONFIG_OCFS2_FS=m +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FANOTIFY=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_NTFS3_FS=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=m +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_SUMMARY=y +CONFIG_UBIFS_FS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFSD=m +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_CEPH_FS=m +CONFIG_CIFS=m +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y +CONFIG_SMB_SERVER=m +CONFIG_9P_FS=m +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_DLM=m +CONFIG_SECURITY=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_LSM="" +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_SHA1_ARM_NEON=m +CONFIG_CRYPTO_AES_ARM=m +CONFIG_CRYPTO_AES_ARM_BS=m +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_ITU_T=y +CONFIG_LIBCRC32C=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=5 +CONFIG_PRINTK_TIME=y +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_KEYBOARD=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_RCU_TRACE is not set +CONFIG_LATENCYTOP=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_UPROBE_EVENTS is not set diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/configs/bcm2711_defconfig linux/arch/arm/configs/bcm2711_defconfig --- linux-6.1.66/arch/arm/configs/bcm2711_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/configs/bcm2711_defconfig 2023-12-13 11:50:48.834961826 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +CONFIG_LOCALVERSION="-v7l" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCM2835=y +CONFIG_ARM_LPAE=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_SMP=y +CONFIG_HIGHMEM=y +CONFIG_UACCESS_WITH_MEMCPY=y +# CONFIG_ATAGS is not set +CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_RASPBERRYPI_CPUFREQ=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +# CONFIG_SUSPEND is not set +CONFIG_PM=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_COMPRESS_XZ=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y +CONFIG_BINFMT_MISC=m +CONFIG_ZSWAP=y +CONFIG_Z3FOLD=m +# CONFIG_COMPAT_BRK is not set +CONFIG_CMA=y +CONFIG_LRU_GEN=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU=m +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BBR=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_ATM=m +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_BATMAN_ADV=m +CONFIG_OPENVSWITCH=m +CONFIG_CGROUP_NET_PRIO=y +CONFIG_NET_PKTGEN=m +CONFIG_HAMRADIO=y +CONFIG_AX25=m +CONFIG_NETROM=m +CONFIG_ROSE=m +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_YAM=m +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_6LOWPAN=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_NET_9P=m +CONFIG_NFC=m +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEASPM is not set +CONFIG_PCI_MSI=y +CONFIG_PCIE_BRCMSTB=y +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_MTD=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK2MTD=m +CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_UBI=m +CONFIG_OF_CONFIGFS=y +CONFIG_ZRAM=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_BLK_DEV_NVME=y +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_TI_ST=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_ISCSI_ATTRS=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_ATA=m +CONFIG_SATA_AHCI=m +CONFIG_SATA_MV=m +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_DELAY=m +CONFIG_DM_INTEGRITY=m +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_IFB=m +CONFIG_MACVLAN=m +CONFIG_IPVLAN=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_TUN=m +CONFIG_VETH=m +CONFIG_NET_VRF=m +CONFIG_BCMGENET=y +CONFIG_ENC28J60=m +CONFIG_LAN743X=m +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +CONFIG_R8169=m +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5100_SPI=m +CONFIG_MICREL_PHY=y +CONFIG_CAN_VCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_MCP251X=m +CONFIG_CAN_MCP251XFD=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_MDIO_BITBANG=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=y +CONFIG_USB_LAN78XX=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=y +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_AQC111=m +CONFIG_ATH9K=m +CONFIG_ATH9K_HTC=m +CONFIG_CARL9170=m +CONFIG_ATH6KL=m +CONFIG_ATH6KL_USB=m +CONFIG_AR5523=m +CONFIG_AT76C50X_USB=m +CONFIG_B43=m +# CONFIG_B43_PHY_N is not set +CONFIG_B43LEGACY=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMDBG=y +CONFIG_HOSTAP=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x2U=m +CONFIG_MT7921U=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8187=m +CONFIG_RTL8192CU=m +CONFIG_RTL8XXXU=m +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_TCA6416=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_CAP11XX=m +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_RPISENSE=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_EGALAX=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_STMPE=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_CMA3000=m +CONFIG_SERIO=m +CONFIG_SERIO_RAW=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_BRCM_CHAR_DRIVERS=y +CONFIG_BCM_VCIO=y +CONFIG_RPIVID_MEM=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DMA is not set +CONFIG_SERIAL_8250_NR_UARTS=5 +CONFIG_SERIAL_8250_RUNTIME_UARTS=0 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_BCM2835AUX=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_SPI=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=y +CONFIG_HW_RANDOM=y +CONFIG_TCG_TPM=m +CONFIG_TCG_TIS_SPI=m +CONFIG_TCG_TIS_I2C=m +CONFIG_XILLYBUS=m +CONFIG_XILLYBUS_PCIE=m +CONFIG_XILLYUSB=m +CONFIG_RASPBERRYPI_GPIOMEM=m +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_PCA954x=m +CONFIG_I2C_MUX_PINCTRL=m +CONFIG_I2C_BCM2708=m +CONFIG_I2C_BCM2835=m +CONFIG_I2C_BRCMSTB=m +CONFIG_I2C_GPIO=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_TINY_USB=m +CONFIG_SPI=y +CONFIG_SPI_BCM2835=m +CONFIG_SPI_BCM2835AUX=m +CONFIG_SPI_GPIO=m +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SLAVE=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_BCM_VIRT=y +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_ARIZONA=m +CONFIG_GPIO_FSM=m +CONFIG_GPIO_STMPE=y +CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MOCKUP=m +CONFIG_W1=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_RPI_POE_POWER=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_MAX17040=m +CONFIG_CHARGER_GPIO=m +CONFIG_BATTERY_GAUGE_LTC2941=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_AHT10=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_RASPBERRYPI_HWMON=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_TMP102=m +CONFIG_BCM2711_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_GPIO_WATCHDOG=m +CONFIG_BCM2835_WDT=y +CONFIG_MFD_RASPBERRYPI_POE_HAT=m +CONFIG_MFD_STMPE=y +CONFIG_STMPE_SPI=y +CONFIG_MFD_ARIZONA_I2C=m +CONFIG_MFD_ARIZONA_SPI=m +CONFIG_MFD_WM5102=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m +CONFIG_RC_CORE=y +CONFIG_BPF_LIRC_MODE2=y +CONFIG_LIRC=y +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_LOOPBACK=m +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_DVB_AS102=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m +CONFIG_USB_DSBR=m +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_MR800=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_I2C_SI4713=m +CONFIG_RADIO_WL128X=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MUX=m +CONFIG_VIDEO_BCM2835_UNICAM=m +CONFIG_VIDEO_ARDUCAM_64MP=m +CONFIG_VIDEO_ARDUCAM_PIVARIETY=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX296=m +CONFIG_VIDEO_IMX477=m +CONFIG_VIDEO_IMX519=m +CONFIG_VIDEO_IMX708=m +CONFIG_VIDEO_MT9V011=m +CONFIG_VIDEO_OV2311=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV64A40=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV7640=m +CONFIG_VIDEO_AD5398=m +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_BU64754=m +CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_OV9281=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m +CONFIG_VIDEO_IRS1125=m +CONFIG_VIDEO_I2C=m +CONFIG_DRM=m +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_UDL=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m +CONFIG_DRM_PANEL_ILITEK_ILI9881C=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +CONFIG_DRM_PANEL_SITRONIX_ST7701=m +CONFIG_DRM_PANEL_TPO_Y17P=m +CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_V3D=m +CONFIG_DRM_VC4=m +CONFIG_DRM_VC4_HDMI_CEC=y +CONFIG_DRM_PANEL_MIPI_DBI=m +CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m +CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m +CONFIG_TINYDRM_ST7735R=m +CONFIG_DRM_GUD=m +CONFIG_FB=y +CONFIG_FB_BCM2708=y +CONFIG_FB_SIMPLE=y +CONFIG_FB_SSD1307=m +CONFIG_FB_RPISENSE=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_RPI=m +CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_GPIO=m +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_PCM_OSS=m +CONFIG_SND_HRTIMER=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_MPU401=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_SOC=m +CONFIG_SND_BCM2835_SOC_I2S=m +CONFIG_SND_BCM2708_SOC_CHIPDIP_DAC=m +CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSHD=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADC=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADCPRO=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSDSP=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m +CONFIG_SND_BCM2708_SOC_PIFI_40=m +CONFIG_SND_BCM2708_SOC_RPI_CIRRUS=m +CONFIG_SND_BCM2708_SOC_RPI_DAC=m +CONFIG_SND_BCM2708_SOC_RPI_PROTO=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_BOTH=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_CODEC=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI=m +CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m +CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m +CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m +CONFIG_SND_AUDIOSENSE_PI=m +CONFIG_SND_DIGIDAC1_SOUNDCARD=m +CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m +CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO_V2=m +CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS=m +CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_BOSS2_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE=m +CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC=m +CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO=m +CONFIG_SND_PISOUND=m +CONFIG_SND_DACBERRY400=m +CONFIG_SND_SOC_AD193X_SPI=m +CONFIG_SND_SOC_AD193X_I2C=m +CONFIG_SND_SOC_ADAU1701=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_AK4554=m +CONFIG_SND_SOC_CS4265=m +CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_APPLE=m +CONFIG_HID_ASUS=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_HOLTEK=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_GYRATION=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_NINTENDO_FF=y +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PLAYSTATION=m +CONFIG_PLAYSTATION_FF=y +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_GREENASIA=m +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_MON=m +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_DWCOTG=y +CONFIG_USB_PRINTER=m +CONFIG_USB_TMC=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=y +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VUDC=m +CONFIG_USB_DWC2=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_TEST=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_HID=m +CONFIG_USB_G_WEBCAM=m +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_BCM2835_MMC=y +CONFIG_MMC_BCM2835_DMA=y +CONFIG_MMC_BCM2835_SDHOST=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_IPROC=y +CONFIG_MMC_SPI=m +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA955X=m +CONFIG_LEDS_PCA963X=m +CONFIG_LEDS_PWM=y +CONFIG_LEDS_IS31FL32XX=m +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_INPUT=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_ACTPWR=y +CONFIG_ACCESSIBILITY=y +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_ISL12022=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_BQ32K=m +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_DS1302=m +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_RX4581=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_DMADEVICES=y +CONFIG_DMA_BCM2835=y +CONFIG_DMA_BCM2708=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_AUXDISPLAY=y +CONFIG_HD44780=m +CONFIG_UIO=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_R8712U=m +CONFIG_R8188EU=m +CONFIG_VT6656=m +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_RPIVID=m +CONFIG_STAGING_MEDIA_DEPRECATED=y +CONFIG_VIDEO_CPIA2=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_USB_ZR364XX=m +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m +CONFIG_FB_TFT_HX8340BN=m +CONFIG_FB_TFT_HX8347D=m +CONFIG_FB_TFT_HX8353D=m +CONFIG_FB_TFT_HX8357D=m +CONFIG_FB_TFT_ILI9163=m +CONFIG_FB_TFT_ILI9320=m +CONFIG_FB_TFT_ILI9325=m +CONFIG_FB_TFT_ILI9340=m +CONFIG_FB_TFT_ILI9341=m +CONFIG_FB_TFT_ILI9481=m +CONFIG_FB_TFT_ILI9486=m +CONFIG_FB_TFT_PCD8544=m +CONFIG_FB_TFT_RA8875=m +CONFIG_FB_TFT_S6D02A1=m +CONFIG_FB_TFT_S6D1121=m +CONFIG_FB_TFT_SH1106=m +CONFIG_FB_TFT_SSD1289=m +CONFIG_FB_TFT_SSD1306=m +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m +CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m +CONFIG_BCM2835_VCHIQ=y +CONFIG_SND_BCM2835=m +CONFIG_VIDEO_BCM2835=m +CONFIG_VIDEO_CODEC_BCM2835=m +CONFIG_VIDEO_ISP_BCM2835=m +CONFIG_CLK_RASPBERRYPI=y +CONFIG_MAILBOX=y +CONFIG_BCM2835_MBOX=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RASPBERRYPI_POWER=y +CONFIG_IIO=m +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m +CONFIG_TI_ADS1015=m +CONFIG_BME680=m +CONFIG_CCS811=m +CONFIG_SENSIRION_SGP30=m +CONFIG_SPS30_I2C=m +CONFIG_MAX30102=m +CONFIG_DHT11=m +CONFIG_HDC100X=m +CONFIG_HTU21=m +CONFIG_SI7020=m +CONFIG_BOSCH_BNO055_I2C=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_APDS9960=m +CONFIG_BH1750=m +CONFIG_TSL4531=m +CONFIG_VEML6070=m +CONFIG_IIO_HRTIMER_TRIGGER=m +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_BMP280=m +CONFIG_MS5637=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_MAX31856=m +CONFIG_PWM=y +CONFIG_PWM_BCM2835=m +CONFIG_PWM_PCA9685=m +CONFIG_PWM_RASPBERRYPI_POE=m +CONFIG_RPI_AXIPERF=m +CONFIG_NVMEM_RMEM=m +CONFIG_MUX_GPIO=m +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_REISERFS_FS=m +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +CONFIG_JFS_STATISTICS=y +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_GFS2_FS=m +CONFIG_OCFS2_FS=m +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FANOTIFY=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_NTFS3_FS=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=m +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_SUMMARY=y +CONFIG_UBIFS_FS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFSD=m +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_CEPH_FS=m +CONFIG_CIFS=m +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y +CONFIG_SMB_SERVER=m +CONFIG_9P_FS=m +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_DLM=m +CONFIG_SECURITY=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_LSM="" +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_SHA1_ARM_NEON=m +CONFIG_CRYPTO_AES_ARM=m +CONFIG_CRYPTO_AES_ARM_BS=m +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_ITU_T=y +CONFIG_LIBCRC32C=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=5 +CONFIG_PRINTK_TIME=y +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_KEYBOARD=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_RCU_TRACE is not set +CONFIG_LATENCYTOP=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_UPROBE_EVENTS is not set diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/configs/bcmrpi_defconfig linux/arch/arm/configs/bcmrpi_defconfig --- linux-6.1.66/arch/arm/configs/bcmrpi_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/configs/bcmrpi_defconfig 2023-12-13 11:50:48.834961826 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_ARCH_MULTI_V6=y +# CONFIG_ARCH_MULTI_V7 is not set +CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCM2835=y +# CONFIG_CACHE_L2X0 is not set +# CONFIG_CPU_SW_DOMAIN_PAN is not set +CONFIG_UACCESS_WITH_MEMCPY=y +# CONFIG_ATAGS is not set +CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_RASPBERRYPI_CPUFREQ=y +CONFIG_VFP=y +# CONFIG_SUSPEND is not set +CONFIG_PM=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_COMPRESS_XZ=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y +CONFIG_BINFMT_MISC=m +CONFIG_ZSWAP=y +CONFIG_Z3FOLD=m +# CONFIG_COMPAT_BRK is not set +CONFIG_CMA=y +CONFIG_LRU_GEN=y +CONFIG_LRU_GEN_ENABLED=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU=m +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BBR=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_ATM=m +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_BATMAN_ADV=m +CONFIG_OPENVSWITCH=m +CONFIG_CGROUP_NET_PRIO=y +CONFIG_NET_PKTGEN=m +CONFIG_HAMRADIO=y +CONFIG_AX25=m +CONFIG_NETROM=m +CONFIG_ROSE=m +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_YAM=m +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_6LOWPAN=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_NET_9P=m +CONFIG_NFC=m +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_MTD=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK2MTD=m +CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_UBI=m +CONFIG_OF_CONFIGFS=y +CONFIG_ZRAM=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_TI_ST=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_ISCSI_ATTRS=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_ATA=m +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_DELAY=m +CONFIG_DM_INTEGRITY=m +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_IFB=m +CONFIG_MACVLAN=m +CONFIG_IPVLAN=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_TUN=m +CONFIG_VETH=m +CONFIG_NET_VRF=m +CONFIG_ENC28J60=m +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5100_SPI=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_MCP251X=m +CONFIG_CAN_MCP251XFD=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_MDIO_BITBANG=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=y +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_AQC111=m +CONFIG_ATH9K=m +CONFIG_ATH9K_HTC=m +CONFIG_CARL9170=m +CONFIG_ATH6KL=m +CONFIG_ATH6KL_USB=m +CONFIG_AR5523=m +CONFIG_AT76C50X_USB=m +CONFIG_B43=m +# CONFIG_B43_PHY_N is not set +CONFIG_B43LEGACY=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMDBG=y +CONFIG_HOSTAP=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x2U=m +CONFIG_MT7921U=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8187=m +CONFIG_RTL8192CU=m +CONFIG_RTL8XXXU=m +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_TCA6416=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_CAP11XX=m +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_RPISENSE=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_EGALAX=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_STMPE=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_CMA3000=m +CONFIG_SERIO=m +CONFIG_SERIO_RAW=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_BRCM_CHAR_DRIVERS=y +CONFIG_BCM_VCIO=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DMA is not set +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=0 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_BCM2835AUX=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_SPI=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=y +CONFIG_HW_RANDOM=y +CONFIG_TCG_TPM=m +CONFIG_TCG_TIS_SPI=m +CONFIG_TCG_TIS_I2C=m +CONFIG_RASPBERRYPI_GPIOMEM=m +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_PCA954x=m +CONFIG_I2C_MUX_PINCTRL=m +CONFIG_I2C_BCM2708=m +CONFIG_I2C_BCM2835=m +# CONFIG_I2C_BRCMSTB is not set +CONFIG_I2C_GPIO=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_TINY_USB=m +CONFIG_SPI=y +CONFIG_SPI_BCM2835=m +CONFIG_SPI_BCM2835AUX=m +CONFIG_SPI_GPIO=m +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SLAVE=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_ARIZONA=m +CONFIG_GPIO_FSM=m +CONFIG_GPIO_STMPE=y +CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MOCKUP=m +CONFIG_W1=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_RPI_POE_POWER=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_MAX17040=m +CONFIG_CHARGER_GPIO=m +CONFIG_BATTERY_GAUGE_LTC2941=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_AHT10=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_RASPBERRYPI_HWMON=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_TMP102=m +CONFIG_BCM2835_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_GPIO_WATCHDOG=m +CONFIG_BCM2835_WDT=y +CONFIG_MFD_RASPBERRYPI_POE_HAT=m +CONFIG_MFD_STMPE=y +CONFIG_STMPE_SPI=y +CONFIG_MFD_ARIZONA_I2C=m +CONFIG_MFD_ARIZONA_SPI=m +CONFIG_MFD_WM5102=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=m +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m +CONFIG_RC_CORE=y +CONFIG_BPF_LIRC_MODE2=y +CONFIG_LIRC=y +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_LOOPBACK=m +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_DVB_AS102=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m +CONFIG_USB_DSBR=m +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_MR800=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_I2C_SI4713=m +CONFIG_RADIO_WL128X=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MUX=m +CONFIG_VIDEO_BCM2835_UNICAM=m +CONFIG_VIDEO_ARDUCAM_64MP=m +CONFIG_VIDEO_ARDUCAM_PIVARIETY=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX296=m +CONFIG_VIDEO_IMX477=m +CONFIG_VIDEO_IMX519=m +CONFIG_VIDEO_IMX708=m +CONFIG_VIDEO_MT9V011=m +CONFIG_VIDEO_OV2311=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV64A40=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV7640=m +CONFIG_VIDEO_AD5398=m +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_BU64754=m +CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_OV9281=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m +CONFIG_VIDEO_IRS1125=m +CONFIG_VIDEO_I2C=m +CONFIG_DRM=m +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_UDL=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +CONFIG_DRM_PANEL_SITRONIX_ST7701=m +CONFIG_DRM_PANEL_TPO_Y17P=m +CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_VC4=m +CONFIG_DRM_VC4_HDMI_CEC=y +CONFIG_DRM_PANEL_MIPI_DBI=m +CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m +CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m +CONFIG_TINYDRM_ST7735R=m +CONFIG_DRM_GUD=m +CONFIG_FB=y +CONFIG_FB_BCM2708=y +CONFIG_FB_SIMPLE=y +CONFIG_FB_SSD1307=m +CONFIG_FB_RPISENSE=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_RPI=m +CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_GPIO=m +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_PCM_OSS=m +CONFIG_SND_HRTIMER=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_MPU401=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_SOC=m +CONFIG_SND_BCM2835_SOC_I2S=m +CONFIG_SND_BCM2708_SOC_CHIPDIP_DAC=m +CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSHD=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADC=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADCPRO=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSDSP=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m +CONFIG_SND_BCM2708_SOC_PIFI_40=m +CONFIG_SND_BCM2708_SOC_RPI_CIRRUS=m +CONFIG_SND_BCM2708_SOC_RPI_DAC=m +CONFIG_SND_BCM2708_SOC_RPI_PROTO=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_BOTH=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_CODEC=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI=m +CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m +CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m +CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m +CONFIG_SND_AUDIOSENSE_PI=m +CONFIG_SND_DIGIDAC1_SOUNDCARD=m +CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m +CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO_V2=m +CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS=m +CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_BOSS2_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE=m +CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC=m +CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO=m +CONFIG_SND_PISOUND=m +CONFIG_SND_SOC_AD193X_SPI=m +CONFIG_SND_SOC_AD193X_I2C=m +CONFIG_SND_SOC_ADAU1701=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_AK4554=m +CONFIG_SND_SOC_CS4265=m +CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_APPLE=m +CONFIG_HID_ASUS=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_HOLTEK=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_GYRATION=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_NINTENDO_FF=y +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PLAYSTATION=m +CONFIG_PLAYSTATION_FF=y +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_GREENASIA=m +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_MON=m +CONFIG_USB_DWCOTG=y +CONFIG_USB_PRINTER=m +CONFIG_USB_TMC=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VUDC=m +CONFIG_USB_DWC2=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_TEST=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_HID=m +CONFIG_USB_G_WEBCAM=m +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_BCM2835_MMC=y +CONFIG_MMC_BCM2835_DMA=y +CONFIG_MMC_BCM2835_SDHOST=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SPI=m +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA955X=m +CONFIG_LEDS_PCA963X=m +CONFIG_LEDS_PWM=y +CONFIG_LEDS_IS31FL32XX=m +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_INPUT=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_ACTPWR=y +CONFIG_ACCESSIBILITY=y +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_ISL12022=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_BQ32K=m +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_DS1302=m +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_RX4581=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_DMADEVICES=y +CONFIG_DMA_BCM2835=y +CONFIG_DMA_BCM2708=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_AUXDISPLAY=y +CONFIG_HD44780=m +CONFIG_UIO=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_R8712U=m +CONFIG_R8188EU=m +CONFIG_VT6656=m +CONFIG_STAGING_MEDIA=y +CONFIG_STAGING_MEDIA_DEPRECATED=y +CONFIG_VIDEO_CPIA2=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_USB_ZR364XX=m +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m +CONFIG_FB_TFT_HX8340BN=m +CONFIG_FB_TFT_HX8347D=m +CONFIG_FB_TFT_HX8353D=m +CONFIG_FB_TFT_HX8357D=m +CONFIG_FB_TFT_ILI9163=m +CONFIG_FB_TFT_ILI9320=m +CONFIG_FB_TFT_ILI9325=m +CONFIG_FB_TFT_ILI9340=m +CONFIG_FB_TFT_ILI9341=m +CONFIG_FB_TFT_ILI9481=m +CONFIG_FB_TFT_ILI9486=m +CONFIG_FB_TFT_PCD8544=m +CONFIG_FB_TFT_RA8875=m +CONFIG_FB_TFT_S6D02A1=m +CONFIG_FB_TFT_S6D1121=m +CONFIG_FB_TFT_SH1106=m +CONFIG_FB_TFT_SSD1289=m +CONFIG_FB_TFT_SSD1306=m +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m +CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m +CONFIG_BCM2835_VCHIQ=y +CONFIG_SND_BCM2835=m +CONFIG_VIDEO_BCM2835=m +CONFIG_VIDEO_CODEC_BCM2835=m +CONFIG_VIDEO_ISP_BCM2835=m +CONFIG_CLK_RASPBERRYPI=y +CONFIG_MAILBOX=y +CONFIG_BCM2835_MBOX=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RASPBERRYPI_POWER=y +CONFIG_IIO=m +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m +CONFIG_TI_ADS1015=m +CONFIG_BME680=m +CONFIG_CCS811=m +CONFIG_SENSIRION_SGP30=m +CONFIG_SPS30_I2C=m +CONFIG_MAX30102=m +CONFIG_DHT11=m +CONFIG_HDC100X=m +CONFIG_HTU21=m +CONFIG_SI7020=m +CONFIG_BOSCH_BNO055_I2C=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_APDS9960=m +CONFIG_BH1750=m +CONFIG_TSL4531=m +CONFIG_VEML6070=m +CONFIG_IIO_HRTIMER_TRIGGER=m +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_BMP280=m +CONFIG_MS5637=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_MAX31856=m +CONFIG_PWM=y +CONFIG_PWM_BCM2835=m +CONFIG_PWM_PCA9685=m +CONFIG_PWM_RASPBERRYPI_POE=m +CONFIG_RPI_AXIPERF=m +CONFIG_MUX_GPIO=m +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_REISERFS_FS=m +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +CONFIG_JFS_STATISTICS=y +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_GFS2_FS=m +CONFIG_OCFS2_FS=m +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_FANOTIFY=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_NTFS3_FS=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=m +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_SUMMARY=y +CONFIG_UBIFS_FS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFSD=m +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_CEPH_FS=m +CONFIG_CIFS=m +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y +CONFIG_SMB_SERVER=m +CONFIG_9P_FS=m +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_DLM=m +CONFIG_SECURITY=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_LSM="" +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_SHA1_ARM=m +CONFIG_CRYPTO_AES_ARM=m +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_ITU_T=y +CONFIG_LIBCRC32C=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=5 +CONFIG_PRINTK_TIME=y +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_KEYBOARD=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_LATENCYTOP=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_UPROBE_EVENTS is not set diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/include/asm/cacheflush.h linux/arch/arm/include/asm/cacheflush.h --- linux-6.1.66/arch/arm/include/asm/cacheflush.h 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/include/asm/cacheflush.h 2023-12-13 11:50:48.865961899 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:94 @ * DMA Cache Coherency * =================== * + * dma_inv_range(start, end) + * + * Invalidate (discard) the specified virtual address range. + * May not write back any entries. If 'start' or 'end' + * are not cache line aligned, those lines must be written + * back. + * - start - virtual start address + * - end - virtual end address + * + * dma_clean_range(start, end) + * + * Clean (write back) the specified virtual address range. + * - start - virtual start address + * - end - virtual end address + * * dma_flush_range(start, end) * * Clean and invalidate the specified virtual address range. @ linux/arch/arm/boot/dts/bcm2708.dtsi:130 @ void (*dma_map_area)(const void *, size_t, int); void (*dma_unmap_area)(const void *, size_t, int); + void (*dma_inv_range)(const void *, const void *); + void (*dma_clean_range)(const void *, const void *); void (*dma_flush_range)(const void *, const void *); } __no_randomize_layout; @ linux/arch/arm/boot/dts/bcm2708.dtsi:157 @ * is visible to DMA, or data written by DMA to system memory is * visible to the CPU. */ +#define dmac_inv_range cpu_cache.dma_inv_range +#define dmac_clean_range cpu_cache.dma_clean_range #define dmac_flush_range cpu_cache.dma_flush_range #else @ linux/arch/arm/boot/dts/bcm2708.dtsi:178 @ * is visible to DMA, or data written by DMA to system memory is * visible to the CPU. */ +extern void dmac_inv_range(const void *, const void *); +extern void dmac_clean_range(const void *, const void *); extern void dmac_flush_range(const void *, const void *); #endif diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/include/asm/glue-cache.h linux/arch/arm/include/asm/glue-cache.h --- linux-6.1.66/arch/arm/include/asm/glue-cache.h 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/include/asm/glue-cache.h 2023-12-13 11:50:48.871961913 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:158 @ #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) +#define dmac_inv_range __glue(_CACHE,_dma_inv_range) +#define dmac_clean_range __glue(_CACHE,_dma_clean_range) #define dmac_flush_range __glue(_CACHE,_dma_flush_range) #endif diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/include/asm/irqflags.h linux/arch/arm/include/asm/irqflags.h --- linux-6.1.66/arch/arm/include/asm/irqflags.h 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/include/asm/irqflags.h 2023-12-13 11:50:48.877961927 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:166 @ } /* - * restore saved IRQ & FIQ state + * restore saved IRQ state */ #define arch_local_irq_restore arch_local_irq_restore static inline void arch_local_irq_restore(unsigned long flags) { - asm volatile( - " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore" + unsigned long temp = 0; + flags &= ~(1 << 6); + asm volatile ( + " mrs %0, cpsr" + : "=r" (temp) + : + : "memory", "cc"); + /* Preserve FIQ bit */ + temp &= (1 << 6); + flags = flags | temp; + asm volatile ( + " msr cpsr_c, %0 @ local_irq_restore" : : "r" (flags) : "memory", "cc"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/include/asm/string.h linux/arch/arm/include/asm/string.h --- linux-6.1.66/arch/arm/include/asm/string.h 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/include/asm/string.h 2023-12-13 11:50:48.890961958 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:68 @ #endif +#ifdef CONFIG_BCM2835_FAST_MEMCPY +#define __HAVE_ARCH_MEMCMP +extern int memcmp(const void *, const void *, size_t); +#endif + #endif diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/include/asm/uaccess.h linux/arch/arm/include/asm/uaccess.h --- linux-6.1.66/arch/arm/include/asm/uaccess.h 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/include/asm/uaccess.h 2023-12-13 11:50:48.893961965 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:512 @ extern unsigned long __must_check arm_copy_from_user(void *to, const void __user *from, unsigned long n); +extern unsigned long __must_check +__copy_from_user_std(void *to, const void __user *from, unsigned long n); + static inline unsigned long __must_check raw_copy_from_user(void *to, const void __user *from, unsigned long n) { diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/kernel/fiqasm.S linux/arch/arm/kernel/fiqasm.S --- linux-6.1.66/arch/arm/kernel/fiqasm.S 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/kernel/fiqasm.S 2023-12-13 11:50:48.911962008 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:50 @ mov r0, r0 @ avoid hazard prior to ARMv4 ret lr ENDPROC(__get_fiq_regs) + +ENTRY(__FIQ_Branch) + mov pc, r8 +ENDPROC(__FIQ_Branch) diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/kernel/fiq.c linux/arch/arm/kernel/fiq.c --- linux-6.1.66/arch/arm/kernel/fiq.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/kernel/fiq.c 2023-12-13 11:50:48.911962008 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:59 @ static unsigned long dfl_fiq_insn; static struct pt_regs dfl_fiq_regs; +extern int irq_activate(struct irq_desc *desc); + /* Default reacquire function * - we always relinquish FIQ control * - we always reacquire FIQ control @ linux/arch/arm/boot/dts/bcm2708.dtsi:145 @ void enable_fiq(int fiq) { + struct irq_desc *desc = irq_to_desc(fiq + fiq_start); + irq_activate(desc); enable_irq(fiq + fiq_start); } diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/kernel/reboot.c linux/arch/arm/kernel/reboot.c --- linux-6.1.66/arch/arm/kernel/reboot.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/kernel/reboot.c 2023-12-13 11:50:48.920962029 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:105 @ */ void machine_halt(void) { - local_irq_disable(); - smp_send_stop(); - while (1); + machine_power_off(); } /* diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/kernel/setup.c linux/arch/arm/kernel/setup.c --- linux-6.1.66/arch/arm/kernel/setup.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/kernel/setup.c 2023-12-13 11:50:48.921962031 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1268 @ { int i, j; u32 cpuid; + struct device_node *np; + const char *model; for_each_online_cpu(i) { /* @ linux/arch/arm/boot/dts/bcm2708.dtsi:1329 @ seq_printf(m, "Revision\t: %04x\n", system_rev); seq_printf(m, "Serial\t\t: %s\n", system_serial); + np = of_find_node_by_path("/"); + if (np) { + if (!of_property_read_string(np, "model", + &model)) + seq_printf(m, "Model\t\t: %s\n", model); + of_node_put(np); + } + return 0; } diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/lib/arm-mem.h linux/arch/arm/lib/arm-mem.h --- linux-6.1.66/arch/arm/lib/arm-mem.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/lib/arm-mem.h 2023-12-13 11:50:48.927962045 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* +Copyright (c) 2013, Raspberry Pi Foundation +Copyright (c) 2013, RISC OS Open Ltd +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the copyright holder nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +.macro myfunc fname + .func fname + .global fname +fname: +.endm + +.macro preload_leading_step1 backwards, ptr, base +/* If the destination is already 16-byte aligned, then we need to preload + * between 0 and prefetch_distance (inclusive) cache lines ahead so there + * are no gaps when the inner loop starts. + */ + .if backwards + sub ptr, base, #1 + bic ptr, ptr, #31 + .else + bic ptr, base, #31 + .endif + .set OFFSET, 0 + .rept prefetch_distance+1 + pld [ptr, #OFFSET] + .if backwards + .set OFFSET, OFFSET-32 + .else + .set OFFSET, OFFSET+32 + .endif + .endr +.endm + +.macro preload_leading_step2 backwards, ptr, base, leading_bytes, tmp +/* However, if the destination is not 16-byte aligned, we may need to + * preload one more cache line than that. The question we need to ask is: + * are the leading bytes more than the amount by which the source + * pointer will be rounded down for preloading, and if so, by how many + * cache lines? + */ + .if backwards +/* Here we compare against how many bytes we are into the + * cache line, counting down from the highest such address. + * Effectively, we want to calculate + * leading_bytes = dst&15 + * cacheline_offset = 31-((src-leading_bytes-1)&31) + * extra_needed = leading_bytes - cacheline_offset + * and test if extra_needed is <= 0, or rearranging: + * leading_bytes + (src-leading_bytes-1)&31 <= 31 + */ + mov tmp, base, lsl #32-5 + sbc tmp, tmp, leading_bytes, lsl #32-5 + adds tmp, tmp, leading_bytes, lsl #32-5 + bcc 61f + pld [ptr, #-32*(prefetch_distance+1)] + .else +/* Effectively, we want to calculate + * leading_bytes = (-dst)&15 + * cacheline_offset = (src+leading_bytes)&31 + * extra_needed = leading_bytes - cacheline_offset + * and test if extra_needed is <= 0. + */ + mov tmp, base, lsl #32-5 + add tmp, tmp, leading_bytes, lsl #32-5 + rsbs tmp, tmp, leading_bytes, lsl #32-5 + bls 61f + pld [ptr, #32*(prefetch_distance+1)] + .endif +61: +.endm + +.macro preload_trailing backwards, base, remain, tmp + /* We need either 0, 1 or 2 extra preloads */ + .if backwards + rsb tmp, base, #0 + mov tmp, tmp, lsl #32-5 + .else + mov tmp, base, lsl #32-5 + .endif + adds tmp, tmp, remain, lsl #32-5 + adceqs tmp, tmp, #0 + /* The instruction above has two effects: ensures Z is only + * set if C was clear (so Z indicates that both shifted quantities + * were 0), and clears C if Z was set (so C indicates that the sum + * of the shifted quantities was greater and not equal to 32) */ + beq 82f + .if backwards + sub tmp, base, #1 + bic tmp, tmp, #31 + .else + bic tmp, base, #31 + .endif + bcc 81f + .if backwards + pld [tmp, #-32*(prefetch_distance+1)] +81: + pld [tmp, #-32*prefetch_distance] + .else + pld [tmp, #32*(prefetch_distance+2)] +81: + pld [tmp, #32*(prefetch_distance+1)] + .endif +82: +.endm + +.macro preload_all backwards, narrow_case, shift, base, remain, tmp0, tmp1 + .if backwards + sub tmp0, base, #1 + bic tmp0, tmp0, #31 + pld [tmp0] + sub tmp1, base, remain, lsl #shift + .else + bic tmp0, base, #31 + pld [tmp0] + add tmp1, base, remain, lsl #shift + sub tmp1, tmp1, #1 + .endif + bic tmp1, tmp1, #31 + cmp tmp1, tmp0 + beq 92f + .if narrow_case + /* In this case, all the data fits in either 1 or 2 cache lines */ + pld [tmp1] + .else +91: + .if backwards + sub tmp0, tmp0, #32 + .else + add tmp0, tmp0, #32 + .endif + cmp tmp0, tmp1 + pld [tmp0] + bne 91b + .endif +92: +.endm diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/lib/copy_from_user.S linux/arch/arm/lib/copy_from_user.S --- linux-6.1.66/arch/arm/lib/copy_from_user.S 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/lib/copy_from_user.S 2023-12-13 11:50:48.928962047 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:107 @ .text -ENTRY(arm_copy_from_user) +ENTRY(__copy_from_user_std) +WEAK(arm_copy_from_user) #ifdef CONFIG_CPU_SPECTRE ldr r3, =TASK_SIZE uaccess_mask_range_ptr r1, r2, r3, ip @ linux/arch/arm/boot/dts/bcm2708.dtsi:117 @ #include "copy_template.S" ENDPROC(arm_copy_from_user) +ENDPROC(__copy_from_user_std) .pushsection .text.fixup,"ax" .align 0 diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/lib/exports_rpi.c linux/arch/arm/lib/exports_rpi.c --- linux-6.1.66/arch/arm/lib/exports_rpi.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/lib/exports_rpi.c 2023-12-13 11:50:48.931962055 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/** + * Copyright (c) 2014, Raspberry Pi (Trading) Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2, as published by the Free + * Software Foundation. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <linux/kernel.h> +#include <linux/module.h> + +EXPORT_SYMBOL(memcmp); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/lib/Makefile linux/arch/arm/lib/Makefile --- linux-6.1.66/arch/arm/lib/Makefile 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/lib/Makefile 2023-12-13 11:50:48.927962045 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:10 @ lib-y := changebit.o csumipv6.o csumpartial.o \ csumpartialcopy.o csumpartialcopyuser.o clearbit.o \ - delay.o delay-loop.o findbit.o memchr.o memcpy.o \ - memmove.o memset.o setbit.o \ + delay.o delay-loop.o findbit.o memchr.o \ + setbit.o \ strchr.o strrchr.o \ testchangebit.o testclearbit.o testsetbit.o \ ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \ @ linux/arch/arm/boot/dts/bcm2708.dtsi:28 @ lib-y += backtrace.o endif +# Choose optimised implementations for Raspberry Pi +ifeq ($(CONFIG_BCM2835_FAST_MEMCPY),y) + CFLAGS_uaccess_with_memcpy.o += -DCOPY_FROM_USER_THRESHOLD=1600 + CFLAGS_uaccess_with_memcpy.o += -DCOPY_TO_USER_THRESHOLD=672 + obj-$(CONFIG_MODULES) += exports_rpi.o + lib-y += memcpy_rpi.o memmove_rpi.o memset_rpi.o memcmp_rpi.o +else + lib-y += memcpy.o memmove.o memset.o +endif + # using lib_ here won't override already available weak symbols obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/lib/memcmp_rpi.S linux/arch/arm/lib/memcmp_rpi.S --- linux-6.1.66/arch/arm/lib/memcmp_rpi.S 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/lib/memcmp_rpi.S 2023-12-13 11:50:48.933962059 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* +Copyright (c) 2013, Raspberry Pi Foundation +Copyright (c) 2013, RISC OS Open Ltd +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the copyright holder nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include <linux/linkage.h> +#include "arm-mem.h" + +/* Prevent the stack from becoming executable */ +#if defined(__linux__) && defined(__ELF__) +.section .note.GNU-stack,"",%progbits +#endif + + .text + .arch armv6 + .object_arch armv4 + .arm + .altmacro + .p2align 2 + +.macro memcmp_process_head unaligned + .if unaligned + ldr DAT0, [S_1], #4 + ldr DAT1, [S_1], #4 + ldr DAT2, [S_1], #4 + ldr DAT3, [S_1], #4 + .else + ldmia S_1!, {DAT0, DAT1, DAT2, DAT3} + .endif + ldmia S_2!, {DAT4, DAT5, DAT6, DAT7} +.endm + +.macro memcmp_process_tail + cmp DAT0, DAT4 + cmpeq DAT1, DAT5 + cmpeq DAT2, DAT6 + cmpeq DAT3, DAT7 + bne 200f +.endm + +.macro memcmp_leading_31bytes + movs DAT0, OFF, lsl #31 + ldrmib DAT0, [S_1], #1 + ldrcsh DAT1, [S_1], #2 + ldrmib DAT4, [S_2], #1 + ldrcsh DAT5, [S_2], #2 + movpl DAT0, #0 + movcc DAT1, #0 + movpl DAT4, #0 + movcc DAT5, #0 + submi N, N, #1 + subcs N, N, #2 + cmp DAT0, DAT4 + cmpeq DAT1, DAT5 + bne 200f + movs DAT0, OFF, lsl #29 + ldrmi DAT0, [S_1], #4 + ldrcs DAT1, [S_1], #4 + ldrcs DAT2, [S_1], #4 + ldrmi DAT4, [S_2], #4 + ldmcsia S_2!, {DAT5, DAT6} + movpl DAT0, #0 + movcc DAT1, #0 + movcc DAT2, #0 + movpl DAT4, #0 + movcc DAT5, #0 + movcc DAT6, #0 + submi N, N, #4 + subcs N, N, #8 + cmp DAT0, DAT4 + cmpeq DAT1, DAT5 + cmpeq DAT2, DAT6 + bne 200f + tst OFF, #16 + beq 105f + memcmp_process_head 1 + sub N, N, #16 + memcmp_process_tail +105: +.endm + +.macro memcmp_trailing_15bytes unaligned + movs N, N, lsl #29 + .if unaligned + ldrcs DAT0, [S_1], #4 + ldrcs DAT1, [S_1], #4 + .else + ldmcsia S_1!, {DAT0, DAT1} + .endif + ldrmi DAT2, [S_1], #4 + ldmcsia S_2!, {DAT4, DAT5} + ldrmi DAT6, [S_2], #4 + movcc DAT0, #0 + movcc DAT1, #0 + movpl DAT2, #0 + movcc DAT4, #0 + movcc DAT5, #0 + movpl DAT6, #0 + cmp DAT0, DAT4 + cmpeq DAT1, DAT5 + cmpeq DAT2, DAT6 + bne 200f + movs N, N, lsl #2 + ldrcsh DAT0, [S_1], #2 + ldrmib DAT1, [S_1] + ldrcsh DAT4, [S_2], #2 + ldrmib DAT5, [S_2] + movcc DAT0, #0 + movpl DAT1, #0 + movcc DAT4, #0 + movpl DAT5, #0 + cmp DAT0, DAT4 + cmpeq DAT1, DAT5 + bne 200f +.endm + +.macro memcmp_long_inner_loop unaligned +110: + memcmp_process_head unaligned + pld [S_2, #prefetch_distance*32 + 16] + memcmp_process_tail + memcmp_process_head unaligned + pld [S_1, OFF] + memcmp_process_tail + subs N, N, #32 + bhs 110b + /* Just before the final (prefetch_distance+1) 32-byte blocks, + * deal with final preloads */ + preload_trailing 0, S_1, N, DAT0 + preload_trailing 0, S_2, N, DAT0 + add N, N, #(prefetch_distance+2)*32 - 16 +120: + memcmp_process_head unaligned + memcmp_process_tail + subs N, N, #16 + bhs 120b + /* Trailing words and bytes */ + tst N, #15 + beq 199f + memcmp_trailing_15bytes unaligned +199: /* Reached end without detecting a difference */ + mov a1, #0 + setend le + pop {DAT1-DAT6, pc} +.endm + +.macro memcmp_short_inner_loop unaligned + subs N, N, #16 /* simplifies inner loop termination */ + blo 122f +120: + memcmp_process_head unaligned + memcmp_process_tail + subs N, N, #16 + bhs 120b +122: /* Trailing words and bytes */ + tst N, #15 + beq 199f + memcmp_trailing_15bytes unaligned +199: /* Reached end without detecting a difference */ + mov a1, #0 + setend le + pop {DAT1-DAT6, pc} +.endm + +/* + * int memcmp(const void *s1, const void *s2, size_t n); + * On entry: + * a1 = pointer to buffer 1 + * a2 = pointer to buffer 2 + * a3 = number of bytes to compare (as unsigned chars) + * On exit: + * a1 = >0/=0/<0 if s1 >/=/< s2 + */ + +.set prefetch_distance, 2 + +ENTRY(memcmp) + S_1 .req a1 + S_2 .req a2 + N .req a3 + DAT0 .req a4 + DAT1 .req v1 + DAT2 .req v2 + DAT3 .req v3 + DAT4 .req v4 + DAT5 .req v5 + DAT6 .req v6 + DAT7 .req ip + OFF .req lr + + push {DAT1-DAT6, lr} + setend be /* lowest-addressed bytes are most significant */ + + /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */ + cmp N, #(prefetch_distance+3)*32 - 1 + blo 170f + + /* Long case */ + /* Adjust N so that the decrement instruction can also test for + * inner loop termination. We want it to stop when there are + * (prefetch_distance+1) complete blocks to go. */ + sub N, N, #(prefetch_distance+2)*32 + preload_leading_step1 0, DAT0, S_1 + preload_leading_step1 0, DAT1, S_2 + tst S_2, #31 + beq 154f + rsb OFF, S_2, #0 /* no need to AND with 15 here */ + preload_leading_step2 0, DAT0, S_1, OFF, DAT2 + preload_leading_step2 0, DAT1, S_2, OFF, DAT2 + memcmp_leading_31bytes +154: /* Second source now cacheline (32-byte) aligned; we have at + * least one prefetch to go. */ + /* Prefetch offset is best selected such that it lies in the + * first 8 of each 32 bytes - but it's just as easy to aim for + * the first one */ + and OFF, S_1, #31 + rsb OFF, OFF, #32*prefetch_distance + tst S_1, #3 + bne 140f + memcmp_long_inner_loop 0 +140: memcmp_long_inner_loop 1 + +170: /* Short case */ + teq N, #0 + beq 199f + preload_all 0, 0, 0, S_1, N, DAT0, DAT1 + preload_all 0, 0, 0, S_2, N, DAT0, DAT1 + tst S_2, #3 + beq 174f +172: subs N, N, #1 + blo 199f + ldrb DAT0, [S_1], #1 + ldrb DAT4, [S_2], #1 + cmp DAT0, DAT4 + bne 200f + tst S_2, #3 + bne 172b +174: /* Second source now 4-byte aligned; we have 0 or more bytes to go */ + tst S_1, #3 + bne 140f + memcmp_short_inner_loop 0 +140: memcmp_short_inner_loop 1 + +200: /* Difference found: determine sign. */ + movhi a1, #1 + movlo a1, #-1 + setend le + pop {DAT1-DAT6, pc} + + .unreq S_1 + .unreq S_2 + .unreq N + .unreq DAT0 + .unreq DAT1 + .unreq DAT2 + .unreq DAT3 + .unreq DAT4 + .unreq DAT5 + .unreq DAT6 + .unreq DAT7 + .unreq OFF +ENDPROC(memcmp) diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/lib/memcpymove.h linux/arch/arm/lib/memcpymove.h --- linux-6.1.66/arch/arm/lib/memcpymove.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/lib/memcpymove.h 2023-12-13 11:50:48.933962059 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* +Copyright (c) 2013, Raspberry Pi Foundation +Copyright (c) 2013, RISC OS Open Ltd +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the copyright holder nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +.macro unaligned_words backwards, align, use_pld, words, r0, r1, r2, r3, r4, r5, r6, r7, r8 + .if words == 1 + .if backwards + mov r1, r0, lsl #32-align*8 + ldr r0, [S, #-4]! + orr r1, r1, r0, lsr #align*8 + str r1, [D, #-4]! + .else + mov r0, r1, lsr #align*8 + ldr r1, [S, #4]! + orr r0, r0, r1, lsl #32-align*8 + str r0, [D], #4 + .endif + .elseif words == 2 + .if backwards + ldr r1, [S, #-4]! + mov r2, r0, lsl #32-align*8 + ldr r0, [S, #-4]! + orr r2, r2, r1, lsr #align*8 + mov r1, r1, lsl #32-align*8 + orr r1, r1, r0, lsr #align*8 + stmdb D!, {r1, r2} + .else + ldr r1, [S, #4]! + mov r0, r2, lsr #align*8 + ldr r2, [S, #4]! + orr r0, r0, r1, lsl #32-align*8 + mov r1, r1, lsr #align*8 + orr r1, r1, r2, lsl #32-align*8 + stmia D!, {r0, r1} + .endif + .elseif words == 4 + .if backwards + ldmdb S!, {r2, r3} + mov r4, r0, lsl #32-align*8 + ldmdb S!, {r0, r1} + orr r4, r4, r3, lsr #align*8 + mov r3, r3, lsl #32-align*8 + orr r3, r3, r2, lsr #align*8 + mov r2, r2, lsl #32-align*8 + orr r2, r2, r1, lsr #align*8 + mov r1, r1, lsl #32-align*8 + orr r1, r1, r0, lsr #align*8 + stmdb D!, {r1, r2, r3, r4} + .else + ldmib S!, {r1, r2} + mov r0, r4, lsr #align*8 + ldmib S!, {r3, r4} + orr r0, r0, r1, lsl #32-align*8 + mov r1, r1, lsr #align*8 + orr r1, r1, r2, lsl #32-align*8 + mov r2, r2, lsr #align*8 + orr r2, r2, r3, lsl #32-align*8 + mov r3, r3, lsr #align*8 + orr r3, r3, r4, lsl #32-align*8 + stmia D!, {r0, r1, r2, r3} + .endif + .elseif words == 8 + .if backwards + ldmdb S!, {r4, r5, r6, r7} + mov r8, r0, lsl #32-align*8 + ldmdb S!, {r0, r1, r2, r3} + .if use_pld + pld [S, OFF] + .endif + orr r8, r8, r7, lsr #align*8 + mov r7, r7, lsl #32-align*8 + orr r7, r7, r6, lsr #align*8 + mov r6, r6, lsl #32-align*8 + orr r6, r6, r5, lsr #align*8 + mov r5, r5, lsl #32-align*8 + orr r5, r5, r4, lsr #align*8 + mov r4, r4, lsl #32-align*8 + orr r4, r4, r3, lsr #align*8 + mov r3, r3, lsl #32-align*8 + orr r3, r3, r2, lsr #align*8 + mov r2, r2, lsl #32-align*8 + orr r2, r2, r1, lsr #align*8 + mov r1, r1, lsl #32-align*8 + orr r1, r1, r0, lsr #align*8 + stmdb D!, {r5, r6, r7, r8} + stmdb D!, {r1, r2, r3, r4} + .else + ldmib S!, {r1, r2, r3, r4} + mov r0, r8, lsr #align*8 + ldmib S!, {r5, r6, r7, r8} + .if use_pld + pld [S, OFF] + .endif + orr r0, r0, r1, lsl #32-align*8 + mov r1, r1, lsr #align*8 + orr r1, r1, r2, lsl #32-align*8 + mov r2, r2, lsr #align*8 + orr r2, r2, r3, lsl #32-align*8 + mov r3, r3, lsr #align*8 + orr r3, r3, r4, lsl #32-align*8 + mov r4, r4, lsr #align*8 + orr r4, r4, r5, lsl #32-align*8 + mov r5, r5, lsr #align*8 + orr r5, r5, r6, lsl #32-align*8 + mov r6, r6, lsr #align*8 + orr r6, r6, r7, lsl #32-align*8 + mov r7, r7, lsr #align*8 + orr r7, r7, r8, lsl #32-align*8 + stmia D!, {r0, r1, r2, r3} + stmia D!, {r4, r5, r6, r7} + .endif + .endif +.endm + +.macro memcpy_leading_15bytes backwards, align + movs DAT1, DAT2, lsl #31 + sub N, N, DAT2 + .if backwards + ldrmib DAT0, [S, #-1]! + ldrcsh DAT1, [S, #-2]! + strmib DAT0, [D, #-1]! + strcsh DAT1, [D, #-2]! + .else + ldrmib DAT0, [S], #1 + ldrcsh DAT1, [S], #2 + strmib DAT0, [D], #1 + strcsh DAT1, [D], #2 + .endif + movs DAT1, DAT2, lsl #29 + .if backwards + ldrmi DAT0, [S, #-4]! + .if align == 0 + ldmcsdb S!, {DAT1, DAT2} + .else + ldrcs DAT2, [S, #-4]! + ldrcs DAT1, [S, #-4]! + .endif + strmi DAT0, [D, #-4]! + stmcsdb D!, {DAT1, DAT2} + .else + ldrmi DAT0, [S], #4 + .if align == 0 + ldmcsia S!, {DAT1, DAT2} + .else + ldrcs DAT1, [S], #4 + ldrcs DAT2, [S], #4 + .endif + strmi DAT0, [D], #4 + stmcsia D!, {DAT1, DAT2} + .endif +.endm + +.macro memcpy_trailing_15bytes backwards, align + movs N, N, lsl #29 + .if backwards + .if align == 0 + ldmcsdb S!, {DAT0, DAT1} + .else + ldrcs DAT1, [S, #-4]! + ldrcs DAT0, [S, #-4]! + .endif + ldrmi DAT2, [S, #-4]! + stmcsdb D!, {DAT0, DAT1} + strmi DAT2, [D, #-4]! + .else + .if align == 0 + ldmcsia S!, {DAT0, DAT1} + .else + ldrcs DAT0, [S], #4 + ldrcs DAT1, [S], #4 + .endif + ldrmi DAT2, [S], #4 + stmcsia D!, {DAT0, DAT1} + strmi DAT2, [D], #4 + .endif + movs N, N, lsl #2 + .if backwards + ldrcsh DAT0, [S, #-2]! + ldrmib DAT1, [S, #-1] + strcsh DAT0, [D, #-2]! + strmib DAT1, [D, #-1] + .else + ldrcsh DAT0, [S], #2 + ldrmib DAT1, [S] + strcsh DAT0, [D], #2 + strmib DAT1, [D] + .endif +.endm + +.macro memcpy_long_inner_loop backwards, align + .if align != 0 + .if backwards + ldr DAT0, [S, #-align]! + .else + ldr LAST, [S, #-align]! + .endif + .endif +110: + .if align == 0 + .if backwards + ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} + pld [S, OFF] + stmdb D!, {DAT4, DAT5, DAT6, LAST} + stmdb D!, {DAT0, DAT1, DAT2, DAT3} + .else + ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} + pld [S, OFF] + stmia D!, {DAT0, DAT1, DAT2, DAT3} + stmia D!, {DAT4, DAT5, DAT6, LAST} + .endif + .else + unaligned_words backwards, align, 1, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST + .endif + subs N, N, #32 + bhs 110b + /* Just before the final (prefetch_distance+1) 32-byte blocks, deal with final preloads */ + preload_trailing backwards, S, N, OFF + add N, N, #(prefetch_distance+2)*32 - 32 +120: + .if align == 0 + .if backwards + ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} + stmdb D!, {DAT4, DAT5, DAT6, LAST} + stmdb D!, {DAT0, DAT1, DAT2, DAT3} + .else + ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} + stmia D!, {DAT0, DAT1, DAT2, DAT3} + stmia D!, {DAT4, DAT5, DAT6, LAST} + .endif + .else + unaligned_words backwards, align, 0, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST + .endif + subs N, N, #32 + bhs 120b + tst N, #16 + .if align == 0 + .if backwards + ldmnedb S!, {DAT0, DAT1, DAT2, LAST} + stmnedb D!, {DAT0, DAT1, DAT2, LAST} + .else + ldmneia S!, {DAT0, DAT1, DAT2, LAST} + stmneia D!, {DAT0, DAT1, DAT2, LAST} + .endif + .else + beq 130f + unaligned_words backwards, align, 0, 4, DAT0, DAT1, DAT2, DAT3, LAST +130: + .endif + /* Trailing words and bytes */ + tst N, #15 + beq 199f + .if align != 0 + add S, S, #align + .endif + memcpy_trailing_15bytes backwards, align +199: + pop {DAT3, DAT4, DAT5, DAT6, DAT7} + pop {D, DAT1, DAT2, pc} +.endm + +.macro memcpy_medium_inner_loop backwards, align +120: + .if backwards + .if align == 0 + ldmdb S!, {DAT0, DAT1, DAT2, LAST} + .else + ldr LAST, [S, #-4]! + ldr DAT2, [S, #-4]! + ldr DAT1, [S, #-4]! + ldr DAT0, [S, #-4]! + .endif + stmdb D!, {DAT0, DAT1, DAT2, LAST} + .else + .if align == 0 + ldmia S!, {DAT0, DAT1, DAT2, LAST} + .else + ldr DAT0, [S], #4 + ldr DAT1, [S], #4 + ldr DAT2, [S], #4 + ldr LAST, [S], #4 + .endif + stmia D!, {DAT0, DAT1, DAT2, LAST} + .endif + subs N, N, #16 + bhs 120b + /* Trailing words and bytes */ + tst N, #15 + beq 199f + memcpy_trailing_15bytes backwards, align +199: + pop {D, DAT1, DAT2, pc} +.endm + +.macro memcpy_short_inner_loop backwards, align + tst N, #16 + .if backwards + .if align == 0 + ldmnedb S!, {DAT0, DAT1, DAT2, LAST} + .else + ldrne LAST, [S, #-4]! + ldrne DAT2, [S, #-4]! + ldrne DAT1, [S, #-4]! + ldrne DAT0, [S, #-4]! + .endif + stmnedb D!, {DAT0, DAT1, DAT2, LAST} + .else + .if align == 0 + ldmneia S!, {DAT0, DAT1, DAT2, LAST} + .else + ldrne DAT0, [S], #4 + ldrne DAT1, [S], #4 + ldrne DAT2, [S], #4 + ldrne LAST, [S], #4 + .endif + stmneia D!, {DAT0, DAT1, DAT2, LAST} + .endif + memcpy_trailing_15bytes backwards, align +199: + pop {D, DAT1, DAT2, pc} +.endm + +.macro memcpy backwards + D .req a1 + S .req a2 + N .req a3 + DAT0 .req a4 + DAT1 .req v1 + DAT2 .req v2 + DAT3 .req v3 + DAT4 .req v4 + DAT5 .req v5 + DAT6 .req v6 + DAT7 .req sl + LAST .req ip + OFF .req lr + + UNWIND( .fnstart ) + + push {D, DAT1, DAT2, lr} + UNWIND( .fnend ) + + UNWIND( .fnstart ) + UNWIND( .save {D, DAT1, DAT2, lr} ) + + .if backwards + add D, D, N + add S, S, N + .endif + + /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */ + cmp N, #31 + blo 170f + /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */ + cmp N, #(prefetch_distance+3)*32 - 1 + blo 160f + + /* Long case */ + push {DAT3, DAT4, DAT5, DAT6, DAT7} + UNWIND( .fnend ) + + UNWIND( .fnstart ) + UNWIND( .save {D, DAT1, DAT2, lr} ) + UNWIND( .save {DAT3, DAT4, DAT5, DAT6, DAT7} ) + + /* Adjust N so that the decrement instruction can also test for + * inner loop termination. We want it to stop when there are + * (prefetch_distance+1) complete blocks to go. */ + sub N, N, #(prefetch_distance+2)*32 + preload_leading_step1 backwards, DAT0, S + .if backwards + /* Bug in GAS: it accepts, but mis-assembles the instruction + * ands DAT2, D, #60, 2 + * which sets DAT2 to the number of leading bytes until destination is aligned and also clears C (sets borrow) + */ + .word 0xE210513C + beq 154f + .else + ands DAT2, D, #15 + beq 154f + rsb DAT2, DAT2, #16 /* number of leading bytes until destination aligned */ + .endif + preload_leading_step2 backwards, DAT0, S, DAT2, OFF + memcpy_leading_15bytes backwards, 1 +154: /* Destination now 16-byte aligned; we have at least one prefetch as well as at least one 16-byte output block */ + /* Prefetch offset is best selected such that it lies in the first 8 of each 32 bytes - but it's just as easy to aim for the first one */ + .if backwards + rsb OFF, S, #3 + and OFF, OFF, #28 + sub OFF, OFF, #32*(prefetch_distance+1) + .else + and OFF, S, #28 + rsb OFF, OFF, #32*prefetch_distance + .endif + movs DAT0, S, lsl #31 + bhi 157f + bcs 156f + bmi 155f + memcpy_long_inner_loop backwards, 0 +155: memcpy_long_inner_loop backwards, 1 +156: memcpy_long_inner_loop backwards, 2 +157: memcpy_long_inner_loop backwards, 3 + + UNWIND( .fnend ) + + UNWIND( .fnstart ) + UNWIND( .save {D, DAT1, DAT2, lr} ) + +160: /* Medium case */ + preload_all backwards, 0, 0, S, N, DAT2, OFF + sub N, N, #16 /* simplifies inner loop termination */ + .if backwards + ands DAT2, D, #15 + beq 164f + .else + ands DAT2, D, #15 + beq 164f + rsb DAT2, DAT2, #16 + .endif + memcpy_leading_15bytes backwards, align +164: /* Destination now 16-byte aligned; we have at least one 16-byte output block */ + tst S, #3 + bne 140f + memcpy_medium_inner_loop backwards, 0 +140: memcpy_medium_inner_loop backwards, 1 + +170: /* Short case, less than 31 bytes, so no guarantee of at least one 16-byte block */ + teq N, #0 + beq 199f + preload_all backwards, 1, 0, S, N, DAT2, LAST + tst D, #3 + beq 174f +172: subs N, N, #1 + blo 199f + .if backwards + ldrb DAT0, [S, #-1]! + strb DAT0, [D, #-1]! + .else + ldrb DAT0, [S], #1 + strb DAT0, [D], #1 + .endif + tst D, #3 + bne 172b +174: /* Destination now 4-byte aligned; we have 0 or more output bytes to go */ + tst S, #3 + bne 140f + memcpy_short_inner_loop backwards, 0 +140: memcpy_short_inner_loop backwards, 1 + + UNWIND( .fnend ) + + .unreq D + .unreq S + .unreq N + .unreq DAT0 + .unreq DAT1 + .unreq DAT2 + .unreq DAT3 + .unreq DAT4 + .unreq DAT5 + .unreq DAT6 + .unreq DAT7 + .unreq LAST + .unreq OFF +.endm diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/lib/memcpy_rpi.S linux/arch/arm/lib/memcpy_rpi.S --- linux-6.1.66/arch/arm/lib/memcpy_rpi.S 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/lib/memcpy_rpi.S 2023-12-13 11:50:48.933962059 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* +Copyright (c) 2013, Raspberry Pi Foundation +Copyright (c) 2013, RISC OS Open Ltd +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the copyright holder nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/unwind.h> +#include "arm-mem.h" +#include "memcpymove.h" + +/* Prevent the stack from becoming executable */ +#if defined(__linux__) && defined(__ELF__) +.section .note.GNU-stack,"",%progbits +#endif + + .text + .arch armv6 + .object_arch armv4 + .arm + .altmacro + .p2align 2 + +/* + * void *memcpy(void * restrict s1, const void * restrict s2, size_t n); + * On entry: + * a1 = pointer to destination + * a2 = pointer to source + * a3 = number of bytes to copy + * On exit: + * a1 preserved + */ + +.set prefetch_distance, 3 + +ENTRY(mmiocpy) +ENTRY(memcpy) +ENTRY(__memcpy) + memcpy 0 +ENDPROC(__memcpy) +ENDPROC(memcpy) +ENDPROC(mmiocpy) diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/lib/memmove_rpi.S linux/arch/arm/lib/memmove_rpi.S --- linux-6.1.66/arch/arm/lib/memmove_rpi.S 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/lib/memmove_rpi.S 2023-12-13 11:50:48.934962062 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* +Copyright (c) 2013, Raspberry Pi Foundation +Copyright (c) 2013, RISC OS Open Ltd +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the copyright holder nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/unwind.h> +#include "arm-mem.h" +#include "memcpymove.h" + +/* Prevent the stack from becoming executable */ +#if defined(__linux__) && defined(__ELF__) +.section .note.GNU-stack,"",%progbits +#endif + + .text + .arch armv6 + .object_arch armv4 + .arm + .altmacro + .p2align 2 + +/* + * void *memmove(void *s1, const void *s2, size_t n); + * On entry: + * a1 = pointer to destination + * a2 = pointer to source + * a3 = number of bytes to copy + * On exit: + * a1 preserved + */ + +.set prefetch_distance, 3 + +ENTRY(memmove) + cmp a2, a1 + bpl memcpy /* pl works even over -1 - 0 and 0x7fffffff - 0x80000000 boundaries */ + memcpy 1 +ENDPROC(memmove) diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/lib/memset_rpi.S linux/arch/arm/lib/memset_rpi.S --- linux-6.1.66/arch/arm/lib/memset_rpi.S 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm/lib/memset_rpi.S 2023-12-13 11:50:48.934962062 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* +Copyright (c) 2013, Raspberry Pi Foundation +Copyright (c) 2013, RISC OS Open Ltd +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the copyright holder nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include <linux/linkage.h> +#include "arm-mem.h" + +/* Prevent the stack from becoming executable */ +#if defined(__linux__) && defined(__ELF__) +.section .note.GNU-stack,"",%progbits +#endif + + .text + .arch armv6 + .object_arch armv4 + .arm + .altmacro + .p2align 2 + +/* + * void *memset(void *s, int c, size_t n); + * On entry: + * a1 = pointer to buffer to fill + * a2 = byte pattern to fill with (caller-narrowed) + * a3 = number of bytes to fill + * On exit: + * a1 preserved + */ +ENTRY(mmioset) +ENTRY(memset) +ENTRY(__memset) + + S .req a1 + DAT0 .req a2 + N .req a3 + DAT1 .req a4 + DAT2 .req ip + DAT3 .req lr + + orr DAT0, DAT0, DAT0, lsl #8 + orr DAT0, DAT0, DAT0, lsl #16 + +ENTRY(__memset32) + mov DAT1, DAT0 + +ENTRY(__memset64) + push {S, lr} + + /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */ + cmp N, #31 + blo 170f + +161: sub N, N, #16 /* simplifies inner loop termination */ + /* Leading words and bytes */ + tst S, #15 + beq 164f + rsb DAT3, S, #0 /* bits 0-3 = number of leading bytes until aligned */ + movs DAT2, DAT3, lsl #31 + submi N, N, #1 + strmib DAT0, [S], #1 + subcs N, N, #2 + strcsh DAT0, [S], #2 + movs DAT2, DAT3, lsl #29 + submi N, N, #4 + strmi DAT0, [S], #4 + subcs N, N, #8 + stmcsia S!, {DAT0, DAT1} +164: /* Delayed set up of DAT2 and DAT3 so we could use them as scratch registers above */ + mov DAT2, DAT0 + mov DAT3, DAT1 + /* Now the inner loop of 16-byte stores */ +165: stmia S!, {DAT0, DAT1, DAT2, DAT3} + subs N, N, #16 + bhs 165b +166: /* Trailing words and bytes */ + movs N, N, lsl #29 + stmcsia S!, {DAT0, DAT1} + strmi DAT0, [S], #4 + movs N, N, lsl #2 + strcsh DAT0, [S], #2 + strmib DAT0, [S] +199: pop {S, pc} + +170: /* Short case */ + mov DAT2, DAT0 + mov DAT3, DAT1 + tst S, #3 + beq 174f +172: subs N, N, #1 + blo 199b + strb DAT0, [S], #1 + tst S, #3 + bne 172b +174: tst N, #16 + stmneia S!, {DAT0, DAT1, DAT2, DAT3} + b 166b + + .unreq S + .unreq DAT0 + .unreq N + .unreq DAT1 + .unreq DAT2 + .unreq DAT3 +ENDPROC(__memset64) +ENDPROC(__memset32) +ENDPROC(__memset) +ENDPROC(memset) +ENDPROC(mmioset) diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/lib/uaccess_with_memcpy.c linux/arch/arm/lib/uaccess_with_memcpy.c --- linux-6.1.66/arch/arm/lib/uaccess_with_memcpy.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/lib/uaccess_with_memcpy.c 2023-12-13 11:50:48.935962064 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:22 @ #include <asm/current.h> #include <asm/page.h> +#ifndef COPY_FROM_USER_THRESHOLD +#define COPY_FROM_USER_THRESHOLD 64 +#endif + +#ifndef COPY_TO_USER_THRESHOLD +#define COPY_TO_USER_THRESHOLD 64 +#endif + static int pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp) { @ linux/arch/arm/boot/dts/bcm2708.dtsi:54 @ return 0; pmd = pmd_offset(pud, addr); - if (unlikely(pmd_none(*pmd))) + if (unlikely(pmd_none(*pmd) || pmd_bad(*pmd))) return 0; /* @ linux/arch/arm/boot/dts/bcm2708.dtsi:97 @ return 1; } -static unsigned long noinline +static int +pin_page_for_read(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp) +{ + unsigned long addr = (unsigned long)_addr; + pgd_t *pgd; + p4d_t *p4d; + pmd_t *pmd; + pte_t *pte; + pud_t *pud; + spinlock_t *ptl; + + pgd = pgd_offset(current->mm, addr); + if (unlikely(pgd_none(*pgd) || pgd_bad(*pgd))) + return 0; + + p4d = p4d_offset(pgd, addr); + if (unlikely(p4d_none(*p4d) || p4d_bad(*p4d))) + return 0; + + pud = pud_offset(p4d, addr); + if (unlikely(pud_none(*pud) || pud_bad(*pud))) + return 0; + + pmd = pmd_offset(pud, addr); + if (unlikely(pmd_none(*pmd) || pmd_bad(*pmd))) + return 0; + + pte = pte_offset_map_lock(current->mm, pmd, addr, &ptl); + if (unlikely(!pte_present(*pte) || !pte_young(*pte))) { + pte_unmap_unlock(pte, ptl); + return 0; + } + + *ptep = pte; + *ptlp = ptl; + + return 1; +} + +unsigned long noinline __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n) { unsigned long ua_flags; @ linux/arch/arm/boot/dts/bcm2708.dtsi:184 @ return n; } +unsigned long noinline +__copy_from_user_memcpy(void *to, const void __user *from, unsigned long n) +{ + unsigned long ua_flags; + int atomic; + + /* the mmap semaphore is taken only if not in an atomic context */ + atomic = in_atomic(); + + if (!atomic) + mmap_read_lock(current->mm); + while (n) { + pte_t *pte; + spinlock_t *ptl; + int tocopy; + + while (!pin_page_for_read(from, &pte, &ptl)) { + char temp; + if (!atomic) + mmap_read_unlock(current->mm); + if (__get_user(temp, (char __user *)from)) + goto out; + if (!atomic) + mmap_read_lock(current->mm); + } + + tocopy = (~(unsigned long)from & ~PAGE_MASK) + 1; + if (tocopy > n) + tocopy = n; + + ua_flags = uaccess_save_and_enable(); + memcpy(to, (const void *)from, tocopy); + uaccess_restore(ua_flags); + to += tocopy; + from += tocopy; + n -= tocopy; + + pte_unmap_unlock(pte, ptl); + } + if (!atomic) + mmap_read_unlock(current->mm); + +out: + return n; +} + unsigned long arm_copy_to_user(void __user *to, const void *from, unsigned long n) { @ linux/arch/arm/boot/dts/bcm2708.dtsi:240 @ * With frame pointer disabled, tail call optimization kicks in * as well making this test almost invisible. */ - if (n < 64) { + if (n < COPY_TO_USER_THRESHOLD) { unsigned long ua_flags = uaccess_save_and_enable(); n = __copy_to_user_std(to, from, n); uaccess_restore(ua_flags); @ linux/arch/arm/boot/dts/bcm2708.dtsi:250 @ } return n; } + +unsigned long __must_check +arm_copy_from_user(void *to, const void __user *from, unsigned long n) +{ +#ifdef CONFIG_BCM2835_FAST_MEMCPY + /* + * This test is stubbed out of the main function above to keep + * the overhead for small copies low by avoiding a large + * register dump on the stack just to reload them right away. + * With frame pointer disabled, tail call optimization kicks in + * as well making this test almost invisible. + */ + if (n < COPY_TO_USER_THRESHOLD) { + unsigned long ua_flags = uaccess_save_and_enable(); + n = __copy_from_user_std(to, from, n); + uaccess_restore(ua_flags); + } else { + n = __copy_from_user_memcpy(to, from, n); + } +#else + unsigned long ua_flags = uaccess_save_and_enable(); + n = __copy_from_user_std(to, from, n); + uaccess_restore(ua_flags); +#endif + return n; +} static unsigned long noinline __clear_user_memset(void __user *addr, unsigned long n) diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/mach-bcm/board_bcm2835.c linux/arch/arm/mach-bcm/board_bcm2835.c --- linux-6.1.66/arch/arm/mach-bcm/board_bcm2835.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/mach-bcm/board_bcm2835.c 2023-12-13 11:50:48.945962087 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:8 @ #include <linux/init.h> #include <linux/irqchip.h> +#include <linux/mm.h> #include <linux/of_address.h> +#include <linux/of_fdt.h> +#include <asm/system_info.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include <asm/memory.h> +#include <asm/pgtable.h> #include "platsmp.h" +#define BCM2835_USB_VIRT_BASE (VMALLOC_START) +#define BCM2835_USB_VIRT_MPHI (VMALLOC_START + 0x10000) + +static void __init bcm2835_init(void) +{ + struct device_node *np = of_find_node_by_path("/system"); + u32 val; + u64 val64; + + if (!of_property_read_u32(np, "linux,revision", &val)) + system_rev = val; + if (!of_property_read_u64(np, "linux,serial", &val64)) + system_serial_low = val64; +} + +/* + * We need to map registers that are going to be accessed by the FIQ + * very early, before any kernel threads are spawned. Because if done + * later, the mapping tables are not updated instantly but lazily upon + * first access through a data abort handler. While that is fine + * when executing regular kernel code, if the first access in a specific + * thread happens while running FIQ code this will result in a panic. + * + * For more background see the following old mailing list thread: + * https://www.spinics.net/lists/arm-kernel/msg325250.html + */ +static int __init bcm2835_map_usb(unsigned long node, const char *uname, + int depth, void *data) +{ + struct map_desc map[2]; + const __be32 *reg; + int len; + unsigned long p2b_offset = *((unsigned long *) data); + + if (!of_flat_dt_is_compatible(node, "brcm,bcm2708-usb")) + return 0; + reg = of_get_flat_dt_prop(node, "reg", &len); + if (!reg || len != (sizeof(unsigned long) * 4)) + return 0; + + /* Use information about the physical addresses of the + * registers from the device tree, but use legacy + * iotable_init() static mapping function to map them, + * as ioremap() is not functional at this stage in boot. + */ + map[0].virtual = (unsigned long) BCM2835_USB_VIRT_BASE; + map[0].pfn = __phys_to_pfn(be32_to_cpu(reg[0]) - p2b_offset); + map[0].length = be32_to_cpu(reg[1]); + map[0].type = MT_DEVICE; + map[1].virtual = (unsigned long) BCM2835_USB_VIRT_MPHI; + map[1].pfn = __phys_to_pfn(be32_to_cpu(reg[2]) - p2b_offset); + map[1].length = be32_to_cpu(reg[3]); + map[1].type = MT_DEVICE; + iotable_init(map, 2); + + return 1; +} + +static void __init bcm2835_map_io(void) +{ + const __be32 *ranges, *address_cells; + unsigned long root, addr_cells; + int soc, len; + unsigned long p2b_offset; + + debug_ll_io_init(); + + root = of_get_flat_dt_root(); + /* Find out how to map bus to physical address first from soc/ranges */ + soc = of_get_flat_dt_subnode_by_name(root, "soc"); + if (soc < 0) + return; + address_cells = of_get_flat_dt_prop(root, "#address-cells", &len); + if (!address_cells || len < (sizeof(unsigned long))) + return; + addr_cells = be32_to_cpu(address_cells[0]); + ranges = of_get_flat_dt_prop(soc, "ranges", &len); + if (!ranges || len < (sizeof(unsigned long) * (2 + addr_cells))) + return; + p2b_offset = be32_to_cpu(ranges[0]) - be32_to_cpu(ranges[addr_cells]); + + /* Now search for bcm2708-usb node in device tree */ + of_scan_flat_dt(bcm2835_map_usb, &p2b_offset); +} + static const char * const bcm2835_compat[] = { #ifdef CONFIG_ARCH_MULTI_V6 "brcm,bcm2835", @ linux/arch/arm/boot/dts/bcm2708.dtsi:117 @ }; DT_MACHINE_START(BCM2835, "BCM2835") + .map_io = bcm2835_map_io, + .init_machine = bcm2835_init, .dt_compat = bcm2835_compat, .smp = smp_ops(bcm2836_smp_ops), MACHINE_END + +static const char * const bcm2711_compat[] = { +#ifdef CONFIG_ARCH_MULTI_V7 + "brcm,bcm2711", +#endif + NULL +}; + +DT_MACHINE_START(BCM2711, "BCM2711") +#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE) + .dma_zone_size = SZ_1G, +#endif + .map_io = bcm2835_map_io, + .init_machine = bcm2835_init, + .dt_compat = bcm2711_compat, + .smp = smp_ops(bcm2836_smp_ops), +MACHINE_END diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/mach-bcm/Kconfig linux/arch/arm/mach-bcm/Kconfig --- linux-6.1.66/arch/arm/mach-bcm/Kconfig 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/mach-bcm/Kconfig 2023-12-13 11:50:48.943962083 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:162 @ select ARM_TIMER_SP804 select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7 select BCM2835_TIMER + select FIQ select PINCTRL select PINCTRL_BCM2835 select MFD_CORE + select MFD_SYSCON if ARCH_MULTI_V7 help This enables support for the Broadcom BCM2711 and BCM283x SoCs. This SoC is used in the Raspberry Pi and Roku 2 devices. @ linux/arch/arm/boot/dts/bcm2708.dtsi:185 @ The base chip is BCM53573 and there are some packaging modifications like BCM47189 and BCM47452. +config ARCH_BCM_63XX + bool "Broadcom BCM63xx DSL SoC" + depends on ARCH_MULTI_V7 + select ARCH_HAS_RESET_CONTROLLER + select ARM_ERRATA_754322 + select ARM_ERRATA_764369 if SMP + select ARM_GIC + select ARM_GLOBAL_TIMER + select CACHE_L2X0 + select HAVE_ARM_ARCH_TIMER + select HAVE_ARM_TWD if SMP + select HAVE_ARM_SCU if SMP + help + This enables support for systems based on Broadcom DSL SoCs. + It currently supports the 'BCM63XX' ARM-based family, which includes + the BCM63138 variant. + +config BCM2835_FAST_MEMCPY + bool "Enable optimized __copy_to_user and __copy_from_user" + depends on ARCH_BCM2835 && ARCH_MULTI_V6 + default y + help + Optimized versions of __copy_to_user and __copy_from_user for Pi1. + config ARCH_BRCMSTB bool "Broadcom BCM7XXX based boards" depends on ARCH_MULTI_V7 diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/mm/cache-v6.S linux/arch/arm/mm/cache-v6.S --- linux-6.1.66/arch/arm/mm/cache-v6.S 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/mm/cache-v6.S 2023-12-13 11:50:49.207962704 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:201 @ * - start - virtual start address of region * - end - virtual end address of region */ -v6_dma_inv_range: +ENTRY(v6_dma_inv_range) #ifdef CONFIG_DMA_CACHE_RWFO ldrb r2, [r0] @ read for ownership strb r2, [r0] @ write for ownership @ linux/arch/arm/boot/dts/bcm2708.dtsi:246 @ * - start - virtual start address of region * - end - virtual end address of region */ -v6_dma_clean_range: +ENTRY(v6_dma_clean_range) bic r0, r0, #D_CACHE_LINE_SIZE - 1 1: #ifdef CONFIG_DMA_CACHE_RWFO diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/mm/cache-v7.S linux/arch/arm/mm/cache-v7.S --- linux-6.1.66/arch/arm/mm/cache-v7.S 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/mm/cache-v7.S 2023-12-13 11:50:49.207962704 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:362 @ * - start - virtual start address of region * - end - virtual end address of region */ -v7_dma_inv_range: +ENTRY(b15_dma_inv_range) +ENTRY(v7_dma_inv_range) dcache_line_size r2, r3 sub r3, r2, #1 tst r0, r3 @ linux/arch/arm/boot/dts/bcm2708.dtsi:393 @ * - start - virtual start address of region * - end - virtual end address of region */ -v7_dma_clean_range: +ENTRY(b15_dma_clean_range) +ENTRY(v7_dma_clean_range) dcache_line_size r2, r3 sub r3, r2, #1 bic r0, r0, r3 diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/mm/proc-macros.S linux/arch/arm/mm/proc-macros.S --- linux-6.1.66/arch/arm/mm/proc-macros.S 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/mm/proc-macros.S 2023-12-13 11:50:49.220962735 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:336 @ .long \name\()_flush_kern_dcache_area .long \name\()_dma_map_area .long \name\()_dma_unmap_area + .long \name\()_dma_inv_range + .long \name\()_dma_clean_range .long \name\()_dma_flush_range .size \name\()_cache_fns, . - \name\()_cache_fns .endm diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/mm/proc-syms.c linux/arch/arm/mm/proc-syms.c --- linux-6.1.66/arch/arm/mm/proc-syms.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/mm/proc-syms.c 2023-12-13 11:50:49.221962737 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:30 @ EXPORT_SYMBOL(__cpuc_flush_user_range); EXPORT_SYMBOL(__cpuc_coherent_kern_range); EXPORT_SYMBOL(__cpuc_flush_dcache_area); +EXPORT_SYMBOL(dmac_inv_range); +EXPORT_SYMBOL(dmac_clean_range); +EXPORT_SYMBOL(dmac_flush_range); #else EXPORT_SYMBOL(cpu_cache); #endif diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/mm/proc-v6.S linux/arch/arm/mm/proc-v6.S --- linux-6.1.66/arch/arm/mm/proc-v6.S 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/mm/proc-v6.S 2023-12-13 11:50:49.221962737 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:73 @ * * IRQs are already disabled. */ + +/* See jira SW-5991 for details of this workaround */ ENTRY(cpu_v6_do_idle) - mov r1, #0 - mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode - mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt + .align 5 + mov r1, #2 +1: subs r1, #1 + nop + mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode + mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt + nop + nop + nop + bne 1b ret lr ENTRY(cpu_v6_dcache_clean_area) diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm/vfp/vfpmodule.c linux/arch/arm/vfp/vfpmodule.c --- linux-6.1.66/arch/arm/vfp/vfpmodule.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm/vfp/vfpmodule.c 2023-12-13 11:50:49.247962799 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:179 @ * case the thread migrates to a different CPU. The * restoring is done lazily. */ - if ((fpexc & FPEXC_EN) && vfp_current_hw_state[cpu]) + if ((fpexc & FPEXC_EN) && vfp_current_hw_state[cpu]) { + /* vfp_save_state oopses on VFP11 if EX bit set */ + fmxr(FPEXC, fpexc & ~FPEXC_EX); vfp_save_state(vfp_current_hw_state[cpu], fpexc); + } #endif /* @ linux/arch/arm/boot/dts/bcm2708.dtsi:460 @ /* if vfp is on, then save state for resumption */ if (fpexc & FPEXC_EN) { pr_debug("%s: saving vfp state\n", __func__); + /* vfp_save_state oopses on VFP11 if EX bit set */ + fmxr(FPEXC, fpexc & ~FPEXC_EX); vfp_save_state(&ti->vfpstate, fpexc); /* disable, just in case */ fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); } else if (vfp_current_hw_state[ti->cpu]) { #ifndef CONFIG_SMP - fmxr(FPEXC, fpexc | FPEXC_EN); + /* vfp_save_state oopses on VFP11 if EX bit set */ + fmxr(FPEXC, (fpexc & ~FPEXC_EX) | FPEXC_EN); vfp_save_state(vfp_current_hw_state[ti->cpu], fpexc); fmxr(FPEXC, fpexc); #endif @ linux/arch/arm/boot/dts/bcm2708.dtsi:532 @ /* * Save the last VFP state on this CPU. */ - fmxr(FPEXC, fpexc | FPEXC_EN); + /* vfp_save_state oopses on VFP11 if EX bit set */ + fmxr(FPEXC, (fpexc & ~FPEXC_EX) | FPEXC_EN); vfp_save_state(&thread->vfpstate, fpexc | FPEXC_EN); fmxr(FPEXC, fpexc); } @ linux/arch/arm/boot/dts/bcm2708.dtsi:599 @ struct thread_info *thread = current_thread_info(); struct vfp_hard_struct *hwstate = &thread->vfpstate.hard; unsigned long fpexc; + u32 fpsid = fmrx(FPSID); /* Disable VFP to avoid corrupting the new thread state. */ vfp_flush_hwstate(thread); @ linux/arch/arm/boot/dts/bcm2708.dtsi:622 @ /* Ensure the VFP is enabled. */ fpexc |= FPEXC_EN; - /* Ensure FPINST2 is invalid and the exception flag is cleared. */ - fpexc &= ~(FPEXC_EX | FPEXC_FP2V); + /* Mask FPXEC_EX and FPEXC_FP2V if not required by VFP arch */ + if ((fpsid & FPSID_ARCH_MASK) != (1 << FPSID_ARCH_BIT)) { + /* Ensure FPINST2 is invalid and the exception flag is cleared. */ + fpexc &= ~(FPEXC_EX | FPEXC_FP2V); + } + hwstate->fpexc = fpexc; hwstate->fpinst = ufp_exc->fpinst; @ linux/arch/arm/boot/dts/bcm2708.dtsi:741 @ cpu = get_cpu(); fpexc = fmrx(FPEXC) | FPEXC_EN; - fmxr(FPEXC, fpexc); + /* vfp_save_state oopses on VFP11 if EX bit set */ + fmxr(FPEXC, fpexc & ~FPEXC_EX); /* * Save the userland NEON/VFP state. Under UP, diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts linux/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts --- linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts 2023-12-13 11:50:49.296962914 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include "../../../../arm/boot/dts/bcm2710-rpi-2-b.dts" diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts linux/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts --- linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts 2023-12-13 11:50:49.296962914 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include "../../../../arm/boot/dts/bcm2710-rpi-3-b.dts" diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts linux/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts --- linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts 2023-12-13 11:50:49.296962914 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include "../../../../arm/boot/dts/bcm2710-rpi-3-b-plus.dts" diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts linux/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts --- linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts 2023-12-13 11:50:49.296962914 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include "../../../../arm/boot/dts/bcm2710-rpi-cm3.dts" diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2.dts linux/arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2.dts --- linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2.dts 2023-12-13 11:50:49.297962916 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include "../../../../arm/boot/dts/bcm2710-rpi-zero-2-w.dts" diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2-w.dts linux/arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2-w.dts --- linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2-w.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2-w.dts 2023-12-13 11:50:49.297962916 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include "../../../../arm/boot/dts/bcm2710-rpi-zero-2-w.dts" diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts linux/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts --- linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts 2023-12-13 11:50:49.297962916 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ -// SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2711-rpi-400.dts" +#include "../../../../arm/boot/dts/bcm2711-rpi-400.dts" diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts linux/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts --- linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts 2023-12-13 11:50:49.297962916 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ -// SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2711-rpi-4-b.dts" +#include "../../../../arm/boot/dts/bcm2711-rpi-4-b.dts" diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4.dts linux/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4.dts --- linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4.dts 2023-12-13 11:50:49.297962916 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include "../../../../arm/boot/dts/bcm2711-rpi-cm4.dts" diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4s.dts linux/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4s.dts --- linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4s.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4s.dts 2023-12-13 11:50:49.297962916 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include "../../../../arm/boot/dts/bcm2711-rpi-cm4s.dts" diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts linux/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts --- linux-6.1.66/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts 2023-12-13 11:50:49.297962916 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include "../../../../arm/boot/dts/bcm2712-rpi-5-b.dts" diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/boot/dts/broadcom/Makefile linux/arch/arm64/boot/dts/broadcom/Makefile --- linux-6.1.66/arch/arm64/boot/dts/broadcom/Makefile 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm64/boot/dts/broadcom/Makefile 2023-12-13 11:50:49.296962914 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:11 @ bcm2837-rpi-cm3-io3.dtb \ bcm2837-rpi-zero-2-w.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-zero-2.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-zero-2-w.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-2-b.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b-plus.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-cm3.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-cm4.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-cm4s.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2712-rpi-5-b.dtb + subdir-y += bcmbca subdir-y += northstar2 subdir-y += stingray + +# Enable fixups to support overlays on BCM2835 platforms +ifeq ($(CONFIG_ARCH_BCM2835),y) + DTC_FLAGS += -@ +endif diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/boot/dts/Makefile linux/arch/arm64/boot/dts/Makefile --- linux-6.1.66/arch/arm64/boot/dts/Makefile 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm64/boot/dts/Makefile 2023-12-13 11:50:49.252962810 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:35 @ subdir-y += ti subdir-y += toshiba subdir-y += xilinx + +subdir-y += overlays diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/configs/bcm2711_defconfig linux/arch/arm64/configs/bcm2711_defconfig --- linux-6.1.66/arch/arm64/configs/bcm2711_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/configs/bcm2711_defconfig 2023-12-13 11:50:49.566963550 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +CONFIG_LOCALVERSION="-v8" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_PREEMPT=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCM2835=y +CONFIG_ARCH_BRCMSTB=y +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +CONFIG_COMPAT=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" +# CONFIG_SUSPEND is not set +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_RASPBERRYPI_CPUFREQ=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_COMPRESS_XZ=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y +CONFIG_BINFMT_MISC=m +CONFIG_ZSWAP=y +CONFIG_Z3FOLD=m +# CONFIG_COMPAT_BRK is not set +CONFIG_CMA=y +CONFIG_LRU_GEN=y +CONFIG_LRU_GEN_ENABLED=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU=m +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BBR=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_MPTCP=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_ATM=m +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_BATMAN_ADV=m +CONFIG_OPENVSWITCH=m +CONFIG_VSOCKETS=m +CONFIG_CGROUP_NET_PRIO=y +CONFIG_NET_PKTGEN=m +CONFIG_HAMRADIO=y +CONFIG_AX25=m +CONFIG_NETROM=m +CONFIG_ROSE=m +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_YAM=m +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_6LOWPAN=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_NET_9P=m +CONFIG_NFC=m +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM_POWERSAVE=y +CONFIG_PCIE_DPC=y +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_BRCMSTB_GISB_ARB is not set +CONFIG_RASPBERRYPI_FIRMWARE=y +# CONFIG_EFI_VARS_PSTORE is not set +CONFIG_MTD=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK2MTD=m +CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_UBI=m +CONFIG_OF_CONFIGFS=y +CONFIG_ZRAM=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_BLK_DEV_NVME=y +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_TI_ST=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_ISCSI_ATTRS=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_ATA=m +CONFIG_SATA_AHCI=m +CONFIG_SATA_MV=m +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_DELAY=m +CONFIG_DM_INTEGRITY=m +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_IFB=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_TUN=m +CONFIG_VETH=m +CONFIG_NET_VRF=m +CONFIG_VSOCKMON=m +CONFIG_BCMGENET=y +CONFIG_MACB=y +CONFIG_ENC28J60=m +CONFIG_LAN743X=m +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +CONFIG_R8169=m +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5100_SPI=m +CONFIG_MICREL_PHY=y +CONFIG_CAN_VCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_MCP251X=m +CONFIG_CAN_MCP251XFD=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_MDIO_BITBANG=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=y +CONFIG_USB_LAN78XX=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=y +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_AQC111=m +CONFIG_ATH9K=m +CONFIG_ATH9K_HTC=m +CONFIG_CARL9170=m +CONFIG_ATH6KL=m +CONFIG_ATH6KL_USB=m +CONFIG_AR5523=m +CONFIG_AT76C50X_USB=m +CONFIG_B43=m +# CONFIG_B43_PHY_N is not set +CONFIG_B43LEGACY=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMDBG=y +CONFIG_HOSTAP=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x2U=m +CONFIG_MT7921U=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8187=m +CONFIG_RTL8192CU=m +CONFIG_RTL8XXXU=m +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_TCA6416=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_CAP11XX=m +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_RPISENSE=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_EGALAX=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_STMPE=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_RASPBERRYPI_BUTTON=m +CONFIG_SERIO=m +CONFIG_SERIO_RAW=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_BRCM_CHAR_DRIVERS=y +CONFIG_BCM_VCIO=y +CONFIG_RPIVID_MEM=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DMA is not set +CONFIG_SERIAL_8250_NR_UARTS=5 +CONFIG_SERIAL_8250_RUNTIME_UARTS=0 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_BCM2835AUX=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_SPI=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=y +CONFIG_HW_RANDOM=y +CONFIG_TCG_TPM=m +CONFIG_TCG_TIS_SPI=m +CONFIG_TCG_TIS_I2C=m +CONFIG_XILLYBUS=m +CONFIG_XILLYBUS_PCIE=m +CONFIG_XILLYUSB=m +CONFIG_RASPBERRYPI_GPIOMEM=m +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_PCA954x=m +CONFIG_I2C_MUX_PINCTRL=m +CONFIG_I2C_BCM2708=m +CONFIG_I2C_BCM2835=m +CONFIG_I2C_BRCMSTB=m +CONFIG_I2C_DESIGNWARE_PLATFORM=m +CONFIG_I2C_GPIO=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_TINY_USB=m +CONFIG_SPI=y +CONFIG_SPI_BCM2835=m +CONFIG_SPI_BCM2835AUX=m +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_GPIO=m +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SLAVE=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_PINCTRL_RP1=y +CONFIG_PINCTRL_BCM2712=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_BCM_VIRT=y +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_ARIZONA=m +CONFIG_GPIO_FSM=m +CONFIG_GPIO_STMPE=y +CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MOCKUP=m +CONFIG_W1=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m +# CONFIG_POWER_RESET_BRCMSTB is not set +CONFIG_POWER_RESET_GPIO=y +CONFIG_RPI_POE_POWER=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_MAX17040=m +CONFIG_CHARGER_GPIO=m +CONFIG_BATTERY_GAUGE_LTC2941=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_AHT10=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_RASPBERRYPI_HWMON=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_RP1_ADC=m +CONFIG_BCM2711_THERMAL=y +CONFIG_BCM2835_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_GPIO_WATCHDOG=m +CONFIG_BCM2835_WDT=y +CONFIG_MFD_RASPBERRYPI_POE_HAT=m +CONFIG_MFD_STMPE=y +CONFIG_STMPE_SPI=y +CONFIG_MFD_SYSCON=y +CONFIG_MFD_ARIZONA_I2C=m +CONFIG_MFD_ARIZONA_SPI=m +CONFIG_MFD_WM5102=y +CONFIG_MFD_RP1=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m +CONFIG_RC_CORE=y +CONFIG_BPF_LIRC_MODE2=y +CONFIG_LIRC=y +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_LOOPBACK=m +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_DVB_AS102=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m +CONFIG_USB_DSBR=m +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_MR800=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_I2C_SI4713=m +CONFIG_RADIO_WL128X=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MUX=m +CONFIG_VIDEO_BCM2835_UNICAM=m +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m +CONFIG_VIDEO_RP1_CFE=m +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VIDEO_VIM2M=m +CONFIG_VIDEO_VICODEC=m +CONFIG_VIDEO_VIMC=m +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_ARDUCAM_64MP=m +CONFIG_VIDEO_ARDUCAM_PIVARIETY=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX296=m +CONFIG_VIDEO_IMX477=m +CONFIG_VIDEO_IMX519=m +CONFIG_VIDEO_IMX708=m +CONFIG_VIDEO_MT9V011=m +CONFIG_VIDEO_OV2311=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV64A40=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV7640=m +CONFIG_VIDEO_AD5398=m +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_BU64754=m +CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_OV9281=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m +CONFIG_VIDEO_IRS1125=m +CONFIG_VIDEO_I2C=m +CONFIG_DRM=m +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_UDL=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m +CONFIG_DRM_PANEL_ILITEK_ILI9881C=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +CONFIG_DRM_PANEL_SITRONIX_ST7701=m +CONFIG_DRM_PANEL_TPO_Y17P=m +CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_V3D=m +CONFIG_DRM_VC4=m +CONFIG_DRM_VC4_HDMI_CEC=y +CONFIG_DRM_RP1_DSI=m +CONFIG_DRM_RP1_DPI=m +CONFIG_DRM_RP1_VEC=m +CONFIG_DRM_PANEL_MIPI_DBI=m +CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m +CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m +CONFIG_TINYDRM_ST7735R=m +CONFIG_DRM_GUD=m +CONFIG_FB=y +CONFIG_FB_BCM2708=y +CONFIG_FB_SIMPLE=y +CONFIG_FB_SSD1307=m +CONFIG_FB_RPISENSE=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_RPI=m +CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_GPIO=m +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_PCM_OSS=m +CONFIG_SND_HRTIMER=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_MPU401=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_SOC=m +CONFIG_SND_BCM2835_SOC_I2S=m +CONFIG_SND_BCM2708_SOC_CHIPDIP_DAC=m +CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSHD=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADC=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADCPRO=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSDSP=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m +CONFIG_SND_BCM2708_SOC_PIFI_40=m +CONFIG_SND_BCM2708_SOC_RPI_CIRRUS=m +CONFIG_SND_BCM2708_SOC_RPI_DAC=m +CONFIG_SND_BCM2708_SOC_RPI_PROTO=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_BOTH=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_CODEC=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI=m +CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m +CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m +CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m +CONFIG_SND_AUDIOSENSE_PI=m +CONFIG_SND_DIGIDAC1_SOUNDCARD=m +CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m +CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO_V2=m +CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS=m +CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_BOSS2_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE=m +CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC=m +CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO=m +CONFIG_SND_PISOUND=m +CONFIG_SND_DACBERRY400=m +CONFIG_SND_DESIGNWARE_I2S=m +CONFIG_SND_DESIGNWARE_PCM=y +CONFIG_SND_SOC_AD193X_SPI=m +CONFIG_SND_SOC_AD193X_I2C=m +CONFIG_SND_SOC_ADAU1701=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_AK4554=m +CONFIG_SND_SOC_CS4265=m +CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_APPLE=m +CONFIG_HID_ASUS=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_HOLTEK=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_GYRATION=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_NINTENDO_FF=y +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PLAYSTATION=m +CONFIG_PLAYSTATION_FF=y +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_GREENASIA=m +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_MON=m +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWCOTG=y +CONFIG_USB_PRINTER=m +CONFIG_USB_TMC=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=y +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VUDC=m +CONFIG_USB_DWC3=y +CONFIG_USB_DWC2=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_TEST=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_HID=m +CONFIG_USB_G_WEBCAM=m +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_BCM2835_MMC=y +CONFIG_MMC_BCM2835_DMA=y +CONFIG_MMC_BCM2835_SDHOST=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +CONFIG_MMC_SDHCI_IPROC=y +CONFIG_MMC_SPI=m +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA955X=m +CONFIG_LEDS_PCA963X=m +CONFIG_LEDS_PWM=y +CONFIG_LEDS_IS31FL32XX=m +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_INPUT=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_ACTPWR=y +CONFIG_ACCESSIBILITY=y +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_ISL12022=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_BQ32K=m +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_DS1302=m +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_RX4581=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_DMADEVICES=y +CONFIG_DMA_BCM2835=y +CONFIG_DW_AXI_DMAC=y +CONFIG_DMA_BCM2708=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_AUXDISPLAY=y +CONFIG_HD44780=m +CONFIG_UIO=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_VHOST_NET=m +CONFIG_VHOST_VSOCK=m +CONFIG_VHOST_CROSS_ENDIAN_LEGACY=y +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_R8712U=m +CONFIG_R8188EU=m +CONFIG_VT6656=m +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_RPIVID=m +CONFIG_STAGING_MEDIA_DEPRECATED=y +CONFIG_VIDEO_CPIA2=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_USB_ZR364XX=m +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m +CONFIG_FB_TFT_HX8340BN=m +CONFIG_FB_TFT_HX8347D=m +CONFIG_FB_TFT_HX8353D=m +CONFIG_FB_TFT_HX8357D=m +CONFIG_FB_TFT_ILI9163=m +CONFIG_FB_TFT_ILI9320=m +CONFIG_FB_TFT_ILI9325=m +CONFIG_FB_TFT_ILI9340=m +CONFIG_FB_TFT_ILI9341=m +CONFIG_FB_TFT_ILI9481=m +CONFIG_FB_TFT_ILI9486=m +CONFIG_FB_TFT_PCD8544=m +CONFIG_FB_TFT_RA8875=m +CONFIG_FB_TFT_S6D02A1=m +CONFIG_FB_TFT_S6D1121=m +CONFIG_FB_TFT_SH1106=m +CONFIG_FB_TFT_SSD1289=m +CONFIG_FB_TFT_SSD1306=m +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m +CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m +CONFIG_BCM2835_VCHIQ=y +CONFIG_SND_BCM2835=m +CONFIG_VIDEO_BCM2835=m +CONFIG_VIDEO_CODEC_BCM2835=m +CONFIG_VIDEO_ISP_BCM2835=m +CONFIG_COMMON_CLK_RP1=y +CONFIG_COMMON_CLK_RP1_SDIO=y +CONFIG_CLK_RASPBERRYPI=y +CONFIG_MAILBOX=y +CONFIG_BCM2835_MBOX=y +CONFIG_BCM2712_IOMMU=y +CONFIG_RASPBERRYPI_POWER=y +CONFIG_IIO=m +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m +CONFIG_TI_ADS1015=m +CONFIG_BME680=m +CONFIG_CCS811=m +CONFIG_SENSIRION_SGP30=m +CONFIG_SPS30_I2C=m +CONFIG_MAX30102=m +CONFIG_DHT11=m +CONFIG_HDC100X=m +CONFIG_HTU21=m +CONFIG_SI7020=m +CONFIG_BOSCH_BNO055_I2C=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_APDS9960=m +CONFIG_BH1750=m +CONFIG_TSL4531=m +CONFIG_VEML6070=m +CONFIG_IIO_HRTIMER_TRIGGER=m +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_BMP280=m +CONFIG_MS5637=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_MAX31856=m +CONFIG_PWM=y +CONFIG_PWM_BCM2835=m +CONFIG_PWM_BRCMSTB=y +CONFIG_PWM_PCA9685=m +CONFIG_PWM_RASPBERRYPI_POE=m +CONFIG_PWM_RP1=y +CONFIG_BCM2712_MIP=y +CONFIG_RPI_AXIPERF=m +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_BINDERFS=y +CONFIG_NVMEM_RMEM=m +CONFIG_MUX_GPIO=m +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_REISERFS_FS=m +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +CONFIG_JFS_STATISTICS=y +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_GFS2_FS=m +CONFIG_OCFS2_FS=m +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FANOTIFY=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_NTFS3_FS=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=m +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_SUMMARY=y +CONFIG_UBIFS_FS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFSD=m +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_CEPH_FS=m +CONFIG_CIFS=m +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y +CONFIG_SMB_SERVER=m +CONFIG_9P_FS=m +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_DLM=m +CONFIG_SECURITY=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_LSM="" +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_HMAC=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_GHASH_ARM64_CE=m +CONFIG_CRYPTO_SHA1_ARM64_CE=m +CONFIG_CRYPTO_SHA2_ARM64_CE=m +CONFIG_CRYPTO_SHA512_ARM64_CE=m +CONFIG_CRYPTO_SHA3_ARM64=m +CONFIG_CRYPTO_SM3_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64=m +CONFIG_CRYPTO_AES_ARM64_CE_BLK=m +CONFIG_CRYPTO_AES_ARM64_BS=m +CONFIG_CRYPTO_SM4_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=m +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_ITU_T=y +CONFIG_LIBCRC32C=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=5 +CONFIG_PRINTK_TIME=y +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_KEYBOARD=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_LATENCYTOP=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_UPROBE_EVENTS is not set +# CONFIG_STRICT_DEVMEM is not set diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/configs/bcm2712_defconfig linux/arch/arm64/configs/bcm2712_defconfig --- linux-6.1.66/arch/arm64/configs/bcm2712_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/configs/bcm2712_defconfig 2023-12-13 11:50:49.566963550 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +CONFIG_LOCALVERSION="-v8-16k" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_PREEMPT=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCM2835=y +CONFIG_ARCH_BRCMSTB=y +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +CONFIG_ARM64_16K_PAGES=y +CONFIG_COMPAT=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" +# CONFIG_SUSPEND is not set +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_RASPBERRYPI_CPUFREQ=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_JUMP_LABEL=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_COMPRESS_XZ=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y +CONFIG_BINFMT_MISC=m +CONFIG_ZSWAP=y +CONFIG_Z3FOLD=m +# CONFIG_COMPAT_BRK is not set +CONFIG_CMA=y +CONFIG_LRU_GEN=y +CONFIG_LRU_GEN_ENABLED=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU=m +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BBR=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_MPTCP=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_ATM=m +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_BATMAN_ADV=m +CONFIG_OPENVSWITCH=m +CONFIG_VSOCKETS=m +CONFIG_CGROUP_NET_PRIO=y +CONFIG_NET_PKTGEN=m +CONFIG_HAMRADIO=y +CONFIG_AX25=m +CONFIG_NETROM=m +CONFIG_ROSE=m +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_YAM=m +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_6LOWPAN=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_NET_9P=m +CONFIG_NFC=m +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM_POWERSAVE=y +CONFIG_PCIE_DPC=y +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_BRCMSTB_GISB_ARB is not set +CONFIG_RASPBERRYPI_FIRMWARE=y +# CONFIG_EFI_VARS_PSTORE is not set +CONFIG_MTD=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK2MTD=m +CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_UBI=m +CONFIG_OF_CONFIGFS=y +CONFIG_ZRAM=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_BLK_DEV_NVME=y +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_TI_ST=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_ISCSI_ATTRS=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_ATA=m +CONFIG_SATA_AHCI=m +CONFIG_SATA_MV=m +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_DELAY=m +CONFIG_DM_INTEGRITY=m +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_IFB=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_TUN=m +CONFIG_VETH=m +CONFIG_NET_VRF=m +CONFIG_VSOCKMON=m +CONFIG_BCMGENET=y +CONFIG_MACB=y +CONFIG_ENC28J60=m +CONFIG_LAN743X=m +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +CONFIG_R8169=m +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5100_SPI=m +CONFIG_MICREL_PHY=y +CONFIG_CAN_VCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_MCP251X=m +CONFIG_CAN_MCP251XFD=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_MDIO_BITBANG=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=y +CONFIG_USB_LAN78XX=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=y +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_AQC111=m +CONFIG_ATH9K=m +CONFIG_ATH9K_HTC=m +CONFIG_CARL9170=m +CONFIG_ATH6KL=m +CONFIG_ATH6KL_USB=m +CONFIG_AR5523=m +CONFIG_AT76C50X_USB=m +CONFIG_B43=m +# CONFIG_B43_PHY_N is not set +CONFIG_B43LEGACY=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMDBG=y +CONFIG_HOSTAP=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x2U=m +CONFIG_MT7921U=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8187=m +CONFIG_RTL8192CU=m +CONFIG_RTL8XXXU=m +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_TCA6416=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_CAP11XX=m +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_RPISENSE=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_EGALAX=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_STMPE=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_RASPBERRYPI_BUTTON=m +CONFIG_SERIO=m +CONFIG_SERIO_RAW=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_BRCM_CHAR_DRIVERS=y +CONFIG_BCM_VCIO=y +CONFIG_RPIVID_MEM=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DMA is not set +CONFIG_SERIAL_8250_NR_UARTS=5 +CONFIG_SERIAL_8250_RUNTIME_UARTS=0 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_BCM2835AUX=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_SPI=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=y +CONFIG_HW_RANDOM=y +CONFIG_TCG_TPM=m +CONFIG_TCG_TIS_SPI=m +CONFIG_TCG_TIS_I2C=m +CONFIG_XILLYBUS=m +CONFIG_XILLYBUS_PCIE=m +CONFIG_XILLYUSB=m +CONFIG_RASPBERRYPI_GPIOMEM=m +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_PCA954x=m +CONFIG_I2C_MUX_PINCTRL=m +CONFIG_I2C_BCM2708=m +CONFIG_I2C_BCM2835=m +CONFIG_I2C_BRCMSTB=m +CONFIG_I2C_DESIGNWARE_PLATFORM=m +CONFIG_I2C_GPIO=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_TINY_USB=m +CONFIG_SPI=y +CONFIG_SPI_BCM2835=m +CONFIG_SPI_BCM2835AUX=m +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_GPIO=m +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SLAVE=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_PINCTRL_RP1=y +CONFIG_PINCTRL_BCM2712=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_BCM_VIRT=y +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_ARIZONA=m +CONFIG_GPIO_FSM=m +CONFIG_GPIO_STMPE=y +CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MOCKUP=m +CONFIG_W1=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m +# CONFIG_POWER_RESET_BRCMSTB is not set +CONFIG_POWER_RESET_GPIO=y +CONFIG_RPI_POE_POWER=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_MAX17040=m +CONFIG_CHARGER_GPIO=m +CONFIG_BATTERY_GAUGE_LTC2941=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_AHT10=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_RASPBERRYPI_HWMON=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_RP1_ADC=m +CONFIG_BCM2711_THERMAL=y +CONFIG_BCM2835_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_GPIO_WATCHDOG=m +CONFIG_BCM2835_WDT=y +CONFIG_MFD_RASPBERRYPI_POE_HAT=m +CONFIG_MFD_STMPE=y +CONFIG_STMPE_SPI=y +CONFIG_MFD_SYSCON=y +CONFIG_MFD_ARIZONA_I2C=m +CONFIG_MFD_ARIZONA_SPI=m +CONFIG_MFD_WM5102=y +CONFIG_MFD_RP1=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m +CONFIG_RC_CORE=y +CONFIG_BPF_LIRC_MODE2=y +CONFIG_LIRC=y +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_LOOPBACK=m +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_DVB_AS102=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m +CONFIG_USB_DSBR=m +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_MR800=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_I2C_SI4713=m +CONFIG_RADIO_WL128X=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MUX=m +CONFIG_VIDEO_BCM2835_UNICAM=m +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m +CONFIG_VIDEO_RP1_CFE=m +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VIDEO_VIM2M=m +CONFIG_VIDEO_VICODEC=m +CONFIG_VIDEO_VIMC=m +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_ARDUCAM_64MP=m +CONFIG_VIDEO_ARDUCAM_PIVARIETY=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX296=m +CONFIG_VIDEO_IMX477=m +CONFIG_VIDEO_IMX519=m +CONFIG_VIDEO_IMX708=m +CONFIG_VIDEO_MT9V011=m +CONFIG_VIDEO_OV2311=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV64A40=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV7640=m +CONFIG_VIDEO_AD5398=m +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_BU64754=m +CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_OV9281=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m +CONFIG_VIDEO_IRS1125=m +CONFIG_VIDEO_I2C=m +CONFIG_DRM=m +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_UDL=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m +CONFIG_DRM_PANEL_ILITEK_ILI9881C=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +CONFIG_DRM_PANEL_SITRONIX_ST7701=m +CONFIG_DRM_PANEL_TPO_Y17P=m +CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_V3D=m +CONFIG_DRM_VC4=m +CONFIG_DRM_VC4_HDMI_CEC=y +CONFIG_DRM_RP1_DSI=m +CONFIG_DRM_RP1_DPI=m +CONFIG_DRM_RP1_VEC=m +CONFIG_DRM_PANEL_MIPI_DBI=m +CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m +CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m +CONFIG_TINYDRM_ST7735R=m +CONFIG_DRM_GUD=m +CONFIG_FB=y +CONFIG_FB_BCM2708=y +CONFIG_FB_SIMPLE=y +CONFIG_FB_SSD1307=m +CONFIG_FB_RPISENSE=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_RPI=m +CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_GPIO=m +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_PCM_OSS=m +CONFIG_SND_HRTIMER=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_MPU401=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_SOC=m +CONFIG_SND_BCM2835_SOC_I2S=m +CONFIG_SND_BCM2708_SOC_CHIPDIP_DAC=m +CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSHD=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADC=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADCPRO=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSDSP=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m +CONFIG_SND_BCM2708_SOC_PIFI_40=m +CONFIG_SND_BCM2708_SOC_RPI_CIRRUS=m +CONFIG_SND_BCM2708_SOC_RPI_DAC=m +CONFIG_SND_BCM2708_SOC_RPI_PROTO=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_BOTH=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_CODEC=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI=m +CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m +CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m +CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m +CONFIG_SND_AUDIOSENSE_PI=m +CONFIG_SND_DIGIDAC1_SOUNDCARD=m +CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m +CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO_V2=m +CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS=m +CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_BOSS2_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE=m +CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC=m +CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO=m +CONFIG_SND_PISOUND=m +CONFIG_SND_DACBERRY400=m +CONFIG_SND_DESIGNWARE_I2S=m +CONFIG_SND_DESIGNWARE_PCM=y +CONFIG_SND_SOC_AD193X_SPI=m +CONFIG_SND_SOC_AD193X_I2C=m +CONFIG_SND_SOC_ADAU1701=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_AK4554=m +CONFIG_SND_SOC_CS4265=m +CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_APPLE=m +CONFIG_HID_ASUS=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_HOLTEK=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_GYRATION=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_NINTENDO_FF=y +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PLAYSTATION=m +CONFIG_PLAYSTATION_FF=y +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_GREENASIA=m +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_MON=m +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWCOTG=y +CONFIG_USB_PRINTER=m +CONFIG_USB_TMC=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=y +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VUDC=m +CONFIG_USB_DWC3=y +CONFIG_USB_DWC2=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_TEST=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_HID=m +CONFIG_USB_G_WEBCAM=m +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_BCM2835_MMC=y +CONFIG_MMC_BCM2835_DMA=y +CONFIG_MMC_BCM2835_SDHOST=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +CONFIG_MMC_SDHCI_IPROC=y +CONFIG_MMC_SPI=m +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA955X=m +CONFIG_LEDS_PCA963X=m +CONFIG_LEDS_PWM=y +CONFIG_LEDS_IS31FL32XX=m +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_INPUT=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_ACTPWR=y +CONFIG_ACCESSIBILITY=y +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_ISL12022=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_BQ32K=m +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_DS1302=m +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_RX4581=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_DMADEVICES=y +CONFIG_DMA_BCM2835=y +CONFIG_DW_AXI_DMAC=y +CONFIG_DMA_BCM2708=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_AUXDISPLAY=y +CONFIG_HD44780=m +CONFIG_UIO=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_VHOST_NET=m +CONFIG_VHOST_VSOCK=m +CONFIG_VHOST_CROSS_ENDIAN_LEGACY=y +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_R8712U=m +CONFIG_R8188EU=m +CONFIG_VT6656=m +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_RPIVID=m +CONFIG_STAGING_MEDIA_DEPRECATED=y +CONFIG_VIDEO_CPIA2=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_USB_ZR364XX=m +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m +CONFIG_FB_TFT_HX8340BN=m +CONFIG_FB_TFT_HX8347D=m +CONFIG_FB_TFT_HX8353D=m +CONFIG_FB_TFT_HX8357D=m +CONFIG_FB_TFT_ILI9163=m +CONFIG_FB_TFT_ILI9320=m +CONFIG_FB_TFT_ILI9325=m +CONFIG_FB_TFT_ILI9340=m +CONFIG_FB_TFT_ILI9341=m +CONFIG_FB_TFT_ILI9481=m +CONFIG_FB_TFT_ILI9486=m +CONFIG_FB_TFT_PCD8544=m +CONFIG_FB_TFT_RA8875=m +CONFIG_FB_TFT_S6D02A1=m +CONFIG_FB_TFT_S6D1121=m +CONFIG_FB_TFT_SH1106=m +CONFIG_FB_TFT_SSD1289=m +CONFIG_FB_TFT_SSD1306=m +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m +CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m +CONFIG_BCM2835_VCHIQ=y +CONFIG_SND_BCM2835=m +CONFIG_VIDEO_BCM2835=m +CONFIG_VIDEO_CODEC_BCM2835=m +CONFIG_VIDEO_ISP_BCM2835=m +CONFIG_COMMON_CLK_RP1=y +CONFIG_COMMON_CLK_RP1_SDIO=y +CONFIG_CLK_RASPBERRYPI=y +CONFIG_MAILBOX=y +CONFIG_BCM2835_MBOX=y +CONFIG_BCM2712_IOMMU=y +CONFIG_RASPBERRYPI_POWER=y +CONFIG_IIO=m +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m +CONFIG_TI_ADS1015=m +CONFIG_BME680=m +CONFIG_CCS811=m +CONFIG_SENSIRION_SGP30=m +CONFIG_SPS30_I2C=m +CONFIG_MAX30102=m +CONFIG_DHT11=m +CONFIG_HDC100X=m +CONFIG_HTU21=m +CONFIG_SI7020=m +CONFIG_BOSCH_BNO055_I2C=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_APDS9960=m +CONFIG_BH1750=m +CONFIG_TSL4531=m +CONFIG_VEML6070=m +CONFIG_IIO_HRTIMER_TRIGGER=m +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_BMP280=m +CONFIG_MS5637=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_MAX31856=m +CONFIG_PWM=y +CONFIG_PWM_BCM2835=m +CONFIG_PWM_BRCMSTB=y +CONFIG_PWM_PCA9685=m +CONFIG_PWM_RASPBERRYPI_POE=m +CONFIG_PWM_RP1=y +CONFIG_BCM2712_MIP=y +CONFIG_RPI_AXIPERF=m +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_BINDERFS=y +CONFIG_NVMEM_RMEM=m +CONFIG_MUX_GPIO=m +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_REISERFS_FS=m +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +CONFIG_JFS_STATISTICS=y +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_GFS2_FS=m +CONFIG_OCFS2_FS=m +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FANOTIFY=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_NTFS3_FS=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=m +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_SUMMARY=y +CONFIG_UBIFS_FS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFSD=m +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_CEPH_FS=m +CONFIG_CIFS=m +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y +CONFIG_SMB_SERVER=m +CONFIG_9P_FS=m +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_DLM=m +CONFIG_SECURITY=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_LSM="" +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_HMAC=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_GHASH_ARM64_CE=m +CONFIG_CRYPTO_SHA1_ARM64_CE=m +CONFIG_CRYPTO_SHA2_ARM64_CE=m +CONFIG_CRYPTO_SHA512_ARM64_CE=m +CONFIG_CRYPTO_SHA3_ARM64=m +CONFIG_CRYPTO_SM3_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64=m +CONFIG_CRYPTO_AES_ARM64_CE_BLK=m +CONFIG_CRYPTO_AES_ARM64_BS=m +CONFIG_CRYPTO_SM4_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=m +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_ITU_T=y +CONFIG_LIBCRC32C=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=5 +CONFIG_PRINTK_TIME=y +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_KEYBOARD=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_LATENCYTOP=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_UPROBE_EVENTS is not set +# CONFIG_STRICT_DEVMEM is not set diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/configs/bcmrpi3_defconfig linux/arch/arm64/configs/bcmrpi3_defconfig --- linux-6.1.66/arch/arm64/configs/bcmrpi3_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/configs/bcmrpi3_defconfig 2023-12-13 11:50:49.566963550 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +CONFIG_LOCALVERSION="-v8" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_PREEMPT=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCM2835=y +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +CONFIG_SCHED_MC=y +CONFIG_NR_CPUS=4 +CONFIG_HZ_1000=y +CONFIG_COMPAT=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" +# CONFIG_SUSPEND is not set +CONFIG_PM=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_RASPBERRYPI_CPUFREQ=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_COMPRESS_XZ=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y +CONFIG_BINFMT_MISC=y +CONFIG_ZSWAP=y +CONFIG_Z3FOLD=m +# CONFIG_COMPAT_BRK is not set +CONFIG_CMA=y +CONFIG_LRU_GEN=y +CONFIG_LRU_GEN_ENABLED=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_NET_FOU=m +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BBR=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_MPTCP=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_ATM=m +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_BATMAN_ADV=m +CONFIG_OPENVSWITCH=m +CONFIG_VSOCKETS=m +CONFIG_CGROUP_NET_PRIO=y +CONFIG_NET_PKTGEN=m +CONFIG_HAMRADIO=y +CONFIG_AX25=m +CONFIG_NETROM=m +CONFIG_ROSE=m +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_YAM=m +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_6LOWPAN=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_NET_9P=m +CONFIG_NFC=m +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_RASPBERRYPI_FIRMWARE=y +# CONFIG_EFI_VARS_PSTORE is not set +CONFIG_MTD=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_UBI=m +CONFIG_OF_CONFIGFS=y +CONFIG_ZRAM=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_TI_ST=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_ISCSI_ATTRS=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_ATA=m +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_DELAY=m +CONFIG_DM_INTEGRITY=m +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_IFB=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_VXLAN=m +CONFIG_NETCONSOLE=m +CONFIG_TUN=m +CONFIG_VETH=m +CONFIG_NET_VRF=m +CONFIG_VSOCKMON=m +CONFIG_ENC28J60=m +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5100_SPI=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_MCP251X=m +CONFIG_CAN_MCP251XFD=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_MDIO_BITBANG=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=y +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_AQC111=m +CONFIG_ATH9K=m +CONFIG_ATH9K_HTC=m +CONFIG_CARL9170=m +CONFIG_ATH6KL=m +CONFIG_ATH6KL_USB=m +CONFIG_AR5523=m +CONFIG_AT76C50X_USB=m +CONFIG_B43=m +# CONFIG_B43_PHY_N is not set +CONFIG_B43LEGACY=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_USB=y +CONFIG_HOSTAP=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x2U=m +CONFIG_MT7921U=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8187=m +CONFIG_RTL8192CU=m +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_TCA6416=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_CAP11XX=m +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_RPISENSE=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_EGALAX=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_EKTF2127=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_STMPE=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_CMA3000=m +CONFIG_SERIO=m +CONFIG_SERIO_RAW=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_BRCM_CHAR_DRIVERS=y +CONFIG_BCM_VCIO=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DMA is not set +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=0 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_BCM2835AUX=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_SPI=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=y +CONFIG_HW_RANDOM=y +CONFIG_TCG_TPM=m +CONFIG_TCG_TIS_SPI=m +CONFIG_TCG_TIS_I2C=m +CONFIG_RASPBERRYPI_GPIOMEM=m +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_PCA954x=m +CONFIG_I2C_MUX_PINCTRL=m +CONFIG_I2C_BCM2708=m +CONFIG_I2C_BCM2835=m +CONFIG_I2C_GPIO=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_TINY_USB=m +CONFIG_SPI=y +CONFIG_SPI_BCM2835=m +CONFIG_SPI_BCM2835AUX=m +CONFIG_SPI_GPIO=m +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SLAVE=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_BCM_VIRT=y +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_ARIZONA=m +CONFIG_GPIO_FSM=m +CONFIG_GPIO_STMPE=y +CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MOCKUP=m +CONFIG_W1=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m +CONFIG_POWER_RESET_GPIO=y +CONFIG_RPI_POE_POWER=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_MAX17040=m +CONFIG_CHARGER_GPIO=m +CONFIG_BATTERY_GAUGE_LTC2941=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_AHT10=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_RASPBERRYPI_HWMON=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_TMP102=m +CONFIG_BCM2835_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_GPIO_WATCHDOG=m +CONFIG_BCM2835_WDT=y +CONFIG_MFD_RASPBERRYPI_POE_HAT=m +CONFIG_MFD_STMPE=y +CONFIG_STMPE_SPI=y +CONFIG_MFD_SYSCON=y +CONFIG_MFD_ARIZONA_I2C=m +CONFIG_MFD_ARIZONA_SPI=m +CONFIG_MFD_WM5102=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m +CONFIG_RC_CORE=y +CONFIG_BPF_LIRC_MODE2=y +CONFIG_LIRC=y +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_LOOPBACK=m +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_AU0828=m +CONFIG_DVB_AS102=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_SMS_USB_DRV=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m +CONFIG_USB_DSBR=m +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_MR800=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_I2C_SI4713=m +CONFIG_RADIO_WL128X=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MUX=m +CONFIG_VIDEO_BCM2835_UNICAM=m +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VIDEO_VIM2M=m +CONFIG_VIDEO_VICODEC=m +CONFIG_VIDEO_VIMC=m +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_ARDUCAM_64MP=m +CONFIG_VIDEO_ARDUCAM_PIVARIETY=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX296=m +CONFIG_VIDEO_IMX477=m +CONFIG_VIDEO_IMX519=m +CONFIG_VIDEO_IMX708=m +CONFIG_VIDEO_MT9V011=m +CONFIG_VIDEO_OV2311=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV64A40=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV7640=m +CONFIG_VIDEO_AD5398=m +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_BU64754=m +CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_OV9281=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m +CONFIG_VIDEO_IRS1125=m +CONFIG_VIDEO_I2C=m +CONFIG_DRM=m +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_UDL=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m +CONFIG_DRM_PANEL_ILITEK_ILI9881C=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +CONFIG_DRM_PANEL_SITRONIX_ST7701=m +CONFIG_DRM_PANEL_TPO_Y17P=m +CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_VC4=m +CONFIG_DRM_VC4_HDMI_CEC=y +CONFIG_DRM_PANEL_MIPI_DBI=m +CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m +CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m +CONFIG_TINYDRM_ST7735R=m +CONFIG_DRM_GUD=m +CONFIG_FB=y +CONFIG_FB_BCM2708=y +CONFIG_FB_SIMPLE=y +CONFIG_FB_SSD1307=m +CONFIG_FB_RPISENSE=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_RPI=m +CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_GPIO=m +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_PCM_OSS=m +CONFIG_SND_HRTIMER=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_MPU401=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_SOC=m +CONFIG_SND_BCM2835_SOC_I2S=m +CONFIG_SND_BCM2708_SOC_CHIPDIP_DAC=m +CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSHD=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADC=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADCPRO=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSDSP=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m +CONFIG_SND_BCM2708_SOC_PIFI_40=m +CONFIG_SND_BCM2708_SOC_RPI_CIRRUS=m +CONFIG_SND_BCM2708_SOC_RPI_DAC=m +CONFIG_SND_BCM2708_SOC_RPI_PROTO=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_BOTH=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_CODEC=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI=m +CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m +CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m +CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m +CONFIG_SND_AUDIOSENSE_PI=m +CONFIG_SND_DIGIDAC1_SOUNDCARD=m +CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m +CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO_V2=m +CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS=m +CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_BOSS2_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE=m +CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC=m +CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO=m +CONFIG_SND_PISOUND=m +CONFIG_SND_DACBERRY400=m +CONFIG_SND_SOC_AD193X_SPI=m +CONFIG_SND_SOC_AD193X_I2C=m +CONFIG_SND_SOC_ADAU1701=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_AK4554=m +CONFIG_SND_SOC_CS4265=m +CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_APPLE=m +CONFIG_HID_ASUS=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_HOLTEK=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_GYRATION=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_NINTENDO_FF=y +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PLAYSTATION=m +CONFIG_PLAYSTATION_FF=y +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_GREENASIA=m +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_MON=m +CONFIG_USB_DWCOTG=y +CONFIG_USB_PRINTER=m +CONFIG_USB_TMC=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_TEST=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_GADGET=y +CONFIG_U_SERIAL_CONSOLE=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_HID=m +CONFIG_USB_G_WEBCAM=m +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_BCM2835_MMC=y +CONFIG_MMC_BCM2835_DMA=y +CONFIG_MMC_BCM2835_SDHOST=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_IPROC=m +CONFIG_MMC_SPI=m +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA955X=m +CONFIG_LEDS_PCA963X=m +CONFIG_LEDS_PWM=y +CONFIG_LEDS_IS31FL32XX=m +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_INPUT=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_ACTPWR=y +CONFIG_ACCESSIBILITY=y +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_ISL12022=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_BQ32K=m +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_DS1302=m +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_RX4581=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_DMADEVICES=y +CONFIG_DMA_BCM2835=y +CONFIG_DMA_BCM2708=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_UIO=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_VHOST_VSOCK=m +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_R8712U=m +CONFIG_R8188EU=m +CONFIG_VT6656=m +CONFIG_STAGING_MEDIA=y +CONFIG_STAGING_MEDIA_DEPRECATED=y +CONFIG_VIDEO_CPIA2=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_USB_ZR364XX=m +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m +CONFIG_FB_TFT_HX8340BN=m +CONFIG_FB_TFT_HX8347D=m +CONFIG_FB_TFT_HX8353D=m +CONFIG_FB_TFT_HX8357D=m +CONFIG_FB_TFT_ILI9163=m +CONFIG_FB_TFT_ILI9320=m +CONFIG_FB_TFT_ILI9325=m +CONFIG_FB_TFT_ILI9340=m +CONFIG_FB_TFT_ILI9341=m +CONFIG_FB_TFT_ILI9481=m +CONFIG_FB_TFT_ILI9486=m +CONFIG_FB_TFT_PCD8544=m +CONFIG_FB_TFT_RA8875=m +CONFIG_FB_TFT_S6D02A1=m +CONFIG_FB_TFT_S6D1121=m +CONFIG_FB_TFT_SH1106=m +CONFIG_FB_TFT_SSD1289=m +CONFIG_FB_TFT_SSD1306=m +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m +CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m +CONFIG_BCM2835_VCHIQ=y +CONFIG_SND_BCM2835=m +CONFIG_VIDEO_BCM2835=m +CONFIG_VIDEO_CODEC_BCM2835=m +CONFIG_VIDEO_ISP_BCM2835=m +CONFIG_CLK_RASPBERRYPI=y +CONFIG_MAILBOX=y +CONFIG_BCM2835_MBOX=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RASPBERRYPI_POWER=y +CONFIG_IIO=m +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m +CONFIG_TI_ADS1015=m +CONFIG_BME680=m +CONFIG_CCS811=m +CONFIG_SENSIRION_SGP30=m +CONFIG_SPS30_I2C=m +CONFIG_MAX30102=m +CONFIG_DHT11=m +CONFIG_HDC100X=m +CONFIG_HTU21=m +CONFIG_SI7020=m +CONFIG_BOSCH_BNO055_I2C=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_APDS9960=m +CONFIG_BH1750=m +CONFIG_TSL4531=m +CONFIG_VEML6070=m +CONFIG_IIO_HRTIMER_TRIGGER=m +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_BMP280=m +CONFIG_MS5637=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_MAX31856=m +CONFIG_PWM=y +CONFIG_PWM_BCM2835=m +CONFIG_PWM_PCA9685=m +CONFIG_PWM_RASPBERRYPI_POE=m +CONFIG_RPI_AXIPERF=m +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_BINDERFS=y +CONFIG_NVMEM_RMEM=m +CONFIG_MUX_GPIO=m +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_REISERFS_FS=m +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +CONFIG_JFS_STATISTICS=y +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_GFS2_FS=m +CONFIG_OCFS2_FS=m +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FANOTIFY=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_NTFS3_FS=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=m +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_SUMMARY=y +CONFIG_UBIFS_FS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFSD=m +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_CEPH_FS=m +CONFIG_CIFS=m +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y +CONFIG_SMB_SERVER=m +CONFIG_9P_FS=m +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_DLM=m +CONFIG_SECURITY=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_LSM="" +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_AES_ARM64=m +CONFIG_CRYPTO_AES_ARM64_BS=m +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_ITU_T=y +CONFIG_LIBCRC32C=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=5 +CONFIG_PRINTK_TIME=y +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_KEYBOARD=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_LATENCYTOP=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_UPROBE_EVENTS is not set diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/crypto/aes-cipher-glue.c linux/arch/arm64/crypto/aes-cipher-glue.c --- linux-6.1.66/arch/arm64/crypto/aes-cipher-glue.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm64/crypto/aes-cipher-glue.c 2023-12-13 11:50:49.569963557 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:12 @ #include <linux/crypto.h> #include <linux/module.h> +MODULE_ALIAS_CRYPTO("ecb(aes)"); +MODULE_ALIAS_CRYPTO("cbc(aes)"); +MODULE_ALIAS_CRYPTO("ctr(aes)"); +MODULE_ALIAS_CRYPTO("xts(aes)"); +MODULE_ALIAS_CRYPTO("xctr(aes)"); +MODULE_ALIAS_CRYPTO("cts(cbc(aes))"); +MODULE_ALIAS_CRYPTO("essiv(cbc(aes),sha256)"); +MODULE_ALIAS_CRYPTO("cmac(aes)"); +MODULE_ALIAS_CRYPTO("xcbc(aes)"); +MODULE_ALIAS_CRYPTO("cbcmac(aes)"); + asmlinkage void __aes_arm64_encrypt(u32 *rk, u8 *out, const u8 *in, int rounds); asmlinkage void __aes_arm64_decrypt(u32 *rk, u8 *out, const u8 *in, int rounds); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/crypto/aes-glue.c linux/arch/arm64/crypto/aes-glue.c --- linux-6.1.66/arch/arm64/crypto/aes-glue.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm64/crypto/aes-glue.c 2023-12-13 11:50:49.570963559 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:60 @ #define aes_mac_update neon_aes_mac_update MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS/XCTR using ARMv8 NEON"); #endif -#if defined(USE_V8_CRYPTO_EXTENSIONS) || !IS_ENABLED(CONFIG_CRYPTO_AES_ARM64_BS) +#if defined(USE_V8_CRYPTO_EXTENSIONS) MODULE_ALIAS_CRYPTO("ecb(aes)"); MODULE_ALIAS_CRYPTO("cbc(aes)"); MODULE_ALIAS_CRYPTO("ctr(aes)"); MODULE_ALIAS_CRYPTO("xts(aes)"); MODULE_ALIAS_CRYPTO("xctr(aes)"); -#endif MODULE_ALIAS_CRYPTO("cts(cbc(aes))"); MODULE_ALIAS_CRYPTO("essiv(cbc(aes),sha256)"); MODULE_ALIAS_CRYPTO("cmac(aes)"); MODULE_ALIAS_CRYPTO("xcbc(aes)"); MODULE_ALIAS_CRYPTO("cbcmac(aes)"); +#endif MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); MODULE_LICENSE("GPL v2"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/crypto/aes-neonbs-glue.c linux/arch/arm64/crypto/aes-neonbs-glue.c --- linux-6.1.66/arch/arm64/crypto/aes-neonbs-glue.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm64/crypto/aes-neonbs-glue.c 2023-12-13 11:50:49.571963561 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:21 @ MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); MODULE_LICENSE("GPL v2"); -MODULE_ALIAS_CRYPTO("ecb(aes)"); -MODULE_ALIAS_CRYPTO("cbc(aes)"); -MODULE_ALIAS_CRYPTO("ctr(aes)"); -MODULE_ALIAS_CRYPTO("xts(aes)"); - asmlinkage void aesbs_convert_key(u8 out[], u32 const rk[], int rounds); asmlinkage void aesbs_ecb_encrypt(u8 out[], u8 const in[], u8 const rk[], diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/crypto/poly1305-core.S linux/arch/arm64/crypto/poly1305-core.S --- linux-6.1.66/arch/arm64/crypto/poly1305-core.S 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/crypto/poly1305-core.S 2023-12-14 11:56:47.370767516 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +#ifndef __KERNEL__ +# include "arm_arch.h" +.extern OPENSSL_armcap_P +#endif + +.text + +// forward "declarations" are required for Apple +.globl poly1305_blocks +.globl poly1305_emit + +.globl poly1305_init +.type poly1305_init,%function +.align 5 +poly1305_init: + cmp x1,xzr + stp xzr,xzr,[x0] // zero hash value + stp xzr,xzr,[x0,#16] // [along with is_base2_26] + + csel x0,xzr,x0,eq + b.eq .Lno_key + +#ifndef __KERNEL__ + adrp x17,OPENSSL_armcap_P + ldr w17,[x17,#:lo12:OPENSSL_armcap_P] +#endif + + ldp x7,x8,[x1] // load key + mov x9,#0xfffffffc0fffffff + movk x9,#0x0fff,lsl#48 +#ifdef __AARCH64EB__ + rev x7,x7 // flip bytes + rev x8,x8 +#endif + and x7,x7,x9 // &=0ffffffc0fffffff + and x9,x9,#-4 + and x8,x8,x9 // &=0ffffffc0ffffffc + mov w9,#-1 + stp x7,x8,[x0,#32] // save key value + str w9,[x0,#48] // impossible key power value + +#ifndef __KERNEL__ + tst w17,#ARMV7_NEON + + adr x12,.Lpoly1305_blocks + adr x7,.Lpoly1305_blocks_neon + adr x13,.Lpoly1305_emit + + csel x12,x12,x7,eq + +# ifdef __ILP32__ + stp w12,w13,[x2] +# else + stp x12,x13,[x2] +# endif +#endif + mov x0,#1 +.Lno_key: + ret +.size poly1305_init,.-poly1305_init + +.type poly1305_blocks,%function +.align 5 +poly1305_blocks: +.Lpoly1305_blocks: + ands x2,x2,#-16 + b.eq .Lno_data + + ldp x4,x5,[x0] // load hash value + ldp x6,x17,[x0,#16] // [along with is_base2_26] + ldp x7,x8,[x0,#32] // load key value + +#ifdef __AARCH64EB__ + lsr x12,x4,#32 + mov w13,w4 + lsr x14,x5,#32 + mov w15,w5 + lsr x16,x6,#32 +#else + mov w12,w4 + lsr x13,x4,#32 + mov w14,w5 + lsr x15,x5,#32 + mov w16,w6 +#endif + + add x12,x12,x13,lsl#26 // base 2^26 -> base 2^64 + lsr x13,x14,#12 + adds x12,x12,x14,lsl#52 + add x13,x13,x15,lsl#14 + adc x13,x13,xzr + lsr x14,x16,#24 + adds x13,x13,x16,lsl#40 + adc x14,x14,xzr + + cmp x17,#0 // is_base2_26? + add x9,x8,x8,lsr#2 // s1 = r1 + (r1 >> 2) + csel x4,x4,x12,eq // choose between radixes + csel x5,x5,x13,eq + csel x6,x6,x14,eq + +.Loop: + ldp x10,x11,[x1],#16 // load input + sub x2,x2,#16 +#ifdef __AARCH64EB__ + rev x10,x10 + rev x11,x11 +#endif + adds x4,x4,x10 // accumulate input + adcs x5,x5,x11 + + mul x12,x4,x7 // h0*r0 + adc x6,x6,x3 + umulh x13,x4,x7 + + mul x10,x5,x9 // h1*5*r1 + umulh x11,x5,x9 + + adds x12,x12,x10 + mul x10,x4,x8 // h0*r1 + adc x13,x13,x11 + umulh x14,x4,x8 + + adds x13,x13,x10 + mul x10,x5,x7 // h1*r0 + adc x14,x14,xzr + umulh x11,x5,x7 + + adds x13,x13,x10 + mul x10,x6,x9 // h2*5*r1 + adc x14,x14,x11 + mul x11,x6,x7 // h2*r0 + + adds x13,x13,x10 + adc x14,x14,x11 + + and x10,x14,#-4 // final reduction + and x6,x14,#3 + add x10,x10,x14,lsr#2 + adds x4,x12,x10 + adcs x5,x13,xzr + adc x6,x6,xzr + + cbnz x2,.Loop + + stp x4,x5,[x0] // store hash value + stp x6,xzr,[x0,#16] // [and clear is_base2_26] + +.Lno_data: + ret +.size poly1305_blocks,.-poly1305_blocks + +.type poly1305_emit,%function +.align 5 +poly1305_emit: +.Lpoly1305_emit: + ldp x4,x5,[x0] // load hash base 2^64 + ldp x6,x7,[x0,#16] // [along with is_base2_26] + ldp x10,x11,[x2] // load nonce + +#ifdef __AARCH64EB__ + lsr x12,x4,#32 + mov w13,w4 + lsr x14,x5,#32 + mov w15,w5 + lsr x16,x6,#32 +#else + mov w12,w4 + lsr x13,x4,#32 + mov w14,w5 + lsr x15,x5,#32 + mov w16,w6 +#endif + + add x12,x12,x13,lsl#26 // base 2^26 -> base 2^64 + lsr x13,x14,#12 + adds x12,x12,x14,lsl#52 + add x13,x13,x15,lsl#14 + adc x13,x13,xzr + lsr x14,x16,#24 + adds x13,x13,x16,lsl#40 + adc x14,x14,xzr + + cmp x7,#0 // is_base2_26? + csel x4,x4,x12,eq // choose between radixes + csel x5,x5,x13,eq + csel x6,x6,x14,eq + + adds x12,x4,#5 // compare to modulus + adcs x13,x5,xzr + adc x14,x6,xzr + + tst x14,#-4 // see if it's carried/borrowed + + csel x4,x4,x12,eq + csel x5,x5,x13,eq + +#ifdef __AARCH64EB__ + ror x10,x10,#32 // flip nonce words + ror x11,x11,#32 +#endif + adds x4,x4,x10 // accumulate nonce + adc x5,x5,x11 +#ifdef __AARCH64EB__ + rev x4,x4 // flip output bytes + rev x5,x5 +#endif + stp x4,x5,[x1] // write result + + ret +.size poly1305_emit,.-poly1305_emit +.type poly1305_mult,%function +.align 5 +poly1305_mult: + mul x12,x4,x7 // h0*r0 + umulh x13,x4,x7 + + mul x10,x5,x9 // h1*5*r1 + umulh x11,x5,x9 + + adds x12,x12,x10 + mul x10,x4,x8 // h0*r1 + adc x13,x13,x11 + umulh x14,x4,x8 + + adds x13,x13,x10 + mul x10,x5,x7 // h1*r0 + adc x14,x14,xzr + umulh x11,x5,x7 + + adds x13,x13,x10 + mul x10,x6,x9 // h2*5*r1 + adc x14,x14,x11 + mul x11,x6,x7 // h2*r0 + + adds x13,x13,x10 + adc x14,x14,x11 + + and x10,x14,#-4 // final reduction + and x6,x14,#3 + add x10,x10,x14,lsr#2 + adds x4,x12,x10 + adcs x5,x13,xzr + adc x6,x6,xzr + + ret +.size poly1305_mult,.-poly1305_mult + +.type poly1305_splat,%function +.align 4 +poly1305_splat: + and x12,x4,#0x03ffffff // base 2^64 -> base 2^26 + ubfx x13,x4,#26,#26 + extr x14,x5,x4,#52 + and x14,x14,#0x03ffffff + ubfx x15,x5,#14,#26 + extr x16,x6,x5,#40 + + str w12,[x0,#16*0] // r0 + add w12,w13,w13,lsl#2 // r1*5 + str w13,[x0,#16*1] // r1 + add w13,w14,w14,lsl#2 // r2*5 + str w12,[x0,#16*2] // s1 + str w14,[x0,#16*3] // r2 + add w14,w15,w15,lsl#2 // r3*5 + str w13,[x0,#16*4] // s2 + str w15,[x0,#16*5] // r3 + add w15,w16,w16,lsl#2 // r4*5 + str w14,[x0,#16*6] // s3 + str w16,[x0,#16*7] // r4 + str w15,[x0,#16*8] // s4 + + ret +.size poly1305_splat,.-poly1305_splat + +#ifdef __KERNEL__ +.globl poly1305_blocks_neon +#endif +.type poly1305_blocks_neon,%function +.align 5 +poly1305_blocks_neon: +.Lpoly1305_blocks_neon: + ldr x17,[x0,#24] + cmp x2,#128 + b.lo .Lpoly1305_blocks + + .inst 0xd503233f // paciasp + stp x29,x30,[sp,#-80]! + add x29,sp,#0 + + stp d8,d9,[sp,#16] // meet ABI requirements + stp d10,d11,[sp,#32] + stp d12,d13,[sp,#48] + stp d14,d15,[sp,#64] + + cbz x17,.Lbase2_64_neon + + ldp w10,w11,[x0] // load hash value base 2^26 + ldp w12,w13,[x0,#8] + ldr w14,[x0,#16] + + tst x2,#31 + b.eq .Leven_neon + + ldp x7,x8,[x0,#32] // load key value + + add x4,x10,x11,lsl#26 // base 2^26 -> base 2^64 + lsr x5,x12,#12 + adds x4,x4,x12,lsl#52 + add x5,x5,x13,lsl#14 + adc x5,x5,xzr + lsr x6,x14,#24 + adds x5,x5,x14,lsl#40 + adc x14,x6,xzr // can be partially reduced... + + ldp x12,x13,[x1],#16 // load input + sub x2,x2,#16 + add x9,x8,x8,lsr#2 // s1 = r1 + (r1 >> 2) + +#ifdef __AARCH64EB__ + rev x12,x12 + rev x13,x13 +#endif + adds x4,x4,x12 // accumulate input + adcs x5,x5,x13 + adc x6,x6,x3 + + bl poly1305_mult + + and x10,x4,#0x03ffffff // base 2^64 -> base 2^26 + ubfx x11,x4,#26,#26 + extr x12,x5,x4,#52 + and x12,x12,#0x03ffffff + ubfx x13,x5,#14,#26 + extr x14,x6,x5,#40 + + b .Leven_neon + +.align 4 +.Lbase2_64_neon: + ldp x7,x8,[x0,#32] // load key value + + ldp x4,x5,[x0] // load hash value base 2^64 + ldr x6,[x0,#16] + + tst x2,#31 + b.eq .Linit_neon + + ldp x12,x13,[x1],#16 // load input + sub x2,x2,#16 + add x9,x8,x8,lsr#2 // s1 = r1 + (r1 >> 2) +#ifdef __AARCH64EB__ + rev x12,x12 + rev x13,x13 +#endif + adds x4,x4,x12 // accumulate input + adcs x5,x5,x13 + adc x6,x6,x3 + + bl poly1305_mult + +.Linit_neon: + ldr w17,[x0,#48] // first table element + and x10,x4,#0x03ffffff // base 2^64 -> base 2^26 + ubfx x11,x4,#26,#26 + extr x12,x5,x4,#52 + and x12,x12,#0x03ffffff + ubfx x13,x5,#14,#26 + extr x14,x6,x5,#40 + + cmp w17,#-1 // is value impossible? + b.ne .Leven_neon + + fmov d24,x10 + fmov d25,x11 + fmov d26,x12 + fmov d27,x13 + fmov d28,x14 + + ////////////////////////////////// initialize r^n table + mov x4,x7 // r^1 + add x9,x8,x8,lsr#2 // s1 = r1 + (r1 >> 2) + mov x5,x8 + mov x6,xzr + add x0,x0,#48+12 + bl poly1305_splat + + bl poly1305_mult // r^2 + sub x0,x0,#4 + bl poly1305_splat + + bl poly1305_mult // r^3 + sub x0,x0,#4 + bl poly1305_splat + + bl poly1305_mult // r^4 + sub x0,x0,#4 + bl poly1305_splat + sub x0,x0,#48 // restore original x0 + b .Ldo_neon + +.align 4 +.Leven_neon: + fmov d24,x10 + fmov d25,x11 + fmov d26,x12 + fmov d27,x13 + fmov d28,x14 + +.Ldo_neon: + ldp x8,x12,[x1,#32] // inp[2:3] + subs x2,x2,#64 + ldp x9,x13,[x1,#48] + add x16,x1,#96 + adr x17,.Lzeros + + lsl x3,x3,#24 + add x15,x0,#48 + +#ifdef __AARCH64EB__ + rev x8,x8 + rev x12,x12 + rev x9,x9 + rev x13,x13 +#endif + and x4,x8,#0x03ffffff // base 2^64 -> base 2^26 + and x5,x9,#0x03ffffff + ubfx x6,x8,#26,#26 + ubfx x7,x9,#26,#26 + add x4,x4,x5,lsl#32 // bfi x4,x5,#32,#32 + extr x8,x12,x8,#52 + extr x9,x13,x9,#52 + add x6,x6,x7,lsl#32 // bfi x6,x7,#32,#32 + fmov d14,x4 + and x8,x8,#0x03ffffff + and x9,x9,#0x03ffffff + ubfx x10,x12,#14,#26 + ubfx x11,x13,#14,#26 + add x12,x3,x12,lsr#40 + add x13,x3,x13,lsr#40 + add x8,x8,x9,lsl#32 // bfi x8,x9,#32,#32 + fmov d15,x6 + add x10,x10,x11,lsl#32 // bfi x10,x11,#32,#32 + add x12,x12,x13,lsl#32 // bfi x12,x13,#32,#32 + fmov d16,x8 + fmov d17,x10 + fmov d18,x12 + + ldp x8,x12,[x1],#16 // inp[0:1] + ldp x9,x13,[x1],#48 + + ld1 {v0.4s,v1.4s,v2.4s,v3.4s},[x15],#64 + ld1 {v4.4s,v5.4s,v6.4s,v7.4s},[x15],#64 + ld1 {v8.4s},[x15] + +#ifdef __AARCH64EB__ + rev x8,x8 + rev x12,x12 + rev x9,x9 + rev x13,x13 +#endif + and x4,x8,#0x03ffffff // base 2^64 -> base 2^26 + and x5,x9,#0x03ffffff + ubfx x6,x8,#26,#26 + ubfx x7,x9,#26,#26 + add x4,x4,x5,lsl#32 // bfi x4,x5,#32,#32 + extr x8,x12,x8,#52 + extr x9,x13,x9,#52 + add x6,x6,x7,lsl#32 // bfi x6,x7,#32,#32 + fmov d9,x4 + and x8,x8,#0x03ffffff + and x9,x9,#0x03ffffff + ubfx x10,x12,#14,#26 + ubfx x11,x13,#14,#26 + add x12,x3,x12,lsr#40 + add x13,x3,x13,lsr#40 + add x8,x8,x9,lsl#32 // bfi x8,x9,#32,#32 + fmov d10,x6 + add x10,x10,x11,lsl#32 // bfi x10,x11,#32,#32 + add x12,x12,x13,lsl#32 // bfi x12,x13,#32,#32 + movi v31.2d,#-1 + fmov d11,x8 + fmov d12,x10 + fmov d13,x12 + ushr v31.2d,v31.2d,#38 + + b.ls .Lskip_loop + +.align 4 +.Loop_neon: + //////////////////////////////////////////////////////////////// + // ((inp[0]*r^4+inp[2]*r^2+inp[4])*r^4+inp[6]*r^2 + // ((inp[1]*r^4+inp[3]*r^2+inp[5])*r^3+inp[7]*r + // ___________________/ + // ((inp[0]*r^4+inp[2]*r^2+inp[4])*r^4+inp[6]*r^2+inp[8])*r^2 + // ((inp[1]*r^4+inp[3]*r^2+inp[5])*r^4+inp[7]*r^2+inp[9])*r + // ___________________/ ____________________/ + // + // Note that we start with inp[2:3]*r^2. This is because it + // doesn't depend on reduction in previous iteration. + //////////////////////////////////////////////////////////////// + // d4 = h0*r4 + h1*r3 + h2*r2 + h3*r1 + h4*r0 + // d3 = h0*r3 + h1*r2 + h2*r1 + h3*r0 + h4*5*r4 + // d2 = h0*r2 + h1*r1 + h2*r0 + h3*5*r4 + h4*5*r3 + // d1 = h0*r1 + h1*r0 + h2*5*r4 + h3*5*r3 + h4*5*r2 + // d0 = h0*r0 + h1*5*r4 + h2*5*r3 + h3*5*r2 + h4*5*r1 + + subs x2,x2,#64 + umull v23.2d,v14.2s,v7.s[2] + csel x16,x17,x16,lo + umull v22.2d,v14.2s,v5.s[2] + umull v21.2d,v14.2s,v3.s[2] + ldp x8,x12,[x16],#16 // inp[2:3] (or zero) + umull v20.2d,v14.2s,v1.s[2] + ldp x9,x13,[x16],#48 + umull v19.2d,v14.2s,v0.s[2] +#ifdef __AARCH64EB__ + rev x8,x8 + rev x12,x12 + rev x9,x9 + rev x13,x13 +#endif + + umlal v23.2d,v15.2s,v5.s[2] + and x4,x8,#0x03ffffff // base 2^64 -> base 2^26 + umlal v22.2d,v15.2s,v3.s[2] + and x5,x9,#0x03ffffff + umlal v21.2d,v15.2s,v1.s[2] + ubfx x6,x8,#26,#26 + umlal v20.2d,v15.2s,v0.s[2] + ubfx x7,x9,#26,#26 + umlal v19.2d,v15.2s,v8.s[2] + add x4,x4,x5,lsl#32 // bfi x4,x5,#32,#32 + + umlal v23.2d,v16.2s,v3.s[2] + extr x8,x12,x8,#52 + umlal v22.2d,v16.2s,v1.s[2] + extr x9,x13,x9,#52 + umlal v21.2d,v16.2s,v0.s[2] + add x6,x6,x7,lsl#32 // bfi x6,x7,#32,#32 + umlal v20.2d,v16.2s,v8.s[2] + fmov d14,x4 + umlal v19.2d,v16.2s,v6.s[2] + and x8,x8,#0x03ffffff + + umlal v23.2d,v17.2s,v1.s[2] + and x9,x9,#0x03ffffff + umlal v22.2d,v17.2s,v0.s[2] + ubfx x10,x12,#14,#26 + umlal v21.2d,v17.2s,v8.s[2] + ubfx x11,x13,#14,#26 + umlal v20.2d,v17.2s,v6.s[2] + add x8,x8,x9,lsl#32 // bfi x8,x9,#32,#32 + umlal v19.2d,v17.2s,v4.s[2] + fmov d15,x6 + + add v11.2s,v11.2s,v26.2s + add x12,x3,x12,lsr#40 + umlal v23.2d,v18.2s,v0.s[2] + add x13,x3,x13,lsr#40 + umlal v22.2d,v18.2s,v8.s[2] + add x10,x10,x11,lsl#32 // bfi x10,x11,#32,#32 + umlal v21.2d,v18.2s,v6.s[2] + add x12,x12,x13,lsl#32 // bfi x12,x13,#32,#32 + umlal v20.2d,v18.2s,v4.s[2] + fmov d16,x8 + umlal v19.2d,v18.2s,v2.s[2] + fmov d17,x10 + + //////////////////////////////////////////////////////////////// + // (hash+inp[0:1])*r^4 and accumulate + + add v9.2s,v9.2s,v24.2s + fmov d18,x12 + umlal v22.2d,v11.2s,v1.s[0] + ldp x8,x12,[x1],#16 // inp[0:1] + umlal v19.2d,v11.2s,v6.s[0] + ldp x9,x13,[x1],#48 + umlal v23.2d,v11.2s,v3.s[0] + umlal v20.2d,v11.2s,v8.s[0] + umlal v21.2d,v11.2s,v0.s[0] +#ifdef __AARCH64EB__ + rev x8,x8 + rev x12,x12 + rev x9,x9 + rev x13,x13 +#endif + + add v10.2s,v10.2s,v25.2s + umlal v22.2d,v9.2s,v5.s[0] + umlal v23.2d,v9.2s,v7.s[0] + and x4,x8,#0x03ffffff // base 2^64 -> base 2^26 + umlal v21.2d,v9.2s,v3.s[0] + and x5,x9,#0x03ffffff + umlal v19.2d,v9.2s,v0.s[0] + ubfx x6,x8,#26,#26 + umlal v20.2d,v9.2s,v1.s[0] + ubfx x7,x9,#26,#26 + + add v12.2s,v12.2s,v27.2s + add x4,x4,x5,lsl#32 // bfi x4,x5,#32,#32 + umlal v22.2d,v10.2s,v3.s[0] + extr x8,x12,x8,#52 + umlal v23.2d,v10.2s,v5.s[0] + extr x9,x13,x9,#52 + umlal v19.2d,v10.2s,v8.s[0] + add x6,x6,x7,lsl#32 // bfi x6,x7,#32,#32 + umlal v21.2d,v10.2s,v1.s[0] + fmov d9,x4 + umlal v20.2d,v10.2s,v0.s[0] + and x8,x8,#0x03ffffff + + add v13.2s,v13.2s,v28.2s + and x9,x9,#0x03ffffff + umlal v22.2d,v12.2s,v0.s[0] + ubfx x10,x12,#14,#26 + umlal v19.2d,v12.2s,v4.s[0] + ubfx x11,x13,#14,#26 + umlal v23.2d,v12.2s,v1.s[0] + add x8,x8,x9,lsl#32 // bfi x8,x9,#32,#32 + umlal v20.2d,v12.2s,v6.s[0] + fmov d10,x6 + umlal v21.2d,v12.2s,v8.s[0] + add x12,x3,x12,lsr#40 + + umlal v22.2d,v13.2s,v8.s[0] + add x13,x3,x13,lsr#40 + umlal v19.2d,v13.2s,v2.s[0] + add x10,x10,x11,lsl#32 // bfi x10,x11,#32,#32 + umlal v23.2d,v13.2s,v0.s[0] + add x12,x12,x13,lsl#32 // bfi x12,x13,#32,#32 + umlal v20.2d,v13.2s,v4.s[0] + fmov d11,x8 + umlal v21.2d,v13.2s,v6.s[0] + fmov d12,x10 + fmov d13,x12 + + ///////////////////////////////////////////////////////////////// + // lazy reduction as discussed in "NEON crypto" by D.J. Bernstein + // and P. Schwabe + // + // [see discussion in poly1305-armv4 module] + + ushr v29.2d,v22.2d,#26 + xtn v27.2s,v22.2d + ushr v30.2d,v19.2d,#26 + and v19.16b,v19.16b,v31.16b + add v23.2d,v23.2d,v29.2d // h3 -> h4 + bic v27.2s,#0xfc,lsl#24 // &=0x03ffffff + add v20.2d,v20.2d,v30.2d // h0 -> h1 + + ushr v29.2d,v23.2d,#26 + xtn v28.2s,v23.2d + ushr v30.2d,v20.2d,#26 + xtn v25.2s,v20.2d + bic v28.2s,#0xfc,lsl#24 + add v21.2d,v21.2d,v30.2d // h1 -> h2 + + add v19.2d,v19.2d,v29.2d + shl v29.2d,v29.2d,#2 + shrn v30.2s,v21.2d,#26 + xtn v26.2s,v21.2d + add v19.2d,v19.2d,v29.2d // h4 -> h0 + bic v25.2s,#0xfc,lsl#24 + add v27.2s,v27.2s,v30.2s // h2 -> h3 + bic v26.2s,#0xfc,lsl#24 + + shrn v29.2s,v19.2d,#26 + xtn v24.2s,v19.2d + ushr v30.2s,v27.2s,#26 + bic v27.2s,#0xfc,lsl#24 + bic v24.2s,#0xfc,lsl#24 + add v25.2s,v25.2s,v29.2s // h0 -> h1 + add v28.2s,v28.2s,v30.2s // h3 -> h4 + + b.hi .Loop_neon + +.Lskip_loop: + dup v16.2d,v16.d[0] + add v11.2s,v11.2s,v26.2s + + //////////////////////////////////////////////////////////////// + // multiply (inp[0:1]+hash) or inp[2:3] by r^2:r^1 + + adds x2,x2,#32 + b.ne .Long_tail + + dup v16.2d,v11.d[0] + add v14.2s,v9.2s,v24.2s + add v17.2s,v12.2s,v27.2s + add v15.2s,v10.2s,v25.2s + add v18.2s,v13.2s,v28.2s + +.Long_tail: + dup v14.2d,v14.d[0] + umull2 v19.2d,v16.4s,v6.4s + umull2 v22.2d,v16.4s,v1.4s + umull2 v23.2d,v16.4s,v3.4s + umull2 v21.2d,v16.4s,v0.4s + umull2 v20.2d,v16.4s,v8.4s + + dup v15.2d,v15.d[0] + umlal2 v19.2d,v14.4s,v0.4s + umlal2 v21.2d,v14.4s,v3.4s + umlal2 v22.2d,v14.4s,v5.4s + umlal2 v23.2d,v14.4s,v7.4s + umlal2 v20.2d,v14.4s,v1.4s + + dup v17.2d,v17.d[0] + umlal2 v19.2d,v15.4s,v8.4s + umlal2 v22.2d,v15.4s,v3.4s + umlal2 v21.2d,v15.4s,v1.4s + umlal2 v23.2d,v15.4s,v5.4s + umlal2 v20.2d,v15.4s,v0.4s + + dup v18.2d,v18.d[0] + umlal2 v22.2d,v17.4s,v0.4s + umlal2 v23.2d,v17.4s,v1.4s + umlal2 v19.2d,v17.4s,v4.4s + umlal2 v20.2d,v17.4s,v6.4s + umlal2 v21.2d,v17.4s,v8.4s + + umlal2 v22.2d,v18.4s,v8.4s + umlal2 v19.2d,v18.4s,v2.4s + umlal2 v23.2d,v18.4s,v0.4s + umlal2 v20.2d,v18.4s,v4.4s + umlal2 v21.2d,v18.4s,v6.4s + + b.eq .Lshort_tail + + //////////////////////////////////////////////////////////////// + // (hash+inp[0:1])*r^4:r^3 and accumulate + + add v9.2s,v9.2s,v24.2s + umlal v22.2d,v11.2s,v1.2s + umlal v19.2d,v11.2s,v6.2s + umlal v23.2d,v11.2s,v3.2s + umlal v20.2d,v11.2s,v8.2s + umlal v21.2d,v11.2s,v0.2s + + add v10.2s,v10.2s,v25.2s + umlal v22.2d,v9.2s,v5.2s + umlal v19.2d,v9.2s,v0.2s + umlal v23.2d,v9.2s,v7.2s + umlal v20.2d,v9.2s,v1.2s + umlal v21.2d,v9.2s,v3.2s + + add v12.2s,v12.2s,v27.2s + umlal v22.2d,v10.2s,v3.2s + umlal v19.2d,v10.2s,v8.2s + umlal v23.2d,v10.2s,v5.2s + umlal v20.2d,v10.2s,v0.2s + umlal v21.2d,v10.2s,v1.2s + + add v13.2s,v13.2s,v28.2s + umlal v22.2d,v12.2s,v0.2s + umlal v19.2d,v12.2s,v4.2s + umlal v23.2d,v12.2s,v1.2s + umlal v20.2d,v12.2s,v6.2s + umlal v21.2d,v12.2s,v8.2s + + umlal v22.2d,v13.2s,v8.2s + umlal v19.2d,v13.2s,v2.2s + umlal v23.2d,v13.2s,v0.2s + umlal v20.2d,v13.2s,v4.2s + umlal v21.2d,v13.2s,v6.2s + +.Lshort_tail: + //////////////////////////////////////////////////////////////// + // horizontal add + + addp v22.2d,v22.2d,v22.2d + ldp d8,d9,[sp,#16] // meet ABI requirements + addp v19.2d,v19.2d,v19.2d + ldp d10,d11,[sp,#32] + addp v23.2d,v23.2d,v23.2d + ldp d12,d13,[sp,#48] + addp v20.2d,v20.2d,v20.2d + ldp d14,d15,[sp,#64] + addp v21.2d,v21.2d,v21.2d + ldr x30,[sp,#8] + + //////////////////////////////////////////////////////////////// + // lazy reduction, but without narrowing + + ushr v29.2d,v22.2d,#26 + and v22.16b,v22.16b,v31.16b + ushr v30.2d,v19.2d,#26 + and v19.16b,v19.16b,v31.16b + + add v23.2d,v23.2d,v29.2d // h3 -> h4 + add v20.2d,v20.2d,v30.2d // h0 -> h1 + + ushr v29.2d,v23.2d,#26 + and v23.16b,v23.16b,v31.16b + ushr v30.2d,v20.2d,#26 + and v20.16b,v20.16b,v31.16b + add v21.2d,v21.2d,v30.2d // h1 -> h2 + + add v19.2d,v19.2d,v29.2d + shl v29.2d,v29.2d,#2 + ushr v30.2d,v21.2d,#26 + and v21.16b,v21.16b,v31.16b + add v19.2d,v19.2d,v29.2d // h4 -> h0 + add v22.2d,v22.2d,v30.2d // h2 -> h3 + + ushr v29.2d,v19.2d,#26 + and v19.16b,v19.16b,v31.16b + ushr v30.2d,v22.2d,#26 + and v22.16b,v22.16b,v31.16b + add v20.2d,v20.2d,v29.2d // h0 -> h1 + add v23.2d,v23.2d,v30.2d // h3 -> h4 + + //////////////////////////////////////////////////////////////// + // write the result, can be partially reduced + + st4 {v19.s,v20.s,v21.s,v22.s}[0],[x0],#16 + mov x4,#1 + st1 {v23.s}[0],[x0] + str x4,[x0,#8] // set is_base2_26 + + ldr x29,[sp],#80 + .inst 0xd50323bf // autiasp + ret +.size poly1305_blocks_neon,.-poly1305_blocks_neon + +.align 5 +.Lzeros: +.long 0,0,0,0,0,0,0,0 +.asciz "Poly1305 for ARMv8, CRYPTOGAMS by @dot-asm" +.align 2 +#if !defined(__KERNEL__) && !defined(_WIN64) +.comm OPENSSL_armcap_P,4,4 +.hidden OPENSSL_armcap_P +#endif diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/crypto/sha256-core.S linux/arch/arm64/crypto/sha256-core.S --- linux-6.1.66/arch/arm64/crypto/sha256-core.S 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/crypto/sha256-core.S 2023-12-14 11:56:41.524754490 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 + +// This code is taken from the OpenSSL project but the author (Andy Polyakov) +// has relicensed it under the GPLv2. Therefore this program is free software; +// you can redistribute it and/or modify it under the terms of the GNU General +// Public License version 2 as published by the Free Software Foundation. +// +// The original headers, including the original license headers, are +// included below for completeness. + +// Copyright 2014-2016 The OpenSSL Project Authors. All Rights Reserved. +// +// Licensed under the OpenSSL license (the "License"). You may not use +// this file except in compliance with the License. You can obtain a copy +// in the file LICENSE in the source distribution or at +// https://www.openssl.org/source/license.html + +// ==================================================================== +// Written by Andy Polyakov <appro@openssl.org> for the OpenSSL +// project. The module is, however, dual licensed under OpenSSL and +// CRYPTOGAMS licenses depending on where you obtain it. For further +// details see http://www.openssl.org/~appro/cryptogams/. +// ==================================================================== +// +// SHA256/512 for ARMv8. +// +// Performance in cycles per processed byte and improvement coefficient +// over code generated with "default" compiler: +// +// SHA256-hw SHA256(*) SHA512 +// Apple A7 1.97 10.5 (+33%) 6.73 (-1%(**)) +// Cortex-A53 2.38 15.5 (+115%) 10.0 (+150%(***)) +// Cortex-A57 2.31 11.6 (+86%) 7.51 (+260%(***)) +// Denver 2.01 10.5 (+26%) 6.70 (+8%) +// X-Gene 20.0 (+100%) 12.8 (+300%(***)) +// Mongoose 2.36 13.0 (+50%) 8.36 (+33%) +// +// (*) Software SHA256 results are of lesser relevance, presented +// mostly for informational purposes. +// (**) The result is a trade-off: it's possible to improve it by +// 10% (or by 1 cycle per round), but at the cost of 20% loss +// on Cortex-A53 (or by 4 cycles per round). +// (***) Super-impressive coefficients over gcc-generated code are +// indication of some compiler "pathology", most notably code +// generated with -mgeneral-regs-only is significantly faster +// and the gap is only 40-90%. +// +// October 2016. +// +// Originally it was reckoned that it makes no sense to implement NEON +// version of SHA256 for 64-bit processors. This is because performance +// improvement on most wide-spread Cortex-A5x processors was observed +// to be marginal, same on Cortex-A53 and ~10% on A57. But then it was +// observed that 32-bit NEON SHA256 performs significantly better than +// 64-bit scalar version on *some* of the more recent processors. As +// result 64-bit NEON version of SHA256 was added to provide best +// all-round performance. For example it executes ~30% faster on X-Gene +// and Mongoose. [For reference, NEON version of SHA512 is bound to +// deliver much less improvement, likely *negative* on Cortex-A5x. +// Which is why NEON support is limited to SHA256.] + +#ifndef __KERNEL__ +# include "arm_arch.h" +#endif + +.text + +.extern OPENSSL_armcap_P +.globl sha256_block_data_order +.type sha256_block_data_order,%function +.align 6 +sha256_block_data_order: +#ifndef __KERNEL__ +# ifdef __ILP32__ + ldrsw x16,.LOPENSSL_armcap_P +# else + ldr x16,.LOPENSSL_armcap_P +# endif + adr x17,.LOPENSSL_armcap_P + add x16,x16,x17 + ldr w16,[x16] + tst w16,#ARMV8_SHA256 + b.ne .Lv8_entry + tst w16,#ARMV7_NEON + b.ne .Lneon_entry +#endif + stp x29,x30,[sp,#-128]! + add x29,sp,#0 + + stp x19,x20,[sp,#16] + stp x21,x22,[sp,#32] + stp x23,x24,[sp,#48] + stp x25,x26,[sp,#64] + stp x27,x28,[sp,#80] + sub sp,sp,#4*4 + + ldp w20,w21,[x0] // load context + ldp w22,w23,[x0,#2*4] + ldp w24,w25,[x0,#4*4] + add x2,x1,x2,lsl#6 // end of input + ldp w26,w27,[x0,#6*4] + adr x30,.LK256 + stp x0,x2,[x29,#96] + +.Loop: + ldp w3,w4,[x1],#2*4 + ldr w19,[x30],#4 // *K++ + eor w28,w21,w22 // magic seed + str x1,[x29,#112] +#ifndef __AARCH64EB__ + rev w3,w3 // 0 +#endif + ror w16,w24,#6 + add w27,w27,w19 // h+=K[i] + eor w6,w24,w24,ror#14 + and w17,w25,w24 + bic w19,w26,w24 + add w27,w27,w3 // h+=X[i] + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w20,w21 // a^b, b^c in next round + eor w16,w16,w6,ror#11 // Sigma1(e) + ror w6,w20,#2 + add w27,w27,w17 // h+=Ch(e,f,g) + eor w17,w20,w20,ror#9 + add w27,w27,w16 // h+=Sigma1(e) + and w28,w28,w19 // (b^c)&=(a^b) + add w23,w23,w27 // d+=h + eor w28,w28,w21 // Maj(a,b,c) + eor w17,w6,w17,ror#13 // Sigma0(a) + add w27,w27,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + //add w27,w27,w17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev w4,w4 // 1 +#endif + ldp w5,w6,[x1],#2*4 + add w27,w27,w17 // h+=Sigma0(a) + ror w16,w23,#6 + add w26,w26,w28 // h+=K[i] + eor w7,w23,w23,ror#14 + and w17,w24,w23 + bic w28,w25,w23 + add w26,w26,w4 // h+=X[i] + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w27,w20 // a^b, b^c in next round + eor w16,w16,w7,ror#11 // Sigma1(e) + ror w7,w27,#2 + add w26,w26,w17 // h+=Ch(e,f,g) + eor w17,w27,w27,ror#9 + add w26,w26,w16 // h+=Sigma1(e) + and w19,w19,w28 // (b^c)&=(a^b) + add w22,w22,w26 // d+=h + eor w19,w19,w20 // Maj(a,b,c) + eor w17,w7,w17,ror#13 // Sigma0(a) + add w26,w26,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + //add w26,w26,w17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev w5,w5 // 2 +#endif + add w26,w26,w17 // h+=Sigma0(a) + ror w16,w22,#6 + add w25,w25,w19 // h+=K[i] + eor w8,w22,w22,ror#14 + and w17,w23,w22 + bic w19,w24,w22 + add w25,w25,w5 // h+=X[i] + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w26,w27 // a^b, b^c in next round + eor w16,w16,w8,ror#11 // Sigma1(e) + ror w8,w26,#2 + add w25,w25,w17 // h+=Ch(e,f,g) + eor w17,w26,w26,ror#9 + add w25,w25,w16 // h+=Sigma1(e) + and w28,w28,w19 // (b^c)&=(a^b) + add w21,w21,w25 // d+=h + eor w28,w28,w27 // Maj(a,b,c) + eor w17,w8,w17,ror#13 // Sigma0(a) + add w25,w25,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + //add w25,w25,w17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev w6,w6 // 3 +#endif + ldp w7,w8,[x1],#2*4 + add w25,w25,w17 // h+=Sigma0(a) + ror w16,w21,#6 + add w24,w24,w28 // h+=K[i] + eor w9,w21,w21,ror#14 + and w17,w22,w21 + bic w28,w23,w21 + add w24,w24,w6 // h+=X[i] + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w25,w26 // a^b, b^c in next round + eor w16,w16,w9,ror#11 // Sigma1(e) + ror w9,w25,#2 + add w24,w24,w17 // h+=Ch(e,f,g) + eor w17,w25,w25,ror#9 + add w24,w24,w16 // h+=Sigma1(e) + and w19,w19,w28 // (b^c)&=(a^b) + add w20,w20,w24 // d+=h + eor w19,w19,w26 // Maj(a,b,c) + eor w17,w9,w17,ror#13 // Sigma0(a) + add w24,w24,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + //add w24,w24,w17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev w7,w7 // 4 +#endif + add w24,w24,w17 // h+=Sigma0(a) + ror w16,w20,#6 + add w23,w23,w19 // h+=K[i] + eor w10,w20,w20,ror#14 + and w17,w21,w20 + bic w19,w22,w20 + add w23,w23,w7 // h+=X[i] + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w24,w25 // a^b, b^c in next round + eor w16,w16,w10,ror#11 // Sigma1(e) + ror w10,w24,#2 + add w23,w23,w17 // h+=Ch(e,f,g) + eor w17,w24,w24,ror#9 + add w23,w23,w16 // h+=Sigma1(e) + and w28,w28,w19 // (b^c)&=(a^b) + add w27,w27,w23 // d+=h + eor w28,w28,w25 // Maj(a,b,c) + eor w17,w10,w17,ror#13 // Sigma0(a) + add w23,w23,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + //add w23,w23,w17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev w8,w8 // 5 +#endif + ldp w9,w10,[x1],#2*4 + add w23,w23,w17 // h+=Sigma0(a) + ror w16,w27,#6 + add w22,w22,w28 // h+=K[i] + eor w11,w27,w27,ror#14 + and w17,w20,w27 + bic w28,w21,w27 + add w22,w22,w8 // h+=X[i] + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w23,w24 // a^b, b^c in next round + eor w16,w16,w11,ror#11 // Sigma1(e) + ror w11,w23,#2 + add w22,w22,w17 // h+=Ch(e,f,g) + eor w17,w23,w23,ror#9 + add w22,w22,w16 // h+=Sigma1(e) + and w19,w19,w28 // (b^c)&=(a^b) + add w26,w26,w22 // d+=h + eor w19,w19,w24 // Maj(a,b,c) + eor w17,w11,w17,ror#13 // Sigma0(a) + add w22,w22,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + //add w22,w22,w17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev w9,w9 // 6 +#endif + add w22,w22,w17 // h+=Sigma0(a) + ror w16,w26,#6 + add w21,w21,w19 // h+=K[i] + eor w12,w26,w26,ror#14 + and w17,w27,w26 + bic w19,w20,w26 + add w21,w21,w9 // h+=X[i] + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w22,w23 // a^b, b^c in next round + eor w16,w16,w12,ror#11 // Sigma1(e) + ror w12,w22,#2 + add w21,w21,w17 // h+=Ch(e,f,g) + eor w17,w22,w22,ror#9 + add w21,w21,w16 // h+=Sigma1(e) + and w28,w28,w19 // (b^c)&=(a^b) + add w25,w25,w21 // d+=h + eor w28,w28,w23 // Maj(a,b,c) + eor w17,w12,w17,ror#13 // Sigma0(a) + add w21,w21,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + //add w21,w21,w17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev w10,w10 // 7 +#endif + ldp w11,w12,[x1],#2*4 + add w21,w21,w17 // h+=Sigma0(a) + ror w16,w25,#6 + add w20,w20,w28 // h+=K[i] + eor w13,w25,w25,ror#14 + and w17,w26,w25 + bic w28,w27,w25 + add w20,w20,w10 // h+=X[i] + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w21,w22 // a^b, b^c in next round + eor w16,w16,w13,ror#11 // Sigma1(e) + ror w13,w21,#2 + add w20,w20,w17 // h+=Ch(e,f,g) + eor w17,w21,w21,ror#9 + add w20,w20,w16 // h+=Sigma1(e) + and w19,w19,w28 // (b^c)&=(a^b) + add w24,w24,w20 // d+=h + eor w19,w19,w22 // Maj(a,b,c) + eor w17,w13,w17,ror#13 // Sigma0(a) + add w20,w20,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + //add w20,w20,w17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev w11,w11 // 8 +#endif + add w20,w20,w17 // h+=Sigma0(a) + ror w16,w24,#6 + add w27,w27,w19 // h+=K[i] + eor w14,w24,w24,ror#14 + and w17,w25,w24 + bic w19,w26,w24 + add w27,w27,w11 // h+=X[i] + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w20,w21 // a^b, b^c in next round + eor w16,w16,w14,ror#11 // Sigma1(e) + ror w14,w20,#2 + add w27,w27,w17 // h+=Ch(e,f,g) + eor w17,w20,w20,ror#9 + add w27,w27,w16 // h+=Sigma1(e) + and w28,w28,w19 // (b^c)&=(a^b) + add w23,w23,w27 // d+=h + eor w28,w28,w21 // Maj(a,b,c) + eor w17,w14,w17,ror#13 // Sigma0(a) + add w27,w27,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + //add w27,w27,w17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev w12,w12 // 9 +#endif + ldp w13,w14,[x1],#2*4 + add w27,w27,w17 // h+=Sigma0(a) + ror w16,w23,#6 + add w26,w26,w28 // h+=K[i] + eor w15,w23,w23,ror#14 + and w17,w24,w23 + bic w28,w25,w23 + add w26,w26,w12 // h+=X[i] + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w27,w20 // a^b, b^c in next round + eor w16,w16,w15,ror#11 // Sigma1(e) + ror w15,w27,#2 + add w26,w26,w17 // h+=Ch(e,f,g) + eor w17,w27,w27,ror#9 + add w26,w26,w16 // h+=Sigma1(e) + and w19,w19,w28 // (b^c)&=(a^b) + add w22,w22,w26 // d+=h + eor w19,w19,w20 // Maj(a,b,c) + eor w17,w15,w17,ror#13 // Sigma0(a) + add w26,w26,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + //add w26,w26,w17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev w13,w13 // 10 +#endif + add w26,w26,w17 // h+=Sigma0(a) + ror w16,w22,#6 + add w25,w25,w19 // h+=K[i] + eor w0,w22,w22,ror#14 + and w17,w23,w22 + bic w19,w24,w22 + add w25,w25,w13 // h+=X[i] + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w26,w27 // a^b, b^c in next round + eor w16,w16,w0,ror#11 // Sigma1(e) + ror w0,w26,#2 + add w25,w25,w17 // h+=Ch(e,f,g) + eor w17,w26,w26,ror#9 + add w25,w25,w16 // h+=Sigma1(e) + and w28,w28,w19 // (b^c)&=(a^b) + add w21,w21,w25 // d+=h + eor w28,w28,w27 // Maj(a,b,c) + eor w17,w0,w17,ror#13 // Sigma0(a) + add w25,w25,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + //add w25,w25,w17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev w14,w14 // 11 +#endif + ldp w15,w0,[x1],#2*4 + add w25,w25,w17 // h+=Sigma0(a) + str w6,[sp,#12] + ror w16,w21,#6 + add w24,w24,w28 // h+=K[i] + eor w6,w21,w21,ror#14 + and w17,w22,w21 + bic w28,w23,w21 + add w24,w24,w14 // h+=X[i] + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w25,w26 // a^b, b^c in next round + eor w16,w16,w6,ror#11 // Sigma1(e) + ror w6,w25,#2 + add w24,w24,w17 // h+=Ch(e,f,g) + eor w17,w25,w25,ror#9 + add w24,w24,w16 // h+=Sigma1(e) + and w19,w19,w28 // (b^c)&=(a^b) + add w20,w20,w24 // d+=h + eor w19,w19,w26 // Maj(a,b,c) + eor w17,w6,w17,ror#13 // Sigma0(a) + add w24,w24,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + //add w24,w24,w17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev w15,w15 // 12 +#endif + add w24,w24,w17 // h+=Sigma0(a) + str w7,[sp,#0] + ror w16,w20,#6 + add w23,w23,w19 // h+=K[i] + eor w7,w20,w20,ror#14 + and w17,w21,w20 + bic w19,w22,w20 + add w23,w23,w15 // h+=X[i] + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w24,w25 // a^b, b^c in next round + eor w16,w16,w7,ror#11 // Sigma1(e) + ror w7,w24,#2 + add w23,w23,w17 // h+=Ch(e,f,g) + eor w17,w24,w24,ror#9 + add w23,w23,w16 // h+=Sigma1(e) + and w28,w28,w19 // (b^c)&=(a^b) + add w27,w27,w23 // d+=h + eor w28,w28,w25 // Maj(a,b,c) + eor w17,w7,w17,ror#13 // Sigma0(a) + add w23,w23,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + //add w23,w23,w17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev w0,w0 // 13 +#endif + ldp w1,w2,[x1] + add w23,w23,w17 // h+=Sigma0(a) + str w8,[sp,#4] + ror w16,w27,#6 + add w22,w22,w28 // h+=K[i] + eor w8,w27,w27,ror#14 + and w17,w20,w27 + bic w28,w21,w27 + add w22,w22,w0 // h+=X[i] + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w23,w24 // a^b, b^c in next round + eor w16,w16,w8,ror#11 // Sigma1(e) + ror w8,w23,#2 + add w22,w22,w17 // h+=Ch(e,f,g) + eor w17,w23,w23,ror#9 + add w22,w22,w16 // h+=Sigma1(e) + and w19,w19,w28 // (b^c)&=(a^b) + add w26,w26,w22 // d+=h + eor w19,w19,w24 // Maj(a,b,c) + eor w17,w8,w17,ror#13 // Sigma0(a) + add w22,w22,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + //add w22,w22,w17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev w1,w1 // 14 +#endif + ldr w6,[sp,#12] + add w22,w22,w17 // h+=Sigma0(a) + str w9,[sp,#8] + ror w16,w26,#6 + add w21,w21,w19 // h+=K[i] + eor w9,w26,w26,ror#14 + and w17,w27,w26 + bic w19,w20,w26 + add w21,w21,w1 // h+=X[i] + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w22,w23 // a^b, b^c in next round + eor w16,w16,w9,ror#11 // Sigma1(e) + ror w9,w22,#2 + add w21,w21,w17 // h+=Ch(e,f,g) + eor w17,w22,w22,ror#9 + add w21,w21,w16 // h+=Sigma1(e) + and w28,w28,w19 // (b^c)&=(a^b) + add w25,w25,w21 // d+=h + eor w28,w28,w23 // Maj(a,b,c) + eor w17,w9,w17,ror#13 // Sigma0(a) + add w21,w21,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + //add w21,w21,w17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev w2,w2 // 15 +#endif + ldr w7,[sp,#0] + add w21,w21,w17 // h+=Sigma0(a) + str w10,[sp,#12] + ror w16,w25,#6 + add w20,w20,w28 // h+=K[i] + ror w9,w4,#7 + and w17,w26,w25 + ror w8,w1,#17 + bic w28,w27,w25 + ror w10,w21,#2 + add w20,w20,w2 // h+=X[i] + eor w16,w16,w25,ror#11 + eor w9,w9,w4,ror#18 + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w21,w22 // a^b, b^c in next round + eor w16,w16,w25,ror#25 // Sigma1(e) + eor w10,w10,w21,ror#13 + add w20,w20,w17 // h+=Ch(e,f,g) + and w19,w19,w28 // (b^c)&=(a^b) + eor w8,w8,w1,ror#19 + eor w9,w9,w4,lsr#3 // sigma0(X[i+1]) + add w20,w20,w16 // h+=Sigma1(e) + eor w19,w19,w22 // Maj(a,b,c) + eor w17,w10,w21,ror#22 // Sigma0(a) + eor w8,w8,w1,lsr#10 // sigma1(X[i+14]) + add w3,w3,w12 + add w24,w24,w20 // d+=h + add w20,w20,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + add w3,w3,w9 + add w20,w20,w17 // h+=Sigma0(a) + add w3,w3,w8 +.Loop_16_xx: + ldr w8,[sp,#4] + str w11,[sp,#0] + ror w16,w24,#6 + add w27,w27,w19 // h+=K[i] + ror w10,w5,#7 + and w17,w25,w24 + ror w9,w2,#17 + bic w19,w26,w24 + ror w11,w20,#2 + add w27,w27,w3 // h+=X[i] + eor w16,w16,w24,ror#11 + eor w10,w10,w5,ror#18 + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w20,w21 // a^b, b^c in next round + eor w16,w16,w24,ror#25 // Sigma1(e) + eor w11,w11,w20,ror#13 + add w27,w27,w17 // h+=Ch(e,f,g) + and w28,w28,w19 // (b^c)&=(a^b) + eor w9,w9,w2,ror#19 + eor w10,w10,w5,lsr#3 // sigma0(X[i+1]) + add w27,w27,w16 // h+=Sigma1(e) + eor w28,w28,w21 // Maj(a,b,c) + eor w17,w11,w20,ror#22 // Sigma0(a) + eor w9,w9,w2,lsr#10 // sigma1(X[i+14]) + add w4,w4,w13 + add w23,w23,w27 // d+=h + add w27,w27,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + add w4,w4,w10 + add w27,w27,w17 // h+=Sigma0(a) + add w4,w4,w9 + ldr w9,[sp,#8] + str w12,[sp,#4] + ror w16,w23,#6 + add w26,w26,w28 // h+=K[i] + ror w11,w6,#7 + and w17,w24,w23 + ror w10,w3,#17 + bic w28,w25,w23 + ror w12,w27,#2 + add w26,w26,w4 // h+=X[i] + eor w16,w16,w23,ror#11 + eor w11,w11,w6,ror#18 + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w27,w20 // a^b, b^c in next round + eor w16,w16,w23,ror#25 // Sigma1(e) + eor w12,w12,w27,ror#13 + add w26,w26,w17 // h+=Ch(e,f,g) + and w19,w19,w28 // (b^c)&=(a^b) + eor w10,w10,w3,ror#19 + eor w11,w11,w6,lsr#3 // sigma0(X[i+1]) + add w26,w26,w16 // h+=Sigma1(e) + eor w19,w19,w20 // Maj(a,b,c) + eor w17,w12,w27,ror#22 // Sigma0(a) + eor w10,w10,w3,lsr#10 // sigma1(X[i+14]) + add w5,w5,w14 + add w22,w22,w26 // d+=h + add w26,w26,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + add w5,w5,w11 + add w26,w26,w17 // h+=Sigma0(a) + add w5,w5,w10 + ldr w10,[sp,#12] + str w13,[sp,#8] + ror w16,w22,#6 + add w25,w25,w19 // h+=K[i] + ror w12,w7,#7 + and w17,w23,w22 + ror w11,w4,#17 + bic w19,w24,w22 + ror w13,w26,#2 + add w25,w25,w5 // h+=X[i] + eor w16,w16,w22,ror#11 + eor w12,w12,w7,ror#18 + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w26,w27 // a^b, b^c in next round + eor w16,w16,w22,ror#25 // Sigma1(e) + eor w13,w13,w26,ror#13 + add w25,w25,w17 // h+=Ch(e,f,g) + and w28,w28,w19 // (b^c)&=(a^b) + eor w11,w11,w4,ror#19 + eor w12,w12,w7,lsr#3 // sigma0(X[i+1]) + add w25,w25,w16 // h+=Sigma1(e) + eor w28,w28,w27 // Maj(a,b,c) + eor w17,w13,w26,ror#22 // Sigma0(a) + eor w11,w11,w4,lsr#10 // sigma1(X[i+14]) + add w6,w6,w15 + add w21,w21,w25 // d+=h + add w25,w25,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + add w6,w6,w12 + add w25,w25,w17 // h+=Sigma0(a) + add w6,w6,w11 + ldr w11,[sp,#0] + str w14,[sp,#12] + ror w16,w21,#6 + add w24,w24,w28 // h+=K[i] + ror w13,w8,#7 + and w17,w22,w21 + ror w12,w5,#17 + bic w28,w23,w21 + ror w14,w25,#2 + add w24,w24,w6 // h+=X[i] + eor w16,w16,w21,ror#11 + eor w13,w13,w8,ror#18 + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w25,w26 // a^b, b^c in next round + eor w16,w16,w21,ror#25 // Sigma1(e) + eor w14,w14,w25,ror#13 + add w24,w24,w17 // h+=Ch(e,f,g) + and w19,w19,w28 // (b^c)&=(a^b) + eor w12,w12,w5,ror#19 + eor w13,w13,w8,lsr#3 // sigma0(X[i+1]) + add w24,w24,w16 // h+=Sigma1(e) + eor w19,w19,w26 // Maj(a,b,c) + eor w17,w14,w25,ror#22 // Sigma0(a) + eor w12,w12,w5,lsr#10 // sigma1(X[i+14]) + add w7,w7,w0 + add w20,w20,w24 // d+=h + add w24,w24,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + add w7,w7,w13 + add w24,w24,w17 // h+=Sigma0(a) + add w7,w7,w12 + ldr w12,[sp,#4] + str w15,[sp,#0] + ror w16,w20,#6 + add w23,w23,w19 // h+=K[i] + ror w14,w9,#7 + and w17,w21,w20 + ror w13,w6,#17 + bic w19,w22,w20 + ror w15,w24,#2 + add w23,w23,w7 // h+=X[i] + eor w16,w16,w20,ror#11 + eor w14,w14,w9,ror#18 + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w24,w25 // a^b, b^c in next round + eor w16,w16,w20,ror#25 // Sigma1(e) + eor w15,w15,w24,ror#13 + add w23,w23,w17 // h+=Ch(e,f,g) + and w28,w28,w19 // (b^c)&=(a^b) + eor w13,w13,w6,ror#19 + eor w14,w14,w9,lsr#3 // sigma0(X[i+1]) + add w23,w23,w16 // h+=Sigma1(e) + eor w28,w28,w25 // Maj(a,b,c) + eor w17,w15,w24,ror#22 // Sigma0(a) + eor w13,w13,w6,lsr#10 // sigma1(X[i+14]) + add w8,w8,w1 + add w27,w27,w23 // d+=h + add w23,w23,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + add w8,w8,w14 + add w23,w23,w17 // h+=Sigma0(a) + add w8,w8,w13 + ldr w13,[sp,#8] + str w0,[sp,#4] + ror w16,w27,#6 + add w22,w22,w28 // h+=K[i] + ror w15,w10,#7 + and w17,w20,w27 + ror w14,w7,#17 + bic w28,w21,w27 + ror w0,w23,#2 + add w22,w22,w8 // h+=X[i] + eor w16,w16,w27,ror#11 + eor w15,w15,w10,ror#18 + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w23,w24 // a^b, b^c in next round + eor w16,w16,w27,ror#25 // Sigma1(e) + eor w0,w0,w23,ror#13 + add w22,w22,w17 // h+=Ch(e,f,g) + and w19,w19,w28 // (b^c)&=(a^b) + eor w14,w14,w7,ror#19 + eor w15,w15,w10,lsr#3 // sigma0(X[i+1]) + add w22,w22,w16 // h+=Sigma1(e) + eor w19,w19,w24 // Maj(a,b,c) + eor w17,w0,w23,ror#22 // Sigma0(a) + eor w14,w14,w7,lsr#10 // sigma1(X[i+14]) + add w9,w9,w2 + add w26,w26,w22 // d+=h + add w22,w22,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + add w9,w9,w15 + add w22,w22,w17 // h+=Sigma0(a) + add w9,w9,w14 + ldr w14,[sp,#12] + str w1,[sp,#8] + ror w16,w26,#6 + add w21,w21,w19 // h+=K[i] + ror w0,w11,#7 + and w17,w27,w26 + ror w15,w8,#17 + bic w19,w20,w26 + ror w1,w22,#2 + add w21,w21,w9 // h+=X[i] + eor w16,w16,w26,ror#11 + eor w0,w0,w11,ror#18 + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w22,w23 // a^b, b^c in next round + eor w16,w16,w26,ror#25 // Sigma1(e) + eor w1,w1,w22,ror#13 + add w21,w21,w17 // h+=Ch(e,f,g) + and w28,w28,w19 // (b^c)&=(a^b) + eor w15,w15,w8,ror#19 + eor w0,w0,w11,lsr#3 // sigma0(X[i+1]) + add w21,w21,w16 // h+=Sigma1(e) + eor w28,w28,w23 // Maj(a,b,c) + eor w17,w1,w22,ror#22 // Sigma0(a) + eor w15,w15,w8,lsr#10 // sigma1(X[i+14]) + add w10,w10,w3 + add w25,w25,w21 // d+=h + add w21,w21,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + add w10,w10,w0 + add w21,w21,w17 // h+=Sigma0(a) + add w10,w10,w15 + ldr w15,[sp,#0] + str w2,[sp,#12] + ror w16,w25,#6 + add w20,w20,w28 // h+=K[i] + ror w1,w12,#7 + and w17,w26,w25 + ror w0,w9,#17 + bic w28,w27,w25 + ror w2,w21,#2 + add w20,w20,w10 // h+=X[i] + eor w16,w16,w25,ror#11 + eor w1,w1,w12,ror#18 + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w21,w22 // a^b, b^c in next round + eor w16,w16,w25,ror#25 // Sigma1(e) + eor w2,w2,w21,ror#13 + add w20,w20,w17 // h+=Ch(e,f,g) + and w19,w19,w28 // (b^c)&=(a^b) + eor w0,w0,w9,ror#19 + eor w1,w1,w12,lsr#3 // sigma0(X[i+1]) + add w20,w20,w16 // h+=Sigma1(e) + eor w19,w19,w22 // Maj(a,b,c) + eor w17,w2,w21,ror#22 // Sigma0(a) + eor w0,w0,w9,lsr#10 // sigma1(X[i+14]) + add w11,w11,w4 + add w24,w24,w20 // d+=h + add w20,w20,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + add w11,w11,w1 + add w20,w20,w17 // h+=Sigma0(a) + add w11,w11,w0 + ldr w0,[sp,#4] + str w3,[sp,#0] + ror w16,w24,#6 + add w27,w27,w19 // h+=K[i] + ror w2,w13,#7 + and w17,w25,w24 + ror w1,w10,#17 + bic w19,w26,w24 + ror w3,w20,#2 + add w27,w27,w11 // h+=X[i] + eor w16,w16,w24,ror#11 + eor w2,w2,w13,ror#18 + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w20,w21 // a^b, b^c in next round + eor w16,w16,w24,ror#25 // Sigma1(e) + eor w3,w3,w20,ror#13 + add w27,w27,w17 // h+=Ch(e,f,g) + and w28,w28,w19 // (b^c)&=(a^b) + eor w1,w1,w10,ror#19 + eor w2,w2,w13,lsr#3 // sigma0(X[i+1]) + add w27,w27,w16 // h+=Sigma1(e) + eor w28,w28,w21 // Maj(a,b,c) + eor w17,w3,w20,ror#22 // Sigma0(a) + eor w1,w1,w10,lsr#10 // sigma1(X[i+14]) + add w12,w12,w5 + add w23,w23,w27 // d+=h + add w27,w27,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + add w12,w12,w2 + add w27,w27,w17 // h+=Sigma0(a) + add w12,w12,w1 + ldr w1,[sp,#8] + str w4,[sp,#4] + ror w16,w23,#6 + add w26,w26,w28 // h+=K[i] + ror w3,w14,#7 + and w17,w24,w23 + ror w2,w11,#17 + bic w28,w25,w23 + ror w4,w27,#2 + add w26,w26,w12 // h+=X[i] + eor w16,w16,w23,ror#11 + eor w3,w3,w14,ror#18 + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w27,w20 // a^b, b^c in next round + eor w16,w16,w23,ror#25 // Sigma1(e) + eor w4,w4,w27,ror#13 + add w26,w26,w17 // h+=Ch(e,f,g) + and w19,w19,w28 // (b^c)&=(a^b) + eor w2,w2,w11,ror#19 + eor w3,w3,w14,lsr#3 // sigma0(X[i+1]) + add w26,w26,w16 // h+=Sigma1(e) + eor w19,w19,w20 // Maj(a,b,c) + eor w17,w4,w27,ror#22 // Sigma0(a) + eor w2,w2,w11,lsr#10 // sigma1(X[i+14]) + add w13,w13,w6 + add w22,w22,w26 // d+=h + add w26,w26,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + add w13,w13,w3 + add w26,w26,w17 // h+=Sigma0(a) + add w13,w13,w2 + ldr w2,[sp,#12] + str w5,[sp,#8] + ror w16,w22,#6 + add w25,w25,w19 // h+=K[i] + ror w4,w15,#7 + and w17,w23,w22 + ror w3,w12,#17 + bic w19,w24,w22 + ror w5,w26,#2 + add w25,w25,w13 // h+=X[i] + eor w16,w16,w22,ror#11 + eor w4,w4,w15,ror#18 + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w26,w27 // a^b, b^c in next round + eor w16,w16,w22,ror#25 // Sigma1(e) + eor w5,w5,w26,ror#13 + add w25,w25,w17 // h+=Ch(e,f,g) + and w28,w28,w19 // (b^c)&=(a^b) + eor w3,w3,w12,ror#19 + eor w4,w4,w15,lsr#3 // sigma0(X[i+1]) + add w25,w25,w16 // h+=Sigma1(e) + eor w28,w28,w27 // Maj(a,b,c) + eor w17,w5,w26,ror#22 // Sigma0(a) + eor w3,w3,w12,lsr#10 // sigma1(X[i+14]) + add w14,w14,w7 + add w21,w21,w25 // d+=h + add w25,w25,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + add w14,w14,w4 + add w25,w25,w17 // h+=Sigma0(a) + add w14,w14,w3 + ldr w3,[sp,#0] + str w6,[sp,#12] + ror w16,w21,#6 + add w24,w24,w28 // h+=K[i] + ror w5,w0,#7 + and w17,w22,w21 + ror w4,w13,#17 + bic w28,w23,w21 + ror w6,w25,#2 + add w24,w24,w14 // h+=X[i] + eor w16,w16,w21,ror#11 + eor w5,w5,w0,ror#18 + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w25,w26 // a^b, b^c in next round + eor w16,w16,w21,ror#25 // Sigma1(e) + eor w6,w6,w25,ror#13 + add w24,w24,w17 // h+=Ch(e,f,g) + and w19,w19,w28 // (b^c)&=(a^b) + eor w4,w4,w13,ror#19 + eor w5,w5,w0,lsr#3 // sigma0(X[i+1]) + add w24,w24,w16 // h+=Sigma1(e) + eor w19,w19,w26 // Maj(a,b,c) + eor w17,w6,w25,ror#22 // Sigma0(a) + eor w4,w4,w13,lsr#10 // sigma1(X[i+14]) + add w15,w15,w8 + add w20,w20,w24 // d+=h + add w24,w24,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + add w15,w15,w5 + add w24,w24,w17 // h+=Sigma0(a) + add w15,w15,w4 + ldr w4,[sp,#4] + str w7,[sp,#0] + ror w16,w20,#6 + add w23,w23,w19 // h+=K[i] + ror w6,w1,#7 + and w17,w21,w20 + ror w5,w14,#17 + bic w19,w22,w20 + ror w7,w24,#2 + add w23,w23,w15 // h+=X[i] + eor w16,w16,w20,ror#11 + eor w6,w6,w1,ror#18 + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w24,w25 // a^b, b^c in next round + eor w16,w16,w20,ror#25 // Sigma1(e) + eor w7,w7,w24,ror#13 + add w23,w23,w17 // h+=Ch(e,f,g) + and w28,w28,w19 // (b^c)&=(a^b) + eor w5,w5,w14,ror#19 + eor w6,w6,w1,lsr#3 // sigma0(X[i+1]) + add w23,w23,w16 // h+=Sigma1(e) + eor w28,w28,w25 // Maj(a,b,c) + eor w17,w7,w24,ror#22 // Sigma0(a) + eor w5,w5,w14,lsr#10 // sigma1(X[i+14]) + add w0,w0,w9 + add w27,w27,w23 // d+=h + add w23,w23,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + add w0,w0,w6 + add w23,w23,w17 // h+=Sigma0(a) + add w0,w0,w5 + ldr w5,[sp,#8] + str w8,[sp,#4] + ror w16,w27,#6 + add w22,w22,w28 // h+=K[i] + ror w7,w2,#7 + and w17,w20,w27 + ror w6,w15,#17 + bic w28,w21,w27 + ror w8,w23,#2 + add w22,w22,w0 // h+=X[i] + eor w16,w16,w27,ror#11 + eor w7,w7,w2,ror#18 + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w23,w24 // a^b, b^c in next round + eor w16,w16,w27,ror#25 // Sigma1(e) + eor w8,w8,w23,ror#13 + add w22,w22,w17 // h+=Ch(e,f,g) + and w19,w19,w28 // (b^c)&=(a^b) + eor w6,w6,w15,ror#19 + eor w7,w7,w2,lsr#3 // sigma0(X[i+1]) + add w22,w22,w16 // h+=Sigma1(e) + eor w19,w19,w24 // Maj(a,b,c) + eor w17,w8,w23,ror#22 // Sigma0(a) + eor w6,w6,w15,lsr#10 // sigma1(X[i+14]) + add w1,w1,w10 + add w26,w26,w22 // d+=h + add w22,w22,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + add w1,w1,w7 + add w22,w22,w17 // h+=Sigma0(a) + add w1,w1,w6 + ldr w6,[sp,#12] + str w9,[sp,#8] + ror w16,w26,#6 + add w21,w21,w19 // h+=K[i] + ror w8,w3,#7 + and w17,w27,w26 + ror w7,w0,#17 + bic w19,w20,w26 + ror w9,w22,#2 + add w21,w21,w1 // h+=X[i] + eor w16,w16,w26,ror#11 + eor w8,w8,w3,ror#18 + orr w17,w17,w19 // Ch(e,f,g) + eor w19,w22,w23 // a^b, b^c in next round + eor w16,w16,w26,ror#25 // Sigma1(e) + eor w9,w9,w22,ror#13 + add w21,w21,w17 // h+=Ch(e,f,g) + and w28,w28,w19 // (b^c)&=(a^b) + eor w7,w7,w0,ror#19 + eor w8,w8,w3,lsr#3 // sigma0(X[i+1]) + add w21,w21,w16 // h+=Sigma1(e) + eor w28,w28,w23 // Maj(a,b,c) + eor w17,w9,w22,ror#22 // Sigma0(a) + eor w7,w7,w0,lsr#10 // sigma1(X[i+14]) + add w2,w2,w11 + add w25,w25,w21 // d+=h + add w21,w21,w28 // h+=Maj(a,b,c) + ldr w28,[x30],#4 // *K++, w19 in next round + add w2,w2,w8 + add w21,w21,w17 // h+=Sigma0(a) + add w2,w2,w7 + ldr w7,[sp,#0] + str w10,[sp,#12] + ror w16,w25,#6 + add w20,w20,w28 // h+=K[i] + ror w9,w4,#7 + and w17,w26,w25 + ror w8,w1,#17 + bic w28,w27,w25 + ror w10,w21,#2 + add w20,w20,w2 // h+=X[i] + eor w16,w16,w25,ror#11 + eor w9,w9,w4,ror#18 + orr w17,w17,w28 // Ch(e,f,g) + eor w28,w21,w22 // a^b, b^c in next round + eor w16,w16,w25,ror#25 // Sigma1(e) + eor w10,w10,w21,ror#13 + add w20,w20,w17 // h+=Ch(e,f,g) + and w19,w19,w28 // (b^c)&=(a^b) + eor w8,w8,w1,ror#19 + eor w9,w9,w4,lsr#3 // sigma0(X[i+1]) + add w20,w20,w16 // h+=Sigma1(e) + eor w19,w19,w22 // Maj(a,b,c) + eor w17,w10,w21,ror#22 // Sigma0(a) + eor w8,w8,w1,lsr#10 // sigma1(X[i+14]) + add w3,w3,w12 + add w24,w24,w20 // d+=h + add w20,w20,w19 // h+=Maj(a,b,c) + ldr w19,[x30],#4 // *K++, w28 in next round + add w3,w3,w9 + add w20,w20,w17 // h+=Sigma0(a) + add w3,w3,w8 + cbnz w19,.Loop_16_xx + + ldp x0,x2,[x29,#96] + ldr x1,[x29,#112] + sub x30,x30,#260 // rewind + + ldp w3,w4,[x0] + ldp w5,w6,[x0,#2*4] + add x1,x1,#14*4 // advance input pointer + ldp w7,w8,[x0,#4*4] + add w20,w20,w3 + ldp w9,w10,[x0,#6*4] + add w21,w21,w4 + add w22,w22,w5 + add w23,w23,w6 + stp w20,w21,[x0] + add w24,w24,w7 + add w25,w25,w8 + stp w22,w23,[x0,#2*4] + add w26,w26,w9 + add w27,w27,w10 + cmp x1,x2 + stp w24,w25,[x0,#4*4] + stp w26,w27,[x0,#6*4] + b.ne .Loop + + ldp x19,x20,[x29,#16] + add sp,sp,#4*4 + ldp x21,x22,[x29,#32] + ldp x23,x24,[x29,#48] + ldp x25,x26,[x29,#64] + ldp x27,x28,[x29,#80] + ldp x29,x30,[sp],#128 + ret +.size sha256_block_data_order,.-sha256_block_data_order + +.align 6 +.type .LK256,%object +.LK256: + .long 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5 + .long 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5 + .long 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3 + .long 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174 + .long 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc + .long 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da + .long 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7 + .long 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967 + .long 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13 + .long 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85 + .long 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3 + .long 0xd192e819,0xd6990624,0xf40e3585,0x106aa070 + .long 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5 + .long 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3 + .long 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208 + .long 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2 + .long 0 //terminator +.size .LK256,.-.LK256 +#ifndef __KERNEL__ +.align 3 +.LOPENSSL_armcap_P: +# ifdef __ILP32__ + .long OPENSSL_armcap_P-. +# else + .quad OPENSSL_armcap_P-. +# endif +#endif +.asciz "SHA256 block transform for ARMv8, CRYPTOGAMS by <appro@openssl.org>" +.align 2 +#ifndef __KERNEL__ +.type sha256_block_armv8,%function +.align 6 +sha256_block_armv8: +.Lv8_entry: + stp x29,x30,[sp,#-16]! + add x29,sp,#0 + + ld1 {v0.4s,v1.4s},[x0] + adr x3,.LK256 + +.Loop_hw: + ld1 {v4.16b-v7.16b},[x1],#64 + sub x2,x2,#1 + ld1 {v16.4s},[x3],#16 + rev32 v4.16b,v4.16b + rev32 v5.16b,v5.16b + rev32 v6.16b,v6.16b + rev32 v7.16b,v7.16b + orr v18.16b,v0.16b,v0.16b // offload + orr v19.16b,v1.16b,v1.16b + ld1 {v17.4s},[x3],#16 + add v16.4s,v16.4s,v4.4s + .inst 0x5e2828a4 //sha256su0 v4.16b,v5.16b + orr v2.16b,v0.16b,v0.16b + .inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s + .inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s + .inst 0x5e0760c4 //sha256su1 v4.16b,v6.16b,v7.16b + ld1 {v16.4s},[x3],#16 + add v17.4s,v17.4s,v5.4s + .inst 0x5e2828c5 //sha256su0 v5.16b,v6.16b + orr v2.16b,v0.16b,v0.16b + .inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s + .inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s + .inst 0x5e0460e5 //sha256su1 v5.16b,v7.16b,v4.16b + ld1 {v17.4s},[x3],#16 + add v16.4s,v16.4s,v6.4s + .inst 0x5e2828e6 //sha256su0 v6.16b,v7.16b + orr v2.16b,v0.16b,v0.16b + .inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s + .inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s + .inst 0x5e056086 //sha256su1 v6.16b,v4.16b,v5.16b + ld1 {v16.4s},[x3],#16 + add v17.4s,v17.4s,v7.4s + .inst 0x5e282887 //sha256su0 v7.16b,v4.16b + orr v2.16b,v0.16b,v0.16b + .inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s + .inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s + .inst 0x5e0660a7 //sha256su1 v7.16b,v5.16b,v6.16b + ld1 {v17.4s},[x3],#16 + add v16.4s,v16.4s,v4.4s + .inst 0x5e2828a4 //sha256su0 v4.16b,v5.16b + orr v2.16b,v0.16b,v0.16b + .inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s + .inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s + .inst 0x5e0760c4 //sha256su1 v4.16b,v6.16b,v7.16b + ld1 {v16.4s},[x3],#16 + add v17.4s,v17.4s,v5.4s + .inst 0x5e2828c5 //sha256su0 v5.16b,v6.16b + orr v2.16b,v0.16b,v0.16b + .inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s + .inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s + .inst 0x5e0460e5 //sha256su1 v5.16b,v7.16b,v4.16b + ld1 {v17.4s},[x3],#16 + add v16.4s,v16.4s,v6.4s + .inst 0x5e2828e6 //sha256su0 v6.16b,v7.16b + orr v2.16b,v0.16b,v0.16b + .inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s + .inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s + .inst 0x5e056086 //sha256su1 v6.16b,v4.16b,v5.16b + ld1 {v16.4s},[x3],#16 + add v17.4s,v17.4s,v7.4s + .inst 0x5e282887 //sha256su0 v7.16b,v4.16b + orr v2.16b,v0.16b,v0.16b + .inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s + .inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s + .inst 0x5e0660a7 //sha256su1 v7.16b,v5.16b,v6.16b + ld1 {v17.4s},[x3],#16 + add v16.4s,v16.4s,v4.4s + .inst 0x5e2828a4 //sha256su0 v4.16b,v5.16b + orr v2.16b,v0.16b,v0.16b + .inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s + .inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s + .inst 0x5e0760c4 //sha256su1 v4.16b,v6.16b,v7.16b + ld1 {v16.4s},[x3],#16 + add v17.4s,v17.4s,v5.4s + .inst 0x5e2828c5 //sha256su0 v5.16b,v6.16b + orr v2.16b,v0.16b,v0.16b + .inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s + .inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s + .inst 0x5e0460e5 //sha256su1 v5.16b,v7.16b,v4.16b + ld1 {v17.4s},[x3],#16 + add v16.4s,v16.4s,v6.4s + .inst 0x5e2828e6 //sha256su0 v6.16b,v7.16b + orr v2.16b,v0.16b,v0.16b + .inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s + .inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s + .inst 0x5e056086 //sha256su1 v6.16b,v4.16b,v5.16b + ld1 {v16.4s},[x3],#16 + add v17.4s,v17.4s,v7.4s + .inst 0x5e282887 //sha256su0 v7.16b,v4.16b + orr v2.16b,v0.16b,v0.16b + .inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s + .inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s + .inst 0x5e0660a7 //sha256su1 v7.16b,v5.16b,v6.16b + ld1 {v17.4s},[x3],#16 + add v16.4s,v16.4s,v4.4s + orr v2.16b,v0.16b,v0.16b + .inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s + .inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s + + ld1 {v16.4s},[x3],#16 + add v17.4s,v17.4s,v5.4s + orr v2.16b,v0.16b,v0.16b + .inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s + .inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s + + ld1 {v17.4s},[x3] + add v16.4s,v16.4s,v6.4s + sub x3,x3,#64*4-16 // rewind + orr v2.16b,v0.16b,v0.16b + .inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s + .inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s + + add v17.4s,v17.4s,v7.4s + orr v2.16b,v0.16b,v0.16b + .inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s + .inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s + + add v0.4s,v0.4s,v18.4s + add v1.4s,v1.4s,v19.4s + + cbnz x2,.Loop_hw + + st1 {v0.4s,v1.4s},[x0] + + ldr x29,[sp],#16 + ret +.size sha256_block_armv8,.-sha256_block_armv8 +#endif +#ifdef __KERNEL__ +.globl sha256_block_neon +#endif +.type sha256_block_neon,%function +.align 4 +sha256_block_neon: +.Lneon_entry: + stp x29, x30, [sp, #-16]! + mov x29, sp + sub sp,sp,#16*4 + + adr x16,.LK256 + add x2,x1,x2,lsl#6 // len to point at the end of inp + + ld1 {v0.16b},[x1], #16 + ld1 {v1.16b},[x1], #16 + ld1 {v2.16b},[x1], #16 + ld1 {v3.16b},[x1], #16 + ld1 {v4.4s},[x16], #16 + ld1 {v5.4s},[x16], #16 + ld1 {v6.4s},[x16], #16 + ld1 {v7.4s},[x16], #16 + rev32 v0.16b,v0.16b // yes, even on + rev32 v1.16b,v1.16b // big-endian + rev32 v2.16b,v2.16b + rev32 v3.16b,v3.16b + mov x17,sp + add v4.4s,v4.4s,v0.4s + add v5.4s,v5.4s,v1.4s + add v6.4s,v6.4s,v2.4s + st1 {v4.4s-v5.4s},[x17], #32 + add v7.4s,v7.4s,v3.4s + st1 {v6.4s-v7.4s},[x17] + sub x17,x17,#32 + + ldp w3,w4,[x0] + ldp w5,w6,[x0,#8] + ldp w7,w8,[x0,#16] + ldp w9,w10,[x0,#24] + ldr w12,[sp,#0] + mov w13,wzr + eor w14,w4,w5 + mov w15,wzr + b .L_00_48 + +.align 4 +.L_00_48: + ext v4.16b,v0.16b,v1.16b,#4 + add w10,w10,w12 + add w3,w3,w15 + and w12,w8,w7 + bic w15,w9,w7 + ext v7.16b,v2.16b,v3.16b,#4 + eor w11,w7,w7,ror#5 + add w3,w3,w13 + mov d19,v3.d[1] + orr w12,w12,w15 + eor w11,w11,w7,ror#19 + ushr v6.4s,v4.4s,#7 + eor w15,w3,w3,ror#11 + ushr v5.4s,v4.4s,#3 + add w10,w10,w12 + add v0.4s,v0.4s,v7.4s + ror w11,w11,#6 + sli v6.4s,v4.4s,#25 + eor w13,w3,w4 + eor w15,w15,w3,ror#20 + ushr v7.4s,v4.4s,#18 + add w10,w10,w11 + ldr w12,[sp,#4] + and w14,w14,w13 + eor v5.16b,v5.16b,v6.16b + ror w15,w15,#2 + add w6,w6,w10 + sli v7.4s,v4.4s,#14 + eor w14,w14,w4 + ushr v16.4s,v19.4s,#17 + add w9,w9,w12 + add w10,w10,w15 + and w12,w7,w6 + eor v5.16b,v5.16b,v7.16b + bic w15,w8,w6 + eor w11,w6,w6,ror#5 + sli v16.4s,v19.4s,#15 + add w10,w10,w14 + orr w12,w12,w15 + ushr v17.4s,v19.4s,#10 + eor w11,w11,w6,ror#19 + eor w15,w10,w10,ror#11 + ushr v7.4s,v19.4s,#19 + add w9,w9,w12 + ror w11,w11,#6 + add v0.4s,v0.4s,v5.4s + eor w14,w10,w3 + eor w15,w15,w10,ror#20 + sli v7.4s,v19.4s,#13 + add w9,w9,w11 + ldr w12,[sp,#8] + and w13,w13,w14 + eor v17.16b,v17.16b,v16.16b + ror w15,w15,#2 + add w5,w5,w9 + eor w13,w13,w3 + eor v17.16b,v17.16b,v7.16b + add w8,w8,w12 + add w9,w9,w15 + and w12,w6,w5 + add v0.4s,v0.4s,v17.4s + bic w15,w7,w5 + eor w11,w5,w5,ror#5 + add w9,w9,w13 + ushr v18.4s,v0.4s,#17 + orr w12,w12,w15 + ushr v19.4s,v0.4s,#10 + eor w11,w11,w5,ror#19 + eor w15,w9,w9,ror#11 + sli v18.4s,v0.4s,#15 + add w8,w8,w12 + ushr v17.4s,v0.4s,#19 + ror w11,w11,#6 + eor w13,w9,w10 + eor v19.16b,v19.16b,v18.16b + eor w15,w15,w9,ror#20 + add w8,w8,w11 + sli v17.4s,v0.4s,#13 + ldr w12,[sp,#12] + and w14,w14,w13 + ror w15,w15,#2 + ld1 {v4.4s},[x16], #16 + add w4,w4,w8 + eor v19.16b,v19.16b,v17.16b + eor w14,w14,w10 + eor v17.16b,v17.16b,v17.16b + add w7,w7,w12 + add w8,w8,w15 + and w12,w5,w4 + mov v17.d[1],v19.d[0] + bic w15,w6,w4 + eor w11,w4,w4,ror#5 + add w8,w8,w14 + add v0.4s,v0.4s,v17.4s + orr w12,w12,w15 + eor w11,w11,w4,ror#19 + eor w15,w8,w8,ror#11 + add v4.4s,v4.4s,v0.4s + add w7,w7,w12 + ror w11,w11,#6 + eor w14,w8,w9 + eor w15,w15,w8,ror#20 + add w7,w7,w11 + ldr w12,[sp,#16] + and w13,w13,w14 + ror w15,w15,#2 + add w3,w3,w7 + eor w13,w13,w9 + st1 {v4.4s},[x17], #16 + ext v4.16b,v1.16b,v2.16b,#4 + add w6,w6,w12 + add w7,w7,w15 + and w12,w4,w3 + bic w15,w5,w3 + ext v7.16b,v3.16b,v0.16b,#4 + eor w11,w3,w3,ror#5 + add w7,w7,w13 + mov d19,v0.d[1] + orr w12,w12,w15 + eor w11,w11,w3,ror#19 + ushr v6.4s,v4.4s,#7 + eor w15,w7,w7,ror#11 + ushr v5.4s,v4.4s,#3 + add w6,w6,w12 + add v1.4s,v1.4s,v7.4s + ror w11,w11,#6 + sli v6.4s,v4.4s,#25 + eor w13,w7,w8 + eor w15,w15,w7,ror#20 + ushr v7.4s,v4.4s,#18 + add w6,w6,w11 + ldr w12,[sp,#20] + and w14,w14,w13 + eor v5.16b,v5.16b,v6.16b + ror w15,w15,#2 + add w10,w10,w6 + sli v7.4s,v4.4s,#14 + eor w14,w14,w8 + ushr v16.4s,v19.4s,#17 + add w5,w5,w12 + add w6,w6,w15 + and w12,w3,w10 + eor v5.16b,v5.16b,v7.16b + bic w15,w4,w10 + eor w11,w10,w10,ror#5 + sli v16.4s,v19.4s,#15 + add w6,w6,w14 + orr w12,w12,w15 + ushr v17.4s,v19.4s,#10 + eor w11,w11,w10,ror#19 + eor w15,w6,w6,ror#11 + ushr v7.4s,v19.4s,#19 + add w5,w5,w12 + ror w11,w11,#6 + add v1.4s,v1.4s,v5.4s + eor w14,w6,w7 + eor w15,w15,w6,ror#20 + sli v7.4s,v19.4s,#13 + add w5,w5,w11 + ldr w12,[sp,#24] + and w13,w13,w14 + eor v17.16b,v17.16b,v16.16b + ror w15,w15,#2 + add w9,w9,w5 + eor w13,w13,w7 + eor v17.16b,v17.16b,v7.16b + add w4,w4,w12 + add w5,w5,w15 + and w12,w10,w9 + add v1.4s,v1.4s,v17.4s + bic w15,w3,w9 + eor w11,w9,w9,ror#5 + add w5,w5,w13 + ushr v18.4s,v1.4s,#17 + orr w12,w12,w15 + ushr v19.4s,v1.4s,#10 + eor w11,w11,w9,ror#19 + eor w15,w5,w5,ror#11 + sli v18.4s,v1.4s,#15 + add w4,w4,w12 + ushr v17.4s,v1.4s,#19 + ror w11,w11,#6 + eor w13,w5,w6 + eor v19.16b,v19.16b,v18.16b + eor w15,w15,w5,ror#20 + add w4,w4,w11 + sli v17.4s,v1.4s,#13 + ldr w12,[sp,#28] + and w14,w14,w13 + ror w15,w15,#2 + ld1 {v4.4s},[x16], #16 + add w8,w8,w4 + eor v19.16b,v19.16b,v17.16b + eor w14,w14,w6 + eor v17.16b,v17.16b,v17.16b + add w3,w3,w12 + add w4,w4,w15 + and w12,w9,w8 + mov v17.d[1],v19.d[0] + bic w15,w10,w8 + eor w11,w8,w8,ror#5 + add w4,w4,w14 + add v1.4s,v1.4s,v17.4s + orr w12,w12,w15 + eor w11,w11,w8,ror#19 + eor w15,w4,w4,ror#11 + add v4.4s,v4.4s,v1.4s + add w3,w3,w12 + ror w11,w11,#6 + eor w14,w4,w5 + eor w15,w15,w4,ror#20 + add w3,w3,w11 + ldr w12,[sp,#32] + and w13,w13,w14 + ror w15,w15,#2 + add w7,w7,w3 + eor w13,w13,w5 + st1 {v4.4s},[x17], #16 + ext v4.16b,v2.16b,v3.16b,#4 + add w10,w10,w12 + add w3,w3,w15 + and w12,w8,w7 + bic w15,w9,w7 + ext v7.16b,v0.16b,v1.16b,#4 + eor w11,w7,w7,ror#5 + add w3,w3,w13 + mov d19,v1.d[1] + orr w12,w12,w15 + eor w11,w11,w7,ror#19 + ushr v6.4s,v4.4s,#7 + eor w15,w3,w3,ror#11 + ushr v5.4s,v4.4s,#3 + add w10,w10,w12 + add v2.4s,v2.4s,v7.4s + ror w11,w11,#6 + sli v6.4s,v4.4s,#25 + eor w13,w3,w4 + eor w15,w15,w3,ror#20 + ushr v7.4s,v4.4s,#18 + add w10,w10,w11 + ldr w12,[sp,#36] + and w14,w14,w13 + eor v5.16b,v5.16b,v6.16b + ror w15,w15,#2 + add w6,w6,w10 + sli v7.4s,v4.4s,#14 + eor w14,w14,w4 + ushr v16.4s,v19.4s,#17 + add w9,w9,w12 + add w10,w10,w15 + and w12,w7,w6 + eor v5.16b,v5.16b,v7.16b + bic w15,w8,w6 + eor w11,w6,w6,ror#5 + sli v16.4s,v19.4s,#15 + add w10,w10,w14 + orr w12,w12,w15 + ushr v17.4s,v19.4s,#10 + eor w11,w11,w6,ror#19 + eor w15,w10,w10,ror#11 + ushr v7.4s,v19.4s,#19 + add w9,w9,w12 + ror w11,w11,#6 + add v2.4s,v2.4s,v5.4s + eor w14,w10,w3 + eor w15,w15,w10,ror#20 + sli v7.4s,v19.4s,#13 + add w9,w9,w11 + ldr w12,[sp,#40] + and w13,w13,w14 + eor v17.16b,v17.16b,v16.16b + ror w15,w15,#2 + add w5,w5,w9 + eor w13,w13,w3 + eor v17.16b,v17.16b,v7.16b + add w8,w8,w12 + add w9,w9,w15 + and w12,w6,w5 + add v2.4s,v2.4s,v17.4s + bic w15,w7,w5 + eor w11,w5,w5,ror#5 + add w9,w9,w13 + ushr v18.4s,v2.4s,#17 + orr w12,w12,w15 + ushr v19.4s,v2.4s,#10 + eor w11,w11,w5,ror#19 + eor w15,w9,w9,ror#11 + sli v18.4s,v2.4s,#15 + add w8,w8,w12 + ushr v17.4s,v2.4s,#19 + ror w11,w11,#6 + eor w13,w9,w10 + eor v19.16b,v19.16b,v18.16b + eor w15,w15,w9,ror#20 + add w8,w8,w11 + sli v17.4s,v2.4s,#13 + ldr w12,[sp,#44] + and w14,w14,w13 + ror w15,w15,#2 + ld1 {v4.4s},[x16], #16 + add w4,w4,w8 + eor v19.16b,v19.16b,v17.16b + eor w14,w14,w10 + eor v17.16b,v17.16b,v17.16b + add w7,w7,w12 + add w8,w8,w15 + and w12,w5,w4 + mov v17.d[1],v19.d[0] + bic w15,w6,w4 + eor w11,w4,w4,ror#5 + add w8,w8,w14 + add v2.4s,v2.4s,v17.4s + orr w12,w12,w15 + eor w11,w11,w4,ror#19 + eor w15,w8,w8,ror#11 + add v4.4s,v4.4s,v2.4s + add w7,w7,w12 + ror w11,w11,#6 + eor w14,w8,w9 + eor w15,w15,w8,ror#20 + add w7,w7,w11 + ldr w12,[sp,#48] + and w13,w13,w14 + ror w15,w15,#2 + add w3,w3,w7 + eor w13,w13,w9 + st1 {v4.4s},[x17], #16 + ext v4.16b,v3.16b,v0.16b,#4 + add w6,w6,w12 + add w7,w7,w15 + and w12,w4,w3 + bic w15,w5,w3 + ext v7.16b,v1.16b,v2.16b,#4 + eor w11,w3,w3,ror#5 + add w7,w7,w13 + mov d19,v2.d[1] + orr w12,w12,w15 + eor w11,w11,w3,ror#19 + ushr v6.4s,v4.4s,#7 + eor w15,w7,w7,ror#11 + ushr v5.4s,v4.4s,#3 + add w6,w6,w12 + add v3.4s,v3.4s,v7.4s + ror w11,w11,#6 + sli v6.4s,v4.4s,#25 + eor w13,w7,w8 + eor w15,w15,w7,ror#20 + ushr v7.4s,v4.4s,#18 + add w6,w6,w11 + ldr w12,[sp,#52] + and w14,w14,w13 + eor v5.16b,v5.16b,v6.16b + ror w15,w15,#2 + add w10,w10,w6 + sli v7.4s,v4.4s,#14 + eor w14,w14,w8 + ushr v16.4s,v19.4s,#17 + add w5,w5,w12 + add w6,w6,w15 + and w12,w3,w10 + eor v5.16b,v5.16b,v7.16b + bic w15,w4,w10 + eor w11,w10,w10,ror#5 + sli v16.4s,v19.4s,#15 + add w6,w6,w14 + orr w12,w12,w15 + ushr v17.4s,v19.4s,#10 + eor w11,w11,w10,ror#19 + eor w15,w6,w6,ror#11 + ushr v7.4s,v19.4s,#19 + add w5,w5,w12 + ror w11,w11,#6 + add v3.4s,v3.4s,v5.4s + eor w14,w6,w7 + eor w15,w15,w6,ror#20 + sli v7.4s,v19.4s,#13 + add w5,w5,w11 + ldr w12,[sp,#56] + and w13,w13,w14 + eor v17.16b,v17.16b,v16.16b + ror w15,w15,#2 + add w9,w9,w5 + eor w13,w13,w7 + eor v17.16b,v17.16b,v7.16b + add w4,w4,w12 + add w5,w5,w15 + and w12,w10,w9 + add v3.4s,v3.4s,v17.4s + bic w15,w3,w9 + eor w11,w9,w9,ror#5 + add w5,w5,w13 + ushr v18.4s,v3.4s,#17 + orr w12,w12,w15 + ushr v19.4s,v3.4s,#10 + eor w11,w11,w9,ror#19 + eor w15,w5,w5,ror#11 + sli v18.4s,v3.4s,#15 + add w4,w4,w12 + ushr v17.4s,v3.4s,#19 + ror w11,w11,#6 + eor w13,w5,w6 + eor v19.16b,v19.16b,v18.16b + eor w15,w15,w5,ror#20 + add w4,w4,w11 + sli v17.4s,v3.4s,#13 + ldr w12,[sp,#60] + and w14,w14,w13 + ror w15,w15,#2 + ld1 {v4.4s},[x16], #16 + add w8,w8,w4 + eor v19.16b,v19.16b,v17.16b + eor w14,w14,w6 + eor v17.16b,v17.16b,v17.16b + add w3,w3,w12 + add w4,w4,w15 + and w12,w9,w8 + mov v17.d[1],v19.d[0] + bic w15,w10,w8 + eor w11,w8,w8,ror#5 + add w4,w4,w14 + add v3.4s,v3.4s,v17.4s + orr w12,w12,w15 + eor w11,w11,w8,ror#19 + eor w15,w4,w4,ror#11 + add v4.4s,v4.4s,v3.4s + add w3,w3,w12 + ror w11,w11,#6 + eor w14,w4,w5 + eor w15,w15,w4,ror#20 + add w3,w3,w11 + ldr w12,[x16] + and w13,w13,w14 + ror w15,w15,#2 + add w7,w7,w3 + eor w13,w13,w5 + st1 {v4.4s},[x17], #16 + cmp w12,#0 // check for K256 terminator + ldr w12,[sp,#0] + sub x17,x17,#64 + bne .L_00_48 + + sub x16,x16,#256 // rewind x16 + cmp x1,x2 + mov x17, #64 + csel x17, x17, xzr, eq + sub x1,x1,x17 // avoid SEGV + mov x17,sp + add w10,w10,w12 + add w3,w3,w15 + and w12,w8,w7 + ld1 {v0.16b},[x1],#16 + bic w15,w9,w7 + eor w11,w7,w7,ror#5 + ld1 {v4.4s},[x16],#16 + add w3,w3,w13 + orr w12,w12,w15 + eor w11,w11,w7,ror#19 + eor w15,w3,w3,ror#11 + rev32 v0.16b,v0.16b + add w10,w10,w12 + ror w11,w11,#6 + eor w13,w3,w4 + eor w15,w15,w3,ror#20 + add v4.4s,v4.4s,v0.4s + add w10,w10,w11 + ldr w12,[sp,#4] + and w14,w14,w13 + ror w15,w15,#2 + add w6,w6,w10 + eor w14,w14,w4 + add w9,w9,w12 + add w10,w10,w15 + and w12,w7,w6 + bic w15,w8,w6 + eor w11,w6,w6,ror#5 + add w10,w10,w14 + orr w12,w12,w15 + eor w11,w11,w6,ror#19 + eor w15,w10,w10,ror#11 + add w9,w9,w12 + ror w11,w11,#6 + eor w14,w10,w3 + eor w15,w15,w10,ror#20 + add w9,w9,w11 + ldr w12,[sp,#8] + and w13,w13,w14 + ror w15,w15,#2 + add w5,w5,w9 + eor w13,w13,w3 + add w8,w8,w12 + add w9,w9,w15 + and w12,w6,w5 + bic w15,w7,w5 + eor w11,w5,w5,ror#5 + add w9,w9,w13 + orr w12,w12,w15 + eor w11,w11,w5,ror#19 + eor w15,w9,w9,ror#11 + add w8,w8,w12 + ror w11,w11,#6 + eor w13,w9,w10 + eor w15,w15,w9,ror#20 + add w8,w8,w11 + ldr w12,[sp,#12] + and w14,w14,w13 + ror w15,w15,#2 + add w4,w4,w8 + eor w14,w14,w10 + add w7,w7,w12 + add w8,w8,w15 + and w12,w5,w4 + bic w15,w6,w4 + eor w11,w4,w4,ror#5 + add w8,w8,w14 + orr w12,w12,w15 + eor w11,w11,w4,ror#19 + eor w15,w8,w8,ror#11 + add w7,w7,w12 + ror w11,w11,#6 + eor w14,w8,w9 + eor w15,w15,w8,ror#20 + add w7,w7,w11 + ldr w12,[sp,#16] + and w13,w13,w14 + ror w15,w15,#2 + add w3,w3,w7 + eor w13,w13,w9 + st1 {v4.4s},[x17], #16 + add w6,w6,w12 + add w7,w7,w15 + and w12,w4,w3 + ld1 {v1.16b},[x1],#16 + bic w15,w5,w3 + eor w11,w3,w3,ror#5 + ld1 {v4.4s},[x16],#16 + add w7,w7,w13 + orr w12,w12,w15 + eor w11,w11,w3,ror#19 + eor w15,w7,w7,ror#11 + rev32 v1.16b,v1.16b + add w6,w6,w12 + ror w11,w11,#6 + eor w13,w7,w8 + eor w15,w15,w7,ror#20 + add v4.4s,v4.4s,v1.4s + add w6,w6,w11 + ldr w12,[sp,#20] + and w14,w14,w13 + ror w15,w15,#2 + add w10,w10,w6 + eor w14,w14,w8 + add w5,w5,w12 + add w6,w6,w15 + and w12,w3,w10 + bic w15,w4,w10 + eor w11,w10,w10,ror#5 + add w6,w6,w14 + orr w12,w12,w15 + eor w11,w11,w10,ror#19 + eor w15,w6,w6,ror#11 + add w5,w5,w12 + ror w11,w11,#6 + eor w14,w6,w7 + eor w15,w15,w6,ror#20 + add w5,w5,w11 + ldr w12,[sp,#24] + and w13,w13,w14 + ror w15,w15,#2 + add w9,w9,w5 + eor w13,w13,w7 + add w4,w4,w12 + add w5,w5,w15 + and w12,w10,w9 + bic w15,w3,w9 + eor w11,w9,w9,ror#5 + add w5,w5,w13 + orr w12,w12,w15 + eor w11,w11,w9,ror#19 + eor w15,w5,w5,ror#11 + add w4,w4,w12 + ror w11,w11,#6 + eor w13,w5,w6 + eor w15,w15,w5,ror#20 + add w4,w4,w11 + ldr w12,[sp,#28] + and w14,w14,w13 + ror w15,w15,#2 + add w8,w8,w4 + eor w14,w14,w6 + add w3,w3,w12 + add w4,w4,w15 + and w12,w9,w8 + bic w15,w10,w8 + eor w11,w8,w8,ror#5 + add w4,w4,w14 + orr w12,w12,w15 + eor w11,w11,w8,ror#19 + eor w15,w4,w4,ror#11 + add w3,w3,w12 + ror w11,w11,#6 + eor w14,w4,w5 + eor w15,w15,w4,ror#20 + add w3,w3,w11 + ldr w12,[sp,#32] + and w13,w13,w14 + ror w15,w15,#2 + add w7,w7,w3 + eor w13,w13,w5 + st1 {v4.4s},[x17], #16 + add w10,w10,w12 + add w3,w3,w15 + and w12,w8,w7 + ld1 {v2.16b},[x1],#16 + bic w15,w9,w7 + eor w11,w7,w7,ror#5 + ld1 {v4.4s},[x16],#16 + add w3,w3,w13 + orr w12,w12,w15 + eor w11,w11,w7,ror#19 + eor w15,w3,w3,ror#11 + rev32 v2.16b,v2.16b + add w10,w10,w12 + ror w11,w11,#6 + eor w13,w3,w4 + eor w15,w15,w3,ror#20 + add v4.4s,v4.4s,v2.4s + add w10,w10,w11 + ldr w12,[sp,#36] + and w14,w14,w13 + ror w15,w15,#2 + add w6,w6,w10 + eor w14,w14,w4 + add w9,w9,w12 + add w10,w10,w15 + and w12,w7,w6 + bic w15,w8,w6 + eor w11,w6,w6,ror#5 + add w10,w10,w14 + orr w12,w12,w15 + eor w11,w11,w6,ror#19 + eor w15,w10,w10,ror#11 + add w9,w9,w12 + ror w11,w11,#6 + eor w14,w10,w3 + eor w15,w15,w10,ror#20 + add w9,w9,w11 + ldr w12,[sp,#40] + and w13,w13,w14 + ror w15,w15,#2 + add w5,w5,w9 + eor w13,w13,w3 + add w8,w8,w12 + add w9,w9,w15 + and w12,w6,w5 + bic w15,w7,w5 + eor w11,w5,w5,ror#5 + add w9,w9,w13 + orr w12,w12,w15 + eor w11,w11,w5,ror#19 + eor w15,w9,w9,ror#11 + add w8,w8,w12 + ror w11,w11,#6 + eor w13,w9,w10 + eor w15,w15,w9,ror#20 + add w8,w8,w11 + ldr w12,[sp,#44] + and w14,w14,w13 + ror w15,w15,#2 + add w4,w4,w8 + eor w14,w14,w10 + add w7,w7,w12 + add w8,w8,w15 + and w12,w5,w4 + bic w15,w6,w4 + eor w11,w4,w4,ror#5 + add w8,w8,w14 + orr w12,w12,w15 + eor w11,w11,w4,ror#19 + eor w15,w8,w8,ror#11 + add w7,w7,w12 + ror w11,w11,#6 + eor w14,w8,w9 + eor w15,w15,w8,ror#20 + add w7,w7,w11 + ldr w12,[sp,#48] + and w13,w13,w14 + ror w15,w15,#2 + add w3,w3,w7 + eor w13,w13,w9 + st1 {v4.4s},[x17], #16 + add w6,w6,w12 + add w7,w7,w15 + and w12,w4,w3 + ld1 {v3.16b},[x1],#16 + bic w15,w5,w3 + eor w11,w3,w3,ror#5 + ld1 {v4.4s},[x16],#16 + add w7,w7,w13 + orr w12,w12,w15 + eor w11,w11,w3,ror#19 + eor w15,w7,w7,ror#11 + rev32 v3.16b,v3.16b + add w6,w6,w12 + ror w11,w11,#6 + eor w13,w7,w8 + eor w15,w15,w7,ror#20 + add v4.4s,v4.4s,v3.4s + add w6,w6,w11 + ldr w12,[sp,#52] + and w14,w14,w13 + ror w15,w15,#2 + add w10,w10,w6 + eor w14,w14,w8 + add w5,w5,w12 + add w6,w6,w15 + and w12,w3,w10 + bic w15,w4,w10 + eor w11,w10,w10,ror#5 + add w6,w6,w14 + orr w12,w12,w15 + eor w11,w11,w10,ror#19 + eor w15,w6,w6,ror#11 + add w5,w5,w12 + ror w11,w11,#6 + eor w14,w6,w7 + eor w15,w15,w6,ror#20 + add w5,w5,w11 + ldr w12,[sp,#56] + and w13,w13,w14 + ror w15,w15,#2 + add w9,w9,w5 + eor w13,w13,w7 + add w4,w4,w12 + add w5,w5,w15 + and w12,w10,w9 + bic w15,w3,w9 + eor w11,w9,w9,ror#5 + add w5,w5,w13 + orr w12,w12,w15 + eor w11,w11,w9,ror#19 + eor w15,w5,w5,ror#11 + add w4,w4,w12 + ror w11,w11,#6 + eor w13,w5,w6 + eor w15,w15,w5,ror#20 + add w4,w4,w11 + ldr w12,[sp,#60] + and w14,w14,w13 + ror w15,w15,#2 + add w8,w8,w4 + eor w14,w14,w6 + add w3,w3,w12 + add w4,w4,w15 + and w12,w9,w8 + bic w15,w10,w8 + eor w11,w8,w8,ror#5 + add w4,w4,w14 + orr w12,w12,w15 + eor w11,w11,w8,ror#19 + eor w15,w4,w4,ror#11 + add w3,w3,w12 + ror w11,w11,#6 + eor w14,w4,w5 + eor w15,w15,w4,ror#20 + add w3,w3,w11 + and w13,w13,w14 + ror w15,w15,#2 + add w7,w7,w3 + eor w13,w13,w5 + st1 {v4.4s},[x17], #16 + add w3,w3,w15 // h+=Sigma0(a) from the past + ldp w11,w12,[x0,#0] + add w3,w3,w13 // h+=Maj(a,b,c) from the past + ldp w13,w14,[x0,#8] + add w3,w3,w11 // accumulate + add w4,w4,w12 + ldp w11,w12,[x0,#16] + add w5,w5,w13 + add w6,w6,w14 + ldp w13,w14,[x0,#24] + add w7,w7,w11 + add w8,w8,w12 + ldr w12,[sp,#0] + stp w3,w4,[x0,#0] + add w9,w9,w13 + mov w13,wzr + stp w5,w6,[x0,#8] + add w10,w10,w14 + stp w7,w8,[x0,#16] + eor w14,w4,w5 + stp w9,w10,[x0,#24] + mov w15,wzr + mov x17,sp + b.ne .L_00_48 + + ldr x29,[x29] + add sp,sp,#16*4+16 + ret +.size sha256_block_neon,.-sha256_block_neon +#ifndef __KERNEL__ +.comm OPENSSL_armcap_P,4,4 +#endif diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/crypto/sha512-core.S linux/arch/arm64/crypto/sha512-core.S --- linux-6.1.66/arch/arm64/crypto/sha512-core.S 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/crypto/sha512-core.S 2023-12-14 11:56:44.391760878 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 + +// This code is taken from the OpenSSL project but the author (Andy Polyakov) +// has relicensed it under the GPLv2. Therefore this program is free software; +// you can redistribute it and/or modify it under the terms of the GNU General +// Public License version 2 as published by the Free Software Foundation. +// +// The original headers, including the original license headers, are +// included below for completeness. + +// Copyright 2014-2016 The OpenSSL Project Authors. All Rights Reserved. +// +// Licensed under the OpenSSL license (the "License"). You may not use +// this file except in compliance with the License. You can obtain a copy +// in the file LICENSE in the source distribution or at +// https://www.openssl.org/source/license.html + +// ==================================================================== +// Written by Andy Polyakov <appro@openssl.org> for the OpenSSL +// project. The module is, however, dual licensed under OpenSSL and +// CRYPTOGAMS licenses depending on where you obtain it. For further +// details see http://www.openssl.org/~appro/cryptogams/. +// ==================================================================== +// +// SHA256/512 for ARMv8. +// +// Performance in cycles per processed byte and improvement coefficient +// over code generated with "default" compiler: +// +// SHA256-hw SHA256(*) SHA512 +// Apple A7 1.97 10.5 (+33%) 6.73 (-1%(**)) +// Cortex-A53 2.38 15.5 (+115%) 10.0 (+150%(***)) +// Cortex-A57 2.31 11.6 (+86%) 7.51 (+260%(***)) +// Denver 2.01 10.5 (+26%) 6.70 (+8%) +// X-Gene 20.0 (+100%) 12.8 (+300%(***)) +// Mongoose 2.36 13.0 (+50%) 8.36 (+33%) +// +// (*) Software SHA256 results are of lesser relevance, presented +// mostly for informational purposes. +// (**) The result is a trade-off: it's possible to improve it by +// 10% (or by 1 cycle per round), but at the cost of 20% loss +// on Cortex-A53 (or by 4 cycles per round). +// (***) Super-impressive coefficients over gcc-generated code are +// indication of some compiler "pathology", most notably code +// generated with -mgeneral-regs-only is significantly faster +// and the gap is only 40-90%. +// +// October 2016. +// +// Originally it was reckoned that it makes no sense to implement NEON +// version of SHA256 for 64-bit processors. This is because performance +// improvement on most wide-spread Cortex-A5x processors was observed +// to be marginal, same on Cortex-A53 and ~10% on A57. But then it was +// observed that 32-bit NEON SHA256 performs significantly better than +// 64-bit scalar version on *some* of the more recent processors. As +// result 64-bit NEON version of SHA256 was added to provide best +// all-round performance. For example it executes ~30% faster on X-Gene +// and Mongoose. [For reference, NEON version of SHA512 is bound to +// deliver much less improvement, likely *negative* on Cortex-A5x. +// Which is why NEON support is limited to SHA256.] + +#ifndef __KERNEL__ +# include "arm_arch.h" +#endif + +.text + +.extern OPENSSL_armcap_P +.globl sha512_block_data_order +.type sha512_block_data_order,%function +.align 6 +sha512_block_data_order: + stp x29,x30,[sp,#-128]! + add x29,sp,#0 + + stp x19,x20,[sp,#16] + stp x21,x22,[sp,#32] + stp x23,x24,[sp,#48] + stp x25,x26,[sp,#64] + stp x27,x28,[sp,#80] + sub sp,sp,#4*8 + + ldp x20,x21,[x0] // load context + ldp x22,x23,[x0,#2*8] + ldp x24,x25,[x0,#4*8] + add x2,x1,x2,lsl#7 // end of input + ldp x26,x27,[x0,#6*8] + adr x30,.LK512 + stp x0,x2,[x29,#96] + +.Loop: + ldp x3,x4,[x1],#2*8 + ldr x19,[x30],#8 // *K++ + eor x28,x21,x22 // magic seed + str x1,[x29,#112] +#ifndef __AARCH64EB__ + rev x3,x3 // 0 +#endif + ror x16,x24,#14 + add x27,x27,x19 // h+=K[i] + eor x6,x24,x24,ror#23 + and x17,x25,x24 + bic x19,x26,x24 + add x27,x27,x3 // h+=X[i] + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x20,x21 // a^b, b^c in next round + eor x16,x16,x6,ror#18 // Sigma1(e) + ror x6,x20,#28 + add x27,x27,x17 // h+=Ch(e,f,g) + eor x17,x20,x20,ror#5 + add x27,x27,x16 // h+=Sigma1(e) + and x28,x28,x19 // (b^c)&=(a^b) + add x23,x23,x27 // d+=h + eor x28,x28,x21 // Maj(a,b,c) + eor x17,x6,x17,ror#34 // Sigma0(a) + add x27,x27,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + //add x27,x27,x17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev x4,x4 // 1 +#endif + ldp x5,x6,[x1],#2*8 + add x27,x27,x17 // h+=Sigma0(a) + ror x16,x23,#14 + add x26,x26,x28 // h+=K[i] + eor x7,x23,x23,ror#23 + and x17,x24,x23 + bic x28,x25,x23 + add x26,x26,x4 // h+=X[i] + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x27,x20 // a^b, b^c in next round + eor x16,x16,x7,ror#18 // Sigma1(e) + ror x7,x27,#28 + add x26,x26,x17 // h+=Ch(e,f,g) + eor x17,x27,x27,ror#5 + add x26,x26,x16 // h+=Sigma1(e) + and x19,x19,x28 // (b^c)&=(a^b) + add x22,x22,x26 // d+=h + eor x19,x19,x20 // Maj(a,b,c) + eor x17,x7,x17,ror#34 // Sigma0(a) + add x26,x26,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + //add x26,x26,x17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev x5,x5 // 2 +#endif + add x26,x26,x17 // h+=Sigma0(a) + ror x16,x22,#14 + add x25,x25,x19 // h+=K[i] + eor x8,x22,x22,ror#23 + and x17,x23,x22 + bic x19,x24,x22 + add x25,x25,x5 // h+=X[i] + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x26,x27 // a^b, b^c in next round + eor x16,x16,x8,ror#18 // Sigma1(e) + ror x8,x26,#28 + add x25,x25,x17 // h+=Ch(e,f,g) + eor x17,x26,x26,ror#5 + add x25,x25,x16 // h+=Sigma1(e) + and x28,x28,x19 // (b^c)&=(a^b) + add x21,x21,x25 // d+=h + eor x28,x28,x27 // Maj(a,b,c) + eor x17,x8,x17,ror#34 // Sigma0(a) + add x25,x25,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + //add x25,x25,x17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev x6,x6 // 3 +#endif + ldp x7,x8,[x1],#2*8 + add x25,x25,x17 // h+=Sigma0(a) + ror x16,x21,#14 + add x24,x24,x28 // h+=K[i] + eor x9,x21,x21,ror#23 + and x17,x22,x21 + bic x28,x23,x21 + add x24,x24,x6 // h+=X[i] + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x25,x26 // a^b, b^c in next round + eor x16,x16,x9,ror#18 // Sigma1(e) + ror x9,x25,#28 + add x24,x24,x17 // h+=Ch(e,f,g) + eor x17,x25,x25,ror#5 + add x24,x24,x16 // h+=Sigma1(e) + and x19,x19,x28 // (b^c)&=(a^b) + add x20,x20,x24 // d+=h + eor x19,x19,x26 // Maj(a,b,c) + eor x17,x9,x17,ror#34 // Sigma0(a) + add x24,x24,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + //add x24,x24,x17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev x7,x7 // 4 +#endif + add x24,x24,x17 // h+=Sigma0(a) + ror x16,x20,#14 + add x23,x23,x19 // h+=K[i] + eor x10,x20,x20,ror#23 + and x17,x21,x20 + bic x19,x22,x20 + add x23,x23,x7 // h+=X[i] + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x24,x25 // a^b, b^c in next round + eor x16,x16,x10,ror#18 // Sigma1(e) + ror x10,x24,#28 + add x23,x23,x17 // h+=Ch(e,f,g) + eor x17,x24,x24,ror#5 + add x23,x23,x16 // h+=Sigma1(e) + and x28,x28,x19 // (b^c)&=(a^b) + add x27,x27,x23 // d+=h + eor x28,x28,x25 // Maj(a,b,c) + eor x17,x10,x17,ror#34 // Sigma0(a) + add x23,x23,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + //add x23,x23,x17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev x8,x8 // 5 +#endif + ldp x9,x10,[x1],#2*8 + add x23,x23,x17 // h+=Sigma0(a) + ror x16,x27,#14 + add x22,x22,x28 // h+=K[i] + eor x11,x27,x27,ror#23 + and x17,x20,x27 + bic x28,x21,x27 + add x22,x22,x8 // h+=X[i] + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x23,x24 // a^b, b^c in next round + eor x16,x16,x11,ror#18 // Sigma1(e) + ror x11,x23,#28 + add x22,x22,x17 // h+=Ch(e,f,g) + eor x17,x23,x23,ror#5 + add x22,x22,x16 // h+=Sigma1(e) + and x19,x19,x28 // (b^c)&=(a^b) + add x26,x26,x22 // d+=h + eor x19,x19,x24 // Maj(a,b,c) + eor x17,x11,x17,ror#34 // Sigma0(a) + add x22,x22,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + //add x22,x22,x17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev x9,x9 // 6 +#endif + add x22,x22,x17 // h+=Sigma0(a) + ror x16,x26,#14 + add x21,x21,x19 // h+=K[i] + eor x12,x26,x26,ror#23 + and x17,x27,x26 + bic x19,x20,x26 + add x21,x21,x9 // h+=X[i] + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x22,x23 // a^b, b^c in next round + eor x16,x16,x12,ror#18 // Sigma1(e) + ror x12,x22,#28 + add x21,x21,x17 // h+=Ch(e,f,g) + eor x17,x22,x22,ror#5 + add x21,x21,x16 // h+=Sigma1(e) + and x28,x28,x19 // (b^c)&=(a^b) + add x25,x25,x21 // d+=h + eor x28,x28,x23 // Maj(a,b,c) + eor x17,x12,x17,ror#34 // Sigma0(a) + add x21,x21,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + //add x21,x21,x17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev x10,x10 // 7 +#endif + ldp x11,x12,[x1],#2*8 + add x21,x21,x17 // h+=Sigma0(a) + ror x16,x25,#14 + add x20,x20,x28 // h+=K[i] + eor x13,x25,x25,ror#23 + and x17,x26,x25 + bic x28,x27,x25 + add x20,x20,x10 // h+=X[i] + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x21,x22 // a^b, b^c in next round + eor x16,x16,x13,ror#18 // Sigma1(e) + ror x13,x21,#28 + add x20,x20,x17 // h+=Ch(e,f,g) + eor x17,x21,x21,ror#5 + add x20,x20,x16 // h+=Sigma1(e) + and x19,x19,x28 // (b^c)&=(a^b) + add x24,x24,x20 // d+=h + eor x19,x19,x22 // Maj(a,b,c) + eor x17,x13,x17,ror#34 // Sigma0(a) + add x20,x20,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + //add x20,x20,x17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev x11,x11 // 8 +#endif + add x20,x20,x17 // h+=Sigma0(a) + ror x16,x24,#14 + add x27,x27,x19 // h+=K[i] + eor x14,x24,x24,ror#23 + and x17,x25,x24 + bic x19,x26,x24 + add x27,x27,x11 // h+=X[i] + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x20,x21 // a^b, b^c in next round + eor x16,x16,x14,ror#18 // Sigma1(e) + ror x14,x20,#28 + add x27,x27,x17 // h+=Ch(e,f,g) + eor x17,x20,x20,ror#5 + add x27,x27,x16 // h+=Sigma1(e) + and x28,x28,x19 // (b^c)&=(a^b) + add x23,x23,x27 // d+=h + eor x28,x28,x21 // Maj(a,b,c) + eor x17,x14,x17,ror#34 // Sigma0(a) + add x27,x27,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + //add x27,x27,x17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev x12,x12 // 9 +#endif + ldp x13,x14,[x1],#2*8 + add x27,x27,x17 // h+=Sigma0(a) + ror x16,x23,#14 + add x26,x26,x28 // h+=K[i] + eor x15,x23,x23,ror#23 + and x17,x24,x23 + bic x28,x25,x23 + add x26,x26,x12 // h+=X[i] + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x27,x20 // a^b, b^c in next round + eor x16,x16,x15,ror#18 // Sigma1(e) + ror x15,x27,#28 + add x26,x26,x17 // h+=Ch(e,f,g) + eor x17,x27,x27,ror#5 + add x26,x26,x16 // h+=Sigma1(e) + and x19,x19,x28 // (b^c)&=(a^b) + add x22,x22,x26 // d+=h + eor x19,x19,x20 // Maj(a,b,c) + eor x17,x15,x17,ror#34 // Sigma0(a) + add x26,x26,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + //add x26,x26,x17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev x13,x13 // 10 +#endif + add x26,x26,x17 // h+=Sigma0(a) + ror x16,x22,#14 + add x25,x25,x19 // h+=K[i] + eor x0,x22,x22,ror#23 + and x17,x23,x22 + bic x19,x24,x22 + add x25,x25,x13 // h+=X[i] + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x26,x27 // a^b, b^c in next round + eor x16,x16,x0,ror#18 // Sigma1(e) + ror x0,x26,#28 + add x25,x25,x17 // h+=Ch(e,f,g) + eor x17,x26,x26,ror#5 + add x25,x25,x16 // h+=Sigma1(e) + and x28,x28,x19 // (b^c)&=(a^b) + add x21,x21,x25 // d+=h + eor x28,x28,x27 // Maj(a,b,c) + eor x17,x0,x17,ror#34 // Sigma0(a) + add x25,x25,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + //add x25,x25,x17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev x14,x14 // 11 +#endif + ldp x15,x0,[x1],#2*8 + add x25,x25,x17 // h+=Sigma0(a) + str x6,[sp,#24] + ror x16,x21,#14 + add x24,x24,x28 // h+=K[i] + eor x6,x21,x21,ror#23 + and x17,x22,x21 + bic x28,x23,x21 + add x24,x24,x14 // h+=X[i] + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x25,x26 // a^b, b^c in next round + eor x16,x16,x6,ror#18 // Sigma1(e) + ror x6,x25,#28 + add x24,x24,x17 // h+=Ch(e,f,g) + eor x17,x25,x25,ror#5 + add x24,x24,x16 // h+=Sigma1(e) + and x19,x19,x28 // (b^c)&=(a^b) + add x20,x20,x24 // d+=h + eor x19,x19,x26 // Maj(a,b,c) + eor x17,x6,x17,ror#34 // Sigma0(a) + add x24,x24,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + //add x24,x24,x17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev x15,x15 // 12 +#endif + add x24,x24,x17 // h+=Sigma0(a) + str x7,[sp,#0] + ror x16,x20,#14 + add x23,x23,x19 // h+=K[i] + eor x7,x20,x20,ror#23 + and x17,x21,x20 + bic x19,x22,x20 + add x23,x23,x15 // h+=X[i] + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x24,x25 // a^b, b^c in next round + eor x16,x16,x7,ror#18 // Sigma1(e) + ror x7,x24,#28 + add x23,x23,x17 // h+=Ch(e,f,g) + eor x17,x24,x24,ror#5 + add x23,x23,x16 // h+=Sigma1(e) + and x28,x28,x19 // (b^c)&=(a^b) + add x27,x27,x23 // d+=h + eor x28,x28,x25 // Maj(a,b,c) + eor x17,x7,x17,ror#34 // Sigma0(a) + add x23,x23,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + //add x23,x23,x17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev x0,x0 // 13 +#endif + ldp x1,x2,[x1] + add x23,x23,x17 // h+=Sigma0(a) + str x8,[sp,#8] + ror x16,x27,#14 + add x22,x22,x28 // h+=K[i] + eor x8,x27,x27,ror#23 + and x17,x20,x27 + bic x28,x21,x27 + add x22,x22,x0 // h+=X[i] + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x23,x24 // a^b, b^c in next round + eor x16,x16,x8,ror#18 // Sigma1(e) + ror x8,x23,#28 + add x22,x22,x17 // h+=Ch(e,f,g) + eor x17,x23,x23,ror#5 + add x22,x22,x16 // h+=Sigma1(e) + and x19,x19,x28 // (b^c)&=(a^b) + add x26,x26,x22 // d+=h + eor x19,x19,x24 // Maj(a,b,c) + eor x17,x8,x17,ror#34 // Sigma0(a) + add x22,x22,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + //add x22,x22,x17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev x1,x1 // 14 +#endif + ldr x6,[sp,#24] + add x22,x22,x17 // h+=Sigma0(a) + str x9,[sp,#16] + ror x16,x26,#14 + add x21,x21,x19 // h+=K[i] + eor x9,x26,x26,ror#23 + and x17,x27,x26 + bic x19,x20,x26 + add x21,x21,x1 // h+=X[i] + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x22,x23 // a^b, b^c in next round + eor x16,x16,x9,ror#18 // Sigma1(e) + ror x9,x22,#28 + add x21,x21,x17 // h+=Ch(e,f,g) + eor x17,x22,x22,ror#5 + add x21,x21,x16 // h+=Sigma1(e) + and x28,x28,x19 // (b^c)&=(a^b) + add x25,x25,x21 // d+=h + eor x28,x28,x23 // Maj(a,b,c) + eor x17,x9,x17,ror#34 // Sigma0(a) + add x21,x21,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + //add x21,x21,x17 // h+=Sigma0(a) +#ifndef __AARCH64EB__ + rev x2,x2 // 15 +#endif + ldr x7,[sp,#0] + add x21,x21,x17 // h+=Sigma0(a) + str x10,[sp,#24] + ror x16,x25,#14 + add x20,x20,x28 // h+=K[i] + ror x9,x4,#1 + and x17,x26,x25 + ror x8,x1,#19 + bic x28,x27,x25 + ror x10,x21,#28 + add x20,x20,x2 // h+=X[i] + eor x16,x16,x25,ror#18 + eor x9,x9,x4,ror#8 + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x21,x22 // a^b, b^c in next round + eor x16,x16,x25,ror#41 // Sigma1(e) + eor x10,x10,x21,ror#34 + add x20,x20,x17 // h+=Ch(e,f,g) + and x19,x19,x28 // (b^c)&=(a^b) + eor x8,x8,x1,ror#61 + eor x9,x9,x4,lsr#7 // sigma0(X[i+1]) + add x20,x20,x16 // h+=Sigma1(e) + eor x19,x19,x22 // Maj(a,b,c) + eor x17,x10,x21,ror#39 // Sigma0(a) + eor x8,x8,x1,lsr#6 // sigma1(X[i+14]) + add x3,x3,x12 + add x24,x24,x20 // d+=h + add x20,x20,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + add x3,x3,x9 + add x20,x20,x17 // h+=Sigma0(a) + add x3,x3,x8 +.Loop_16_xx: + ldr x8,[sp,#8] + str x11,[sp,#0] + ror x16,x24,#14 + add x27,x27,x19 // h+=K[i] + ror x10,x5,#1 + and x17,x25,x24 + ror x9,x2,#19 + bic x19,x26,x24 + ror x11,x20,#28 + add x27,x27,x3 // h+=X[i] + eor x16,x16,x24,ror#18 + eor x10,x10,x5,ror#8 + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x20,x21 // a^b, b^c in next round + eor x16,x16,x24,ror#41 // Sigma1(e) + eor x11,x11,x20,ror#34 + add x27,x27,x17 // h+=Ch(e,f,g) + and x28,x28,x19 // (b^c)&=(a^b) + eor x9,x9,x2,ror#61 + eor x10,x10,x5,lsr#7 // sigma0(X[i+1]) + add x27,x27,x16 // h+=Sigma1(e) + eor x28,x28,x21 // Maj(a,b,c) + eor x17,x11,x20,ror#39 // Sigma0(a) + eor x9,x9,x2,lsr#6 // sigma1(X[i+14]) + add x4,x4,x13 + add x23,x23,x27 // d+=h + add x27,x27,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + add x4,x4,x10 + add x27,x27,x17 // h+=Sigma0(a) + add x4,x4,x9 + ldr x9,[sp,#16] + str x12,[sp,#8] + ror x16,x23,#14 + add x26,x26,x28 // h+=K[i] + ror x11,x6,#1 + and x17,x24,x23 + ror x10,x3,#19 + bic x28,x25,x23 + ror x12,x27,#28 + add x26,x26,x4 // h+=X[i] + eor x16,x16,x23,ror#18 + eor x11,x11,x6,ror#8 + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x27,x20 // a^b, b^c in next round + eor x16,x16,x23,ror#41 // Sigma1(e) + eor x12,x12,x27,ror#34 + add x26,x26,x17 // h+=Ch(e,f,g) + and x19,x19,x28 // (b^c)&=(a^b) + eor x10,x10,x3,ror#61 + eor x11,x11,x6,lsr#7 // sigma0(X[i+1]) + add x26,x26,x16 // h+=Sigma1(e) + eor x19,x19,x20 // Maj(a,b,c) + eor x17,x12,x27,ror#39 // Sigma0(a) + eor x10,x10,x3,lsr#6 // sigma1(X[i+14]) + add x5,x5,x14 + add x22,x22,x26 // d+=h + add x26,x26,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + add x5,x5,x11 + add x26,x26,x17 // h+=Sigma0(a) + add x5,x5,x10 + ldr x10,[sp,#24] + str x13,[sp,#16] + ror x16,x22,#14 + add x25,x25,x19 // h+=K[i] + ror x12,x7,#1 + and x17,x23,x22 + ror x11,x4,#19 + bic x19,x24,x22 + ror x13,x26,#28 + add x25,x25,x5 // h+=X[i] + eor x16,x16,x22,ror#18 + eor x12,x12,x7,ror#8 + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x26,x27 // a^b, b^c in next round + eor x16,x16,x22,ror#41 // Sigma1(e) + eor x13,x13,x26,ror#34 + add x25,x25,x17 // h+=Ch(e,f,g) + and x28,x28,x19 // (b^c)&=(a^b) + eor x11,x11,x4,ror#61 + eor x12,x12,x7,lsr#7 // sigma0(X[i+1]) + add x25,x25,x16 // h+=Sigma1(e) + eor x28,x28,x27 // Maj(a,b,c) + eor x17,x13,x26,ror#39 // Sigma0(a) + eor x11,x11,x4,lsr#6 // sigma1(X[i+14]) + add x6,x6,x15 + add x21,x21,x25 // d+=h + add x25,x25,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + add x6,x6,x12 + add x25,x25,x17 // h+=Sigma0(a) + add x6,x6,x11 + ldr x11,[sp,#0] + str x14,[sp,#24] + ror x16,x21,#14 + add x24,x24,x28 // h+=K[i] + ror x13,x8,#1 + and x17,x22,x21 + ror x12,x5,#19 + bic x28,x23,x21 + ror x14,x25,#28 + add x24,x24,x6 // h+=X[i] + eor x16,x16,x21,ror#18 + eor x13,x13,x8,ror#8 + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x25,x26 // a^b, b^c in next round + eor x16,x16,x21,ror#41 // Sigma1(e) + eor x14,x14,x25,ror#34 + add x24,x24,x17 // h+=Ch(e,f,g) + and x19,x19,x28 // (b^c)&=(a^b) + eor x12,x12,x5,ror#61 + eor x13,x13,x8,lsr#7 // sigma0(X[i+1]) + add x24,x24,x16 // h+=Sigma1(e) + eor x19,x19,x26 // Maj(a,b,c) + eor x17,x14,x25,ror#39 // Sigma0(a) + eor x12,x12,x5,lsr#6 // sigma1(X[i+14]) + add x7,x7,x0 + add x20,x20,x24 // d+=h + add x24,x24,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + add x7,x7,x13 + add x24,x24,x17 // h+=Sigma0(a) + add x7,x7,x12 + ldr x12,[sp,#8] + str x15,[sp,#0] + ror x16,x20,#14 + add x23,x23,x19 // h+=K[i] + ror x14,x9,#1 + and x17,x21,x20 + ror x13,x6,#19 + bic x19,x22,x20 + ror x15,x24,#28 + add x23,x23,x7 // h+=X[i] + eor x16,x16,x20,ror#18 + eor x14,x14,x9,ror#8 + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x24,x25 // a^b, b^c in next round + eor x16,x16,x20,ror#41 // Sigma1(e) + eor x15,x15,x24,ror#34 + add x23,x23,x17 // h+=Ch(e,f,g) + and x28,x28,x19 // (b^c)&=(a^b) + eor x13,x13,x6,ror#61 + eor x14,x14,x9,lsr#7 // sigma0(X[i+1]) + add x23,x23,x16 // h+=Sigma1(e) + eor x28,x28,x25 // Maj(a,b,c) + eor x17,x15,x24,ror#39 // Sigma0(a) + eor x13,x13,x6,lsr#6 // sigma1(X[i+14]) + add x8,x8,x1 + add x27,x27,x23 // d+=h + add x23,x23,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + add x8,x8,x14 + add x23,x23,x17 // h+=Sigma0(a) + add x8,x8,x13 + ldr x13,[sp,#16] + str x0,[sp,#8] + ror x16,x27,#14 + add x22,x22,x28 // h+=K[i] + ror x15,x10,#1 + and x17,x20,x27 + ror x14,x7,#19 + bic x28,x21,x27 + ror x0,x23,#28 + add x22,x22,x8 // h+=X[i] + eor x16,x16,x27,ror#18 + eor x15,x15,x10,ror#8 + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x23,x24 // a^b, b^c in next round + eor x16,x16,x27,ror#41 // Sigma1(e) + eor x0,x0,x23,ror#34 + add x22,x22,x17 // h+=Ch(e,f,g) + and x19,x19,x28 // (b^c)&=(a^b) + eor x14,x14,x7,ror#61 + eor x15,x15,x10,lsr#7 // sigma0(X[i+1]) + add x22,x22,x16 // h+=Sigma1(e) + eor x19,x19,x24 // Maj(a,b,c) + eor x17,x0,x23,ror#39 // Sigma0(a) + eor x14,x14,x7,lsr#6 // sigma1(X[i+14]) + add x9,x9,x2 + add x26,x26,x22 // d+=h + add x22,x22,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + add x9,x9,x15 + add x22,x22,x17 // h+=Sigma0(a) + add x9,x9,x14 + ldr x14,[sp,#24] + str x1,[sp,#16] + ror x16,x26,#14 + add x21,x21,x19 // h+=K[i] + ror x0,x11,#1 + and x17,x27,x26 + ror x15,x8,#19 + bic x19,x20,x26 + ror x1,x22,#28 + add x21,x21,x9 // h+=X[i] + eor x16,x16,x26,ror#18 + eor x0,x0,x11,ror#8 + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x22,x23 // a^b, b^c in next round + eor x16,x16,x26,ror#41 // Sigma1(e) + eor x1,x1,x22,ror#34 + add x21,x21,x17 // h+=Ch(e,f,g) + and x28,x28,x19 // (b^c)&=(a^b) + eor x15,x15,x8,ror#61 + eor x0,x0,x11,lsr#7 // sigma0(X[i+1]) + add x21,x21,x16 // h+=Sigma1(e) + eor x28,x28,x23 // Maj(a,b,c) + eor x17,x1,x22,ror#39 // Sigma0(a) + eor x15,x15,x8,lsr#6 // sigma1(X[i+14]) + add x10,x10,x3 + add x25,x25,x21 // d+=h + add x21,x21,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + add x10,x10,x0 + add x21,x21,x17 // h+=Sigma0(a) + add x10,x10,x15 + ldr x15,[sp,#0] + str x2,[sp,#24] + ror x16,x25,#14 + add x20,x20,x28 // h+=K[i] + ror x1,x12,#1 + and x17,x26,x25 + ror x0,x9,#19 + bic x28,x27,x25 + ror x2,x21,#28 + add x20,x20,x10 // h+=X[i] + eor x16,x16,x25,ror#18 + eor x1,x1,x12,ror#8 + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x21,x22 // a^b, b^c in next round + eor x16,x16,x25,ror#41 // Sigma1(e) + eor x2,x2,x21,ror#34 + add x20,x20,x17 // h+=Ch(e,f,g) + and x19,x19,x28 // (b^c)&=(a^b) + eor x0,x0,x9,ror#61 + eor x1,x1,x12,lsr#7 // sigma0(X[i+1]) + add x20,x20,x16 // h+=Sigma1(e) + eor x19,x19,x22 // Maj(a,b,c) + eor x17,x2,x21,ror#39 // Sigma0(a) + eor x0,x0,x9,lsr#6 // sigma1(X[i+14]) + add x11,x11,x4 + add x24,x24,x20 // d+=h + add x20,x20,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + add x11,x11,x1 + add x20,x20,x17 // h+=Sigma0(a) + add x11,x11,x0 + ldr x0,[sp,#8] + str x3,[sp,#0] + ror x16,x24,#14 + add x27,x27,x19 // h+=K[i] + ror x2,x13,#1 + and x17,x25,x24 + ror x1,x10,#19 + bic x19,x26,x24 + ror x3,x20,#28 + add x27,x27,x11 // h+=X[i] + eor x16,x16,x24,ror#18 + eor x2,x2,x13,ror#8 + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x20,x21 // a^b, b^c in next round + eor x16,x16,x24,ror#41 // Sigma1(e) + eor x3,x3,x20,ror#34 + add x27,x27,x17 // h+=Ch(e,f,g) + and x28,x28,x19 // (b^c)&=(a^b) + eor x1,x1,x10,ror#61 + eor x2,x2,x13,lsr#7 // sigma0(X[i+1]) + add x27,x27,x16 // h+=Sigma1(e) + eor x28,x28,x21 // Maj(a,b,c) + eor x17,x3,x20,ror#39 // Sigma0(a) + eor x1,x1,x10,lsr#6 // sigma1(X[i+14]) + add x12,x12,x5 + add x23,x23,x27 // d+=h + add x27,x27,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + add x12,x12,x2 + add x27,x27,x17 // h+=Sigma0(a) + add x12,x12,x1 + ldr x1,[sp,#16] + str x4,[sp,#8] + ror x16,x23,#14 + add x26,x26,x28 // h+=K[i] + ror x3,x14,#1 + and x17,x24,x23 + ror x2,x11,#19 + bic x28,x25,x23 + ror x4,x27,#28 + add x26,x26,x12 // h+=X[i] + eor x16,x16,x23,ror#18 + eor x3,x3,x14,ror#8 + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x27,x20 // a^b, b^c in next round + eor x16,x16,x23,ror#41 // Sigma1(e) + eor x4,x4,x27,ror#34 + add x26,x26,x17 // h+=Ch(e,f,g) + and x19,x19,x28 // (b^c)&=(a^b) + eor x2,x2,x11,ror#61 + eor x3,x3,x14,lsr#7 // sigma0(X[i+1]) + add x26,x26,x16 // h+=Sigma1(e) + eor x19,x19,x20 // Maj(a,b,c) + eor x17,x4,x27,ror#39 // Sigma0(a) + eor x2,x2,x11,lsr#6 // sigma1(X[i+14]) + add x13,x13,x6 + add x22,x22,x26 // d+=h + add x26,x26,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + add x13,x13,x3 + add x26,x26,x17 // h+=Sigma0(a) + add x13,x13,x2 + ldr x2,[sp,#24] + str x5,[sp,#16] + ror x16,x22,#14 + add x25,x25,x19 // h+=K[i] + ror x4,x15,#1 + and x17,x23,x22 + ror x3,x12,#19 + bic x19,x24,x22 + ror x5,x26,#28 + add x25,x25,x13 // h+=X[i] + eor x16,x16,x22,ror#18 + eor x4,x4,x15,ror#8 + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x26,x27 // a^b, b^c in next round + eor x16,x16,x22,ror#41 // Sigma1(e) + eor x5,x5,x26,ror#34 + add x25,x25,x17 // h+=Ch(e,f,g) + and x28,x28,x19 // (b^c)&=(a^b) + eor x3,x3,x12,ror#61 + eor x4,x4,x15,lsr#7 // sigma0(X[i+1]) + add x25,x25,x16 // h+=Sigma1(e) + eor x28,x28,x27 // Maj(a,b,c) + eor x17,x5,x26,ror#39 // Sigma0(a) + eor x3,x3,x12,lsr#6 // sigma1(X[i+14]) + add x14,x14,x7 + add x21,x21,x25 // d+=h + add x25,x25,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + add x14,x14,x4 + add x25,x25,x17 // h+=Sigma0(a) + add x14,x14,x3 + ldr x3,[sp,#0] + str x6,[sp,#24] + ror x16,x21,#14 + add x24,x24,x28 // h+=K[i] + ror x5,x0,#1 + and x17,x22,x21 + ror x4,x13,#19 + bic x28,x23,x21 + ror x6,x25,#28 + add x24,x24,x14 // h+=X[i] + eor x16,x16,x21,ror#18 + eor x5,x5,x0,ror#8 + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x25,x26 // a^b, b^c in next round + eor x16,x16,x21,ror#41 // Sigma1(e) + eor x6,x6,x25,ror#34 + add x24,x24,x17 // h+=Ch(e,f,g) + and x19,x19,x28 // (b^c)&=(a^b) + eor x4,x4,x13,ror#61 + eor x5,x5,x0,lsr#7 // sigma0(X[i+1]) + add x24,x24,x16 // h+=Sigma1(e) + eor x19,x19,x26 // Maj(a,b,c) + eor x17,x6,x25,ror#39 // Sigma0(a) + eor x4,x4,x13,lsr#6 // sigma1(X[i+14]) + add x15,x15,x8 + add x20,x20,x24 // d+=h + add x24,x24,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + add x15,x15,x5 + add x24,x24,x17 // h+=Sigma0(a) + add x15,x15,x4 + ldr x4,[sp,#8] + str x7,[sp,#0] + ror x16,x20,#14 + add x23,x23,x19 // h+=K[i] + ror x6,x1,#1 + and x17,x21,x20 + ror x5,x14,#19 + bic x19,x22,x20 + ror x7,x24,#28 + add x23,x23,x15 // h+=X[i] + eor x16,x16,x20,ror#18 + eor x6,x6,x1,ror#8 + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x24,x25 // a^b, b^c in next round + eor x16,x16,x20,ror#41 // Sigma1(e) + eor x7,x7,x24,ror#34 + add x23,x23,x17 // h+=Ch(e,f,g) + and x28,x28,x19 // (b^c)&=(a^b) + eor x5,x5,x14,ror#61 + eor x6,x6,x1,lsr#7 // sigma0(X[i+1]) + add x23,x23,x16 // h+=Sigma1(e) + eor x28,x28,x25 // Maj(a,b,c) + eor x17,x7,x24,ror#39 // Sigma0(a) + eor x5,x5,x14,lsr#6 // sigma1(X[i+14]) + add x0,x0,x9 + add x27,x27,x23 // d+=h + add x23,x23,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + add x0,x0,x6 + add x23,x23,x17 // h+=Sigma0(a) + add x0,x0,x5 + ldr x5,[sp,#16] + str x8,[sp,#8] + ror x16,x27,#14 + add x22,x22,x28 // h+=K[i] + ror x7,x2,#1 + and x17,x20,x27 + ror x6,x15,#19 + bic x28,x21,x27 + ror x8,x23,#28 + add x22,x22,x0 // h+=X[i] + eor x16,x16,x27,ror#18 + eor x7,x7,x2,ror#8 + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x23,x24 // a^b, b^c in next round + eor x16,x16,x27,ror#41 // Sigma1(e) + eor x8,x8,x23,ror#34 + add x22,x22,x17 // h+=Ch(e,f,g) + and x19,x19,x28 // (b^c)&=(a^b) + eor x6,x6,x15,ror#61 + eor x7,x7,x2,lsr#7 // sigma0(X[i+1]) + add x22,x22,x16 // h+=Sigma1(e) + eor x19,x19,x24 // Maj(a,b,c) + eor x17,x8,x23,ror#39 // Sigma0(a) + eor x6,x6,x15,lsr#6 // sigma1(X[i+14]) + add x1,x1,x10 + add x26,x26,x22 // d+=h + add x22,x22,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + add x1,x1,x7 + add x22,x22,x17 // h+=Sigma0(a) + add x1,x1,x6 + ldr x6,[sp,#24] + str x9,[sp,#16] + ror x16,x26,#14 + add x21,x21,x19 // h+=K[i] + ror x8,x3,#1 + and x17,x27,x26 + ror x7,x0,#19 + bic x19,x20,x26 + ror x9,x22,#28 + add x21,x21,x1 // h+=X[i] + eor x16,x16,x26,ror#18 + eor x8,x8,x3,ror#8 + orr x17,x17,x19 // Ch(e,f,g) + eor x19,x22,x23 // a^b, b^c in next round + eor x16,x16,x26,ror#41 // Sigma1(e) + eor x9,x9,x22,ror#34 + add x21,x21,x17 // h+=Ch(e,f,g) + and x28,x28,x19 // (b^c)&=(a^b) + eor x7,x7,x0,ror#61 + eor x8,x8,x3,lsr#7 // sigma0(X[i+1]) + add x21,x21,x16 // h+=Sigma1(e) + eor x28,x28,x23 // Maj(a,b,c) + eor x17,x9,x22,ror#39 // Sigma0(a) + eor x7,x7,x0,lsr#6 // sigma1(X[i+14]) + add x2,x2,x11 + add x25,x25,x21 // d+=h + add x21,x21,x28 // h+=Maj(a,b,c) + ldr x28,[x30],#8 // *K++, x19 in next round + add x2,x2,x8 + add x21,x21,x17 // h+=Sigma0(a) + add x2,x2,x7 + ldr x7,[sp,#0] + str x10,[sp,#24] + ror x16,x25,#14 + add x20,x20,x28 // h+=K[i] + ror x9,x4,#1 + and x17,x26,x25 + ror x8,x1,#19 + bic x28,x27,x25 + ror x10,x21,#28 + add x20,x20,x2 // h+=X[i] + eor x16,x16,x25,ror#18 + eor x9,x9,x4,ror#8 + orr x17,x17,x28 // Ch(e,f,g) + eor x28,x21,x22 // a^b, b^c in next round + eor x16,x16,x25,ror#41 // Sigma1(e) + eor x10,x10,x21,ror#34 + add x20,x20,x17 // h+=Ch(e,f,g) + and x19,x19,x28 // (b^c)&=(a^b) + eor x8,x8,x1,ror#61 + eor x9,x9,x4,lsr#7 // sigma0(X[i+1]) + add x20,x20,x16 // h+=Sigma1(e) + eor x19,x19,x22 // Maj(a,b,c) + eor x17,x10,x21,ror#39 // Sigma0(a) + eor x8,x8,x1,lsr#6 // sigma1(X[i+14]) + add x3,x3,x12 + add x24,x24,x20 // d+=h + add x20,x20,x19 // h+=Maj(a,b,c) + ldr x19,[x30],#8 // *K++, x28 in next round + add x3,x3,x9 + add x20,x20,x17 // h+=Sigma0(a) + add x3,x3,x8 + cbnz x19,.Loop_16_xx + + ldp x0,x2,[x29,#96] + ldr x1,[x29,#112] + sub x30,x30,#648 // rewind + + ldp x3,x4,[x0] + ldp x5,x6,[x0,#2*8] + add x1,x1,#14*8 // advance input pointer + ldp x7,x8,[x0,#4*8] + add x20,x20,x3 + ldp x9,x10,[x0,#6*8] + add x21,x21,x4 + add x22,x22,x5 + add x23,x23,x6 + stp x20,x21,[x0] + add x24,x24,x7 + add x25,x25,x8 + stp x22,x23,[x0,#2*8] + add x26,x26,x9 + add x27,x27,x10 + cmp x1,x2 + stp x24,x25,[x0,#4*8] + stp x26,x27,[x0,#6*8] + b.ne .Loop + + ldp x19,x20,[x29,#16] + add sp,sp,#4*8 + ldp x21,x22,[x29,#32] + ldp x23,x24,[x29,#48] + ldp x25,x26,[x29,#64] + ldp x27,x28,[x29,#80] + ldp x29,x30,[sp],#128 + ret +.size sha512_block_data_order,.-sha512_block_data_order + +.align 6 +.type .LK512,%object +.LK512: + .quad 0x428a2f98d728ae22,0x7137449123ef65cd + .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc + .quad 0x3956c25bf348b538,0x59f111f1b605d019 + .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118 + .quad 0xd807aa98a3030242,0x12835b0145706fbe + .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2 + .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1 + .quad 0x9bdc06a725c71235,0xc19bf174cf692694 + .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3 + .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65 + .quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483 + .quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5 + .quad 0x983e5152ee66dfab,0xa831c66d2db43210 + .quad 0xb00327c898fb213f,0xbf597fc7beef0ee4 + .quad 0xc6e00bf33da88fc2,0xd5a79147930aa725 + .quad 0x06ca6351e003826f,0x142929670a0e6e70 + .quad 0x27b70a8546d22ffc,0x2e1b21385c26c926 + .quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df + .quad 0x650a73548baf63de,0x766a0abb3c77b2a8 + .quad 0x81c2c92e47edaee6,0x92722c851482353b + .quad 0xa2bfe8a14cf10364,0xa81a664bbc423001 + .quad 0xc24b8b70d0f89791,0xc76c51a30654be30 + .quad 0xd192e819d6ef5218,0xd69906245565a910 + .quad 0xf40e35855771202a,0x106aa07032bbd1b8 + .quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53 + .quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8 + .quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb + .quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3 + .quad 0x748f82ee5defb2fc,0x78a5636f43172f60 + .quad 0x84c87814a1f0ab72,0x8cc702081a6439ec + .quad 0x90befffa23631e28,0xa4506cebde82bde9 + .quad 0xbef9a3f7b2c67915,0xc67178f2e372532b + .quad 0xca273eceea26619c,0xd186b8c721c0c207 + .quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178 + .quad 0x06f067aa72176fba,0x0a637dc5a2c898a6 + .quad 0x113f9804bef90dae,0x1b710b35131c471b + .quad 0x28db77f523047d84,0x32caab7b40c72493 + .quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c + .quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a + .quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817 + .quad 0 // terminator +.size .LK512,.-.LK512 +#ifndef __KERNEL__ +.align 3 +.LOPENSSL_armcap_P: +# ifdef __ILP32__ + .long OPENSSL_armcap_P-. +# else + .quad OPENSSL_armcap_P-. +# endif +#endif +.asciz "SHA512 block transform for ARMv8, CRYPTOGAMS by <appro@openssl.org>" +.align 2 +#ifndef __KERNEL__ +.comm OPENSSL_armcap_P,4,4 +#endif diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/bugs.h linux/arch/arm64/include/generated/asm/bugs.h --- linux-6.1.66/arch/arm64/include/generated/asm/bugs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/bugs.h 2023-12-14 11:56:01.519665384 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/bugs.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/cpucaps.h linux/arch/arm64/include/generated/asm/cpucaps.h --- linux-6.1.66/arch/arm64/include/generated/asm/cpucaps.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/cpucaps.h 2023-12-14 14:24:48.665315292 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +#ifndef __ASM_CPUCAPS_H +#define __ASM_CPUCAPS_H + +/* Generated file - do not edit */ + +#define ARM64_ALWAYS_BOOT 0 +#define ARM64_ALWAYS_SYSTEM 1 +#define ARM64_BTI 2 +#define ARM64_HAS_32BIT_EL0_DO_NOT_USE 3 +#define ARM64_HAS_32BIT_EL1 4 +#define ARM64_HAS_ADDRESS_AUTH 5 +#define ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3 6 +#define ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5 7 +#define ARM64_HAS_ADDRESS_AUTH_IMP_DEF 8 +#define ARM64_HAS_AMU_EXTN 9 +#define ARM64_HAS_ARMv8_4_TTL 10 +#define ARM64_HAS_CACHE_DIC 11 +#define ARM64_HAS_CACHE_IDC 12 +#define ARM64_HAS_CNP 13 +#define ARM64_HAS_CRC32 14 +#define ARM64_HAS_DCPODP 15 +#define ARM64_HAS_DCPOP 16 +#define ARM64_HAS_E0PD 17 +#define ARM64_HAS_ECV 18 +#define ARM64_HAS_EPAN 19 +#define ARM64_HAS_GENERIC_AUTH 20 +#define ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3 21 +#define ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5 22 +#define ARM64_HAS_GENERIC_AUTH_IMP_DEF 23 +#define ARM64_HAS_IRQ_PRIO_MASKING 24 +#define ARM64_HAS_LDAPR 25 +#define ARM64_HAS_LSE_ATOMICS 26 +#define ARM64_HAS_NO_FPSIMD 27 +#define ARM64_HAS_NO_HW_PREFETCH 28 +#define ARM64_HAS_PAN 29 +#define ARM64_HAS_RAS_EXTN 30 +#define ARM64_HAS_RNG 31 +#define ARM64_HAS_SB 32 +#define ARM64_HAS_STAGE2_FWB 33 +#define ARM64_HAS_SYSREG_GIC_CPUIF 34 +#define ARM64_HAS_TIDCP1 35 +#define ARM64_HAS_TLB_RANGE 36 +#define ARM64_HAS_VIRT_HOST_EXTN 37 +#define ARM64_HAS_WFXT 38 +#define ARM64_HW_DBM 39 +#define ARM64_KVM_PROTECTED_MODE 40 +#define ARM64_MISMATCHED_CACHE_TYPE 41 +#define ARM64_MTE 42 +#define ARM64_MTE_ASYMM 43 +#define ARM64_SME 44 +#define ARM64_SME_FA64 45 +#define ARM64_SPECTRE_V2 46 +#define ARM64_SPECTRE_V3A 47 +#define ARM64_SPECTRE_V4 48 +#define ARM64_SPECTRE_BHB 49 +#define ARM64_SSBS 50 +#define ARM64_SVE 51 +#define ARM64_UNMAP_KERNEL_AT_EL0 52 +#define ARM64_WORKAROUND_834220 53 +#define ARM64_WORKAROUND_843419 54 +#define ARM64_WORKAROUND_845719 55 +#define ARM64_WORKAROUND_858921 56 +#define ARM64_WORKAROUND_1418040 57 +#define ARM64_WORKAROUND_1463225 58 +#define ARM64_WORKAROUND_1508412 59 +#define ARM64_WORKAROUND_1542419 60 +#define ARM64_WORKAROUND_1742098 61 +#define ARM64_WORKAROUND_1902691 62 +#define ARM64_WORKAROUND_2038923 63 +#define ARM64_WORKAROUND_2064142 64 +#define ARM64_WORKAROUND_2077057 65 +#define ARM64_WORKAROUND_2457168 66 +#define ARM64_WORKAROUND_2658417 67 +#define ARM64_WORKAROUND_2966298 68 +#define ARM64_WORKAROUND_AMPERE_AC03_CPU_38 69 +#define ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 70 +#define ARM64_WORKAROUND_TSB_FLUSH_FAILURE 71 +#define ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 72 +#define ARM64_WORKAROUND_CAVIUM_23154 73 +#define ARM64_WORKAROUND_CAVIUM_27456 74 +#define ARM64_WORKAROUND_CAVIUM_30115 75 +#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 76 +#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 77 +#define ARM64_WORKAROUND_CLEAN_CACHE 78 +#define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 79 +#define ARM64_WORKAROUND_NVIDIA_CARMEL_CNP 80 +#define ARM64_WORKAROUND_QCOM_FALKOR_E1003 81 +#define ARM64_WORKAROUND_REPEAT_TLBI 82 +#define ARM64_WORKAROUND_SPECULATIVE_AT 83 +#define ARM64_NCAPS 84 + +#endif /* __ASM_CPUCAPS_H */ diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/delay.h linux/arch/arm64/include/generated/asm/delay.h --- linux-6.1.66/arch/arm64/include/generated/asm/delay.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/delay.h 2023-12-14 11:56:01.519665384 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/delay.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/div64.h linux/arch/arm64/include/generated/asm/div64.h --- linux-6.1.66/arch/arm64/include/generated/asm/div64.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/div64.h 2023-12-14 11:56:01.520665387 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/div64.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/dma.h linux/arch/arm64/include/generated/asm/dma.h --- linux-6.1.66/arch/arm64/include/generated/asm/dma.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/dma.h 2023-12-14 11:56:01.522665391 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/dma.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/dma-mapping.h linux/arch/arm64/include/generated/asm/dma-mapping.h --- linux-6.1.66/arch/arm64/include/generated/asm/dma-mapping.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/dma-mapping.h 2023-12-14 11:56:01.521665389 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/dma-mapping.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/early_ioremap.h linux/arch/arm64/include/generated/asm/early_ioremap.h --- linux-6.1.66/arch/arm64/include/generated/asm/early_ioremap.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/early_ioremap.h 2023-12-14 11:56:01.513665371 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/early_ioremap.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/emergency-restart.h linux/arch/arm64/include/generated/asm/emergency-restart.h --- linux-6.1.66/arch/arm64/include/generated/asm/emergency-restart.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/emergency-restart.h 2023-12-14 11:56:01.523665393 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/emergency-restart.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/hw_irq.h linux/arch/arm64/include/generated/asm/hw_irq.h --- linux-6.1.66/arch/arm64/include/generated/asm/hw_irq.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/hw_irq.h 2023-12-14 11:56:01.524665396 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/hw_irq.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/irq_regs.h linux/arch/arm64/include/generated/asm/irq_regs.h --- linux-6.1.66/arch/arm64/include/generated/asm/irq_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/irq_regs.h 2023-12-14 11:56:01.525665398 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/irq_regs.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/kdebug.h linux/arch/arm64/include/generated/asm/kdebug.h --- linux-6.1.66/arch/arm64/include/generated/asm/kdebug.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/kdebug.h 2023-12-14 11:56:01.526665400 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/kdebug.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/kmap_size.h linux/arch/arm64/include/generated/asm/kmap_size.h --- linux-6.1.66/arch/arm64/include/generated/asm/kmap_size.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/kmap_size.h 2023-12-14 11:56:01.527665402 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/kmap_size.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/local64.h linux/arch/arm64/include/generated/asm/local64.h --- linux-6.1.66/arch/arm64/include/generated/asm/local64.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/local64.h 2023-12-14 11:56:01.528665404 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/local64.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/local.h linux/arch/arm64/include/generated/asm/local.h --- linux-6.1.66/arch/arm64/include/generated/asm/local.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/local.h 2023-12-14 11:56:01.527665402 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/local.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/mcs_spinlock.h linux/arch/arm64/include/generated/asm/mcs_spinlock.h --- linux-6.1.66/arch/arm64/include/generated/asm/mcs_spinlock.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/mcs_spinlock.h 2023-12-14 11:56:01.514665373 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/mcs_spinlock.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/mmiowb.h linux/arch/arm64/include/generated/asm/mmiowb.h --- linux-6.1.66/arch/arm64/include/generated/asm/mmiowb.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/mmiowb.h 2023-12-14 11:56:01.529665407 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/mmiowb.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/msi.h linux/arch/arm64/include/generated/asm/msi.h --- linux-6.1.66/arch/arm64/include/generated/asm/msi.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/msi.h 2023-12-14 11:56:01.530665409 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/msi.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/parport.h linux/arch/arm64/include/generated/asm/parport.h --- linux-6.1.66/arch/arm64/include/generated/asm/parport.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/parport.h 2023-12-14 11:56:01.517665380 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/parport.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/qrwlock.h linux/arch/arm64/include/generated/asm/qrwlock.h --- linux-6.1.66/arch/arm64/include/generated/asm/qrwlock.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/qrwlock.h 2023-12-14 11:56:01.515665375 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/qrwlock.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/qspinlock.h linux/arch/arm64/include/generated/asm/qspinlock.h --- linux-6.1.66/arch/arm64/include/generated/asm/qspinlock.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/qspinlock.h 2023-12-14 11:56:01.516665378 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/qspinlock.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/serial.h linux/arch/arm64/include/generated/asm/serial.h --- linux-6.1.66/arch/arm64/include/generated/asm/serial.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/serial.h 2023-12-14 11:56:01.531665411 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/serial.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/softirq_stack.h linux/arch/arm64/include/generated/asm/softirq_stack.h --- linux-6.1.66/arch/arm64/include/generated/asm/softirq_stack.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/softirq_stack.h 2023-12-14 11:56:01.532665413 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/softirq_stack.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/switch_to.h linux/arch/arm64/include/generated/asm/switch_to.h --- linux-6.1.66/arch/arm64/include/generated/asm/switch_to.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/switch_to.h 2023-12-14 11:56:01.533665416 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/switch_to.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/sysreg-defs.h linux/arch/arm64/include/generated/asm/sysreg-defs.h --- linux-6.1.66/arch/arm64/include/generated/asm/sysreg-defs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/sysreg-defs.h 2023-12-14 14:24:48.679315322 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +#ifndef __ASM_SYSREG_DEFS_H +#define __ASM_SYSREG_DEFS_H + +/* Generated file - do not edit */ + +#define REG_ID_AA64PFR0_EL1 S3_0_C0_C4_0 +#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) +#define SYS_ID_AA64PFR0_EL1_Op0 3 +#define SYS_ID_AA64PFR0_EL1_Op1 0 +#define SYS_ID_AA64PFR0_EL1_CRn 0 +#define SYS_ID_AA64PFR0_EL1_CRm 4 +#define SYS_ID_AA64PFR0_EL1_Op2 0 + +#define ID_AA64PFR0_EL1_CSV3 GENMASK(63, 60) +#define ID_AA64PFR0_EL1_CSV3_MASK GENMASK(63, 60) +#define ID_AA64PFR0_EL1_CSV3_SHIFT 60 +#define ID_AA64PFR0_EL1_CSV3_WIDTH 4 +#define ID_AA64PFR0_EL1_CSV3_NI UL(0b0000) +#define ID_AA64PFR0_EL1_CSV3_IMP UL(0b0001) + +#define ID_AA64PFR0_EL1_CSV2 GENMASK(59, 56) +#define ID_AA64PFR0_EL1_CSV2_MASK GENMASK(59, 56) +#define ID_AA64PFR0_EL1_CSV2_SHIFT 56 +#define ID_AA64PFR0_EL1_CSV2_WIDTH 4 +#define ID_AA64PFR0_EL1_CSV2_NI UL(0b0000) +#define ID_AA64PFR0_EL1_CSV2_IMP UL(0b0001) +#define ID_AA64PFR0_EL1_CSV2_CSV2_2 UL(0b0010) +#define ID_AA64PFR0_EL1_CSV2_CSV2_3 UL(0b0011) + +#define ID_AA64PFR0_EL1_RME GENMASK(55, 52) +#define ID_AA64PFR0_EL1_RME_MASK GENMASK(55, 52) +#define ID_AA64PFR0_EL1_RME_SHIFT 52 +#define ID_AA64PFR0_EL1_RME_WIDTH 4 +#define ID_AA64PFR0_EL1_RME_NI UL(0b0000) +#define ID_AA64PFR0_EL1_RME_IMP UL(0b0001) + +#define ID_AA64PFR0_EL1_DIT GENMASK(51, 48) +#define ID_AA64PFR0_EL1_DIT_MASK GENMASK(51, 48) +#define ID_AA64PFR0_EL1_DIT_SHIFT 48 +#define ID_AA64PFR0_EL1_DIT_WIDTH 4 +#define ID_AA64PFR0_EL1_DIT_NI UL(0b0000) +#define ID_AA64PFR0_EL1_DIT_IMP UL(0b0001) + +#define ID_AA64PFR0_EL1_AMU GENMASK(47, 44) +#define ID_AA64PFR0_EL1_AMU_MASK GENMASK(47, 44) +#define ID_AA64PFR0_EL1_AMU_SHIFT 44 +#define ID_AA64PFR0_EL1_AMU_WIDTH 4 +#define ID_AA64PFR0_EL1_AMU_NI UL(0b0000) +#define ID_AA64PFR0_EL1_AMU_IMP UL(0b0001) +#define ID_AA64PFR0_EL1_AMU_V1P1 UL(0b0010) + +#define ID_AA64PFR0_EL1_MPAM GENMASK(43, 40) +#define ID_AA64PFR0_EL1_MPAM_MASK GENMASK(43, 40) +#define ID_AA64PFR0_EL1_MPAM_SHIFT 40 +#define ID_AA64PFR0_EL1_MPAM_WIDTH 4 +#define ID_AA64PFR0_EL1_MPAM_0 UL(0b0000) +#define ID_AA64PFR0_EL1_MPAM_1 UL(0b0001) + +#define ID_AA64PFR0_EL1_SEL2 GENMASK(39, 36) +#define ID_AA64PFR0_EL1_SEL2_MASK GENMASK(39, 36) +#define ID_AA64PFR0_EL1_SEL2_SHIFT 36 +#define ID_AA64PFR0_EL1_SEL2_WIDTH 4 +#define ID_AA64PFR0_EL1_SEL2_NI UL(0b0000) +#define ID_AA64PFR0_EL1_SEL2_IMP UL(0b0001) + +#define ID_AA64PFR0_EL1_SVE GENMASK(35, 32) +#define ID_AA64PFR0_EL1_SVE_MASK GENMASK(35, 32) +#define ID_AA64PFR0_EL1_SVE_SHIFT 32 +#define ID_AA64PFR0_EL1_SVE_WIDTH 4 +#define ID_AA64PFR0_EL1_SVE_NI UL(0b0000) +#define ID_AA64PFR0_EL1_SVE_IMP UL(0b0001) + +#define ID_AA64PFR0_EL1_RAS GENMASK(31, 28) +#define ID_AA64PFR0_EL1_RAS_MASK GENMASK(31, 28) +#define ID_AA64PFR0_EL1_RAS_SHIFT 28 +#define ID_AA64PFR0_EL1_RAS_WIDTH 4 +#define ID_AA64PFR0_EL1_RAS_NI UL(0b0000) +#define ID_AA64PFR0_EL1_RAS_IMP UL(0b0001) +#define ID_AA64PFR0_EL1_RAS_V1P1 UL(0b0010) + +#define ID_AA64PFR0_EL1_GIC GENMASK(27, 24) +#define ID_AA64PFR0_EL1_GIC_MASK GENMASK(27, 24) +#define ID_AA64PFR0_EL1_GIC_SHIFT 24 +#define ID_AA64PFR0_EL1_GIC_WIDTH 4 +#define ID_AA64PFR0_EL1_GIC_NI UL(0b0000) +#define ID_AA64PFR0_EL1_GIC_IMP UL(0b0001) +#define ID_AA64PFR0_EL1_GIC_V4P1 UL(0b0010) + +#define ID_AA64PFR0_EL1_AdvSIMD GENMASK(23, 20) +#define ID_AA64PFR0_EL1_AdvSIMD_MASK GENMASK(23, 20) +#define ID_AA64PFR0_EL1_AdvSIMD_SHIFT 20 +#define ID_AA64PFR0_EL1_AdvSIMD_WIDTH 4 +#define ID_AA64PFR0_EL1_AdvSIMD_IMP UL(0b0000) +#define ID_AA64PFR0_EL1_AdvSIMD_FP16 UL(0b0001) +#define ID_AA64PFR0_EL1_AdvSIMD_NI UL(0b1111) + +#define ID_AA64PFR0_EL1_FP GENMASK(19, 16) +#define ID_AA64PFR0_EL1_FP_MASK GENMASK(19, 16) +#define ID_AA64PFR0_EL1_FP_SHIFT 16 +#define ID_AA64PFR0_EL1_FP_WIDTH 4 +#define ID_AA64PFR0_EL1_FP_IMP UL(0b0000) +#define ID_AA64PFR0_EL1_FP_FP16 UL(0b0001) +#define ID_AA64PFR0_EL1_FP_NI UL(0b1111) + +#define ID_AA64PFR0_EL1_EL3 GENMASK(15, 12) +#define ID_AA64PFR0_EL1_EL3_MASK GENMASK(15, 12) +#define ID_AA64PFR0_EL1_EL3_SHIFT 12 +#define ID_AA64PFR0_EL1_EL3_WIDTH 4 +#define ID_AA64PFR0_EL1_EL3_NI UL(0b0000) +#define ID_AA64PFR0_EL1_EL3_IMP UL(0b0001) +#define ID_AA64PFR0_EL1_EL3_AARCH32 UL(0b0010) + +#define ID_AA64PFR0_EL1_EL2 GENMASK(11, 8) +#define ID_AA64PFR0_EL1_EL2_MASK GENMASK(11, 8) +#define ID_AA64PFR0_EL1_EL2_SHIFT 8 +#define ID_AA64PFR0_EL1_EL2_WIDTH 4 +#define ID_AA64PFR0_EL1_EL2_NI UL(0b0000) +#define ID_AA64PFR0_EL1_EL2_IMP UL(0b0001) +#define ID_AA64PFR0_EL1_EL2_AARCH32 UL(0b0010) + +#define ID_AA64PFR0_EL1_EL1 GENMASK(7, 4) +#define ID_AA64PFR0_EL1_EL1_MASK GENMASK(7, 4) +#define ID_AA64PFR0_EL1_EL1_SHIFT 4 +#define ID_AA64PFR0_EL1_EL1_WIDTH 4 +#define ID_AA64PFR0_EL1_EL1_IMP UL(0b0001) +#define ID_AA64PFR0_EL1_EL1_AARCH32 UL(0b0010) + +#define ID_AA64PFR0_EL1_EL0 GENMASK(3, 0) +#define ID_AA64PFR0_EL1_EL0_MASK GENMASK(3, 0) +#define ID_AA64PFR0_EL1_EL0_SHIFT 0 +#define ID_AA64PFR0_EL1_EL0_WIDTH 4 +#define ID_AA64PFR0_EL1_EL0_IMP UL(0b0001) +#define ID_AA64PFR0_EL1_EL0_AARCH32 UL(0b0010) + +#define ID_AA64PFR0_EL1_RES0 (UL(0)) +#define ID_AA64PFR0_EL1_RES1 (UL(0)) + +#define REG_ID_AA64PFR1_EL1 S3_0_C0_C4_1 +#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) +#define SYS_ID_AA64PFR1_EL1_Op0 3 +#define SYS_ID_AA64PFR1_EL1_Op1 0 +#define SYS_ID_AA64PFR1_EL1_CRn 0 +#define SYS_ID_AA64PFR1_EL1_CRm 4 +#define SYS_ID_AA64PFR1_EL1_Op2 1 + +#define ID_AA64PFR1_EL1_NMI GENMASK(39, 36) +#define ID_AA64PFR1_EL1_NMI_MASK GENMASK(39, 36) +#define ID_AA64PFR1_EL1_NMI_SHIFT 36 +#define ID_AA64PFR1_EL1_NMI_WIDTH 4 +#define ID_AA64PFR1_EL1_NMI_NI UL(0b0000) +#define ID_AA64PFR1_EL1_NMI_IMP UL(0b0001) + +#define ID_AA64PFR1_EL1_CSV2_frac GENMASK(35, 32) +#define ID_AA64PFR1_EL1_CSV2_frac_MASK GENMASK(35, 32) +#define ID_AA64PFR1_EL1_CSV2_frac_SHIFT 32 +#define ID_AA64PFR1_EL1_CSV2_frac_WIDTH 4 +#define ID_AA64PFR1_EL1_CSV2_frac_NI UL(0b0000) +#define ID_AA64PFR1_EL1_CSV2_frac_CSV2_1p1 UL(0b0001) +#define ID_AA64PFR1_EL1_CSV2_frac_CSV2_1p2 UL(0b0010) + +#define ID_AA64PFR1_EL1_RNDR_trap GENMASK(31, 28) +#define ID_AA64PFR1_EL1_RNDR_trap_MASK GENMASK(31, 28) +#define ID_AA64PFR1_EL1_RNDR_trap_SHIFT 28 +#define ID_AA64PFR1_EL1_RNDR_trap_WIDTH 4 +#define ID_AA64PFR1_EL1_RNDR_trap_NI UL(0b0000) +#define ID_AA64PFR1_EL1_RNDR_trap_IMP UL(0b0001) + +#define ID_AA64PFR1_EL1_SME GENMASK(27, 24) +#define ID_AA64PFR1_EL1_SME_MASK GENMASK(27, 24) +#define ID_AA64PFR1_EL1_SME_SHIFT 24 +#define ID_AA64PFR1_EL1_SME_WIDTH 4 +#define ID_AA64PFR1_EL1_SME_NI UL(0b0000) +#define ID_AA64PFR1_EL1_SME_IMP UL(0b0001) + +#define ID_AA64PFR1_EL1_MPAM_frac GENMASK(19, 16) +#define ID_AA64PFR1_EL1_MPAM_frac_MASK GENMASK(19, 16) +#define ID_AA64PFR1_EL1_MPAM_frac_SHIFT 16 +#define ID_AA64PFR1_EL1_MPAM_frac_WIDTH 4 +#define ID_AA64PFR1_EL1_MPAM_frac_MINOR_0 UL(0b0000) +#define ID_AA64PFR1_EL1_MPAM_frac_MINOR_1 UL(0b0001) + +#define ID_AA64PFR1_EL1_RAS_frac GENMASK(15, 12) +#define ID_AA64PFR1_EL1_RAS_frac_MASK GENMASK(15, 12) +#define ID_AA64PFR1_EL1_RAS_frac_SHIFT 12 +#define ID_AA64PFR1_EL1_RAS_frac_WIDTH 4 +#define ID_AA64PFR1_EL1_RAS_frac_NI UL(0b0000) +#define ID_AA64PFR1_EL1_RAS_frac_RASv1p1 UL(0b0001) + +#define ID_AA64PFR1_EL1_MTE GENMASK(11, 8) +#define ID_AA64PFR1_EL1_MTE_MASK GENMASK(11, 8) +#define ID_AA64PFR1_EL1_MTE_SHIFT 8 +#define ID_AA64PFR1_EL1_MTE_WIDTH 4 +#define ID_AA64PFR1_EL1_MTE_NI UL(0b0000) +#define ID_AA64PFR1_EL1_MTE_IMP UL(0b0001) +#define ID_AA64PFR1_EL1_MTE_MTE2 UL(0b0010) +#define ID_AA64PFR1_EL1_MTE_MTE3 UL(0b0011) + +#define ID_AA64PFR1_EL1_SSBS GENMASK(7, 4) +#define ID_AA64PFR1_EL1_SSBS_MASK GENMASK(7, 4) +#define ID_AA64PFR1_EL1_SSBS_SHIFT 4 +#define ID_AA64PFR1_EL1_SSBS_WIDTH 4 +#define ID_AA64PFR1_EL1_SSBS_NI UL(0b0000) +#define ID_AA64PFR1_EL1_SSBS_IMP UL(0b0001) +#define ID_AA64PFR1_EL1_SSBS_SSBS2 UL(0b0010) + +#define ID_AA64PFR1_EL1_BT GENMASK(3, 0) +#define ID_AA64PFR1_EL1_BT_MASK GENMASK(3, 0) +#define ID_AA64PFR1_EL1_BT_SHIFT 0 +#define ID_AA64PFR1_EL1_BT_WIDTH 4 +#define ID_AA64PFR1_EL1_BT_NI UL(0b0000) +#define ID_AA64PFR1_EL1_BT_IMP UL(0b0001) + +#define ID_AA64PFR1_EL1_RES0 (UL(0) | GENMASK_ULL(63, 40) | GENMASK_ULL(23, 20)) +#define ID_AA64PFR1_EL1_RES1 (UL(0)) + +#define REG_ID_AA64ZFR0_EL1 S3_0_C0_C4_4 +#define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) +#define SYS_ID_AA64ZFR0_EL1_Op0 3 +#define SYS_ID_AA64ZFR0_EL1_Op1 0 +#define SYS_ID_AA64ZFR0_EL1_CRn 0 +#define SYS_ID_AA64ZFR0_EL1_CRm 4 +#define SYS_ID_AA64ZFR0_EL1_Op2 4 + +#define ID_AA64ZFR0_EL1_F64MM GENMASK(59, 56) +#define ID_AA64ZFR0_EL1_F64MM_MASK GENMASK(59, 56) +#define ID_AA64ZFR0_EL1_F64MM_SHIFT 56 +#define ID_AA64ZFR0_EL1_F64MM_WIDTH 4 +#define ID_AA64ZFR0_EL1_F64MM_NI UL(0b0000) +#define ID_AA64ZFR0_EL1_F64MM_IMP UL(0b0001) + +#define ID_AA64ZFR0_EL1_F32MM GENMASK(55, 52) +#define ID_AA64ZFR0_EL1_F32MM_MASK GENMASK(55, 52) +#define ID_AA64ZFR0_EL1_F32MM_SHIFT 52 +#define ID_AA64ZFR0_EL1_F32MM_WIDTH 4 +#define ID_AA64ZFR0_EL1_F32MM_NI UL(0b0000) +#define ID_AA64ZFR0_EL1_F32MM_IMP UL(0b0001) + +#define ID_AA64ZFR0_EL1_I8MM GENMASK(47, 44) +#define ID_AA64ZFR0_EL1_I8MM_MASK GENMASK(47, 44) +#define ID_AA64ZFR0_EL1_I8MM_SHIFT 44 +#define ID_AA64ZFR0_EL1_I8MM_WIDTH 4 +#define ID_AA64ZFR0_EL1_I8MM_NI UL(0b0000) +#define ID_AA64ZFR0_EL1_I8MM_IMP UL(0b0001) + +#define ID_AA64ZFR0_EL1_SM4 GENMASK(43, 40) +#define ID_AA64ZFR0_EL1_SM4_MASK GENMASK(43, 40) +#define ID_AA64ZFR0_EL1_SM4_SHIFT 40 +#define ID_AA64ZFR0_EL1_SM4_WIDTH 4 +#define ID_AA64ZFR0_EL1_SM4_NI UL(0b0000) +#define ID_AA64ZFR0_EL1_SM4_IMP UL(0b0001) + +#define ID_AA64ZFR0_EL1_SHA3 GENMASK(35, 32) +#define ID_AA64ZFR0_EL1_SHA3_MASK GENMASK(35, 32) +#define ID_AA64ZFR0_EL1_SHA3_SHIFT 32 +#define ID_AA64ZFR0_EL1_SHA3_WIDTH 4 +#define ID_AA64ZFR0_EL1_SHA3_NI UL(0b0000) +#define ID_AA64ZFR0_EL1_SHA3_IMP UL(0b0001) + +#define ID_AA64ZFR0_EL1_BF16 GENMASK(23, 20) +#define ID_AA64ZFR0_EL1_BF16_MASK GENMASK(23, 20) +#define ID_AA64ZFR0_EL1_BF16_SHIFT 20 +#define ID_AA64ZFR0_EL1_BF16_WIDTH 4 +#define ID_AA64ZFR0_EL1_BF16_NI UL(0b0000) +#define ID_AA64ZFR0_EL1_BF16_IMP UL(0b0001) +#define ID_AA64ZFR0_EL1_BF16_EBF16 UL(0b0010) + +#define ID_AA64ZFR0_EL1_BitPerm GENMASK(19, 16) +#define ID_AA64ZFR0_EL1_BitPerm_MASK GENMASK(19, 16) +#define ID_AA64ZFR0_EL1_BitPerm_SHIFT 16 +#define ID_AA64ZFR0_EL1_BitPerm_WIDTH 4 +#define ID_AA64ZFR0_EL1_BitPerm_NI UL(0b0000) +#define ID_AA64ZFR0_EL1_BitPerm_IMP UL(0b0001) + +#define ID_AA64ZFR0_EL1_AES GENMASK(7, 4) +#define ID_AA64ZFR0_EL1_AES_MASK GENMASK(7, 4) +#define ID_AA64ZFR0_EL1_AES_SHIFT 4 +#define ID_AA64ZFR0_EL1_AES_WIDTH 4 +#define ID_AA64ZFR0_EL1_AES_NI UL(0b0000) +#define ID_AA64ZFR0_EL1_AES_IMP UL(0b0001) +#define ID_AA64ZFR0_EL1_AES_PMULL128 UL(0b0010) + +#define ID_AA64ZFR0_EL1_SVEver GENMASK(3, 0) +#define ID_AA64ZFR0_EL1_SVEver_MASK GENMASK(3, 0) +#define ID_AA64ZFR0_EL1_SVEver_SHIFT 0 +#define ID_AA64ZFR0_EL1_SVEver_WIDTH 4 +#define ID_AA64ZFR0_EL1_SVEver_IMP UL(0b0000) +#define ID_AA64ZFR0_EL1_SVEver_SVE2 UL(0b0001) + +#define ID_AA64ZFR0_EL1_RES0 (UL(0) | GENMASK_ULL(63, 60) | GENMASK_ULL(51, 48) | GENMASK_ULL(39, 36) | GENMASK_ULL(31, 24) | GENMASK_ULL(15, 8)) +#define ID_AA64ZFR0_EL1_RES1 (UL(0)) + +#define REG_ID_AA64SMFR0_EL1 S3_0_C0_C4_5 +#define SYS_ID_AA64SMFR0_EL1 sys_reg(3, 0, 0, 4, 5) +#define SYS_ID_AA64SMFR0_EL1_Op0 3 +#define SYS_ID_AA64SMFR0_EL1_Op1 0 +#define SYS_ID_AA64SMFR0_EL1_CRn 0 +#define SYS_ID_AA64SMFR0_EL1_CRm 4 +#define SYS_ID_AA64SMFR0_EL1_Op2 5 + +#define ID_AA64SMFR0_EL1_FA64 GENMASK(63, 63) +#define ID_AA64SMFR0_EL1_FA64_MASK GENMASK(63, 63) +#define ID_AA64SMFR0_EL1_FA64_SHIFT 63 +#define ID_AA64SMFR0_EL1_FA64_WIDTH 1 +#define ID_AA64SMFR0_EL1_FA64_NI UL(0b0) +#define ID_AA64SMFR0_EL1_FA64_IMP UL(0b1) + +#define ID_AA64SMFR0_EL1_SMEver GENMASK(59, 56) +#define ID_AA64SMFR0_EL1_SMEver_MASK GENMASK(59, 56) +#define ID_AA64SMFR0_EL1_SMEver_SHIFT 56 +#define ID_AA64SMFR0_EL1_SMEver_WIDTH 4 +#define ID_AA64SMFR0_EL1_SMEver_IMP UL(0b0000) + +#define ID_AA64SMFR0_EL1_I16I64 GENMASK(55, 52) +#define ID_AA64SMFR0_EL1_I16I64_MASK GENMASK(55, 52) +#define ID_AA64SMFR0_EL1_I16I64_SHIFT 52 +#define ID_AA64SMFR0_EL1_I16I64_WIDTH 4 +#define ID_AA64SMFR0_EL1_I16I64_NI UL(0b0000) +#define ID_AA64SMFR0_EL1_I16I64_IMP UL(0b1111) + +#define ID_AA64SMFR0_EL1_F64F64 GENMASK(48, 48) +#define ID_AA64SMFR0_EL1_F64F64_MASK GENMASK(48, 48) +#define ID_AA64SMFR0_EL1_F64F64_SHIFT 48 +#define ID_AA64SMFR0_EL1_F64F64_WIDTH 1 +#define ID_AA64SMFR0_EL1_F64F64_NI UL(0b0) +#define ID_AA64SMFR0_EL1_F64F64_IMP UL(0b1) + +#define ID_AA64SMFR0_EL1_I8I32 GENMASK(39, 36) +#define ID_AA64SMFR0_EL1_I8I32_MASK GENMASK(39, 36) +#define ID_AA64SMFR0_EL1_I8I32_SHIFT 36 +#define ID_AA64SMFR0_EL1_I8I32_WIDTH 4 +#define ID_AA64SMFR0_EL1_I8I32_NI UL(0b0000) +#define ID_AA64SMFR0_EL1_I8I32_IMP UL(0b1111) + +#define ID_AA64SMFR0_EL1_F16F32 GENMASK(35, 35) +#define ID_AA64SMFR0_EL1_F16F32_MASK GENMASK(35, 35) +#define ID_AA64SMFR0_EL1_F16F32_SHIFT 35 +#define ID_AA64SMFR0_EL1_F16F32_WIDTH 1 +#define ID_AA64SMFR0_EL1_F16F32_NI UL(0b0) +#define ID_AA64SMFR0_EL1_F16F32_IMP UL(0b1) + +#define ID_AA64SMFR0_EL1_B16F32 GENMASK(34, 34) +#define ID_AA64SMFR0_EL1_B16F32_MASK GENMASK(34, 34) +#define ID_AA64SMFR0_EL1_B16F32_SHIFT 34 +#define ID_AA64SMFR0_EL1_B16F32_WIDTH 1 +#define ID_AA64SMFR0_EL1_B16F32_NI UL(0b0) +#define ID_AA64SMFR0_EL1_B16F32_IMP UL(0b1) + +#define ID_AA64SMFR0_EL1_F32F32 GENMASK(32, 32) +#define ID_AA64SMFR0_EL1_F32F32_MASK GENMASK(32, 32) +#define ID_AA64SMFR0_EL1_F32F32_SHIFT 32 +#define ID_AA64SMFR0_EL1_F32F32_WIDTH 1 +#define ID_AA64SMFR0_EL1_F32F32_NI UL(0b0) +#define ID_AA64SMFR0_EL1_F32F32_IMP UL(0b1) + +#define ID_AA64SMFR0_EL1_RES0 (UL(0) | GENMASK_ULL(62, 60) | GENMASK_ULL(51, 49) | GENMASK_ULL(47, 40) | GENMASK_ULL(33, 33) | GENMASK_ULL(31, 0)) +#define ID_AA64SMFR0_EL1_RES1 (UL(0)) + +#define REG_ID_AA64DFR0_EL1 S3_0_C0_C5_0 +#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) +#define SYS_ID_AA64DFR0_EL1_Op0 3 +#define SYS_ID_AA64DFR0_EL1_Op1 0 +#define SYS_ID_AA64DFR0_EL1_CRn 0 +#define SYS_ID_AA64DFR0_EL1_CRm 5 +#define SYS_ID_AA64DFR0_EL1_Op2 0 + +#define ID_AA64DFR0_EL1_HPMN0 GENMASK(63, 60) +#define ID_AA64DFR0_EL1_HPMN0_MASK GENMASK(63, 60) +#define ID_AA64DFR0_EL1_HPMN0_SHIFT 60 +#define ID_AA64DFR0_EL1_HPMN0_WIDTH 4 +#define ID_AA64DFR0_EL1_HPMN0_UNPREDICTABLE UL(0b0000) +#define ID_AA64DFR0_EL1_HPMN0_DEF UL(0b0001) + +#define ID_AA64DFR0_EL1_BRBE GENMASK(55, 52) +#define ID_AA64DFR0_EL1_BRBE_MASK GENMASK(55, 52) +#define ID_AA64DFR0_EL1_BRBE_SHIFT 52 +#define ID_AA64DFR0_EL1_BRBE_WIDTH 4 +#define ID_AA64DFR0_EL1_BRBE_NI UL(0b0000) +#define ID_AA64DFR0_EL1_BRBE_IMP UL(0b0001) +#define ID_AA64DFR0_EL1_BRBE_BRBE_V1P1 UL(0b0010) + +#define ID_AA64DFR0_EL1_MTPMU GENMASK(51, 48) +#define ID_AA64DFR0_EL1_MTPMU_MASK GENMASK(51, 48) +#define ID_AA64DFR0_EL1_MTPMU_SHIFT 48 +#define ID_AA64DFR0_EL1_MTPMU_WIDTH 4 +#define ID_AA64DFR0_EL1_MTPMU_NI_IMPDEF UL(0b0000) +#define ID_AA64DFR0_EL1_MTPMU_IMP UL(0b0001) +#define ID_AA64DFR0_EL1_MTPMU_NI UL(0b1111) + +#define ID_AA64DFR0_EL1_TraceBuffer GENMASK(47, 44) +#define ID_AA64DFR0_EL1_TraceBuffer_MASK GENMASK(47, 44) +#define ID_AA64DFR0_EL1_TraceBuffer_SHIFT 44 +#define ID_AA64DFR0_EL1_TraceBuffer_WIDTH 4 +#define ID_AA64DFR0_EL1_TraceBuffer_NI UL(0b0000) +#define ID_AA64DFR0_EL1_TraceBuffer_IMP UL(0b0001) + +#define ID_AA64DFR0_EL1_TraceFilt GENMASK(43, 40) +#define ID_AA64DFR0_EL1_TraceFilt_MASK GENMASK(43, 40) +#define ID_AA64DFR0_EL1_TraceFilt_SHIFT 40 +#define ID_AA64DFR0_EL1_TraceFilt_WIDTH 4 +#define ID_AA64DFR0_EL1_TraceFilt_NI UL(0b0000) +#define ID_AA64DFR0_EL1_TraceFilt_IMP UL(0b0001) + +#define ID_AA64DFR0_EL1_DoubleLock GENMASK(39, 36) +#define ID_AA64DFR0_EL1_DoubleLock_MASK GENMASK(39, 36) +#define ID_AA64DFR0_EL1_DoubleLock_SHIFT 36 +#define ID_AA64DFR0_EL1_DoubleLock_WIDTH 4 +#define ID_AA64DFR0_EL1_DoubleLock_IMP UL(0b0000) +#define ID_AA64DFR0_EL1_DoubleLock_NI UL(0b1111) + +#define ID_AA64DFR0_EL1_PMSVer GENMASK(35, 32) +#define ID_AA64DFR0_EL1_PMSVer_MASK GENMASK(35, 32) +#define ID_AA64DFR0_EL1_PMSVer_SHIFT 32 +#define ID_AA64DFR0_EL1_PMSVer_WIDTH 4 +#define ID_AA64DFR0_EL1_PMSVer_NI UL(0b0000) +#define ID_AA64DFR0_EL1_PMSVer_IMP UL(0b0001) +#define ID_AA64DFR0_EL1_PMSVer_V1P1 UL(0b0010) +#define ID_AA64DFR0_EL1_PMSVer_V1P2 UL(0b0011) +#define ID_AA64DFR0_EL1_PMSVer_V1P3 UL(0b0100) + +#define ID_AA64DFR0_EL1_CTX_CMPs GENMASK(31, 28) +#define ID_AA64DFR0_EL1_CTX_CMPs_MASK GENMASK(31, 28) +#define ID_AA64DFR0_EL1_CTX_CMPs_SHIFT 28 +#define ID_AA64DFR0_EL1_CTX_CMPs_WIDTH 4 + +#define ID_AA64DFR0_EL1_WRPs GENMASK(23, 20) +#define ID_AA64DFR0_EL1_WRPs_MASK GENMASK(23, 20) +#define ID_AA64DFR0_EL1_WRPs_SHIFT 20 +#define ID_AA64DFR0_EL1_WRPs_WIDTH 4 + +#define ID_AA64DFR0_EL1_BRPs GENMASK(15, 12) +#define ID_AA64DFR0_EL1_BRPs_MASK GENMASK(15, 12) +#define ID_AA64DFR0_EL1_BRPs_SHIFT 12 +#define ID_AA64DFR0_EL1_BRPs_WIDTH 4 + +#define ID_AA64DFR0_EL1_PMUVer GENMASK(11, 8) +#define ID_AA64DFR0_EL1_PMUVer_MASK GENMASK(11, 8) +#define ID_AA64DFR0_EL1_PMUVer_SHIFT 8 +#define ID_AA64DFR0_EL1_PMUVer_WIDTH 4 +#define ID_AA64DFR0_EL1_PMUVer_NI UL(0b0000) +#define ID_AA64DFR0_EL1_PMUVer_IMP UL(0b0001) +#define ID_AA64DFR0_EL1_PMUVer_V3P1 UL(0b0100) +#define ID_AA64DFR0_EL1_PMUVer_V3P4 UL(0b0101) +#define ID_AA64DFR0_EL1_PMUVer_V3P5 UL(0b0110) +#define ID_AA64DFR0_EL1_PMUVer_V3P7 UL(0b0111) +#define ID_AA64DFR0_EL1_PMUVer_V3P8 UL(0b1000) +#define ID_AA64DFR0_EL1_PMUVer_IMP_DEF UL(0b1111) + +#define ID_AA64DFR0_EL1_TraceVer GENMASK(7, 4) +#define ID_AA64DFR0_EL1_TraceVer_MASK GENMASK(7, 4) +#define ID_AA64DFR0_EL1_TraceVer_SHIFT 4 +#define ID_AA64DFR0_EL1_TraceVer_WIDTH 4 +#define ID_AA64DFR0_EL1_TraceVer_NI UL(0b0000) +#define ID_AA64DFR0_EL1_TraceVer_IMP UL(0b0001) + +#define ID_AA64DFR0_EL1_DebugVer GENMASK(3, 0) +#define ID_AA64DFR0_EL1_DebugVer_MASK GENMASK(3, 0) +#define ID_AA64DFR0_EL1_DebugVer_SHIFT 0 +#define ID_AA64DFR0_EL1_DebugVer_WIDTH 4 +#define ID_AA64DFR0_EL1_DebugVer_IMP UL(0b0110) +#define ID_AA64DFR0_EL1_DebugVer_VHE UL(0b0111) +#define ID_AA64DFR0_EL1_DebugVer_V8P2 UL(0b1000) +#define ID_AA64DFR0_EL1_DebugVer_V8P4 UL(0b1001) +#define ID_AA64DFR0_EL1_DebugVer_V8P8 UL(0b1010) + +#define ID_AA64DFR0_EL1_RES0 (UL(0) | GENMASK_ULL(59, 56) | GENMASK_ULL(27, 24) | GENMASK_ULL(19, 16)) +#define ID_AA64DFR0_EL1_RES1 (UL(0)) + +#define REG_ID_AA64DFR1_EL1 S3_0_C0_C5_1 +#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) +#define SYS_ID_AA64DFR1_EL1_Op0 3 +#define SYS_ID_AA64DFR1_EL1_Op1 0 +#define SYS_ID_AA64DFR1_EL1_CRn 0 +#define SYS_ID_AA64DFR1_EL1_CRm 5 +#define SYS_ID_AA64DFR1_EL1_Op2 1 + +#define ID_AA64DFR1_EL1_RES0 (UL(0) | GENMASK_ULL(63, 0)) +#define ID_AA64DFR1_EL1_RES1 (UL(0)) + +#define REG_ID_AA64AFR0_EL1 S3_0_C0_C5_4 +#define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) +#define SYS_ID_AA64AFR0_EL1_Op0 3 +#define SYS_ID_AA64AFR0_EL1_Op1 0 +#define SYS_ID_AA64AFR0_EL1_CRn 0 +#define SYS_ID_AA64AFR0_EL1_CRm 5 +#define SYS_ID_AA64AFR0_EL1_Op2 4 + +#define ID_AA64AFR0_EL1_IMPDEF7 GENMASK(31, 28) +#define ID_AA64AFR0_EL1_IMPDEF7_MASK GENMASK(31, 28) +#define ID_AA64AFR0_EL1_IMPDEF7_SHIFT 28 +#define ID_AA64AFR0_EL1_IMPDEF7_WIDTH 4 + +#define ID_AA64AFR0_EL1_IMPDEF6 GENMASK(27, 24) +#define ID_AA64AFR0_EL1_IMPDEF6_MASK GENMASK(27, 24) +#define ID_AA64AFR0_EL1_IMPDEF6_SHIFT 24 +#define ID_AA64AFR0_EL1_IMPDEF6_WIDTH 4 + +#define ID_AA64AFR0_EL1_IMPDEF5 GENMASK(23, 20) +#define ID_AA64AFR0_EL1_IMPDEF5_MASK GENMASK(23, 20) +#define ID_AA64AFR0_EL1_IMPDEF5_SHIFT 20 +#define ID_AA64AFR0_EL1_IMPDEF5_WIDTH 4 + +#define ID_AA64AFR0_EL1_IMPDEF4 GENMASK(19, 16) +#define ID_AA64AFR0_EL1_IMPDEF4_MASK GENMASK(19, 16) +#define ID_AA64AFR0_EL1_IMPDEF4_SHIFT 16 +#define ID_AA64AFR0_EL1_IMPDEF4_WIDTH 4 + +#define ID_AA64AFR0_EL1_IMPDEF3 GENMASK(15, 12) +#define ID_AA64AFR0_EL1_IMPDEF3_MASK GENMASK(15, 12) +#define ID_AA64AFR0_EL1_IMPDEF3_SHIFT 12 +#define ID_AA64AFR0_EL1_IMPDEF3_WIDTH 4 + +#define ID_AA64AFR0_EL1_IMPDEF2 GENMASK(11, 8) +#define ID_AA64AFR0_EL1_IMPDEF2_MASK GENMASK(11, 8) +#define ID_AA64AFR0_EL1_IMPDEF2_SHIFT 8 +#define ID_AA64AFR0_EL1_IMPDEF2_WIDTH 4 + +#define ID_AA64AFR0_EL1_IMPDEF1 GENMASK(7, 4) +#define ID_AA64AFR0_EL1_IMPDEF1_MASK GENMASK(7, 4) +#define ID_AA64AFR0_EL1_IMPDEF1_SHIFT 4 +#define ID_AA64AFR0_EL1_IMPDEF1_WIDTH 4 + +#define ID_AA64AFR0_EL1_IMPDEF0 GENMASK(3, 0) +#define ID_AA64AFR0_EL1_IMPDEF0_MASK GENMASK(3, 0) +#define ID_AA64AFR0_EL1_IMPDEF0_SHIFT 0 +#define ID_AA64AFR0_EL1_IMPDEF0_WIDTH 4 + +#define ID_AA64AFR0_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32)) +#define ID_AA64AFR0_EL1_RES1 (UL(0)) + +#define REG_ID_AA64AFR1_EL1 S3_0_C0_C5_5 +#define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) +#define SYS_ID_AA64AFR1_EL1_Op0 3 +#define SYS_ID_AA64AFR1_EL1_Op1 0 +#define SYS_ID_AA64AFR1_EL1_CRn 0 +#define SYS_ID_AA64AFR1_EL1_CRm 5 +#define SYS_ID_AA64AFR1_EL1_Op2 5 + +#define ID_AA64AFR1_EL1_RES0 (UL(0) | GENMASK_ULL(63, 0)) +#define ID_AA64AFR1_EL1_RES1 (UL(0)) + +#define REG_ID_AA64ISAR0_EL1 S3_0_C0_C6_0 +#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) +#define SYS_ID_AA64ISAR0_EL1_Op0 3 +#define SYS_ID_AA64ISAR0_EL1_Op1 0 +#define SYS_ID_AA64ISAR0_EL1_CRn 0 +#define SYS_ID_AA64ISAR0_EL1_CRm 6 +#define SYS_ID_AA64ISAR0_EL1_Op2 0 + +#define ID_AA64ISAR0_EL1_RNDR GENMASK(63, 60) +#define ID_AA64ISAR0_EL1_RNDR_MASK GENMASK(63, 60) +#define ID_AA64ISAR0_EL1_RNDR_SHIFT 60 +#define ID_AA64ISAR0_EL1_RNDR_WIDTH 4 +#define ID_AA64ISAR0_EL1_RNDR_NI UL(0b0000) +#define ID_AA64ISAR0_EL1_RNDR_IMP UL(0b0001) + +#define ID_AA64ISAR0_EL1_TLB GENMASK(59, 56) +#define ID_AA64ISAR0_EL1_TLB_MASK GENMASK(59, 56) +#define ID_AA64ISAR0_EL1_TLB_SHIFT 56 +#define ID_AA64ISAR0_EL1_TLB_WIDTH 4 +#define ID_AA64ISAR0_EL1_TLB_NI UL(0b0000) +#define ID_AA64ISAR0_EL1_TLB_OS UL(0b0001) +#define ID_AA64ISAR0_EL1_TLB_RANGE UL(0b0010) + +#define ID_AA64ISAR0_EL1_TS GENMASK(55, 52) +#define ID_AA64ISAR0_EL1_TS_MASK GENMASK(55, 52) +#define ID_AA64ISAR0_EL1_TS_SHIFT 52 +#define ID_AA64ISAR0_EL1_TS_WIDTH 4 +#define ID_AA64ISAR0_EL1_TS_NI UL(0b0000) +#define ID_AA64ISAR0_EL1_TS_FLAGM UL(0b0001) +#define ID_AA64ISAR0_EL1_TS_FLAGM2 UL(0b0010) + +#define ID_AA64ISAR0_EL1_FHM GENMASK(51, 48) +#define ID_AA64ISAR0_EL1_FHM_MASK GENMASK(51, 48) +#define ID_AA64ISAR0_EL1_FHM_SHIFT 48 +#define ID_AA64ISAR0_EL1_FHM_WIDTH 4 +#define ID_AA64ISAR0_EL1_FHM_NI UL(0b0000) +#define ID_AA64ISAR0_EL1_FHM_IMP UL(0b0001) + +#define ID_AA64ISAR0_EL1_DP GENMASK(47, 44) +#define ID_AA64ISAR0_EL1_DP_MASK GENMASK(47, 44) +#define ID_AA64ISAR0_EL1_DP_SHIFT 44 +#define ID_AA64ISAR0_EL1_DP_WIDTH 4 +#define ID_AA64ISAR0_EL1_DP_NI UL(0b0000) +#define ID_AA64ISAR0_EL1_DP_IMP UL(0b0001) + +#define ID_AA64ISAR0_EL1_SM4 GENMASK(43, 40) +#define ID_AA64ISAR0_EL1_SM4_MASK GENMASK(43, 40) +#define ID_AA64ISAR0_EL1_SM4_SHIFT 40 +#define ID_AA64ISAR0_EL1_SM4_WIDTH 4 +#define ID_AA64ISAR0_EL1_SM4_NI UL(0b0000) +#define ID_AA64ISAR0_EL1_SM4_IMP UL(0b0001) + +#define ID_AA64ISAR0_EL1_SM3 GENMASK(39, 36) +#define ID_AA64ISAR0_EL1_SM3_MASK GENMASK(39, 36) +#define ID_AA64ISAR0_EL1_SM3_SHIFT 36 +#define ID_AA64ISAR0_EL1_SM3_WIDTH 4 +#define ID_AA64ISAR0_EL1_SM3_NI UL(0b0000) +#define ID_AA64ISAR0_EL1_SM3_IMP UL(0b0001) + +#define ID_AA64ISAR0_EL1_SHA3 GENMASK(35, 32) +#define ID_AA64ISAR0_EL1_SHA3_MASK GENMASK(35, 32) +#define ID_AA64ISAR0_EL1_SHA3_SHIFT 32 +#define ID_AA64ISAR0_EL1_SHA3_WIDTH 4 +#define ID_AA64ISAR0_EL1_SHA3_NI UL(0b0000) +#define ID_AA64ISAR0_EL1_SHA3_IMP UL(0b0001) + +#define ID_AA64ISAR0_EL1_RDM GENMASK(31, 28) +#define ID_AA64ISAR0_EL1_RDM_MASK GENMASK(31, 28) +#define ID_AA64ISAR0_EL1_RDM_SHIFT 28 +#define ID_AA64ISAR0_EL1_RDM_WIDTH 4 +#define ID_AA64ISAR0_EL1_RDM_NI UL(0b0000) +#define ID_AA64ISAR0_EL1_RDM_IMP UL(0b0001) + +#define ID_AA64ISAR0_EL1_TME GENMASK(27, 24) +#define ID_AA64ISAR0_EL1_TME_MASK GENMASK(27, 24) +#define ID_AA64ISAR0_EL1_TME_SHIFT 24 +#define ID_AA64ISAR0_EL1_TME_WIDTH 4 +#define ID_AA64ISAR0_EL1_TME_NI UL(0b0000) +#define ID_AA64ISAR0_EL1_TME_IMP UL(0b0001) + +#define ID_AA64ISAR0_EL1_ATOMIC GENMASK(23, 20) +#define ID_AA64ISAR0_EL1_ATOMIC_MASK GENMASK(23, 20) +#define ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20 +#define ID_AA64ISAR0_EL1_ATOMIC_WIDTH 4 +#define ID_AA64ISAR0_EL1_ATOMIC_NI UL(0b0000) +#define ID_AA64ISAR0_EL1_ATOMIC_IMP UL(0b0010) + +#define ID_AA64ISAR0_EL1_CRC32 GENMASK(19, 16) +#define ID_AA64ISAR0_EL1_CRC32_MASK GENMASK(19, 16) +#define ID_AA64ISAR0_EL1_CRC32_SHIFT 16 +#define ID_AA64ISAR0_EL1_CRC32_WIDTH 4 +#define ID_AA64ISAR0_EL1_CRC32_NI UL(0b0000) +#define ID_AA64ISAR0_EL1_CRC32_IMP UL(0b0001) + +#define ID_AA64ISAR0_EL1_SHA2 GENMASK(15, 12) +#define ID_AA64ISAR0_EL1_SHA2_MASK GENMASK(15, 12) +#define ID_AA64ISAR0_EL1_SHA2_SHIFT 12 +#define ID_AA64ISAR0_EL1_SHA2_WIDTH 4 +#define ID_AA64ISAR0_EL1_SHA2_NI UL(0b0000) +#define ID_AA64ISAR0_EL1_SHA2_SHA256 UL(0b0001) +#define ID_AA64ISAR0_EL1_SHA2_SHA512 UL(0b0010) + +#define ID_AA64ISAR0_EL1_SHA1 GENMASK(11, 8) +#define ID_AA64ISAR0_EL1_SHA1_MASK GENMASK(11, 8) +#define ID_AA64ISAR0_EL1_SHA1_SHIFT 8 +#define ID_AA64ISAR0_EL1_SHA1_WIDTH 4 +#define ID_AA64ISAR0_EL1_SHA1_NI UL(0b0000) +#define ID_AA64ISAR0_EL1_SHA1_IMP UL(0b0001) + +#define ID_AA64ISAR0_EL1_AES GENMASK(7, 4) +#define ID_AA64ISAR0_EL1_AES_MASK GENMASK(7, 4) +#define ID_AA64ISAR0_EL1_AES_SHIFT 4 +#define ID_AA64ISAR0_EL1_AES_WIDTH 4 +#define ID_AA64ISAR0_EL1_AES_NI UL(0b0000) +#define ID_AA64ISAR0_EL1_AES_AES UL(0b0001) +#define ID_AA64ISAR0_EL1_AES_PMULL UL(0b0010) + +#define ID_AA64ISAR0_EL1_RES0 (UL(0) | GENMASK_ULL(3, 0)) +#define ID_AA64ISAR0_EL1_RES1 (UL(0)) + +#define REG_ID_AA64ISAR1_EL1 S3_0_C0_C6_1 +#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) +#define SYS_ID_AA64ISAR1_EL1_Op0 3 +#define SYS_ID_AA64ISAR1_EL1_Op1 0 +#define SYS_ID_AA64ISAR1_EL1_CRn 0 +#define SYS_ID_AA64ISAR1_EL1_CRm 6 +#define SYS_ID_AA64ISAR1_EL1_Op2 1 + +#define ID_AA64ISAR1_EL1_LS64 GENMASK(63, 60) +#define ID_AA64ISAR1_EL1_LS64_MASK GENMASK(63, 60) +#define ID_AA64ISAR1_EL1_LS64_SHIFT 60 +#define ID_AA64ISAR1_EL1_LS64_WIDTH 4 +#define ID_AA64ISAR1_EL1_LS64_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_LS64_LS64 UL(0b0001) +#define ID_AA64ISAR1_EL1_LS64_LS64_V UL(0b0010) +#define ID_AA64ISAR1_EL1_LS64_LS64_ACCDATA UL(0b0011) + +#define ID_AA64ISAR1_EL1_XS GENMASK(59, 56) +#define ID_AA64ISAR1_EL1_XS_MASK GENMASK(59, 56) +#define ID_AA64ISAR1_EL1_XS_SHIFT 56 +#define ID_AA64ISAR1_EL1_XS_WIDTH 4 +#define ID_AA64ISAR1_EL1_XS_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_XS_IMP UL(0b0001) + +#define ID_AA64ISAR1_EL1_I8MM GENMASK(55, 52) +#define ID_AA64ISAR1_EL1_I8MM_MASK GENMASK(55, 52) +#define ID_AA64ISAR1_EL1_I8MM_SHIFT 52 +#define ID_AA64ISAR1_EL1_I8MM_WIDTH 4 +#define ID_AA64ISAR1_EL1_I8MM_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_I8MM_IMP UL(0b0001) + +#define ID_AA64ISAR1_EL1_DGH GENMASK(51, 48) +#define ID_AA64ISAR1_EL1_DGH_MASK GENMASK(51, 48) +#define ID_AA64ISAR1_EL1_DGH_SHIFT 48 +#define ID_AA64ISAR1_EL1_DGH_WIDTH 4 +#define ID_AA64ISAR1_EL1_DGH_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_DGH_IMP UL(0b0001) + +#define ID_AA64ISAR1_EL1_BF16 GENMASK(47, 44) +#define ID_AA64ISAR1_EL1_BF16_MASK GENMASK(47, 44) +#define ID_AA64ISAR1_EL1_BF16_SHIFT 44 +#define ID_AA64ISAR1_EL1_BF16_WIDTH 4 +#define ID_AA64ISAR1_EL1_BF16_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_BF16_IMP UL(0b0001) +#define ID_AA64ISAR1_EL1_BF16_EBF16 UL(0b0010) + +#define ID_AA64ISAR1_EL1_SPECRES GENMASK(43, 40) +#define ID_AA64ISAR1_EL1_SPECRES_MASK GENMASK(43, 40) +#define ID_AA64ISAR1_EL1_SPECRES_SHIFT 40 +#define ID_AA64ISAR1_EL1_SPECRES_WIDTH 4 +#define ID_AA64ISAR1_EL1_SPECRES_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_SPECRES_IMP UL(0b0001) + +#define ID_AA64ISAR1_EL1_SB GENMASK(39, 36) +#define ID_AA64ISAR1_EL1_SB_MASK GENMASK(39, 36) +#define ID_AA64ISAR1_EL1_SB_SHIFT 36 +#define ID_AA64ISAR1_EL1_SB_WIDTH 4 +#define ID_AA64ISAR1_EL1_SB_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_SB_IMP UL(0b0001) + +#define ID_AA64ISAR1_EL1_FRINTTS GENMASK(35, 32) +#define ID_AA64ISAR1_EL1_FRINTTS_MASK GENMASK(35, 32) +#define ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32 +#define ID_AA64ISAR1_EL1_FRINTTS_WIDTH 4 +#define ID_AA64ISAR1_EL1_FRINTTS_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_FRINTTS_IMP UL(0b0001) + +#define ID_AA64ISAR1_EL1_GPI GENMASK(31, 28) +#define ID_AA64ISAR1_EL1_GPI_MASK GENMASK(31, 28) +#define ID_AA64ISAR1_EL1_GPI_SHIFT 28 +#define ID_AA64ISAR1_EL1_GPI_WIDTH 4 +#define ID_AA64ISAR1_EL1_GPI_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_GPI_IMP UL(0b0001) + +#define ID_AA64ISAR1_EL1_GPA GENMASK(27, 24) +#define ID_AA64ISAR1_EL1_GPA_MASK GENMASK(27, 24) +#define ID_AA64ISAR1_EL1_GPA_SHIFT 24 +#define ID_AA64ISAR1_EL1_GPA_WIDTH 4 +#define ID_AA64ISAR1_EL1_GPA_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_GPA_IMP UL(0b0001) + +#define ID_AA64ISAR1_EL1_LRCPC GENMASK(23, 20) +#define ID_AA64ISAR1_EL1_LRCPC_MASK GENMASK(23, 20) +#define ID_AA64ISAR1_EL1_LRCPC_SHIFT 20 +#define ID_AA64ISAR1_EL1_LRCPC_WIDTH 4 +#define ID_AA64ISAR1_EL1_LRCPC_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_LRCPC_IMP UL(0b0001) +#define ID_AA64ISAR1_EL1_LRCPC_LRCPC2 UL(0b0010) + +#define ID_AA64ISAR1_EL1_FCMA GENMASK(19, 16) +#define ID_AA64ISAR1_EL1_FCMA_MASK GENMASK(19, 16) +#define ID_AA64ISAR1_EL1_FCMA_SHIFT 16 +#define ID_AA64ISAR1_EL1_FCMA_WIDTH 4 +#define ID_AA64ISAR1_EL1_FCMA_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_FCMA_IMP UL(0b0001) + +#define ID_AA64ISAR1_EL1_JSCVT GENMASK(15, 12) +#define ID_AA64ISAR1_EL1_JSCVT_MASK GENMASK(15, 12) +#define ID_AA64ISAR1_EL1_JSCVT_SHIFT 12 +#define ID_AA64ISAR1_EL1_JSCVT_WIDTH 4 +#define ID_AA64ISAR1_EL1_JSCVT_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_JSCVT_IMP UL(0b0001) + +#define ID_AA64ISAR1_EL1_API GENMASK(11, 8) +#define ID_AA64ISAR1_EL1_API_MASK GENMASK(11, 8) +#define ID_AA64ISAR1_EL1_API_SHIFT 8 +#define ID_AA64ISAR1_EL1_API_WIDTH 4 +#define ID_AA64ISAR1_EL1_API_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_API_PAuth UL(0b0001) +#define ID_AA64ISAR1_EL1_API_EPAC UL(0b0010) +#define ID_AA64ISAR1_EL1_API_PAuth2 UL(0b0011) +#define ID_AA64ISAR1_EL1_API_FPAC UL(0b0100) +#define ID_AA64ISAR1_EL1_API_FPACCOMBINE UL(0b0101) + +#define ID_AA64ISAR1_EL1_APA GENMASK(7, 4) +#define ID_AA64ISAR1_EL1_APA_MASK GENMASK(7, 4) +#define ID_AA64ISAR1_EL1_APA_SHIFT 4 +#define ID_AA64ISAR1_EL1_APA_WIDTH 4 +#define ID_AA64ISAR1_EL1_APA_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_APA_PAuth UL(0b0001) +#define ID_AA64ISAR1_EL1_APA_EPAC UL(0b0010) +#define ID_AA64ISAR1_EL1_APA_PAuth2 UL(0b0011) +#define ID_AA64ISAR1_EL1_APA_FPAC UL(0b0100) +#define ID_AA64ISAR1_EL1_APA_FPACCOMBINE UL(0b0101) + +#define ID_AA64ISAR1_EL1_DPB GENMASK(3, 0) +#define ID_AA64ISAR1_EL1_DPB_MASK GENMASK(3, 0) +#define ID_AA64ISAR1_EL1_DPB_SHIFT 0 +#define ID_AA64ISAR1_EL1_DPB_WIDTH 4 +#define ID_AA64ISAR1_EL1_DPB_NI UL(0b0000) +#define ID_AA64ISAR1_EL1_DPB_IMP UL(0b0001) +#define ID_AA64ISAR1_EL1_DPB_DPB2 UL(0b0010) + +#define ID_AA64ISAR1_EL1_RES0 (UL(0)) +#define ID_AA64ISAR1_EL1_RES1 (UL(0)) + +#define REG_ID_AA64ISAR2_EL1 S3_0_C0_C6_2 +#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) +#define SYS_ID_AA64ISAR2_EL1_Op0 3 +#define SYS_ID_AA64ISAR2_EL1_Op1 0 +#define SYS_ID_AA64ISAR2_EL1_CRn 0 +#define SYS_ID_AA64ISAR2_EL1_CRm 6 +#define SYS_ID_AA64ISAR2_EL1_Op2 2 + +#define ID_AA64ISAR2_EL1_CLRBHB GENMASK(31, 28) +#define ID_AA64ISAR2_EL1_CLRBHB_MASK GENMASK(31, 28) +#define ID_AA64ISAR2_EL1_CLRBHB_SHIFT 28 +#define ID_AA64ISAR2_EL1_CLRBHB_WIDTH 4 +#define ID_AA64ISAR2_EL1_CLRBHB_NI UL(0b0000) +#define ID_AA64ISAR2_EL1_CLRBHB_IMP UL(0b0001) + +#define ID_AA64ISAR2_EL1_PAC_frac GENMASK(27, 24) +#define ID_AA64ISAR2_EL1_PAC_frac_MASK GENMASK(27, 24) +#define ID_AA64ISAR2_EL1_PAC_frac_SHIFT 24 +#define ID_AA64ISAR2_EL1_PAC_frac_WIDTH 4 +#define ID_AA64ISAR2_EL1_PAC_frac_NI UL(0b0000) +#define ID_AA64ISAR2_EL1_PAC_frac_IMP UL(0b0001) + +#define ID_AA64ISAR2_EL1_BC GENMASK(23, 20) +#define ID_AA64ISAR2_EL1_BC_MASK GENMASK(23, 20) +#define ID_AA64ISAR2_EL1_BC_SHIFT 20 +#define ID_AA64ISAR2_EL1_BC_WIDTH 4 +#define ID_AA64ISAR2_EL1_BC_NI UL(0b0000) +#define ID_AA64ISAR2_EL1_BC_IMP UL(0b0001) + +#define ID_AA64ISAR2_EL1_MOPS GENMASK(19, 16) +#define ID_AA64ISAR2_EL1_MOPS_MASK GENMASK(19, 16) +#define ID_AA64ISAR2_EL1_MOPS_SHIFT 16 +#define ID_AA64ISAR2_EL1_MOPS_WIDTH 4 +#define ID_AA64ISAR2_EL1_MOPS_NI UL(0b0000) +#define ID_AA64ISAR2_EL1_MOPS_IMP UL(0b0001) + +#define ID_AA64ISAR2_EL1_APA3 GENMASK(15, 12) +#define ID_AA64ISAR2_EL1_APA3_MASK GENMASK(15, 12) +#define ID_AA64ISAR2_EL1_APA3_SHIFT 12 +#define ID_AA64ISAR2_EL1_APA3_WIDTH 4 +#define ID_AA64ISAR2_EL1_APA3_NI UL(0b0000) +#define ID_AA64ISAR2_EL1_APA3_PAuth UL(0b0001) +#define ID_AA64ISAR2_EL1_APA3_EPAC UL(0b0010) +#define ID_AA64ISAR2_EL1_APA3_PAuth2 UL(0b0011) +#define ID_AA64ISAR2_EL1_APA3_FPAC UL(0b0100) +#define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE UL(0b0101) + +#define ID_AA64ISAR2_EL1_GPA3 GENMASK(11, 8) +#define ID_AA64ISAR2_EL1_GPA3_MASK GENMASK(11, 8) +#define ID_AA64ISAR2_EL1_GPA3_SHIFT 8 +#define ID_AA64ISAR2_EL1_GPA3_WIDTH 4 +#define ID_AA64ISAR2_EL1_GPA3_NI UL(0b0000) +#define ID_AA64ISAR2_EL1_GPA3_IMP UL(0b0001) + +#define ID_AA64ISAR2_EL1_RPRES GENMASK(7, 4) +#define ID_AA64ISAR2_EL1_RPRES_MASK GENMASK(7, 4) +#define ID_AA64ISAR2_EL1_RPRES_SHIFT 4 +#define ID_AA64ISAR2_EL1_RPRES_WIDTH 4 +#define ID_AA64ISAR2_EL1_RPRES_NI UL(0b0000) +#define ID_AA64ISAR2_EL1_RPRES_IMP UL(0b0001) + +#define ID_AA64ISAR2_EL1_WFxT GENMASK(3, 0) +#define ID_AA64ISAR2_EL1_WFxT_MASK GENMASK(3, 0) +#define ID_AA64ISAR2_EL1_WFxT_SHIFT 0 +#define ID_AA64ISAR2_EL1_WFxT_WIDTH 4 +#define ID_AA64ISAR2_EL1_WFxT_NI UL(0b0000) +#define ID_AA64ISAR2_EL1_WFxT_IMP UL(0b0010) + +#define ID_AA64ISAR2_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32)) +#define ID_AA64ISAR2_EL1_RES1 (UL(0)) + +#define REG_ID_AA64MMFR0_EL1 S3_0_C0_C7_0 +#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) +#define SYS_ID_AA64MMFR0_EL1_Op0 3 +#define SYS_ID_AA64MMFR0_EL1_Op1 0 +#define SYS_ID_AA64MMFR0_EL1_CRn 0 +#define SYS_ID_AA64MMFR0_EL1_CRm 7 +#define SYS_ID_AA64MMFR0_EL1_Op2 0 + +#define ID_AA64MMFR0_EL1_ECV GENMASK(63, 60) +#define ID_AA64MMFR0_EL1_ECV_MASK GENMASK(63, 60) +#define ID_AA64MMFR0_EL1_ECV_SHIFT 60 +#define ID_AA64MMFR0_EL1_ECV_WIDTH 4 +#define ID_AA64MMFR0_EL1_ECV_NI UL(0b0000) +#define ID_AA64MMFR0_EL1_ECV_IMP UL(0b0001) +#define ID_AA64MMFR0_EL1_ECV_CNTPOFF UL(0b0010) + +#define ID_AA64MMFR0_EL1_FGT GENMASK(59, 56) +#define ID_AA64MMFR0_EL1_FGT_MASK GENMASK(59, 56) +#define ID_AA64MMFR0_EL1_FGT_SHIFT 56 +#define ID_AA64MMFR0_EL1_FGT_WIDTH 4 +#define ID_AA64MMFR0_EL1_FGT_NI UL(0b0000) +#define ID_AA64MMFR0_EL1_FGT_IMP UL(0b0001) + +#define ID_AA64MMFR0_EL1_EXS GENMASK(47, 44) +#define ID_AA64MMFR0_EL1_EXS_MASK GENMASK(47, 44) +#define ID_AA64MMFR0_EL1_EXS_SHIFT 44 +#define ID_AA64MMFR0_EL1_EXS_WIDTH 4 +#define ID_AA64MMFR0_EL1_EXS_NI UL(0b0000) +#define ID_AA64MMFR0_EL1_EXS_IMP UL(0b0001) + +#define ID_AA64MMFR0_EL1_TGRAN4_2 GENMASK(43, 40) +#define ID_AA64MMFR0_EL1_TGRAN4_2_MASK GENMASK(43, 40) +#define ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40 +#define ID_AA64MMFR0_EL1_TGRAN4_2_WIDTH 4 +#define ID_AA64MMFR0_EL1_TGRAN4_2_TGRAN4 UL(0b0000) +#define ID_AA64MMFR0_EL1_TGRAN4_2_NI UL(0b0001) +#define ID_AA64MMFR0_EL1_TGRAN4_2_IMP UL(0b0010) +#define ID_AA64MMFR0_EL1_TGRAN4_2_52_BIT UL(0b0011) + +#define ID_AA64MMFR0_EL1_TGRAN64_2 GENMASK(39, 36) +#define ID_AA64MMFR0_EL1_TGRAN64_2_MASK GENMASK(39, 36) +#define ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36 +#define ID_AA64MMFR0_EL1_TGRAN64_2_WIDTH 4 +#define ID_AA64MMFR0_EL1_TGRAN64_2_TGRAN64 UL(0b0000) +#define ID_AA64MMFR0_EL1_TGRAN64_2_NI UL(0b0001) +#define ID_AA64MMFR0_EL1_TGRAN64_2_IMP UL(0b0010) + +#define ID_AA64MMFR0_EL1_TGRAN16_2 GENMASK(35, 32) +#define ID_AA64MMFR0_EL1_TGRAN16_2_MASK GENMASK(35, 32) +#define ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32 +#define ID_AA64MMFR0_EL1_TGRAN16_2_WIDTH 4 +#define ID_AA64MMFR0_EL1_TGRAN16_2_TGRAN16 UL(0b0000) +#define ID_AA64MMFR0_EL1_TGRAN16_2_NI UL(0b0001) +#define ID_AA64MMFR0_EL1_TGRAN16_2_IMP UL(0b0010) +#define ID_AA64MMFR0_EL1_TGRAN16_2_52_BIT UL(0b0011) + +#define ID_AA64MMFR0_EL1_TGRAN4 GENMASK(31, 28) +#define ID_AA64MMFR0_EL1_TGRAN4_MASK GENMASK(31, 28) +#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28 +#define ID_AA64MMFR0_EL1_TGRAN4_WIDTH 4 +#define ID_AA64MMFR0_EL1_TGRAN4_IMP UL(0b0000) +#define ID_AA64MMFR0_EL1_TGRAN4_52_BIT UL(0b0001) +#define ID_AA64MMFR0_EL1_TGRAN4_NI UL(0b1111) + +#define ID_AA64MMFR0_EL1_TGRAN64 GENMASK(27, 24) +#define ID_AA64MMFR0_EL1_TGRAN64_MASK GENMASK(27, 24) +#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24 +#define ID_AA64MMFR0_EL1_TGRAN64_WIDTH 4 +#define ID_AA64MMFR0_EL1_TGRAN64_IMP UL(0b0000) +#define ID_AA64MMFR0_EL1_TGRAN64_NI UL(0b1111) + +#define ID_AA64MMFR0_EL1_TGRAN16 GENMASK(23, 20) +#define ID_AA64MMFR0_EL1_TGRAN16_MASK GENMASK(23, 20) +#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20 +#define ID_AA64MMFR0_EL1_TGRAN16_WIDTH 4 +#define ID_AA64MMFR0_EL1_TGRAN16_NI UL(0b0000) +#define ID_AA64MMFR0_EL1_TGRAN16_IMP UL(0b0001) +#define ID_AA64MMFR0_EL1_TGRAN16_52_BIT UL(0b0010) + +#define ID_AA64MMFR0_EL1_BIGENDEL0 GENMASK(19, 16) +#define ID_AA64MMFR0_EL1_BIGENDEL0_MASK GENMASK(19, 16) +#define ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16 +#define ID_AA64MMFR0_EL1_BIGENDEL0_WIDTH 4 +#define ID_AA64MMFR0_EL1_BIGENDEL0_NI UL(0b0000) +#define ID_AA64MMFR0_EL1_BIGENDEL0_IMP UL(0b0001) + +#define ID_AA64MMFR0_EL1_SNSMEM GENMASK(15, 12) +#define ID_AA64MMFR0_EL1_SNSMEM_MASK GENMASK(15, 12) +#define ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12 +#define ID_AA64MMFR0_EL1_SNSMEM_WIDTH 4 +#define ID_AA64MMFR0_EL1_SNSMEM_NI UL(0b0000) +#define ID_AA64MMFR0_EL1_SNSMEM_IMP UL(0b0001) + +#define ID_AA64MMFR0_EL1_BIGEND GENMASK(11, 8) +#define ID_AA64MMFR0_EL1_BIGEND_MASK GENMASK(11, 8) +#define ID_AA64MMFR0_EL1_BIGEND_SHIFT 8 +#define ID_AA64MMFR0_EL1_BIGEND_WIDTH 4 +#define ID_AA64MMFR0_EL1_BIGEND_NI UL(0b0000) +#define ID_AA64MMFR0_EL1_BIGEND_IMP UL(0b0001) + +#define ID_AA64MMFR0_EL1_ASIDBITS GENMASK(7, 4) +#define ID_AA64MMFR0_EL1_ASIDBITS_MASK GENMASK(7, 4) +#define ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4 +#define ID_AA64MMFR0_EL1_ASIDBITS_WIDTH 4 +#define ID_AA64MMFR0_EL1_ASIDBITS_8 UL(0b0000) +#define ID_AA64MMFR0_EL1_ASIDBITS_16 UL(0b0010) + +#define ID_AA64MMFR0_EL1_PARANGE GENMASK(3, 0) +#define ID_AA64MMFR0_EL1_PARANGE_MASK GENMASK(3, 0) +#define ID_AA64MMFR0_EL1_PARANGE_SHIFT 0 +#define ID_AA64MMFR0_EL1_PARANGE_WIDTH 4 +#define ID_AA64MMFR0_EL1_PARANGE_32 UL(0b0000) +#define ID_AA64MMFR0_EL1_PARANGE_36 UL(0b0001) +#define ID_AA64MMFR0_EL1_PARANGE_40 UL(0b0010) +#define ID_AA64MMFR0_EL1_PARANGE_42 UL(0b0011) +#define ID_AA64MMFR0_EL1_PARANGE_44 UL(0b0100) +#define ID_AA64MMFR0_EL1_PARANGE_48 UL(0b0101) +#define ID_AA64MMFR0_EL1_PARANGE_52 UL(0b0110) + +#define ID_AA64MMFR0_EL1_RES0 (UL(0) | GENMASK_ULL(55, 48)) +#define ID_AA64MMFR0_EL1_RES1 (UL(0)) + +#define REG_ID_AA64MMFR1_EL1 S3_0_C0_C7_1 +#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) +#define SYS_ID_AA64MMFR1_EL1_Op0 3 +#define SYS_ID_AA64MMFR1_EL1_Op1 0 +#define SYS_ID_AA64MMFR1_EL1_CRn 0 +#define SYS_ID_AA64MMFR1_EL1_CRm 7 +#define SYS_ID_AA64MMFR1_EL1_Op2 1 + +#define ID_AA64MMFR1_EL1_ECBHB GENMASK(63, 60) +#define ID_AA64MMFR1_EL1_ECBHB_MASK GENMASK(63, 60) +#define ID_AA64MMFR1_EL1_ECBHB_SHIFT 60 +#define ID_AA64MMFR1_EL1_ECBHB_WIDTH 4 +#define ID_AA64MMFR1_EL1_ECBHB_NI UL(0b0000) +#define ID_AA64MMFR1_EL1_ECBHB_IMP UL(0b0001) + +#define ID_AA64MMFR1_EL1_CMOW GENMASK(59, 56) +#define ID_AA64MMFR1_EL1_CMOW_MASK GENMASK(59, 56) +#define ID_AA64MMFR1_EL1_CMOW_SHIFT 56 +#define ID_AA64MMFR1_EL1_CMOW_WIDTH 4 +#define ID_AA64MMFR1_EL1_CMOW_NI UL(0b0000) +#define ID_AA64MMFR1_EL1_CMOW_IMP UL(0b0001) + +#define ID_AA64MMFR1_EL1_TIDCP1 GENMASK(55, 52) +#define ID_AA64MMFR1_EL1_TIDCP1_MASK GENMASK(55, 52) +#define ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52 +#define ID_AA64MMFR1_EL1_TIDCP1_WIDTH 4 +#define ID_AA64MMFR1_EL1_TIDCP1_NI UL(0b0000) +#define ID_AA64MMFR1_EL1_TIDCP1_IMP UL(0b0001) + +#define ID_AA64MMFR1_EL1_nTLBPA GENMASK(51, 48) +#define ID_AA64MMFR1_EL1_nTLBPA_MASK GENMASK(51, 48) +#define ID_AA64MMFR1_EL1_nTLBPA_SHIFT 48 +#define ID_AA64MMFR1_EL1_nTLBPA_WIDTH 4 +#define ID_AA64MMFR1_EL1_nTLBPA_NI UL(0b0000) +#define ID_AA64MMFR1_EL1_nTLBPA_IMP UL(0b0001) + +#define ID_AA64MMFR1_EL1_AFP GENMASK(47, 44) +#define ID_AA64MMFR1_EL1_AFP_MASK GENMASK(47, 44) +#define ID_AA64MMFR1_EL1_AFP_SHIFT 44 +#define ID_AA64MMFR1_EL1_AFP_WIDTH 4 +#define ID_AA64MMFR1_EL1_AFP_NI UL(0b0000) +#define ID_AA64MMFR1_EL1_AFP_IMP UL(0b0001) + +#define ID_AA64MMFR1_EL1_HCX GENMASK(43, 40) +#define ID_AA64MMFR1_EL1_HCX_MASK GENMASK(43, 40) +#define ID_AA64MMFR1_EL1_HCX_SHIFT 40 +#define ID_AA64MMFR1_EL1_HCX_WIDTH 4 +#define ID_AA64MMFR1_EL1_HCX_NI UL(0b0000) +#define ID_AA64MMFR1_EL1_HCX_IMP UL(0b0001) + +#define ID_AA64MMFR1_EL1_ETS GENMASK(39, 36) +#define ID_AA64MMFR1_EL1_ETS_MASK GENMASK(39, 36) +#define ID_AA64MMFR1_EL1_ETS_SHIFT 36 +#define ID_AA64MMFR1_EL1_ETS_WIDTH 4 +#define ID_AA64MMFR1_EL1_ETS_NI UL(0b0000) +#define ID_AA64MMFR1_EL1_ETS_IMP UL(0b0001) + +#define ID_AA64MMFR1_EL1_TWED GENMASK(35, 32) +#define ID_AA64MMFR1_EL1_TWED_MASK GENMASK(35, 32) +#define ID_AA64MMFR1_EL1_TWED_SHIFT 32 +#define ID_AA64MMFR1_EL1_TWED_WIDTH 4 +#define ID_AA64MMFR1_EL1_TWED_NI UL(0b0000) +#define ID_AA64MMFR1_EL1_TWED_IMP UL(0b0001) + +#define ID_AA64MMFR1_EL1_XNX GENMASK(31, 28) +#define ID_AA64MMFR1_EL1_XNX_MASK GENMASK(31, 28) +#define ID_AA64MMFR1_EL1_XNX_SHIFT 28 +#define ID_AA64MMFR1_EL1_XNX_WIDTH 4 +#define ID_AA64MMFR1_EL1_XNX_NI UL(0b0000) +#define ID_AA64MMFR1_EL1_XNX_IMP UL(0b0001) + +#define ID_AA64MMFR1_EL1_SpecSEI GENMASK(27, 24) +#define ID_AA64MMFR1_EL1_SpecSEI_MASK GENMASK(27, 24) +#define ID_AA64MMFR1_EL1_SpecSEI_SHIFT 24 +#define ID_AA64MMFR1_EL1_SpecSEI_WIDTH 4 +#define ID_AA64MMFR1_EL1_SpecSEI_NI UL(0b0000) +#define ID_AA64MMFR1_EL1_SpecSEI_IMP UL(0b0001) + +#define ID_AA64MMFR1_EL1_PAN GENMASK(23, 20) +#define ID_AA64MMFR1_EL1_PAN_MASK GENMASK(23, 20) +#define ID_AA64MMFR1_EL1_PAN_SHIFT 20 +#define ID_AA64MMFR1_EL1_PAN_WIDTH 4 +#define ID_AA64MMFR1_EL1_PAN_NI UL(0b0000) +#define ID_AA64MMFR1_EL1_PAN_IMP UL(0b0001) +#define ID_AA64MMFR1_EL1_PAN_PAN2 UL(0b0010) +#define ID_AA64MMFR1_EL1_PAN_PAN3 UL(0b0011) + +#define ID_AA64MMFR1_EL1_LO GENMASK(19, 16) +#define ID_AA64MMFR1_EL1_LO_MASK GENMASK(19, 16) +#define ID_AA64MMFR1_EL1_LO_SHIFT 16 +#define ID_AA64MMFR1_EL1_LO_WIDTH 4 +#define ID_AA64MMFR1_EL1_LO_NI UL(0b0000) +#define ID_AA64MMFR1_EL1_LO_IMP UL(0b0001) + +#define ID_AA64MMFR1_EL1_HPDS GENMASK(15, 12) +#define ID_AA64MMFR1_EL1_HPDS_MASK GENMASK(15, 12) +#define ID_AA64MMFR1_EL1_HPDS_SHIFT 12 +#define ID_AA64MMFR1_EL1_HPDS_WIDTH 4 +#define ID_AA64MMFR1_EL1_HPDS_NI UL(0b0000) +#define ID_AA64MMFR1_EL1_HPDS_IMP UL(0b0001) +#define ID_AA64MMFR1_EL1_HPDS_HPDS2 UL(0b0010) + +#define ID_AA64MMFR1_EL1_VH GENMASK(11, 8) +#define ID_AA64MMFR1_EL1_VH_MASK GENMASK(11, 8) +#define ID_AA64MMFR1_EL1_VH_SHIFT 8 +#define ID_AA64MMFR1_EL1_VH_WIDTH 4 +#define ID_AA64MMFR1_EL1_VH_NI UL(0b0000) +#define ID_AA64MMFR1_EL1_VH_IMP UL(0b0001) + +#define ID_AA64MMFR1_EL1_VMIDBits GENMASK(7, 4) +#define ID_AA64MMFR1_EL1_VMIDBits_MASK GENMASK(7, 4) +#define ID_AA64MMFR1_EL1_VMIDBits_SHIFT 4 +#define ID_AA64MMFR1_EL1_VMIDBits_WIDTH 4 +#define ID_AA64MMFR1_EL1_VMIDBits_8 UL(0b0000) +#define ID_AA64MMFR1_EL1_VMIDBits_16 UL(0b0010) + +#define ID_AA64MMFR1_EL1_HAFDBS GENMASK(3, 0) +#define ID_AA64MMFR1_EL1_HAFDBS_MASK GENMASK(3, 0) +#define ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0 +#define ID_AA64MMFR1_EL1_HAFDBS_WIDTH 4 +#define ID_AA64MMFR1_EL1_HAFDBS_NI UL(0b0000) +#define ID_AA64MMFR1_EL1_HAFDBS_AF UL(0b0001) +#define ID_AA64MMFR1_EL1_HAFDBS_DBM UL(0b0010) + +#define ID_AA64MMFR1_EL1_RES0 (UL(0)) +#define ID_AA64MMFR1_EL1_RES1 (UL(0)) + +#define REG_ID_AA64MMFR2_EL1 S3_0_C0_C7_2 +#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) +#define SYS_ID_AA64MMFR2_EL1_Op0 3 +#define SYS_ID_AA64MMFR2_EL1_Op1 0 +#define SYS_ID_AA64MMFR2_EL1_CRn 0 +#define SYS_ID_AA64MMFR2_EL1_CRm 7 +#define SYS_ID_AA64MMFR2_EL1_Op2 2 + +#define ID_AA64MMFR2_EL1_E0PD GENMASK(63, 60) +#define ID_AA64MMFR2_EL1_E0PD_MASK GENMASK(63, 60) +#define ID_AA64MMFR2_EL1_E0PD_SHIFT 60 +#define ID_AA64MMFR2_EL1_E0PD_WIDTH 4 +#define ID_AA64MMFR2_EL1_E0PD_NI UL(0b0000) +#define ID_AA64MMFR2_EL1_E0PD_IMP UL(0b0001) + +#define ID_AA64MMFR2_EL1_EVT GENMASK(59, 56) +#define ID_AA64MMFR2_EL1_EVT_MASK GENMASK(59, 56) +#define ID_AA64MMFR2_EL1_EVT_SHIFT 56 +#define ID_AA64MMFR2_EL1_EVT_WIDTH 4 +#define ID_AA64MMFR2_EL1_EVT_NI UL(0b0000) +#define ID_AA64MMFR2_EL1_EVT_IMP UL(0b0001) +#define ID_AA64MMFR2_EL1_EVT_TTLBxS UL(0b0010) + +#define ID_AA64MMFR2_EL1_BBM GENMASK(55, 52) +#define ID_AA64MMFR2_EL1_BBM_MASK GENMASK(55, 52) +#define ID_AA64MMFR2_EL1_BBM_SHIFT 52 +#define ID_AA64MMFR2_EL1_BBM_WIDTH 4 +#define ID_AA64MMFR2_EL1_BBM_0 UL(0b0000) +#define ID_AA64MMFR2_EL1_BBM_1 UL(0b0001) +#define ID_AA64MMFR2_EL1_BBM_2 UL(0b0010) + +#define ID_AA64MMFR2_EL1_TTL GENMASK(51, 48) +#define ID_AA64MMFR2_EL1_TTL_MASK GENMASK(51, 48) +#define ID_AA64MMFR2_EL1_TTL_SHIFT 48 +#define ID_AA64MMFR2_EL1_TTL_WIDTH 4 +#define ID_AA64MMFR2_EL1_TTL_NI UL(0b0000) +#define ID_AA64MMFR2_EL1_TTL_IMP UL(0b0001) + +#define ID_AA64MMFR2_EL1_FWB GENMASK(43, 40) +#define ID_AA64MMFR2_EL1_FWB_MASK GENMASK(43, 40) +#define ID_AA64MMFR2_EL1_FWB_SHIFT 40 +#define ID_AA64MMFR2_EL1_FWB_WIDTH 4 +#define ID_AA64MMFR2_EL1_FWB_NI UL(0b0000) +#define ID_AA64MMFR2_EL1_FWB_IMP UL(0b0001) + +#define ID_AA64MMFR2_EL1_IDS GENMASK(39, 36) +#define ID_AA64MMFR2_EL1_IDS_MASK GENMASK(39, 36) +#define ID_AA64MMFR2_EL1_IDS_SHIFT 36 +#define ID_AA64MMFR2_EL1_IDS_WIDTH 4 +#define ID_AA64MMFR2_EL1_IDS_0x0 UL(0b0000) +#define ID_AA64MMFR2_EL1_IDS_0x18 UL(0b0001) + +#define ID_AA64MMFR2_EL1_AT GENMASK(35, 32) +#define ID_AA64MMFR2_EL1_AT_MASK GENMASK(35, 32) +#define ID_AA64MMFR2_EL1_AT_SHIFT 32 +#define ID_AA64MMFR2_EL1_AT_WIDTH 4 +#define ID_AA64MMFR2_EL1_AT_NI UL(0b0000) +#define ID_AA64MMFR2_EL1_AT_IMP UL(0b0001) + +#define ID_AA64MMFR2_EL1_ST GENMASK(31, 28) +#define ID_AA64MMFR2_EL1_ST_MASK GENMASK(31, 28) +#define ID_AA64MMFR2_EL1_ST_SHIFT 28 +#define ID_AA64MMFR2_EL1_ST_WIDTH 4 +#define ID_AA64MMFR2_EL1_ST_39 UL(0b0000) +#define ID_AA64MMFR2_EL1_ST_48_47 UL(0b0001) + +#define ID_AA64MMFR2_EL1_NV GENMASK(27, 24) +#define ID_AA64MMFR2_EL1_NV_MASK GENMASK(27, 24) +#define ID_AA64MMFR2_EL1_NV_SHIFT 24 +#define ID_AA64MMFR2_EL1_NV_WIDTH 4 +#define ID_AA64MMFR2_EL1_NV_NI UL(0b0000) +#define ID_AA64MMFR2_EL1_NV_IMP UL(0b0001) +#define ID_AA64MMFR2_EL1_NV_NV2 UL(0b0010) + +#define ID_AA64MMFR2_EL1_CCIDX GENMASK(23, 20) +#define ID_AA64MMFR2_EL1_CCIDX_MASK GENMASK(23, 20) +#define ID_AA64MMFR2_EL1_CCIDX_SHIFT 20 +#define ID_AA64MMFR2_EL1_CCIDX_WIDTH 4 +#define ID_AA64MMFR2_EL1_CCIDX_32 UL(0b0000) +#define ID_AA64MMFR2_EL1_CCIDX_64 UL(0b0001) + +#define ID_AA64MMFR2_EL1_VARange GENMASK(19, 16) +#define ID_AA64MMFR2_EL1_VARange_MASK GENMASK(19, 16) +#define ID_AA64MMFR2_EL1_VARange_SHIFT 16 +#define ID_AA64MMFR2_EL1_VARange_WIDTH 4 +#define ID_AA64MMFR2_EL1_VARange_48 UL(0b0000) +#define ID_AA64MMFR2_EL1_VARange_52 UL(0b0001) + +#define ID_AA64MMFR2_EL1_IESB GENMASK(15, 12) +#define ID_AA64MMFR2_EL1_IESB_MASK GENMASK(15, 12) +#define ID_AA64MMFR2_EL1_IESB_SHIFT 12 +#define ID_AA64MMFR2_EL1_IESB_WIDTH 4 +#define ID_AA64MMFR2_EL1_IESB_NI UL(0b0000) +#define ID_AA64MMFR2_EL1_IESB_IMP UL(0b0001) + +#define ID_AA64MMFR2_EL1_LSM GENMASK(11, 8) +#define ID_AA64MMFR2_EL1_LSM_MASK GENMASK(11, 8) +#define ID_AA64MMFR2_EL1_LSM_SHIFT 8 +#define ID_AA64MMFR2_EL1_LSM_WIDTH 4 +#define ID_AA64MMFR2_EL1_LSM_NI UL(0b0000) +#define ID_AA64MMFR2_EL1_LSM_IMP UL(0b0001) + +#define ID_AA64MMFR2_EL1_UAO GENMASK(7, 4) +#define ID_AA64MMFR2_EL1_UAO_MASK GENMASK(7, 4) +#define ID_AA64MMFR2_EL1_UAO_SHIFT 4 +#define ID_AA64MMFR2_EL1_UAO_WIDTH 4 +#define ID_AA64MMFR2_EL1_UAO_NI UL(0b0000) +#define ID_AA64MMFR2_EL1_UAO_IMP UL(0b0001) + +#define ID_AA64MMFR2_EL1_CnP GENMASK(3, 0) +#define ID_AA64MMFR2_EL1_CnP_MASK GENMASK(3, 0) +#define ID_AA64MMFR2_EL1_CnP_SHIFT 0 +#define ID_AA64MMFR2_EL1_CnP_WIDTH 4 +#define ID_AA64MMFR2_EL1_CnP_NI UL(0b0000) +#define ID_AA64MMFR2_EL1_CnP_IMP UL(0b0001) + +#define ID_AA64MMFR2_EL1_RES0 (UL(0) | GENMASK_ULL(47, 44)) +#define ID_AA64MMFR2_EL1_RES1 (UL(0)) + +#define REG_SCTLR_EL1 S3_0_C1_C0_0 +#define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) +#define SYS_SCTLR_EL1_Op0 3 +#define SYS_SCTLR_EL1_Op1 0 +#define SYS_SCTLR_EL1_CRn 1 +#define SYS_SCTLR_EL1_CRm 0 +#define SYS_SCTLR_EL1_Op2 0 + +#define SCTLR_EL1_TIDCP GENMASK(63, 63) +#define SCTLR_EL1_TIDCP_MASK GENMASK(63, 63) +#define SCTLR_EL1_TIDCP_SHIFT 63 +#define SCTLR_EL1_TIDCP_WIDTH 1 + +#define SCTLR_EL1_SPINTMASK GENMASK(62, 62) +#define SCTLR_EL1_SPINTMASK_MASK GENMASK(62, 62) +#define SCTLR_EL1_SPINTMASK_SHIFT 62 +#define SCTLR_EL1_SPINTMASK_WIDTH 1 + +#define SCTLR_EL1_NMI GENMASK(61, 61) +#define SCTLR_EL1_NMI_MASK GENMASK(61, 61) +#define SCTLR_EL1_NMI_SHIFT 61 +#define SCTLR_EL1_NMI_WIDTH 1 + +#define SCTLR_EL1_EnTP2 GENMASK(60, 60) +#define SCTLR_EL1_EnTP2_MASK GENMASK(60, 60) +#define SCTLR_EL1_EnTP2_SHIFT 60 +#define SCTLR_EL1_EnTP2_WIDTH 1 + +#define SCTLR_EL1_EPAN GENMASK(57, 57) +#define SCTLR_EL1_EPAN_MASK GENMASK(57, 57) +#define SCTLR_EL1_EPAN_SHIFT 57 +#define SCTLR_EL1_EPAN_WIDTH 1 + +#define SCTLR_EL1_EnALS GENMASK(56, 56) +#define SCTLR_EL1_EnALS_MASK GENMASK(56, 56) +#define SCTLR_EL1_EnALS_SHIFT 56 +#define SCTLR_EL1_EnALS_WIDTH 1 + +#define SCTLR_EL1_EnAS0 GENMASK(55, 55) +#define SCTLR_EL1_EnAS0_MASK GENMASK(55, 55) +#define SCTLR_EL1_EnAS0_SHIFT 55 +#define SCTLR_EL1_EnAS0_WIDTH 1 + +#define SCTLR_EL1_EnASR GENMASK(54, 54) +#define SCTLR_EL1_EnASR_MASK GENMASK(54, 54) +#define SCTLR_EL1_EnASR_SHIFT 54 +#define SCTLR_EL1_EnASR_WIDTH 1 + +#define SCTLR_EL1_TME GENMASK(53, 53) +#define SCTLR_EL1_TME_MASK GENMASK(53, 53) +#define SCTLR_EL1_TME_SHIFT 53 +#define SCTLR_EL1_TME_WIDTH 1 + +#define SCTLR_EL1_TME0 GENMASK(52, 52) +#define SCTLR_EL1_TME0_MASK GENMASK(52, 52) +#define SCTLR_EL1_TME0_SHIFT 52 +#define SCTLR_EL1_TME0_WIDTH 1 + +#define SCTLR_EL1_TMT GENMASK(51, 51) +#define SCTLR_EL1_TMT_MASK GENMASK(51, 51) +#define SCTLR_EL1_TMT_SHIFT 51 +#define SCTLR_EL1_TMT_WIDTH 1 + +#define SCTLR_EL1_TMT0 GENMASK(50, 50) +#define SCTLR_EL1_TMT0_MASK GENMASK(50, 50) +#define SCTLR_EL1_TMT0_SHIFT 50 +#define SCTLR_EL1_TMT0_WIDTH 1 + +#define SCTLR_EL1_TWEDEL GENMASK(49, 46) +#define SCTLR_EL1_TWEDEL_MASK GENMASK(49, 46) +#define SCTLR_EL1_TWEDEL_SHIFT 46 +#define SCTLR_EL1_TWEDEL_WIDTH 4 + +#define SCTLR_EL1_TWEDEn GENMASK(45, 45) +#define SCTLR_EL1_TWEDEn_MASK GENMASK(45, 45) +#define SCTLR_EL1_TWEDEn_SHIFT 45 +#define SCTLR_EL1_TWEDEn_WIDTH 1 + +#define SCTLR_EL1_DSSBS GENMASK(44, 44) +#define SCTLR_EL1_DSSBS_MASK GENMASK(44, 44) +#define SCTLR_EL1_DSSBS_SHIFT 44 +#define SCTLR_EL1_DSSBS_WIDTH 1 + +#define SCTLR_EL1_ATA GENMASK(43, 43) +#define SCTLR_EL1_ATA_MASK GENMASK(43, 43) +#define SCTLR_EL1_ATA_SHIFT 43 +#define SCTLR_EL1_ATA_WIDTH 1 + +#define SCTLR_EL1_ATA0 GENMASK(42, 42) +#define SCTLR_EL1_ATA0_MASK GENMASK(42, 42) +#define SCTLR_EL1_ATA0_SHIFT 42 +#define SCTLR_EL1_ATA0_WIDTH 1 + +#define SCTLR_EL1_TCF GENMASK(41, 40) +#define SCTLR_EL1_TCF_MASK GENMASK(41, 40) +#define SCTLR_EL1_TCF_SHIFT 40 +#define SCTLR_EL1_TCF_WIDTH 2 +#define SCTLR_EL1_TCF_NONE UL(0b00) +#define SCTLR_EL1_TCF_SYNC UL(0b01) +#define SCTLR_EL1_TCF_ASYNC UL(0b10) +#define SCTLR_EL1_TCF_ASYMM UL(0b11) + +#define SCTLR_EL1_TCF0 GENMASK(39, 38) +#define SCTLR_EL1_TCF0_MASK GENMASK(39, 38) +#define SCTLR_EL1_TCF0_SHIFT 38 +#define SCTLR_EL1_TCF0_WIDTH 2 +#define SCTLR_EL1_TCF0_NONE UL(0b00) +#define SCTLR_EL1_TCF0_SYNC UL(0b01) +#define SCTLR_EL1_TCF0_ASYNC UL(0b10) +#define SCTLR_EL1_TCF0_ASYMM UL(0b11) + +#define SCTLR_EL1_ITFSB GENMASK(37, 37) +#define SCTLR_EL1_ITFSB_MASK GENMASK(37, 37) +#define SCTLR_EL1_ITFSB_SHIFT 37 +#define SCTLR_EL1_ITFSB_WIDTH 1 + +#define SCTLR_EL1_BT1 GENMASK(36, 36) +#define SCTLR_EL1_BT1_MASK GENMASK(36, 36) +#define SCTLR_EL1_BT1_SHIFT 36 +#define SCTLR_EL1_BT1_WIDTH 1 + +#define SCTLR_EL1_BT0 GENMASK(35, 35) +#define SCTLR_EL1_BT0_MASK GENMASK(35, 35) +#define SCTLR_EL1_BT0_SHIFT 35 +#define SCTLR_EL1_BT0_WIDTH 1 + +#define SCTLR_EL1_MSCEn GENMASK(33, 33) +#define SCTLR_EL1_MSCEn_MASK GENMASK(33, 33) +#define SCTLR_EL1_MSCEn_SHIFT 33 +#define SCTLR_EL1_MSCEn_WIDTH 1 + +#define SCTLR_EL1_CMOW GENMASK(32, 32) +#define SCTLR_EL1_CMOW_MASK GENMASK(32, 32) +#define SCTLR_EL1_CMOW_SHIFT 32 +#define SCTLR_EL1_CMOW_WIDTH 1 + +#define SCTLR_EL1_EnIA GENMASK(31, 31) +#define SCTLR_EL1_EnIA_MASK GENMASK(31, 31) +#define SCTLR_EL1_EnIA_SHIFT 31 +#define SCTLR_EL1_EnIA_WIDTH 1 + +#define SCTLR_EL1_EnIB GENMASK(30, 30) +#define SCTLR_EL1_EnIB_MASK GENMASK(30, 30) +#define SCTLR_EL1_EnIB_SHIFT 30 +#define SCTLR_EL1_EnIB_WIDTH 1 + +#define SCTLR_EL1_LSMAOE GENMASK(29, 29) +#define SCTLR_EL1_LSMAOE_MASK GENMASK(29, 29) +#define SCTLR_EL1_LSMAOE_SHIFT 29 +#define SCTLR_EL1_LSMAOE_WIDTH 1 + +#define SCTLR_EL1_nTLSMD GENMASK(28, 28) +#define SCTLR_EL1_nTLSMD_MASK GENMASK(28, 28) +#define SCTLR_EL1_nTLSMD_SHIFT 28 +#define SCTLR_EL1_nTLSMD_WIDTH 1 + +#define SCTLR_EL1_EnDA GENMASK(27, 27) +#define SCTLR_EL1_EnDA_MASK GENMASK(27, 27) +#define SCTLR_EL1_EnDA_SHIFT 27 +#define SCTLR_EL1_EnDA_WIDTH 1 + +#define SCTLR_EL1_UCI GENMASK(26, 26) +#define SCTLR_EL1_UCI_MASK GENMASK(26, 26) +#define SCTLR_EL1_UCI_SHIFT 26 +#define SCTLR_EL1_UCI_WIDTH 1 + +#define SCTLR_EL1_EE GENMASK(25, 25) +#define SCTLR_EL1_EE_MASK GENMASK(25, 25) +#define SCTLR_EL1_EE_SHIFT 25 +#define SCTLR_EL1_EE_WIDTH 1 + +#define SCTLR_EL1_E0E GENMASK(24, 24) +#define SCTLR_EL1_E0E_MASK GENMASK(24, 24) +#define SCTLR_EL1_E0E_SHIFT 24 +#define SCTLR_EL1_E0E_WIDTH 1 + +#define SCTLR_EL1_SPAN GENMASK(23, 23) +#define SCTLR_EL1_SPAN_MASK GENMASK(23, 23) +#define SCTLR_EL1_SPAN_SHIFT 23 +#define SCTLR_EL1_SPAN_WIDTH 1 + +#define SCTLR_EL1_EIS GENMASK(22, 22) +#define SCTLR_EL1_EIS_MASK GENMASK(22, 22) +#define SCTLR_EL1_EIS_SHIFT 22 +#define SCTLR_EL1_EIS_WIDTH 1 + +#define SCTLR_EL1_IESB GENMASK(21, 21) +#define SCTLR_EL1_IESB_MASK GENMASK(21, 21) +#define SCTLR_EL1_IESB_SHIFT 21 +#define SCTLR_EL1_IESB_WIDTH 1 + +#define SCTLR_EL1_TSCXT GENMASK(20, 20) +#define SCTLR_EL1_TSCXT_MASK GENMASK(20, 20) +#define SCTLR_EL1_TSCXT_SHIFT 20 +#define SCTLR_EL1_TSCXT_WIDTH 1 + +#define SCTLR_EL1_WXN GENMASK(19, 19) +#define SCTLR_EL1_WXN_MASK GENMASK(19, 19) +#define SCTLR_EL1_WXN_SHIFT 19 +#define SCTLR_EL1_WXN_WIDTH 1 + +#define SCTLR_EL1_nTWE GENMASK(18, 18) +#define SCTLR_EL1_nTWE_MASK GENMASK(18, 18) +#define SCTLR_EL1_nTWE_SHIFT 18 +#define SCTLR_EL1_nTWE_WIDTH 1 + +#define SCTLR_EL1_nTWI GENMASK(16, 16) +#define SCTLR_EL1_nTWI_MASK GENMASK(16, 16) +#define SCTLR_EL1_nTWI_SHIFT 16 +#define SCTLR_EL1_nTWI_WIDTH 1 + +#define SCTLR_EL1_UCT GENMASK(15, 15) +#define SCTLR_EL1_UCT_MASK GENMASK(15, 15) +#define SCTLR_EL1_UCT_SHIFT 15 +#define SCTLR_EL1_UCT_WIDTH 1 + +#define SCTLR_EL1_DZE GENMASK(14, 14) +#define SCTLR_EL1_DZE_MASK GENMASK(14, 14) +#define SCTLR_EL1_DZE_SHIFT 14 +#define SCTLR_EL1_DZE_WIDTH 1 + +#define SCTLR_EL1_EnDB GENMASK(13, 13) +#define SCTLR_EL1_EnDB_MASK GENMASK(13, 13) +#define SCTLR_EL1_EnDB_SHIFT 13 +#define SCTLR_EL1_EnDB_WIDTH 1 + +#define SCTLR_EL1_I GENMASK(12, 12) +#define SCTLR_EL1_I_MASK GENMASK(12, 12) +#define SCTLR_EL1_I_SHIFT 12 +#define SCTLR_EL1_I_WIDTH 1 + +#define SCTLR_EL1_EOS GENMASK(11, 11) +#define SCTLR_EL1_EOS_MASK GENMASK(11, 11) +#define SCTLR_EL1_EOS_SHIFT 11 +#define SCTLR_EL1_EOS_WIDTH 1 + +#define SCTLR_EL1_EnRCTX GENMASK(10, 10) +#define SCTLR_EL1_EnRCTX_MASK GENMASK(10, 10) +#define SCTLR_EL1_EnRCTX_SHIFT 10 +#define SCTLR_EL1_EnRCTX_WIDTH 1 + +#define SCTLR_EL1_UMA GENMASK(9, 9) +#define SCTLR_EL1_UMA_MASK GENMASK(9, 9) +#define SCTLR_EL1_UMA_SHIFT 9 +#define SCTLR_EL1_UMA_WIDTH 1 + +#define SCTLR_EL1_SED GENMASK(8, 8) +#define SCTLR_EL1_SED_MASK GENMASK(8, 8) +#define SCTLR_EL1_SED_SHIFT 8 +#define SCTLR_EL1_SED_WIDTH 1 + +#define SCTLR_EL1_ITD GENMASK(7, 7) +#define SCTLR_EL1_ITD_MASK GENMASK(7, 7) +#define SCTLR_EL1_ITD_SHIFT 7 +#define SCTLR_EL1_ITD_WIDTH 1 + +#define SCTLR_EL1_nAA GENMASK(6, 6) +#define SCTLR_EL1_nAA_MASK GENMASK(6, 6) +#define SCTLR_EL1_nAA_SHIFT 6 +#define SCTLR_EL1_nAA_WIDTH 1 + +#define SCTLR_EL1_CP15BEN GENMASK(5, 5) +#define SCTLR_EL1_CP15BEN_MASK GENMASK(5, 5) +#define SCTLR_EL1_CP15BEN_SHIFT 5 +#define SCTLR_EL1_CP15BEN_WIDTH 1 + +#define SCTLR_EL1_SA0 GENMASK(4, 4) +#define SCTLR_EL1_SA0_MASK GENMASK(4, 4) +#define SCTLR_EL1_SA0_SHIFT 4 +#define SCTLR_EL1_SA0_WIDTH 1 + +#define SCTLR_EL1_SA GENMASK(3, 3) +#define SCTLR_EL1_SA_MASK GENMASK(3, 3) +#define SCTLR_EL1_SA_SHIFT 3 +#define SCTLR_EL1_SA_WIDTH 1 + +#define SCTLR_EL1_C GENMASK(2, 2) +#define SCTLR_EL1_C_MASK GENMASK(2, 2) +#define SCTLR_EL1_C_SHIFT 2 +#define SCTLR_EL1_C_WIDTH 1 + +#define SCTLR_EL1_A GENMASK(1, 1) +#define SCTLR_EL1_A_MASK GENMASK(1, 1) +#define SCTLR_EL1_A_SHIFT 1 +#define SCTLR_EL1_A_WIDTH 1 + +#define SCTLR_EL1_M GENMASK(0, 0) +#define SCTLR_EL1_M_MASK GENMASK(0, 0) +#define SCTLR_EL1_M_SHIFT 0 +#define SCTLR_EL1_M_WIDTH 1 + +#define SCTLR_EL1_RES0 (UL(0) | GENMASK_ULL(59, 58) | GENMASK_ULL(34, 34) | GENMASK_ULL(17, 17)) +#define SCTLR_EL1_RES1 (UL(0)) + +#define CPACR_ELx_TTA GENMASK(28, 28) +#define CPACR_ELx_TTA_MASK GENMASK(28, 28) +#define CPACR_ELx_TTA_SHIFT 28 +#define CPACR_ELx_TTA_WIDTH 1 + +#define CPACR_ELx_SMEN GENMASK(25, 24) +#define CPACR_ELx_SMEN_MASK GENMASK(25, 24) +#define CPACR_ELx_SMEN_SHIFT 24 +#define CPACR_ELx_SMEN_WIDTH 2 + +#define CPACR_ELx_FPEN GENMASK(21, 20) +#define CPACR_ELx_FPEN_MASK GENMASK(21, 20) +#define CPACR_ELx_FPEN_SHIFT 20 +#define CPACR_ELx_FPEN_WIDTH 2 + +#define CPACR_ELx_ZEN GENMASK(17, 16) +#define CPACR_ELx_ZEN_MASK GENMASK(17, 16) +#define CPACR_ELx_ZEN_SHIFT 16 +#define CPACR_ELx_ZEN_WIDTH 2 + +#define CPACR_ELx_RES0 (UL(0) | GENMASK_ULL(63, 29) | GENMASK_ULL(27, 26) | GENMASK_ULL(23, 22) | GENMASK_ULL(19, 18) | GENMASK_ULL(15, 0)) +#define CPACR_ELx_RES1 (UL(0)) + +#define REG_CPACR_EL1 S3_0_C1_C0_2 +#define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) +#define SYS_CPACR_EL1_Op0 3 +#define SYS_CPACR_EL1_Op1 0 +#define SYS_CPACR_EL1_CRn 1 +#define SYS_CPACR_EL1_CRm 0 +#define SYS_CPACR_EL1_Op2 2 + +/* For CPACR_EL1 fields see CPACR_ELx */ + +#define REG_SMPRI_EL1 S3_0_C1_C2_4 +#define SYS_SMPRI_EL1 sys_reg(3, 0, 1, 2, 4) +#define SYS_SMPRI_EL1_Op0 3 +#define SYS_SMPRI_EL1_Op1 0 +#define SYS_SMPRI_EL1_CRn 1 +#define SYS_SMPRI_EL1_CRm 2 +#define SYS_SMPRI_EL1_Op2 4 + +#define SMPRI_EL1_PRIORITY GENMASK(3, 0) +#define SMPRI_EL1_PRIORITY_MASK GENMASK(3, 0) +#define SMPRI_EL1_PRIORITY_SHIFT 0 +#define SMPRI_EL1_PRIORITY_WIDTH 4 + +#define SMPRI_EL1_RES0 (UL(0) | GENMASK_ULL(63, 4)) +#define SMPRI_EL1_RES1 (UL(0)) + +#define ZCR_ELx_LEN GENMASK(3, 0) +#define ZCR_ELx_LEN_MASK GENMASK(3, 0) +#define ZCR_ELx_LEN_SHIFT 0 +#define ZCR_ELx_LEN_WIDTH 4 + +#define ZCR_ELx_RES0 (UL(0) | GENMASK_ULL(63, 9)) +#define ZCR_ELx_RES1 (UL(0)) + +#define REG_ZCR_EL1 S3_0_C1_C2_0 +#define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) +#define SYS_ZCR_EL1_Op0 3 +#define SYS_ZCR_EL1_Op1 0 +#define SYS_ZCR_EL1_CRn 1 +#define SYS_ZCR_EL1_CRm 2 +#define SYS_ZCR_EL1_Op2 0 + +/* For ZCR_EL1 fields see ZCR_ELx */ + +#define SMCR_ELx_FA64 GENMASK(31, 31) +#define SMCR_ELx_FA64_MASK GENMASK(31, 31) +#define SMCR_ELx_FA64_SHIFT 31 +#define SMCR_ELx_FA64_WIDTH 1 + +#define SMCR_ELx_LEN GENMASK(3, 0) +#define SMCR_ELx_LEN_MASK GENMASK(3, 0) +#define SMCR_ELx_LEN_SHIFT 0 +#define SMCR_ELx_LEN_WIDTH 4 + +#define SMCR_ELx_RES0 (UL(0) | GENMASK_ULL(63, 32) | GENMASK_ULL(30, 9)) +#define SMCR_ELx_RES1 (UL(0)) + +#define REG_SMCR_EL1 S3_0_C1_C2_6 +#define SYS_SMCR_EL1 sys_reg(3, 0, 1, 2, 6) +#define SYS_SMCR_EL1_Op0 3 +#define SYS_SMCR_EL1_Op1 0 +#define SYS_SMCR_EL1_CRn 1 +#define SYS_SMCR_EL1_CRm 2 +#define SYS_SMCR_EL1_Op2 6 + +/* For SMCR_EL1 fields see SMCR_ELx */ + +#define REG_ALLINT S3_0_C4_C3_0 +#define SYS_ALLINT sys_reg(3, 0, 4, 3, 0) +#define SYS_ALLINT_Op0 3 +#define SYS_ALLINT_Op1 0 +#define SYS_ALLINT_CRn 4 +#define SYS_ALLINT_CRm 3 +#define SYS_ALLINT_Op2 0 + +#define ALLINT_ALLINT GENMASK(13, 13) +#define ALLINT_ALLINT_MASK GENMASK(13, 13) +#define ALLINT_ALLINT_SHIFT 13 +#define ALLINT_ALLINT_WIDTH 1 + +#define ALLINT_RES0 (UL(0) | GENMASK_ULL(63, 14) | GENMASK_ULL(12, 0)) +#define ALLINT_RES1 (UL(0)) + +#define REG_FAR_EL1 S3_0_C6_C0_0 +#define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) +#define SYS_FAR_EL1_Op0 3 +#define SYS_FAR_EL1_Op1 0 +#define SYS_FAR_EL1_CRn 6 +#define SYS_FAR_EL1_CRm 0 +#define SYS_FAR_EL1_Op2 0 + +#define FAR_EL1_ADDR GENMASK(63, 0) +#define FAR_EL1_ADDR_MASK GENMASK(63, 0) +#define FAR_EL1_ADDR_SHIFT 0 +#define FAR_EL1_ADDR_WIDTH 64 + +#define FAR_EL1_RES0 (UL(0)) +#define FAR_EL1_RES1 (UL(0)) + +#define CONTEXTIDR_ELx_PROCID GENMASK(31, 0) +#define CONTEXTIDR_ELx_PROCID_MASK GENMASK(31, 0) +#define CONTEXTIDR_ELx_PROCID_SHIFT 0 +#define CONTEXTIDR_ELx_PROCID_WIDTH 32 + +#define CONTEXTIDR_ELx_RES0 (UL(0) | GENMASK_ULL(63, 32)) +#define CONTEXTIDR_ELx_RES1 (UL(0)) + +#define REG_CONTEXTIDR_EL1 S3_0_C13_C0_1 +#define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) +#define SYS_CONTEXTIDR_EL1_Op0 3 +#define SYS_CONTEXTIDR_EL1_Op1 0 +#define SYS_CONTEXTIDR_EL1_CRn 13 +#define SYS_CONTEXTIDR_EL1_CRm 0 +#define SYS_CONTEXTIDR_EL1_Op2 1 + +/* For CONTEXTIDR_EL1 fields see CONTEXTIDR_ELx */ + +#define REG_TPIDR_EL1 S3_0_C13_C0_4 +#define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) +#define SYS_TPIDR_EL1_Op0 3 +#define SYS_TPIDR_EL1_Op1 0 +#define SYS_TPIDR_EL1_CRn 13 +#define SYS_TPIDR_EL1_CRm 0 +#define SYS_TPIDR_EL1_Op2 4 + +#define TPIDR_EL1_ThreadID GENMASK(63, 0) +#define TPIDR_EL1_ThreadID_MASK GENMASK(63, 0) +#define TPIDR_EL1_ThreadID_SHIFT 0 +#define TPIDR_EL1_ThreadID_WIDTH 64 + +#define TPIDR_EL1_RES0 (UL(0)) +#define TPIDR_EL1_RES1 (UL(0)) + +#define REG_SCXTNUM_EL1 S3_0_C13_C0_7 +#define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, 0, 7) +#define SYS_SCXTNUM_EL1_Op0 3 +#define SYS_SCXTNUM_EL1_Op1 0 +#define SYS_SCXTNUM_EL1_CRn 13 +#define SYS_SCXTNUM_EL1_CRm 0 +#define SYS_SCXTNUM_EL1_Op2 7 + +#define SCXTNUM_EL1_SoftwareContextNumber GENMASK(63, 0) +#define SCXTNUM_EL1_SoftwareContextNumber_MASK GENMASK(63, 0) +#define SCXTNUM_EL1_SoftwareContextNumber_SHIFT 0 +#define SCXTNUM_EL1_SoftwareContextNumber_WIDTH 64 + +#define SCXTNUM_EL1_RES0 (UL(0)) +#define SCXTNUM_EL1_RES1 (UL(0)) + +#define REG_CLIDR_EL1 S3_1_C0_C0_1 +#define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) +#define SYS_CLIDR_EL1_Op0 3 +#define SYS_CLIDR_EL1_Op1 1 +#define SYS_CLIDR_EL1_CRn 0 +#define SYS_CLIDR_EL1_CRm 0 +#define SYS_CLIDR_EL1_Op2 1 + +#define CLIDR_EL1_Ttypen GENMASK(46, 33) +#define CLIDR_EL1_Ttypen_MASK GENMASK(46, 33) +#define CLIDR_EL1_Ttypen_SHIFT 33 +#define CLIDR_EL1_Ttypen_WIDTH 14 + +#define CLIDR_EL1_ICB GENMASK(32, 30) +#define CLIDR_EL1_ICB_MASK GENMASK(32, 30) +#define CLIDR_EL1_ICB_SHIFT 30 +#define CLIDR_EL1_ICB_WIDTH 3 + +#define CLIDR_EL1_LoUU GENMASK(29, 27) +#define CLIDR_EL1_LoUU_MASK GENMASK(29, 27) +#define CLIDR_EL1_LoUU_SHIFT 27 +#define CLIDR_EL1_LoUU_WIDTH 3 + +#define CLIDR_EL1_LoC GENMASK(26, 24) +#define CLIDR_EL1_LoC_MASK GENMASK(26, 24) +#define CLIDR_EL1_LoC_SHIFT 24 +#define CLIDR_EL1_LoC_WIDTH 3 + +#define CLIDR_EL1_LoUIS GENMASK(23, 21) +#define CLIDR_EL1_LoUIS_MASK GENMASK(23, 21) +#define CLIDR_EL1_LoUIS_SHIFT 21 +#define CLIDR_EL1_LoUIS_WIDTH 3 + +#define CLIDR_EL1_Ctype7 GENMASK(20, 18) +#define CLIDR_EL1_Ctype7_MASK GENMASK(20, 18) +#define CLIDR_EL1_Ctype7_SHIFT 18 +#define CLIDR_EL1_Ctype7_WIDTH 3 + +#define CLIDR_EL1_Ctype6 GENMASK(17, 15) +#define CLIDR_EL1_Ctype6_MASK GENMASK(17, 15) +#define CLIDR_EL1_Ctype6_SHIFT 15 +#define CLIDR_EL1_Ctype6_WIDTH 3 + +#define CLIDR_EL1_Ctype5 GENMASK(14, 12) +#define CLIDR_EL1_Ctype5_MASK GENMASK(14, 12) +#define CLIDR_EL1_Ctype5_SHIFT 12 +#define CLIDR_EL1_Ctype5_WIDTH 3 + +#define CLIDR_EL1_Ctype4 GENMASK(11, 9) +#define CLIDR_EL1_Ctype4_MASK GENMASK(11, 9) +#define CLIDR_EL1_Ctype4_SHIFT 9 +#define CLIDR_EL1_Ctype4_WIDTH 3 + +#define CLIDR_EL1_Ctype3 GENMASK(8, 6) +#define CLIDR_EL1_Ctype3_MASK GENMASK(8, 6) +#define CLIDR_EL1_Ctype3_SHIFT 6 +#define CLIDR_EL1_Ctype3_WIDTH 3 + +#define CLIDR_EL1_Ctype2 GENMASK(5, 3) +#define CLIDR_EL1_Ctype2_MASK GENMASK(5, 3) +#define CLIDR_EL1_Ctype2_SHIFT 3 +#define CLIDR_EL1_Ctype2_WIDTH 3 + +#define CLIDR_EL1_Ctype1 GENMASK(2, 0) +#define CLIDR_EL1_Ctype1_MASK GENMASK(2, 0) +#define CLIDR_EL1_Ctype1_SHIFT 0 +#define CLIDR_EL1_Ctype1_WIDTH 3 + +#define CLIDR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 47)) +#define CLIDR_EL1_RES1 (UL(0)) + +#define REG_GMID_EL1 S3_1_C0_C0_4 +#define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4) +#define SYS_GMID_EL1_Op0 3 +#define SYS_GMID_EL1_Op1 1 +#define SYS_GMID_EL1_CRn 0 +#define SYS_GMID_EL1_CRm 0 +#define SYS_GMID_EL1_Op2 4 + +#define GMID_EL1_BS GENMASK(3, 0) +#define GMID_EL1_BS_MASK GENMASK(3, 0) +#define GMID_EL1_BS_SHIFT 0 +#define GMID_EL1_BS_WIDTH 4 + +#define GMID_EL1_RES0 (UL(0) | GENMASK_ULL(63, 4)) +#define GMID_EL1_RES1 (UL(0)) + +#define REG_SMIDR_EL1 S3_1_C0_C0_6 +#define SYS_SMIDR_EL1 sys_reg(3, 1, 0, 0, 6) +#define SYS_SMIDR_EL1_Op0 3 +#define SYS_SMIDR_EL1_Op1 1 +#define SYS_SMIDR_EL1_CRn 0 +#define SYS_SMIDR_EL1_CRm 0 +#define SYS_SMIDR_EL1_Op2 6 + +#define SMIDR_EL1_IMPLEMENTER GENMASK(31, 24) +#define SMIDR_EL1_IMPLEMENTER_MASK GENMASK(31, 24) +#define SMIDR_EL1_IMPLEMENTER_SHIFT 24 +#define SMIDR_EL1_IMPLEMENTER_WIDTH 8 + +#define SMIDR_EL1_REVISION GENMASK(23, 16) +#define SMIDR_EL1_REVISION_MASK GENMASK(23, 16) +#define SMIDR_EL1_REVISION_SHIFT 16 +#define SMIDR_EL1_REVISION_WIDTH 8 + +#define SMIDR_EL1_SMPS GENMASK(15, 15) +#define SMIDR_EL1_SMPS_MASK GENMASK(15, 15) +#define SMIDR_EL1_SMPS_SHIFT 15 +#define SMIDR_EL1_SMPS_WIDTH 1 + +#define SMIDR_EL1_AFFINITY GENMASK(11, 0) +#define SMIDR_EL1_AFFINITY_MASK GENMASK(11, 0) +#define SMIDR_EL1_AFFINITY_SHIFT 0 +#define SMIDR_EL1_AFFINITY_WIDTH 12 + +#define SMIDR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32) | GENMASK_ULL(14, 12)) +#define SMIDR_EL1_RES1 (UL(0)) + +#define REG_CSSELR_EL1 S3_2_C0_C0_0 +#define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) +#define SYS_CSSELR_EL1_Op0 3 +#define SYS_CSSELR_EL1_Op1 2 +#define SYS_CSSELR_EL1_CRn 0 +#define SYS_CSSELR_EL1_CRm 0 +#define SYS_CSSELR_EL1_Op2 0 + +#define CSSELR_EL1_TnD GENMASK(4, 4) +#define CSSELR_EL1_TnD_MASK GENMASK(4, 4) +#define CSSELR_EL1_TnD_SHIFT 4 +#define CSSELR_EL1_TnD_WIDTH 1 + +#define CSSELR_EL1_Level GENMASK(3, 1) +#define CSSELR_EL1_Level_MASK GENMASK(3, 1) +#define CSSELR_EL1_Level_SHIFT 1 +#define CSSELR_EL1_Level_WIDTH 3 + +#define CSSELR_EL1_InD GENMASK(0, 0) +#define CSSELR_EL1_InD_MASK GENMASK(0, 0) +#define CSSELR_EL1_InD_SHIFT 0 +#define CSSELR_EL1_InD_WIDTH 1 + +#define CSSELR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 5)) +#define CSSELR_EL1_RES1 (UL(0)) + +#define REG_CTR_EL0 S3_3_C0_C0_1 +#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) +#define SYS_CTR_EL0_Op0 3 +#define SYS_CTR_EL0_Op1 3 +#define SYS_CTR_EL0_CRn 0 +#define SYS_CTR_EL0_CRm 0 +#define SYS_CTR_EL0_Op2 1 + +#define CTR_EL0_TminLine GENMASK(37, 32) +#define CTR_EL0_TminLine_MASK GENMASK(37, 32) +#define CTR_EL0_TminLine_SHIFT 32 +#define CTR_EL0_TminLine_WIDTH 6 + +#define CTR_EL0_DIC GENMASK(29, 29) +#define CTR_EL0_DIC_MASK GENMASK(29, 29) +#define CTR_EL0_DIC_SHIFT 29 +#define CTR_EL0_DIC_WIDTH 1 + +#define CTR_EL0_IDC GENMASK(28, 28) +#define CTR_EL0_IDC_MASK GENMASK(28, 28) +#define CTR_EL0_IDC_SHIFT 28 +#define CTR_EL0_IDC_WIDTH 1 + +#define CTR_EL0_CWG GENMASK(27, 24) +#define CTR_EL0_CWG_MASK GENMASK(27, 24) +#define CTR_EL0_CWG_SHIFT 24 +#define CTR_EL0_CWG_WIDTH 4 + +#define CTR_EL0_ERG GENMASK(23, 20) +#define CTR_EL0_ERG_MASK GENMASK(23, 20) +#define CTR_EL0_ERG_SHIFT 20 +#define CTR_EL0_ERG_WIDTH 4 + +#define CTR_EL0_DminLine GENMASK(19, 16) +#define CTR_EL0_DminLine_MASK GENMASK(19, 16) +#define CTR_EL0_DminLine_SHIFT 16 +#define CTR_EL0_DminLine_WIDTH 4 + +#define CTR_EL0_L1Ip GENMASK(15, 14) +#define CTR_EL0_L1Ip_MASK GENMASK(15, 14) +#define CTR_EL0_L1Ip_SHIFT 14 +#define CTR_EL0_L1Ip_WIDTH 2 +#define CTR_EL0_L1Ip_VPIPT UL(0b00) +#define CTR_EL0_L1Ip_RESERVED UL(0b01) +#define CTR_EL0_L1Ip_VIPT UL(0b10) +#define CTR_EL0_L1Ip_PIPT UL(0b11) + +#define CTR_EL0_IminLine GENMASK(3, 0) +#define CTR_EL0_IminLine_MASK GENMASK(3, 0) +#define CTR_EL0_IminLine_SHIFT 0 +#define CTR_EL0_IminLine_WIDTH 4 + +#define CTR_EL0_RES0 (UL(0) | GENMASK_ULL(63, 38) | GENMASK_ULL(30, 30) | GENMASK_ULL(13, 4)) +#define CTR_EL0_RES1 (UL(0) | GENMASK_ULL(31, 31)) + +#define REG_DCZID_EL0 S3_3_C0_C0_7 +#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) +#define SYS_DCZID_EL0_Op0 3 +#define SYS_DCZID_EL0_Op1 3 +#define SYS_DCZID_EL0_CRn 0 +#define SYS_DCZID_EL0_CRm 0 +#define SYS_DCZID_EL0_Op2 7 + +#define DCZID_EL0_DZP GENMASK(4, 4) +#define DCZID_EL0_DZP_MASK GENMASK(4, 4) +#define DCZID_EL0_DZP_SHIFT 4 +#define DCZID_EL0_DZP_WIDTH 1 + +#define DCZID_EL0_BS GENMASK(3, 0) +#define DCZID_EL0_BS_MASK GENMASK(3, 0) +#define DCZID_EL0_BS_SHIFT 0 +#define DCZID_EL0_BS_WIDTH 4 + +#define DCZID_EL0_RES0 (UL(0) | GENMASK_ULL(63, 5)) +#define DCZID_EL0_RES1 (UL(0)) + +#define REG_SVCR S3_3_C4_C2_2 +#define SYS_SVCR sys_reg(3, 3, 4, 2, 2) +#define SYS_SVCR_Op0 3 +#define SYS_SVCR_Op1 3 +#define SYS_SVCR_CRn 4 +#define SYS_SVCR_CRm 2 +#define SYS_SVCR_Op2 2 + +#define SVCR_ZA GENMASK(1, 1) +#define SVCR_ZA_MASK GENMASK(1, 1) +#define SVCR_ZA_SHIFT 1 +#define SVCR_ZA_WIDTH 1 + +#define SVCR_SM GENMASK(0, 0) +#define SVCR_SM_MASK GENMASK(0, 0) +#define SVCR_SM_SHIFT 0 +#define SVCR_SM_WIDTH 1 + +#define SVCR_RES0 (UL(0) | GENMASK_ULL(63, 2)) +#define SVCR_RES1 (UL(0)) + +#define REG_ZCR_EL2 S3_4_C1_C2_0 +#define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) +#define SYS_ZCR_EL2_Op0 3 +#define SYS_ZCR_EL2_Op1 4 +#define SYS_ZCR_EL2_CRn 1 +#define SYS_ZCR_EL2_CRm 2 +#define SYS_ZCR_EL2_Op2 0 + +/* For ZCR_EL2 fields see ZCR_ELx */ + +#define REG_HCRX_EL2 S3_4_C1_C2_2 +#define SYS_HCRX_EL2 sys_reg(3, 4, 1, 2, 2) +#define SYS_HCRX_EL2_Op0 3 +#define SYS_HCRX_EL2_Op1 4 +#define SYS_HCRX_EL2_CRn 1 +#define SYS_HCRX_EL2_CRm 2 +#define SYS_HCRX_EL2_Op2 2 + +#define HCRX_EL2_MSCEn GENMASK(11, 11) +#define HCRX_EL2_MSCEn_MASK GENMASK(11, 11) +#define HCRX_EL2_MSCEn_SHIFT 11 +#define HCRX_EL2_MSCEn_WIDTH 1 + +#define HCRX_EL2_MCE2 GENMASK(10, 10) +#define HCRX_EL2_MCE2_MASK GENMASK(10, 10) +#define HCRX_EL2_MCE2_SHIFT 10 +#define HCRX_EL2_MCE2_WIDTH 1 + +#define HCRX_EL2_CMOW GENMASK(9, 9) +#define HCRX_EL2_CMOW_MASK GENMASK(9, 9) +#define HCRX_EL2_CMOW_SHIFT 9 +#define HCRX_EL2_CMOW_WIDTH 1 + +#define HCRX_EL2_VFNMI GENMASK(8, 8) +#define HCRX_EL2_VFNMI_MASK GENMASK(8, 8) +#define HCRX_EL2_VFNMI_SHIFT 8 +#define HCRX_EL2_VFNMI_WIDTH 1 + +#define HCRX_EL2_VINMI GENMASK(7, 7) +#define HCRX_EL2_VINMI_MASK GENMASK(7, 7) +#define HCRX_EL2_VINMI_SHIFT 7 +#define HCRX_EL2_VINMI_WIDTH 1 + +#define HCRX_EL2_TALLINT GENMASK(6, 6) +#define HCRX_EL2_TALLINT_MASK GENMASK(6, 6) +#define HCRX_EL2_TALLINT_SHIFT 6 +#define HCRX_EL2_TALLINT_WIDTH 1 + +#define HCRX_EL2_SMPME GENMASK(5, 5) +#define HCRX_EL2_SMPME_MASK GENMASK(5, 5) +#define HCRX_EL2_SMPME_SHIFT 5 +#define HCRX_EL2_SMPME_WIDTH 1 + +#define HCRX_EL2_FGTnXS GENMASK(4, 4) +#define HCRX_EL2_FGTnXS_MASK GENMASK(4, 4) +#define HCRX_EL2_FGTnXS_SHIFT 4 +#define HCRX_EL2_FGTnXS_WIDTH 1 + +#define HCRX_EL2_FnXS GENMASK(3, 3) +#define HCRX_EL2_FnXS_MASK GENMASK(3, 3) +#define HCRX_EL2_FnXS_SHIFT 3 +#define HCRX_EL2_FnXS_WIDTH 1 + +#define HCRX_EL2_EnASR GENMASK(2, 2) +#define HCRX_EL2_EnASR_MASK GENMASK(2, 2) +#define HCRX_EL2_EnASR_SHIFT 2 +#define HCRX_EL2_EnASR_WIDTH 1 + +#define HCRX_EL2_EnALS GENMASK(1, 1) +#define HCRX_EL2_EnALS_MASK GENMASK(1, 1) +#define HCRX_EL2_EnALS_SHIFT 1 +#define HCRX_EL2_EnALS_WIDTH 1 + +#define HCRX_EL2_EnAS0 GENMASK(0, 0) +#define HCRX_EL2_EnAS0_MASK GENMASK(0, 0) +#define HCRX_EL2_EnAS0_SHIFT 0 +#define HCRX_EL2_EnAS0_WIDTH 1 + +#define HCRX_EL2_RES0 (UL(0) | GENMASK_ULL(63, 12)) +#define HCRX_EL2_RES1 (UL(0)) + +#define REG_SMPRIMAP_EL2 S3_4_C1_C2_5 +#define SYS_SMPRIMAP_EL2 sys_reg(3, 4, 1, 2, 5) +#define SYS_SMPRIMAP_EL2_Op0 3 +#define SYS_SMPRIMAP_EL2_Op1 4 +#define SYS_SMPRIMAP_EL2_CRn 1 +#define SYS_SMPRIMAP_EL2_CRm 2 +#define SYS_SMPRIMAP_EL2_Op2 5 + +#define SMPRIMAP_EL2_P15 GENMASK(63, 60) +#define SMPRIMAP_EL2_P15_MASK GENMASK(63, 60) +#define SMPRIMAP_EL2_P15_SHIFT 60 +#define SMPRIMAP_EL2_P15_WIDTH 4 + +#define SMPRIMAP_EL2_P14 GENMASK(59, 56) +#define SMPRIMAP_EL2_P14_MASK GENMASK(59, 56) +#define SMPRIMAP_EL2_P14_SHIFT 56 +#define SMPRIMAP_EL2_P14_WIDTH 4 + +#define SMPRIMAP_EL2_P13 GENMASK(55, 52) +#define SMPRIMAP_EL2_P13_MASK GENMASK(55, 52) +#define SMPRIMAP_EL2_P13_SHIFT 52 +#define SMPRIMAP_EL2_P13_WIDTH 4 + +#define SMPRIMAP_EL2_P12 GENMASK(51, 48) +#define SMPRIMAP_EL2_P12_MASK GENMASK(51, 48) +#define SMPRIMAP_EL2_P12_SHIFT 48 +#define SMPRIMAP_EL2_P12_WIDTH 4 + +#define SMPRIMAP_EL2_P11 GENMASK(47, 44) +#define SMPRIMAP_EL2_P11_MASK GENMASK(47, 44) +#define SMPRIMAP_EL2_P11_SHIFT 44 +#define SMPRIMAP_EL2_P11_WIDTH 4 + +#define SMPRIMAP_EL2_P10 GENMASK(43, 40) +#define SMPRIMAP_EL2_P10_MASK GENMASK(43, 40) +#define SMPRIMAP_EL2_P10_SHIFT 40 +#define SMPRIMAP_EL2_P10_WIDTH 4 + +#define SMPRIMAP_EL2_F9 GENMASK(39, 36) +#define SMPRIMAP_EL2_F9_MASK GENMASK(39, 36) +#define SMPRIMAP_EL2_F9_SHIFT 36 +#define SMPRIMAP_EL2_F9_WIDTH 4 + +#define SMPRIMAP_EL2_P8 GENMASK(35, 32) +#define SMPRIMAP_EL2_P8_MASK GENMASK(35, 32) +#define SMPRIMAP_EL2_P8_SHIFT 32 +#define SMPRIMAP_EL2_P8_WIDTH 4 + +#define SMPRIMAP_EL2_P7 GENMASK(31, 28) +#define SMPRIMAP_EL2_P7_MASK GENMASK(31, 28) +#define SMPRIMAP_EL2_P7_SHIFT 28 +#define SMPRIMAP_EL2_P7_WIDTH 4 + +#define SMPRIMAP_EL2_P6 GENMASK(27, 24) +#define SMPRIMAP_EL2_P6_MASK GENMASK(27, 24) +#define SMPRIMAP_EL2_P6_SHIFT 24 +#define SMPRIMAP_EL2_P6_WIDTH 4 + +#define SMPRIMAP_EL2_P5 GENMASK(23, 20) +#define SMPRIMAP_EL2_P5_MASK GENMASK(23, 20) +#define SMPRIMAP_EL2_P5_SHIFT 20 +#define SMPRIMAP_EL2_P5_WIDTH 4 + +#define SMPRIMAP_EL2_P4 GENMASK(19, 16) +#define SMPRIMAP_EL2_P4_MASK GENMASK(19, 16) +#define SMPRIMAP_EL2_P4_SHIFT 16 +#define SMPRIMAP_EL2_P4_WIDTH 4 + +#define SMPRIMAP_EL2_P3 GENMASK(15, 12) +#define SMPRIMAP_EL2_P3_MASK GENMASK(15, 12) +#define SMPRIMAP_EL2_P3_SHIFT 12 +#define SMPRIMAP_EL2_P3_WIDTH 4 + +#define SMPRIMAP_EL2_P2 GENMASK(11, 8) +#define SMPRIMAP_EL2_P2_MASK GENMASK(11, 8) +#define SMPRIMAP_EL2_P2_SHIFT 8 +#define SMPRIMAP_EL2_P2_WIDTH 4 + +#define SMPRIMAP_EL2_P1 GENMASK(7, 4) +#define SMPRIMAP_EL2_P1_MASK GENMASK(7, 4) +#define SMPRIMAP_EL2_P1_SHIFT 4 +#define SMPRIMAP_EL2_P1_WIDTH 4 + +#define SMPRIMAP_EL2_P0 GENMASK(3, 0) +#define SMPRIMAP_EL2_P0_MASK GENMASK(3, 0) +#define SMPRIMAP_EL2_P0_SHIFT 0 +#define SMPRIMAP_EL2_P0_WIDTH 4 + +#define SMPRIMAP_EL2_RES0 (UL(0)) +#define SMPRIMAP_EL2_RES1 (UL(0)) + +#define REG_SMCR_EL2 S3_4_C1_C2_6 +#define SYS_SMCR_EL2 sys_reg(3, 4, 1, 2, 6) +#define SYS_SMCR_EL2_Op0 3 +#define SYS_SMCR_EL2_Op1 4 +#define SYS_SMCR_EL2_CRn 1 +#define SYS_SMCR_EL2_CRm 2 +#define SYS_SMCR_EL2_Op2 6 + +/* For SMCR_EL2 fields see SMCR_ELx */ + +#define REG_DACR32_EL2 S3_4_C3_C0_0 +#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) +#define SYS_DACR32_EL2_Op0 3 +#define SYS_DACR32_EL2_Op1 4 +#define SYS_DACR32_EL2_CRn 3 +#define SYS_DACR32_EL2_CRm 0 +#define SYS_DACR32_EL2_Op2 0 + +#define DACR32_EL2_D15 GENMASK(31, 30) +#define DACR32_EL2_D15_MASK GENMASK(31, 30) +#define DACR32_EL2_D15_SHIFT 30 +#define DACR32_EL2_D15_WIDTH 2 + +#define DACR32_EL2_D14 GENMASK(29, 28) +#define DACR32_EL2_D14_MASK GENMASK(29, 28) +#define DACR32_EL2_D14_SHIFT 28 +#define DACR32_EL2_D14_WIDTH 2 + +#define DACR32_EL2_D13 GENMASK(27, 26) +#define DACR32_EL2_D13_MASK GENMASK(27, 26) +#define DACR32_EL2_D13_SHIFT 26 +#define DACR32_EL2_D13_WIDTH 2 + +#define DACR32_EL2_D12 GENMASK(25, 24) +#define DACR32_EL2_D12_MASK GENMASK(25, 24) +#define DACR32_EL2_D12_SHIFT 24 +#define DACR32_EL2_D12_WIDTH 2 + +#define DACR32_EL2_D11 GENMASK(23, 22) +#define DACR32_EL2_D11_MASK GENMASK(23, 22) +#define DACR32_EL2_D11_SHIFT 22 +#define DACR32_EL2_D11_WIDTH 2 + +#define DACR32_EL2_D10 GENMASK(21, 20) +#define DACR32_EL2_D10_MASK GENMASK(21, 20) +#define DACR32_EL2_D10_SHIFT 20 +#define DACR32_EL2_D10_WIDTH 2 + +#define DACR32_EL2_D9 GENMASK(19, 18) +#define DACR32_EL2_D9_MASK GENMASK(19, 18) +#define DACR32_EL2_D9_SHIFT 18 +#define DACR32_EL2_D9_WIDTH 2 + +#define DACR32_EL2_D8 GENMASK(17, 16) +#define DACR32_EL2_D8_MASK GENMASK(17, 16) +#define DACR32_EL2_D8_SHIFT 16 +#define DACR32_EL2_D8_WIDTH 2 + +#define DACR32_EL2_D7 GENMASK(15, 14) +#define DACR32_EL2_D7_MASK GENMASK(15, 14) +#define DACR32_EL2_D7_SHIFT 14 +#define DACR32_EL2_D7_WIDTH 2 + +#define DACR32_EL2_D6 GENMASK(13, 12) +#define DACR32_EL2_D6_MASK GENMASK(13, 12) +#define DACR32_EL2_D6_SHIFT 12 +#define DACR32_EL2_D6_WIDTH 2 + +#define DACR32_EL2_D5 GENMASK(11, 10) +#define DACR32_EL2_D5_MASK GENMASK(11, 10) +#define DACR32_EL2_D5_SHIFT 10 +#define DACR32_EL2_D5_WIDTH 2 + +#define DACR32_EL2_D4 GENMASK(9, 8) +#define DACR32_EL2_D4_MASK GENMASK(9, 8) +#define DACR32_EL2_D4_SHIFT 8 +#define DACR32_EL2_D4_WIDTH 2 + +#define DACR32_EL2_D3 GENMASK(7, 6) +#define DACR32_EL2_D3_MASK GENMASK(7, 6) +#define DACR32_EL2_D3_SHIFT 6 +#define DACR32_EL2_D3_WIDTH 2 + +#define DACR32_EL2_D2 GENMASK(5, 4) +#define DACR32_EL2_D2_MASK GENMASK(5, 4) +#define DACR32_EL2_D2_SHIFT 4 +#define DACR32_EL2_D2_WIDTH 2 + +#define DACR32_EL2_D1 GENMASK(3, 2) +#define DACR32_EL2_D1_MASK GENMASK(3, 2) +#define DACR32_EL2_D1_SHIFT 2 +#define DACR32_EL2_D1_WIDTH 2 + +#define DACR32_EL2_D0 GENMASK(1, 0) +#define DACR32_EL2_D0_MASK GENMASK(1, 0) +#define DACR32_EL2_D0_SHIFT 0 +#define DACR32_EL2_D0_WIDTH 2 + +#define DACR32_EL2_RES0 (UL(0) | GENMASK_ULL(63, 32)) +#define DACR32_EL2_RES1 (UL(0)) + +#define REG_FAR_EL2 S3_4_C6_C0_0 +#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) +#define SYS_FAR_EL2_Op0 3 +#define SYS_FAR_EL2_Op1 4 +#define SYS_FAR_EL2_CRn 6 +#define SYS_FAR_EL2_CRm 0 +#define SYS_FAR_EL2_Op2 0 + +#define FAR_EL2_ADDR GENMASK(63, 0) +#define FAR_EL2_ADDR_MASK GENMASK(63, 0) +#define FAR_EL2_ADDR_SHIFT 0 +#define FAR_EL2_ADDR_WIDTH 64 + +#define FAR_EL2_RES0 (UL(0)) +#define FAR_EL2_RES1 (UL(0)) + +#define REG_CONTEXTIDR_EL2 S3_4_C13_C0_1 +#define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1) +#define SYS_CONTEXTIDR_EL2_Op0 3 +#define SYS_CONTEXTIDR_EL2_Op1 4 +#define SYS_CONTEXTIDR_EL2_CRn 13 +#define SYS_CONTEXTIDR_EL2_CRm 0 +#define SYS_CONTEXTIDR_EL2_Op2 1 + +/* For CONTEXTIDR_EL2 fields see CONTEXTIDR_ELx */ + +#define REG_CPACR_EL12 S3_5_C1_C0_2 +#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) +#define SYS_CPACR_EL12_Op0 3 +#define SYS_CPACR_EL12_Op1 5 +#define SYS_CPACR_EL12_CRn 1 +#define SYS_CPACR_EL12_CRm 0 +#define SYS_CPACR_EL12_Op2 2 + +/* For CPACR_EL12 fields see CPACR_ELx */ + +#define REG_ZCR_EL12 S3_5_C1_C2_0 +#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) +#define SYS_ZCR_EL12_Op0 3 +#define SYS_ZCR_EL12_Op1 5 +#define SYS_ZCR_EL12_CRn 1 +#define SYS_ZCR_EL12_CRm 2 +#define SYS_ZCR_EL12_Op2 0 + +/* For ZCR_EL12 fields see ZCR_ELx */ + +#define REG_SMCR_EL12 S3_5_C1_C2_6 +#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6) +#define SYS_SMCR_EL12_Op0 3 +#define SYS_SMCR_EL12_Op1 5 +#define SYS_SMCR_EL12_CRn 1 +#define SYS_SMCR_EL12_CRm 2 +#define SYS_SMCR_EL12_Op2 6 + +/* For SMCR_EL12 fields see SMCR_ELx */ + +#define REG_FAR_EL12 S3_5_C6_C0_0 +#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) +#define SYS_FAR_EL12_Op0 3 +#define SYS_FAR_EL12_Op1 5 +#define SYS_FAR_EL12_CRn 6 +#define SYS_FAR_EL12_CRm 0 +#define SYS_FAR_EL12_Op2 0 + +#define FAR_EL12_ADDR GENMASK(63, 0) +#define FAR_EL12_ADDR_MASK GENMASK(63, 0) +#define FAR_EL12_ADDR_SHIFT 0 +#define FAR_EL12_ADDR_WIDTH 64 + +#define FAR_EL12_RES0 (UL(0)) +#define FAR_EL12_RES1 (UL(0)) + +#define REG_CONTEXTIDR_EL12 S3_5_C13_C0_1 +#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1) +#define SYS_CONTEXTIDR_EL12_Op0 3 +#define SYS_CONTEXTIDR_EL12_Op1 5 +#define SYS_CONTEXTIDR_EL12_CRn 13 +#define SYS_CONTEXTIDR_EL12_CRm 0 +#define SYS_CONTEXTIDR_EL12_Op2 1 + +/* For CONTEXTIDR_EL12 fields see CONTEXTIDR_ELx */ + +#define TTBRx_EL1_ASID GENMASK(63, 48) +#define TTBRx_EL1_ASID_MASK GENMASK(63, 48) +#define TTBRx_EL1_ASID_SHIFT 48 +#define TTBRx_EL1_ASID_WIDTH 16 + +#define TTBRx_EL1_BADDR GENMASK(47, 1) +#define TTBRx_EL1_BADDR_MASK GENMASK(47, 1) +#define TTBRx_EL1_BADDR_SHIFT 1 +#define TTBRx_EL1_BADDR_WIDTH 47 + +#define TTBRx_EL1_CnP GENMASK(0, 0) +#define TTBRx_EL1_CnP_MASK GENMASK(0, 0) +#define TTBRx_EL1_CnP_SHIFT 0 +#define TTBRx_EL1_CnP_WIDTH 1 + +#define TTBRx_EL1_RES0 (UL(0)) +#define TTBRx_EL1_RES1 (UL(0)) + +#define REG_TTBR0_EL1 S3_0_C2_C0_0 +#define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) +#define SYS_TTBR0_EL1_Op0 3 +#define SYS_TTBR0_EL1_Op1 0 +#define SYS_TTBR0_EL1_CRn 2 +#define SYS_TTBR0_EL1_CRm 0 +#define SYS_TTBR0_EL1_Op2 0 + +/* For TTBR0_EL1 fields see TTBRx_EL1 */ + +#define REG_TTBR1_EL1 S3_0_C2_C0_1 +#define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) +#define SYS_TTBR1_EL1_Op0 3 +#define SYS_TTBR1_EL1_Op1 0 +#define SYS_TTBR1_EL1_CRn 2 +#define SYS_TTBR1_EL1_CRm 0 +#define SYS_TTBR1_EL1_Op2 1 + +/* For TTBR1_EL1 fields see TTBRx_EL1 */ + +#define REG_LORSA_EL1 S3_0_C10_C4_0 +#define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) +#define SYS_LORSA_EL1_Op0 3 +#define SYS_LORSA_EL1_Op1 0 +#define SYS_LORSA_EL1_CRn 10 +#define SYS_LORSA_EL1_CRm 4 +#define SYS_LORSA_EL1_Op2 0 + +#define LORSA_EL1_SA GENMASK(51, 16) +#define LORSA_EL1_SA_MASK GENMASK(51, 16) +#define LORSA_EL1_SA_SHIFT 16 +#define LORSA_EL1_SA_WIDTH 36 + +#define LORSA_EL1_Valid GENMASK(0, 0) +#define LORSA_EL1_Valid_MASK GENMASK(0, 0) +#define LORSA_EL1_Valid_SHIFT 0 +#define LORSA_EL1_Valid_WIDTH 1 + +#define LORSA_EL1_RES0 (UL(0) | GENMASK_ULL(63, 52) | GENMASK_ULL(15, 1)) +#define LORSA_EL1_RES1 (UL(0)) + +#define REG_LOREA_EL1 S3_0_C10_C4_1 +#define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) +#define SYS_LOREA_EL1_Op0 3 +#define SYS_LOREA_EL1_Op1 0 +#define SYS_LOREA_EL1_CRn 10 +#define SYS_LOREA_EL1_CRm 4 +#define SYS_LOREA_EL1_Op2 1 + +#define LOREA_EL1_EA_51_48 GENMASK(51, 48) +#define LOREA_EL1_EA_51_48_MASK GENMASK(51, 48) +#define LOREA_EL1_EA_51_48_SHIFT 48 +#define LOREA_EL1_EA_51_48_WIDTH 4 + +#define LOREA_EL1_EA_47_16 GENMASK(47, 16) +#define LOREA_EL1_EA_47_16_MASK GENMASK(47, 16) +#define LOREA_EL1_EA_47_16_SHIFT 16 +#define LOREA_EL1_EA_47_16_WIDTH 32 + +#define LOREA_EL1_RES0 (UL(0) | GENMASK_ULL(63, 52) | GENMASK_ULL(15, 0)) +#define LOREA_EL1_RES1 (UL(0)) + +#define REG_LORN_EL1 S3_0_C10_C4_2 +#define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) +#define SYS_LORN_EL1_Op0 3 +#define SYS_LORN_EL1_Op1 0 +#define SYS_LORN_EL1_CRn 10 +#define SYS_LORN_EL1_CRm 4 +#define SYS_LORN_EL1_Op2 2 + +#define LORN_EL1_Num GENMASK(7, 0) +#define LORN_EL1_Num_MASK GENMASK(7, 0) +#define LORN_EL1_Num_SHIFT 0 +#define LORN_EL1_Num_WIDTH 8 + +#define LORN_EL1_RES0 (UL(0) | GENMASK_ULL(63, 8)) +#define LORN_EL1_RES1 (UL(0)) + +#define REG_LORC_EL1 S3_0_C10_C4_3 +#define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) +#define SYS_LORC_EL1_Op0 3 +#define SYS_LORC_EL1_Op1 0 +#define SYS_LORC_EL1_CRn 10 +#define SYS_LORC_EL1_CRm 4 +#define SYS_LORC_EL1_Op2 3 + +#define LORC_EL1_DS GENMASK(9, 2) +#define LORC_EL1_DS_MASK GENMASK(9, 2) +#define LORC_EL1_DS_SHIFT 2 +#define LORC_EL1_DS_WIDTH 8 + +#define LORC_EL1_EN GENMASK(0, 0) +#define LORC_EL1_EN_MASK GENMASK(0, 0) +#define LORC_EL1_EN_SHIFT 0 +#define LORC_EL1_EN_WIDTH 1 + +#define LORC_EL1_RES0 (UL(0) | GENMASK_ULL(63, 10) | GENMASK_ULL(1, 1)) +#define LORC_EL1_RES1 (UL(0)) + +#define REG_LORID_EL1 S3_0_C10_C4_7 +#define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) +#define SYS_LORID_EL1_Op0 3 +#define SYS_LORID_EL1_Op1 0 +#define SYS_LORID_EL1_CRn 10 +#define SYS_LORID_EL1_CRm 4 +#define SYS_LORID_EL1_Op2 7 + +#define LORID_EL1_LD GENMASK(23, 16) +#define LORID_EL1_LD_MASK GENMASK(23, 16) +#define LORID_EL1_LD_SHIFT 16 +#define LORID_EL1_LD_WIDTH 8 + +#define LORID_EL1_LR GENMASK(7, 0) +#define LORID_EL1_LR_MASK GENMASK(7, 0) +#define LORID_EL1_LR_SHIFT 0 +#define LORID_EL1_LR_WIDTH 8 + +#define LORID_EL1_RES0 (UL(0) | GENMASK_ULL(63, 24) | GENMASK_ULL(15, 8)) +#define LORID_EL1_RES1 (UL(0)) + +#endif /* __ASM_SYSREG_DEFS_H */ diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/trace_clock.h linux/arch/arm64/include/generated/asm/trace_clock.h --- linux-6.1.66/arch/arm64/include/generated/asm/trace_clock.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/trace_clock.h 2023-12-14 11:56:01.533665416 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/trace_clock.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/unaligned.h linux/arch/arm64/include/generated/asm/unaligned.h --- linux-6.1.66/arch/arm64/include/generated/asm/unaligned.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/unaligned.h 2023-12-14 11:56:01.535665420 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/unaligned.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/user.h linux/arch/arm64/include/generated/asm/user.h --- linux-6.1.66/arch/arm64/include/generated/asm/user.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/user.h 2023-12-14 11:56:01.517665380 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/user.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/asm/vga.h linux/arch/arm64/include/generated/asm/vga.h --- linux-6.1.66/arch/arm64/include/generated/asm/vga.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/asm/vga.h 2023-12-14 11:56:01.536665422 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/vga.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/errno.h linux/arch/arm64/include/generated/uapi/asm/errno.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/errno.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/errno.h 2023-12-14 11:56:01.387665090 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/errno.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/ioctl.h linux/arch/arm64/include/generated/uapi/asm/ioctl.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/ioctl.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/ioctl.h 2023-12-14 11:56:01.388665093 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/ioctl.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/ioctls.h linux/arch/arm64/include/generated/uapi/asm/ioctls.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/ioctls.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/ioctls.h 2023-12-14 11:56:01.389665095 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/ioctls.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/ipcbuf.h linux/arch/arm64/include/generated/uapi/asm/ipcbuf.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/ipcbuf.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/ipcbuf.h 2023-12-14 11:56:01.389665095 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/ipcbuf.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/kvm_para.h linux/arch/arm64/include/generated/uapi/asm/kvm_para.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/kvm_para.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/kvm_para.h 2023-12-14 11:56:01.386665088 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/kvm_para.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/msgbuf.h linux/arch/arm64/include/generated/uapi/asm/msgbuf.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/msgbuf.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/msgbuf.h 2023-12-14 11:56:01.390665097 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/msgbuf.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/poll.h linux/arch/arm64/include/generated/uapi/asm/poll.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/poll.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/poll.h 2023-12-14 11:56:01.391665099 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/poll.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/resource.h linux/arch/arm64/include/generated/uapi/asm/resource.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/resource.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/resource.h 2023-12-14 11:56:01.392665102 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/resource.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/sembuf.h linux/arch/arm64/include/generated/uapi/asm/sembuf.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/sembuf.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/sembuf.h 2023-12-14 11:56:01.393665104 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/sembuf.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/shmbuf.h linux/arch/arm64/include/generated/uapi/asm/shmbuf.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/shmbuf.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/shmbuf.h 2023-12-14 11:56:01.394665106 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/shmbuf.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/siginfo.h linux/arch/arm64/include/generated/uapi/asm/siginfo.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/siginfo.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/siginfo.h 2023-12-14 11:56:01.395665108 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/siginfo.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/socket.h linux/arch/arm64/include/generated/uapi/asm/socket.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/socket.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/socket.h 2023-12-14 11:56:01.396665111 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/socket.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/sockios.h linux/arch/arm64/include/generated/uapi/asm/sockios.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/sockios.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/sockios.h 2023-12-14 11:56:01.397665113 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/sockios.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/stat.h linux/arch/arm64/include/generated/uapi/asm/stat.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/stat.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/stat.h 2023-12-14 11:56:01.398665115 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/stat.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/swab.h linux/arch/arm64/include/generated/uapi/asm/swab.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/swab.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/swab.h 2023-12-14 11:56:01.399665117 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/swab.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/termbits.h linux/arch/arm64/include/generated/uapi/asm/termbits.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/termbits.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/termbits.h 2023-12-14 11:56:01.400665119 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/termbits.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/termios.h linux/arch/arm64/include/generated/uapi/asm/termios.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/termios.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/termios.h 2023-12-14 11:56:01.401665122 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/termios.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/include/generated/uapi/asm/types.h linux/arch/arm64/include/generated/uapi/asm/types.h --- linux-6.1.66/arch/arm64/include/generated/uapi/asm/types.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/include/generated/uapi/asm/types.h 2023-12-14 11:56:01.402665124 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +#include <asm-generic/types.h> diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/kernel/armv8_deprecated.c linux/arch/arm64/kernel/armv8_deprecated.c --- linux-6.1.66/arch/arm64/kernel/armv8_deprecated.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm64/kernel/armv8_deprecated.c 2023-12-13 11:50:49.618963672 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:186 @ switch (ops->status) { case INSN_DEPRECATED: +#if 0 insn->current_mode = INSN_EMULATE; /* Disable the HW mode if it was turned on at early boot time */ run_all_cpu_set_hw_mode(insn, false); +#else + insn->current_mode = INSN_HW; + run_all_cpu_set_hw_mode(insn, true); insn->max = INSN_HW; +#endif break; case INSN_OBSOLETE: insn->current_mode = INSN_UNDEF; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/kernel/cpuinfo.c linux/arch/arm64/kernel/cpuinfo.c --- linux-6.1.66/arch/arm64/kernel/cpuinfo.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm64/kernel/cpuinfo.c 2023-12-13 11:50:49.622963681 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:20 @ #include <linux/elf.h> #include <linux/init.h> #include <linux/kernel.h> +#include <linux/of_platform.h> #include <linux/personality.h> #include <linux/preempt.h> #include <linux/printk.h> @ linux/arch/arm/boot/dts/bcm2708.dtsi:163 @ { int i, j; bool compat = personality(current->personality) == PER_LINUX32; + struct device_node *np; + const char *model; + const char *serial; + u32 revision; for_each_online_cpu(i) { struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); @ linux/arch/arm/boot/dts/bcm2708.dtsi:227 @ seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); } + np = of_find_node_by_path("/system"); + if (np) { + if (!of_property_read_u32(np, "linux,revision", &revision)) + seq_printf(m, "Revision\t: %04x\n", revision); + of_node_put(np); + } + + np = of_find_node_by_path("/"); + if (np) { + if (!of_property_read_string(np, "serial-number", + &serial)) + seq_printf(m, "Serial\t\t: %s\n", serial); + if (!of_property_read_string(np, "model", + &model)) + seq_printf(m, "Model\t\t: %s\n", model); + of_node_put(np); + } + return 0; } diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/kernel/process.c linux/arch/arm64/kernel/process.c --- linux-6.1.66/arch/arm64/kernel/process.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm64/kernel/process.c 2023-12-13 11:50:49.634963710 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:99 @ */ void machine_halt(void) { - local_irq_disable(); - smp_send_stop(); - while (1); + machine_power_off(); } /* diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/kernel/setup.c linux/arch/arm64/kernel/setup.c --- linux-6.1.66/arch/arm64/kernel/setup.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/arch/arm64/kernel/setup.c 2023-12-13 11:50:49.637963717 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:225 @ size_t res_size; kernel_code.start = __pa_symbol(_stext); - kernel_code.end = __pa_symbol(__init_begin - 1); + kernel_code.end = __pa_symbol(__init_begin) - 1; kernel_data.start = __pa_symbol(_sdata); - kernel_data.end = __pa_symbol(_end - 1); + kernel_data.end = __pa_symbol(_end) - 1; insert_resource(&iomem_resource, &kernel_code); insert_resource(&iomem_resource, &kernel_data); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/kernel/vdso/vdso.lds linux/arch/arm64/kernel/vdso/vdso.lds --- linux-6.1.66/arch/arm64/kernel/vdso/vdso.lds 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/kernel/vdso/vdso.lds 2023-12-14 14:24:51.238320730 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * This header exists to force full rebuild when the compiler is upgraded. + * + * When fixdep scans this, it will find this string "CONFIG_CC_VERSION_TEXT" + * and add dependency on include/config/CC_VERSION_TEXT, which is touched + * by Kconfig when the version string from the compiler changes. + */ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Automatically generated file; DO NOT EDIT. + * Linux/arm64 6.1.66 Kernel Configuration + */ +/* + * The use of "&&" / "||" is limited in certain expressions. + * The following enable to calculate "and" / "or" with macro expansion only. + */ +/* + * Helper macros to use CONFIG_ options in C/CPP expressions. Note that + * these only work with boolean and tristate options. + */ +/* + * Getting something that works in C and CPP for an arg that may or may + * not be defined is tricky. Here, if we have "#define CONFIG_BOOGER 1" + * we match on the placeholder define, insert the "0," for arg1 and generate + * the triplet (0, 1, 0). Then the last step cherry picks the 2nd arg (a one). + * When CONFIG_BOOGER is not defined, we generate a (... 1, 0) pair, and when + * the last step cherry picks the 2nd arg, we get a zero. + */ +/* + * IS_BUILTIN(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'y', 0 + * otherwise. For boolean options, this is equivalent to + * IS_ENABLED(CONFIG_FOO). + */ +/* + * IS_MODULE(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'm', 0 + * otherwise. CONFIG_FOO=m results in "#define CONFIG_FOO_MODULE 1" in + * autoconf.h. + */ +/* + * IS_REACHABLE(CONFIG_FOO) evaluates to 1 if the currently compiled + * code can call a function defined in code compiled based on CONFIG_FOO. + * This is similar to IS_ENABLED(), but returns false when invoked from + * built-in code when CONFIG_FOO is set to 'm'. + */ +/* + * IS_ENABLED(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'y' or 'm', + * 0 otherwise. Note that CONFIG_FOO=y results in "#define CONFIG_FOO 1" in + * autoconf.h, while CONFIG_FOO=m results in "#define CONFIG_FOO_MODULE 1". + */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * GNU linker script for the VDSO library. +* + * Copyright (C) 2012 ARM Limited + * + * Author: Will Deacon <will.deacon@arm.com> + * Heavily based on the vDSO linker scripts for other archs. + */ +/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* const.h: Macros for dealing with constants. */ +/* Some constant macros are used in both assembler and + * C code. Therefore we cannot annotate them always with + * 'UL' and other type specifiers unilaterally. We + * use the following macros to deal with this. + * + * Similarly, _AT() will cast an expression with a type in C, but + * leave it unchanged in asm. + */ +/* + * This returns a constant expression while determining if an argument is + * a constant expression, most importantly without evaluating the argument. + * Glory to Martin Uecker <Martin.Uecker@med.uni-goettingen.de> + */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Based on arch/arm/include/asm/page.h + * + * Copyright (C) 1995-2003 Russell King + * Copyright (C) 2012 ARM Ltd. + */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Based on arch/arm/include/asm/page.h + * + * Copyright (C) 1995-2003 Russell King + * Copyright (C) 2017 ARM Ltd. + */ +/* PAGE_SHIFT determines the page size */ +/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2012 ARM Limited + */ +/* + * Default link address for the vDSO. + * Since we randomise the VDSO mapping, there's little point in trying + * to prelink this. + */ +/* + * Helper macros to support writing architecture specific + * linker scripts. + * + * A minimal linker scripts has following content: + * [This is a sample, architectures may have special requiriements] + * + * OUTPUT_FORMAT(...) + * OUTPUT_ARCH(...) + * ENTRY(...) + * SECTIONS + * { + * . = START; + * __init_begin = .; + * HEAD_TEXT_SECTION + * INIT_TEXT_SECTION(PAGE_SIZE) + * INIT_DATA_SECTION(...) + * PERCPU_SECTION(CACHELINE_SIZE) + * __init_end = .; + * + * _stext = .; + * TEXT_SECTION = 0 + * _etext = .; + * + * _sdata = .; + * RO_DATA(PAGE_SIZE) + * RW_DATA(...) + * _edata = .; + * + * EXCEPTION_TABLE(...) + * + * BSS_SECTION(0, 0, 0) + * _end = .; + * + * STABS_DEBUG + * DWARF_DEBUG + * ELF_DETAILS + * + * DISCARDS // must be the last + * } + * + * [__init_begin, __init_end] is the init section that may be freed after init + * // __init_begin and __init_end should be page aligned, so that we can + * // free the whole .init memory + * [_stext, _etext] is the text section + * [_sdata, _edata] is the data section + * + * Some of the included output section have their own set of constants. + * Examples are: [__initramfs_start, __initramfs_end] for initramfs and + * [__nosave_begin, __nosave_end] for the nosave data + */ +/* + * Only some architectures want to have the .notes segment visible in + * a separate PT_NOTE ELF Program Header. When this happens, it needs + * to be visible in both the kernel text's PT_LOAD and the PT_NOTE + * Program Headers. In this case, though, the PT_LOAD needs to be made + * the default again so that all the following sections don't also end + * up in the PT_NOTE Program Header. + */ +/* + * Some architectures have non-executable read-only exception tables. + * They can be added to the RO_DATA segment by specifying their desired + * alignment. + */ +/* Align . to a 8 byte boundary equals to maximum function alignment. */ +/* + * LD_DEAD_CODE_DATA_ELIMINATION option enables -fdata-sections, which + * generates .data.identifier sections, which need to be pulled in with + * .data. We don't want to pull in .data..other sections, which Linux + * has defined. Same for text and bss. + * + * With LTO_CLANG, the linker also splits sections by default, so we need + * these macros to combine the sections during the final link. + * + * RODATA_MAIN is not used because existing code already defines .rodata.x + * sections to be brought in with rodata. + */ +/* + * GCC 4.5 and later have a 32 bytes section alignment for structures. + * Except GCC 4.9, that feels the need to align on 64 bytes. + */ +/* + * The order of the sched class addresses are important, as they are + * used to determine the order of the priority of each sched class in + * relation to each other. + */ +/* The actual configuration determine if the init/exit sections + * are handled as text/data or they can be discarded (which + * often happens at runtime) + */ +/* + * The ftrace call sites are logged to a section whose name depends on the + * compiler option used. A given kernel image will only use one, AKA + * FTRACE_CALLSITE_SECTION. We capture all of them here to avoid header + * dependencies for FTRACE_CALLSITE_SECTION's definition. + * + * ftrace_ops_list_func will be defined as arch_ftrace_ops_list_func + * as some archs will have a different prototype for that function + * but ftrace_ops_list_func() will have a single prototype. + */ +/* + * .data section + */ +/* + * Data section helpers + */ +/* + * Allow architectures to handle ro_after_init data on their + * own by defining an empty RO_AFTER_INIT_DATA. + */ +/* + * .kcfi_traps contains a list KCFI trap locations. + */ +/* + * Read only Data + */ +/* + * Non-instrumentable text section + */ +/* + * .text section. Map to function alignment to avoid address changes + * during second ld run in second ld pass when generating System.map + * + * TEXT_MAIN here will match .text.fixup and .text.unlikely if dead + * code elimination is enabled, so these sections should be converted + * to use ".." first. + */ +/* sched.text is aling to function alignment to secure we have same + * address even at second ld pass when generating System.map */ +/* spinlock.text is aling to function alignment to secure we have same + * address even at second ld pass when generating System.map */ +/* Section used for early init (in .S files) */ +/* + * Exception table + */ +/* + * .BTF + */ +/* + * Init task + */ +/* init and exit section handling */ +/* + * bss (Block Started by Symbol) - uninitialized data + * zeroed during startup + */ +/* + * Allow archectures to redefine BSS_FIRST_SECTIONS to add extra + * sections to the front of bss. + */ +/* + * DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to + * the beginning of the section so we begin them at 0. + */ +/* Stabs debugging sections. */ +/* Required sections not related to debugging. */ +/* Built-in firmware blobs */ +/* + * Discard .note.GNU-stack, which is emitted as PROGBITS by the compiler. + * Otherwise, the type of .notes section would become PROGBITS instead of NOTES. + */ +/* Alignment must be consistent with (kunit_suite *) in include/kunit/test.h */ +/* + * Memory encryption operates on a page basis. Since we need to clear + * the memory encryption mask for this section, it needs to be aligned + * on a page boundary and be a page-size multiple in length. + * + * Note: We use a separate section so that only this section gets + * decrypted to avoid exposing more than we wish. + */ +/* + * Default discarded sections. + * + * Some archs want to discard exit text/data at runtime rather than + * link time due to cross-section references such as alt instructions, + * bug table, eh_frame, etc. DISCARDS must be the last of output + * section definitions so that such archs put those in earlier section + * definitions. + */ +/* + * Clang's -fprofile-arcs, -fsanitize=kernel-address, and + * -fsanitize=thread produce unwanted sections (.eh_frame + * and .init_array.*), but CONFIG_CONSTRUCTORS wants to + * keep any .init_array.* sections. + * https://bugs.llvm.org/show_bug.cgi?id=46478 + */ +/** + * PERCPU_INPUT - the percpu input sections + * @cacheline: cacheline size + * + * The core percpu section names and core symbols which do not rely + * directly upon load addresses. + * + * @cacheline is used to align subsections to avoid false cacheline + * sharing between subsections for different purposes. + */ +/** + * PERCPU_VADDR - define output section for percpu area + * @cacheline: cacheline size + * @vaddr: explicit base address (optional) + * @phdr: destination PHDR (optional) + * + * Macro which expands to output section for percpu area. + * + * @cacheline is used to align subsections to avoid false cacheline + * sharing between subsections for different purposes. + * + * If @vaddr is not blank, it specifies explicit base address and all + * percpu symbols will be offset from the given address. If blank, + * @vaddr always equals @laddr + LOAD_OFFSET. + * + * @phdr defines the output PHDR to use if not blank. Be warned that + * output PHDR is sticky. If @phdr is specified, the next output + * section in the linker script will go there too. @phdr should have + * a leading colon. + * + * Note that this macros defines __per_cpu_load as an absolute symbol. + * If there is no need to put the percpu section at a predetermined + * address, use PERCPU_SECTION. + */ +/** + * PERCPU_SECTION - define output section for percpu area, simple version + * @cacheline: cacheline size + * + * Align to PAGE_SIZE and outputs output section for percpu area. This + * macro doesn't manipulate @vaddr or @phdr and __per_cpu_load and + * __per_cpu_start will be identical. + * + * This macro is equivalent to ALIGN(PAGE_SIZE); PERCPU_VADDR(@cacheline,,) + * except that __per_cpu_load is defined as a relative symbol against + * .data..percpu which is required for relocatable x86_32 configuration. + */ +/* + * Definition of the high level *_SECTION macros + * They will fit only a subset of the architectures + */ +/* + * Writeable data. + * All sections are combined in a single .data section. + * The sections following CONSTRUCTORS are arranged so their + * typical alignment matches. + * A cacheline is typical/always less than a PAGE_SIZE so + * the sections that has this restriction (or similar) + * is located before the ones requiring PAGE_SIZE alignment. + * NOSAVE_DATA starts and ends with a PAGE_SIZE alignment which + * matches the requirement of PAGE_ALIGNED_DATA. + * + * use 0 as page_align if page_aligned data is not used */ +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-bigaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +SECTIONS +{ + PROVIDE(_vdso_data = . - 2 * (1 << 14)); + PROVIDE(_timens_data = _vdso_data + (1 << 14)); + . = 0x0 + SIZEOF_HEADERS; + .hash : { *(.hash) } :text + .gnu.hash : { *(.gnu.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + /* + * Discard .note.gnu.property sections which are unused and have + * different alignment requirement from vDSO note sections. + */ + /DISCARD/ : { + *(.note.GNU-stack .note.gnu.property) + } + .note : { *(.note.*) } :text :note + . = ALIGN(16); + .text : { *(.text*) } :text =0xd503201f + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + . = ALIGN(4); + .altinstructions : { + __alt_instructions = .; + *(.altinstructions) + __alt_instructions_end = .; + } + .dynamic : { *(.dynamic) } :text :dynamic + .rela.dyn : ALIGN(8) { *(.rela .rela*) } + .rodata : { + *(.rodata*) + *(.got) + *(.got.plt) + *(.plt) + *(.plt.*) + *(.iplt) + *(.igot .igot.plt) + } :text + _end = .; + PROVIDE(end = .); + .debug 0 : { *(.debug) } .line 0 : { *(.line) } .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } .debug_pubtypes 0 : { *(.debug_pubtypes) } .debug_ranges 0 : { *(.debug_ranges) } .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) } .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) } .debug_types 0 : { *(.debug_types) } .debug_addr 0 : { *(.debug_addr) } .debug_line_str 0 : { *(.debug_line_str) } .debug_loclists 0 : { *(.debug_loclists) } .debug_macro 0 : { *(.debug_macro) } .debug_names 0 : { *(.debug_names) } .debug_rnglists 0 : { *(.debug_rnglists) } .debug_str_offsets 0 : { *(.debug_str_offsets) } + .comment 0 : { *(.comment) } .symtab 0 : { *(.symtab) } .strtab 0 : { *(.strtab) } .shstrtab 0 : { *(.shstrtab) } + /DISCARD/ : { + *(.data .data.* .gnu.linkonce.d.* .sdata*) + *(.bss .sbss .dynbss .dynsbss) + *(.eh_frame .eh_frame_hdr) + } +} +/* + * We must supply the ELF program headers explicitly to get just one + * PT_LOAD segment, and set the flags explicitly to make segments read-only. + */ +PHDRS +{ + text PT_LOAD FLAGS(5) FILEHDR PHDRS; /* PF_R|PF_X */ + dynamic PT_DYNAMIC FLAGS(4); /* PF_R */ + note PT_NOTE FLAGS(4); /* PF_R */ +} +/* + * This controls what symbols we export from the DSO. + */ +VERSION +{ + LINUX_2.6.39 { + global: + __kernel_rt_sigreturn; + __kernel_gettimeofday; + __kernel_clock_gettime; + __kernel_clock_getres; + local: *; + }; +} +/* + * Make the sigreturn code visible to the kernel. + */ +VDSO_sigtramp = __kernel_rt_sigreturn; Warning: `tput cols` did not return numeric input ──────────────────────────────────────────────────────────────────────────────── renamed: linux-6.1.66/arch/arm64/kernel/vdso/vdso.so to linux/arch/arm64/kernel/vdso/vdso.so (binary) ──────────────────────────────────────────────────────────────────────────────── ──────────────────────────────────────────────────────────────────────────────── renamed: linux-6.1.66/arch/arm64/kernel/vdso/vdso.so.dbg to linux/arch/arm64/kernel/vdso/vdso.so.dbg (binary) ──────────────────────────────────────────────────────────────────────────────── diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/kernel/vmlinux.lds linux/arch/arm64/kernel/vmlinux.lds --- linux-6.1.66/arch/arm64/kernel/vmlinux.lds 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/kernel/vmlinux.lds 2023-12-14 14:24:51.552321393 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +OUTPUT_ARCH(aarch64) +ENTRY(_text) +jiffies = jiffies_64; +PECOFF_FILE_ALIGNMENT = 0x200; +SECTIONS +{ + /DISCARD/ : { *(.exitcall.exit) *(.discard) *(.discard.*) *(.modinfo) *(.gnu.version*) } + /DISCARD/ : { + *(.interp .dynamic) + *(.dynsym .dynstr .hash .gnu.hash) + } + . = ((((-(((1)) << ((((47))) - 1)))) + (0x08000000))); + .head.text : { + _text = .; + KEEP(*(.head.text)) + } + .text : ALIGN(0x00010000) { + _stext = .; + . = ALIGN(8); __irqentry_text_start = .; *(.irqentry.text) __irqentry_text_end = .; + . = ALIGN(8); __softirqentry_text_start = .; *(.softirqentry.text) __softirqentry_text_end = .; + . = ALIGN(8); __entry_text_start = .; *(.entry.text) __entry_text_end = .; + . = ALIGN(8); *(.text.hot .text.hot.*) *(.text .text.fixup) *(.text.unlikely .text.unlikely.*) *(.text.unknown .text.unknown.*) . = ALIGN(8); __noinstr_text_start = .; *(.noinstr.text) __noinstr_text_end = .; *(.text..refcount) *(.ref.text) *(.text.asan.* .text.tsan.*) + . = ALIGN(8); __sched_text_start = .; *(.sched.text) __sched_text_end = .; + . = ALIGN(8); __cpuidle_text_start = .; *(.cpuidle.text) __cpuidle_text_end = .; + . = ALIGN(8); __lock_text_start = .; *(.spinlock.text) __lock_text_end = .; + . = ALIGN(8); __kprobes_text_start = .; *(.kprobes.text) __kprobes_text_end = .; + . = ALIGN((1 << 14)); __hyp_idmap_text_start = .; *(.hyp.idmap.text) __hyp_idmap_text_end = .; __hyp_text_start = .; *(.hyp.text) . = ALIGN(0x00000008); __start___kvm_ex_table = .; *(__kvm_ex_table) __stop___kvm_ex_table = .; . = ALIGN((1 << 14)); __hyp_text_end = .; + . = ALIGN(0x00001000); __idmap_text_start = .; *(.idmap.text) __idmap_text_end = .; + *(.gnu.warning) + . = ALIGN(16); + *(.got) + } + .got.plt : { *(.got.plt) } + ASSERT(SIZEOF(.got.plt) == 0 || SIZEOF(.got.plt) == 0x18, + "Unexpected GOT/PLT entries detected!") + . = ALIGN(0x00010000); + _etext = .; + . = ALIGN(((1 << 14))); .rodata : AT(ADDR(.rodata) - 0) { __start_rodata = .; *(.rodata) *(.rodata.*) . = ALIGN(32); __sched_class_highest = .; *(__stop_sched_class) *(__dl_sched_class) *(__rt_sched_class) *(__fair_sched_class) *(__idle_sched_class) __sched_class_lowest = .; . = ALIGN(8); __start_ro_after_init = .; *(.data..ro_after_init) . = ALIGN(8); __start___jump_table = .; KEEP(*(__jump_table)) __stop___jump_table = .; __end_ro_after_init = .; . = ALIGN(8); __start___tracepoints_ptrs = .; KEEP(*(__tracepoints_ptrs)) __stop___tracepoints_ptrs = .; *(__tracepoints_strings) } .rodata1 : AT(ADDR(.rodata1) - 0) { *(.rodata1) } .pci_fixup : AT(ADDR(.pci_fixup) - 0) { __start_pci_fixups_early = .; KEEP(*(.pci_fixup_early)) __end_pci_fixups_early = .; __start_pci_fixups_header = .; KEEP(*(.pci_fixup_header)) __end_pci_fixups_header = .; __start_pci_fixups_final = .; KEEP(*(.pci_fixup_final)) __end_pci_fixups_final = .; __start_pci_fixups_enable = .; KEEP(*(.pci_fixup_enable)) __end_pci_fixups_enable = .; __start_pci_fixups_resume = .; KEEP(*(.pci_fixup_resume)) __end_pci_fixups_resume = .; __start_pci_fixups_resume_early = .; KEEP(*(.pci_fixup_resume_early)) __end_pci_fixups_resume_early = .; __start_pci_fixups_suspend = .; KEEP(*(.pci_fixup_suspend)) __end_pci_fixups_suspend = .; __start_pci_fixups_suspend_late = .; KEEP(*(.pci_fixup_suspend_late)) __end_pci_fixups_suspend_late = .; } .builtin_fw : AT(ADDR(.builtin_fw) - 0) ALIGN(8) { __start_builtin_fw = .; KEEP(*(.builtin_fw)) __end_builtin_fw = .; } __ksymtab : AT(ADDR(__ksymtab) - 0) { __start___ksymtab = .; KEEP(*(SORT(___ksymtab+*))) __stop___ksymtab = .; } __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - 0) { __start___ksymtab_gpl = .; KEEP(*(SORT(___ksymtab_gpl+*))) __stop___ksymtab_gpl = .; } __kcrctab : AT(ADDR(__kcrctab) - 0) { __start___kcrctab = .; KEEP(*(SORT(___kcrctab+*))) __stop___kcrctab = .; } __kcrctab_gpl : AT(ADDR(__kcrctab_gpl) - 0) { __start___kcrctab_gpl = .; KEEP(*(SORT(___kcrctab_gpl+*))) __stop___kcrctab_gpl = .; } __ksymtab_strings : AT(ADDR(__ksymtab_strings) - 0) { *(__ksymtab_strings) } __init_rodata : AT(ADDR(__init_rodata) - 0) { *(.ref.rodata) } __param : AT(ADDR(__param) - 0) { __start___param = .; KEEP(*(__param)) __stop___param = .; } __modver : AT(ADDR(__modver) - 0) { __start___modver = .; KEEP(*(__modver)) __stop___modver = .; } . = ALIGN(4); __ex_table : AT(ADDR(__ex_table) - 0) { __start___ex_table = .; KEEP(*(__ex_table)) __stop___ex_table = .; } /DISCARD/ : { *(.note.GNU-stack) } .notes : AT(ADDR(.notes) - 0) { __start_notes = .; KEEP(*(.note.*)) __stop_notes = .; } . = ALIGN(((1 << 14))); __end_rodata = .; + .hyp.rodata : { . = ALIGN((1 << 14)); __hyp_rodata_start = .; *(.hyp.data..ro_after_init) *(.hyp.rodata) . = ALIGN((1 << 14)); __hyp_rodata_end = .; } + .rodata.text : { + . = ALIGN((1 << 14)); __entry_tramp_text_start = .; *(.entry.tramp.text) . = ALIGN((1 << 14)); __entry_tramp_text_end = .; *(.entry.tramp.rodata) + + + . = ALIGN((1 << 14)); + } + idmap_pg_dir = .; + . += (1 << 14); + tramp_pg_dir = .; + . += (1 << 14); + reserved_pg_dir = .; + . += (1 << 14); + swapper_pg_dir = .; + . += (1 << 14); + . = ALIGN(0x00010000); + __init_begin = .; + __inittext_begin = .; + . = ALIGN(8); .init.text : AT(ADDR(.init.text) - 0) { _sinittext = .; *(.init.text .init.text.*) *(.text.startup) *(.meminit.text*) _einittext = .; } + __exittext_begin = .; + .exit.text : { + *(.exit.text) *(.text.exit) *(.memexit.text) + } + __exittext_end = .; + . = ALIGN(4); + .altinstructions : { + __alt_instructions = .; + *(.altinstructions) + __alt_instructions_end = .; + } + . = ALIGN(0x00010000); + __inittext_end = .; + __initdata_begin = .; + init_idmap_pg_dir = .; + . += ((( 1 + ((((((_end + 0x00200000 + (1 << 14))) - 1) >> (((14 - 3) * (4 - (4 - 3)) + 3))) - (((((((-(((1)) << ((((47))) - 1)))) + (0x08000000))))) >> (((14 - 3) * (4 - (4 - 3)) + 3))) + 1 + 1)) + (0) + ((((((_end + 0x00200000 + (1 << 14))) - 1) >> (((14 - 3) * (4 - (2)) + 3))) - (((((((-(((1)) << ((((47))) - 1)))) + (0x08000000))))) >> (((14 - 3) * (4 - (2)) + 3))) + 1 + 1))) + 2) * (1 << 14)); + init_idmap_pg_end = .; + .init.data : { + KEEP(*(SORT(___kentry+*))) *(.init.data init.data.*) *(.meminit.data*) . = ALIGN(8); __start_mcount_loc = .; KEEP(*(__mcount_loc)) KEEP(*(__patchable_function_entries)) __stop_mcount_loc = .; ftrace_ops_list_func = arch_ftrace_ops_list_func; *(.init.rodata .init.rodata.*) . = ALIGN(8); __start_ftrace_events = .; KEEP(*(_ftrace_events)) __stop_ftrace_events = .; __start_ftrace_eval_maps = .; KEEP(*(_ftrace_eval_map)) __stop_ftrace_eval_maps = .; . = ALIGN(8); __start_kprobe_blacklist = .; KEEP(*(_kprobe_blacklist)) __stop_kprobe_blacklist = .; *(.meminit.rodata) . = ALIGN(8); __clk_of_table = .; KEEP(*(__clk_of_table)) KEEP(*(__clk_of_table_end)) . = ALIGN(8); __reservedmem_of_table = .; KEEP(*(__reservedmem_of_table)) KEEP(*(__reservedmem_of_table_end)) . = ALIGN(8); __timer_of_table = .; KEEP(*(__timer_of_table)) KEEP(*(__timer_of_table_end)) . = ALIGN(8); __cpu_method_of_table = .; KEEP(*(__cpu_method_of_table)) KEEP(*(__cpu_method_of_table_end)) . = ALIGN(8); __cpuidle_method_of_table = .; KEEP(*(__cpuidle_method_of_table)) KEEP(*(__cpuidle_method_of_table_end)) . = ALIGN(32); __dtb_start = .; KEEP(*(.dtb.init.rodata)) __dtb_end = .; . = ALIGN(8); __irqchip_of_table = .; KEEP(*(__irqchip_of_table)) KEEP(*(__irqchip_of_table_end)) . = ALIGN(8); __governor_thermal_table = .; KEEP(*(__governor_thermal_table)) __governor_thermal_table_end = .; . = ALIGN(8); __earlycon_table = .; KEEP(*(__earlycon_table)) __earlycon_table_end = .; . = ALIGN(8); __start_lsm_info = .; KEEP(*(.lsm_info.init)) __end_lsm_info = .; . = ALIGN(8); __start_early_lsm_info = .; KEEP(*(.early_lsm_info.init)) __end_early_lsm_info = .; . = ALIGN(8); __kunit_suites_start = .; KEEP(*(.kunit_test_suites)) __kunit_suites_end = .; + . = ALIGN(16); __setup_start = .; KEEP(*(.init.setup)) __setup_end = .; + __initcall_start = .; KEEP(*(.initcallearly.init)) __initcall0_start = .; KEEP(*(.initcall0.init)) KEEP(*(.initcall0s.init)) __initcall1_start = .; KEEP(*(.initcall1.init)) KEEP(*(.initcall1s.init)) __initcall2_start = .; KEEP(*(.initcall2.init)) KEEP(*(.initcall2s.init)) __initcall3_start = .; KEEP(*(.initcall3.init)) KEEP(*(.initcall3s.init)) __initcall4_start = .; KEEP(*(.initcall4.init)) KEEP(*(.initcall4s.init)) __initcall5_start = .; KEEP(*(.initcall5.init)) KEEP(*(.initcall5s.init)) __initcallrootfs_start = .; KEEP(*(.initcallrootfs.init)) KEEP(*(.initcallrootfss.init)) __initcall6_start = .; KEEP(*(.initcall6.init)) KEEP(*(.initcall6s.init)) __initcall7_start = .; KEEP(*(.initcall7.init)) KEEP(*(.initcall7s.init)) __initcall_end = .; + __con_initcall_start = .; KEEP(*(.con_initcall.init)) __con_initcall_end = .; + . = ALIGN(4); __initramfs_start = .; KEEP(*(.init.ramfs)) . = ALIGN(8); KEEP(*(.init.ramfs.info)) + *(.init.altinstructions .init.bss) + } + .exit.data : { + *(.exit.data .exit.data.*) *(.fini_array .fini_array.*) *(.dtors .dtors.*) *(.memexit.data*) *(.memexit.rodata*) + } + . = ALIGN((1 << 14)); .data..percpu : AT(ADDR(.data..percpu) - 0) { __per_cpu_load = .; __per_cpu_start = .; *(.data..percpu..first) . = ALIGN((1 << 14)); *(.data..percpu..page_aligned) . = ALIGN((1 << (6))); *(.data..percpu..read_mostly) . = ALIGN((1 << (6))); *(.data..percpu) *(.data..percpu..shared_aligned) __per_cpu_end = .; } + . = ALIGN((1 << 14)); .hyp.data..percpu : { *(.hyp.data..percpu) } + .hyp.reloc : ALIGN(4) { __hyp_reloc_begin = .; *(.hyp.reloc) __hyp_reloc_end = .; } + .rela.dyn : ALIGN(8) { + __rela_start = .; + *(.rela .rela*) + __rela_end = .; + } + .relr.dyn : ALIGN(8) { + __relr_start = .; + *(.relr.dyn) + __relr_end = .; + } + . = ALIGN(0x00010000); + __initdata_end = .; + __init_end = .; + _data = .; + _sdata = .; + . = ALIGN((1 << 14)); .data : AT(ADDR(.data) - 0) { . = ALIGN((2 * (((1)) << (14 + 0)))); __start_init_task = .; init_thread_union = .; init_stack = .; KEEP(*(.data..init_task)) KEEP(*(.data..init_thread_info)) . = __start_init_task + (((1)) << (14 + 0)); __end_init_task = .; . = ALIGN((1 << 14)); __nosave_begin = .; *(.data..nosave) . = ALIGN((1 << 14)); __nosave_end = .; . = ALIGN((1 << 14)); *(.data..page_aligned) . = ALIGN((1 << 14)); . = ALIGN((1 << (6))); *(.data..cacheline_aligned) . = ALIGN((1 << (6))); *(.data..read_mostly) . = ALIGN((1 << (6))); *(.xiptext) *(.data) *(.data..decrypted) *(.ref.data) *(.data..shared_aligned) *(.data.unlikely) __start_once = .; *(.data.once) __end_once = .; . = ALIGN(32); *(__tracepoints) . = ALIGN(8); __start___dyndbg_classes = .; KEEP(*(__dyndbg_classes)) __stop___dyndbg_classes = .; __start___dyndbg = .; KEEP(*(__dyndbg)) __stop___dyndbg = .; __start___trace_bprintk_fmt = .; KEEP(*(__trace_printk_fmt)) __stop___trace_bprintk_fmt = .; . = ALIGN(32); __start__bpf_raw_tp = .; KEEP(*(__bpf_raw_tp_map)) __stop__bpf_raw_tp = .; __start___tracepoint_str = .; KEEP(*(__tracepoint_str)) __stop___tracepoint_str = .; CONSTRUCTORS } . = ALIGN(8); __bug_table : AT(ADDR(__bug_table) - 0) { __start___bug_table = .; KEEP(*(__bug_table)) __stop___bug_table = .; } + .mmuoff.data.write : ALIGN(0x00000800) { + __mmuoff_data_start = .; + *(.mmuoff.data.write) + } + . = ALIGN(0x00000800); + .mmuoff.data.read : { + *(.mmuoff.data.read) + __mmuoff_data_end = .; + } + .pecoff_edata_padding : { BYTE(0); . = ALIGN(PECOFF_FILE_ALIGNMENT); } + __pecoff_data_rawsize = ABSOLUTE(. - __initdata_begin); + _edata = .; + . = ALIGN((1 << 14)); __bss_start = .; . = ALIGN((1 << 14)); .sbss : AT(ADDR(.sbss) - 0) { *(.dynsbss) *(.sbss) *(.scommon) } . = ALIGN(0); .bss : AT(ADDR(.bss) - 0) { __hyp_bss_start = .; *(.hyp.bss) . = ALIGN((1 << 14)); __hyp_bss_end = .; . = ALIGN((1 << 14)); *(.bss..page_aligned) . = ALIGN((1 << 14)); *(.dynbss) *(.bss) *(COMMON) } . = ALIGN(0); __bss_stop = .; + . = ALIGN((1 << 14)); + init_pg_dir = .; + . += ((1 << 14) * ( 1 + ((((((_end)) - 1) >> (((14 - 3) * (4 - (4 - 3)) + 3))) - (((((((-(((1)) << ((((47))) - 1)))) + (0x08000000))))) >> (((14 - 3) * (4 - (4 - 3)) + 3))) + 1 + (1))) + (0) + ((((((_end)) - 1) >> (((14 - 3) * (4 - (2)) + 3))) - (((((((-(((1)) << ((((47))) - 1)))) + (0x08000000))))) >> (((14 - 3) * (4 - (2)) + 3))) + 1 + (1))))); + init_pg_end = .; + . = ALIGN(0x00010000); + __pecoff_data_size = ABSOLUTE(. - __initdata_begin); + _end = .; + .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } .stab.excl 0 : { *(.stab.excl) } .stab.exclstr 0 : { *(.stab.exclstr) } .stab.index 0 : { *(.stab.index) } .stab.indexstr 0 : { *(.stab.indexstr) } + .debug 0 : { *(.debug) } .line 0 : { *(.line) } .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } .debug_pubtypes 0 : { *(.debug_pubtypes) } .debug_ranges 0 : { *(.debug_ranges) } .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) } .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) } .debug_types 0 : { *(.debug_types) } .debug_addr 0 : { *(.debug_addr) } .debug_line_str 0 : { *(.debug_line_str) } .debug_loclists 0 : { *(.debug_loclists) } .debug_macro 0 : { *(.debug_macro) } .debug_names 0 : { *(.debug_names) } .debug_rnglists 0 : { *(.debug_rnglists) } .debug_str_offsets 0 : { *(.debug_str_offsets) } + .comment 0 : { *(.comment) } .symtab 0 : { *(.symtab) } .strtab 0 : { *(.strtab) } .shstrtab 0 : { *(.shstrtab) } + _kernel_size_le_lo32 = (((_end - _text) & 0xffffffff) & 0xffffffff); _kernel_size_le_hi32 = (((_end - _text) >> 32) & 0xffffffff); _kernel_flags_le_lo32 = (((((0 << 0) | (((14 - 10) / 2) << (0 + 1)) | (1 << ((0 + 1) + 2)))) & 0xffffffff) & 0xffffffff); _kernel_flags_le_hi32 = (((((0 << 0) | (((14 - 10) / 2) << (0 + 1)) | (1 << ((0 + 1) + 2)))) >> 32) & 0xffffffff); + .plt : { + *(.plt) *(.plt.*) *(.iplt) *(.igot .igot.plt) + } + ASSERT(SIZEOF(.plt) == 0, "Unexpected run-time procedure linkages detected!") + .data.rel.ro : { *(.data.rel.ro) } + ASSERT(SIZEOF(.data.rel.ro) == 0, "Unexpected RELRO detected!") +} +PROVIDE(__efistub_kernel_size = _edata - _text); +PROVIDE(__efistub_primary_entry_offset = primary_entry - _text); +PROVIDE(__efistub_memcmp = __pi_memcmp); +PROVIDE(__efistub_memchr = __pi_memchr); +PROVIDE(__efistub_strlen = __pi_strlen); +PROVIDE(__efistub_strnlen = __pi_strnlen); +PROVIDE(__efistub_strcmp = __pi_strcmp); +PROVIDE(__efistub_strncmp = __pi_strncmp); +PROVIDE(__efistub_strrchr = __pi_strrchr); +PROVIDE(__efistub_dcache_clean_poc = __pi_dcache_clean_poc); +PROVIDE(__efistub__text = _text); +PROVIDE(__efistub__end = _end); +PROVIDE(__efistub__edata = _edata); +PROVIDE(__efistub_screen_info = screen_info); +PROVIDE(__efistub__ctype = _ctype); +PROVIDE(__pi___memcpy = __pi_memcpy); +PROVIDE(__pi___memmove = __pi_memmove); +PROVIDE(__pi___memset = __pi_memset); +__kvm_nvhe_kvm_patch_vector_branch = kvm_patch_vector_branch;; +__kvm_nvhe_kvm_update_va_mask = kvm_update_va_mask;; +__kvm_nvhe_kvm_get_kimage_voffset = kvm_get_kimage_voffset;; +__kvm_nvhe_kvm_compute_final_ctr_el0 = kvm_compute_final_ctr_el0;; +__kvm_nvhe_spectre_bhb_patch_loop_iter = spectre_bhb_patch_loop_iter;; +__kvm_nvhe_spectre_bhb_patch_loop_mitigation_enable = spectre_bhb_patch_loop_mitigation_enable;; +__kvm_nvhe_spectre_bhb_patch_wa3 = spectre_bhb_patch_wa3;; +__kvm_nvhe_spectre_bhb_patch_clearbhb = spectre_bhb_patch_clearbhb;; +__kvm_nvhe_alt_cb_patch_nops = alt_cb_patch_nops;; +__kvm_nvhe_kvm_vgic_global_state = kvm_vgic_global_state;; +__kvm_nvhe_nvhe_hyp_panic_handler = nvhe_hyp_panic_handler;; +__kvm_nvhe___hyp_stub_vectors = __hyp_stub_vectors;; +__kvm_nvhe___icache_flags = __icache_flags;; +__kvm_nvhe_kvm_arm_vmid_bits = kvm_arm_vmid_bits;; +__kvm_nvhe_vgic_v2_cpuif_trap = vgic_v2_cpuif_trap;; +__kvm_nvhe_vgic_v3_cpuif_trap = vgic_v3_cpuif_trap;; +__kvm_nvhe___start___kvm_ex_table = __start___kvm_ex_table;; +__kvm_nvhe___stop___kvm_ex_table = __stop___kvm_ex_table;; +__kvm_nvhe_kvm_arm_hyp_percpu_base = kvm_arm_hyp_percpu_base;; +__kvm_nvhe_kvm_arm_pmu_available = kvm_arm_pmu_available;; +__kvm_nvhe_clear_page = __kvm_nvhe___pi_clear_page;; +__kvm_nvhe_copy_page = __kvm_nvhe___pi_copy_page;; +__kvm_nvhe_memcpy = __kvm_nvhe___pi_memcpy;; +__kvm_nvhe_memset = __kvm_nvhe___pi_memset;; +__kvm_nvhe___start_rodata = __start_rodata;; +__kvm_nvhe___end_rodata = __end_rodata;; +__kvm_nvhe___bss_start = __bss_start;; +__kvm_nvhe___bss_stop = __bss_stop;; +__kvm_nvhe___hyp_idmap_text_start = __hyp_idmap_text_start;; +__kvm_nvhe___hyp_idmap_text_end = __hyp_idmap_text_end;; +__kvm_nvhe___hyp_text_start = __hyp_text_start;; +__kvm_nvhe___hyp_text_end = __hyp_text_end;; +__kvm_nvhe___hyp_bss_start = __hyp_bss_start;; +__kvm_nvhe___hyp_bss_end = __hyp_bss_end;; +__kvm_nvhe___hyp_rodata_start = __hyp_rodata_start;; +__kvm_nvhe___hyp_rodata_end = __hyp_rodata_end;; +__kvm_nvhe_kvm_protected_mode_initialized = kvm_protected_mode_initialized;; +ASSERT(__hyp_idmap_text_end - __hyp_idmap_text_start <= (1 << 14), + "HYP init code too big") +ASSERT(__idmap_text_end - (__idmap_text_start & ~(0x00001000 - 1)) <= 0x00001000, + "ID map text too big or misaligned") +ASSERT((__entry_tramp_text_end - __entry_tramp_text_start) <= 3*(1 << 14), + "Entry trampoline text too big") +ASSERT(__hyp_bss_start == __bss_start, "HYP and Host BSS are misaligned") +ASSERT(_text == ((((-(((1)) << ((((47))) - 1)))) + (0x08000000))), "HEAD is misaligned") +ASSERT(swapper_pg_dir - reserved_pg_dir == ((1 << 14)), + "RESERVED_SWAPPER_OFFSET is wrong!") +ASSERT(swapper_pg_dir - tramp_pg_dir == (2 * (1 << 14)), + "TRAMP_SWAPPER_OFFSET is wrong!") ──────────────────────────────────────────────────────────────────────────────── renamed: linux-6.1.66/arch/arm64/kvm/hyp/nvhe/gen-hyprel to linux/arch/arm64/kvm/hyp/nvhe/gen-hyprel (binary) ──────────────────────────────────────────────────────────────────────────────── diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/kvm/hyp/nvhe/hyp.lds linux/arch/arm64/kvm/hyp/nvhe/hyp.lds --- linux-6.1.66/arch/arm64/kvm/hyp/nvhe/hyp.lds 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/kvm/hyp/nvhe/hyp.lds 2023-12-14 14:24:55.208329120 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +SECTIONS { + .hyp.idmap.text : { __hyp_section_.hyp.idmap.text = .; *(.idmap.text .idmap.text.*) } + .hyp.text : { __hyp_section_.hyp.text = .; *(.text .text.*) } + .hyp.data..ro_after_init : { __hyp_section_.hyp.data..ro_after_init = .; *(.data..ro_after_init .data..ro_after_init.*) } + .hyp.rodata : { __hyp_section_.hyp.rodata = .; *(.rodata .rodata.*) } + . = ALIGN((1 << 14)); + .hyp.data..percpu : { __hyp_section_.hyp.data..percpu = .; + __per_cpu_start = .; *(.data..percpu..first) . = ALIGN((1 << 14)); *(.data..percpu..page_aligned) . = ALIGN((1 << (6))); *(.data..percpu..read_mostly) . = ALIGN((1 << (6))); *(.data..percpu) *(.data..percpu..shared_aligned) __per_cpu_end = .; + } + .hyp.bss : { __hyp_section_.hyp.bss = .; *(.bss .bss.*) } +} diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/kvm/hyp/nvhe/hyp-reloc.S linux/arch/arm64/kvm/hyp/nvhe/hyp-reloc.S --- linux-6.1.66/arch/arm64/kvm/hyp/nvhe/hyp-reloc.S 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/kvm/hyp/nvhe/hyp-reloc.S 2023-12-14 11:57:23.779848667 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +.data +.pushsection .hyp.reloc, "a" +.global __hyp_section_.hyp.idmap.text +.word 0 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584, R_AARCH64_PREL32, __hyp_section_.hyp.rodata + 0x1fa8 +.word 0 +.reloc 588, R_AARCH64_PREL32, __hyp_section_.hyp.rodata + 0x1ff8 +.word 0 +.reloc 592, R_AARCH64_PREL32, __hyp_section_.hyp.rodata + 0x2048 +.word 0 +.reloc 596, R_AARCH64_PREL32, __hyp_section_.hyp.rodata + 0x2098 +.word 0 +.reloc 600, R_AARCH64_PREL32, __hyp_section_.hyp.rodata + 0x20e8 +.popsection diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/arch/arm64/kvm/hyp_constants.h linux/arch/arm64/kvm/hyp_constants.h --- linux-6.1.66/arch/arm64/kvm/hyp_constants.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/arm64/kvm/hyp_constants.h 2023-12-14 11:56:23.232713741 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +#ifndef __HYP_CONSTANTS_H__ +#define __HYP_CONSTANTS_H__ +/* + * DO NOT MODIFY. + * + * This file was generated by Kbuild + */ + +#define STRUCT_HYP_PAGE_SIZE 4 /* sizeof(struct hyp_page) */ + +#endif diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/admin-guide/media/bcm2835-isp.rst linux/Documentation/admin-guide/media/bcm2835-isp.rst --- linux-6.1.66/Documentation/admin-guide/media/bcm2835-isp.rst 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/admin-guide/media/bcm2835-isp.rst 2023-12-13 11:50:46.462956241 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +.. SPDX-License-Identifier: GPL-2.0 + +BCM2835 ISP Driver +================== + +Introduction +------------ + +The BCM2835 Image Sensor Pipeline (ISP) is a fixed function hardware pipeline +for performing image processing operations. Images are fed to the input +of the ISP through memory frame buffers. These images may be in various YUV, +RGB, or Bayer formats. A typical use case would have Bayer images obtained from +an image sensor by the BCM2835 Unicam peripheral, written to a memory +frame buffer, and finally fed into the input of the ISP. Two concurrent output +images may be generated in YUV or RGB format at different resolutions. +Statistics output is also generated for Bayer input images. + +The bcm2835-isp driver exposes the following media pads as V4L2 device nodes: + +.. tabularcolumns:: |l|l|l|l| + +.. cssclass: longtable + +.. flat-table:: + + * - *Pad* + - *Direction* + - *Purpose* + - *Formats* + + * - "bcm2835-isp0-output0" + - sink + - Accepts Bayer, RGB or YUV format frame buffers as input to the ISP HW + pipeline. + - :ref:`RAW8 <V4L2-PIX-FMT-SRGGB8>`, + :ref:`RAW10P <V4L2-PIX-FMT-SRGGB10P>`, + :ref:`RAW12P <V4L2-PIX-FMT-SRGGB12P>`, + :ref:`RAW14P <V4L2-PIX-FMT-SRGGB14P>`, + :ref:`RAW16 <V4L2-PIX-FMT-SRGGB16>`, + :ref:`RGB24/BGR24 <V4L2-PIX-FMT-RGB24>`, + :ref:`YUYV <V4L2-PIX-FMT-YUYV>`, + :ref:`YVYU <V4L2-PIX-FMT-YVYU>`, + :ref:`UYVY <V4L2-PIX-FMT-UYVY>`, + :ref:`VYUY <V4L2-PIX-FMT-VYUY>`, + :ref:`YUV420/YVU420 <V4L2-PIX-FMT-YUV420>` + + * - "bcm2835-isp0-capture1" + - source + - High resolution YUV or RGB processed output from the ISP. + - :ref:`RGB565 <V4L2-PIX-FMT-RGB565>`, + :ref:`RGB24/BGR24 <V4L2-PIX-FMT-RGB24>`, + :ref:`ABGR32 <V4L2-PIX-FMT-ABGR32>`, + :ref:`YUYV <V4L2-PIX-FMT-YUYV>`, + :ref:`YVYU <V4L2-PIX-FMT-YVYU>`, + :ref:`UYVY <V4L2-PIX-FMT-UYVY>`, + :ref:`VYUY <V4L2-PIX-FMT-VYUY>`. + :ref:`YUV420/YVU420 <V4L2-PIX-FMT-YUV420>`, + :ref:`NV12/NV21 <V4L2-PIX-FMT-NV12>`, + + * - "bcm2835-isp0-capture2" + - source + - Low resolution YUV processed output from the ISP. The output of + this pad cannot have a resolution larger than the "bcm2835-isp0-capture1" pad in any dimension. + - :ref:`YUYV <V4L2-PIX-FMT-YUYV>`, + :ref:`YVYU <V4L2-PIX-FMT-YVYU>`, + :ref:`UYVY <V4L2-PIX-FMT-UYVY>`, + :ref:`VYUY <V4L2-PIX-FMT-VYUY>`. + :ref:`YUV420/YVU420 <V4L2-PIX-FMT-YUV420>`, + :ref:`NV12/NV21 <V4L2-PIX-FMT-NV12>`, + + * - "bcm2835-isp0-capture1" + - source + - Image statistics calculated from the input image provided on the + "bcm2835-isp0-output0" pad. Statistics are only available for Bayer + format input images. + - :ref:`v4l2-meta-fmt-bcm2835-isp-stats`. + +Pipeline Configuration +---------------------- + +The ISP pipeline can be configure through user-space by calling +:ref:`VIDIOC_S_EXT_CTRLS <VIDIOC_G_EXT_CTRLS>` on the “bcm2835-isp0-output0” +node with the appropriate parameters as shown in the table below. + +.. tabularcolumns:: |p{2cm}|p{5.0cm}| + +.. cssclass: longtable + +.. flat-table:: + + * - *id* + - *Parameter* + + * - ``V4L2_CID_USER_BCM2835_ISP_CC_MATRIX`` + - struct :c:type:`bcm2835_isp_custom_ccm` + + * - ``V4L2_CID_USER_BCM2835_ISP_LENS_SHADING`` + - struct :c:type:`bcm2835_isp_lens_shading` + + * - ``V4L2_CID_USER_BCM2835_ISP_BLACK_LEVEL`` + - struct :c:type:`bcm2835_isp_black_level` + + * - ``V4L2_CID_USER_BCM2835_ISP_GEQ`` + - struct :c:type:`bcm2835_isp_geq` + + * - ``V4L2_CID_USER_BCM2835_ISP_GAMMA`` + - struct :c:type:`bcm2835_isp_gamma` + + * - ``V4L2_CID_USER_BCM2835_ISP_DENOISE`` + - struct :c:type:`bcm2835_isp_denoise` + + * - ``V4L2_CID_USER_BCM2835_ISP_SHARPEN`` + - struct :c:type:`bcm2835_isp_sharpen` + + * - ``V4L2_CID_USER_BCM2835_ISP_DPC`` + - struct :c:type:`bcm2835_isp_dpc` + +++++++++++++++++++++++++ +Configuration Parameters +++++++++++++++++++++++++ + +.. kernel-doc:: include/uapi/linux/bcm2835-isp.h + :functions: bcm2835_isp_rational bcm2835_isp_ccm bcm2835_isp_custom_ccm + bcm2835_isp_gain_format bcm2835_isp_lens_shading + bcm2835_isp_black_level bcm2835_isp_geq bcm2835_isp_gamma + bcm2835_isp_denoise bcm2835_isp_sharpen + bcm2835_isp_dpc_mode bcm2835_isp_dpc diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml linux/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml --- linux-6.1.66/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml 2023-12-13 11:50:46.698956797 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:17 @ enum: - brcm,bcm2711-hdmi0 - brcm,bcm2711-hdmi1 + - brcm,bcm2712-hdmi0 + - brcm,bcm2712-hdmi1 reg: items: diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml linux/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml --- linux-6.1.66/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml 2023-12-13 11:50:46.698956797 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:24 @ - brcm,bcm2711-dsi1 - brcm,bcm2835-dsi0 - brcm,bcm2835-dsi1 + - brcm,bcm2711-dsi1 reg: maxItems: 1 diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml linux/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml --- linux-6.1.66/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml 2023-12-13 11:50:46.698956797 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:16 @ compatible: enum: - brcm,bcm2711-hvs + - brcm,bcm2712-hvs - brcm,bcm2835-hvs reg: @ linux/arch/arm/boot/dts/bcm2708.dtsi:40 @ properties: compatible: contains: - const: brcm,bcm2711-hvs + enum: + - brcm,bcm2711-hvs + - brcm,bcm2712-hvs then: required: diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml linux/Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml --- linux-6.1.66/Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml 2023-12-13 11:50:46.699956799 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:23 @ - brcm,bcm2711-pixelvalve2 - brcm,bcm2711-pixelvalve3 - brcm,bcm2711-pixelvalve4 + - brcm,bcm2712-pixelvalve0 + - brcm,bcm2712-pixelvalve1 + - brcm,bcm2712-pixelvalve2 reg: maxItems: 1 diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/display/brcm,bcm2835-txp.yaml linux/Documentation/devicetree/bindings/display/brcm,bcm2835-txp.yaml --- linux-6.1.66/Documentation/devicetree/bindings/display/brcm,bcm2835-txp.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/display/brcm,bcm2835-txp.yaml 2023-12-13 11:50:46.699956799 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:14 @ properties: compatible: - const: brcm,bcm2835-txp + enum: + - brcm,bcm2712-mop + - brcm,bcm2712-moplet + - brcm,bcm2835-txp reg: maxItems: 1 diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml linux/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml --- linux-6.1.66/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml 2023-12-13 11:50:46.699956799 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:21 @ compatible: enum: - brcm,bcm2711-vc5 + - brcm,bcm2712-vc6 - brcm,bcm2835-vc4 - brcm,cygnus-vc4 diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/display/panel/panel-dsi.yaml linux/Documentation/devicetree/bindings/display/panel/panel-dsi.yaml --- linux-6.1.66/Documentation/devicetree/bindings/display/panel/panel-dsi.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/display/panel/panel-dsi.yaml 2023-12-13 11:50:46.727956866 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/panel-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic MIPI DSI Panel + +maintainers: + - Timon Skerutsch <kernel@diodes-delight.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + description: + Shall contain a panel specific compatible and "panel-dsi" + in that order. + items: + - {} + - const: panel-dsi + + dsi-color-format: + description: | + The color format used by the panel. Only DSI supported formats are allowed. + enum: + - RGB888 + - RGB666 + - RGB666_PACKED + - RGB565 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Panel MIPI DSI input + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: true + + required: + - data-lanes + + mode: + description: | + DSI mode flags. See DSI Specs for details. + These are driver independent features of the DSI bus. + items: + - const: MODE_VIDEO + - const: MODE_VIDEO_BURST + - const: MODE_VIDEO_SYNC_PULSE + - const: MODE_VIDEO_AUTO_VERT + - const: MODE_VIDEO_HSE + - const: MODE_VIDEO_NO_HFP + - const: MODE_VIDEO_NO_HBP + - const: MODE_VIDEO_NO_HSA + - const: MODE_VSYNC_FLUSH + - const: MODE_NO_EOT_PACKET + - const: CLOCK_NON_CONTINUOUS + - const: MODE_LPM + - const: HS_PKT_END_ALIGNED + + reg: true + backlight: true + enable-gpios: true + width-mm: true + height-mm: true + panel-timing: true + power-supply: true + reset-gpios: true + ddc-i2c-bus: true + +required: + - panel-timing + - reg + - power-supply + - dsi-color-format + - port + +additionalProperties: false + +examples: + - | + panel { + compatible = "panel-mfgr,generic-dsi-panel","panel-dsi"; + power-supply = <&vcc_supply>; + backlight = <&backlight>; + dsi-color-format = "RGB888"; + reg = <0>; + mode = "MODE_VIDEO", "MODE_VIDEO_BURST", "MODE_NO_EOT_PACKET"; + + port { + panel_dsi_port: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&dsi_out>; + }; + }; + + panel-timing { + clock-frequency = <9200000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + }; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/display/panel/panel-simple.yaml linux/Documentation/devicetree/bindings/display/panel/panel-simple.yaml --- linux-6.1.66/Documentation/devicetree/bindings/display/panel/panel-simple.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/display/panel/panel-simple.yaml 2023-12-13 11:50:46.728956868 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:159 @ - frida,frd350h54004 # FriendlyELEC HD702E 800x1280 LCD panel - friendlyarm,hd702e + # Geekworm MZP280 2.8" 480x640 LCD panel with capacitive touch + - geekworm,mzp280 # GiantPlus GPG48273QS5 4.3" (480x272) WQVGA TFT LCD panel - giantplus,gpg48273qs5 # GiantPlus GPM940B0 3.0" QVGA TFT LCD panel @ linux/arch/arm/boot/dts/bcm2708.dtsi:177 @ - ivo,m133nwf4-r0 # Innolux AT043TN24 4.3" WQVGA TFT LCD panel - innolux,at043tn24 + # Innolux AT056tN53V1 5.6" VGA (640x480) TFT LCD panel + - innolux,at056tn53v1 # Innolux AT070TN92 7.0" WQVGA TFT LCD panel - innolux,at070tn92 # Innolux G070Y2-L01 7" WVGA (800x480) TFT LCD panel diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml linux/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml --- linux-6.1.66/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml 2023-12-13 11:50:46.785957002 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:19 @ compatible: enum: + - brcm,2712-v3d - brcm,2711-v3d - brcm,7268-v3d - brcm,7278-v3d diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml linux/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml --- linux-6.1.66/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml 2023-12-13 11:50:46.795957026 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/hwmon/emc2305.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip EMC230[1|2|3|5] RPM-based PWM Fan Speed Controller + +properties: + compatible: + enum: + - microchip,emc2305 + - microchip,emc2301 + emc2305,pwm-min: + description: + Min pwm of emc2305 + maxItems: 1 + emc2305,pwm-max: + description: + Max pwm of emc2305 + maxItems: 1 + emc2305,pwm-channel: + description: + Max number of pwm channels + maxItems: 1 + emcs205,max-state: + description: + maxItems: 1 + emc2305,cooling-levels: + description: + Quantity of cooling level state. + maxItems: 1 + +required: + - compatible + +optional: + - emc2305,min-pwm + - emc2305,max-pwm + - emc2305,pwm-channels + - emc2305,cooling-levels + +additionalProperties: false + +examples: + - | + fan { + compatible = "microchip,emc2305"; + emc2305,pwm-min = <0>; + emc2305,pwm-max = <255>; + emc2305,pwm-channel = <5> + emc2305,cooling-levels = <10>; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/input/raspberrypi,firmware-button.yaml linux/Documentation/devicetree/bindings/input/raspberrypi,firmware-button.yaml --- linux-6.1.66/Documentation/devicetree/bindings/input/raspberrypi,firmware-button.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/input/raspberrypi,firmware-button.yaml 2023-12-13 11:50:46.865957190 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/raspberrypi,firmware-button.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Raspberry Pi firmware buttons + +maintainers: + - Phil Elwell <phil@raspberrypi.com> + +description: > + The Raspberry Pi 5 firmware exposes the state of the power button. The + raspberrypi-button driver generates a keycode when it is pressed. + +properties: + compatible: + enum: + - raspberrypi,firmware-button + + id: + description: A numeric identifier of the button + + label: + description: Descriptive name of the button. + + linux,code: + description: Key code to emit. + +required: + - compatible + - linux,code + +additionalProperties: false + +examples: + - | + #include <dt-bindings/input/raspberrypi-button.h> + + pwr_button: pwr_button { + compatible = "raspberrypi,firmware-button"; + id = <RASPBERRYPI_BUTTON_POWER>; + label = "pwr_button"; + linux,code = <116>; // KEY_POWER + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/bcm2835-unicam.txt linux/Documentation/devicetree/bindings/media/bcm2835-unicam.txt --- linux-6.1.66/Documentation/devicetree/bindings/media/bcm2835-unicam.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/bcm2835-unicam.txt 2023-12-13 11:50:46.917957313 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +Broadcom BCM283x Camera Interface (Unicam) +------------------------------------------ + +The Unicam block on BCM283x SoCs is the receiver for either +CSI-2 or CCP2 data from image sensors or similar devices. + +The main platform using this SoC is the Raspberry Pi family of boards. +On the Pi the VideoCore firmware can also control this hardware block, +and driving it from two different processors will cause issues. +To avoid this, the firmware checks the device tree configuration +during boot. If it finds device tree nodes called csi0 or csi1 then +it will stop the firmware accessing the block, and it can then +safely be used via the device tree binding. + +Required properties: +=================== +- compatible : must be "brcm,bcm2835-unicam". +- reg : physical base address and length of the register sets for the + device. +- interrupts : should contain the IRQ line for this Unicam instance. +- clocks : list of clock specifiers, corresponding to entries in + clock-names property. +- clock-names : must contain "lp" and "vpu" entries, matching entries in the + clocks property. + +Unicam supports a single port node. It should contain one 'port' child node +with child 'endpoint' node. Please refer to the bindings defined in +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Within the endpoint node the "remote-endpoint" and "data-lanes" properties +are mandatory. +Data lane reordering is not supported so the data lanes must be in order, +starting at 1. The number of data lanes should represent the number of +usable lanes for the hardware block. That may be limited by either the SoC or +how the platform presents the interface, and the lower value must be used. + +Lane reordering is not supported on the clock lane either, so the optional +property "clock-lane" will implicitly be <0>. +Similarly lane inversion is not supported, therefore "lane-polarities" will +implicitly be <0 0 0 0 0>. +Neither of these values will be checked. + +Example: + csi1: csi1@7e801000 { + compatible = "brcm,bcm2835-unicam"; + reg = <0x7e801000 0x800>, + <0x7e802004 0x4>; + interrupts = <2 7>; + clocks = <&clocks BCM2835_CLOCK_CAM1>, + <&firmware_clocks 4>; + clock-names = "lp", "vpu"; + port { + csi1_ep: endpoint { + remote-endpoint = <&tc358743_0>; + data-lanes = <1 2>; + }; + }; + }; + + i2c0: i2c@7e205000 { + tc358743: csi-hdmi-bridge@0f { + compatible = "toshiba,tc358743"; + reg = <0x0f>; + + clocks = <&tc358743_clk>; + clock-names = "refclk"; + + tc358743_clk: bridge-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + port { + tc358743_0: endpoint { + remote-endpoint = <&csi1_ep>; + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <297000000>; + }; + }; + }; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/ad5398.txt linux/Documentation/devicetree/bindings/media/i2c/ad5398.txt --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/ad5398.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/ad5398.txt 2023-12-13 11:50:46.919957318 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +* Analog Devices AD5398 autofocus coil + +Required Properties: + + - compatible: Must contain one of: + - "adi,ad5398" + + - reg: I2C slave address + + - VANA-supply: supply of voltage for VANA pin + +Example: + + ad5398: coil@c { + compatible = "adi,ad5398"; + reg = <0x0c>; + + VANA-supply = <&vaux4>; + }; + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/ak7375.txt linux/Documentation/devicetree/bindings/media/i2c/ak7375.txt --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/ak7375.txt 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/ak7375.txt 1970-01-01 01:00:00.000000000 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ -Asahi Kasei Microdevices AK7375 voice coil lens driver - -AK7375 is a camera voice coil lens. - -Mandatory properties: - -- compatible: "asahi-kasei,ak7375" -- reg: I2C slave address diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/arducam,64mp.yaml linux/Documentation/devicetree/bindings/media/i2c/arducam,64mp.yaml --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/arducam,64mp.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/arducam,64mp.yaml 2023-12-13 11:50:46.921957322 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/arducam,64mp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arducam 1/1.7-Inch 64Mpixel CMOS Digital Image Sensor + +maintainers: + - Lee Jackson <info@arducam.com> + +description: |- + The Arducam 1/1.7-Inch 64Mpixel CMOS active pixel digital image sensor + with an active array size of 9248 x 6944. It is programmable through + I2C interface. The I2C address is fixed to 0x1A as per sensor data sheet. + Image data is sent through MIPI CSI-2, which can be configured for operation + with either 2 or 4 data lanes. + +properties: + compatible: + const: arducam,64mp + + reg: + description: I2C device address + maxItems: 1 + + clocks: + maxItems: 1 + + VDIG-supply: + description: + Digital I/O voltage supply, 1.05 volts + + VANA-supply: + description: + Analog voltage supply, 2.8 volts + + VDDL-supply: + description: + Digital core voltage supply, 1.8 volts + + reset-gpios: + description: |- + Reference to the GPIO connected to the xclr pin, if any. + Must be released (set high) after all supplies and INCK are applied. + + # See ../video-interfaces.txt for more details + port: + type: object + properties: + endpoint: + type: object + properties: + data-lanes: + description: |- + The sensor supports either two-lane, or four-lane operation. + For two-lane operation the property must be set to <1 2>. + anyOf: + - items: + - const: 1 + - const: 2 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + clock-noncontinuous: true + + link-frequencies: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint64-array + description: + Allowed data bus frequencies. + + required: + - link-frequencies + +required: + - compatible + - reg + - clocks + - VANA-supply + - VDIG-supply + - VDDL-supply + - port + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + arducam_64mp: sensor@1a { + compatible = "arducam,64mp"; + reg = <0x1a>; + clocks = <&arducam_64mp_clk>; + VANA-supply = <&arducam_64mp_vana>; /* 2.8v */ + VDIG-supply = <&arducam_64mp_vdig>; /* 1.05v */ + VDDL-supply = <&arducam_64mp_vddl>; /* 1.8v */ + + port { + arducam_64mp_0: endpoint { + remote-endpoint = <&csi1_ep>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/arducam-pivariety.yaml linux/Documentation/devicetree/bindings/media/i2c/arducam-pivariety.yaml --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/arducam-pivariety.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/arducam-pivariety.yaml 2023-12-13 11:50:46.921957322 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/arducam-pivariety.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arducam Pivariety Series CMOS Digital Image Sensor + +maintainers: + - Lee Jackson <info@arducam.com> + +description: |- + Arducam Pivariety series cameras make compatibility layers for various CMOS + sensors and provide a unified command interface. It is programmable through + I2C interface. The I2C address is fixed to 0x0C. Image data is sent through + MIPI CSI-2, which is configured as either 1, 2 or 4 data lanes. + +properties: + compatible: + const: arducam,arducam-pivariety + + reg: + description: I2C device address + maxItems: 1 + + clocks: + maxItems: 1 + + VDIG-supply: + description: + Digital I/O voltage supply, 1.05 volts + + VANA-supply: + description: + Analog voltage supply, 2.8 volts + + VDDL-supply: + description: + Digital core voltage supply, 1.8 volts + + reset-gpios: + description: |- + Reference to the GPIO connected to the xclr pin, if any. + Must be released (set high) after all supplies and INCK are applied. + + # See ../video-interfaces.txt for more details + port: + type: object + properties: + endpoint: + type: object + properties: + data-lanes: + description: |- + The sensor supports either two-lane, or four-lane operation. + For two-lane operation the property must be set to <1 2>. + items: + - const: 1 + - const: 2 + + clock-noncontinuous: + type: boolean + description: |- + MIPI CSI-2 clock is non-continuous if this property is present, + otherwise it's continuous. + + link-frequencies: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint64-array + description: + Allowed data bus frequencies. + + required: + - link-frequencies + +required: + - compatible + - reg + - clocks + - VANA-supply + - VDIG-supply + - VDDL-supply + - port + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + arducam_pivariety: sensor@0c { + compatible = "arducam,arducam-pivariety"; + reg = <0x0c>; + clocks = <&arducam_pivariety_clk>; + VANA-supply = <&arducam_pivariety_vana>; /* 2.8v */ + VDIG-supply = <&arducam_pivariety_vdig>; /* 1.05v */ + VDDL-supply = <&arducam_pivariety_vddl>; /* 1.8v */ + + port { + arducam_pivariety_0: endpoint { + remote-endpoint = <&csi1_ep>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <493500000>; + }; + }; + }; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/asahi-kasei,ak7375.yaml linux/Documentation/devicetree/bindings/media/i2c/asahi-kasei,ak7375.yaml --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/asahi-kasei,ak7375.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/asahi-kasei,ak7375.yaml 2023-12-13 11:50:46.921957322 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/asahi-kasei,ak7375.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Asahi Kasei Microdevices AK7375 voice coil lens actuator + +maintainers: + - Tianshu Qiu <tian.shu.qiu@intel.com> + +description: + AK7375 is a voice coil motor (VCM) camera lens actuator that + is controlled over I2C. + +properties: + compatible: + const: asahi-kasei,ak7375 + + reg: + maxItems: 1 + + vdd-supply: + description: VDD supply + + vio-supply: + description: I/O pull-up supply + +required: + - compatible + - reg + - vdd-supply + - vio-supply + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ak7375: camera-lens@c { + compatible = "asahi-kasei,ak7375"; + reg = <0x0c>; + + vdd-supply = <&vreg_l23a_2p8>; + vio-supply = <&vreg_lvs1a_1p8>; + }; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9807-vcm.yaml linux/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9807-vcm.yaml --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9807-vcm.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9807-vcm.yaml 2023-12-13 11:50:46.921957322 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:8 @ $id: http://devicetree.org/schemas/media/i2c/dongwoon,dw9807-vcm.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Dongwoon Anatech DW9807 voice coil lens driver +title: Dongwoon Anatech DW9807 and DW9817 voice coil lens driver maintainers: - Sakari Ailus <sakari.ailus@linux.intel.com> description: | DW9807 is a 10-bit DAC with current sink capability. It is intended for - controlling voice coil lenses. + controlling voice coil lenses. The output drive is 0-100mA. + DW9817 is very similar as a 10-bit DAC with current sink capability, + however the output drive is a bidirection -100 to +100mA. + properties: compatible: - const: dongwoon,dw9807-vcm + items: + - enum: + - dongwoon,dw9807-vcm + - dongwoon,dw9817-vcm reg: maxItems: 1 + VDD-supply: + description: + Definition of the regulator used as VDD power supply to the driver. + required: - compatible - reg diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/imx258.yaml linux/Documentation/devicetree/bindings/media/i2c/imx258.yaml --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/imx258.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/imx258.yaml 2023-12-13 11:50:46.922957324 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:17 @ type stacked image sensor with a square pixel array of size 4208 x 3120. It is programmable through I2C interface. Image data is sent through MIPI CSI-2. + There are a number of variants of the sensor which cannot be detected at + runtime, so multiple compatible strings are required to differentiate these. properties: compatible: - const: sony,imx258 + enum: + - sony,imx258 + - sony,imx258-pdaf assigned-clocks: true assigned-clock-parents: true diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/imx290.txt linux/Documentation/devicetree/bindings/media/i2c/imx290.txt --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/imx290.txt 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/imx290.txt 1970-01-01 01:00:00.000000000 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ -* Sony IMX290 1/2.8-Inch CMOS Image Sensor - -The Sony IMX290 is a 1/2.8-Inch CMOS Solid-state image sensor with -Square Pixel for Color Cameras. It is programmable through I2C and 4-wire -interfaces. The sensor output is available via CMOS logic parallel SDR output, -Low voltage LVDS DDR output and CSI-2 serial data output. The CSI-2 bus is the -default. No bindings have been defined for the other busses. - -Required Properties: -- compatible: Should be "sony,imx290" -- reg: I2C bus address of the device -- clocks: Reference to the xclk clock. -- clock-names: Should be "xclk". -- clock-frequency: Frequency of the xclk clock in Hz. -- vdddo-supply: Sensor digital IO regulator. -- vdda-supply: Sensor analog regulator. -- vddd-supply: Sensor digital core regulator. - -Optional Properties: -- reset-gpios: Sensor reset GPIO - -The imx290 device node should contain one 'port' child node with -an 'endpoint' subnode. For further reading on port node refer to -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Required Properties on endpoint: -- data-lanes: check ../video-interfaces.txt -- link-frequencies: check ../video-interfaces.txt -- remote-endpoint: check ../video-interfaces.txt - -Example: - &i2c1 { - ... - imx290: camera-sensor@1a { - compatible = "sony,imx290"; - reg = <0x1a>; - - reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&camera_rear_default>; - - clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; - clock-names = "xclk"; - clock-frequency = <37125000>; - - vdddo-supply = <&camera_vdddo_1v8>; - vdda-supply = <&camera_vdda_2v8>; - vddd-supply = <&camera_vddd_1v5>; - - port { - imx290_ep: endpoint { - data-lanes = <1 2 3 4>; - link-frequencies = /bits/ 64 <445500000>; - remote-endpoint = <&csiphy0_ep>; - }; - }; - }; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/imx378.yaml linux/Documentation/devicetree/bindings/media/i2c/imx378.yaml --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/imx378.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/imx378.yaml 2023-12-13 11:50:46.922957324 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/imx378.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony 1/2.3-Inch 12Mpixel CMOS Digital Image Sensor + +maintainers: + - Naushir Patuck <naush@raspberypi.com> + +description: |- + The Sony IMX378 is a 1/2.3-inch CMOS active pixel digital image sensor + with an active array size of 4056H x 3040V. It is programmable through + I2C interface. The I2C address is fixed to 0x1A as per sensor data sheet. + Image data is sent through MIPI CSI-2, which is configured as either 2 or + 4 data lanes. + +properties: + compatible: + const: sony,imx378 + + reg: + description: I2C device address + maxItems: 1 + + clocks: + maxItems: 1 + + VDIG-supply: + description: + Digital I/O voltage supply, 1.05 volts + + VANA-supply: + description: + Analog voltage supply, 2.8 volts + + VDDL-supply: + description: + Digital core voltage supply, 1.8 volts + + reset-gpios: + description: |- + Reference to the GPIO connected to the xclr pin, if any. + Must be released (set high) after all supplies and INCK are applied. + + # See ../video-interfaces.txt for more details + port: + type: object + properties: + endpoint: + type: object + properties: + data-lanes: + description: |- + The sensor supports either two-lane, or four-lane operation. + For two-lane operation the property must be set to <1 2>. + items: + - const: 1 + - const: 2 + + clock-noncontinuous: + type: boolean + description: |- + MIPI CSI-2 clock is non-continuous if this property is present, + otherwise it's continuous. + + link-frequencies: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint64-array + description: + Allowed data bus frequencies. + + required: + - link-frequencies + +required: + - compatible + - reg + - clocks + - VANA-supply + - VDIG-supply + - VDDL-supply + - port + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + imx378: sensor@10 { + compatible = "sony,imx378"; + reg = <0x1a>; + clocks = <&imx378_clk>; + VANA-supply = <&imx378_vana>; /* 2.8v */ + VDIG-supply = <&imx378_vdig>; /* 1.05v */ + VDDL-supply = <&imx378_vddl>; /* 1.8v */ + + port { + imx378_0: endpoint { + remote-endpoint = <&csi1_ep>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <450000000>; + }; + }; + }; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/imx477.yaml linux/Documentation/devicetree/bindings/media/i2c/imx477.yaml --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/imx477.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/imx477.yaml 2023-12-13 11:50:46.922957324 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/imx477.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony 1/2.3-Inch 12Mpixel CMOS Digital Image Sensor + +maintainers: + - Naushir Patuck <naush@raspberypi.com> + +description: |- + The Sony IMX477 is a 1/2.3-inch CMOS active pixel digital image sensor + with an active array size of 4056H x 3040V. It is programmable through + I2C interface. The I2C address is fixed to 0x1A as per sensor data sheet. + Image data is sent through MIPI CSI-2, which is configured as either 2 or + 4 data lanes. + +properties: + compatible: + const: sony,imx477 + + reg: + description: I2C device address + maxItems: 1 + + clocks: + maxItems: 1 + + VDIG-supply: + description: + Digital I/O voltage supply, 1.05 volts + + VANA-supply: + description: + Analog voltage supply, 2.8 volts + + VDDL-supply: + description: + Digital core voltage supply, 1.8 volts + + reset-gpios: + description: |- + Reference to the GPIO connected to the xclr pin, if any. + Must be released (set high) after all all supplies and INCK are applied. + + # See ../video-interfaces.txt for more details + port: + type: object + properties: + endpoint: + type: object + properties: + data-lanes: + description: |- + The sensor supports either two-lane, or four-lane operation. + For two-lane operation the property must be set to <1 2>. + items: + - const: 1 + - const: 2 + + clock-noncontinuous: + type: boolean + description: |- + MIPI CSI-2 clock is non-continuous if this property is present, + otherwise it's continuous. + + link-frequencies: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint64-array + description: + Allowed data bus frequencies. + + required: + - link-frequencies + +required: + - compatible + - reg + - clocks + - VANA-supply + - VDIG-supply + - VDDL-supply + - port + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + imx477: sensor@10 { + compatible = "sony,imx477"; + reg = <0x1a>; + clocks = <&imx477_clk>; + VANA-supply = <&imx477_vana>; /* 2.8v */ + VDIG-supply = <&imx477_vdig>; /* 1.05v */ + VDDL-supply = <&imx477_vddl>; /* 1.8v */ + + port { + imx477_0: endpoint { + remote-endpoint = <&csi1_ep>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <450000000>; + }; + }; + }; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/imx519.yaml linux/Documentation/devicetree/bindings/media/i2c/imx519.yaml --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/imx519.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/imx519.yaml 2023-12-13 11:50:46.923957327 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/imx519.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony 1/2.5-Inch 16Mpixel CMOS Digital Image Sensor + +maintainers: + - Lee Jackson <info@arducam.com> + +description: |- + The Sony IMX519 is a 1/2.5-inch CMOS active pixel digital image sensor + with an active array size of 4656H x 3496V. It is programmable through + I2C interface. The I2C address is fixed to 0x1A as per sensor data sheet. + Image data is sent through MIPI CSI-2, which is configured as either 2 or + 4 data lanes. + +properties: + compatible: + const: sony,imx519 + + reg: + description: I2C device address + maxItems: 1 + + clocks: + maxItems: 1 + + VDIG-supply: + description: + Digital I/O voltage supply, 1.05 volts + + VANA-supply: + description: + Analog voltage supply, 2.8 volts + + VDDL-supply: + description: + Digital core voltage supply, 1.8 volts + + reset-gpios: + description: |- + Reference to the GPIO connected to the xclr pin, if any. + Must be released (set high) after all supplies and INCK are applied. + + # See ../video-interfaces.txt for more details + port: + type: object + properties: + endpoint: + type: object + properties: + data-lanes: + description: |- + The sensor supports either two-lane, or four-lane operation. + For two-lane operation the property must be set to <1 2>. + items: + - const: 1 + - const: 2 + + clock-noncontinuous: + type: boolean + description: |- + MIPI CSI-2 clock is non-continuous if this property is present, + otherwise it's continuous. + + link-frequencies: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint64-array + description: + Allowed data bus frequencies. + + required: + - link-frequencies + +required: + - compatible + - reg + - clocks + - VANA-supply + - VDIG-supply + - VDDL-supply + - port + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + imx519: sensor@1a { + compatible = "sony,imx519"; + reg = <0x1a>; + clocks = <&imx519_clk>; + VANA-supply = <&imx519_vana>; /* 2.8v */ + VDIG-supply = <&imx519_vdig>; /* 1.05v */ + VDDL-supply = <&imx519_vddl>; /* 1.8v */ + + port { + imx519_0: endpoint { + remote-endpoint = <&csi1_ep>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <493500000>; + }; + }; + }; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/irs1125.txt linux/Documentation/devicetree/bindings/media/i2c/irs1125.txt --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/irs1125.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/irs1125.txt 2023-12-13 11:50:46.923957327 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +* Infineon irs1125 time of flight sensor + +The Infineon irs1125 is a time of flight digital image sensor with +an active array size of 352H x 286V. It is programmable through I2C +interface. The I2C address defaults to 0x3D, but can be reconfigured +to address 0x3C or 0x41 via I2C commands. Image data is sent through +MIPI CSI-2, which is configured as either 1 or 2 data lanes. + +Required Properties: +- compatible: value should be "infineon,irs1125" for irs1125 sensor +- reg: I2C bus address of the device +- clocks: reference to the xclk input clock. +- pwdn-gpios: reference to the GPIO connected to the reset pin. + This is an active low signal to the iirs1125. + +The irs1125 device node should contain one 'port' child node with +an 'endpoint' subnode. For further reading on port node refer to +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Endpoint node required properties for CSI-2 connection are: +- remote-endpoint: a phandle to the bus receiver's endpoint node. +- clock-lanes: should be set to <0> (clock lane on hardware lane 0) +- data-lanes: should be set to <1> or <1 2> (one or two lane CSI-2 + supported) + +Example: + sensor@10 { + compatible = "infineon,irs1125"; + reg = <0x3D>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&irs1125_clk>; + pwdn-gpios = <&gpio 5 0>; + + irs1125_clk: camera-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + port { + sensor_out: endpoint { + remote-endpoint = <&csiss_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/ovti,ov64a40.yaml linux/Documentation/devicetree/bindings/media/i2c/ovti,ov64a40.yaml --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/ovti,ov64a40.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/ovti,ov64a40.yaml 2023-12-13 11:50:46.927957336 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov64a40.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OmniVision OV64A40 Image Sensor + +maintainers: + - Jacopo Mondi <jacopo.mondi@ideasonboard.com> + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + const: ovti,ov64a40 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + avdd-supply: + description: Analog voltage supply, 2.8 volts + + dvdd-supply: + description: Digital core voltage supply, 1.1 volts + + dovdd-supply: + description: Digital I/O voltage supply, 1.8 volts + + powerdown-gpios: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + additionalProperties: false + + properties: + bus-type: + enum: + - 1 # MIPI CSI-2 C-PHY + - 4 # MIPI CSI-2 D-PHY + data-lanes: true + link-frequencies: true + clock-noncontinuous: true + remote-endpoint: true + +required: + - compatible + - reg + - clocks + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera@36 { + compatible = "ovti,ov64a40"; + reg = <0x36>; + clocks = <&camera_clk>; + dovdd-supply = <&vgen4_reg>; + avdd-supply = <&vgen3_reg>; + dvdd-supply = <&vgen2_reg>; + powerdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + rotation = <180>; + orientation = <2>; + + port { + endpoint { + remote-endpoint = <&mipi_csi2_in>; + bus-type = <4>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/rohm,bu64754.yaml linux/Documentation/devicetree/bindings/media/i2c/rohm,bu64754.yaml --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/rohm,bu64754.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/rohm,bu64754.yaml 2023-12-13 11:50:46.928957339 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2023 Ideas on Board Oy. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/rohm,bu64754.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BU64754 Actuator Driver for Camera Autofocus + +maintainers: + - Kieran Bingham <kieran.bingham@ideasonboard.com> + +description: | + The BU64754GWZ is an actuator driver IC which can control the actuator + position precisely using an internal Hall Sensor. + +properties: + compatible: + items: + - enum: + - rohm,bu64754 + + reg: + maxItems: 1 + + vdd-supply: + description: + Definition of the regulator used as VDD power supply to the driver. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + lens@76 { + compatible = "rohm,bu64754"; + reg = <0x76>; + vdd-supply = <&cam1_reg>; + }; + }; +... diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml linux/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml 2023-12-13 11:50:46.929957341 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/sony,imx290.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony IMX290 1/2.8-Inch CMOS Image Sensor + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + - Laurent Pinchart <laurent.pinchart@ideasonboard.com> + +description: |- + The Sony IMX290 is a 1/2.8-Inch CMOS Solid-state image sensor with Square + Pixel, available in either mono or colour variants. It is programmable + through I2C and 4-wire interfaces. + + The sensor output is available via CMOS logic parallel SDR output, Low voltage + LVDS DDR output and CSI-2 serial data output. The CSI-2 bus is the default. + No bindings have been defined for the other busses. + + imx290lqr is the full model identifier for the colour variant. "sony,imx290" + is treated the same as this as it was the original compatible string. + imx290llr is the mono version of the sensor. + +properties: + compatible: + oneOf: + - enum: + - sony,imx290lqr # Colour + - sony,imx290llr # Monochrome + - sony,imx327lqr # Colour + - const: sony,imx290 + deprecated: true + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + description: Input clock (37.125 MHz or 74.25 MHz) + items: + - const: xclk + + clock-frequency: + description: Frequency of the xclk clock in Hz + + vdda-supply: + description: Analog power supply (2.9V) + + vddd-supply: + description: Digital core power supply (1.2V) + + vdddo-supply: + description: Digital I/O power supply (1.8V) + + reset-gpios: + description: Sensor reset (XCLR) GPIO + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + description: | + Video output port + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + anyOf: + - items: + - const: 1 + - const: 2 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + link-frequencies: true + + required: + - data-lanes + - link-frequencies + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - clock-frequency + - vdda-supply + - vddd-supply + - vdddo-supply + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + imx290: camera-sensor@1a { + compatible = "sony,imx290lqr"; + reg = <0x1a>; + + pinctrl-names = "default"; + pinctrl-0 = <&camera_rear_default>; + + clocks = <&gcc 90>; + clock-names = "xclk"; + clock-frequency = <37125000>; + + vdddo-supply = <&camera_vdddo_1v8>; + vdda-supply = <&camera_vdda_2v8>; + vddd-supply = <&camera_vddd_1v5>; + + reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; + + port { + imx290_ep: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <445500000>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; + }; +... diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/sony,imx296.yaml linux/Documentation/devicetree/bindings/media/i2c/sony,imx296.yaml --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/sony,imx296.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/sony,imx296.yaml 2023-12-13 11:50:46.929957341 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/sony,imx296.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony IMX296 1/2.8-Inch CMOS Image Sensor + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + - Laurent Pinchart <laurent.pinchart@ideasonboard.com> + +description: |- + The Sony IMX296 is a 1/2.9-Inch active pixel type CMOS Solid-state image + sensor with square pixel array and 1.58 M effective pixels. This chip + features a global shutter with variable charge-integration time. It is + programmable through I2C and 4-wire interfaces. The sensor output is + available via CSI-2 serial data output (1 Lane). + +properties: + compatible: + enum: + - sony,imx296 + - sony,imx296ll + - sony,imx296lq + description: + The IMX296 sensor exists in two different models, a colour variant + (IMX296LQ) and a monochrome variant (IMX296LL). The device exposes the + model through registers, allowing for auto-detection with a common + "sony,imx296" compatible string. However, some camera modules disable the + ability to read the sensor model register, which disables this feature. + In those cases, the exact model needs to be specified as "sony,imx296ll" + or "sony,imx296lq". + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + description: Input clock (37.125 MHz, 54 MHz or 74.25 MHz) + items: + - const: inck + + avdd-supply: + description: Analog power supply (3.3V) + + dvdd-supply: + description: Digital power supply (1.2V) + + ovdd-supply: + description: Interface power supply (1.8V) + + reset-gpios: + description: Sensor reset (XCLR) GPIO + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - avdd-supply + - dvdd-supply + - ovdd-supply + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + imx296: camera-sensor@1a { + compatible = "sony,imx296"; + reg = <0x1a>; + + pinctrl-names = "default"; + pinctrl-0 = <&camera_rear_default>; + + clocks = <&gcc 90>; + clock-names = "inck"; + + avdd-supply = <&camera_vdda_3v3>; + dvdd-supply = <&camera_vddd_1v2>; + ovdd-supply = <&camera_vddo_1v8>; + + reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; + + port { + imx296_ep: endpoint { + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/i2c/sony,imx708.yaml linux/Documentation/devicetree/bindings/media/i2c/sony,imx708.yaml --- linux-6.1.66/Documentation/devicetree/bindings/media/i2c/sony,imx708.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/i2c/sony,imx708.yaml 2023-12-13 11:50:46.929957341 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/sony,imx708.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony 1/2.3-Inch 12Mpixel CMOS Digital Image Sensor + +maintainers: + - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com> + +description: |- + The Sony IMX708 is a 1/2.3-inch CMOS active pixel digital image sensor + with an active array size of 4608H x 2592V. It is programmable through + I2C interface. The I2C address is fixed to 0x1A as per sensor data sheet. + Image data is sent through MIPI CSI-2, which is configured as either 2 or + 4 data lanes. + +properties: + compatible: + const: sony,imx708 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + description: Input clock (6 to 27 MHz) + items: + - const: inck + + vdig-supply: + description: + Digital I/O voltage supply, 1.1 volts + + vana1-supply: + description: + Analog1 voltage supply, 2.8 volts + + vana2-supply: + description: + Analog2 voltage supply, 1.8 volts + + vddl-supply: + description: + Digital core voltage supply, 1.8 volts + + reset-gpios: + description: Sensor reset (XCLR) GPIO + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + description: | + Video output port + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + anyOf: + - items: + - const: 1 + - const: 2 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + link-frequencies: true + + required: + - data-lanes + - link-frequencies + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - vdig-supply + - vana1-supply + - vana2-supply + - vddl-supply + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + imx708: camera-sensor@1a { + compatible = "sony,imx708"; + reg = <0x1a>; + + clocks = <&clk 90>; + clock-names = "inck"; + + vdig-supply = <&camera_vdig>; + vana1-supply = <&camera_vana1>; + vana2-supply = <&camera_vana2>; + vddl-supply = <&camera_vddl>; + + reset-gpios = <&gpio 35 GPIO_ACTIVE_LOW>; + + port { + imx708_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <450000000>; + remote-endpoint = <&csi_ep>; + }; + }; + }; + }; +... diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/media/rpivid_hevc.yaml linux/Documentation/devicetree/bindings/media/rpivid_hevc.yaml --- linux-6.1.66/Documentation/devicetree/bindings/media/rpivid_hevc.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/media/rpivid_hevc.yaml 2023-12-13 11:50:46.940957367 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rpivid_hevc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Raspberry Pi HEVC Decoder + +maintainers: + - Raspberry Pi <kernel-list@raspberrypi.com> + +description: |- + The Camera Adaptation Layer (CAL) is a key component for image capture + applications. The capture module provides the system interface and the + processing capability to connect CSI2 image-sensor modules to the + DRA72x device. + +properties: + compatible: + enum: + - raspberrypi,rpivid-vid-decoder + + reg: + minItems: 2 + items: + - description: The HEVC main register region + - description: The Interrupt controller register region + + reg-names: + minItems: 2 + items: + - const: hevc + - const: intc + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The HEVC block clock + + clock-names: + items: + - const: hevc + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + video-codec@7eb10000 { + compatible = "raspberrypi,rpivid-vid-decoder"; + reg = <0x0 0x7eb10000 0x1000>, /* INTC */ + <0x0 0x7eb00000 0x10000>; /* HEVC */ + reg-names = "intc", + "hevc"; + + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&clk 0>; + clock-names = "hevc"; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt linux/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt --- linux-6.1.66/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt 2023-12-13 11:50:46.984957470 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +* Broadcom BCM2835 SMI character device driver. + +SMI or secondary memory interface is a peripheral specific to certain Broadcom +SOCs, and is helpful for talking to things like parallel-interface displays +and NAND flashes (in fact, most things with a parallel register interface). + +This driver adds a character device which provides a user-space interface to +an instance of the SMI driver. + +Required properties: +- compatible: "brcm,bcm2835-smi-dev" +- smi_handle: a phandle to the smi node. + +Optional properties: +- None. + + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt linux/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt --- linux-6.1.66/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt 2023-12-13 11:50:46.984957470 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +* Broadcom BCM2835 SMI driver. + +SMI or secondary memory interface is a peripheral specific to certain Broadcom +SOCs, and is helpful for talking to things like parallel-interface displays +and NAND flashes (in fact, most things with a parallel register interface). + +Required properties: +- compatible: "brcm,bcm2835-smi" +- reg: Should contain location and length of SMI registers and SMI clkman regs +- interrupts: *the* SMI interrupt. +- pinctrl-names: should be "default". +- pinctrl-0: the phandle of the gpio pin node. +- brcm,smi-clock-source: the clock source for clkman +- brcm,smi-clock-divisor: the integer clock divisor for clkman +- dmas: the dma controller phandle and the DREQ number (4 on a 2835) +- dma-names: the name used by the driver to request its channel. + Should be "rx-tx". + +Optional properties: +- None. + +Examples: + +8 data pin configuration: + +smi: smi@7e600000 { + compatible = "brcm,bcm2835-smi"; + reg = <0x7e600000 0x44>, <0x7e1010b0 0x8>; + interrupts = <2 16>; + pinctrl-names = "default"; + pinctrl-0 = <&smi_pins>; + brcm,smi-clock-source = <6>; + brcm,smi-clock-divisor = <4>; + dmas = <&dma 4>; + dma-names = "rx-tx"; + + status = "okay"; +}; + +smi_pins: smi_pins { + brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + /* Alt 1: SMI */ + brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5>; + /* /CS, /WE and /OE are pulled high, as they are + generally active low signals */ + brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0>; +}; + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml linux/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml --- linux-6.1.66/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml 2023-12-13 11:50:46.996957499 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:19 @ properties: compatible: enum: + - raspberrypi,rp1-dwcmshc - rockchip,rk3568-dwcmshc - rockchip,rk3588-dwcmshc - snps,dwcmshc-sdhci @ linux/arch/arm/boot/dts/bcm2708.dtsi:38 @ - description: axi clock for rockchip specified - description: block clock for rockchip specified - description: timer clock for rockchip specified + - description: timeout clock for rp1 specified + - description: sdio clock generator for rp1 specified clock-names: @ linux/arch/arm/boot/dts/bcm2708.dtsi:50 @ - const: axi - const: block - const: timer + - const: timeout + - const: sdio rockchip,txclk-tapnum: description: Specify the number of delay for tx sampling. diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/net/cdns,macb.yaml linux/Documentation/devicetree/bindings/net/cdns,macb.yaml --- linux-6.1.66/Documentation/devicetree/bindings/net/cdns,macb.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/net/cdns,macb.yaml 2023-12-13 11:50:47.018957551 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:124 @ Node containing PHY children. If this node is not present, then PHYs will be direct children. + cdns,aw2w-max-pipe: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Maximum number of outstanding AXI write requests + + cdns,ar2r-max-pipe: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Maximum number of outstanding AXI read requests + + cdns,use-aw2b-fill: + type: boolean + description: + If set, the maximum number of outstanding write transactions operates + between the AW to B AXI channel, instead of the AW to W AXI channel. + patternProperties: "^ethernet-phy@[0-9a-f]$": type: object diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/net/microchip,lan78xx.txt linux/Documentation/devicetree/bindings/net/microchip,lan78xx.txt --- linux-6.1.66/Documentation/devicetree/bindings/net/microchip,lan78xx.txt 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/net/microchip,lan78xx.txt 2023-12-13 11:50:47.034957588 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:17 @ - microchip,led-modes: a 0..4 element vector, with each element configuring the operating mode of an LED. Omitted LEDs are turned off. Allowed values are defined in "include/dt-bindings/net/microchip-lan78xx.h". +- microchip,downshift-after: sets the number of failed auto-negotiation + attempts after which the link is downgraded from 1000BASE-T. Should be one of + 2, 3, 4, 5 or 0, where 0 means never downshift. Example: diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt linux/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt --- linux-6.1.66/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt 2023-12-13 11:50:47.059957647 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +Brcmstb PCIe Host Controller Device Tree Bindings + +Required Properties: +- compatible + "brcm,bcm7425-pcie" -- for 7425 family MIPS-based SOCs. + "brcm,bcm7435-pcie" -- for 7435 family MIPS-based SOCs. + "brcm,bcm7445-pcie" -- for 7445 and later ARM based SOCs (not including + the 7278). + "brcm,bcm7278-pcie" -- for 7278 family ARM-based SOCs. + +- reg -- the register start address and length for the PCIe reg block. +- interrupts -- two interrupts are specified; the first interrupt is for + the PCI host controller and the second is for MSI if the built-in + MSI controller is to be used. +- interrupt-names -- names of the interrupts (above): "pcie" and "msi". +- #address-cells -- set to <3>. +- #size-cells -- set to <2>. +- #interrupt-cells: set to <1>. +- interrupt-map-mask and interrupt-map, standard PCI properties to define the + mapping of the PCIe interface to interrupt numbers. +- ranges: ranges for the PCI memory and I/O regions. +- linux,pci-domain -- should be unique per host controller. + +Optional Properties: +- clocks -- phandle of pcie clock. +- clock-names -- set to "sw_pcie" if clocks is used. +- dma-ranges -- Specifies the inbound memory mapping regions when + an "identity map" is not possible. +- msi-controller -- this property is typically specified to have the + PCIe controller use its internal MSI controller. +- msi-parent -- set to use an external MSI interrupt controller. +- brcm,enable-ssc -- (boolean) indicates usage of spread-spectrum clocking. +- max-link-speed -- (integer) indicates desired generation of link: + 1 => 2.5 Gbps (gen1), 2 => 5.0 Gbps (gen2), 3 => 8.0 Gbps (gen3). + +Example Node: + +pcie0: pcie@f0460000 { + reg = <0x0 0xf0460000 0x0 0x9310>; + interrupts = <0x0 0x0 0x4>; + compatible = "brcm,bcm7445-pcie"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0x00000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x08000000 + 0x02000000 0x00000000 0x08000000 0x00000000 0xc8000000 0x00000000 0x08000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &intc 0 47 3 + 0 0 0 2 &intc 0 48 3 + 0 0 0 3 &intc 0 49 3 + 0 0 0 4 &intc 0 50 3>; + clocks = <&sw_pcie0>; + clock-names = "sw_pcie"; + msi-parent = <&pcie0>; /* use PCIe's internal MSI controller */ + msi-controller; /* use PCIe's internal MSI controller */ + brcm,ssc; + max-link-speed = <1>; + linux,pci-domain = <0>; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml linux/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml --- linux-6.1.66/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml 2023-12-13 11:50:47.058957645 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:80 @ minItems: 1 maxItems: 3 + brcm,tperst-clk-ms: + category: optional + type: int + description: u32 giving the number of milliseconds to extend + the time between internal release of fundamental reset and + the deassertion of the external PERST# pin. This has the + effect of increasing the Tperst_clk phase of link init. + required: - compatible - reg diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt linux/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt --- linux-6.1.66/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt 2023-12-13 11:50:47.137957831 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +Driver a GPIO line that can be used to turn the power off. + +The driver supports both level triggered and edge triggered power off. +At driver load time, the driver will request the given gpio line and +install a handler to power off the system. If the optional properties +'input' is not found, the GPIO line will be driven in the inactive +state. Otherwise its configured as an input. + +When the power-off handler is called, the gpio is configured as an +output, and drive active, so triggering a level triggered power off +condition. This will also cause an inactive->active edge condition, so +triggering positive edge triggered power off. After a delay of 100ms, +the GPIO is set to inactive, thus causing an active->inactive edge, +triggering negative edge triggered power off. After another 100ms +delay the GPIO is driver active again. If the power is still on and +the CPU still running after a 3000ms delay, a WARN_ON(1) is emitted. + +Required properties: +- compatible : should be "gpio-poweroff". +- gpios : The GPIO to set high/low, see "gpios property" in + Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be + low to power down the board set it to "Active Low", otherwise set + gpio to "Active High". + +Optional properties: +- input : Initially configure the GPIO line as an input. Only reconfigure + it to an output when the power-off handler is called. If this optional + property is not specified, the GPIO is initialized as an output in its + inactive state. +- active-delay-ms: Delay (default 100) to wait after driving gpio active +- inactive-delay-ms: Delay (default 100) to wait after driving gpio inactive +- timeout-ms: Time to wait before asserting a WARN_ON(1). If nothing is + specified, 3000 ms is used. +- export : Export the GPIO line to the sysfs system + +Examples: + +gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio 4 0>; + timeout-ms = <3000>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/pwm/pwm-rp1.yaml linux/Documentation/devicetree/bindings/pwm/pwm-rp1.yaml --- linux-6.1.66/Documentation/devicetree/bindings/pwm/pwm-rp1.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/pwm/pwm-rp1.yaml 2023-12-13 11:50:47.163957892 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-rp1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Raspberry Pi RP1 PWM controller + +maintainers: + - Naushir Patuck <naush@raspberrypi.com> + +properties: + compatible: + enum: + - raspberrypi,rp1-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + pwm0: pwm@98000 { + compatible = "raspberrypi,rp1-pwm"; + reg = <0x0 0x98000 0x0 0x100>; + clocks = <&rp1_sys>; + #pwm-cells = <3>; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/rtc/rtc-rpi.txt linux/Documentation/devicetree/bindings/rtc/rtc-rpi.txt --- linux-6.1.66/Documentation/devicetree/bindings/rtc/rtc-rpi.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/rtc/rtc-rpi.txt 2023-12-13 11:50:47.212958007 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +* Raspberry Pi RTC + +This is a Linux interface to an RTC managed by firmware, hence it's +virtual from a Linux perspective. + +The interface uses the firmware mailbox api to access the RTC registers. + +Required properties: +compatible: should be "raspberrypi,rpi-rtc" +firmware: Reference to the RPi firmware device node. + +Optional property: +trickle-charge-microvolt: specify a trickle charge voltage for the backup + battery in microvolts. + +Example: + + rpi_rtc: rpi_rtc { + compatible = "raspberrypi,rpi-rtc"; + firmware = <&firmware>; + trickle-charge-microvolt = <3000000>; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/serial/pl011.yaml linux/Documentation/devicetree/bindings/serial/pl011.yaml --- linux-6.1.66/Documentation/devicetree/bindings/serial/pl011.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/serial/pl011.yaml 2023-12-13 11:50:47.221958029 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:103 @ on the device. enum: [1, 4] + cts-event-workaround: + description: + Enables the (otherwise vendor-specific) workaround for the + CTS-induced TX lockup. + type: boolean + required: - compatible - reg diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/sound/pcm512x.txt linux/Documentation/devicetree/bindings/sound/pcm512x.txt --- linux-6.1.66/Documentation/devicetree/bindings/sound/pcm512x.txt 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/sound/pcm512x.txt 2023-12-13 11:50:47.277958160 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ -PCM512x audio CODECs +PCM512x and TAS575x audio CODECs/amplifiers These devices support both I2C and SPI (configured with pin strapping -on the board). +on the board). The TAS575x devices only support I2C. Required properties: - - compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141" or - "ti,pcm5142" + - compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141", + "ti,pcm5142", "ti,tas5754" or "ti,tas5756" - reg : the I2C address of the device for I2C, the chip select number for SPI. @ linux/arch/arm/boot/dts/bcm2708.dtsi:28 @ through <6>. The device will be configured for clock input on the given pll-in pin and PLL output on the given pll-out pin. An external connection from the pll-out pin to the SCLK pin is assumed. + Caution: the TAS-desvices only support gpios 1,2 and 3 Examples: diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/spi/spi-gpio.yaml linux/Documentation/devicetree/bindings/spi/spi-gpio.yaml --- linux-6.1.66/Documentation/devicetree/bindings/spi/spi-gpio.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/spi/spi-gpio.yaml 2023-12-13 11:50:47.311958240 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:46 @ with no chip select is connected. $ref: "/schemas/types.yaml#/definitions/uint32" + sck-idle-input: + description: Make SCK an input when inactive. + type: boolean + # Deprecated properties gpio-sck: false gpio-miso: false diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/vendor-prefixes.txt linux/Documentation/devicetree/bindings/vendor-prefixes.txt --- linux-6.1.66/Documentation/devicetree/bindings/vendor-prefixes.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/bindings/vendor-prefixes.txt 2023-12-13 11:50:47.354958342 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +Device tree binding vendor prefix registry. Keep list in alphabetical order. + +This isn't an exhaustive list, but you should add new prefixes to it before +using them to avoid name-space collisions. + +abilis Abilis Systems +abracon Abracon Corporation +actions Actions Semiconductor Co., Ltd. +active-semi Active-Semi International Inc +ad Avionic Design GmbH +adafruit Adafruit Industries, LLC +adapteva Adapteva, Inc. +adaptrum Adaptrum, Inc. +adh AD Holdings Plc. +adi Analog Devices, Inc. +advantech Advantech Corporation +aeroflexgaisler Aeroflex Gaisler AB +al Annapurna Labs +allo Allo.com +allwinner Allwinner Technology Co., Ltd. +alphascale AlphaScale Integrated Circuits Systems, Inc. +altr Altera Corp. +amarula Amarula Solutions +amazon Amazon.com, Inc. +amcc Applied Micro Circuits Corporation (APM, formally AMCC) +amd Advanced Micro Devices (AMD), Inc. +amediatech Shenzhen Amediatech Technology Co., Ltd +amlogic Amlogic, Inc. +ampire Ampire Co., Ltd. +ams AMS AG +amstaos AMS-Taos Inc. +analogix Analogix Semiconductor, Inc. +andestech Andes Technology Corporation +apm Applied Micro Circuits Corporation (APM) +aptina Aptina Imaging +arasan Arasan Chip Systems +archermind ArcherMind Technology (Nanjing) Co., Ltd. +arctic Arctic Sand +aries Aries Embedded GmbH +arm ARM Ltd. +armadeus ARMadeus Systems SARL +arrow Arrow Electronics +artesyn Artesyn Embedded Technologies Inc. +asahi-kasei Asahi Kasei Corp. +aspeed ASPEED Technology Inc. +asus AsusTek Computer Inc. +atlas Atlas Scientific LLC +atmel Atmel Corporation +auo AU Optronics Corporation +auvidea Auvidea GmbH +avago Avago Technologies +avia avia semiconductor +avic Shanghai AVIC Optoelectronics Co., Ltd. +avnet Avnet, Inc. +axentia Axentia Technologies AB +axis Axis Communications AB +bananapi BIPAI KEJI LIMITED +bhf Beckhoff Automation GmbH & Co. KG +bitmain Bitmain Technologies +blokaslabs Vilniaus Blokas UAB +boe BOE Technology Group Co., Ltd. +bosch Bosch Sensortec GmbH +boundary Boundary Devices Inc. +brcm Broadcom Corporation +buffalo Buffalo, Inc. +bticino Bticino International +calxeda Calxeda +capella Capella Microsystems, Inc +cascoda Cascoda, Ltd. +catalyst Catalyst Semiconductor, Inc. +cavium Cavium, Inc. +cdns Cadence Design Systems Inc. +cdtech CDTech(H.K.) Electronics Limited +ceva Ceva, Inc. +chipidea Chipidea, Inc +chipone ChipOne +chipspark ChipSPARK +chrp Common Hardware Reference Platform +chunghwa Chunghwa Picture Tubes Ltd. +ciaa Computadora Industrial Abierta Argentina +cirrus Cirrus Logic, Inc. +cloudengines Cloud Engines, Inc. +cnm Chips&Media, Inc. +cnxt Conexant Systems, Inc. +compulab CompuLab Ltd. +cortina Cortina Systems, Inc. +cosmic Cosmic Circuits +crane Crane Connectivity Solutions +creative Creative Technology Ltd +crystalfontz Crystalfontz America, Inc. +csky Hangzhou C-SKY Microsystems Co., Ltd +cubietech Cubietech, Ltd. +cypress Cypress Semiconductor Corporation +cznic CZ.NIC, z.s.p.o. +dallas Maxim Integrated Products (formerly Dallas Semiconductor) +dataimage DataImage, Inc. +davicom DAVICOM Semiconductor, Inc. +delta Delta Electronics, Inc. +denx Denx Software Engineering +devantech Devantech, Ltd. +dh DH electronics GmbH +digi Digi International Inc. +digilent Diglent, Inc. +dioo Dioo Microcircuit Co., Ltd +dlc DLC Display Co., Ltd. +dlg Dialog Semiconductor +dlink D-Link Corporation +dmo Data Modul AG +domintech Domintech Co., Ltd. +dongwoon Dongwoon Anatech +dptechnics DPTechnics +dragino Dragino Technology Co., Limited +ea Embedded Artists AB +ebs-systart EBS-SYSTART GmbH +ebv EBV Elektronik +eckelmann Eckelmann AG +edt Emerging Display Technologies +eeti eGalax_eMPIA Technology Inc +elan Elan Microelectronic Corp. +elgin Elgin S/A. +embest Shenzhen Embest Technology Co., Ltd. +emlid Emlid, Ltd. +emmicro EM Microelectronic +emtrion emtrion GmbH +endless Endless Mobile, Inc. +energymicro Silicon Laboratories (formerly Energy Micro AS) +engicam Engicam S.r.l. +epcos EPCOS AG +epfl Ecole Polytechnique Fédérale de Lausanne +epson Seiko Epson Corp. +est ESTeem Wireless Modems +ettus NI Ettus Research +eukrea Eukréa Electromatique +everest Everest Semiconductor Co. Ltd. +everspin Everspin Technologies, Inc. +exar Exar Corporation +excito Excito +ezchip EZchip Semiconductor +facebook Facebook +fairphone Fairphone B.V. +faraday Faraday Technology Corporation +fastrax Fastrax Oy +fcs Fairchild Semiconductor +feiyang Shenzhen Fly Young Technology Co.,LTD. +firefly Firefly +focaltech FocalTech Systems Co.,Ltd +friendlyarm Guangzhou FriendlyARM Computer Tech Co., Ltd +fsl Freescale Semiconductor +fujitsu Fujitsu Ltd. +gateworks Gateworks Corporation +gcw Game Consoles Worldwide +ge General Electric Company +geekbuying GeekBuying +gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. +GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. +geniatech Geniatech, Inc. +giantec Giantec Semiconductor, Inc. +giantplus Giantplus Technology Co., Ltd. +globalscale Globalscale Technologies, Inc. +globaltop GlobalTop Technology, Inc. +gmt Global Mixed-mode Technology, Inc. +goodix Shenzhen Huiding Technology Co., Ltd. +google Google, Inc. +grinn Grinn +grmn Garmin Limited +gumstix Gumstix, Inc. +gw Gateworks Corporation +hannstar HannStar Display Corporation +haoyu Haoyu Microelectronic Co. Ltd. +hardkernel Hardkernel Co., Ltd +hideep HiDeep Inc. +himax Himax Technologies, Inc. +hisilicon Hisilicon Limited. +hit Hitachi Ltd. +hitex Hitex Development Tools +holt Holt Integrated Circuits, Inc. +honeywell Honeywell +hp Hewlett Packard +holtek Holtek Semiconductor, Inc. +hwacom HwaCom Systems Inc. +i2se I2SE GmbH +ibm International Business Machines (IBM) +icplus IC Plus Corp. +idt Integrated Device Technologies, Inc. +ifi Ingenieurburo Fur Ic-Technologie (I/F/I) +ilitek ILI Technology Corporation (ILITEK) +img Imagination Technologies Ltd. +infineon Infineon Technologies +inforce Inforce Computing +ingenic Ingenic Semiconductor +innolux Innolux Corporation +inside-secure INSIDE Secure +intel Intel Corporation +intercontrol Inter Control Group +invensense InvenSense Inc. +inversepath Inverse Path +iom Iomega Corporation +isee ISEE 2007 S.L. +isil Intersil +issi Integrated Silicon Solutions Inc. +itead ITEAD Intelligent Systems Co.Ltd +iwave iWave Systems Technologies Pvt. Ltd. +jdi Japan Display Inc. +jedec JEDEC Solid State Technology Association +jianda Jiandangjing Technology Co., Ltd. +karo Ka-Ro electronics GmbH +keithkoep Keith & Koep GmbH +keymile Keymile GmbH +khadas Khadas +kiebackpeter Kieback & Peter GmbH +kinetic Kinetic Technologies +kingdisplay King & Display Technology Co., Ltd. +kingnovel Kingnovel Technology Co., Ltd. +koe Kaohsiung Opto-Electronics Inc. +kosagi Sutajio Ko-Usagi PTE Ltd. +kyo Kyocera Corporation +lacie LaCie +laird Laird PLC +lantiq Lantiq Semiconductor +lattice Lattice Semiconductor +lego LEGO Systems A/S +lemaker Shenzhen LeMaker Technology Co., Ltd. +lenovo Lenovo Group Ltd. +lg LG Corporation +libretech Shenzhen Libre Technology Co., Ltd +licheepi Lichee Pi +linaro Linaro Limited +linksys Belkin International, Inc. (Linksys) +linux Linux-specific binding +linx Linx Technologies +lltc Linear Technology Corporation +logicpd Logic PD, Inc. +lsi LSI Corp. (LSI Logic) +lwn Liebherr-Werk Nenzing GmbH +macnica Macnica Americas +marvell Marvell Technology Group Ltd. +maxim Maxim Integrated Products +mbvl Mobiveil Inc. +mcube mCube +meas Measurement Specialties +mediatek MediaTek Inc. +megachips MegaChips +mele Shenzhen MeLE Digital Technology Ltd. +melexis Melexis N.V. +melfas MELFAS Inc. +mellanox Mellanox Technologies +memsic MEMSIC Inc. +merrii Merrii Technology Co., Ltd. +micrel Micrel Inc. +microchip Microchip Technology Inc. +microcrystal Micro Crystal AG +micron Micron Technology Inc. +mikroe MikroElektronika d.o.o. +minix MINIX Technology Ltd. +miramems MiraMEMS Sensing Technology Co., Ltd. +mitsubishi Mitsubishi Electric Corporation +mosaixtech Mosaix Technologies, Inc. +motorola Motorola, Inc. +moxa Moxa Inc. +mpl MPL AG +mqmaker mqmaker Inc. +mscc Microsemi Corporation +msi Micro-Star International Co. Ltd. +mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.) +multi-inno Multi-Inno Technology Co.,Ltd +mundoreader Mundo Reader S.L. +murata Murata Manufacturing Co., Ltd. +mxicy Macronix International Co., Ltd. +myir MYIR Tech Limited +national National Semiconductor +nec NEC LCD Technologies, Ltd. +neonode Neonode Inc. +netgear NETGEAR +netlogic Broadcom Corporation (formerly NetLogic Microsystems) +netron-dy Netron DY +netxeon Shenzhen Netxeon Technology CO., LTD +nexbox Nexbox +nextthing Next Thing Co. +newhaven Newhaven Display International +ni National Instruments +nintendo Nintendo +nlt NLT Technologies, Ltd. +nokia Nokia +nordic Nordic Semiconductor +novtech NovTech, Inc. +nutsboard NutsBoard +nuvoton Nuvoton Technology Corporation +nvd New Vision Display +nvidia NVIDIA +nxp NXP Semiconductors +okaya Okaya Electric America, Inc. +oki Oki Electric Industry Co., Ltd. +olimex OLIMEX Ltd. +olpc One Laptop Per Child +onion Onion Corporation +onnn ON Semiconductor Corp. +ontat On Tat Industrial Company +opalkelly Opal Kelly Incorporated +opencores OpenCores.org +openrisc OpenRISC.io +option Option NV +oranth Shenzhen Oranth Technology Co., Ltd. +ORCL Oracle Corporation +orisetech Orise Technology +ortustech Ortus Technology Co., Ltd. +ovti OmniVision Technologies +oxsemi Oxford Semiconductor, Ltd. +panasonic Panasonic Corporation +parade Parade Technologies Inc. +pda Precision Design Associates, Inc. +pericom Pericom Technology Inc. +pervasive Pervasive Displays, Inc. +phicomm PHICOMM Co., Ltd. +phytec PHYTEC Messtechnik GmbH +picochip Picochip Ltd +pine64 Pine64 +pixcir PIXCIR MICROELECTRONICS Co., Ltd +plantower Plantower Co., Ltd +plathome Plat'Home Co., Ltd. +plda PLDA +plx Broadcom Corporation (formerly PLX Technology) +pni PNI Sensor Corporation +portwell Portwell Inc. +poslab Poslab Technology Co., Ltd. +powervr PowerVR (deprecated, use img) +probox2 PROBOX2 (by W2COMP Co., Ltd.) +pulsedlight PulsedLight, Inc +qca Qualcomm Atheros, Inc. +qcom Qualcomm Technologies, Inc +qemu QEMU, a generic and open source machine emulator and virtualizer +qi Qi Hardware +qiaodian QiaoDian XianShi Corporation +qnap QNAP Systems, Inc. +radxa Radxa +raidsonic RaidSonic Technology GmbH +ralink Mediatek/Ralink Technology Corp. +ramtron Ramtron International +raspberrypi Raspberry Pi Foundation +raydium Raydium Semiconductor Corp. +rda Unisoc Communications, Inc. +realtek Realtek Semiconductor Corp. +renesas Renesas Electronics Corporation +richtek Richtek Technology Corporation +ricoh Ricoh Co. Ltd. +rikomagic Rikomagic Tech Corp. Ltd +riscv RISC-V Foundation +rockchip Fuzhou Rockchip Electronics Co., Ltd +rohm ROHM Semiconductor Co., Ltd +roofull Shenzhen Roofull Technology Co, Ltd +samsung Samsung Semiconductor +samtec Samtec/Softing company +sancloud Sancloud Ltd +sandisk Sandisk Corporation +sbs Smart Battery System +schindler Schindler +seagate Seagate Technology PLC +semtech Semtech Corporation +sensirion Sensirion AG +sff Small Form Factor Committee +sgd Solomon Goldentek Display Corporation +sgx SGX Sensortech +sharp Sharp Corporation +shimafuji Shimafuji Electric, Inc. +si-en Si-En Technology Ltd. +sifive SiFive, Inc. +sigma Sigma Designs, Inc. +sii Seiko Instruments, Inc. +sil Silicon Image +silabs Silicon Laboratories +silead Silead Inc. +silergy Silergy Corp. +siliconmitus Silicon Mitus, Inc. +simtek +sirf SiRF Technology, Inc. +sis Silicon Integrated Systems Corp. +sitronix Sitronix Technology Corporation +skyworks Skyworks Solutions, Inc. +smsc Standard Microsystems Corporation +snps Synopsys, Inc. +socionext Socionext Inc. +solidrun SolidRun +solomon Solomon Systech Limited +sony Sony Corporation +spansion Spansion Inc. +sprd Spreadtrum Communications Inc. +sst Silicon Storage Technology, Inc. +st STMicroelectronics +starry Starry Electronic Technology (ShenZhen) Co., LTD +startek Startek +ste ST-Ericsson +stericsson ST-Ericsson +summit Summit microelectronics +sunchip Shenzhen Sunchip Technology Co., Ltd +SUNW Sun Microsystems, Inc +swir Sierra Wireless +syna Synaptics Inc. +synology Synology, Inc. +tbs TBS Technologies +tbs-biometrics Touchless Biometric Systems AG +tcg Trusted Computing Group +tcl Toby Churchill Ltd. +technexion TechNexion +technologic Technologic Systems +tempo Tempo Semiconductor +techstar Shenzhen Techstar Electronics Co., Ltd. +terasic Terasic Inc. +thine THine Electronics, Inc. +ti Texas Instruments +tianma Tianma Micro-electronics Co., Ltd. +tlm Trusted Logic Mobility +tmt Tecon Microprocessor Technologies, LLC. +topeet Topeet +toradex Toradex AG +toshiba Toshiba Corporation +toumaz Toumaz +tpk TPK U.S.A. LLC +tplink TP-LINK Technologies Co., Ltd. +tpo TPO +tronfy Tronfy +tronsmart Tronsmart +truly Truly Semiconductors Limited +tsd Theobroma Systems Design und Consulting GmbH +tyan Tyan Computer Corporation +u-blox u-blox +ucrobotics uCRobotics +ubnt Ubiquiti Networks +udoo Udoo +uniwest United Western Technologies Corp (UniWest) +upisemi uPI Semiconductor Corp. +urt United Radiant Technology Corporation +usi Universal Scientific Industrial Co., Ltd. +v3 V3 Semiconductor +vamrs Vamrs Ltd. +variscite Variscite Ltd. +via VIA Technologies, Inc. +virtio Virtual I/O Device Specification, developed by the OASIS consortium +vishay Vishay Intertechnology, Inc +vitesse Vitesse Semiconductor Corporation +vivante Vivante Corporation +vocore VoCore Studio +voipac Voipac Technologies s.r.o. +vot Vision Optical Technology Co., Ltd. +wd Western Digital Corp. +wetek WeTek Electronics, limited. +wexler Wexler +whwave Shenzhen whwave Electronics, Inc. +wi2wi Wi2Wi, Inc. +winbond Winbond Electronics corp. +winstar Winstar Display Corp. +wlf Wolfson Microelectronics +wm Wondermedia Technologies, Inc. +x-powers X-Powers +xes Extreme Engineering Solutions (X-ES) +xillybus Xillybus Ltd. +xlnx Xilinx +xunlong Shenzhen Xunlong Software CO.,Limited +ysoft Y Soft Corporation a.s. +zarlink Zarlink Semiconductor +zeitec ZEITEC Semiconductor Co., LTD. +zidoo Shenzhen Zidoo Technology Co., Ltd. +zii Zodiac Inflight Innovations +zte ZTE Corp. +zyxel ZyXEL Communications Corp. diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/bindings/vendor-prefixes.yaml linux/Documentation/devicetree/bindings/vendor-prefixes.yaml --- linux-6.1.66/Documentation/devicetree/bindings/vendor-prefixes.yaml 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/devicetree/bindings/vendor-prefixes.yaml 2023-12-13 11:50:47.354958342 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:130 @ description: arcx Inc. / Archronix Inc. "^aries,.*": description: Aries Embedded GmbH + "^arducam,.*": + description: Arducam Technology co., Ltd. "^arm,.*": description: ARM Ltd. "^armadeus,.*": @ linux/arch/arm/boot/dts/bcm2708.dtsi:193 @ description: Beckhoff Automation GmbH & Co. KG "^bitmain,.*": description: Bitmain Technologies + "^blokaslabs,.*": + description: Vilniaus Blokas UAB "^blutek,.*": description: BluTek Power "^boe,.*": @ linux/arch/arm/boot/dts/bcm2708.dtsi:489 @ description: General Electric Company "^geekbuying,.*": description: GeekBuying + "^geekworm,.*": + description: Geekworm "^gef,.*": description: GE Fanuc Intelligent Platforms Embedded Systems, Inc. "^GEFanuc,.*": diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/devicetree/configfs-overlays.txt linux/Documentation/devicetree/configfs-overlays.txt --- linux-6.1.66/Documentation/devicetree/configfs-overlays.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/devicetree/configfs-overlays.txt 2023-12-13 11:50:47.388958422 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +Howto use the configfs overlay interface. + +A device-tree configfs entry is created in /config/device-tree/overlays +and and it is manipulated using standard file system I/O. +Note that this is a debug level interface, for use by developers and +not necessarily something accessed by normal users due to the +security implications of having direct access to the kernel's device tree. + +* To create an overlay you mkdir the directory: + + # mkdir /config/device-tree/overlays/foo + +* Either you echo the overlay firmware file to the path property file. + + # echo foo.dtbo >/config/device-tree/overlays/foo/path + +* Or you cat the contents of the overlay to the dtbo file + + # cat foo.dtbo >/config/device-tree/overlays/foo/dtbo + +The overlay file will be applied, and devices will be created/destroyed +as required. + +To remove it simply rmdir the directory. + + # rmdir /config/device-tree/overlays/foo + +The rationalle of the dual interface (firmware & direct copy) is that each is +better suited to different use patterns. The firmware interface is what's +intended to be used by hardware managers in the kernel, while the copy interface +make sense for developers (since it avoids problems with namespaces). diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/dev-tools/kunit/usage.rst linux/Documentation/dev-tools/kunit/usage.rst --- linux-6.1.66/Documentation/dev-tools/kunit/usage.rst 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/dev-tools/kunit/usage.rst 2023-12-13 11:50:46.575956508 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:628 @ Accessing The Current Test -------------------------- -In some cases, we need to call test-only code from outside the test file. -For example, see example in section *Injecting Test-Only Code* or if -we are providing a fake implementation of an ops struct. Using -``kunit_test`` field in ``task_struct``, we can access it via -``current->kunit_test``. +In some cases, we need to call test-only code from outside the test file. This +is helpful, for example, when providing a fake implementation of a function, or +to fail any current test from within an error handler. +We can do this via the ``kunit_test`` field in ``task_struct``, which we can +access using the ``kunit_get_current_test()`` function in ``kunit/test-bug.h``. + +``kunit_get_current_test()`` is safe to call even if KUnit is not enabled. If +KUnit is not enabled, was built as a module (``CONFIG_KUNIT=m``), or no test is +running in the current task, it will return ``NULL``. This compiles down to +either a no-op or a static key check, so will have a negligible performance +impact when no test is running. -The example below includes how to implement "mocking": +The example below uses this to implement a "mock" implementation of a function, ``foo``: .. code-block:: c - #include <linux/sched.h> /* for current */ + #include <kunit/test-bug.h> /* for kunit_get_current_test */ struct test_data { int foo_result; @ linux/arch/arm/boot/dts/bcm2708.dtsi:653 @ static int fake_foo(int arg) { - struct kunit *test = current->kunit_test; + struct kunit *test = kunit_get_current_test(); struct test_data *test_data = test->priv; KUNIT_EXPECT_EQ(test, test_data->want_foo_called_with, arg); @ linux/arch/arm/boot/dts/bcm2708.dtsi:684 @ flexibility as a ``priv`` member, but also, for example, allowing helper functions to create resources without conflicting with each other. It is also possible to define a clean up function for each resource, making it easy to -avoid resource leaks. For more information, see Documentation/dev-tools/kunit/api/test.rst. +avoid resource leaks. For more information, see Documentation/dev-tools/kunit/api/resource.rst. Failing The Current Test ------------------------ @ linux/arch/arm/boot/dts/bcm2708.dtsi:712 @ static void my_debug_function(void) { } #endif +``kunit_fail_current_test()`` is safe to call even if KUnit is not enabled. If +KUnit is not enabled, was built as a module (``CONFIG_KUNIT=m``), or no test is +running in the current task, it will do nothing. This compiles down to either a +no-op or a static key check, so will have a negligible performance impact when +no test is running. + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/driver-api/media/v4l2-cci.rst linux/Documentation/driver-api/media/v4l2-cci.rst --- linux-6.1.66/Documentation/driver-api/media/v4l2-cci.rst 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/driver-api/media/v4l2-cci.rst 2023-12-13 11:50:47.426958511 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:2 @ +.. SPDX-License-Identifier: GPL-2.0 + +V4L2 CCI kAPI +^^^^^^^^^^^^^ +.. kernel-doc:: include/media/v4l2-cci.h diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/driver-api/media/v4l2-core.rst linux/Documentation/driver-api/media/v4l2-core.rst --- linux-6.1.66/Documentation/driver-api/media/v4l2-core.rst 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/driver-api/media/v4l2-core.rst 2023-12-13 11:50:47.427958513 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:25 @ v4l2-mem2mem v4l2-async v4l2-fwnode + v4l2-cci v4l2-rect v4l2-tuner v4l2-common diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/gpu/vc4.rst linux/Documentation/gpu/vc4.rst --- linux-6.1.66/Documentation/gpu/vc4.rst 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/gpu/vc4.rst 2023-12-13 11:50:47.548958798 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:57 @ .. kernel-doc:: drivers/gpu/drm/vc4/vc4_vec.c :doc: VC4 SDTV module +KUnit Tests +=========== + +The VC4 Driver uses KUnit to perform driver-specific unit and +integration tests. + +These tests are using a mock driver and can be ran using the +command:: + ./tools/testing/kunit/kunit.py run \ + --kunitconfig=drivers/gpu/drm/vc4/tests/.kunitconfig \ + --cross_compile aarch64-linux-gnu- --arch arm64 + +Parts of the driver that are currently covered by tests are: + * The HVS to PixelValve dynamic FIFO assignment, for the BCM2835-7 + and BCM2711. + Memory Management and 3D Command Submission =========================================== diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/userspace-api/media/drivers/index.rst linux/Documentation/userspace-api/media/drivers/index.rst --- linux-6.1.66/Documentation/userspace-api/media/drivers/index.rst 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/userspace-api/media/drivers/index.rst 2023-12-13 11:50:47.960959768 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:38 @ cx2341x-uapi dw100 imx-uapi + bcm2835-isp max2175 meye-uapi omap3isp-uapi diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/userspace-api/media/v4l/meta-formats.rst linux/Documentation/userspace-api/media/v4l/meta-formats.rst --- linux-6.1.66/Documentation/userspace-api/media/v4l/meta-formats.rst 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/userspace-api/media/v4l/meta-formats.rst 2023-12-13 11:50:48.006959877 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:15 @ .. toctree:: :maxdepth: 1 + pixfmt-meta-bcm2835-isp-stats pixfmt-meta-d4xx pixfmt-meta-intel-ipu3 pixfmt-meta-rkisp1 + pixfmt-meta-sensor-data pixfmt-meta-uvc pixfmt-meta-vsp1-hgo pixfmt-meta-vsp1-hgt diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/userspace-api/media/v4l/pixfmt-meta-bcm2835-isp-stats.rst linux/Documentation/userspace-api/media/v4l/pixfmt-meta-bcm2835-isp-stats.rst --- linux-6.1.66/Documentation/userspace-api/media/v4l/pixfmt-meta-bcm2835-isp-stats.rst 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/userspace-api/media/v4l/pixfmt-meta-bcm2835-isp-stats.rst 2023-12-13 11:50:48.008959882 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +.. Permission is granted to copy, distribute and/or modify this +.. document under the terms of the GNU Free Documentation License, +.. Version 1.1 or any later version published by the Free Software +.. Foundation, with no Invariant Sections, no Front-Cover Texts +.. and no Back-Cover Texts. A copy of the license is included at +.. Documentation/media/uapi/fdl-appendix.rst. +.. +.. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections + +.. _v4l2-meta-fmt-bcm2835-isp-stats: + +***************************************** +V4L2_META_FMT_BCM2835_ISP_STATS ('BSTA') +***************************************** + +BCM2835 ISP Statistics + +Description +=========== + +The BCM2835 ISP hardware calculate image statistics for an input Bayer frame. +These statistics are obtained from the "bcm2835-isp0-capture3" device node +using the :c:type:`v4l2_meta_format` interface. They are formatted as described +by the :c:type:`bcm2835_isp_stats` structure below. + +.. code-block:: c + + #define DEFAULT_AWB_REGIONS_X 16 + #define DEFAULT_AWB_REGIONS_Y 12 + + #define NUM_HISTOGRAMS 2 + #define NUM_HISTOGRAM_BINS 128 + #define AWB_REGIONS (DEFAULT_AWB_REGIONS_X * DEFAULT_AWB_REGIONS_Y) + #define FLOATING_REGIONS 16 + #define AGC_REGIONS 16 + #define FOCUS_REGIONS 12 + +.. kernel-doc:: include/uapi/linux/bcm2835-isp.h + :functions: bcm2835_isp_stats_hist bcm2835_isp_stats_region + bcm2835_isp_stats_focus bcm2835_isp_stats + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/userspace-api/media/v4l/pixfmt-meta-sensor-data.rst linux/Documentation/userspace-api/media/v4l/pixfmt-meta-sensor-data.rst --- linux-6.1.66/Documentation/userspace-api/media/v4l/pixfmt-meta-sensor-data.rst 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/userspace-api/media/v4l/pixfmt-meta-sensor-data.rst 2023-12-13 11:50:48.009959884 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +.. Permission is granted to copy, distribute and/or modify this +.. document under the terms of the GNU Free Documentation License, +.. Version 1.1 or any later version published by the Free Software +.. Foundation, with no Invariant Sections, no Front-Cover Texts +.. and no Back-Cover Texts. A copy of the license is included at +.. Documentation/media/uapi/fdl-appendix.rst. +.. +.. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections + +.. _v4l2-meta-fmt-sensor-data: + +*********************************** +V4L2_META_FMT_SENSOR_DATA ('SENS') +*********************************** + +Sensor Ancillary Metadata + +Description +=========== + +This format describes ancillary data generated by a camera sensor and +transmitted over a stream on the camera bus. Sensor vendors generally have their +own custom format for this ancillary data. Some vendors follow a generic +CSI-2/SMIA embedded data format as described in the `CSI-2 specification. +<https://mipi.org/specifications/csi-2>`_ + +The size of the embedded buffer is defined as a single line with a pixel width +width specified in bytes. This is obtained by a call to the +:c:type:`VIDIOC_SUBDEV_G_FMT` ioctl on the sensor subdevice where the ``pad`` +field in :c:type:`v4l2_subdev_format` is set to 1. Note that this size is fixed +and cannot be modified with a call to :c:type:`VIDIOC_SUBDEV_S_FMT`. + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/userspace-api/media/v4l/pixfmt-nv12-col128.rst linux/Documentation/userspace-api/media/v4l/pixfmt-nv12-col128.rst --- linux-6.1.66/Documentation/userspace-api/media/v4l/pixfmt-nv12-col128.rst 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/userspace-api/media/v4l/pixfmt-nv12-col128.rst 2023-12-13 11:50:48.010959886 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +.. Permission is granted to copy, distribute and/or modify this +.. document under the terms of the GNU Free Documentation License, +.. Version 1.1 or any later version published by the Free Software +.. Foundation, with no Invariant Sections, no Front-Cover Texts +.. and no Back-Cover Texts. A copy of the license is included at +.. Documentation/media/uapi/fdl-appendix.rst. +.. +.. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections + +.. _V4L2_PIX_FMT_NV12_COL128: +.. _V4L2_PIX_FMT_NV12_10_COL128: + +******************************************************************************** +V4L2_PIX_FMT_NV12_COL128, V4L2_PIX_FMT_NV12_10_COL128 +******************************************************************************** + + +V4L2_PIX_FMT_NV21_COL128 +Formats with ½ horizontal and vertical chroma resolution. This format +has two planes - one for luminance and one for chrominance. Chroma +samples are interleaved. The difference to ``V4L2_PIX_FMT_NV12`` is the +memory layout. The image is split into columns of 128 bytes wide rather than +being in raster order. + +V4L2_PIX_FMT_NV12_10_COL128 +Follows the same pattern as ``V4L2_PIX_FMT_NV21_COL128`` with 128 byte, but is +a 10bit format with 3 10-bit samples being packed into 4 bytes. Each 128 byte +wide column therefore contains 96 samples. + + +Description +=========== + +This is the two-plane versions of the YUV 4:2:0 format where data is +grouped into 128 byte wide columns. The three components are separated into +two sub-images or planes. The Y plane has one byte per pixel and pixels +are grouped into 128 byte wide columns. The CbCr plane has the same width, +in bytes, as the Y plane (and the image), but is half as tall in pixels. +The chroma plane is also in 128 byte columns, reflecting 64 Cb and 64 Cr +samples. + +The chroma samples for a column follow the luma samples. If there is any +paddding, then that will be reflected via the selection API. +The luma height must be a multiple of 2 lines. + +The normal bytesperline is effectively fixed at 128. However the format +requires knowledge of the stride between columns, therefore the bytesperline +value has been repurposed to denote the number of 128 byte long lines between +the start of each column. + +**Byte Order.** + + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + :widths: 12 12 12 12 12 4 12 12 12 12 + + * - start + 0: + - Y'\ :sub:`0,0` + - Y'\ :sub:`0,1` + - Y'\ :sub:`0,2` + - Y'\ :sub:`0,3` + - ... + - Y'\ :sub:`0,124` + - Y'\ :sub:`0,125` + - Y'\ :sub:`0,126` + - Y'\ :sub:`0,127` + * - start + 128: + - Y'\ :sub:`1,0` + - Y'\ :sub:`1,1` + - Y'\ :sub:`1,2` + - Y'\ :sub:`1,3` + - ... + - Y'\ :sub:`1,124` + - Y'\ :sub:`1,125` + - Y'\ :sub:`1,126` + - Y'\ :sub:`1,127` + * - start + 256: + - Y'\ :sub:`2,0` + - Y'\ :sub:`2,1` + - Y'\ :sub:`2,2` + - Y'\ :sub:`2,3` + - ... + - Y'\ :sub:`2,124` + - Y'\ :sub:`2,125` + - Y'\ :sub:`2,126` + - Y'\ :sub:`2,127` + * - ... + - ... + - ... + - ... + - ... + - ... + - ... + - ... + * - start + ((height-1) * 128): + - Y'\ :sub:`height-1,0` + - Y'\ :sub:`height-1,1` + - Y'\ :sub:`height-1,2` + - Y'\ :sub:`height-1,3` + - ... + - Y'\ :sub:`height-1,124` + - Y'\ :sub:`height-1,125` + - Y'\ :sub:`height-1,126` + - Y'\ :sub:`height-1,127` + * - start + ((height) * 128): + - Cb\ :sub:`0,0` + - Cr\ :sub:`0,0` + - Cb\ :sub:`0,1` + - Cr\ :sub:`0,1` + - ... + - Cb\ :sub:`0,62` + - Cr\ :sub:`0,62` + - Cb\ :sub:`0,63` + - Cr\ :sub:`0,63` + * - start + ((height+1) * 128): + - Cb\ :sub:`1,0` + - Cr\ :sub:`1,0` + - Cb\ :sub:`1,1` + - Cr\ :sub:`1,1` + - ... + - Cb\ :sub:`1,62` + - Cr\ :sub:`1,62` + - Cb\ :sub:`1,63` + - Cr\ :sub:`1,63` + * - ... + - ... + - ... + - ... + - ... + - ... + - ... + - ... + * - start + ((height+(height/2)-1) * 128): + - Cb\ :sub:`(height/2)-1,0` + - Cr\ :sub:`(height/2)-1,0` + - Cb\ :sub:`(height/2)-1,1` + - Cr\ :sub:`(height/2)-1,1` + - ... + - Cb\ :sub:`(height/2)-1,62` + - Cr\ :sub:`(height/2)-1,62` + - Cb\ :sub:`(height/2)-1,63` + - Cr\ :sub:`(height/2)-1,63` + * - start + (bytesperline * 128): + - Y'\ :sub:`0,128` + - Y'\ :sub:`0,129` + - Y'\ :sub:`0,130` + - Y'\ :sub:`0,131` + - ... + - Y'\ :sub:`0,252` + - Y'\ :sub:`0,253` + - Y'\ :sub:`0,254` + - Y'\ :sub:`0,255` + * - ... + - ... + - ... + - ... + - ... + - ... + - ... + - ... + +V4L2_PIX_FMT_NV12_10_COL128 uses the same 128 byte column structure, but +encodes 10-bit YUV. +3 10-bit values are packed into 4 bytes as bits 9:0, 19:10, and 29:20, with +bits 30 & 31 unused. For the luma plane, bits 9:0 are Y0, 19:10 are Y1, and +29:20 are Y2. For the chroma plane the samples always come in pairs of Cr +and Cb, so it needs to be considered 6 values packed in 8 bytes. + +Bit-packed representation. + +.. raw:: latex + + \small + +.. tabularcolumns:: |p{1.2cm}||p{1.2cm}||p{1.2cm}||p{1.2cm}|p{3.2cm}|p{3.2cm}| + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + :widths: 8 8 8 8 + + * - Y'\ :sub:`00[7:0]` + - Y'\ :sub:`01[5:0] (bits 7--2)` Y'\ :sub:`00[9:8]`\ (bits 1--0) + - Y'\ :sub:`02[3:0] (bits 7--4)` Y'\ :sub:`01[9:6]`\ (bits 3--0) + - unused (bits 7--6)` Y'\ :sub:`02[9:4]`\ (bits 5--0) + +.. raw:: latex + + \small + +.. tabularcolumns:: |p{1.2cm}||p{1.2cm}||p{1.2cm}||p{1.2cm}|p{3.2cm}|p{3.2cm}| + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + :widths: 12 12 12 12 12 12 12 12 + + * - Cb\ :sub:`00[7:0]` + - Cr\ :sub:`00[5:0]`\ (bits 7--2) Cb\ :sub:`00[9:8]`\ (bits 1--0) + - Cb\ :sub:`01[3:0]`\ (bits 7--4) Cr\ :sub:`00[9:6]`\ (bits 3--0) + - unused (bits 7--6) Cb\ :sub:`02[9:4]`\ (bits 5--0) + - Cr\ :sub:`01[7:0]` + - Cb\ :sub:`02[5:0]`\ (bits 7--2) Cr\ :sub:`01[9:8]`\ (bits 1--0) + - Cr\ :sub:`02[3:0]`\ (bits 7--4) Cb\ :sub:`02[9:6]`\ (bits 3--0) + - unused (bits 7--6) Cr\ :sub:`02[9:4]`\ (bits 5--0) + +.. raw:: latex + + \normalsize + + + + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/userspace-api/media/v4l/pixfmt-y12p.rst linux/Documentation/userspace-api/media/v4l/pixfmt-y12p.rst --- linux-6.1.66/Documentation/userspace-api/media/v4l/pixfmt-y12p.rst 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/userspace-api/media/v4l/pixfmt-y12p.rst 2023-12-13 11:50:48.015959898 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +.. Permission is granted to copy, distribute and/or modify this +.. document under the terms of the GNU Free Documentation License, +.. Version 1.1 or any later version published by the Free Software +.. Foundation, with no Invariant Sections, no Front-Cover Texts +.. and no Back-Cover Texts. A copy of the license is included at +.. Documentation/media/uapi/fdl-appendix.rst. +.. +.. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections + +.. _V4L2-PIX-FMT-Y12P: + +****************************** +V4L2_PIX_FMT_Y12P ('Y12P') +****************************** + +Grey-scale image as a MIPI RAW12 packed array + + +Description +=========== + +This is a packed grey-scale image format with a depth of 12 bits per +pixel. Two consecutive pixels are packed into 3 bytes. The first 2 bytes +contain the 8 high order bits of the pixels, and the 3rd byte contains the 4 +least significants bits of each pixel, in the same order. + +**Byte Order.** +Each cell is one byte. + +.. tabularcolumns:: |p{2.2cm}|p{1.2cm}|p{1.2cm}|p{3.1cm}| + + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + :widths: 2 1 1 1 + + + - - start + 0: + - Y'\ :sub:`00high` + - Y'\ :sub:`01high` + - Y'\ :sub:`01low`\ (bits 7--4) + + Y'\ :sub:`00low`\ (bits 3--0) + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/userspace-api/media/v4l/pixfmt-y14p.rst linux/Documentation/userspace-api/media/v4l/pixfmt-y14p.rst --- linux-6.1.66/Documentation/userspace-api/media/v4l/pixfmt-y14p.rst 1970-01-01 01:00:00.000000000 +0100 +++ linux/Documentation/userspace-api/media/v4l/pixfmt-y14p.rst 2023-12-13 11:50:48.015959898 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +.. Permission is granted to copy, distribute and/or modify this +.. document under the terms of the GNU Free Documentation License, +.. Version 1.1 or any later version published by the Free Software +.. Foundation, with no Invariant Sections, no Front-Cover Texts +.. and no Back-Cover Texts. A copy of the license is included at +.. Documentation/media/uapi/fdl-appendix.rst. +.. +.. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections + +.. _V4L2-PIX-FMT-Y14P: + +************************** +V4L2_PIX_FMT_Y14P ('Y14P') +************************** + +Grey-scale image as a MIPI RAW14 packed array + + +Description +=========== + +This is a packed grey-scale image format with a depth of 14 bits per +pixel. Every four consecutive samples are packed into seven bytes. Each +of the first four bytes contain the eight high order bits of the pixels, +and the three following bytes contains the six least significants bits of +each pixel, in the same order. + +**Byte Order.** +Each cell is one byte. + +.. tabularcolumns:: |p{1.8cm}|p{1.0cm}|p{1.0cm}|p{1.0cm}|p{1.1cm}|p{3.3cm}|p{3.3cm}|p{3.3cm}| + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + :widths: 2 1 1 1 1 3 3 3 + + + - - start + 0: + - Y'\ :sub:`00high` + - Y'\ :sub:`01high` + - Y'\ :sub:`02high` + - Y'\ :sub:`03high` + - Y'\ :sub:`01low bits 1--0`\ (bits 7--6) + + Y'\ :sub:`00low bits 5--0`\ (bits 5--0) + + - Y'\ :sub:`02low bits 3--0`\ (bits 7--4) + + Y'\ :sub:`01low bits 5--2`\ (bits 3--0) + + - Y'\ :sub:`03low bits 5--0`\ (bits 7--2) + + Y'\ :sub:`02low bits 5--4`\ (bits 1--0) diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst linux/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst --- linux-6.1.66/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst 2023-12-13 11:50:48.016959900 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:582 @ - Cr\ :sub:`11` +V4L2_PIX_FMT_NV12_COL128 +------------------------ + +``V4L2_PIX_FMT_NV12_COL128`` is the tiled version of +``V4L2_PIX_FMT_NV12`` with the image broken down into 128 pixel wide columns of +Y followed by the associated combined CbCr plane. +The normal bytesperline is effectively fixed at 128. However the format +requires knowledge of the stride between columns, therefore the bytesperline +value has been repurposed to denote the number of 128 byte long lines between +the start of each column. + + Fully Planar YUV Formats ======================== diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/userspace-api/media/v4l/subdev-formats.rst linux/Documentation/userspace-api/media/v4l/subdev-formats.rst --- linux-6.1.66/Documentation/userspace-api/media/v4l/subdev-formats.rst 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/userspace-api/media/v4l/subdev-formats.rst 2023-12-13 11:50:48.022959914 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:627 @ - b\ :sub:`2` - b\ :sub:`1` - b\ :sub:`0` + * .. _MEDIA_BUS_FMT_RGB565_1X24_CPADHI: + + - MEDIA_BUS_FMT_RGB565_1X24_CPADHI + - 0x1022 + - + - + - + - + - + - + - + - + - + - 0 + - 0 + - 0 + - r\ :sub:`4` + - r\ :sub:`3` + - r\ :sub:`2` + - r\ :sub:`1` + - r\ :sub:`0` + - 0 + - 0 + - g\ :sub:`5` + - g\ :sub:`4` + - g\ :sub:`3` + - g\ :sub:`2` + - g\ :sub:`1` + - g\ :sub:`0` + - 0 + - 0 + - 0 + - b\ :sub:`4` + - b\ :sub:`3` + - b\ :sub:`2` + - b\ :sub:`1` + - b\ :sub:`0` * .. _MEDIA-BUS-FMT-BGR565-2X8-BE: - MEDIA_BUS_FMT_BGR565_2X8_BE @ linux/arch/arm/boot/dts/bcm2708.dtsi:952 @ - g\ :sub:`5` - g\ :sub:`4` - g\ :sub:`3` + * .. _MEDIA-BUS-FMT-BGR666-1X18: + + - MEDIA_BUS_FMT-BGR666_1X18 + - 0x1023 + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - b\ :sub:`5` + - b\ :sub:`4` + - b\ :sub:`3` + - b\ :sub:`2` + - b\ :sub:`1` + - b\ :sub:`0` + - g\ :sub:`5` + - g\ :sub:`4` + - g\ :sub:`3` + - g\ :sub:`2` + - g\ :sub:`1` + - g\ :sub:`0` + - r\ :sub:`5` + - r\ :sub:`4` + - r\ :sub:`3` + - r\ :sub:`2` + - r\ :sub:`1` + - r\ :sub:`0` * .. _MEDIA-BUS-FMT-RGB666-1X18: - MEDIA_BUS_FMT_RGB666_1X18 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1063 @ - g\ :sub:`2` - g\ :sub:`1` - g\ :sub:`0` + * .. _MEDIA-BUS-FMT-BGR666-1X24_CPADHI: + + - MEDIA_BUS_FMT_BGR666_1X24_CPADHI + - 0x1024 + - + - + - + - + - + - + - + - + - + - 0 + - 0 + - b\ :sub:`5` + - b\ :sub:`4` + - b\ :sub:`3` + - b\ :sub:`2` + - b\ :sub:`1` + - b\ :sub:`0` + - 0 + - 0 + - g\ :sub:`5` + - g\ :sub:`4` + - g\ :sub:`3` + - g\ :sub:`2` + - g\ :sub:`1` + - g\ :sub:`0` + - 0 + - 0 + - r\ :sub:`5` + - r\ :sub:`4` + - r\ :sub:`3` + - r\ :sub:`2` + - r\ :sub:`1` + - r\ :sub:`0` * .. _MEDIA-BUS-FMT-RGB666-1X24_CPADHI: - MEDIA_BUS_FMT_RGB666_1X24_CPADHI @ linux/arch/arm/boot/dts/bcm2708.dtsi:8200 @ both sides of the link and the bus format is a fixed metadata format that is not configurable from userspace. Width and height will be set to 0 for this format. + + +.. _v4l2-mbus-sensor-data: + +Sensor Ancillary Metadata Formats +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This section lists ancillary data generated by a camera sensor and +transmitted over a stream on the camera bus. + +The following table lists the existing sensor ancillary metadata formats: + + +.. _v4l2-mbus-pixelcode-sensor-metadata: + +.. tabularcolumns:: |p{8.0cm}|p{1.4cm}|p{7.7cm}| + +.. flat-table:: Sensor ancillary metadata formats + :header-rows: 1 + :stub-columns: 0 + + * - Identifier + - Code + - Comments + * .. _MEDIA_BUS_FMT_SENSOR_DATA: + + - MEDIA_BUS_FMT_SENSOR_DATA + - 0x7001 + - Sensor vendor specific ancillary metadata. Some vendors follow a generic + CSI-2/SMIA embedded data format as described in the `CSI-2 specification. + <https://mipi.org/specifications/csi-2>`_ + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/Documentation/userspace-api/media/v4l/yuv-formats.rst linux/Documentation/userspace-api/media/v4l/yuv-formats.rst --- linux-6.1.66/Documentation/userspace-api/media/v4l/yuv-formats.rst 2023-12-08 08:51:20.000000000 +0100 +++ linux/Documentation/userspace-api/media/v4l/yuv-formats.rst 2023-12-13 11:50:48.040959957 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:270 @ pixfmt-packed-yuv pixfmt-yuv-planar pixfmt-yuv-luma + pixfmt-y12p + pixfmt-y14p pixfmt-y8i pixfmt-y12i pixfmt-uv8 + pixfmt-yuyv + pixfmt-uyvy + pixfmt-yvyu + pixfmt-vyuy + pixfmt-y41p + pixfmt-yuv420 + pixfmt-yuv420m + pixfmt-yuv422m + pixfmt-yuv444m + pixfmt-yuv410 + pixfmt-yuv422p + pixfmt-yuv411p + pixfmt-nv12 + pixfmt-nv12m + pixfmt-nv12mt + pixfmt-nv12-col128 + pixfmt-nv16 + pixfmt-nv16m + pixfmt-nv24 pixfmt-m420 diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/base/regmap/regcache.c linux/drivers/base/regmap/regcache.c --- linux-6.1.66/drivers/base/regmap/regcache.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/base/regmap/regcache.c 2023-12-13 11:50:52.780971117 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:334 @ return 0; } -static int rbtree_all(const void *key, const struct rb_node *node) -{ - return 0; -} - /** * regcache_sync - Sync the register cache with the hardware. * @ linux/arch/arm/boot/dts/bcm2708.dtsi:351 @ unsigned int i; const char *name; bool bypass; - struct rb_node *node; if (WARN_ON(map->cache_type == REGCACHE_NONE)) return -EINVAL; @ linux/arch/arm/boot/dts/bcm2708.dtsi:395 @ map->async = false; map->cache_bypass = bypass; map->no_sync_defaults = false; - - /* - * If we did any paging with cache bypassed and a cached - * paging register then the register and cache state might - * have gone out of sync, force writes of all the paging - * registers. - */ - rb_for_each(node, 0, &map->range_tree, rbtree_all) { - struct regmap_range_node *this = - rb_entry(node, struct regmap_range_node, node); - - /* If there's nothing in the cache there's nothing to sync */ - ret = regcache_read(map, this->selector_reg, &i); - if (ret != 0) - continue; - - ret = _regmap_write(map, this->selector_reg, i); - if (ret != 0) { - dev_err(map->dev, "Failed to write %x = %x: %d\n", - this->selector_reg, i, ret); - break; - } - } - map->unlock(map->lock_arg); regmap_async_complete(map); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/bluetooth/btbcm.c linux/drivers/bluetooth/btbcm.c --- linux-6.1.66/drivers/bluetooth/btbcm.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/bluetooth/btbcm.c 2023-12-13 11:50:52.847971275 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:27 @ #define BDADDR_BCM20702A1 (&(bdaddr_t) {{0x00, 0x00, 0xa0, 0x02, 0x70, 0x20}}) #define BDADDR_BCM2076B1 (&(bdaddr_t) {{0x79, 0x56, 0x00, 0xa0, 0x76, 0x20}}) #define BDADDR_BCM43430A0 (&(bdaddr_t) {{0xac, 0x1f, 0x12, 0xa0, 0x43, 0x43}}) +#define BDADDR_BCM43430A1 (&(bdaddr_t) {{0xac, 0x1f, 0x12, 0xa1, 0x43, 0x43}}) +#define BDADDR_BCM43430B0 (&(bdaddr_t) {{0xac, 0x1f, 0x37, 0xb0, 0x43, 0x43}}) #define BDADDR_BCM4324B3 (&(bdaddr_t) {{0x00, 0x00, 0x00, 0xb3, 0x24, 0x43}}) #define BDADDR_BCM4330B1 (&(bdaddr_t) {{0x00, 0x00, 0x00, 0xb1, 0x30, 0x43}}) #define BDADDR_BCM4334B0 (&(bdaddr_t) {{0x00, 0x00, 0x00, 0xb0, 0x34, 0x43}}) +#define BDADDR_BCM4345C0 (&(bdaddr_t) {{0xac, 0x1f, 0x00, 0xc0, 0x45, 0x43}}) #define BDADDR_BCM4345C5 (&(bdaddr_t) {{0xac, 0x1f, 0x00, 0xc5, 0x45, 0x43}}) #define BDADDR_BCM43341B (&(bdaddr_t) {{0xac, 0x1f, 0x00, 0x1b, 0x34, 0x43}}) +#define BDADDR_BCM43438 (&(bdaddr_t) {{0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}}) #define BCM_FW_NAME_LEN 64 #define BCM_FW_NAME_COUNT_MAX 4 @ linux/arch/arm/boot/dts/bcm2708.dtsi:129 @ !bacmp(&bda->bdaddr, BDADDR_BCM4324B3) || !bacmp(&bda->bdaddr, BDADDR_BCM4330B1) || !bacmp(&bda->bdaddr, BDADDR_BCM4334B0) || + !bacmp(&bda->bdaddr, BDADDR_BCM4345C0) || !bacmp(&bda->bdaddr, BDADDR_BCM4345C5) || !bacmp(&bda->bdaddr, BDADDR_BCM43430A0) || + !bacmp(&bda->bdaddr, BDADDR_BCM43430A1) || + !bacmp(&bda->bdaddr, BDADDR_BCM43430B0) || + !bacmp(&bda->bdaddr, BDADDR_BCM43438) || !bacmp(&bda->bdaddr, BDADDR_BCM43341B)) { /* Try falling back to BDADDR EFI variable */ if (btbcm_set_bdaddr_from_efi(hdev) != 0) { diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/bluetooth/hci_h5.c linux/drivers/bluetooth/hci_h5.c --- linux-6.1.66/drivers/bluetooth/hci_h5.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/bluetooth/hci_h5.c 2023-12-13 11:50:52.857971298 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:360 @ h5_link_control(hu, conf_req, 3); } else if (memcmp(data, conf_req, 2) == 0) { h5_link_control(hu, conf_rsp, 2); - h5_link_control(hu, conf_req, 3); + if (h5->state != H5_ACTIVE) + h5_link_control(hu, conf_req, 3); } else if (memcmp(data, conf_rsp, 2) == 0) { if (H5_HDR_LEN(hdr) > 2) h5->tx_win = (data[2] & 0x07); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/char/broadcom/bcm2835_smi_dev.c linux/drivers/char/broadcom/bcm2835_smi_dev.c --- linux-6.1.66/drivers/char/broadcom/bcm2835_smi_dev.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/char/broadcom/bcm2835_smi_dev.c 2023-12-13 11:50:52.894971385 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/** + * Character device driver for Broadcom Secondary Memory Interface + * + * Written by Luke Wren <luke@raspberrypi.org> + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2, as published by the Free + * Software Foundation. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/mm.h> +#include <linux/pagemap.h> +#include <linux/fs.h> +#include <linux/cdev.h> +#include <linux/fs.h> + +#include <linux/broadcom/bcm2835_smi.h> + +#define DEVICE_NAME "bcm2835-smi-dev" +#define DRIVER_NAME "smi-dev-bcm2835" +#define DEVICE_MINOR 0 + +static struct cdev bcm2835_smi_cdev; +static dev_t bcm2835_smi_devid; +static struct class *bcm2835_smi_class; +static struct device *bcm2835_smi_dev; + +struct bcm2835_smi_dev_instance { + struct device *dev; +}; + +static struct bcm2835_smi_instance *smi_inst; +static struct bcm2835_smi_dev_instance *inst; + +static const char *const ioctl_names[] = { + "READ_SETTINGS", + "WRITE_SETTINGS", + "ADDRESS" +}; + +/**************************************************************************** +* +* SMI chardev file ops +* +***************************************************************************/ +static long +bcm2835_smi_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + + dev_info(inst->dev, "serving ioctl..."); + + switch (cmd) { + case BCM2835_SMI_IOC_GET_SETTINGS:{ + struct smi_settings *settings; + + dev_info(inst->dev, "Reading SMI settings to user."); + settings = bcm2835_smi_get_settings_from_regs(smi_inst); + if (copy_to_user((void *)arg, settings, + sizeof(struct smi_settings))) + dev_err(inst->dev, "settings copy failed."); + break; + } + case BCM2835_SMI_IOC_WRITE_SETTINGS:{ + struct smi_settings *settings; + + dev_info(inst->dev, "Setting user's SMI settings."); + settings = bcm2835_smi_get_settings_from_regs(smi_inst); + if (copy_from_user(settings, (void *)arg, + sizeof(struct smi_settings))) + dev_err(inst->dev, "settings copy failed."); + else + bcm2835_smi_set_regs_from_settings(smi_inst); + break; + } + case BCM2835_SMI_IOC_ADDRESS: + dev_info(inst->dev, "SMI address set: 0x%02x", (int)arg); + bcm2835_smi_set_address(smi_inst, arg); + break; + default: + dev_err(inst->dev, "invalid ioctl cmd: %d", cmd); + ret = -ENOTTY; + break; + } + + return ret; +} + +static int bcm2835_smi_open(struct inode *inode, struct file *file) +{ + int dev = iminor(inode); + + dev_dbg(inst->dev, "SMI device opened."); + + if (dev != DEVICE_MINOR) { + dev_err(inst->dev, + "bcm2835_smi_release: Unknown minor device: %d", + dev); + return -ENXIO; + } + + return 0; +} + +static int bcm2835_smi_release(struct inode *inode, struct file *file) +{ + int dev = iminor(inode); + + if (dev != DEVICE_MINOR) { + dev_err(inst->dev, + "bcm2835_smi_release: Unknown minor device %d", dev); + return -ENXIO; + } + + return 0; +} + +static ssize_t dma_bounce_user( + enum dma_transfer_direction dma_dir, + char __user *user_ptr, + size_t count, + struct bcm2835_smi_bounce_info *bounce) +{ + int chunk_size; + int chunk_no = 0; + int count_left = count; + + while (count_left) { + int rv; + void *buf; + + /* Wait for current chunk to complete: */ + if (down_timeout(&bounce->callback_sem, + msecs_to_jiffies(1000))) { + dev_err(inst->dev, "DMA bounce timed out"); + count -= (count_left); + break; + } + + if (bounce->callback_sem.count >= DMA_BOUNCE_BUFFER_COUNT - 1) + dev_err(inst->dev, "WARNING: Ring buffer overflow"); + chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ? + DMA_BOUNCE_BUFFER_SIZE : count_left; + buf = bounce->buffer[chunk_no % DMA_BOUNCE_BUFFER_COUNT]; + if (dma_dir == DMA_DEV_TO_MEM) + rv = copy_to_user(user_ptr, buf, chunk_size); + else + rv = copy_from_user(buf, user_ptr, chunk_size); + if (rv) + dev_err(inst->dev, "copy_*_user() failed!: %d", rv); + user_ptr += chunk_size; + count_left -= chunk_size; + chunk_no++; + } + return count; +} + +static ssize_t +bcm2835_read_file(struct file *f, char __user *user_ptr, + size_t count, loff_t *offs) +{ + int odd_bytes; + size_t count_check; + + dev_dbg(inst->dev, "User reading %zu bytes from SMI.", count); + /* We don't want to DMA a number of bytes % 4 != 0 (32 bit FIFO) */ + if (count > DMA_THRESHOLD_BYTES) + odd_bytes = count & 0x3; + else + odd_bytes = count; + count -= odd_bytes; + count_check = count; + if (count) { + struct bcm2835_smi_bounce_info *bounce; + + count = bcm2835_smi_user_dma(smi_inst, + DMA_DEV_TO_MEM, user_ptr, count, + &bounce); + if (count) + count = dma_bounce_user(DMA_DEV_TO_MEM, user_ptr, + count, bounce); + } + if (odd_bytes && (count == count_check)) { + /* Read from FIFO directly if not using DMA */ + uint8_t buf[DMA_THRESHOLD_BYTES]; + unsigned long bytes_not_transferred; + + bcm2835_smi_read_buf(smi_inst, buf, odd_bytes); + bytes_not_transferred = copy_to_user(user_ptr + count, buf, odd_bytes); + if (bytes_not_transferred) + dev_err(inst->dev, "copy_to_user() failed."); + count += odd_bytes - bytes_not_transferred; + } + return count; +} + +static ssize_t +bcm2835_write_file(struct file *f, const char __user *user_ptr, + size_t count, loff_t *offs) +{ + int odd_bytes; + size_t count_check; + + dev_dbg(inst->dev, "User writing %zu bytes to SMI.", count); + if (count > DMA_THRESHOLD_BYTES) + odd_bytes = count & 0x3; + else + odd_bytes = count; + count -= odd_bytes; + count_check = count; + if (count) { + struct bcm2835_smi_bounce_info *bounce; + + count = bcm2835_smi_user_dma(smi_inst, + DMA_MEM_TO_DEV, (char __user *)user_ptr, count, + &bounce); + if (count) + count = dma_bounce_user(DMA_MEM_TO_DEV, + (char __user *)user_ptr, + count, bounce); + } + if (odd_bytes && (count == count_check)) { + uint8_t buf[DMA_THRESHOLD_BYTES]; + unsigned long bytes_not_transferred; + + bytes_not_transferred = copy_from_user(buf, user_ptr + count, odd_bytes); + if (bytes_not_transferred) + dev_err(inst->dev, "copy_from_user() failed."); + else + bcm2835_smi_write_buf(smi_inst, buf, odd_bytes); + count += odd_bytes - bytes_not_transferred; + } + return count; +} + +static const struct file_operations +bcm2835_smi_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = bcm2835_smi_ioctl, + .open = bcm2835_smi_open, + .release = bcm2835_smi_release, + .read = bcm2835_read_file, + .write = bcm2835_write_file, +}; + + +/**************************************************************************** +* +* bcm2835_smi_probe - called when the driver is loaded. +* +***************************************************************************/ + +static int bcm2835_smi_dev_probe(struct platform_device *pdev) +{ + int err; + void *ptr_err; + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node, *smi_node; + + if (!node) { + dev_err(dev, "No device tree node supplied!"); + return -EINVAL; + } + + smi_node = of_parse_phandle(node, "smi_handle", 0); + + if (!smi_node) { + dev_err(dev, "No such property: smi_handle"); + return -ENXIO; + } + + smi_inst = bcm2835_smi_get(smi_node); + + if (!smi_inst) + return -EPROBE_DEFER; + + /* Allocate buffers and instance data */ + + inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL); + + if (!inst) + return -ENOMEM; + + inst->dev = dev; + + /* Create character device entries */ + + err = alloc_chrdev_region(&bcm2835_smi_devid, + DEVICE_MINOR, 1, DEVICE_NAME); + if (err != 0) { + dev_err(inst->dev, "unable to allocate device number"); + return -ENOMEM; + } + cdev_init(&bcm2835_smi_cdev, &bcm2835_smi_fops); + bcm2835_smi_cdev.owner = THIS_MODULE; + err = cdev_add(&bcm2835_smi_cdev, bcm2835_smi_devid, 1); + if (err != 0) { + dev_err(inst->dev, "unable to register device"); + err = -ENOMEM; + goto failed_cdev_add; + } + + /* Create sysfs entries */ + + bcm2835_smi_class = class_create(THIS_MODULE, DEVICE_NAME); + ptr_err = bcm2835_smi_class; + if (IS_ERR(ptr_err)) + goto failed_class_create; + + bcm2835_smi_dev = device_create(bcm2835_smi_class, NULL, + bcm2835_smi_devid, NULL, + "smi"); + ptr_err = bcm2835_smi_dev; + if (IS_ERR(ptr_err)) + goto failed_device_create; + + dev_info(inst->dev, "initialised"); + + return 0; + +failed_device_create: + class_destroy(bcm2835_smi_class); +failed_class_create: + cdev_del(&bcm2835_smi_cdev); + err = PTR_ERR(ptr_err); +failed_cdev_add: + unregister_chrdev_region(bcm2835_smi_devid, 1); + dev_err(dev, "could not load bcm2835_smi_dev"); + return err; +} + +/**************************************************************************** +* +* bcm2835_smi_remove - called when the driver is unloaded. +* +***************************************************************************/ + +static int bcm2835_smi_dev_remove(struct platform_device *pdev) +{ + device_destroy(bcm2835_smi_class, bcm2835_smi_devid); + class_destroy(bcm2835_smi_class); + cdev_del(&bcm2835_smi_cdev); + unregister_chrdev_region(bcm2835_smi_devid, 1); + + dev_info(inst->dev, "SMI character dev removed - OK"); + return 0; +} + +/**************************************************************************** +* +* Register the driver with device tree +* +***************************************************************************/ + +static const struct of_device_id bcm2835_smi_dev_of_match[] = { + {.compatible = "brcm,bcm2835-smi-dev",}, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, bcm2835_smi_dev_of_match); + +static struct platform_driver bcm2835_smi_dev_driver = { + .probe = bcm2835_smi_dev_probe, + .remove = bcm2835_smi_dev_remove, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = bcm2835_smi_dev_of_match, + }, +}; + +module_platform_driver(bcm2835_smi_dev_driver); + +MODULE_ALIAS("platform:smi-dev-bcm2835"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION( + "Character device driver for BCM2835's secondary memory interface"); +MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/char/broadcom/Kconfig linux/drivers/char/broadcom/Kconfig --- linux-6.1.66/drivers/char/broadcom/Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/char/broadcom/Kconfig 2023-12-13 11:50:52.893971383 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# +# Broadcom char driver config +# + +menuconfig BRCM_CHAR_DRIVERS + bool "Broadcom Char Drivers" + help + Broadcom's char drivers + +if BRCM_CHAR_DRIVERS + +config BCM2708_VCMEM + bool "Videocore Memory" + default y + help + Helper for videocore memory access and total size allocation. + +config BCM_VCIO + tristate "Mailbox userspace access" + depends on BCM2835_MBOX + help + Gives access to the mailbox property channel from userspace. + +endif + +config BCM2835_SMI_DEV + tristate "Character device driver for BCM2835 Secondary Memory Interface" + depends on BCM2835_SMI + default m + help + This driver provides a character device interface (ioctl + read/write) to + Broadcom's Secondary Memory interface. The low-level functionality is provided + by the SMI driver itself. + +config RPIVID_MEM + tristate "Character device driver for the Raspberry Pi RPIVid video decoder hardware" + default n + help + This driver provides a character device interface for memory-map operations + so userspace tools can access the control and status registers of the + Raspberry Pi RPiVid video decoder hardware. diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/char/broadcom/Makefile linux/drivers/char/broadcom/Makefile --- linux-6.1.66/drivers/char/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/char/broadcom/Makefile 2023-12-13 11:50:52.894971385 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o +obj-$(CONFIG_BCM_VCIO) += vcio.o +obj-$(CONFIG_BCM2835_SMI_DEV) += bcm2835_smi_dev.o +obj-$(CONFIG_RPIVID_MEM) += rpivid-mem.o diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/char/broadcom/rpivid-mem.c linux/drivers/char/broadcom/rpivid-mem.c --- linux-6.1.66/drivers/char/broadcom/rpivid-mem.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/char/broadcom/rpivid-mem.c 2023-12-13 11:50:52.894971385 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/** + * rpivid-mem.c - character device access to the RPiVid decoder registers + * + * Based on bcm2835-gpiomem.c. Provides IO memory access to the decoder + * register blocks such that ffmpeg plugins can access the hardware. + * + * Jonathan Bell <jonathan@raspberrypi.org> + * Copyright (c) 2019, Raspberry Pi (Trading) Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2, as published by the Free + * Software Foundation. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/mm.h> +#include <linux/slab.h> +#include <linux/cdev.h> +#include <linux/pagemap.h> +#include <linux/io.h> + +#define DRIVER_NAME "rpivid-mem" +#define DEVICE_MINOR 0 + +struct rpivid_mem_priv { + dev_t devid; + struct class *class; + struct cdev rpivid_mem_cdev; + unsigned long regs_phys; + unsigned long mem_window_len; + struct device *dev; + const char *name; +}; + +static int rpivid_mem_open(struct inode *inode, struct file *file) +{ + int dev = iminor(inode); + int ret = 0; + struct rpivid_mem_priv *priv; + + if (dev != DEVICE_MINOR && dev != DEVICE_MINOR + 1) + ret = -ENXIO; + + priv = container_of(inode->i_cdev, struct rpivid_mem_priv, + rpivid_mem_cdev); + if (!priv) + return -EINVAL; + file->private_data = priv; + return ret; +} + +static int rpivid_mem_release(struct inode *inode, struct file *file) +{ + int dev = iminor(inode); + int ret = 0; + + if (dev != DEVICE_MINOR && dev != DEVICE_MINOR + 1) + ret = -ENXIO; + + return ret; +} + +static const struct vm_operations_struct rpivid_mem_vm_ops = { +#ifdef CONFIG_HAVE_IOREMAP_PROT + .access = generic_access_phys +#endif +}; + +static int rpivid_mem_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct rpivid_mem_priv *priv; + unsigned long pages; + unsigned long len; + + priv = file->private_data; + pages = priv->regs_phys >> PAGE_SHIFT; + /* + * The address decode is far larger than the actual number of registers. + * Just map the whole lot in. + */ + len = min(vma->vm_end - vma->vm_start, priv->mem_window_len); + vma->vm_page_prot = phys_mem_access_prot(file, pages, len, + vma->vm_page_prot); + vma->vm_ops = &rpivid_mem_vm_ops; + if (remap_pfn_range(vma, vma->vm_start, + pages, len, + vma->vm_page_prot)) { + return -EAGAIN; + } + return 0; +} + +static const struct file_operations +rpivid_mem_fops = { + .owner = THIS_MODULE, + .open = rpivid_mem_open, + .release = rpivid_mem_release, + .mmap = rpivid_mem_mmap, +}; + +static const struct of_device_id rpivid_mem_of_match[]; +static int rpivid_mem_probe(struct platform_device *pdev) +{ + int err; + const struct of_device_id *id; + struct device *dev = &pdev->dev; + struct resource *ioresource; + struct rpivid_mem_priv *priv; + + /* Allocate buffers and instance data */ + + priv = kzalloc(sizeof(struct rpivid_mem_priv), GFP_KERNEL); + + if (!priv) { + err = -ENOMEM; + goto failed_inst_alloc; + } + platform_set_drvdata(pdev, priv); + + priv->dev = dev; + id = of_match_device(rpivid_mem_of_match, dev); + if (!id) + return -EINVAL; + priv->name = id->data; + + ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (ioresource) { + priv->regs_phys = ioresource->start; + priv->mem_window_len = (ioresource->end + 1) - ioresource->start; + } else { + dev_err(priv->dev, "failed to get IO resource"); + err = -ENOENT; + goto failed_get_resource; + } + + /* Create character device entries */ + + err = alloc_chrdev_region(&priv->devid, + DEVICE_MINOR, 2, priv->name); + if (err != 0) { + dev_err(priv->dev, "unable to allocate device number"); + goto failed_alloc_chrdev; + } + cdev_init(&priv->rpivid_mem_cdev, &rpivid_mem_fops); + priv->rpivid_mem_cdev.owner = THIS_MODULE; + err = cdev_add(&priv->rpivid_mem_cdev, priv->devid, 2); + if (err != 0) { + dev_err(priv->dev, "unable to register device"); + goto failed_cdev_add; + } + + /* Create sysfs entries */ + + priv->class = class_create(THIS_MODULE, priv->name); + if (IS_ERR(priv->class)) { + err = PTR_ERR(priv->class); + goto failed_class_create; + } + + dev = device_create(priv->class, NULL, priv->devid, NULL, priv->name); + if (IS_ERR(dev)) { + err = PTR_ERR(dev); + goto failed_device_create; + } + + dev_info(priv->dev, "%s initialised: Registers at 0x%08lx length 0x%08lx", + priv->name, priv->regs_phys, priv->mem_window_len); + + return 0; + +failed_device_create: + class_destroy(priv->class); +failed_class_create: + cdev_del(&priv->rpivid_mem_cdev); +failed_cdev_add: + unregister_chrdev_region(priv->devid, 1); +failed_alloc_chrdev: +failed_get_resource: + kfree(priv); +failed_inst_alloc: + dev_err(&pdev->dev, "could not load rpivid_mem"); + return err; +} + +static int rpivid_mem_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rpivid_mem_priv *priv = platform_get_drvdata(pdev); + + device_destroy(priv->class, priv->devid); + class_destroy(priv->class); + cdev_del(&priv->rpivid_mem_cdev); + unregister_chrdev_region(priv->devid, 1); + kfree(priv); + + dev_info(dev, "%s driver removed - OK", priv->name); + return 0; +} + +static const struct of_device_id rpivid_mem_of_match[] = { + { + .compatible = "raspberrypi,rpivid-hevc-decoder", + .data = "rpivid-hevcmem", + }, + { + .compatible = "raspberrypi,rpivid-h264-decoder", + .data = "rpivid-h264mem", + }, + { + .compatible = "raspberrypi,rpivid-vp9-decoder", + .data = "rpivid-vp9mem", + }, + /* The "intc" is included as this block of hardware contains the + * "frame done" status flags. + */ + { + .compatible = "raspberrypi,rpivid-local-intc", + .data = "rpivid-intcmem", + }, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, rpivid_mem_of_match); + +static struct platform_driver rpivid_mem_driver = { + .probe = rpivid_mem_probe, + .remove = rpivid_mem_remove, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = rpivid_mem_of_match, + }, +}; + +module_platform_driver(rpivid_mem_driver); + +MODULE_ALIAS("platform:rpivid-mem"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Driver for accessing RPiVid decoder registers from userspace"); +MODULE_AUTHOR("Jonathan Bell <jonathan@raspberrypi.org>"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/char/broadcom/vcio.c linux/drivers/char/broadcom/vcio.c --- linux-6.1.66/drivers/char/broadcom/vcio.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/char/broadcom/vcio.c 2023-12-13 11:50:52.895971388 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Copyright (C) 2010 Broadcom + * Copyright (C) 2015 Noralf Trønnes + * Copyright (C) 2021 Raspberry Pi (Trading) Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/cdev.h> +#include <linux/device.h> +#include <linux/fs.h> +#include <linux/init.h> +#include <linux/ioctl.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/uaccess.h> +#include <linux/compat.h> +#include <linux/miscdevice.h> +#include <soc/bcm2835/raspberrypi-firmware.h> + +#define MODULE_NAME "vcio" +#define VCIO_IOC_MAGIC 100 +#define IOCTL_MBOX_PROPERTY _IOWR(VCIO_IOC_MAGIC, 0, char *) +#ifdef CONFIG_COMPAT +#define IOCTL_MBOX_PROPERTY32 _IOWR(VCIO_IOC_MAGIC, 0, compat_uptr_t) +#endif + +struct vcio_data { + struct rpi_firmware *fw; + struct miscdevice misc_dev; +}; + +static int vcio_user_property_list(struct vcio_data *vcio, void *user) +{ + u32 *buf, size; + int ret; + + /* The first 32-bit is the size of the buffer */ + if (copy_from_user(&size, user, sizeof(size))) + return -EFAULT; + + buf = kmalloc(size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + if (copy_from_user(buf, user, size)) { + kfree(buf); + return -EFAULT; + } + + /* Strip off protocol encapsulation */ + ret = rpi_firmware_property_list(vcio->fw, &buf[2], size - 12); + if (ret) { + kfree(buf); + return ret; + } + + buf[1] = RPI_FIRMWARE_STATUS_SUCCESS; + if (copy_to_user(user, buf, size)) + ret = -EFAULT; + + kfree(buf); + + return ret; +} + +static int vcio_device_open(struct inode *inode, struct file *file) +{ + try_module_get(THIS_MODULE); + + return 0; +} + +static int vcio_device_release(struct inode *inode, struct file *file) +{ + module_put(THIS_MODULE); + + return 0; +} + +static long vcio_device_ioctl(struct file *file, unsigned int ioctl_num, + unsigned long ioctl_param) +{ + struct vcio_data *vcio = container_of(file->private_data, + struct vcio_data, misc_dev); + + switch (ioctl_num) { + case IOCTL_MBOX_PROPERTY: + return vcio_user_property_list(vcio, (void *)ioctl_param); + default: + pr_err("unknown ioctl: %x\n", ioctl_num); + return -EINVAL; + } +} + +#ifdef CONFIG_COMPAT +static long vcio_device_compat_ioctl(struct file *file, unsigned int ioctl_num, + unsigned long ioctl_param) +{ + struct vcio_data *vcio = container_of(file->private_data, + struct vcio_data, misc_dev); + + switch (ioctl_num) { + case IOCTL_MBOX_PROPERTY32: + return vcio_user_property_list(vcio, compat_ptr(ioctl_param)); + default: + pr_err("unknown ioctl: %x\n", ioctl_num); + return -EINVAL; + } +} +#endif + +const struct file_operations vcio_fops = { + .unlocked_ioctl = vcio_device_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = vcio_device_compat_ioctl, +#endif + .open = vcio_device_open, + .release = vcio_device_release, +}; + +static int vcio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *fw_node; + struct rpi_firmware *fw; + struct vcio_data *vcio; + + fw_node = of_get_parent(np); + if (!fw_node) { + dev_err(dev, "Missing firmware node\n"); + return -ENOENT; + } + + fw = rpi_firmware_get(fw_node); + of_node_put(fw_node); + if (!fw) + return -EPROBE_DEFER; + + vcio = devm_kzalloc(dev, sizeof(struct vcio_data), GFP_KERNEL); + if (!vcio) + return -ENOMEM; + + vcio->fw = fw; + vcio->misc_dev.fops = &vcio_fops; + vcio->misc_dev.minor = MISC_DYNAMIC_MINOR; + vcio->misc_dev.name = "vcio"; + vcio->misc_dev.parent = dev; + + return misc_register(&vcio->misc_dev); +} + +static int vcio_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + + misc_deregister(dev_get_drvdata(dev)); + return 0; +} + +static const struct of_device_id vcio_ids[] = { + { .compatible = "raspberrypi,vcio" }, + { } +}; +MODULE_DEVICE_TABLE(of, vcio_ids); + +static struct platform_driver vcio_driver = { + .driver = { + .name = MODULE_NAME, + .of_match_table = of_match_ptr(vcio_ids), + }, + .probe = vcio_probe, + .remove = vcio_remove, +}; + +module_platform_driver(vcio_driver); + +MODULE_AUTHOR("Gray Girling"); +MODULE_AUTHOR("Noralf Trønnes"); +MODULE_DESCRIPTION("Mailbox userspace access"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:rpi-vcio"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/char/broadcom/vc_mem.c linux/drivers/char/broadcom/vc_mem.c --- linux-6.1.66/drivers/char/broadcom/vc_mem.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/char/broadcom/vc_mem.c 2023-12-13 11:50:52.894971385 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Copyright 2010 - 2011 Broadcom Corporation. All rights reserved. + * + * Unless you and Broadcom execute a separate written software license + * agreement governing use of this software, this software is licensed to you + * under the terms of the GNU General Public License version 2, available at + * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). + * + * Notwithstanding the above, under no circumstances may you combine this + * software in any way with any other Broadcom software provided under a + * license other than the GPL, without Broadcom's express prior written + * consent. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/fs.h> +#include <linux/device.h> +#include <linux/cdev.h> +#include <linux/mm.h> +#include <linux/slab.h> +#include <linux/debugfs.h> +#include <linux/uaccess.h> +#include <linux/dma-mapping.h> +#include <linux/broadcom/vc_mem.h> +#include <linux/compat.h> +#include <linux/platform_data/dma-bcm2708.h> +#include <soc/bcm2835/raspberrypi-firmware.h> + +#define DRIVER_NAME "vc-mem" + +/* N.B. These use a different magic value for compatibility with bmc7208_fb */ +#define VC_MEM_IOC_DMACOPY _IOW('z', 0x22, struct vc_mem_dmacopy) +#define VC_MEM_IOC_DMACOPY32 _IOW('z', 0x22, struct vc_mem_dmacopy32) + +/* address with no aliases */ +#define INTALIAS_NORMAL(x) ((x) & ~0xc0000000) +/* cache coherent but non-allocating in L1 and L2 */ +#define INTALIAS_L1L2_NONALLOCATING(x) (((x) & ~0xc0000000) | 0x80000000) + +/* Device (/dev) related variables */ +static dev_t vc_mem_devnum; +static struct class *vc_mem_class; +static struct cdev vc_mem_cdev; +static int vc_mem_inited; + +#ifdef CONFIG_DEBUG_FS +static struct dentry *vc_mem_debugfs_entry; +#endif + +struct vc_mem_dmacopy { + void *dst; + __u32 src; + __u32 length; +}; + +#ifdef CONFIG_COMPAT +struct vc_mem_dmacopy32 { + compat_uptr_t dst; + __u32 src; + __u32 length; +}; +#endif + +/* + * Videocore memory addresses and size + * + * Drivers that wish to know the videocore memory addresses and sizes should + * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in + * headers. This allows the other drivers to not be tied down to a a certain + * address/size at compile time. + * + * In the future, the goal is to have the videocore memory virtual address and + * size be calculated at boot time rather than at compile time. The decision of + * where the videocore memory resides and its size would be in the hands of the + * bootloader (and/or kernel). When that happens, the values of these variables + * would be calculated and assigned in the init function. + */ +/* In the 2835 VC in mapped above ARM, but ARM has full access to VC space */ +unsigned long mm_vc_mem_phys_addr; +EXPORT_SYMBOL(mm_vc_mem_phys_addr); +unsigned int mm_vc_mem_size; +EXPORT_SYMBOL(mm_vc_mem_size); +unsigned int mm_vc_mem_base; +EXPORT_SYMBOL(mm_vc_mem_base); + +static uint phys_addr; +static uint mem_size; +static uint mem_base; + +struct vc_mem_dma { + struct device *dev; + int dma_chan; + int dma_irq; + void __iomem *dma_chan_base; + wait_queue_head_t dma_waitq; + void *cb_base; /* DMA control blocks */ + dma_addr_t cb_handle; +}; + +struct { u32 base, length; } gpu_mem; +static struct mutex dma_mutex; +static struct vc_mem_dma vc_mem_dma; + +static int +vc_mem_open(struct inode *inode, struct file *file) +{ + (void)inode; + + pr_debug("%s: called file = 0x%p\n", __func__, file); + + return 0; +} + +static int +vc_mem_release(struct inode *inode, struct file *file) +{ + (void)inode; + + pr_debug("%s: called file = 0x%p\n", __func__, file); + + return 0; +} + +static void +vc_mem_get_size(void) +{ +} + +static void +vc_mem_get_base(void) +{ +} + +int +vc_mem_get_current_size(void) +{ + return mm_vc_mem_size; +} +EXPORT_SYMBOL_GPL(vc_mem_get_current_size); + +static int +vc_mem_dma_init(void) +{ + struct vc_mem_dma *vcdma = &vc_mem_dma; + struct platform_device *pdev; + struct device_node *fwnode; + struct rpi_firmware *fw; + struct device *dev; + u32 revision; + int rc; + + if (vcdma->dev) + return 0; + + fwnode = of_find_node_by_path("/system"); + rc = of_property_read_u32(fwnode, "linux,revision", &revision); + revision = (revision >> 12) & 0xf; + if (revision != 1 && revision != 2) { + /* Only BCM2709 and BCM2710 may have logs where the ARMs + * can't see them. + */ + return -ENXIO; + } + + fwnode = rpi_firmware_find_node(); + if (!fwnode) + return -ENXIO; + + pdev = of_find_device_by_node(fwnode); + dev = &pdev->dev; + + rc = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); + if (rc) + return rc; + + fw = rpi_firmware_get(fwnode); + if (!fw) + return -ENXIO; + rc = rpi_firmware_property(fw, RPI_FIRMWARE_GET_VC_MEMORY, + &gpu_mem, sizeof(gpu_mem)); + if (rc) + return rc; + + gpu_mem.base = INTALIAS_NORMAL(gpu_mem.base); + + if (!gpu_mem.base || !gpu_mem.length) { + dev_err(dev, "%s: unable to determine gpu memory (%x,%x)\n", + __func__, gpu_mem.base, gpu_mem.length); + return -EFAULT; + } + + vcdma->cb_base = dma_alloc_wc(dev, SZ_4K, &vcdma->cb_handle, GFP_KERNEL); + if (!vcdma->cb_base) { + dev_err(dev, "failed to allocate DMA CBs\n"); + return -ENOMEM; + } + + rc = bcm_dma_chan_alloc(BCM_DMA_FEATURE_BULK, + &vcdma->dma_chan_base, + &vcdma->dma_irq); + if (rc < 0) { + dev_err(dev, "failed to allocate a DMA channel\n"); + goto free_cb; + } + + vcdma->dma_chan = rc; + + init_waitqueue_head(&vcdma->dma_waitq); + + vcdma->dev = dev; + + return 0; + +free_cb: + dma_free_wc(dev, SZ_4K, vcdma->cb_base, vcdma->cb_handle); + + return rc; +} + +static void +vc_mem_dma_uninit(void) +{ + struct vc_mem_dma *vcdma = &vc_mem_dma; + + if (vcdma->dev) { + bcm_dma_chan_free(vcdma->dma_chan); + dma_free_wc(vcdma->dev, SZ_4K, vcdma->cb_base, vcdma->cb_handle); + vcdma->dev = NULL; + } +} + +static int dma_memcpy(struct vc_mem_dma *vcdma, dma_addr_t dst, dma_addr_t src, + int size) +{ + struct bcm2708_dma_cb *cb = vcdma->cb_base; + int burst_size = (vcdma->dma_chan == 0) ? 8 : 2; + + cb->info = BCM2708_DMA_BURST(burst_size) | BCM2708_DMA_S_WIDTH | + BCM2708_DMA_S_INC | BCM2708_DMA_D_WIDTH | + BCM2708_DMA_D_INC; + cb->dst = dst; + cb->src = src; + cb->length = size; + cb->stride = 0; + cb->pad[0] = 0; + cb->pad[1] = 0; + cb->next = 0; + + bcm_dma_start(vcdma->dma_chan_base, vcdma->cb_handle); + bcm_dma_wait_idle(vcdma->dma_chan_base); + + return 0; +} + +static long vc_mem_copy(struct vc_mem_dmacopy *ioparam) +{ + struct vc_mem_dma *vcdma = &vc_mem_dma; + size_t size = PAGE_SIZE; + const u32 dma_xfer_chunk = 256; + u32 *buf = NULL; + dma_addr_t bus_addr; + long rc = 0; + size_t offset; + + /* restrict this to root user */ + if (!uid_eq(current_euid(), GLOBAL_ROOT_UID)) + return -EFAULT; + + if (mutex_lock_interruptible(&dma_mutex)) + return -EINTR; + + rc = vc_mem_dma_init(); + if (rc) + goto out; + + vcdma = &vc_mem_dma; + + if (INTALIAS_NORMAL(ioparam->src) < gpu_mem.base || + INTALIAS_NORMAL(ioparam->src) >= gpu_mem.base + gpu_mem.length) { + pr_err("%s: invalid memory access %x (%x-%x)", __func__, + INTALIAS_NORMAL(ioparam->src), gpu_mem.base, + gpu_mem.base + gpu_mem.length); + rc = -EFAULT; + goto out; + } + + buf = dma_alloc_coherent(vcdma->dev, PAGE_ALIGN(size), &bus_addr, + GFP_ATOMIC); + if (!buf) { + rc = -ENOMEM; + goto out; + } + + for (offset = 0; offset < ioparam->length; offset += size) { + size_t remaining = ioparam->length - offset; + size_t s = min(size, remaining); + u8 *p = (u8 *)((uintptr_t)ioparam->src + offset); + u8 *q = (u8 *)ioparam->dst + offset; + + rc = dma_memcpy(vcdma, bus_addr, + INTALIAS_L1L2_NONALLOCATING((u32)(uintptr_t)p), + (s + dma_xfer_chunk - 1) & ~(dma_xfer_chunk - 1)); + if (rc) { + dev_err(vcdma->dev, "dma_memcpy failed\n"); + break; + } + if (copy_to_user(q, buf, s) != 0) { + pr_err("%s: copy_to_user failed\n", __func__); + rc = -EFAULT; + break; + } + } + +out: + if (buf) + dma_free_coherent(vcdma->dev, PAGE_ALIGN(size), buf, + bus_addr); + + mutex_unlock(&dma_mutex); + + return rc; +} + +static long +vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + int rc = 0; + + (void) cmd; + (void) arg; + + pr_debug("%s: called file = 0x%p, cmd %08x\n", __func__, file, cmd); + + switch (cmd) { + case VC_MEM_IOC_MEM_PHYS_ADDR: + { + pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n", + __func__, (void *)mm_vc_mem_phys_addr); + + if (copy_to_user((void *)arg, &mm_vc_mem_phys_addr, + sizeof(mm_vc_mem_phys_addr))) { + rc = -EFAULT; + } + break; + } + case VC_MEM_IOC_MEM_SIZE: + { + /* Get the videocore memory size first */ + vc_mem_get_size(); + + pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%x\n", __func__, + mm_vc_mem_size); + + if (copy_to_user((void *)arg, &mm_vc_mem_size, + sizeof(mm_vc_mem_size))) { + rc = -EFAULT; + } + break; + } + case VC_MEM_IOC_MEM_BASE: + { + /* Get the videocore memory base */ + vc_mem_get_base(); + + pr_debug("%s: VC_MEM_IOC_MEM_BASE=%x\n", __func__, + mm_vc_mem_base); + + if (copy_to_user((void *)arg, &mm_vc_mem_base, + sizeof(mm_vc_mem_base))) { + rc = -EFAULT; + } + break; + } + case VC_MEM_IOC_MEM_LOAD: + { + /* Get the videocore memory base */ + vc_mem_get_base(); + + pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%x\n", __func__, + mm_vc_mem_base); + + if (copy_to_user((void *)arg, &mm_vc_mem_base, + sizeof(mm_vc_mem_base))) { + rc = -EFAULT; + } + break; + } + case VC_MEM_IOC_DMACOPY: + { + struct vc_mem_dmacopy ioparam; + /* Get the parameter data. + */ + if (copy_from_user + (&ioparam, (void *)arg, sizeof(ioparam))) { + pr_err("%s: copy_from_user failed\n", __func__); + rc = -EFAULT; + break; + } + + rc = vc_mem_copy(&ioparam); + break; + } + default: + { + return -ENOTTY; + } + } + pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc); + + return rc; +} + +#ifdef CONFIG_COMPAT +static long +vc_mem_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + int rc = 0; + + switch (cmd) { + case VC_MEM_IOC_MEM_PHYS_ADDR32: + pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR32=0x%p\n", + __func__, (void *)mm_vc_mem_phys_addr); + + /* This isn't correct, but will cover us for now as + * VideoCore is 32bit only. + */ + if (copy_to_user((void *)arg, &mm_vc_mem_phys_addr, + sizeof(compat_ulong_t))) + rc = -EFAULT; + + break; + + case VC_MEM_IOC_DMACOPY32: + { + struct vc_mem_dmacopy32 param32; + struct vc_mem_dmacopy param; + /* Get the parameter data. + */ + if (copy_from_user(¶m32, (void *)arg, sizeof(param32))) { + pr_err("%s: copy_from_user failed\n", __func__); + rc = -EFAULT; + break; + } + param.dst = compat_ptr(param32.dst); + param.src = param32.src; + param.length = param32.length; + rc = vc_mem_copy(¶m); + break; + } + + default: + rc = vc_mem_ioctl(file, cmd, arg); + break; + } + + return rc; +} +#endif + +static int +vc_mem_mmap(struct file *filp, struct vm_area_struct *vma) +{ + int rc = 0; + unsigned long length = vma->vm_end - vma->vm_start; + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; + + pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n", + __func__, (long)vma->vm_start, (long)vma->vm_end, + (long)vma->vm_pgoff); + + if (offset + length > mm_vc_mem_size) { + pr_err("%s: length %ld is too big\n", __func__, length); + return -EINVAL; + } + /* Do not cache the memory map */ + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + rc = remap_pfn_range(vma, vma->vm_start, + (mm_vc_mem_phys_addr >> PAGE_SHIFT) + + vma->vm_pgoff, length, vma->vm_page_prot); + if (rc) + pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc); + + return rc; +} + +/* File Operations for the driver. */ +static const struct file_operations vc_mem_fops = { + .owner = THIS_MODULE, + .open = vc_mem_open, + .release = vc_mem_release, + .unlocked_ioctl = vc_mem_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = vc_mem_compat_ioctl, +#endif + .mmap = vc_mem_mmap, +}; + +#ifdef CONFIG_DEBUG_FS +static void vc_mem_debugfs_deinit(void) +{ + debugfs_remove_recursive(vc_mem_debugfs_entry); + vc_mem_debugfs_entry = NULL; +} + + +static int vc_mem_debugfs_init( + struct device *dev) +{ + vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL); + if (!vc_mem_debugfs_entry) { + dev_warn(dev, "could not create debugfs entry\n"); + return -EFAULT; + } + + debugfs_create_x32("vc_mem_phys_addr", + 0444, + vc_mem_debugfs_entry, + (u32 *)&mm_vc_mem_phys_addr); + debugfs_create_x32("vc_mem_size", + 0444, + vc_mem_debugfs_entry, + (u32 *)&mm_vc_mem_size); + debugfs_create_x32("vc_mem_base", + 0444, + vc_mem_debugfs_entry, + (u32 *)&mm_vc_mem_base); + + return 0; +} + +#endif /* CONFIG_DEBUG_FS */ + +/* Module load/unload functions */ + +static int __init +vc_mem_init(void) +{ + int rc = -EFAULT; + struct device *dev; + + pr_debug("%s: called\n", __func__); + + mm_vc_mem_phys_addr = phys_addr; + mm_vc_mem_size = mem_size; + mm_vc_mem_base = mem_base; + + vc_mem_get_size(); + + pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n", + mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, + mm_vc_mem_size / (1024 * 1024)); + + rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME); + if (rc < 0) { + pr_err("%s: alloc_chrdev_region failed (rc=%d)\n", + __func__, rc); + goto out_err; + } + + cdev_init(&vc_mem_cdev, &vc_mem_fops); + rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1); + if (rc) { + pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc); + goto out_unregister; + } + + vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME); + if (IS_ERR(vc_mem_class)) { + rc = PTR_ERR(vc_mem_class); + pr_err("%s: class_create failed (rc=%d)\n", __func__, rc); + goto out_cdev_del; + } + + dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL, + DRIVER_NAME); + if (IS_ERR(dev)) { + rc = PTR_ERR(dev); + pr_err("%s: device_create failed (rc=%d)\n", __func__, rc); + goto out_class_destroy; + } + +#ifdef CONFIG_DEBUG_FS + /* don't fail if the debug entries cannot be created */ + vc_mem_debugfs_init(dev); +#endif + + mutex_init(&dma_mutex); + vc_mem_inited = 1; + return 0; + +out_class_destroy: + class_destroy(vc_mem_class); + vc_mem_class = NULL; + +out_cdev_del: + cdev_del(&vc_mem_cdev); + +out_unregister: + unregister_chrdev_region(vc_mem_devnum, 1); + +out_err: + return -1; +} + +static void __exit +vc_mem_exit(void) +{ + pr_debug("%s: called\n", __func__); + + vc_mem_dma_uninit(); + if (vc_mem_inited) { +#ifdef CONFIG_DEBUG_FS + vc_mem_debugfs_deinit(); +#endif + device_destroy(vc_mem_class, vc_mem_devnum); + class_destroy(vc_mem_class); + cdev_del(&vc_mem_cdev); + unregister_chrdev_region(vc_mem_devnum, 1); + vc_mem_inited = 0; + } +} + +module_init(vc_mem_init); +module_exit(vc_mem_exit); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Broadcom Corporation"); + +module_param(phys_addr, uint, 0644); +module_param(mem_size, uint, 0644); +module_param(mem_base, uint, 0644); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/char/hw_random/bcm2835-rng.c linux/drivers/char/hw_random/bcm2835-rng.c --- linux-6.1.66/drivers/char/hw_random/bcm2835-rng.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/char/hw_random/bcm2835-rng.c 2023-12-13 11:50:52.898971395 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:17 @ #include <linux/printk.h> #include <linux/clk.h> #include <linux/reset.h> +#include <linux/delay.h> #define RNG_CTRL 0x0 #define RNG_STATUS 0x4 @ linux/arch/arm/boot/dts/bcm2708.dtsi:32 @ #define RNG_INT_OFF 0x1 +#define RNG_FIFO_WORDS 4 +#define RNG_US_PER_WORD 34 /* Tuned for throughput */ + struct bcm2835_rng_priv { struct hwrng rng; void __iomem *base; @ linux/arch/arm/boot/dts/bcm2708.dtsi:71 @ static int bcm2835_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) { + u32 retries = 1000000/(RNG_FIFO_WORDS * RNG_US_PER_WORD); struct bcm2835_rng_priv *priv = to_rng_priv(rng); u32 max_words = max / sizeof(u32); u32 num_words, count; - while ((rng_readl(priv, RNG_STATUS) >> 24) == 0) { - if (!wait) + num_words = rng_readl(priv, RNG_STATUS) >> 24; + + while (!num_words) { + if (!wait || !retries) return 0; - hwrng_yield(rng); + retries--; + usleep_range((u32)RNG_US_PER_WORD, + (u32)RNG_US_PER_WORD * RNG_FIFO_WORDS); + num_words = rng_readl(priv, RNG_STATUS) >> 24; } - num_words = rng_readl(priv, RNG_STATUS) >> 24; - if (num_words > max_words) - num_words = max_words; + num_words = min(num_words, max_words); for (count = 0; count < num_words; count++) ((u32 *)buf)[count] = rng_readl(priv, RNG_DATA); @ linux/arch/arm/boot/dts/bcm2708.dtsi:117 @ } /* set warm-up count & enable */ - rng_writel(priv, RNG_WARMUP_COUNT, RNG_STATUS); - rng_writel(priv, RNG_RBGEN, RNG_CTRL); + if (!(rng_readl(priv, RNG_CTRL) & RNG_RBGEN)) { + rng_writel(priv, RNG_WARMUP_COUNT, RNG_STATUS); + rng_writel(priv, RNG_RBGEN, RNG_CTRL); + } return ret; } diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/char/hw_random/iproc-rng200.c linux/drivers/char/hw_random/iproc-rng200.c --- linux-6.1.66/drivers/char/hw_random/iproc-rng200.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/char/hw_random/iproc-rng200.c 2023-12-13 11:50:52.901971402 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:17 @ #include <linux/module.h> #include <linux/of_address.h> #include <linux/of_platform.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/delay.h> @ linux/arch/arm/boot/dts/bcm2708.dtsi:25 @ #define RNG_CTRL_OFFSET 0x00 #define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF #define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001 +#define RNG_CTRL_RNG_DIV_CTRL_SHIFT 13 #define RNG_SOFT_RESET_OFFSET 0x04 #define RNG_SOFT_RESET 0x00000001 @ linux/arch/arm/boot/dts/bcm2708.dtsi:33 @ #define RBG_SOFT_RESET_OFFSET 0x08 #define RBG_SOFT_RESET 0x00000001 +#define RNG_TOTAL_BIT_COUNT_OFFSET 0x0C + +#define RNG_TOTAL_BIT_COUNT_THRESHOLD_OFFSET 0x10 + #define RNG_INT_STATUS_OFFSET 0x18 #define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK 0x80000000 #define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK 0x00020000 #define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK 0x00000020 #define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK 0x00000001 +#define RNG_INT_ENABLE_OFFSET 0x1C + #define RNG_FIFO_DATA_OFFSET 0x20 #define RNG_FIFO_COUNT_OFFSET 0x24 #define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK 0x000000FF +#define RNG_FIFO_COUNT_RNG_FIFO_THRESHOLD_SHIFT 8 struct iproc_rng200_dev { struct hwrng rng; @ linux/arch/arm/boot/dts/bcm2708.dtsi:170 @ return 0; } +static int bcm2711_rng200_read(struct hwrng *rng, void *buf, size_t max, + bool wait) +{ + struct iproc_rng200_dev *priv = to_rng_priv(rng); + u32 max_words = max / sizeof(u32); + u32 num_words, count, val; + + /* ensure warm up period has elapsed */ + while (1) { + val = ioread32(priv->base + RNG_TOTAL_BIT_COUNT_OFFSET); + if (val > 16) + break; + cpu_relax(); + } + + /* ensure fifo is not empty */ + while (1) { + num_words = ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) & + RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK; + if (num_words) + break; + if (!wait) + return 0; + cpu_relax(); + } + + if (num_words > max_words) + num_words = max_words; + + for (count = 0; count < num_words; count++) { + ((u32 *)buf)[count] = ioread32(priv->base + + RNG_FIFO_DATA_OFFSET); + } + + return num_words * sizeof(u32); +} + +static int bcm2711_rng200_init(struct hwrng *rng) +{ + struct iproc_rng200_dev *priv = to_rng_priv(rng); + uint32_t val; + + if (ioread32(priv->base + RNG_CTRL_OFFSET) & RNG_CTRL_RNG_RBGEN_MASK) + return 0; + + /* initial numbers generated are "less random" so will be discarded */ + val = 0x40000; + iowrite32(val, priv->base + RNG_TOTAL_BIT_COUNT_THRESHOLD_OFFSET); + /* min fifo count to generate full interrupt */ + val = 2 << RNG_FIFO_COUNT_RNG_FIFO_THRESHOLD_SHIFT; + iowrite32(val, priv->base + RNG_FIFO_COUNT_OFFSET); + /* enable the rng - 1Mhz sample rate */ + val = (0x3 << RNG_CTRL_RNG_DIV_CTRL_SHIFT) | RNG_CTRL_RNG_RBGEN_MASK; + iowrite32(val, priv->base + RNG_CTRL_OFFSET); + + return 0; +} + static void iproc_rng200_cleanup(struct hwrng *rng) { struct iproc_rng200_dev *priv = to_rng_priv(rng); @ linux/arch/arm/boot/dts/bcm2708.dtsi:254 @ dev_set_drvdata(dev, priv); - priv->rng.name = "iproc-rng200"; - priv->rng.read = iproc_rng200_read; - priv->rng.init = iproc_rng200_init; + priv->rng.name = pdev->name; priv->rng.cleanup = iproc_rng200_cleanup; + if (of_device_is_compatible(dev->of_node, "brcm,bcm2711-rng200")) { + priv->rng.init = bcm2711_rng200_init; + priv->rng.read = bcm2711_rng200_read; + } else { + priv->rng.init = iproc_rng200_init; + priv->rng.read = iproc_rng200_read; + } + /* Register driver */ ret = devm_hwrng_register(dev, &priv->rng); if (ret) { diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/char/hw_random/Kconfig linux/drivers/char/hw_random/Kconfig --- linux-6.1.66/drivers/char/hw_random/Kconfig 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/char/hw_random/Kconfig 2023-12-13 11:50:52.897971393 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:107 @ default HW_RANDOM help This driver provides kernel-side support for the RNG200 - hardware found on the Broadcom iProc and STB SoCs. + hardware found on the Broadcom iProc, BCM2711 and STB SoCs. To compile this driver as a module, choose M here: the module will be called iproc-rng200 diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/char/Kconfig linux/drivers/char/Kconfig --- linux-6.1.66/drivers/char/Kconfig 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/char/Kconfig 2023-12-13 11:50:52.883971360 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:8 @ menu "Character devices" +source "drivers/char/broadcom/Kconfig" + source "drivers/tty/Kconfig" config TTY_PRINTK @ linux/arch/arm/boot/dts/bcm2708.dtsi:464 @ believe its RNG facilities may be faulty. This may also be configured at boot time with "random.trust_bootloader=on/off". +config RASPBERRYPI_GPIOMEM + tristate "Rootless GPIO access via mmap() on Raspberry Pi boards" + default n + help + Provides users with root-free access to the GPIO registers + on the board. Calling mmap(/dev/gpiomem) will map the GPIO + register page to the user's pointer. + endmenu diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/char/Makefile linux/drivers/char/Makefile --- linux-6.1.66/drivers/char/Makefile 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/char/Makefile 2023-12-13 11:50:52.883971360 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:48 @ obj-$(CONFIG_XILLYBUS_CLASS) += xillybus/ obj-$(CONFIG_POWERNV_OP_PANEL) += powernv-op-panel.o obj-$(CONFIG_ADI) += adi.o +obj-$(CONFIG_BRCM_CHAR_DRIVERS) += broadcom/ +obj-$(CONFIG_RASPBERRYPI_GPIOMEM) += raspberrypi-gpiomem.o diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/char/random.c linux/drivers/char/random.c --- linux-6.1.66/drivers/char/random.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/char/random.c 2023-12-13 11:50:52.931971473 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:826 @ unsigned long entropy[BLAKE2S_BLOCK_SIZE / sizeof(long)]; size_t i, longs, arch_bits; + /* + * If we were initialized by the bootloader before jump labels are + * initialized, then we should enable the static branch here, where + * it's guaranteed that jump labels have been initialized. + */ + if (!static_branch_likely(&crng_is_ready) && crng_init >= CRNG_READY) + crng_set_ready(NULL); + #if defined(LATENT_ENTROPY_PLUGIN) static const u8 compiletime_seed[BLAKE2S_BLOCK_SIZE] __initconst __latent_entropy; _mix_pool_bytes(compiletime_seed, sizeof(compiletime_seed)); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/char/raspberrypi-gpiomem.c linux/drivers/char/raspberrypi-gpiomem.c --- linux-6.1.66/drivers/char/raspberrypi-gpiomem.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/char/raspberrypi-gpiomem.c 2023-12-13 11:50:52.931971473 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/** + * raspberrypi-gpiomem.c + * + * Provides MMIO access to discontiguous section of Device memory as a linear + * user mapping. Successor to bcm2835-gpiomem.c. + * + * Copyright (c) 2023, Raspberry Pi Ltd. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/mm.h> +#include <linux/slab.h> +#include <linux/cdev.h> +#include <linux/pagemap.h> +#include <linux/io.h> + +#define DRIVER_NAME "rpi-gpiomem" +#define DEVICE_MINOR 0 + +/* + * Sensible max for a hypothetical "gpio" controller that splits pads, + * IO controls, GPIO in/out/enable, and function selection into different + * ranges. Most use only one or two. + */ +#define MAX_RANGES 4 + +struct io_windows { + unsigned long phys_base; + unsigned long len; +}; + +struct rpi_gpiomem_priv { + dev_t devid; + struct class *class; + struct cdev rpi_gpiomem_cdev; + struct device *dev; + const char *name; + unsigned int nr_wins; + struct io_windows iowins[4]; +}; + +static int rpi_gpiomem_open(struct inode *inode, struct file *file) +{ + int dev = iminor(inode); + int ret = 0; + struct rpi_gpiomem_priv *priv; + + if (dev != DEVICE_MINOR) + ret = -ENXIO; + + priv = container_of(inode->i_cdev, struct rpi_gpiomem_priv, + rpi_gpiomem_cdev); + if (!priv) + return -EINVAL; + file->private_data = priv; + return ret; +} + +static int rpi_gpiomem_release(struct inode *inode, struct file *file) +{ + int dev = iminor(inode); + int ret = 0; + + if (dev != DEVICE_MINOR) + ret = -ENXIO; + + return ret; +} + +static const struct vm_operations_struct rpi_gpiomem_vm_ops = { +#ifdef CONFIG_HAVE_IOREMAP_PROT + .access = generic_access_phys +#endif +}; + +static int rpi_gpiomem_mmap(struct file *file, struct vm_area_struct *vma) +{ + int i; + struct rpi_gpiomem_priv *priv; + unsigned long base; + unsigned long len = 0; + unsigned long offset; + + priv = file->private_data; + /* + * Userspace must provide a virtual address space at least + * the size of the concatenated ranges. + */ + for (i = 0; i < priv->nr_wins; i++) + len += priv->iowins[i].len; + if (len > vma->vm_end - vma->vm_start + 1) + return -EINVAL; + + vma->vm_ops = &rpi_gpiomem_vm_ops; + offset = vma->vm_start; + for (i = 0; i < priv->nr_wins; i++) { + base = priv->iowins[i].phys_base >> PAGE_SHIFT; + len = priv->iowins[i].len; + vma->vm_page_prot = phys_mem_access_prot(file, base, len, + vma->vm_page_prot); + if (remap_pfn_range(vma, offset, + base, len, + vma->vm_page_prot)) + break; + offset += len; + } + + if (i < priv->nr_wins) + return -EAGAIN; + + return 0; +} + +static const struct file_operations rpi_gpiomem_fops = { + .owner = THIS_MODULE, + .open = rpi_gpiomem_open, + .release = rpi_gpiomem_release, + .mmap = rpi_gpiomem_mmap, +}; + +static const struct of_device_id rpi_gpiomem_of_match[]; + +static int rpi_gpiomem_probe(struct platform_device *pdev) +{ + int err, i; + const struct of_device_id *id; + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct resource *ioresource; + struct rpi_gpiomem_priv *priv; + + /* Allocate buffers and instance data */ + + priv = kzalloc(sizeof(struct rpi_gpiomem_priv), GFP_KERNEL); + + if (!priv) { + err = -ENOMEM; + goto failed_inst_alloc; + } + platform_set_drvdata(pdev, priv); + + priv->dev = dev; + id = of_match_device(rpi_gpiomem_of_match, dev); + if (!id) + return -EINVAL; + + /* + * Device node naming - for legacy (bcm2835) DT bindings, the driver + * created the node based on a hardcoded name - for new bindings, + * take the node name from DT. + */ + if (id == &rpi_gpiomem_of_match[0]) { + priv->name = "gpiomem"; + } else { + err = of_property_read_string(node, "chardev-name", &priv->name); + if (err) + return -EINVAL; + } + + /* + * Go find the register ranges associated with this instance + */ + for (i = 0; i < MAX_RANGES; i++) { + ioresource = platform_get_resource(pdev, IORESOURCE_MEM, i); + if (!ioresource && i == 0) { + dev_err(priv->dev, "failed to get IO resource - no ranges available\n"); + err = -ENOENT; + goto failed_get_resource; + } + if (!ioresource) + break; + + priv->iowins[i].phys_base = ioresource->start; + priv->iowins[i].len = (ioresource->end + 1) - ioresource->start; + dev_info(&pdev->dev, "window base 0x%08lx size 0x%08lx\n", + priv->iowins[i].phys_base, priv->iowins[i].len); + priv->nr_wins++; + } + + /* Create character device entries */ + + err = alloc_chrdev_region(&priv->devid, + DEVICE_MINOR, 1, priv->name); + if (err != 0) { + dev_err(priv->dev, "unable to allocate device number"); + goto failed_alloc_chrdev; + } + cdev_init(&priv->rpi_gpiomem_cdev, &rpi_gpiomem_fops); + priv->rpi_gpiomem_cdev.owner = THIS_MODULE; + err = cdev_add(&priv->rpi_gpiomem_cdev, priv->devid, 1); + if (err != 0) { + dev_err(priv->dev, "unable to register device"); + goto failed_cdev_add; + } + + /* Create sysfs entries */ + + priv->class = class_create(THIS_MODULE, priv->name); + if (IS_ERR(priv->class)) { + err = PTR_ERR(priv->class); + goto failed_class_create; + } + + dev = device_create(priv->class, NULL, priv->devid, NULL, priv->name); + if (IS_ERR(dev)) { + err = PTR_ERR(dev); + goto failed_device_create; + } + + dev_info(priv->dev, "initialised %u regions as /dev/%s\n", + priv->nr_wins, priv->name); + + return 0; + +failed_device_create: + class_destroy(priv->class); +failed_class_create: + cdev_del(&priv->rpi_gpiomem_cdev); +failed_cdev_add: + unregister_chrdev_region(priv->devid, 1); +failed_alloc_chrdev: +failed_get_resource: + kfree(priv); +failed_inst_alloc: + dev_err(&pdev->dev, "could not load rpi_gpiomem"); + return err; +} + +static int rpi_gpiomem_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rpi_gpiomem_priv *priv = platform_get_drvdata(pdev); + + device_destroy(priv->class, priv->devid); + class_destroy(priv->class); + cdev_del(&priv->rpi_gpiomem_cdev); + unregister_chrdev_region(priv->devid, 1); + kfree(priv); + + dev_info(dev, "%s driver removed - OK", priv->name); + return 0; +} + +static const struct of_device_id rpi_gpiomem_of_match[] = { + { + .compatible = "brcm,bcm2835-gpiomem", + }, + { + .compatible = "raspberrypi,gpiomem", + }, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, rpi_gpiomem_of_match); + +static struct platform_driver rpi_gpiomem_driver = { + .probe = rpi_gpiomem_probe, + .remove = rpi_gpiomem_remove, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = rpi_gpiomem_of_match, + }, +}; + +module_platform_driver(rpi_gpiomem_driver); + +MODULE_ALIAS("platform:rpi-gpiomem"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("Driver for accessing GPIOs from userspace"); +MODULE_AUTHOR("Jonathan Bell <jonathan@raspberrypi.com>"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/char/tpm/tpm_tis_spi_main.c linux/drivers/char/tpm/tpm_tis_spi_main.c --- linux-6.1.66/drivers/char/tpm/tpm_tis_spi_main.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/char/tpm/tpm_tis_spi_main.c 2023-12-13 11:50:52.945971505 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:255 @ .pm = &tpm_tis_pm, .of_match_table = of_match_ptr(of_tis_spi_match), .acpi_match_table = ACPI_PTR(acpi_tis_spi_match), +#ifdef CONFIG_IMA + .probe_type = PROBE_FORCE_SYNCHRONOUS, +#else .probe_type = PROBE_PREFER_ASYNCHRONOUS, +#endif }, .probe = tpm_tis_spi_driver_probe, .remove = tpm_tis_spi_remove, diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/clk/bcm/clk-bcm2835.c linux/drivers/clk/bcm/clk-bcm2835.c --- linux-6.1.66/drivers/clk/bcm/clk-bcm2835.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/clk/bcm/clk-bcm2835.c 2023-12-13 11:50:52.971971567 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:39 @ #include <linux/platform_device.h> #include <linux/slab.h> #include <dt-bindings/clock/bcm2835.h> +#include <soc/bcm2835/raspberrypi-firmware.h> #define CM_PASSWORD 0x5a000000 @ linux/arch/arm/boot/dts/bcm2708.dtsi:300 @ #define SOC_BCM2711 BIT(1) #define SOC_ALL (SOC_BCM2835 | SOC_BCM2711) +#define VCMSG_ID_CORE_CLOCK 4 + /* * Names of clocks used within the driver that need to be replaced * with an external parent's name. This array is in the order that @ linux/arch/arm/boot/dts/bcm2708.dtsi:320 @ struct bcm2835_cprman { struct device *dev; void __iomem *regs; + struct rpi_firmware *fw; spinlock_t regs_lock; /* spinlock for all clocks */ unsigned int soc; @ linux/arch/arm/boot/dts/bcm2708.dtsi:650 @ spin_unlock(&cprman->regs_lock); /* Wait for the PLL to lock. */ - timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); - while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { - if (ktime_after(ktime_get(), timeout)) { - dev_err(cprman->dev, "%s: couldn't lock PLL\n", - clk_hw_get_name(hw)); - return -ETIMEDOUT; - } + if (strcmp(data->name, "pllh")) { + timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); + while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { + if (ktime_after(ktime_get(), timeout)) { + dev_err(cprman->dev, "%s: couldn't lock PLL\n", + clk_hw_get_name(hw)); + return -ETIMEDOUT; + } - cpu_relax(); + cpu_relax(); + } } cprman_write(cprman, data->a2w_ctrl_reg, @ linux/arch/arm/boot/dts/bcm2708.dtsi:1048 @ return rate; } +static unsigned long bcm2835_clock_get_rate_vpu(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); + struct bcm2835_cprman *cprman = clock->cprman; + + if (cprman->fw) { + struct { + u32 id; + u32 val; + } packet; + + packet.id = VCMSG_ID_CORE_CLOCK; + packet.val = 0; + + if (!rpi_firmware_property(cprman->fw, + RPI_FIRMWARE_GET_MAX_CLOCK_RATE, + &packet, sizeof(packet))) + return packet.val; + } + + return bcm2835_clock_get_rate(hw, parent_rate); +} + static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) { struct bcm2835_cprman *cprman = clock->cprman; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1130 @ return 0; } -static int bcm2835_clock_set_rate(struct clk_hw *hw, - unsigned long rate, unsigned long parent_rate) +static int bcm2835_clock_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate, + u8 parent) { struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct bcm2835_cprman *cprman = clock->cprman; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1143 @ spin_lock(&cprman->regs_lock); - /* - * Setting up frac support - * - * In principle it is recommended to stop/start the clock first, - * but as we set CLK_SET_RATE_GATE during registration of the - * clock this requirement should be take care of by the - * clk-framework. - */ - ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; + ctl = cprman_read(cprman, data->ctl_reg); + + /* If the clock is running, we have to pause clock generation while + * updating the control and div regs. This is glitchless (no clock + * signals generated faster than the rate) but each reg access is two + * OSC cycles so the clock will slow down for a moment. + */ + if (ctl & CM_ENABLE) { + cprman_write(cprman, data->ctl_reg, ctl & ~CM_ENABLE); + bcm2835_clock_wait_busy(clock); + } + + if (parent != 0xff) { + ctl &= ~(CM_SRC_MASK << CM_SRC_SHIFT); + ctl |= parent << CM_SRC_SHIFT; + } + + ctl &= ~CM_FRAC; ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; cprman_write(cprman, data->ctl_reg, ctl); @ linux/arch/arm/boot/dts/bcm2708.dtsi:1171 @ return 0; } +static int bcm2835_clock_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + return bcm2835_clock_set_rate_and_parent(hw, rate, parent_rate, 0xff); +} + static bool bcm2835_clk_is_pllc(struct clk_hw *hw) { @ linux/arch/arm/boot/dts/bcm2708.dtsi:1360 @ .unprepare = bcm2835_clock_off, .recalc_rate = bcm2835_clock_get_rate, .set_rate = bcm2835_clock_set_rate, + .set_rate_and_parent = bcm2835_clock_set_rate_and_parent, .determine_rate = bcm2835_clock_determine_rate, .set_parent = bcm2835_clock_set_parent, .get_parent = bcm2835_clock_get_parent, @ linux/arch/arm/boot/dts/bcm2708.dtsi:1378 @ */ static const struct clk_ops bcm2835_vpu_clock_clk_ops = { .is_prepared = bcm2835_vpu_clock_is_on, - .recalc_rate = bcm2835_clock_get_rate, + .recalc_rate = bcm2835_clock_get_rate_vpu, .set_rate = bcm2835_clock_set_rate, .determine_rate = bcm2835_clock_determine_rate, .set_parent = bcm2835_clock_set_parent, @ linux/arch/arm/boot/dts/bcm2708.dtsi:1386 @ .debug_init = bcm2835_clock_debug_init, }; +static bool bcm2835_clk_is_claimed(const char *name); + static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, const void *data) { @ linux/arch/arm/boot/dts/bcm2708.dtsi:1405 @ init.ops = &bcm2835_pll_clk_ops; init.flags = pll_data->flags | CLK_IGNORE_UNUSED; + if (!bcm2835_clk_is_claimed(pll_data->name)) + init.flags |= CLK_IS_CRITICAL; + pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) return NULL; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1463 @ divider->div.hw.init = &init; divider->div.table = NULL; + if (!(cprman_read(cprman, divider_data->cm_reg) & divider_data->hold_mask)) { + if (!bcm2835_clk_is_claimed(divider_data->source_pll)) + init.flags |= CLK_IS_CRITICAL; + if (!bcm2835_clk_is_claimed(divider_data->name)) + divider->div.flags |= CLK_IS_CRITICAL; + } + divider->cprman = cprman; divider->data = divider_data; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1524 @ init.flags = clock_data->flags | CLK_IGNORE_UNUSED; /* + * Some GPIO clocks for ethernet/wifi PLLs are marked as + * critical (since some platforms use them), but if the + * firmware didn't have them turned on then they clearly + * aren't actually critical. + */ + if ((cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE) == 0) + init.flags &= ~CLK_IS_CRITICAL; + + /* * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate * rate changes on at least of the parents. */ @ linux/arch/arm/boot/dts/bcm2708.dtsi:1543 @ init.ops = &bcm2835_vpu_clock_clk_ops; } else { init.ops = &bcm2835_clock_clk_ops; - init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; /* If the clock wasn't actually enabled at boot, it's not * critical. @ linux/arch/arm/boot/dts/bcm2708.dtsi:1767 @ .hold_mask = CM_PLLA_HOLDCORE, .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), - [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( - SOC_ALL, - .name = "plla_per", - .source_pll = "plla", - .cm_reg = CM_PLLA, - .a2w_reg = A2W_PLLA_PER, - .load_mask = CM_PLLA_LOADPER, - .hold_mask = CM_PLLA_HOLDPER, - .fixed_divider = 1, - .flags = CLK_SET_RATE_PARENT), + + /* + * PLLA_PER is used for gpu clocks. Controlled by firmware, see + * clk-raspberrypi.c. + */ + [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( SOC_ALL, .name = "plla_dsi0", @ linux/arch/arm/boot/dts/bcm2708.dtsi:2073 @ .int_bits = 6, .frac_bits = 0, .tcnt_mux = 3), - [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK( - SOC_ALL, - .name = "v3d", - .ctl_reg = CM_V3DCTL, - .div_reg = CM_V3DDIV, - .int_bits = 4, - .frac_bits = 8, - .tcnt_mux = 4), + + /* + * CLOCK_V3D is used for v3d clock. Controlled by firmware, see + * clk-raspberrypi.c. + */ + /* * VPU clock. This doesn't have an enable bit, since it drives * the bus for everything else, and is special so it doesn't need @ linux/arch/arm/boot/dts/bcm2708.dtsi:2241 @ .tcnt_mux = 28, .round_up = true), - /* TV encoder clock. Only operating frequency is 108Mhz. */ - [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( - SOC_ALL, - .name = "vec", - .ctl_reg = CM_VECCTL, - .div_reg = CM_VECDIV, - .int_bits = 4, - .frac_bits = 0, - /* - * Allow rate change propagation only on PLLH_AUX which is - * assigned index 7 in the parent array. - */ - .set_rate_parent = BIT(7), - .tcnt_mux = 29), - /* dsi clocks */ [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( SOC_ALL, @ linux/arch/arm/boot/dts/bcm2708.dtsi:2290 @ .ctl_reg = CM_PERIICTL), }; +static bool bcm2835_clk_claimed[ARRAY_SIZE(clk_desc_array)]; + /* * Permanently take a reference on the parent of the SDRAM clock. * @ linux/arch/arm/boot/dts/bcm2708.dtsi:2311 @ return clk_prepare_enable(parent); } +static bool bcm2835_clk_is_claimed(const char *name) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(clk_desc_array); i++) { + if (clk_desc_array[i].data) { + const char *clk_name = *(const char **)(clk_desc_array[i].data); + if (!strcmp(name, clk_name)) + return bcm2835_clk_claimed[i]; + } + } + + return false; +} + static int bcm2835_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @ linux/arch/arm/boot/dts/bcm2708.dtsi:2334 @ const struct bcm2835_clk_desc *desc; const size_t asize = ARRAY_SIZE(clk_desc_array); const struct cprman_plat_data *pdata; + struct device_node *fw_node; size_t i; + u32 clk_id; int ret; pdata = of_device_get_match_data(&pdev->dev); @ linux/arch/arm/boot/dts/bcm2708.dtsi:2355 @ if (IS_ERR(cprman->regs)) return PTR_ERR(cprman->regs); + fw_node = of_parse_phandle(dev->of_node, "firmware", 0); + if (fw_node) { + struct rpi_firmware *fw = rpi_firmware_get(fw_node); + if (!fw) + return -EPROBE_DEFER; + cprman->fw = fw; + } + + memset(bcm2835_clk_claimed, 0, sizeof(bcm2835_clk_claimed)); + for (i = 0; + !of_property_read_u32_index(pdev->dev.of_node, "claim-clocks", + i, &clk_id); + i++) + bcm2835_clk_claimed[clk_id]= true; + memcpy(cprman->real_parent_names, cprman_parent_names, sizeof(cprman_parent_names)); of_clk_parent_fill(dev->of_node, cprman->real_parent_names, @ linux/arch/arm/boot/dts/bcm2708.dtsi:2403 @ if (ret) return ret; - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, &cprman->onecell); + if (ret) + return ret; + + /* note that we have registered all the clocks */ + dev_dbg(dev, "registered %zd clocks\n", asize); + + return 0; } static const struct cprman_plat_data cprman_bcm2835_plat_data = { @ linux/arch/arm/boot/dts/bcm2708.dtsi:2437 @ .probe = bcm2835_clk_probe, }; -builtin_platform_driver(bcm2835_clk_driver); +static int __init __bcm2835_clk_driver_init(void) +{ + return platform_driver_register(&bcm2835_clk_driver); +} +#ifdef CONFIG_IMA +subsys_initcall(__bcm2835_clk_driver_init); +#else +postcore_initcall(__bcm2835_clk_driver_init); +#endif MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); MODULE_DESCRIPTION("BCM2835 clock driver"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/clk/bcm/clk-raspberrypi.c linux/drivers/clk/bcm/clk-raspberrypi.c --- linux-6.1.66/drivers/clk/bcm/clk-raspberrypi.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/clk/bcm/clk-raspberrypi.c 2023-12-13 11:50:52.975971576 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:21 @ #include <soc/bcm2835/raspberrypi-firmware.h> -enum rpi_firmware_clk_id { - RPI_FIRMWARE_EMMC_CLK_ID = 1, - RPI_FIRMWARE_UART_CLK_ID, - RPI_FIRMWARE_ARM_CLK_ID, - RPI_FIRMWARE_CORE_CLK_ID, - RPI_FIRMWARE_V3D_CLK_ID, - RPI_FIRMWARE_H264_CLK_ID, - RPI_FIRMWARE_ISP_CLK_ID, - RPI_FIRMWARE_SDRAM_CLK_ID, - RPI_FIRMWARE_PIXEL_CLK_ID, - RPI_FIRMWARE_PWM_CLK_ID, - RPI_FIRMWARE_HEVC_CLK_ID, - RPI_FIRMWARE_EMMC2_CLK_ID, - RPI_FIRMWARE_M2MC_CLK_ID, - RPI_FIRMWARE_PIXEL_BVB_CLK_ID, - RPI_FIRMWARE_VEC_CLK_ID, - RPI_FIRMWARE_NUM_CLK_ID, -}; - static char *rpi_firmware_clk_names[] = { [RPI_FIRMWARE_EMMC_CLK_ID] = "emmc", [RPI_FIRMWARE_UART_CLK_ID] = "uart", @ linux/arch/arm/boot/dts/bcm2708.dtsi:37 @ [RPI_FIRMWARE_M2MC_CLK_ID] = "m2mc", [RPI_FIRMWARE_PIXEL_BVB_CLK_ID] = "pixel-bvb", [RPI_FIRMWARE_VEC_CLK_ID] = "vec", + [RPI_FIRMWARE_DISP_CLK_ID] = "disp", }; #define RPI_FIRMWARE_STATE_ENABLE_BIT BIT(0) @ linux/arch/arm/boot/dts/bcm2708.dtsi:60 @ struct raspberrypi_clk *rpi; }; +static inline +const struct raspberrypi_clk_data *clk_hw_to_data(const struct clk_hw *hw) +{ + return container_of(hw, struct raspberrypi_clk_data, hw); +} + struct raspberrypi_clk_variant { bool export; char *clkdev; @ linux/arch/arm/boot/dts/bcm2708.dtsi:121 @ }, [RPI_FIRMWARE_V3D_CLK_ID] = { .export = true, + .minimize = true, }, [RPI_FIRMWARE_PIXEL_CLK_ID] = { .export = true, + .minimize = true, }, [RPI_FIRMWARE_HEVC_CLK_ID] = { .export = true, + .minimize = true, + }, + [RPI_FIRMWARE_ISP_CLK_ID] = { + .export = true, + .minimize = true, }, [RPI_FIRMWARE_PIXEL_BVB_CLK_ID] = { .export = true, + .minimize = true, }, [RPI_FIRMWARE_VEC_CLK_ID] = { .export = true, + .minimize = true, + }, + [RPI_FIRMWARE_DISP_CLK_ID] = { + .export = true, + .minimize = true, }, }; @ linux/arch/arm/boot/dts/bcm2708.dtsi:176 @ struct raspberrypi_firmware_prop msg = { .id = cpu_to_le32(data->id), .val = cpu_to_le32(*val), - .disable_turbo = cpu_to_le32(1), + .disable_turbo = cpu_to_le32(0), }; int ret; @ linux/arch/arm/boot/dts/bcm2708.dtsi:191 @ static int raspberrypi_fw_is_prepared(struct clk_hw *hw) { - struct raspberrypi_clk_data *data = - container_of(hw, struct raspberrypi_clk_data, hw); + const struct raspberrypi_clk_data *data = clk_hw_to_data(hw); struct raspberrypi_clk *rpi = data->rpi; u32 val = 0; int ret; @ linux/arch/arm/boot/dts/bcm2708.dtsi:208 @ static unsigned long raspberrypi_fw_get_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct raspberrypi_clk_data *data = - container_of(hw, struct raspberrypi_clk_data, hw); + const struct raspberrypi_clk_data *data = clk_hw_to_data(hw); struct raspberrypi_clk *rpi = data->rpi; u32 val = 0; int ret; @ linux/arch/arm/boot/dts/bcm2708.dtsi:224 @ static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct raspberrypi_clk_data *data = - container_of(hw, struct raspberrypi_clk_data, hw); + const struct raspberrypi_clk_data *data = clk_hw_to_data(hw); struct raspberrypi_clk *rpi = data->rpi; u32 _rate = rate; int ret; @ linux/arch/arm/boot/dts/bcm2708.dtsi:241 @ static int raspberrypi_fw_dumb_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - struct raspberrypi_clk_data *data = - container_of(hw, struct raspberrypi_clk_data, hw); + const struct raspberrypi_clk_data *data = clk_hw_to_data(hw); struct raspberrypi_clk_variant *variant = data->variant; /* diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/clk/clk-hifiberry-dachd.c linux/drivers/clk/clk-hifiberry-dachd.c --- linux-6.1.66/drivers/clk/clk-hifiberry-dachd.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/clk/clk-hifiberry-dachd.c 2023-12-13 11:50:52.985971600 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock Driver for HiFiBerry DAC+ HD + * + * Author: Joerg Schambacher, i2Audio GmbH for HiFiBerry + * Copyright 2020 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/clk.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/slab.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> +#include <linux/regmap.h> + +#define NO_PLL_RESET 0 +#define PLL_RESET 1 +#define HIFIBERRY_PLL_MAX_REGISTER 256 +#define DEFAULT_RATE 44100 + +static struct reg_default hifiberry_pll_reg_defaults[] = { + {0x02, 0x53}, {0x03, 0x00}, {0x07, 0x20}, {0x0F, 0x00}, + {0x10, 0x0D}, {0x11, 0x1D}, {0x12, 0x0D}, {0x13, 0x8C}, + {0x14, 0x8C}, {0x15, 0x8C}, {0x16, 0x8C}, {0x17, 0x8C}, + {0x18, 0x2A}, {0x1C, 0x00}, {0x1D, 0x0F}, {0x1F, 0x00}, + {0x2A, 0x00}, {0x2C, 0x00}, {0x2F, 0x00}, {0x30, 0x00}, + {0x31, 0x00}, {0x32, 0x00}, {0x34, 0x00}, {0x37, 0x00}, + {0x38, 0x00}, {0x39, 0x00}, {0x3A, 0x00}, {0x3B, 0x01}, + {0x3E, 0x00}, {0x3F, 0x00}, {0x40, 0x00}, {0x41, 0x00}, + {0x5A, 0x00}, {0x5B, 0x00}, {0x95, 0x00}, {0x96, 0x00}, + {0x97, 0x00}, {0x98, 0x00}, {0x99, 0x00}, {0x9A, 0x00}, + {0x9B, 0x00}, {0xA2, 0x00}, {0xA3, 0x00}, {0xA4, 0x00}, + {0xB7, 0x92}, + {0x1A, 0x3D}, {0x1B, 0x09}, {0x1E, 0xF3}, {0x20, 0x13}, + {0x21, 0x75}, {0x2B, 0x04}, {0x2D, 0x11}, {0x2E, 0xE0}, + {0x3D, 0x7A}, + {0x35, 0x9D}, {0x36, 0x00}, {0x3C, 0x42}, + { 177, 0xAC}, +}; +static struct reg_default common_pll_regs[HIFIBERRY_PLL_MAX_REGISTER]; +static int num_common_pll_regs; +static struct reg_default dedicated_192k_pll_regs[HIFIBERRY_PLL_MAX_REGISTER]; +static int num_dedicated_192k_pll_regs; +static struct reg_default dedicated_96k_pll_regs[HIFIBERRY_PLL_MAX_REGISTER]; +static int num_dedicated_96k_pll_regs; +static struct reg_default dedicated_48k_pll_regs[HIFIBERRY_PLL_MAX_REGISTER]; +static int num_dedicated_48k_pll_regs; +static struct reg_default dedicated_176k4_pll_regs[HIFIBERRY_PLL_MAX_REGISTER]; +static int num_dedicated_176k4_pll_regs; +static struct reg_default dedicated_88k2_pll_regs[HIFIBERRY_PLL_MAX_REGISTER]; +static int num_dedicated_88k2_pll_regs; +static struct reg_default dedicated_44k1_pll_regs[HIFIBERRY_PLL_MAX_REGISTER]; +static int num_dedicated_44k1_pll_regs; + +/** + * struct clk_hifiberry_drvdata - Common struct to the HiFiBerry DAC HD Clk + * @hw: clk_hw for the common clk framework + */ +struct clk_hifiberry_drvdata { + struct regmap *regmap; + struct clk *clk; + struct clk_hw hw; + unsigned long rate; +}; + +#define to_hifiberry_clk(_hw) \ + container_of(_hw, struct clk_hifiberry_drvdata, hw) + +static int clk_hifiberry_dachd_write_pll_regs(struct regmap *regmap, + struct reg_default *regs, + int num, int do_pll_reset) +{ + int i; + int ret = 0; + char pll_soft_reset[] = { 177, 0xAC, }; + + for (i = 0; i < num; i++) { + ret |= regmap_write(regmap, regs[i].reg, regs[i].def); + if (ret) + return ret; + } + if (do_pll_reset) { + ret |= regmap_write(regmap, pll_soft_reset[0], + pll_soft_reset[1]); + mdelay(10); + } + return ret; +} + +static unsigned long clk_hifiberry_dachd_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return to_hifiberry_clk(hw)->rate; +} + +static long clk_hifiberry_dachd_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + return rate; +} + +static int clk_hifiberry_dachd_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + int ret; + struct clk_hifiberry_drvdata *drvdata = to_hifiberry_clk(hw); + + switch (rate) { + case 44100: + ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap, + dedicated_44k1_pll_regs, num_dedicated_44k1_pll_regs, + PLL_RESET); + break; + case 88200: + ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap, + dedicated_88k2_pll_regs, num_dedicated_88k2_pll_regs, + PLL_RESET); + break; + case 176400: + ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap, + dedicated_176k4_pll_regs, num_dedicated_176k4_pll_regs, + PLL_RESET); + break; + case 48000: + ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap, + dedicated_48k_pll_regs, num_dedicated_48k_pll_regs, + PLL_RESET); + break; + case 96000: + ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap, + dedicated_96k_pll_regs, num_dedicated_96k_pll_regs, + PLL_RESET); + break; + case 192000: + ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap, + dedicated_192k_pll_regs, num_dedicated_192k_pll_regs, + PLL_RESET); + break; + default: + ret = -EINVAL; + break; + } + to_hifiberry_clk(hw)->rate = rate; + + return ret; +} + +const struct clk_ops clk_hifiberry_dachd_rate_ops = { + .recalc_rate = clk_hifiberry_dachd_recalc_rate, + .round_rate = clk_hifiberry_dachd_round_rate, + .set_rate = clk_hifiberry_dachd_set_rate, +}; + +static int clk_hifiberry_get_prop_values(struct device *dev, + char *prop_name, + struct reg_default *regs) +{ + int ret; + int i; + u8 tmp[2 * HIFIBERRY_PLL_MAX_REGISTER]; + + ret = of_property_read_variable_u8_array(dev->of_node, prop_name, + tmp, 0, 2 * HIFIBERRY_PLL_MAX_REGISTER); + if (ret < 0) + return ret; + if (ret & 1) { + dev_err(dev, + "%s <%s> -> #%i odd number of bytes for reg/val pairs!", + __func__, + prop_name, + ret); + return -EINVAL; + } + ret /= 2; + for (i = 0; i < ret; i++) { + regs[i].reg = (u32)tmp[2 * i]; + regs[i].def = (u32)tmp[2 * i + 1]; + } + return ret; +} + + +static int clk_hifiberry_dachd_dt_parse(struct device *dev) +{ + num_common_pll_regs = clk_hifiberry_get_prop_values(dev, + "common_pll_regs", common_pll_regs); + num_dedicated_44k1_pll_regs = clk_hifiberry_get_prop_values(dev, + "44k1_pll_regs", dedicated_44k1_pll_regs); + num_dedicated_88k2_pll_regs = clk_hifiberry_get_prop_values(dev, + "88k2_pll_regs", dedicated_88k2_pll_regs); + num_dedicated_176k4_pll_regs = clk_hifiberry_get_prop_values(dev, + "176k4_pll_regs", dedicated_176k4_pll_regs); + num_dedicated_48k_pll_regs = clk_hifiberry_get_prop_values(dev, + "48k_pll_regs", dedicated_48k_pll_regs); + num_dedicated_96k_pll_regs = clk_hifiberry_get_prop_values(dev, + "96k_pll_regs", dedicated_96k_pll_regs); + num_dedicated_192k_pll_regs = clk_hifiberry_get_prop_values(dev, + "192k_pll_regs", dedicated_192k_pll_regs); + return 0; +} + + +static int clk_hifiberry_dachd_remove(struct device *dev) +{ + of_clk_del_provider(dev->of_node); + return 0; +} + +const struct regmap_config hifiberry_pll_regmap = { + .reg_bits = 8, + .val_bits = 8, + .max_register = HIFIBERRY_PLL_MAX_REGISTER, + .reg_defaults = hifiberry_pll_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(hifiberry_pll_reg_defaults), + .cache_type = REGCACHE_RBTREE, +}; +EXPORT_SYMBOL_GPL(hifiberry_pll_regmap); + + +static int clk_hifiberry_dachd_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct clk_hifiberry_drvdata *hdclk; + int ret = 0; + struct clk_init_data init; + struct device *dev = &i2c->dev; + struct device_node *dev_node = dev->of_node; + struct regmap_config config = hifiberry_pll_regmap; + + hdclk = devm_kzalloc(&i2c->dev, + sizeof(struct clk_hifiberry_drvdata), GFP_KERNEL); + if (!hdclk) + return -ENOMEM; + + i2c_set_clientdata(i2c, hdclk); + + hdclk->regmap = devm_regmap_init_i2c(i2c, &config); + + if (IS_ERR(hdclk->regmap)) + return PTR_ERR(hdclk->regmap); + + /* start PLL to allow detection of DAC */ + ret = clk_hifiberry_dachd_write_pll_regs(hdclk->regmap, + hifiberry_pll_reg_defaults, + ARRAY_SIZE(hifiberry_pll_reg_defaults), + PLL_RESET); + if (ret) + return ret; + + clk_hifiberry_dachd_dt_parse(dev); + + /* restart PLL with configs from DTB */ + ret = clk_hifiberry_dachd_write_pll_regs(hdclk->regmap, common_pll_regs, + num_common_pll_regs, PLL_RESET); + if (ret) + return ret; + + init.name = "clk-hifiberry-dachd"; + init.ops = &clk_hifiberry_dachd_rate_ops; + init.flags = 0; + init.parent_names = NULL; + init.num_parents = 0; + + hdclk->hw.init = &init; + + hdclk->clk = devm_clk_register(dev, &hdclk->hw); + if (IS_ERR(hdclk->clk)) { + dev_err(dev, "unable to register %s\n", init.name); + return PTR_ERR(hdclk->clk); + } + + ret = of_clk_add_provider(dev_node, of_clk_src_simple_get, hdclk->clk); + if (ret != 0) { + dev_err(dev, "Cannot of_clk_add_provider"); + return ret; + } + + ret = clk_set_rate(hdclk->hw.clk, DEFAULT_RATE); + if (ret != 0) { + dev_err(dev, "Cannot set rate : %d\n", ret); + return -EINVAL; + } + + return ret; +} + +static void clk_hifiberry_dachd_i2c_remove(struct i2c_client *i2c) +{ + clk_hifiberry_dachd_remove(&i2c->dev); +} + +static const struct i2c_device_id clk_hifiberry_dachd_i2c_id[] = { + { "dachd-clk", }, + { } +}; +MODULE_DEVICE_TABLE(i2c, clk_hifiberry_dachd_i2c_id); + +static const struct of_device_id clk_hifiberry_dachd_of_match[] = { + { .compatible = "hifiberry,dachd-clk", }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_hifiberry_dachd_of_match); + +static struct i2c_driver clk_hifiberry_dachd_i2c_driver = { + .probe = clk_hifiberry_dachd_i2c_probe, + .remove = clk_hifiberry_dachd_i2c_remove, + .id_table = clk_hifiberry_dachd_i2c_id, + .driver = { + .name = "dachd-clk", + .of_match_table = of_match_ptr(clk_hifiberry_dachd_of_match), + }, +}; + +module_i2c_driver(clk_hifiberry_dachd_i2c_driver); + + +MODULE_DESCRIPTION("HiFiBerry DAC+ HD clock driver"); +MODULE_AUTHOR("Joerg Schambacher <joerg@i2audio.com>"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:clk-hifiberry-dachd"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/clk/clk-hifiberry-dacpro.c linux/drivers/clk/clk-hifiberry-dacpro.c --- linux-6.1.66/drivers/clk/clk-hifiberry-dacpro.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/clk/clk-hifiberry-dacpro.c 2023-12-13 11:50:52.986971602 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * Clock Driver for HiFiBerry DAC Pro + * + * Author: Stuart MacLean + * Copyright 2015 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/clkdev.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/slab.h> +#include <linux/platform_device.h> + +struct ext_clk_rates { + /* Clock rate of CLK44EN attached to GPIO6 pin */ + unsigned long clk_44en; + /* Clock rate of CLK48EN attached to GPIO3 pin */ + unsigned long clk_48en; +}; + +/** + * struct hifiberry_dacpro_clk - Common struct to the HiFiBerry DAC Pro + * @hw: clk_hw for the common clk framework + * @mode: 0 => CLK44EN, 1 => CLK48EN + */ +struct clk_hifiberry_hw { + struct clk_hw hw; + uint8_t mode; + struct ext_clk_rates clk_rates; +}; + +#define to_hifiberry_clk(_hw) container_of(_hw, struct clk_hifiberry_hw, hw) + +static const struct ext_clk_rates hifiberry_dacpro_clks = { + .clk_44en = 22579200UL, + .clk_48en = 24576000UL, +}; + +static const struct ext_clk_rates allo_dac_clks = { + .clk_44en = 45158400UL, + .clk_48en = 49152000UL, +}; + +static const struct of_device_id clk_hifiberry_dacpro_dt_ids[] = { + { .compatible = "hifiberry,dacpro-clk", &hifiberry_dacpro_clks }, + { .compatible = "allo,dac-clk", &allo_dac_clks }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_hifiberry_dacpro_dt_ids); + +static unsigned long clk_hifiberry_dacpro_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_hifiberry_hw *clk = to_hifiberry_clk(hw); + return (clk->mode == 0) ? clk->clk_rates.clk_44en : + clk->clk_rates.clk_48en; +} + +static long clk_hifiberry_dacpro_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + struct clk_hifiberry_hw *clk = to_hifiberry_clk(hw); + long actual_rate; + + if (rate <= clk->clk_rates.clk_44en) { + actual_rate = (long)clk->clk_rates.clk_44en; + } else if (rate >= clk->clk_rates.clk_48en) { + actual_rate = (long)clk->clk_rates.clk_48en; + } else { + long diff44Rate = (long)(rate - clk->clk_rates.clk_44en); + long diff48Rate = (long)(clk->clk_rates.clk_48en - rate); + + if (diff44Rate < diff48Rate) + actual_rate = (long)clk->clk_rates.clk_44en; + else + actual_rate = (long)clk->clk_rates.clk_48en; + } + return actual_rate; +} + + +static int clk_hifiberry_dacpro_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + struct clk_hifiberry_hw *clk = to_hifiberry_clk(hw); + unsigned long actual_rate; + + actual_rate = (unsigned long)clk_hifiberry_dacpro_round_rate(hw, rate, + &parent_rate); + clk->mode = (actual_rate == clk->clk_rates.clk_44en) ? 0 : 1; + return 0; +} + + +const struct clk_ops clk_hifiberry_dacpro_rate_ops = { + .recalc_rate = clk_hifiberry_dacpro_recalc_rate, + .round_rate = clk_hifiberry_dacpro_round_rate, + .set_rate = clk_hifiberry_dacpro_set_rate, +}; + +static int clk_hifiberry_dacpro_probe(struct platform_device *pdev) +{ + const struct of_device_id *of_id; + struct clk_hifiberry_hw *proclk; + struct clk *clk; + struct device *dev; + struct clk_init_data init; + int ret; + + dev = &pdev->dev; + of_id = of_match_node(clk_hifiberry_dacpro_dt_ids, dev->of_node); + if (!of_id) + return -EINVAL; + + proclk = kzalloc(sizeof(struct clk_hifiberry_hw), GFP_KERNEL); + if (!proclk) + return -ENOMEM; + + init.name = "clk-hifiberry-dacpro"; + init.ops = &clk_hifiberry_dacpro_rate_ops; + init.flags = 0; + init.parent_names = NULL; + init.num_parents = 0; + + proclk->mode = 0; + proclk->hw.init = &init; + memcpy(&proclk->clk_rates, of_id->data, sizeof(proclk->clk_rates)); + + clk = devm_clk_register(dev, &proclk->hw); + if (!IS_ERR(clk)) { + ret = of_clk_add_provider(dev->of_node, of_clk_src_simple_get, + clk); + } else { + dev_err(dev, "Fail to register clock driver\n"); + kfree(proclk); + ret = PTR_ERR(clk); + } + return ret; +} + +static int clk_hifiberry_dacpro_remove(struct platform_device *pdev) +{ + of_clk_del_provider(pdev->dev.of_node); + return 0; +} + +static struct platform_driver clk_hifiberry_dacpro_driver = { + .probe = clk_hifiberry_dacpro_probe, + .remove = clk_hifiberry_dacpro_remove, + .driver = { + .name = "clk-hifiberry-dacpro", + .of_match_table = clk_hifiberry_dacpro_dt_ids, + }, +}; + +static int __init clk_hifiberry_dacpro_init(void) +{ + return platform_driver_register(&clk_hifiberry_dacpro_driver); +} +core_initcall(clk_hifiberry_dacpro_init); + +static void __exit clk_hifiberry_dacpro_exit(void) +{ + platform_driver_unregister(&clk_hifiberry_dacpro_driver); +} +module_exit(clk_hifiberry_dacpro_exit); + +MODULE_DESCRIPTION("HiFiBerry DAC Pro clock driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:clk-hifiberry-dacpro"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/clk/clk-rp1.c linux/drivers/clk/clk-rp1.c --- linux-6.1.66/drivers/clk/clk-rp1.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/clk/clk-rp1.c 2023-12-13 11:50:52.993971618 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Raspberry Pi Ltd. + * + * Clock driver for RP1 PCIe multifunction chip. + */ + +#include <linux/clk-provider.h> +#include <linux/clkdev.h> +#include <linux/clk.h> +#include <linux/debugfs.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/math64.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/rp1_platform.h> +#include <linux/slab.h> + +#include <asm/div64.h> + +#include <dt-bindings/clock/rp1.h> + +#define PLL_SYS_CS 0x08000 +#define PLL_SYS_PWR 0x08004 +#define PLL_SYS_FBDIV_INT 0x08008 +#define PLL_SYS_FBDIV_FRAC 0x0800c +#define PLL_SYS_PRIM 0x08010 +#define PLL_SYS_SEC 0x08014 + +#define PLL_AUDIO_CS 0x0c000 +#define PLL_AUDIO_PWR 0x0c004 +#define PLL_AUDIO_FBDIV_INT 0x0c008 +#define PLL_AUDIO_FBDIV_FRAC 0x0c00c +#define PLL_AUDIO_PRIM 0x0c010 +#define PLL_AUDIO_SEC 0x0c014 + +#define PLL_VIDEO_CS 0x10000 +#define PLL_VIDEO_PWR 0x10004 +#define PLL_VIDEO_FBDIV_INT 0x10008 +#define PLL_VIDEO_FBDIV_FRAC 0x1000c +#define PLL_VIDEO_PRIM 0x10010 +#define PLL_VIDEO_SEC 0x10014 + +#define CLK_SYS_CTRL 0x00014 +#define CLK_SYS_DIV_INT 0x00018 +#define CLK_SYS_SEL 0x00020 + +#define CLK_SLOW_SYS_CTRL 0x00024 +#define CLK_SLOW_SYS_DIV_INT 0x00028 +#define CLK_SLOW_SYS_SEL 0x00030 + +#define CLK_DMA_CTRL 0x00044 +#define CLK_DMA_DIV_INT 0x00048 +#define CLK_DMA_SEL 0x00050 + +#define CLK_UART_CTRL 0x00054 +#define CLK_UART_DIV_INT 0x00058 +#define CLK_UART_SEL 0x00060 + +#define CLK_ETH_CTRL 0x00064 +#define CLK_ETH_DIV_INT 0x00068 +#define CLK_ETH_SEL 0x00070 + +#define CLK_PWM0_CTRL 0x00074 +#define CLK_PWM0_DIV_INT 0x00078 +#define CLK_PWM0_DIV_FRAC 0x0007c +#define CLK_PWM0_SEL 0x00080 + +#define CLK_PWM1_CTRL 0x00084 +#define CLK_PWM1_DIV_INT 0x00088 +#define CLK_PWM1_DIV_FRAC 0x0008c +#define CLK_PWM1_SEL 0x00090 + +#define CLK_AUDIO_IN_CTRL 0x00094 +#define CLK_AUDIO_IN_DIV_INT 0x00098 +#define CLK_AUDIO_IN_SEL 0x000a0 + +#define CLK_AUDIO_OUT_CTRL 0x000a4 +#define CLK_AUDIO_OUT_DIV_INT 0x000a8 +#define CLK_AUDIO_OUT_SEL 0x000b0 + +#define CLK_I2S_CTRL 0x000b4 +#define CLK_I2S_DIV_INT 0x000b8 +#define CLK_I2S_SEL 0x000c0 + +#define CLK_MIPI0_CFG_CTRL 0x000c4 +#define CLK_MIPI0_CFG_DIV_INT 0x000c8 +#define CLK_MIPI0_CFG_SEL 0x000d0 + +#define CLK_MIPI1_CFG_CTRL 0x000d4 +#define CLK_MIPI1_CFG_DIV_INT 0x000d8 +#define CLK_MIPI1_CFG_SEL 0x000e0 + +#define CLK_PCIE_AUX_CTRL 0x000e4 +#define CLK_PCIE_AUX_DIV_INT 0x000e8 +#define CLK_PCIE_AUX_SEL 0x000f0 + +#define CLK_USBH0_MICROFRAME_CTRL 0x000f4 +#define CLK_USBH0_MICROFRAME_DIV_INT 0x000f8 +#define CLK_USBH0_MICROFRAME_SEL 0x00100 + +#define CLK_USBH1_MICROFRAME_CTRL 0x00104 +#define CLK_USBH1_MICROFRAME_DIV_INT 0x00108 +#define CLK_USBH1_MICROFRAME_SEL 0x00110 + +#define CLK_USBH0_SUSPEND_CTRL 0x00114 +#define CLK_USBH0_SUSPEND_DIV_INT 0x00118 +#define CLK_USBH0_SUSPEND_SEL 0x00120 + +#define CLK_USBH1_SUSPEND_CTRL 0x00124 +#define CLK_USBH1_SUSPEND_DIV_INT 0x00128 +#define CLK_USBH1_SUSPEND_SEL 0x00130 + +#define CLK_ETH_TSU_CTRL 0x00134 +#define CLK_ETH_TSU_DIV_INT 0x00138 +#define CLK_ETH_TSU_SEL 0x00140 + +#define CLK_ADC_CTRL 0x00144 +#define CLK_ADC_DIV_INT 0x00148 +#define CLK_ADC_SEL 0x00150 + +#define CLK_SDIO_TIMER_CTRL 0x00154 +#define CLK_SDIO_TIMER_DIV_INT 0x00158 +#define CLK_SDIO_TIMER_SEL 0x00160 + +#define CLK_SDIO_ALT_SRC_CTRL 0x00164 +#define CLK_SDIO_ALT_SRC_DIV_INT 0x00168 +#define CLK_SDIO_ALT_SRC_SEL 0x00170 + +#define CLK_GP0_CTRL 0x00174 +#define CLK_GP0_DIV_INT 0x00178 +#define CLK_GP0_DIV_FRAC 0x0017c +#define CLK_GP0_SEL 0x00180 + +#define CLK_GP1_CTRL 0x00184 +#define CLK_GP1_DIV_INT 0x00188 +#define CLK_GP1_DIV_FRAC 0x0018c +#define CLK_GP1_SEL 0x00190 + +#define CLK_GP2_CTRL 0x00194 +#define CLK_GP2_DIV_INT 0x00198 +#define CLK_GP2_DIV_FRAC 0x0019c +#define CLK_GP2_SEL 0x001a0 + +#define CLK_GP3_CTRL 0x001a4 +#define CLK_GP3_DIV_INT 0x001a8 +#define CLK_GP3_DIV_FRAC 0x001ac +#define CLK_GP3_SEL 0x001b0 + +#define CLK_GP4_CTRL 0x001b4 +#define CLK_GP4_DIV_INT 0x001b8 +#define CLK_GP4_DIV_FRAC 0x001bc +#define CLK_GP4_SEL 0x001c0 + +#define CLK_GP5_CTRL 0x001c4 +#define CLK_GP5_DIV_INT 0x001c8 +#define CLK_GP5_DIV_FRAC 0x001cc +#define CLK_GP5_SEL 0x001d0 + +#define CLK_SYS_RESUS_CTRL 0x0020c + +#define CLK_SLOW_SYS_RESUS_CTRL 0x00214 + +#define FC0_REF_KHZ 0x0021c +#define FC0_MIN_KHZ 0x00220 +#define FC0_MAX_KHZ 0x00224 +#define FC0_DELAY 0x00228 +#define FC0_INTERVAL 0x0022c +#define FC0_SRC 0x00230 +#define FC0_STATUS 0x00234 +#define FC0_RESULT 0x00238 +#define FC_SIZE 0x20 +#define FC_COUNT 8 +#define FC_NUM(idx, off) ((idx) * 32 + (off)) + +#define AUX_SEL 1 + +#define VIDEO_CLOCKS_OFFSET 0x4000 +#define VIDEO_CLK_VEC_CTRL (VIDEO_CLOCKS_OFFSET + 0x0000) +#define VIDEO_CLK_VEC_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0004) +#define VIDEO_CLK_VEC_SEL (VIDEO_CLOCKS_OFFSET + 0x000c) +#define VIDEO_CLK_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0010) +#define VIDEO_CLK_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0014) +#define VIDEO_CLK_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x001c) +#define VIDEO_CLK_MIPI0_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0020) +#define VIDEO_CLK_MIPI0_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0024) +#define VIDEO_CLK_MIPI0_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0028) +#define VIDEO_CLK_MIPI0_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x002c) +#define VIDEO_CLK_MIPI1_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0030) +#define VIDEO_CLK_MIPI1_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0034) +#define VIDEO_CLK_MIPI1_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0038) +#define VIDEO_CLK_MIPI1_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x003c) + +#define DIV_INT_8BIT_MAX 0x000000ffu /* max divide for most clocks */ +#define DIV_INT_16BIT_MAX 0x0000ffffu /* max divide for GPx, PWM */ +#define DIV_INT_24BIT_MAX 0x00ffffffu /* max divide for CLK_SYS */ + +#define FC0_STATUS_DONE BIT(4) +#define FC0_STATUS_RUNNING BIT(8) +#define FC0_RESULT_FRAC_SHIFT 5 + +#define PLL_PRIM_DIV1_SHIFT 16 +#define PLL_PRIM_DIV1_MASK 0x00070000 +#define PLL_PRIM_DIV2_SHIFT 12 +#define PLL_PRIM_DIV2_MASK 0x00007000 + +#define PLL_SEC_DIV_SHIFT 8 +#define PLL_SEC_DIV_WIDTH 5 +#define PLL_SEC_DIV_MASK 0x00001f00 + +#define PLL_CS_LOCK BIT(31) +#define PLL_CS_REFDIV_SHIFT 0 + +#define PLL_PWR_PD BIT(0) +#define PLL_PWR_DACPD BIT(1) +#define PLL_PWR_DSMPD BIT(2) +#define PLL_PWR_POSTDIVPD BIT(3) +#define PLL_PWR_4PHASEPD BIT(4) +#define PLL_PWR_VCOPD BIT(5) +#define PLL_PWR_MASK 0x0000003f + +#define PLL_SEC_RST BIT(16) +#define PLL_SEC_IMPL BIT(31) + +/* PLL phase output for both PRI and SEC */ +#define PLL_PH_EN BIT(4) +#define PLL_PH_PHASE_SHIFT 0 + +#define RP1_PLL_PHASE_0 0 +#define RP1_PLL_PHASE_90 1 +#define RP1_PLL_PHASE_180 2 +#define RP1_PLL_PHASE_270 3 + +/* Clock fields for all clocks */ +#define CLK_CTRL_ENABLE BIT(11) +#define CLK_CTRL_AUXSRC_MASK 0x000003e0 +#define CLK_CTRL_AUXSRC_SHIFT 5 +#define CLK_CTRL_SRC_SHIFT 0 +#define CLK_DIV_FRAC_BITS 16 + +#define KHz 1000 +#define MHz (KHz * KHz) +#define LOCK_TIMEOUT_NS 100000000 +#define FC_TIMEOUT_NS 100000000 + +#define MAX_CLK_PARENTS 8 + +#define MEASURE_CLOCK_RATE +const char * const fc0_ref_clk_name = "clk_slow_sys"; + +#define ABS_DIFF(a, b) ((a) > (b) ? (a) - (b) : (b) - (a)) +#define DIV_U64_NEAREST(a, b) div_u64(((a) + ((b) >> 1)), (b)) + +/* + * Names of the reference clock for the pll cores. This name must match + * the DT reference clock-output-name. + */ +static const char *const ref_clock = "xosc"; + +/* + * Secondary PLL channel output divider table. + * Divider values range from 8 to 19. + * Invalid values default to 19 + */ +static const struct clk_div_table pll_sec_div_table[] = { + { 0x00, 19 }, + { 0x01, 19 }, + { 0x02, 19 }, + { 0x03, 19 }, + { 0x04, 19 }, + { 0x05, 19 }, + { 0x06, 19 }, + { 0x07, 19 }, + { 0x08, 8 }, + { 0x09, 9 }, + { 0x0a, 10 }, + { 0x0b, 11 }, + { 0x0c, 12 }, + { 0x0d, 13 }, + { 0x0e, 14 }, + { 0x0f, 15 }, + { 0x10, 16 }, + { 0x11, 17 }, + { 0x12, 18 }, + { 0x13, 19 }, + { 0x14, 19 }, + { 0x15, 19 }, + { 0x16, 19 }, + { 0x17, 19 }, + { 0x18, 19 }, + { 0x19, 19 }, + { 0x1a, 19 }, + { 0x1b, 19 }, + { 0x1c, 19 }, + { 0x1d, 19 }, + { 0x1e, 19 }, + { 0x1f, 19 }, + { 0 } +}; + +struct rp1_clockman { + struct device *dev; + void __iomem *regs; + spinlock_t regs_lock; /* spinlock for all clocks */ + + /* Must be last */ + struct clk_hw_onecell_data onecell; +}; + +struct rp1_pll_core_data { + const char *name; + u32 cs_reg; + u32 pwr_reg; + u32 fbdiv_int_reg; + u32 fbdiv_frac_reg; + unsigned long flags; + u32 fc0_src; +}; + +struct rp1_pll_data { + const char *name; + const char *source_pll; + u32 ctrl_reg; + unsigned long flags; + u32 fc0_src; +}; + +struct rp1_pll_ph_data { + const char *name; + const char *source_pll; + unsigned int phase; + unsigned int fixed_divider; + u32 ph_reg; + unsigned long flags; + u32 fc0_src; +}; + +struct rp1_pll_divider_data { + const char *name; + const char *source_pll; + u32 sec_reg; + unsigned long flags; + u32 fc0_src; +}; + +struct rp1_clock_data { + const char *name; + const char *const parents[MAX_CLK_PARENTS]; + int num_std_parents; + int num_aux_parents; + unsigned long flags; + u32 clk_src_mask; + u32 ctrl_reg; + u32 div_int_reg; + u32 div_frac_reg; + u32 sel_reg; + u32 div_int_max; + u32 fc0_src; +}; + +struct rp1_pll_core { + struct clk_hw hw; + struct rp1_clockman *clockman; + const struct rp1_pll_core_data *data; + unsigned long cached_rate; +}; + +struct rp1_pll { + struct clk_hw hw; + struct clk_divider div; + struct rp1_clockman *clockman; + const struct rp1_pll_data *data; + unsigned long cached_rate; +}; + +struct rp1_pll_ph { + struct clk_hw hw; + struct rp1_clockman *clockman; + const struct rp1_pll_ph_data *data; +}; + +struct rp1_clock { + struct clk_hw hw; + struct rp1_clockman *clockman; + const struct rp1_clock_data *data; + unsigned long cached_rate; +}; + +static void rp1_debugfs_regset(struct rp1_clockman *clockman, u32 base, + const struct debugfs_reg32 *regs, + size_t nregs, struct dentry *dentry) +{ + struct debugfs_regset32 *regset; + + regset = devm_kzalloc(clockman->dev, sizeof(*regset), GFP_KERNEL); + if (!regset) + return; + + regset->regs = regs; + regset->nregs = nregs; + regset->base = clockman->regs + base; + + debugfs_create_regset32("regdump", 0444, dentry, regset); +} + +static inline u32 set_register_field(u32 reg, u32 val, u32 mask, u32 shift) +{ + reg &= ~mask; + reg |= (val << shift) & mask; + return reg; +} + +static inline +void clockman_write(struct rp1_clockman *clockman, u32 reg, u32 val) +{ + writel(val, clockman->regs + reg); +} + +static inline u32 clockman_read(struct rp1_clockman *clockman, u32 reg) +{ + return readl(clockman->regs + reg); +} + +#ifdef MEASURE_CLOCK_RATE +static unsigned long clockman_measure_clock(struct rp1_clockman *clockman, + const char *clk_name, + unsigned int fc0_src) +{ + struct clk *ref_clk = __clk_lookup(fc0_ref_clk_name); + unsigned long result; + ktime_t timeout; + unsigned int fc_idx, fc_offset, fc_src; + + fc_idx = fc0_src / 32; + fc_src = fc0_src % 32; + + /* fc_src == 0 is invalid. */ + if (!fc_src || fc_idx >= FC_COUNT) + return 0; + + fc_offset = fc_idx * FC_SIZE; + + /* Ensure the frequency counter is idle. */ + timeout = ktime_add_ns(ktime_get(), FC_TIMEOUT_NS); + while (clockman_read(clockman, fc_offset + FC0_STATUS) & FC0_STATUS_RUNNING) { + if (ktime_after(ktime_get(), timeout)) { + dev_err(clockman->dev, "%s: FC0 busy timeout\n", + clk_name); + return 0; + } + cpu_relax(); + } + + spin_lock(&clockman->regs_lock); + clockman_write(clockman, fc_offset + FC0_REF_KHZ, + clk_get_rate(ref_clk) / KHz); + clockman_write(clockman, fc_offset + FC0_MIN_KHZ, 0); + clockman_write(clockman, fc_offset + FC0_MAX_KHZ, 0x1ffffff); + clockman_write(clockman, fc_offset + FC0_INTERVAL, 8); + clockman_write(clockman, fc_offset + FC0_DELAY, 7); + clockman_write(clockman, fc_offset + FC0_SRC, fc_src); + spin_unlock(&clockman->regs_lock); + + /* Ensure the frequency counter is idle. */ + timeout = ktime_add_ns(ktime_get(), FC_TIMEOUT_NS); + while (!(clockman_read(clockman, fc_offset + FC0_STATUS) & FC0_STATUS_DONE)) { + if (ktime_after(ktime_get(), timeout)) { + dev_err(clockman->dev, "%s: FC0 wait timeout\n", + clk_name); + return 0; + } + cpu_relax(); + } + + result = clockman_read(clockman, fc_offset + FC0_RESULT); + + /* Disable FC0 */ + spin_lock(&clockman->regs_lock); + clockman_write(clockman, fc_offset + FC0_SRC, 0); + spin_unlock(&clockman->regs_lock); + + return result; +} +#endif + +static int rp1_pll_core_is_on(struct clk_hw *hw) +{ + struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw); + struct rp1_clockman *clockman = pll_core->clockman; + const struct rp1_pll_core_data *data = pll_core->data; + u32 pwr = clockman_read(clockman, data->pwr_reg); + + return (pwr & PLL_PWR_PD) || (pwr & PLL_PWR_POSTDIVPD); +} + +static int rp1_pll_core_on(struct clk_hw *hw) +{ + struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw); + struct rp1_clockman *clockman = pll_core->clockman; + const struct rp1_pll_core_data *data = pll_core->data; + u32 fbdiv_frac; + ktime_t timeout; + + spin_lock(&clockman->regs_lock); + + if (!(clockman_read(clockman, data->cs_reg) & PLL_CS_LOCK)) { + /* Reset to a known state. */ + clockman_write(clockman, data->pwr_reg, PLL_PWR_MASK); + clockman_write(clockman, data->fbdiv_int_reg, 20); + clockman_write(clockman, data->fbdiv_frac_reg, 0); + clockman_write(clockman, data->cs_reg, 1 << PLL_CS_REFDIV_SHIFT); + } + + /* Come out of reset. */ + fbdiv_frac = clockman_read(clockman, data->fbdiv_frac_reg); + clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD); + spin_unlock(&clockman->regs_lock); + + /* Wait for the PLL to lock. */ + timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); + while (!(clockman_read(clockman, data->cs_reg) & PLL_CS_LOCK)) { + if (ktime_after(ktime_get(), timeout)) { + dev_err(clockman->dev, "%s: can't lock PLL\n", + clk_hw_get_name(hw)); + return -ETIMEDOUT; + } + cpu_relax(); + } + + return 0; +} + +static void rp1_pll_core_off(struct clk_hw *hw) +{ + struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw); + struct rp1_clockman *clockman = pll_core->clockman; + const struct rp1_pll_core_data *data = pll_core->data; + + spin_lock(&clockman->regs_lock); + clockman_write(clockman, data->pwr_reg, 0); + spin_unlock(&clockman->regs_lock); +} + +static inline unsigned long get_pll_core_divider(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate, + u32 *div_int, u32 *div_frac) +{ + unsigned long calc_rate; + u32 fbdiv_int, fbdiv_frac; + u64 div_fp64; /* 32.32 fixed point fraction. */ + + /* Factor of reference clock to VCO frequency. */ + div_fp64 = (u64)(rate) << 32; + div_fp64 = DIV_U64_NEAREST(div_fp64, parent_rate); + + /* Round the fractional component at 24 bits. */ + div_fp64 += 1 << (32 - 24 - 1); + + fbdiv_int = div_fp64 >> 32; + fbdiv_frac = (div_fp64 >> (32 - 24)) & 0xffffff; + + calc_rate = + ((u64)parent_rate * (((u64)fbdiv_int << 24) + fbdiv_frac) + (1 << 23)) >> 24; + + *div_int = fbdiv_int; + *div_frac = fbdiv_frac; + + return calc_rate; +} + +static int rp1_pll_core_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw); + struct rp1_clockman *clockman = pll_core->clockman; + const struct rp1_pll_core_data *data = pll_core->data; + unsigned long calc_rate; + u32 fbdiv_int, fbdiv_frac; + + // todo: is this needed?? + //rp1_pll_off(hw); + + /* Disable dividers to start with. */ + spin_lock(&clockman->regs_lock); + clockman_write(clockman, data->fbdiv_int_reg, 0); + clockman_write(clockman, data->fbdiv_frac_reg, 0); + spin_unlock(&clockman->regs_lock); + + calc_rate = get_pll_core_divider(hw, rate, parent_rate, + &fbdiv_int, &fbdiv_frac); + + spin_lock(&clockman->regs_lock); + clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD); + clockman_write(clockman, data->fbdiv_int_reg, fbdiv_int); + clockman_write(clockman, data->fbdiv_frac_reg, fbdiv_frac); + spin_unlock(&clockman->regs_lock); + + /* Check that reference frequency is no greater than VCO / 16. */ + BUG_ON(parent_rate > (rate / 16)); + + pll_core->cached_rate = calc_rate; + + spin_lock(&clockman->regs_lock); + /* Don't need to divide ref unless parent_rate > (output freq / 16) */ + clockman_write(clockman, data->cs_reg, + clockman_read(clockman, data->cs_reg) | + (1 << PLL_CS_REFDIV_SHIFT)); + spin_unlock(&clockman->regs_lock); + + return 0; +} + +static unsigned long rp1_pll_core_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw); + struct rp1_clockman *clockman = pll_core->clockman; + const struct rp1_pll_core_data *data = pll_core->data; + u32 fbdiv_int, fbdiv_frac; + unsigned long calc_rate; + + fbdiv_int = clockman_read(clockman, data->fbdiv_int_reg); + fbdiv_frac = clockman_read(clockman, data->fbdiv_frac_reg); + calc_rate = + ((u64)parent_rate * (((u64)fbdiv_int << 24) + fbdiv_frac) + (1 << 23)) >> 24; + + return calc_rate; +} + +static long rp1_pll_core_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + u32 fbdiv_int, fbdiv_frac; + long calc_rate; + + calc_rate = get_pll_core_divider(hw, rate, *parent_rate, + &fbdiv_int, &fbdiv_frac); + return calc_rate; +} + +static void rp1_pll_core_debug_init(struct clk_hw *hw, struct dentry *dentry) +{ + struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw); + struct rp1_clockman *clockman = pll_core->clockman; + const struct rp1_pll_core_data *data = pll_core->data; + struct debugfs_reg32 *regs; + + regs = devm_kcalloc(clockman->dev, 4, sizeof(*regs), GFP_KERNEL); + if (!regs) + return; + + regs[0].name = "cs"; + regs[0].offset = data->cs_reg; + regs[1].name = "pwr"; + regs[1].offset = data->pwr_reg; + regs[2].name = "fbdiv_int"; + regs[2].offset = data->fbdiv_int_reg; + regs[3].name = "fbdiv_frac"; + regs[3].offset = data->fbdiv_frac_reg; + + rp1_debugfs_regset(clockman, 0, regs, 4, dentry); +} + +static void get_pll_prim_dividers(unsigned long rate, unsigned long parent_rate, + u32 *divider1, u32 *divider2) +{ + unsigned int div1, div2; + unsigned int best_div1 = 7, best_div2 = 7; + unsigned long best_rate_diff = + ABS_DIFF(DIV_ROUND_CLOSEST(parent_rate, best_div1 * best_div2), rate); + long rate_diff, calc_rate; + + for (div1 = 1; div1 <= 7; div1++) { + for (div2 = 1; div2 <= div1; div2++) { + calc_rate = DIV_ROUND_CLOSEST(parent_rate, div1 * div2); + rate_diff = ABS_DIFF(calc_rate, rate); + + if (calc_rate == rate) { + best_div1 = div1; + best_div2 = div2; + goto done; + } else if (rate_diff < best_rate_diff) { + best_div1 = div1; + best_div2 = div2; + best_rate_diff = rate_diff; + } + } + } + +done: + *divider1 = best_div1; + *divider2 = best_div2; +} + +static int rp1_pll_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + struct rp1_pll *pll = container_of(hw, struct rp1_pll, hw); + struct rp1_clockman *clockman = pll->clockman; + const struct rp1_pll_data *data = pll->data; + u32 prim, prim_div1, prim_div2; + + get_pll_prim_dividers(rate, parent_rate, &prim_div1, &prim_div2); + + spin_lock(&clockman->regs_lock); + prim = clockman_read(clockman, data->ctrl_reg); + prim = set_register_field(prim, prim_div1, PLL_PRIM_DIV1_MASK, + PLL_PRIM_DIV1_SHIFT); + prim = set_register_field(prim, prim_div2, PLL_PRIM_DIV2_MASK, + PLL_PRIM_DIV2_SHIFT); + clockman_write(clockman, data->ctrl_reg, prim); + spin_unlock(&clockman->regs_lock); + +#ifdef MEASURE_CLOCK_RATE + clockman_measure_clock(clockman, data->name, data->fc0_src); +#endif + return 0; +} + +static unsigned long rp1_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rp1_pll *pll = container_of(hw, struct rp1_pll, hw); + struct rp1_clockman *clockman = pll->clockman; + const struct rp1_pll_data *data = pll->data; + u32 prim, prim_div1, prim_div2; + + prim = clockman_read(clockman, data->ctrl_reg); + prim_div1 = (prim & PLL_PRIM_DIV1_MASK) >> PLL_PRIM_DIV1_SHIFT; + prim_div2 = (prim & PLL_PRIM_DIV2_MASK) >> PLL_PRIM_DIV2_SHIFT; + + if (!prim_div1 || !prim_div2) { + dev_err(clockman->dev, "%s: (%s) zero divider value\n", + __func__, data->name); + return 0; + } + + return DIV_ROUND_CLOSEST(parent_rate, prim_div1 * prim_div2); +} + +static long rp1_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + u32 div1, div2; + + get_pll_prim_dividers(rate, *parent_rate, &div1, &div2); + + return DIV_ROUND_CLOSEST(*parent_rate, div1 * div2); +} + +static void rp1_pll_debug_init(struct clk_hw *hw, + struct dentry *dentry) +{ + struct rp1_pll *pll = container_of(hw, struct rp1_pll, hw); + struct rp1_clockman *clockman = pll->clockman; + const struct rp1_pll_data *data = pll->data; + struct debugfs_reg32 *regs; + + regs = devm_kcalloc(clockman->dev, 1, sizeof(*regs), GFP_KERNEL); + if (!regs) + return; + + regs[0].name = "prim"; + regs[0].offset = data->ctrl_reg; + + rp1_debugfs_regset(clockman, 0, regs, 1, dentry); +} + +static int rp1_pll_ph_is_on(struct clk_hw *hw) +{ + struct rp1_pll_ph *pll = container_of(hw, struct rp1_pll_ph, hw); + struct rp1_clockman *clockman = pll->clockman; + const struct rp1_pll_ph_data *data = pll->data; + + return !!(clockman_read(clockman, data->ph_reg) & PLL_PH_EN); +} + +static int rp1_pll_ph_on(struct clk_hw *hw) +{ + struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw); + struct rp1_clockman *clockman = pll_ph->clockman; + const struct rp1_pll_ph_data *data = pll_ph->data; + u32 ph_reg; + + /* todo: ensure pri/sec is enabled! */ + spin_lock(&clockman->regs_lock); + ph_reg = clockman_read(clockman, data->ph_reg); + ph_reg |= data->phase << PLL_PH_PHASE_SHIFT; + ph_reg |= PLL_PH_EN; + clockman_write(clockman, data->ph_reg, ph_reg); + spin_unlock(&clockman->regs_lock); + +#ifdef MEASURE_CLOCK_RATE + clockman_measure_clock(clockman, data->name, data->fc0_src); +#endif + return 0; +} + +static void rp1_pll_ph_off(struct clk_hw *hw) +{ + struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw); + struct rp1_clockman *clockman = pll_ph->clockman; + const struct rp1_pll_ph_data *data = pll_ph->data; + + spin_lock(&clockman->regs_lock); + clockman_write(clockman, data->ph_reg, + clockman_read(clockman, data->ph_reg) & ~PLL_PH_EN); + spin_unlock(&clockman->regs_lock); +} + +static int rp1_pll_ph_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw); + const struct rp1_pll_ph_data *data = pll_ph->data; + struct rp1_clockman *clockman = pll_ph->clockman; + + /* Nothing really to do here! */ + WARN_ON(data->fixed_divider != 1 && data->fixed_divider != 2); + WARN_ON(rate != parent_rate / data->fixed_divider); + +#ifdef MEASURE_CLOCK_RATE + if (rp1_pll_ph_is_on(hw)) + clockman_measure_clock(clockman, data->name, data->fc0_src); +#endif + return 0; +} + +static unsigned long rp1_pll_ph_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw); + const struct rp1_pll_ph_data *data = pll_ph->data; + + return parent_rate / data->fixed_divider; +} + +static long rp1_pll_ph_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw); + const struct rp1_pll_ph_data *data = pll_ph->data; + + return *parent_rate / data->fixed_divider; +} + +static void rp1_pll_ph_debug_init(struct clk_hw *hw, + struct dentry *dentry) +{ + struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw); + const struct rp1_pll_ph_data *data = pll_ph->data; + struct rp1_clockman *clockman = pll_ph->clockman; + struct debugfs_reg32 *regs; + + regs = devm_kcalloc(clockman->dev, 1, sizeof(*regs), GFP_KERNEL); + if (!regs) + return; + + regs[0].name = "ph_reg"; + regs[0].offset = data->ph_reg; + + rp1_debugfs_regset(clockman, 0, regs, 1, dentry); +} + +static int rp1_pll_divider_is_on(struct clk_hw *hw) +{ + struct rp1_pll *divider = container_of(hw, struct rp1_pll, div.hw); + struct rp1_clockman *clockman = divider->clockman; + const struct rp1_pll_data *data = divider->data; + + return !(clockman_read(clockman, data->ctrl_reg) & PLL_SEC_RST); +} + +static int rp1_pll_divider_on(struct clk_hw *hw) +{ + struct rp1_pll *divider = container_of(hw, struct rp1_pll, div.hw); + struct rp1_clockman *clockman = divider->clockman; + const struct rp1_pll_data *data = divider->data; + + spin_lock(&clockman->regs_lock); + /* Check the implementation bit is set! */ + WARN_ON(!(clockman_read(clockman, data->ctrl_reg) & PLL_SEC_IMPL)); + clockman_write(clockman, data->ctrl_reg, + clockman_read(clockman, data->ctrl_reg) & ~PLL_SEC_RST); + spin_unlock(&clockman->regs_lock); + +#ifdef MEASURE_CLOCK_RATE + clockman_measure_clock(clockman, data->name, data->fc0_src); +#endif + return 0; +} + +static void rp1_pll_divider_off(struct clk_hw *hw) +{ + struct rp1_pll *divider = container_of(hw, struct rp1_pll, div.hw); + struct rp1_clockman *clockman = divider->clockman; + const struct rp1_pll_data *data = divider->data; + + spin_lock(&clockman->regs_lock); + clockman_write(clockman, data->ctrl_reg, PLL_SEC_RST); + spin_unlock(&clockman->regs_lock); +} + +static int rp1_pll_divider_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct rp1_pll *divider = container_of(hw, struct rp1_pll, div.hw); + struct rp1_clockman *clockman = divider->clockman; + const struct rp1_pll_data *data = divider->data; + u32 div, sec; + + div = DIV_ROUND_UP_ULL(parent_rate, rate); + div = clamp(div, 8u, 19u); + + spin_lock(&clockman->regs_lock); + sec = clockman_read(clockman, data->ctrl_reg); + sec = set_register_field(sec, div, PLL_SEC_DIV_MASK, PLL_SEC_DIV_SHIFT); + + /* Must keep the divider in reset to change the value. */ + sec |= PLL_SEC_RST; + clockman_write(clockman, data->ctrl_reg, sec); + + // todo: must sleep 10 pll vco cycles + sec &= ~PLL_SEC_RST; + clockman_write(clockman, data->ctrl_reg, sec); + spin_unlock(&clockman->regs_lock); + +#ifdef MEASURE_CLOCK_RATE + if (rp1_pll_divider_is_on(hw)) + clockman_measure_clock(clockman, data->name, data->fc0_src); +#endif + return 0; +} + +static unsigned long rp1_pll_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return clk_divider_ops.recalc_rate(hw, parent_rate); +} + +static long rp1_pll_divider_round_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *parent_rate) +{ + return clk_divider_ops.round_rate(hw, rate, parent_rate); +} + +static void rp1_pll_divider_debug_init(struct clk_hw *hw, struct dentry *dentry) +{ + struct rp1_pll *divider = container_of(hw, struct rp1_pll, div.hw); + struct rp1_clockman *clockman = divider->clockman; + const struct rp1_pll_data *data = divider->data; + struct debugfs_reg32 *regs; + + regs = devm_kcalloc(clockman->dev, 1, sizeof(*regs), GFP_KERNEL); + if (!regs) + return; + + regs[0].name = "sec"; + regs[0].offset = data->ctrl_reg; + + rp1_debugfs_regset(clockman, 0, regs, 1, dentry); +} + +static int rp1_clock_is_on(struct clk_hw *hw) +{ + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); + struct rp1_clockman *clockman = clock->clockman; + const struct rp1_clock_data *data = clock->data; + + return !!(clockman_read(clockman, data->ctrl_reg) & CLK_CTRL_ENABLE); +} + +static unsigned long rp1_clock_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); + struct rp1_clockman *clockman = clock->clockman; + const struct rp1_clock_data *data = clock->data; + u64 calc_rate; + u64 div; + + u32 frac; + + div = clockman_read(clockman, data->div_int_reg); + frac = (data->div_frac_reg != 0) ? + clockman_read(clockman, data->div_frac_reg) : 0; + + /* If the integer portion of the divider is 0, treat it as 2^16 */ + if (!div) + div = 1 << 16; + + div = (div << CLK_DIV_FRAC_BITS) | (frac >> (32 - CLK_DIV_FRAC_BITS)); + + calc_rate = (u64)parent_rate << CLK_DIV_FRAC_BITS; + calc_rate = div64_u64(calc_rate, div); + + return calc_rate; +} + +static int rp1_clock_on(struct clk_hw *hw) +{ + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); + struct rp1_clockman *clockman = clock->clockman; + const struct rp1_clock_data *data = clock->data; + + spin_lock(&clockman->regs_lock); + clockman_write(clockman, data->ctrl_reg, + clockman_read(clockman, data->ctrl_reg) | CLK_CTRL_ENABLE); + spin_unlock(&clockman->regs_lock); + +#ifdef MEASURE_CLOCK_RATE + clockman_measure_clock(clockman, data->name, data->fc0_src); +#endif + return 0; +} + +static void rp1_clock_off(struct clk_hw *hw) +{ + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); + struct rp1_clockman *clockman = clock->clockman; + const struct rp1_clock_data *data = clock->data; + + spin_lock(&clockman->regs_lock); + clockman_write(clockman, data->ctrl_reg, + clockman_read(clockman, data->ctrl_reg) & ~CLK_CTRL_ENABLE); + spin_unlock(&clockman->regs_lock); +} + +static u32 rp1_clock_choose_div(unsigned long rate, unsigned long parent_rate, + const struct rp1_clock_data *data) +{ + u64 div; + + /* + * Due to earlier rounding, calculated parent_rate may differ from + * expected value. Don't fail on a small discrepancy near unity divide. + */ + if (!rate || rate > parent_rate + (parent_rate >> CLK_DIV_FRAC_BITS)) + return 0; + + /* + * Always express div in fixed-point format for fractional division; + * If no fractional divider is present, the fraction part will be zero. + */ + if (data->div_frac_reg) { + div = (u64)parent_rate << CLK_DIV_FRAC_BITS; + div = DIV_U64_NEAREST(div, rate); + } else { + div = DIV_U64_NEAREST(parent_rate, rate); + div <<= CLK_DIV_FRAC_BITS; + } + + div = clamp(div, + 1ull << CLK_DIV_FRAC_BITS, + (u64)data->div_int_max << CLK_DIV_FRAC_BITS); + + return div; +} + +static u8 rp1_clock_get_parent(struct clk_hw *hw) +{ + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); + struct rp1_clockman *clockman = clock->clockman; + const struct rp1_clock_data *data = clock->data; + u32 sel, ctrl; + u8 parent; + + /* Sel is one-hot, so find the first bit set */ + sel = clockman_read(clockman, data->sel_reg); + parent = ffs(sel) - 1; + + /* sel == 0 implies the parent clock is not enabled yet. */ + if (!sel) { + /* Read the clock src from the CTRL register instead */ + ctrl = clockman_read(clockman, data->ctrl_reg); + parent = (ctrl & data->clk_src_mask) >> CLK_CTRL_SRC_SHIFT; + } + + if (parent >= data->num_std_parents) + parent = AUX_SEL; + + if (parent == AUX_SEL) { + /* + * Clock parent is an auxiliary source, so get the parent from + * the AUXSRC register field. + */ + ctrl = clockman_read(clockman, data->ctrl_reg); + parent = (ctrl & CLK_CTRL_AUXSRC_MASK) >> CLK_CTRL_AUXSRC_SHIFT; + parent += data->num_std_parents; + } + + return parent; +} + +static int rp1_clock_set_parent(struct clk_hw *hw, u8 index) +{ + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); + struct rp1_clockman *clockman = clock->clockman; + const struct rp1_clock_data *data = clock->data; + u32 ctrl, sel; + + spin_lock(&clockman->regs_lock); + ctrl = clockman_read(clockman, data->ctrl_reg); + + if (index >= data->num_std_parents) { + /* This is an aux source request */ + if (index >= data->num_std_parents + data->num_aux_parents) + return -EINVAL; + + /* Select parent from aux list */ + ctrl = set_register_field(ctrl, index - data->num_std_parents, + CLK_CTRL_AUXSRC_MASK, + CLK_CTRL_AUXSRC_SHIFT); + /* Set src to aux list */ + ctrl = set_register_field(ctrl, AUX_SEL, data->clk_src_mask, + CLK_CTRL_SRC_SHIFT); + } else { + ctrl = set_register_field(ctrl, index, data->clk_src_mask, + CLK_CTRL_SRC_SHIFT); + } + + clockman_write(clockman, data->ctrl_reg, ctrl); + spin_unlock(&clockman->regs_lock); + + sel = rp1_clock_get_parent(hw); + WARN(sel != index, "(%s): Parent index req %u returned back %u\n", + data->name, index, sel); + + return 0; +} + +static int rp1_clock_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate, + u8 parent) +{ + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); + struct rp1_clockman *clockman = clock->clockman; + const struct rp1_clock_data *data = clock->data; + u32 div = rp1_clock_choose_div(rate, parent_rate, data); + + WARN(rate > 4000000000ll, "rate is -ve (%d)\n", (int)rate); + + if (WARN(!div, + "clk divider calculated as 0! (%s, rate %ld, parent rate %ld)\n", + data->name, rate, parent_rate)) + div = 1 << CLK_DIV_FRAC_BITS; + + spin_lock(&clockman->regs_lock); + + clockman_write(clockman, data->div_int_reg, div >> CLK_DIV_FRAC_BITS); + if (data->div_frac_reg) + clockman_write(clockman, data->div_frac_reg, div << (32 - CLK_DIV_FRAC_BITS)); + + spin_unlock(&clockman->regs_lock); + + if (parent != 0xff) + rp1_clock_set_parent(hw, parent); + +#ifdef MEASURE_CLOCK_RATE + if (rp1_clock_is_on(hw)) + clockman_measure_clock(clockman, data->name, data->fc0_src); +#endif + return 0; +} + +static int rp1_clock_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return rp1_clock_set_rate_and_parent(hw, rate, parent_rate, 0xff); +} + +static void rp1_clock_choose_div_and_prate(struct clk_hw *hw, + int parent_idx, + unsigned long rate, + unsigned long *prate, + unsigned long *calc_rate) +{ + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); + const struct rp1_clock_data *data = clock->data; + struct clk_hw *parent; + u32 div; + u64 tmp; + + parent = clk_hw_get_parent_by_index(hw, parent_idx); + *prate = clk_hw_get_rate(parent); + div = rp1_clock_choose_div(rate, *prate, data); + + if (!div) { + *calc_rate = 0; + return; + } + + /* Recalculate to account for rounding errors */ + tmp = (u64)*prate << CLK_DIV_FRAC_BITS; + tmp = div_u64(tmp, div); + *calc_rate = tmp; +} + +static int rp1_clock_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_hw *parent, *best_parent = NULL; + unsigned long best_rate = 0; + unsigned long best_prate = 0; + unsigned long best_rate_diff = ULONG_MAX; + unsigned long prate, calc_rate; + size_t i; + + /* + * If the NO_REPARENT flag is set, try to use existing parent. + */ + if ((clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT)) { + i = rp1_clock_get_parent(hw); + parent = clk_hw_get_parent_by_index(hw, i); + if (parent) { + rp1_clock_choose_div_and_prate(hw, i, req->rate, &prate, + &calc_rate); + if (calc_rate > 0) { + req->best_parent_hw = parent; + req->best_parent_rate = prate; + req->rate = calc_rate; + return 0; + } + } + } + + /* + * Select parent clock that results in the closest rate (lower or + * higher) + */ + for (i = 0; i < clk_hw_get_num_parents(hw); i++) { + parent = clk_hw_get_parent_by_index(hw, i); + if (!parent) + continue; + + rp1_clock_choose_div_and_prate(hw, i, req->rate, &prate, + &calc_rate); + + if (ABS_DIFF(calc_rate, req->rate) < best_rate_diff) { + best_parent = parent; + best_prate = prate; + best_rate = calc_rate; + best_rate_diff = ABS_DIFF(calc_rate, req->rate); + + if (best_rate_diff == 0) + break; + } + } + + if (best_rate == 0) + return -EINVAL; + + req->best_parent_hw = best_parent; + req->best_parent_rate = best_prate; + req->rate = best_rate; + + return 0; +} + +static void rp1_clk_debug_init(struct clk_hw *hw, struct dentry *dentry) +{ + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); + struct rp1_clockman *clockman = clock->clockman; + const struct rp1_clock_data *data = clock->data; + struct debugfs_reg32 *regs; + int i; + + regs = devm_kcalloc(clockman->dev, 4, sizeof(*regs), GFP_KERNEL); + if (!regs) + return; + + i = 0; + regs[i].name = "ctrl"; + regs[i++].offset = data->ctrl_reg; + regs[i].name = "div_int"; + regs[i++].offset = data->div_int_reg; + regs[i].name = "div_frac"; + regs[i++].offset = data->div_frac_reg; + regs[i].name = "sel"; + regs[i++].offset = data->sel_reg; + + rp1_debugfs_regset(clockman, 0, regs, i, dentry); +} + +static const struct clk_ops rp1_pll_core_ops = { + .is_prepared = rp1_pll_core_is_on, + .prepare = rp1_pll_core_on, + .unprepare = rp1_pll_core_off, + .set_rate = rp1_pll_core_set_rate, + .recalc_rate = rp1_pll_core_recalc_rate, + .round_rate = rp1_pll_core_round_rate, + .debug_init = rp1_pll_core_debug_init, +}; + +static const struct clk_ops rp1_pll_ops = { + .set_rate = rp1_pll_set_rate, + .recalc_rate = rp1_pll_recalc_rate, + .round_rate = rp1_pll_round_rate, + .debug_init = rp1_pll_debug_init, +}; + +static const struct clk_ops rp1_pll_ph_ops = { + .is_prepared = rp1_pll_ph_is_on, + .prepare = rp1_pll_ph_on, + .unprepare = rp1_pll_ph_off, + .set_rate = rp1_pll_ph_set_rate, + .recalc_rate = rp1_pll_ph_recalc_rate, + .round_rate = rp1_pll_ph_round_rate, + .debug_init = rp1_pll_ph_debug_init, +}; + +static const struct clk_ops rp1_pll_divider_ops = { + .is_prepared = rp1_pll_divider_is_on, + .prepare = rp1_pll_divider_on, + .unprepare = rp1_pll_divider_off, + .set_rate = rp1_pll_divider_set_rate, + .recalc_rate = rp1_pll_divider_recalc_rate, + .round_rate = rp1_pll_divider_round_rate, + .debug_init = rp1_pll_divider_debug_init, +}; + +static const struct clk_ops rp1_clk_ops = { + .is_prepared = rp1_clock_is_on, + .prepare = rp1_clock_on, + .unprepare = rp1_clock_off, + .recalc_rate = rp1_clock_recalc_rate, + .get_parent = rp1_clock_get_parent, + .set_parent = rp1_clock_set_parent, + .set_rate_and_parent = rp1_clock_set_rate_and_parent, + .set_rate = rp1_clock_set_rate, + .determine_rate = rp1_clock_determine_rate, + .debug_init = rp1_clk_debug_init, +}; + +static bool rp1_clk_is_claimed(const char *name); + +static struct clk_hw *rp1_register_pll_core(struct rp1_clockman *clockman, + const void *data) +{ + const struct rp1_pll_core_data *pll_core_data = data; + struct rp1_pll_core *pll_core; + struct clk_init_data init; + int ret; + + memset(&init, 0, sizeof(init)); + + /* All of the PLL cores derive from the external oscillator. */ + init.parent_names = &ref_clock; + init.num_parents = 1; + init.name = pll_core_data->name; + init.ops = &rp1_pll_core_ops; + init.flags = pll_core_data->flags | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL; + + pll_core = kzalloc(sizeof(*pll_core), GFP_KERNEL); + if (!pll_core) + return NULL; + + pll_core->clockman = clockman; + pll_core->data = pll_core_data; + pll_core->hw.init = &init; + + ret = devm_clk_hw_register(clockman->dev, &pll_core->hw); + if (ret) { + kfree(pll_core); + return NULL; + } + + return &pll_core->hw; +} + +static struct clk_hw *rp1_register_pll(struct rp1_clockman *clockman, + const void *data) +{ + const struct rp1_pll_data *pll_data = data; + struct rp1_pll *pll; + struct clk_init_data init; + int ret; + + memset(&init, 0, sizeof(init)); + + init.parent_names = &pll_data->source_pll; + init.num_parents = 1; + init.name = pll_data->name; + init.ops = &rp1_pll_ops; + init.flags = pll_data->flags | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return NULL; + + pll->clockman = clockman; + pll->data = pll_data; + pll->hw.init = &init; + + ret = devm_clk_hw_register(clockman->dev, &pll->hw); + if (ret) { + kfree(pll); + return NULL; + } + + return &pll->hw; +} + +static struct clk_hw *rp1_register_pll_ph(struct rp1_clockman *clockman, + const void *data) +{ + const struct rp1_pll_ph_data *ph_data = data; + struct rp1_pll_ph *ph; + struct clk_init_data init; + int ret; + + memset(&init, 0, sizeof(init)); + + /* All of the PLLs derive from the external oscillator. */ + init.parent_names = &ph_data->source_pll; + init.num_parents = 1; + init.name = ph_data->name; + init.ops = &rp1_pll_ph_ops; + init.flags = ph_data->flags | CLK_IGNORE_UNUSED; + + ph = kzalloc(sizeof(*ph), GFP_KERNEL); + if (!ph) + return NULL; + + ph->clockman = clockman; + ph->data = ph_data; + ph->hw.init = &init; + + ret = devm_clk_hw_register(clockman->dev, &ph->hw); + if (ret) { + kfree(ph); + return NULL; + } + + return &ph->hw; +} + +static struct clk_hw *rp1_register_pll_divider(struct rp1_clockman *clockman, + const void *data) +{ + const struct rp1_pll_data *divider_data = data; + struct rp1_pll *divider; + struct clk_init_data init; + int ret; + + memset(&init, 0, sizeof(init)); + + init.parent_names = ÷r_data->source_pll; + init.num_parents = 1; + init.name = divider_data->name; + init.ops = &rp1_pll_divider_ops; + init.flags = divider_data->flags | CLK_IGNORE_UNUSED; + + divider = devm_kzalloc(clockman->dev, sizeof(*divider), GFP_KERNEL); + if (!divider) + return NULL; + + divider->div.reg = clockman->regs + divider_data->ctrl_reg; + divider->div.shift = PLL_SEC_DIV_SHIFT; + divider->div.width = PLL_SEC_DIV_WIDTH; + divider->div.flags = CLK_DIVIDER_ROUND_CLOSEST; + divider->div.lock = &clockman->regs_lock; + divider->div.hw.init = &init; + divider->div.table = pll_sec_div_table; + + if (!rp1_clk_is_claimed(divider_data->source_pll)) + init.flags |= CLK_IS_CRITICAL; + if (!rp1_clk_is_claimed(divider_data->name)) + divider->div.flags |= CLK_IS_CRITICAL; + + divider->clockman = clockman; + divider->data = divider_data; + + ret = devm_clk_hw_register(clockman->dev, ÷r->div.hw); + if (ret) + return ERR_PTR(ret); + + return ÷r->div.hw; +} + +static struct clk_hw *rp1_register_clock(struct rp1_clockman *clockman, + const void *data) +{ + const struct rp1_clock_data *clock_data = data; + struct rp1_clock *clock; + struct clk_init_data init; + int ret; + + BUG_ON(MAX_CLK_PARENTS < + clock_data->num_std_parents + clock_data->num_aux_parents); + /* There must be a gap for the AUX selector */ + BUG_ON((clock_data->num_std_parents > AUX_SEL) && + strcmp("-", clock_data->parents[AUX_SEL])); + + memset(&init, 0, sizeof(init)); + init.parent_names = clock_data->parents; + init.num_parents = + clock_data->num_std_parents + clock_data->num_aux_parents; + init.name = clock_data->name; + init.flags = clock_data->flags | CLK_IGNORE_UNUSED; + init.ops = &rp1_clk_ops; + + clock = devm_kzalloc(clockman->dev, sizeof(*clock), GFP_KERNEL); + if (!clock) + return NULL; + + clock->clockman = clockman; + clock->data = clock_data; + clock->hw.init = &init; + + ret = devm_clk_hw_register(clockman->dev, &clock->hw); + if (ret) + return ERR_PTR(ret); + + return &clock->hw; +} + +struct rp1_clk_desc { + struct clk_hw *(*clk_register)(struct rp1_clockman *clockman, + const void *data); + const void *data; +}; + +/* Assignment helper macros for different clock types. */ +#define _REGISTER(f, ...) { .clk_register = f, .data = __VA_ARGS__ } + +#define REGISTER_PLL_CORE(...) _REGISTER(&rp1_register_pll_core, \ + &(struct rp1_pll_core_data) \ + {__VA_ARGS__}) + +#define REGISTER_PLL(...) _REGISTER(&rp1_register_pll, \ + &(struct rp1_pll_data) \ + {__VA_ARGS__}) + +#define REGISTER_PLL_PH(...) _REGISTER(&rp1_register_pll_ph, \ + &(struct rp1_pll_ph_data) \ + {__VA_ARGS__}) + +#define REGISTER_PLL_DIV(...) _REGISTER(&rp1_register_pll_divider, \ + &(struct rp1_pll_data) \ + {__VA_ARGS__}) + +#define REGISTER_CLK(...) _REGISTER(&rp1_register_clock, \ + &(struct rp1_clock_data) \ + {__VA_ARGS__}) + +static const struct rp1_clk_desc clk_desc_array[] = { + [RP1_PLL_SYS_CORE] = REGISTER_PLL_CORE( + .name = "pll_sys_core", + .cs_reg = PLL_SYS_CS, + .pwr_reg = PLL_SYS_PWR, + .fbdiv_int_reg = PLL_SYS_FBDIV_INT, + .fbdiv_frac_reg = PLL_SYS_FBDIV_FRAC, + ), + + [RP1_PLL_AUDIO_CORE] = REGISTER_PLL_CORE( + .name = "pll_audio_core", + .cs_reg = PLL_AUDIO_CS, + .pwr_reg = PLL_AUDIO_PWR, + .fbdiv_int_reg = PLL_AUDIO_FBDIV_INT, + .fbdiv_frac_reg = PLL_AUDIO_FBDIV_FRAC, + ), + + [RP1_PLL_VIDEO_CORE] = REGISTER_PLL_CORE( + .name = "pll_video_core", + .cs_reg = PLL_VIDEO_CS, + .pwr_reg = PLL_VIDEO_PWR, + .fbdiv_int_reg = PLL_VIDEO_FBDIV_INT, + .fbdiv_frac_reg = PLL_VIDEO_FBDIV_FRAC, + ), + + [RP1_PLL_SYS] = REGISTER_PLL( + .name = "pll_sys", + .source_pll = "pll_sys_core", + .ctrl_reg = PLL_SYS_PRIM, + .fc0_src = FC_NUM(0, 2), + ), + + [RP1_PLL_AUDIO] = REGISTER_PLL( + .name = "pll_audio", + .source_pll = "pll_audio_core", + .ctrl_reg = PLL_AUDIO_PRIM, + .fc0_src = FC_NUM(4, 2), + ), + + [RP1_PLL_VIDEO] = REGISTER_PLL( + .name = "pll_video", + .source_pll = "pll_video_core", + .ctrl_reg = PLL_VIDEO_PRIM, + .fc0_src = FC_NUM(3, 2), + ), + + [RP1_PLL_SYS_PRI_PH] = REGISTER_PLL_PH( + .name = "pll_sys_pri_ph", + .source_pll = "pll_sys", + .ph_reg = PLL_SYS_PRIM, + .fixed_divider = 2, + .phase = RP1_PLL_PHASE_0, + .fc0_src = FC_NUM(1, 2), + ), + + [RP1_PLL_AUDIO_PRI_PH] = REGISTER_PLL_PH( + .name = "pll_audio_pri_ph", + .source_pll = "pll_audio", + .ph_reg = PLL_AUDIO_PRIM, + .fixed_divider = 2, + .phase = RP1_PLL_PHASE_0, + .fc0_src = FC_NUM(5, 1), + ), + + [RP1_PLL_SYS_SEC] = REGISTER_PLL_DIV( + .name = "pll_sys_sec", + .source_pll = "pll_sys_core", + .ctrl_reg = PLL_SYS_SEC, + .fc0_src = FC_NUM(2, 2), + ), + + [RP1_PLL_AUDIO_SEC] = REGISTER_PLL_DIV( + .name = "pll_audio_sec", + .source_pll = "pll_audio_core", + .ctrl_reg = PLL_AUDIO_SEC, + .fc0_src = FC_NUM(6, 2), + ), + + [RP1_PLL_VIDEO_SEC] = REGISTER_PLL_DIV( + .name = "pll_video_sec", + .source_pll = "pll_video_core", + .ctrl_reg = PLL_VIDEO_SEC, + .fc0_src = FC_NUM(5, 3), + ), + + [RP1_CLK_SYS] = REGISTER_CLK( + .name = "clk_sys", + .parents = {"xosc", "-", "pll_sys"}, + .num_std_parents = 3, + .num_aux_parents = 0, + .ctrl_reg = CLK_SYS_CTRL, + .div_int_reg = CLK_SYS_DIV_INT, + .sel_reg = CLK_SYS_SEL, + .div_int_max = DIV_INT_24BIT_MAX, + .fc0_src = FC_NUM(0, 4), + .clk_src_mask = 0x3, + ), + + [RP1_CLK_SLOW_SYS] = REGISTER_CLK( + .name = "clk_slow_sys", + .parents = {"xosc"}, + .num_std_parents = 1, + .num_aux_parents = 0, + .ctrl_reg = CLK_SLOW_SYS_CTRL, + .div_int_reg = CLK_SLOW_SYS_DIV_INT, + .sel_reg = CLK_SLOW_SYS_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(1, 4), + .clk_src_mask = 0x1, + ), + + [RP1_CLK_UART] = REGISTER_CLK( + .name = "clk_uart", + .parents = {"pll_sys_pri_ph", + "pll_video", + "xosc"}, + .num_std_parents = 0, + .num_aux_parents = 3, + .ctrl_reg = CLK_UART_CTRL, + .div_int_reg = CLK_UART_DIV_INT, + .sel_reg = CLK_UART_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(6, 7), + ), + + [RP1_CLK_ETH] = REGISTER_CLK( + .name = "clk_eth", + .parents = {"-"}, + .num_std_parents = 1, + .num_aux_parents = 0, + .ctrl_reg = CLK_ETH_CTRL, + .div_int_reg = CLK_ETH_DIV_INT, + .sel_reg = CLK_ETH_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(4, 6), + ), + + [RP1_CLK_PWM0] = REGISTER_CLK( + .name = "clk_pwm0", + .parents = {"pll_audio_pri_ph", + "pll_video_sec", + "xosc"}, + .num_std_parents = 0, + .num_aux_parents = 3, + .ctrl_reg = CLK_PWM0_CTRL, + .div_int_reg = CLK_PWM0_DIV_INT, + .div_frac_reg = CLK_PWM0_DIV_FRAC, + .sel_reg = CLK_PWM0_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .fc0_src = FC_NUM(0, 5), + ), + + [RP1_CLK_PWM1] = REGISTER_CLK( + .name = "clk_pwm1", + .parents = {"pll_audio_pri_ph", + "pll_video_sec", + "xosc"}, + .num_std_parents = 0, + .num_aux_parents = 3, + .ctrl_reg = CLK_PWM1_CTRL, + .div_int_reg = CLK_PWM1_DIV_INT, + .div_frac_reg = CLK_PWM1_DIV_FRAC, + .sel_reg = CLK_PWM1_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .fc0_src = FC_NUM(1, 5), + ), + + [RP1_CLK_AUDIO_IN] = REGISTER_CLK( + .name = "clk_audio_in", + .parents = {"-"}, + .num_std_parents = 1, + .num_aux_parents = 0, + .ctrl_reg = CLK_AUDIO_IN_CTRL, + .div_int_reg = CLK_AUDIO_IN_DIV_INT, + .sel_reg = CLK_AUDIO_IN_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(2, 5), + ), + + [RP1_CLK_AUDIO_OUT] = REGISTER_CLK( + .name = "clk_audio_out", + .parents = {"-"}, + .num_std_parents = 1, + .num_aux_parents = 0, + .ctrl_reg = CLK_AUDIO_OUT_CTRL, + .div_int_reg = CLK_AUDIO_OUT_DIV_INT, + .sel_reg = CLK_AUDIO_OUT_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(3, 5), + ), + + [RP1_CLK_I2S] = REGISTER_CLK( + .name = "clk_i2s", + .parents = {"xosc", + "pll_audio", + "pll_audio_sec"}, + .num_std_parents = 0, + .num_aux_parents = 3, + .ctrl_reg = CLK_I2S_CTRL, + .div_int_reg = CLK_I2S_DIV_INT, + .sel_reg = CLK_I2S_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(4, 4), + ), + + [RP1_CLK_MIPI0_CFG] = REGISTER_CLK( + .name = "clk_mipi0_cfg", + .parents = {"xosc"}, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_MIPI0_CFG_CTRL, + .div_int_reg = CLK_MIPI0_CFG_DIV_INT, + .sel_reg = CLK_MIPI0_CFG_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(4, 5), + ), + + [RP1_CLK_MIPI1_CFG] = REGISTER_CLK( + .name = "clk_mipi1_cfg", + .parents = {"xosc"}, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_MIPI1_CFG_CTRL, + .div_int_reg = CLK_MIPI1_CFG_DIV_INT, + .sel_reg = CLK_MIPI1_CFG_SEL, + .clk_src_mask = 1, + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(5, 6), + ), + + [RP1_CLK_ETH_TSU] = REGISTER_CLK( + .name = "clk_eth_tsu", + .parents = {"xosc"}, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_ETH_TSU_CTRL, + .div_int_reg = CLK_ETH_TSU_DIV_INT, + .sel_reg = CLK_ETH_TSU_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(5, 7), + ), + + [RP1_CLK_ADC] = REGISTER_CLK( + .name = "clk_adc", + .parents = {"xosc"}, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_ADC_CTRL, + .div_int_reg = CLK_ADC_DIV_INT, + .sel_reg = CLK_ADC_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(5, 5), + ), + + [RP1_CLK_SDIO_TIMER] = REGISTER_CLK( + .name = "clk_sdio_timer", + .parents = {"xosc"}, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_SDIO_TIMER_CTRL, + .div_int_reg = CLK_SDIO_TIMER_DIV_INT, + .sel_reg = CLK_SDIO_TIMER_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(3, 4), + ), + + [RP1_CLK_SDIO_ALT_SRC] = REGISTER_CLK( + .name = "clk_sdio_alt_src", + .parents = {"pll_sys"}, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_SDIO_ALT_SRC_CTRL, + .div_int_reg = CLK_SDIO_ALT_SRC_DIV_INT, + .sel_reg = CLK_SDIO_ALT_SRC_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(5, 4), + ), + + [RP1_CLK_GP0] = REGISTER_CLK( + .name = "clk_gp0", + .parents = {"xosc"}, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_GP0_CTRL, + .div_int_reg = CLK_GP0_DIV_INT, + .div_frac_reg = CLK_GP0_DIV_FRAC, + .sel_reg = CLK_GP0_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .fc0_src = FC_NUM(0, 1), + ), + + [RP1_CLK_GP1] = REGISTER_CLK( + .name = "clk_gp1", + .parents = {"xosc"}, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_GP1_CTRL, + .div_int_reg = CLK_GP1_DIV_INT, + .div_frac_reg = CLK_GP1_DIV_FRAC, + .sel_reg = CLK_GP1_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .fc0_src = FC_NUM(1, 1), + ), + + [RP1_CLK_GP2] = REGISTER_CLK( + .name = "clk_gp2", + .parents = {"xosc"}, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_GP2_CTRL, + .div_int_reg = CLK_GP2_DIV_INT, + .div_frac_reg = CLK_GP2_DIV_FRAC, + .sel_reg = CLK_GP2_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .fc0_src = FC_NUM(2, 1), + ), + + [RP1_CLK_GP3] = REGISTER_CLK( + .name = "clk_gp3", + .parents = {"xosc"}, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_GP3_CTRL, + .div_int_reg = CLK_GP3_DIV_INT, + .div_frac_reg = CLK_GP3_DIV_FRAC, + .sel_reg = CLK_GP3_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .fc0_src = FC_NUM(3, 1), + ), + + [RP1_CLK_GP4] = REGISTER_CLK( + .name = "clk_gp4", + .parents = {"xosc"}, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_GP4_CTRL, + .div_int_reg = CLK_GP4_DIV_INT, + .div_frac_reg = CLK_GP4_DIV_FRAC, + .sel_reg = CLK_GP4_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .fc0_src = FC_NUM(4, 1), + ), + + [RP1_CLK_GP5] = REGISTER_CLK( + .name = "clk_gp5", + .parents = {"xosc"}, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_GP5_CTRL, + .div_int_reg = CLK_GP5_DIV_INT, + .div_frac_reg = CLK_GP5_DIV_FRAC, + .sel_reg = CLK_GP5_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .fc0_src = FC_NUM(5, 1), + ), + + [RP1_CLK_VEC] = REGISTER_CLK( + .name = "clk_vec", + .parents = {"pll_sys_pri_ph", + "pll_video_sec", + "pll_video", + "clk_gp0", + "clk_gp1", + "clk_gp2", + "clk_gp3", + "clk_gp4"}, + .num_std_parents = 0, + .num_aux_parents = 8, /* XXX in fact there are more than 8 */ + .ctrl_reg = VIDEO_CLK_VEC_CTRL, + .div_int_reg = VIDEO_CLK_VEC_DIV_INT, + .sel_reg = VIDEO_CLK_VEC_SEL, + .flags = CLK_SET_RATE_NO_REPARENT, /* Let VEC driver set parent */ + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(0, 6), + ), + + [RP1_CLK_DPI] = REGISTER_CLK( + .name = "clk_dpi", + .parents = {"pll_sys", + "pll_video_sec", + "pll_video", + "clk_gp0", + "clk_gp1", + "clk_gp2", + "clk_gp3", + "clk_gp4"}, + .num_std_parents = 0, + .num_aux_parents = 8, /* XXX in fact there are more than 8 */ + .ctrl_reg = VIDEO_CLK_DPI_CTRL, + .div_int_reg = VIDEO_CLK_DPI_DIV_INT, + .sel_reg = VIDEO_CLK_DPI_SEL, + .flags = CLK_SET_RATE_NO_REPARENT, /* Let DPI driver set parent */ + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(1, 6), + ), + + [RP1_CLK_MIPI0_DPI] = REGISTER_CLK( + .name = "clk_mipi0_dpi", + .parents = {"pll_sys", + "pll_video_sec", + "pll_video", + "clksrc_mipi0_dsi_byteclk", + "clk_gp0", + "clk_gp1", + "clk_gp2", + "clk_gp3"}, + .num_std_parents = 0, + .num_aux_parents = 8, /* XXX in fact there are more than 8 */ + .ctrl_reg = VIDEO_CLK_MIPI0_DPI_CTRL, + .div_int_reg = VIDEO_CLK_MIPI0_DPI_DIV_INT, + .div_frac_reg = VIDEO_CLK_MIPI0_DPI_DIV_FRAC, + .sel_reg = VIDEO_CLK_MIPI0_DPI_SEL, + .flags = CLK_SET_RATE_NO_REPARENT, /* Let DSI driver set parent */ + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(2, 6), + ), + + [RP1_CLK_MIPI1_DPI] = REGISTER_CLK( + .name = "clk_mipi1_dpi", + .parents = {"pll_sys", + "pll_video_sec", + "pll_video", + "clksrc_mipi1_dsi_byteclk", + "clk_gp0", + "clk_gp1", + "clk_gp2", + "clk_gp3"}, + .num_std_parents = 0, + .num_aux_parents = 8, /* XXX in fact there are more than 8 */ + .ctrl_reg = VIDEO_CLK_MIPI1_DPI_CTRL, + .div_int_reg = VIDEO_CLK_MIPI1_DPI_DIV_INT, + .div_frac_reg = VIDEO_CLK_MIPI1_DPI_DIV_FRAC, + .sel_reg = VIDEO_CLK_MIPI1_DPI_SEL, + .flags = CLK_SET_RATE_NO_REPARENT, /* Let DSI driver set parent */ + .div_int_max = DIV_INT_8BIT_MAX, + .fc0_src = FC_NUM(3, 6), + ), +}; + +static bool rp1_clk_claimed[ARRAY_SIZE(clk_desc_array)]; + +static bool rp1_clk_is_claimed(const char *name) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(clk_desc_array); i++) { + if (clk_desc_array[i].data) { + const char *clk_name = *(const char **)(clk_desc_array[i].data); + + if (!strcmp(name, clk_name)) + return rp1_clk_claimed[i]; + } + } + + return false; +} + +static int rp1_clk_probe(struct platform_device *pdev) +{ + const struct rp1_clk_desc *desc; + struct device *dev = &pdev->dev; + struct rp1_clockman *clockman; + struct resource *res; + struct clk_hw **hws; + const size_t asize = ARRAY_SIZE(clk_desc_array); + u32 chip_id, platform; + unsigned int i; + u32 clk_id; + int ret; + + clockman = devm_kzalloc(dev, struct_size(clockman, onecell.hws, asize), + GFP_KERNEL); + if (!clockman) + return -ENOMEM; + + rp1_get_platform(&chip_id, &platform); + + spin_lock_init(&clockman->regs_lock); + clockman->dev = dev; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + clockman->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(clockman->regs)) + return PTR_ERR(clockman->regs); + + memset(rp1_clk_claimed, 0, sizeof(rp1_clk_claimed)); + for (i = 0; + !of_property_read_u32_index(pdev->dev.of_node, "claim-clocks", + i, &clk_id); + i++) + rp1_clk_claimed[clk_id] = true; + + platform_set_drvdata(pdev, clockman); + + clockman->onecell.num = asize; + hws = clockman->onecell.hws; + + for (i = 0; i < asize; i++) { + desc = &clk_desc_array[i]; + if (desc->clk_register && desc->data) + hws[i] = desc->clk_register(clockman, desc->data); + } + + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + &clockman->onecell); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id rp1_clk_of_match[] = { + { .compatible = "raspberrypi,rp1-clocks" }, + {} +}; +MODULE_DEVICE_TABLE(of, rp1_clk_of_match); + +static struct platform_driver rp1_clk_driver = { + .driver = { + .name = "rp1-clk", + .of_match_table = rp1_clk_of_match, + }, + .probe = rp1_clk_probe, +}; + +static int __init __rp1_clk_driver_init(void) +{ + return platform_driver_register(&rp1_clk_driver); +} +postcore_initcall(__rp1_clk_driver_init); + +MODULE_AUTHOR("Naushir Patuck <naush@raspberrypi.com>"); +MODULE_DESCRIPTION("RP1 clock driver"); +MODULE_LICENSE("GPL"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/clk/clk-rp1-sdio.c linux/drivers/clk/clk-rp1-sdio.c --- linux-6.1.66/drivers/clk/clk-rp1-sdio.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/clk/clk-rp1-sdio.c 2023-12-13 11:50:52.992971616 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * SDIO clock driver for RP1 + * + * Copyright (C) 2023 Raspberry Pi Ltd. + */ + +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +// Register : MODE +#define MODE 0x00000000 +#define MODE_BITS 0x70030000 +#define MODE_RESET 0x00000000 +// Field : MODE_STEPS_PER_CYCLE +#define MODE_STEPS_PER_CYCLE_RESET 0x0 +#define MODE_STEPS_PER_CYCLE_BITS 0x70000000 +#define MODE_STEPS_PER_CYCLE_MSB 30 +#define MODE_STEPS_PER_CYCLE_LSB 28 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_20 0x0 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_10 0x1 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_16 0x2 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_8 0x3 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_12 0x4 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_6 0x5 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_5 0x6 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_4 0x7 +// Field : MODE_SRC_SEL +#define MODE_SRC_SEL_RESET 0x0 +#define MODE_SRC_SEL_BITS 0x00030000 +#define MODE_SRC_SEL_MSB 17 +#define MODE_SRC_SEL_LSB 16 +#define MODE_SRC_SEL_VALUE_STOP 0x0 +#define MODE_SRC_SEL_VALUE_CLK_ALT_SRC 0x1 +#define MODE_SRC_SEL_VALUE_PLL_SYS_VCO 0x2 +#define MODE_SRC_SEL_VALUE_PLL_SYS_VCO_AGAIN 0x3 +// Register : FROMIP +#define FROMIP 0x00000004 +#define FROMIP_BITS 0x0f9713ff +#define FROMIP_RESET 0x00000000 +// Field : FROMIP_TUNING_CCLK_SEL +#define FROMIP_TUNING_CCLK_SEL_RESET 0x0 +#define FROMIP_TUNING_CCLK_SEL_BITS 0x0f000000 +#define FROMIP_TUNING_CCLK_SEL_MSB 27 +#define FROMIP_TUNING_CCLK_SEL_LSB 24 +// Field : FROMIP_TUNING_CCLK_UPDATE +#define FROMIP_TUNING_CCLK_UPDATE_RESET 0x0 +#define FROMIP_TUNING_CCLK_UPDATE_BITS 0x00800000 +#define FROMIP_TUNING_CCLK_UPDATE_MSB 23 +#define FROMIP_TUNING_CCLK_UPDATE_LSB 23 +// Field : FROMIP_SAMPLE_CCLK_SEL +#define FROMIP_SAMPLE_CCLK_SEL_RESET 0x0 +#define FROMIP_SAMPLE_CCLK_SEL_BITS 0x00100000 +#define FROMIP_SAMPLE_CCLK_SEL_MSB 20 +#define FROMIP_SAMPLE_CCLK_SEL_LSB 20 +// Field : FROMIP_CLK2CARD_ON +#define FROMIP_CLK2CARD_ON_RESET 0x0 +#define FROMIP_CLK2CARD_ON_BITS 0x00040000 +#define FROMIP_CLK2CARD_ON_MSB 18 +#define FROMIP_CLK2CARD_ON_LSB 18 +// Field : FROMIP_CARD_CLK_STABLE +#define FROMIP_CARD_CLK_STABLE_RESET 0x0 +#define FROMIP_CARD_CLK_STABLE_BITS 0x00020000 +#define FROMIP_CARD_CLK_STABLE_MSB 17 +#define FROMIP_CARD_CLK_STABLE_LSB 17 +// Field : FROMIP_CARD_CLK_EN +#define FROMIP_CARD_CLK_EN_RESET 0x0 +#define FROMIP_CARD_CLK_EN_BITS 0x00010000 +#define FROMIP_CARD_CLK_EN_MSB 16 +#define FROMIP_CARD_CLK_EN_LSB 16 +// Field : FROMIP_CLK_GEN_SEL +#define FROMIP_CLK_GEN_SEL_RESET 0x0 +#define FROMIP_CLK_GEN_SEL_BITS 0x00001000 +#define FROMIP_CLK_GEN_SEL_MSB 12 +#define FROMIP_CLK_GEN_SEL_LSB 12 +// Field : FROMIP_FREQ_SEL +#define FROMIP_FREQ_SEL_RESET 0x000 +#define FROMIP_FREQ_SEL_BITS 0x000003ff +#define FROMIP_FREQ_SEL_MSB 9 +#define FROMIP_FREQ_SEL_LSB 0 +// Register : LOCAL +#define LOCAL 0x00000008 +#define LOCAL_BITS 0x1f9713ff +#define LOCAL_RESET 0x00000000 +// Field : LOCAL_TUNING_CCLK_SEL +#define LOCAL_TUNING_CCLK_SEL_RESET 0x00 +#define LOCAL_TUNING_CCLK_SEL_BITS 0x1f000000 +#define LOCAL_TUNING_CCLK_SEL_MSB 28 +#define LOCAL_TUNING_CCLK_SEL_LSB 24 +// Field : LOCAL_TUNING_CCLK_UPDATE +#define LOCAL_TUNING_CCLK_UPDATE_RESET 0x0 +#define LOCAL_TUNING_CCLK_UPDATE_BITS 0x00800000 +#define LOCAL_TUNING_CCLK_UPDATE_MSB 23 +#define LOCAL_TUNING_CCLK_UPDATE_LSB 23 +// Field : LOCAL_SAMPLE_CCLK_SEL +#define LOCAL_SAMPLE_CCLK_SEL_RESET 0x0 +#define LOCAL_SAMPLE_CCLK_SEL_BITS 0x00100000 +#define LOCAL_SAMPLE_CCLK_SEL_MSB 20 +#define LOCAL_SAMPLE_CCLK_SEL_LSB 20 +// Field : LOCAL_CLK2CARD_ON +#define LOCAL_CLK2CARD_ON_RESET 0x0 +#define LOCAL_CLK2CARD_ON_BITS 0x00040000 +#define LOCAL_CLK2CARD_ON_MSB 18 +#define LOCAL_CLK2CARD_ON_LSB 18 +// Field : LOCAL_CARD_CLK_STABLE +#define LOCAL_CARD_CLK_STABLE_RESET 0x0 +#define LOCAL_CARD_CLK_STABLE_BITS 0x00020000 +#define LOCAL_CARD_CLK_STABLE_MSB 17 +#define LOCAL_CARD_CLK_STABLE_LSB 17 +// Field : LOCAL_CARD_CLK_EN +#define LOCAL_CARD_CLK_EN_RESET 0x0 +#define LOCAL_CARD_CLK_EN_BITS 0x00010000 +#define LOCAL_CARD_CLK_EN_MSB 16 +#define LOCAL_CARD_CLK_EN_LSB 16 +// Field : LOCAL_CLK_GEN_SEL +#define LOCAL_CLK_GEN_SEL_RESET 0x0 +#define LOCAL_CLK_GEN_SEL_BITS 0x00001000 +#define LOCAL_CLK_GEN_SEL_MSB 12 +#define LOCAL_CLK_GEN_SEL_LSB 12 +#define LOCAL_CLK_GEN_SEL_VALUE_PROGCLOCKMODE 0x0 +#define LOCAL_CLK_GEN_SEL_VALUE_DIVCLOCKMODE 0x1 +// Field : LOCAL_FREQ_SEL +#define LOCAL_FREQ_SEL_RESET 0x000 +#define LOCAL_FREQ_SEL_BITS 0x000003ff +#define LOCAL_FREQ_SEL_MSB 9 +#define LOCAL_FREQ_SEL_LSB 0 +// Register : USE_LOCAL +#define USE_LOCAL 0x0000000c +#define USE_LOCAL_BITS 0x01951001 +#define USE_LOCAL_RESET 0x00000000 +// Field : USE_LOCAL_TUNING_CCLK_SEL +#define USE_LOCAL_TUNING_CCLK_SEL_RESET 0x0 +#define USE_LOCAL_TUNING_CCLK_SEL_BITS 0x01000000 +#define USE_LOCAL_TUNING_CCLK_SEL_MSB 24 +#define USE_LOCAL_TUNING_CCLK_SEL_LSB 24 +// Field : USE_LOCAL_TUNING_CCLK_UPDATE +#define USE_LOCAL_TUNING_CCLK_UPDATE_RESET 0x0 +#define USE_LOCAL_TUNING_CCLK_UPDATE_BITS 0x00800000 +#define USE_LOCAL_TUNING_CCLK_UPDATE_MSB 23 +#define USE_LOCAL_TUNING_CCLK_UPDATE_LSB 23 +// Field : USE_LOCAL_SAMPLE_CCLK_SEL +#define USE_LOCAL_SAMPLE_CCLK_SEL_RESET 0x0 +#define USE_LOCAL_SAMPLE_CCLK_SEL_BITS 0x00100000 +#define USE_LOCAL_SAMPLE_CCLK_SEL_MSB 20 +#define USE_LOCAL_SAMPLE_CCLK_SEL_LSB 20 +// Field : USE_LOCAL_CLK2CARD_ON +#define USE_LOCAL_CLK2CARD_ON_RESET 0x0 +#define USE_LOCAL_CLK2CARD_ON_BITS 0x00040000 +#define USE_LOCAL_CLK2CARD_ON_MSB 18 +#define USE_LOCAL_CLK2CARD_ON_LSB 18 +// Field : USE_LOCAL_CARD_CLK_EN +#define USE_LOCAL_CARD_CLK_EN_RESET 0x0 +#define USE_LOCAL_CARD_CLK_EN_BITS 0x00010000 +#define USE_LOCAL_CARD_CLK_EN_MSB 16 +#define USE_LOCAL_CARD_CLK_EN_LSB 16 +// Field : USE_LOCAL_CLK_GEN_SEL +#define USE_LOCAL_CLK_GEN_SEL_RESET 0x0 +#define USE_LOCAL_CLK_GEN_SEL_BITS 0x00001000 +#define USE_LOCAL_CLK_GEN_SEL_MSB 12 +#define USE_LOCAL_CLK_GEN_SEL_LSB 12 +// Field : USE_LOCAL_FREQ_SEL +#define USE_LOCAL_FREQ_SEL_RESET 0x0 +#define USE_LOCAL_FREQ_SEL_BITS 0x00000001 +#define USE_LOCAL_FREQ_SEL_MSB 0 +#define USE_LOCAL_FREQ_SEL_LSB 0 +// Register : SD_DELAY +#define SD_DELAY 0x00000010 +#define SD_DELAY_BITS 0x0000001f +#define SD_DELAY_RESET 0x00000000 +// Field : SD_DELAY_STEPS +#define SD_DELAY_STEPS_RESET 0x00 +#define SD_DELAY_STEPS_BITS 0x0000001f +#define SD_DELAY_STEPS_MSB 4 +#define SD_DELAY_STEPS_LSB 0 +// Register : RX_DELAY +#define RX_DELAY 0x00000014 +#define RX_DELAY_BITS 0x19f3331f +#define RX_DELAY_RESET 0x00000000 +// Field : RX_DELAY_BYPASS +#define RX_DELAY_BYPASS_RESET 0x0 +#define RX_DELAY_BYPASS_BITS 0x10000000 +#define RX_DELAY_BYPASS_MSB 28 +#define RX_DELAY_BYPASS_LSB 28 +// Field : RX_DELAY_FAIL_ACTUAL +#define RX_DELAY_FAIL_ACTUAL_RESET 0x0 +#define RX_DELAY_FAIL_ACTUAL_BITS 0x08000000 +#define RX_DELAY_FAIL_ACTUAL_MSB 27 +#define RX_DELAY_FAIL_ACTUAL_LSB 27 +// Field : RX_DELAY_ACTUAL +#define RX_DELAY_ACTUAL_RESET 0x00 +#define RX_DELAY_ACTUAL_BITS 0x01f00000 +#define RX_DELAY_ACTUAL_MSB 24 +#define RX_DELAY_ACTUAL_LSB 20 +// Field : RX_DELAY_OFFSET +#define RX_DELAY_OFFSET_RESET 0x0 +#define RX_DELAY_OFFSET_BITS 0x00030000 +#define RX_DELAY_OFFSET_MSB 17 +#define RX_DELAY_OFFSET_LSB 16 +// Field : RX_DELAY_OVERFLOW +#define RX_DELAY_OVERFLOW_RESET 0x0 +#define RX_DELAY_OVERFLOW_BITS 0x00003000 +#define RX_DELAY_OVERFLOW_MSB 13 +#define RX_DELAY_OVERFLOW_LSB 12 +#define RX_DELAY_OVERFLOW_VALUE_ALLOW 0x0 +#define RX_DELAY_OVERFLOW_VALUE_CLAMP 0x1 +#define RX_DELAY_OVERFLOW_VALUE_FAIL 0x2 +// Field : RX_DELAY_MAP +#define RX_DELAY_MAP_RESET 0x0 +#define RX_DELAY_MAP_BITS 0x00000300 +#define RX_DELAY_MAP_MSB 9 +#define RX_DELAY_MAP_LSB 8 +#define RX_DELAY_MAP_VALUE_DIRECT 0x0 +#define RX_DELAY_MAP_VALUE 0x1 +#define RX_DELAY_MAP_VALUE_STRETCH 0x2 +// Field : RX_DELAY_FIXED +#define RX_DELAY_FIXED_RESET 0x00 +#define RX_DELAY_FIXED_BITS 0x0000001f +#define RX_DELAY_FIXED_MSB 4 +#define RX_DELAY_FIXED_LSB 0 +// Register : NDIV +#define NDIV 0x00000018 +#define NDIV_BITS 0x1fff0000 +#define NDIV_RESET 0x00110000 +// Field : NDIV_DIVB +#define NDIV_DIVB_RESET 0x001 +#define NDIV_DIVB_BITS 0x1ff00000 +#define NDIV_DIVB_MSB 28 +#define NDIV_DIVB_LSB 20 +// Field : NDIV_DIVA +#define NDIV_DIVA_RESET 0x1 +#define NDIV_DIVA_BITS 0x000f0000 +#define NDIV_DIVA_MSB 19 +#define NDIV_DIVA_LSB 16 +// Register : CS +#define CS 0x0000001c +#define CS_BITS 0x00111101 +#define CS_RESET 0x00000001 +// Field : CS_RX_DEL_UPDATED +#define CS_RX_DEL_UPDATED_RESET 0x0 +#define CS_RX_DEL_UPDATED_BITS 0x00100000 +#define CS_RX_DEL_UPDATED_MSB 20 +#define CS_RX_DEL_UPDATED_LSB 20 +// Field : CS_RX_CLK_RUNNING +#define CS_RX_CLK_RUNNING_RESET 0x0 +#define CS_RX_CLK_RUNNING_BITS 0x00010000 +#define CS_RX_CLK_RUNNING_MSB 16 +#define CS_RX_CLK_RUNNING_LSB 16 +// Field : CS_SD_CLK_RUNNING +#define CS_SD_CLK_RUNNING_RESET 0x0 +#define CS_SD_CLK_RUNNING_BITS 0x00001000 +#define CS_SD_CLK_RUNNING_MSB 12 +#define CS_SD_CLK_RUNNING_LSB 12 +// Field : CS_TX_CLK_RUNNING +#define CS_TX_CLK_RUNNING_RESET 0x0 +#define CS_TX_CLK_RUNNING_BITS 0x00000100 +#define CS_TX_CLK_RUNNING_MSB 8 +#define CS_TX_CLK_RUNNING_LSB 8 +// Field : CS_RESET +#define CS_RESET_RESET 0x1 +#define CS_RESET_BITS 0x00000001 +#define CS_RESET_MSB 0 +#define CS_RESET_LSB 0 + +#define FPGA_SRC_RATE 400000000 + +/* Base number of steps to delay in relation to tx clk. + * The relationship of the 3 clocks are as follows: + * tx_clk: This clock is provided to the controller. Data is sent out + * to the pads using this clock. + * sd_clk: This clock is sent out to the card. + * rx_clk: This clock is used to sample the data coming back from the card. + * This may need to be several steps ahead of the tx_clk. The default rx delay + * is used as a base delay, and can be further adjusted by the sd host + * controller during the tuning process if using a DDR50 or faster SD card + */ +/* + * PRJY-1813 - the default SD clock delay needs to be set to ~60% of the total + * number of steps to meet tISU (>6ns) and tIH (>2ns) in high-speed mode. + * On FPGA this means delay SDCLK by 5, and sample RX with a delay of 6. + */ +#define DEFAULT_RX_DELAY 6 +#define DEFAULT_SD_DELAY 5 + +struct rp1_sdio_clkgen { + struct device *dev; + + /* Source clock. Either PLL VCO or fixed freq on FPGA */ + struct clk *src_clk; + /* Desired base frequency. Max freq card can go */ + struct clk *base_clk; + + struct clk_hw hw; + void __iomem *regs; + + /* Starting value of local register before changing freq */ + u32 local_base; +}; + +static inline void clkgen_write(struct rp1_sdio_clkgen *clkgen, u32 reg, u32 val) +{ + dev_dbg(clkgen->dev, "%s: write reg 0x%x: 0x%x\n", __func__, reg, val); + writel(val, clkgen->regs + reg); +} + +static inline u32 clkgen_read(struct rp1_sdio_clkgen *clkgen, u32 reg) +{ + u32 val = readl(clkgen->regs + reg); + + dev_dbg(clkgen->dev, "%s: read reg 0x%x: 0x%x\n", __func__, reg, val); + return val; +} + +static int get_steps(unsigned int steps) +{ + int ret = -1; + + if (steps == 4) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_4; + else if (steps == 5) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_5; + else if (steps == 6) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_6; + else if (steps == 8) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_8; + else if (steps == 10) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_10; + else if (steps == 12) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_12; + else if (steps == 16) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_16; + else if (steps == 20) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_20; + return ret; +} + +static int rp1_sdio_clk_init(struct rp1_sdio_clkgen *clkgen) +{ + unsigned long src_rate = clk_get_rate(clkgen->src_clk); + unsigned long base_rate = clk_get_rate(clkgen->base_clk); + unsigned int steps = src_rate / base_rate; + u32 reg = 0; + int steps_value = 0; + + dev_dbg(clkgen->dev, "init: src_rate %lu, base_rate %lu, steps %d\n", + src_rate, base_rate, steps); + + /* Assert reset while we set up clkgen */ + clkgen_write(clkgen, CS, CS_RESET_BITS); + + /* Pick clock source */ + if (src_rate == FPGA_SRC_RATE) { + /* Using ALT SRC */ + reg |= MODE_SRC_SEL_VALUE_CLK_ALT_SRC << MODE_SRC_SEL_LSB; + } else { + /* Assume we are using PLL SYS VCO */ + reg |= MODE_SRC_SEL_VALUE_PLL_SYS_VCO << MODE_SRC_SEL_LSB; + } + + /* How many delay steps are available in one cycle for this source */ + steps_value = get_steps(steps); + if (steps_value < 0) { + dev_err(clkgen->dev, "Invalid step value: %d\n", steps); + return -EINVAL; + } + reg |= steps_value << MODE_STEPS_PER_CYCLE_LSB; + + /* Mode register is done now*/ + clkgen_write(clkgen, MODE, reg); + + /* Now set delay mode */ + /* Clamp value if out of range rx delay is used */ + reg = RX_DELAY_OVERFLOW_VALUE_CLAMP << RX_DELAY_OVERFLOW_LSB; + /* SD tuning bus goes from 0x0 to 0xf but we don't necessarily have that + * many steps available depending on the source so map 0x0 -> 0xf to one + * cycle of rx delay + */ + reg |= RX_DELAY_MAP_VALUE_STRETCH << RX_DELAY_MAP_LSB; + + /* Default RX delay */ + dev_dbg(clkgen->dev, "default rx delay %d\n", DEFAULT_RX_DELAY); + reg |= (DEFAULT_RX_DELAY & RX_DELAY_FIXED_BITS) << RX_DELAY_FIXED_LSB; + clkgen_write(clkgen, RX_DELAY, reg); + + /* Default SD delay */ + dev_dbg(clkgen->dev, "default sd delay %d\n", DEFAULT_SD_DELAY); + reg = (DEFAULT_SD_DELAY & SD_DELAY_STEPS_BITS) << SD_DELAY_STEPS_LSB; + clkgen_write(clkgen, SD_DELAY, reg); + + /* We select freq, we turn on tx clock, we turn on sd clk, + * we pick clock generator mode + */ + reg = USE_LOCAL_FREQ_SEL_BITS | USE_LOCAL_CARD_CLK_EN_BITS | + USE_LOCAL_CLK2CARD_ON_BITS | USE_LOCAL_CLK_GEN_SEL_BITS; + clkgen_write(clkgen, USE_LOCAL, reg); + + /* Deassert reset. Reset bit is only writable bit of CS + * reg so fine to write a 0. + */ + clkgen_write(clkgen, CS, 0); + + return 0; +} + +#define RUNNING \ + (CS_TX_CLK_RUNNING_BITS | CS_RX_CLK_RUNNING_BITS | \ + CS_SD_CLK_RUNNING_BITS) +static int rp1_sdio_clk_is_prepared(struct clk_hw *hw) +{ + struct rp1_sdio_clkgen *clkgen = + container_of(hw, struct rp1_sdio_clkgen, hw); + u32 status; + + dev_dbg(clkgen->dev, "is_prepared\n"); + status = clkgen_read(clkgen, CS); + return ((status & RUNNING) == RUNNING); +} + +/* Can define an additional divider if an sd card isn't working at full speed */ +/* #define SLOWDOWN 3 */ + +static unsigned long rp1_sdio_clk_get_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + /* Get the current rate */ + struct rp1_sdio_clkgen *clkgen = + container_of(hw, struct rp1_sdio_clkgen, hw); + unsigned long actual_rate = 0; + u32 ndiv_diva; + u32 ndiv_divb; + u32 tmp; + u32 div; + + tmp = clkgen_read(clkgen, LOCAL); + if ((tmp & LOCAL_CLK2CARD_ON_BITS) == 0) { + dev_dbg(clkgen->dev, "get_rate 0\n"); + return 0; + } + + tmp = clkgen_read(clkgen, NDIV); + ndiv_diva = (tmp & NDIV_DIVA_BITS) >> NDIV_DIVA_LSB; + ndiv_divb = (tmp & NDIV_DIVB_BITS) >> NDIV_DIVB_LSB; + div = ndiv_diva * ndiv_divb; + actual_rate = (clk_get_rate(clkgen->base_clk) / div); + +#ifdef SLOWDOWN + actual_rate *= SLOWDOWN; +#endif + + dev_dbg(clkgen->dev, "get_rate. ndiv_diva %d, ndiv_divb %d = %lu\n", + ndiv_diva, ndiv_divb, actual_rate); + + return actual_rate; +} + +static int rp1_sdio_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct rp1_sdio_clkgen *clkgen = + container_of(hw, struct rp1_sdio_clkgen, hw); + u32 div; + u32 reg; + + dev_dbg(clkgen->dev, "set_rate %lu\n", rate); + + if (rate == 0) { + /* Keep tx clock running */ + clkgen_write(clkgen, LOCAL, LOCAL_CARD_CLK_EN_BITS); + return 0; + } + +#ifdef SLOWDOWN + rate /= SLOWDOWN; +#endif + + div = (clk_get_rate(clkgen->base_clk) / rate) - 1; + reg = LOCAL_CLK_GEN_SEL_BITS | LOCAL_CARD_CLK_EN_BITS | + LOCAL_CLK2CARD_ON_BITS | (div << LOCAL_FREQ_SEL_LSB); + clkgen_write(clkgen, LOCAL, reg); + + return 0; +} + +#define MAX_NDIV (256 * 8) +static int rp1_sdio_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long rate; + struct rp1_sdio_clkgen *clkgen = + container_of(hw, struct rp1_sdio_clkgen, hw); + unsigned long base_rate = clk_get_rate(clkgen->base_clk); + u32 div; + + /* What is the actual rate I can get if I request xyz */ + if (req->rate) { + div = min((u32)(base_rate / req->rate), (u32)MAX_NDIV); + rate = base_rate / div; + req->rate = rate; + dev_dbg(clkgen->dev, "determine_rate %lu: %lu / %d = %lu\n", + req->rate, base_rate, div, rate); + } else { + rate = 0; + dev_dbg(clkgen->dev, "determine_rate %lu: %lu\n", req->rate, + rate); + } + + return 0; +} + +static const struct clk_ops rp1_sdio_clk_ops = { + .is_prepared = rp1_sdio_clk_is_prepared, + .recalc_rate = rp1_sdio_clk_get_rate, + .set_rate = rp1_sdio_clk_set_rate, + .determine_rate = rp1_sdio_clk_determine_rate, +}; + +static int rp1_sdio_clk_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct rp1_sdio_clkgen *clkgen; + void __iomem *regs; + struct clk_init_data init = {}; + int ret; + + clkgen = devm_kzalloc(&pdev->dev, sizeof(*clkgen), GFP_KERNEL); + if (!clkgen) + return -ENOMEM; + platform_set_drvdata(pdev, clkgen); + + clkgen->dev = &pdev->dev; + + /* Source freq */ + clkgen->src_clk = devm_clk_get(&pdev->dev, "src"); + if (IS_ERR(clkgen->src_clk)) { + int err = PTR_ERR(clkgen->src_clk); + + dev_err(&pdev->dev, "failed to get src clk: %d\n", err); + return err; + } + + /* Desired maximum output freq (i.e. base freq) */ + clkgen->base_clk = devm_clk_get(&pdev->dev, "base"); + if (IS_ERR(clkgen->base_clk)) { + int err = PTR_ERR(clkgen->base_clk); + + dev_err(&pdev->dev, "failed to get base clk: %d\n", err); + return err; + } + + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + init.name = node->name; + init.ops = &rp1_sdio_clk_ops; + init.flags = CLK_GET_RATE_NOCACHE; + + clkgen->hw.init = &init; + clkgen->regs = regs; + + dev_info(&pdev->dev, "loaded %s\n", init.name); + + ret = devm_clk_hw_register(&pdev->dev, &clkgen->hw); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &clkgen->hw); + if (ret) + return ret; + + ret = rp1_sdio_clk_init(clkgen); + return ret; +} + +static int rp1_sdio_clk_remove(struct platform_device *pdev) +{ + return 0; +} + +static const struct of_device_id rp1_sdio_clk_dt_ids[] = { + { .compatible = "raspberrypi,rp1-sdio-clk", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rp1_sdio_clk_dt_ids); + +static struct platform_driver rp1_sdio_clk_driver = { + .probe = rp1_sdio_clk_probe, + .remove = rp1_sdio_clk_remove, + .driver = { + .name = "rp1-sdio-clk", + .of_match_table = rp1_sdio_clk_dt_ids, + }, +}; +module_platform_driver(rp1_sdio_clk_driver); + +MODULE_AUTHOR("Liam Fraser <liam@raspberrypi.com>"); +MODULE_DESCRIPTION("RP1 SDIO clock driver"); +MODULE_LICENSE("GPL"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/clk/Kconfig linux/drivers/clk/Kconfig --- linux-6.1.66/drivers/clk/Kconfig 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/clk/Kconfig 2023-12-13 11:50:52.952971522 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:92 @ These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each. Clkout1 is always on, Clkout2 can off by control register. +config COMMON_CLK_RP1 + tristate "Raspberry Pi RP1-based clock support" + depends on PCI || COMPILE_TEST + depends on COMMON_CLK + help + Enable common clock framework support for Raspberry Pi RP1 + +config COMMON_CLK_RP1_SDIO + tristate "Clock driver for the RP1 SDIO interfaces" + depends on MFD_RP1 + help + SDIO clock driver for the RP1 support chip + config COMMON_CLK_HI655X tristate "Clock driver for Hi655x" if EXPERT depends on (MFD_HI655X_PMIC || COMPILE_TEST) @ linux/arch/arm/boot/dts/bcm2708.dtsi:115 @ multi-function device has one fixed-rate oscillator, clocked at 32KHz. +config COMMON_CLK_HIFIBERRY_DACPLUSHD + tristate + +config COMMON_CLK_HIFIBERRY_DACPRO + tristate + config COMMON_CLK_SCMI tristate "Clock driver controlled via SCMI interface" depends on ARM_SCMI_PROTOCOL || COMPILE_TEST diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/clk/Makefile linux/drivers/clk/Makefile --- linux-6.1.66/drivers/clk/Makefile 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/clk/Makefile 2023-12-13 11:50:52.953971524 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:46 @ obj-$(CONFIG_LMK04832) += clk-lmk04832.o obj-$(CONFIG_COMMON_CLK_LAN966X) += clk-lan966x.o obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o +obj-$(CONFIG_COMMON_CLK_HIFIBERRY_DACPRO) += clk-hifiberry-dacpro.o +obj-$(CONFIG_COMMON_CLK_HIFIBERRY_DACPLUSHD) += clk-hifiberry-dachd.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o obj-$(CONFIG_ARCH_MILBEAUT_M10V) += clk-milbeaut.o @ linux/arch/arm/boot/dts/bcm2708.dtsi:61 @ obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o +obj-$(CONFIG_COMMON_CLK_RP1) += clk-rp1.o +obj-$(CONFIG_COMMON_CLK_RP1_SDIO) += clk-rp1-sdio.o obj-$(CONFIG_COMMON_CLK_HI655X) += clk-hi655x.o obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o obj-$(CONFIG_COMMON_CLK_SCMI) += clk-scmi.o diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/dma/bcm2708-dmaengine.c linux/drivers/dma/bcm2708-dmaengine.c --- linux-6.1.66/drivers/dma/bcm2708-dmaengine.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/dma/bcm2708-dmaengine.c 2023-12-13 11:50:53.599973045 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * BCM2708 legacy DMA API + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/platform_data/dma-bcm2708.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/spinlock.h> + +#include "virt-dma.h" + +#define CACHE_LINE_MASK 31 +#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */ + +/* valid only for channels 0 - 14, 15 has its own base address */ +#define BCM2708_DMA_CHAN(n) ((n) << 8) /* base address */ +#define BCM2708_DMA_CHANIO(dma_base, n) \ + ((void __iomem *)((char *)(dma_base) + BCM2708_DMA_CHAN(n))) + +struct vc_dmaman { + void __iomem *dma_base; + u32 chan_available; /* bitmap of available channels */ + u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */ + struct mutex lock; +}; + +static struct device *dmaman_dev; /* we assume there's only one! */ +static struct vc_dmaman *g_dmaman; /* DMA manager */ + +/* DMA Auxiliary Functions */ + +/* A DMA buffer on an arbitrary boundary may separate a cache line into a + section inside the DMA buffer and another section outside it. + Even if we flush DMA buffers from the cache there is always the chance that + during a DMA someone will access the part of a cache line that is outside + the DMA buffer - which will then bring in unwelcome data. + Without being able to dictate our own buffer pools we must insist that + DMA buffers consist of a whole number of cache lines. +*/ +extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len) +{ + int i; + + for (i = 0; i < sg_len; i++) { + if (sg_ptr[i].offset & CACHE_LINE_MASK || + sg_ptr[i].length & CACHE_LINE_MASK) + return 0; + } + + return 1; +} +EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma); + +extern void bcm_dma_start(void __iomem *dma_chan_base, + dma_addr_t control_block) +{ + dsb(sy); /* ARM data synchronization (push) operation */ + + writel(control_block, dma_chan_base + BCM2708_DMA_ADDR); + writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS); +} +EXPORT_SYMBOL_GPL(bcm_dma_start); + +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base) +{ + dsb(sy); + + /* ugly busy wait only option for now */ + while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE) + cpu_relax(); +} +EXPORT_SYMBOL_GPL(bcm_dma_wait_idle); + +extern bool bcm_dma_is_busy(void __iomem *dma_chan_base) +{ + dsb(sy); + + return readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE; +} +EXPORT_SYMBOL_GPL(bcm_dma_is_busy); + +/* Complete an ongoing DMA (assuming its results are to be ignored) + Does nothing if there is no DMA in progress. + This routine waits for the current AXI transfer to complete before + terminating the current DMA. If the current transfer is hung on a DREQ used + by an uncooperative peripheral the AXI transfer may never complete. In this + case the routine times out and return a non-zero error code. + Use of this routine doesn't guarantee that the ongoing or aborted DMA + does not produce an interrupt. +*/ +extern int bcm_dma_abort(void __iomem *dma_chan_base) +{ + unsigned long int cs; + int rc = 0; + + cs = readl(dma_chan_base + BCM2708_DMA_CS); + + if (BCM2708_DMA_ACTIVE & cs) { + long int timeout = 10000; + + /* write 0 to the active bit - pause the DMA */ + writel(0, dma_chan_base + BCM2708_DMA_CS); + + /* wait for any current AXI transfer to complete */ + while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0) + cs = readl(dma_chan_base + BCM2708_DMA_CS); + + if (0 != (cs & BCM2708_DMA_ISPAUSED)) { + /* we'll un-pause when we set of our next DMA */ + rc = -ETIMEDOUT; + + } else if (BCM2708_DMA_ACTIVE & cs) { + /* terminate the control block chain */ + writel(0, dma_chan_base + BCM2708_DMA_NEXTCB); + + /* abort the whole DMA */ + writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE, + dma_chan_base + BCM2708_DMA_CS); + } + } + + return rc; +} +EXPORT_SYMBOL_GPL(bcm_dma_abort); + + /* DMA Manager Device Methods */ + +static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base, + u32 chans_available) +{ + dmaman->dma_base = dma_base; + dmaman->chan_available = chans_available; + dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* 2 & 3 */ + dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* 0 */ + dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe; /* 1 to 7 */ + dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00; /* 8 to 14 */ +} + +static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman, + unsigned required_feature_set) +{ + u32 chans; + int chan = 0; + int feature; + + chans = dmaman->chan_available; + for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++) + /* select the subset of available channels with the desired + features */ + if (required_feature_set & (1 << feature)) + chans &= dmaman->has_feature[feature]; + + if (!chans) + return -ENOENT; + + /* return the ordinal of the first channel in the bitmap */ + while (chans != 0 && (chans & 1) == 0) { + chans >>= 1; + chan++; + } + /* claim the channel */ + dmaman->chan_available &= ~(1 << chan); + + return chan; +} + +static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan) +{ + if (chan < 0) + return -EINVAL; + + if ((1 << chan) & dmaman->chan_available) + return -EIDRM; + + dmaman->chan_available |= (1 << chan); + + return 0; +} + +/* DMA Manager Monitor */ + +extern int bcm_dma_chan_alloc(unsigned required_feature_set, + void __iomem **out_dma_base, int *out_dma_irq) +{ + struct vc_dmaman *dmaman = g_dmaman; + struct platform_device *pdev = to_platform_device(dmaman_dev); + int chan; + int irq; + + if (!dmaman_dev) + return -ENODEV; + + mutex_lock(&dmaman->lock); + chan = vc_dmaman_chan_alloc(dmaman, required_feature_set); + if (chan < 0) + goto out; + + irq = platform_get_irq(pdev, (unsigned int)chan); + if (irq < 0) { + dev_err(dmaman_dev, "failed to get irq for DMA channel %d\n", + chan); + vc_dmaman_chan_free(dmaman, chan); + chan = -ENOENT; + goto out; + } + + *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base, chan); + *out_dma_irq = irq; + dev_dbg(dmaman_dev, + "Legacy API allocated channel=%d, base=%p, irq=%i\n", + chan, *out_dma_base, *out_dma_irq); + +out: + mutex_unlock(&dmaman->lock); + + return chan; +} +EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc); + +extern int bcm_dma_chan_free(int channel) +{ + struct vc_dmaman *dmaman = g_dmaman; + int rc; + + if (!dmaman_dev) + return -ENODEV; + + mutex_lock(&dmaman->lock); + rc = vc_dmaman_chan_free(dmaman, channel); + mutex_unlock(&dmaman->lock); + + return rc; +} +EXPORT_SYMBOL_GPL(bcm_dma_chan_free); + +int bcm_dmaman_probe(struct platform_device *pdev, void __iomem *base, + u32 chans_available) +{ + struct device *dev = &pdev->dev; + struct vc_dmaman *dmaman; + + dmaman = devm_kzalloc(dev, sizeof(*dmaman), GFP_KERNEL); + if (!dmaman) + return -ENOMEM; + + mutex_init(&dmaman->lock); + vc_dmaman_init(dmaman, base, chans_available); + g_dmaman = dmaman; + dmaman_dev = dev; + + dev_info(dev, "DMA legacy API manager, dmachans=0x%x\n", + chans_available); + + return 0; +} +EXPORT_SYMBOL(bcm_dmaman_probe); + +int bcm_dmaman_remove(struct platform_device *pdev) +{ + dmaman_dev = NULL; + + return 0; +} +EXPORT_SYMBOL(bcm_dmaman_remove); + +MODULE_LICENSE("GPL"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/dma/bcm2835-dma.c linux/drivers/dma/bcm2835-dma.c --- linux-6.1.66/drivers/dma/bcm2835-dma.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/dma/bcm2835-dma.c 2023-12-13 11:50:53.599973045 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:21 @ * Copyright 2012 Marvell International Ltd. */ #include <linux/dmaengine.h> +#include <linux/dma-direct.h> #include <linux/dma-mapping.h> #include <linux/dmapool.h> #include <linux/err.h> @ linux/arch/arm/boot/dts/bcm2708.dtsi:29 @ #include <linux/interrupt.h> #include <linux/list.h> #include <linux/module.h> +#include <linux/platform_data/dma-bcm2708.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/io.h> @ linux/arch/arm/boot/dts/bcm2708.dtsi:41 @ #define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14 #define BCM2835_DMA_CHAN_NAME_SIZE 8 +#define BCM2835_DMA_BULK_MASK BIT(0) +#define BCM2711_DMA_MEMCPY_CHAN 14 + +struct bcm2835_dma_cfg_data { + u64 dma_mask; + u32 chan_40bit_mask; +}; /** * struct bcm2835_dmadev - BCM2835 DMA controller @ linux/arch/arm/boot/dts/bcm2708.dtsi:60 @ struct dma_device ddev; void __iomem *base; dma_addr_t zero_page; + const struct bcm2835_dma_cfg_data *cfg_data; }; struct bcm2835_dma_cb { @ linux/arch/arm/boot/dts/bcm2708.dtsi:73 @ uint32_t pad[2]; }; +struct bcm2711_dma40_scb { + uint32_t ti; + uint32_t src; + uint32_t srci; + uint32_t dst; + uint32_t dsti; + uint32_t len; + uint32_t next_cb; + uint32_t rsvd; +}; + struct bcm2835_cb_entry { struct bcm2835_dma_cb *cb; dma_addr_t paddr; @ linux/arch/arm/boot/dts/bcm2708.dtsi:104 @ unsigned int irq_flags; bool is_lite_channel; + bool is_40bit_channel; + bool is_2712; }; struct bcm2835_desc { @ linux/arch/arm/boot/dts/bcm2708.dtsi:162 @ #define BCM2835_DMA_S_WIDTH BIT(9) /* 128bit writes if set */ #define BCM2835_DMA_S_DREQ BIT(10) /* enable SREQ for source */ #define BCM2835_DMA_S_IGNORE BIT(11) /* ignore source reads - read 0 */ -#define BCM2835_DMA_BURST_LENGTH(x) ((x & 15) << 12) +#define BCM2835_DMA_BURST_LENGTH(x) (((x) & 15) << 12) +#define BCM2835_DMA_GET_BURST_LENGTH(x) (((x) >> 12) & 15) +#define BCM2835_DMA_CS_FLAGS(x) (x & (BCM2835_DMA_PRIORITY(15) | \ + BCM2835_DMA_PANIC_PRIORITY(15) | \ + BCM2835_DMA_WAIT_FOR_WRITES | \ + BCM2835_DMA_DIS_DEBUG)) #define BCM2835_DMA_PER_MAP(x) ((x & 31) << 16) /* REQ source */ #define BCM2835_DMA_WAIT(x) ((x & 31) << 21) /* add DMA-wait cycles */ #define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */ +/* A fake bit to request that the driver doesn't set the WAIT_RESP bit. */ +#define BCM2835_DMA_NO_WAIT_RESP BIT(27) +#define WAIT_RESP(x) ((x & BCM2835_DMA_NO_WAIT_RESP) ? \ + 0 : BCM2835_DMA_WAIT_RESP) + +/* A fake bit to request that the driver requires wide reads */ +#define BCM2835_DMA_WIDE_SOURCE BIT(24) +#define WIDE_SOURCE(x) ((x & BCM2835_DMA_WIDE_SOURCE) ? \ + BCM2835_DMA_S_WIDTH : 0) + +/* A fake bit to request that the driver requires wide writes */ +#define BCM2835_DMA_WIDE_DEST BIT(25) +#define WIDE_DEST(x) ((x & BCM2835_DMA_WIDE_DEST) ? \ + BCM2835_DMA_D_WIDTH : 0) + +/* A fake bit to request that the driver requires multi-beat burst */ +#define BCM2835_DMA_BURST BIT(30) +#define BURST_LENGTH(x) ((x & BCM2835_DMA_BURST) ? \ + BCM2835_DMA_BURST_LENGTH(3) : 0) + + /* debug register bits */ #define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR BIT(0) #define BCM2835_DMA_DEBUG_FIFO_ERR BIT(1) @ linux/arch/arm/boot/dts/bcm2708.dtsi:217 @ #define BCM2835_DMA_DATA_TYPE_S128 16 /* Valid only for channels 0 - 14, 15 has its own base address */ -#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */ +#define BCM2835_DMA_CHAN_SIZE 0x100 +#define BCM2835_DMA_CHAN(n) ((n) * BCM2835_DMA_CHAN_SIZE) /* Base address */ #define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n)) /* the max dma length for different channels */ #define MAX_DMA_LEN SZ_1G #define MAX_LITE_DMA_LEN (SZ_64K - 4) +/* 40-bit DMA support */ +#define BCM2711_DMA40_CS 0x00 +#define BCM2711_DMA40_CB 0x04 +#define BCM2711_DMA40_DEBUG 0x0c +#define BCM2711_DMA40_TI 0x10 +#define BCM2711_DMA40_SRC 0x14 +#define BCM2711_DMA40_SRCI 0x18 +#define BCM2711_DMA40_DEST 0x1c +#define BCM2711_DMA40_DESTI 0x20 +#define BCM2711_DMA40_LEN 0x24 +#define BCM2711_DMA40_NEXT_CB 0x28 +#define BCM2711_DMA40_DEBUG2 0x2c + +#define BCM2711_DMA40_ACTIVE BIT(0) +#define BCM2711_DMA40_END BIT(1) +#define BCM2711_DMA40_INT BIT(2) +#define BCM2711_DMA40_DREQ BIT(3) /* DREQ state */ +#define BCM2711_DMA40_RD_PAUSED BIT(4) /* Reading is paused */ +#define BCM2711_DMA40_WR_PAUSED BIT(5) /* Writing is paused */ +#define BCM2711_DMA40_DREQ_PAUSED BIT(6) /* Is paused by DREQ flow control */ +#define BCM2711_DMA40_WAITING_FOR_WRITES BIT(7) /* Waiting for last write */ +// we always want to run in supervisor mode +#define BCM2711_DMA40_PROT (BIT(8)|BIT(9)) +#define BCM2711_DMA40_ERR BIT(10) +#define BCM2711_DMA40_QOS(x) (((x) & 0x1f) << 16) +#define BCM2711_DMA40_PANIC_QOS(x) (((x) & 0x1f) << 20) +#define BCM2711_DMA40_TRANSACTIONS BIT(25) +#define BCM2711_DMA40_WAIT_FOR_WRITES BIT(28) +#define BCM2711_DMA40_DISDEBUG BIT(29) +#define BCM2711_DMA40_ABORT BIT(30) +#define BCM2711_DMA40_HALT BIT(31) + +#define BCM2711_DMA40_CS_FLAGS(x) (x & (BCM2711_DMA40_QOS(15) | \ + BCM2711_DMA40_PANIC_QOS(15) | \ + BCM2711_DMA40_WAIT_FOR_WRITES | \ + BCM2711_DMA40_DISDEBUG)) + +/* Transfer information bits */ +#define BCM2711_DMA40_INTEN BIT(0) +#define BCM2711_DMA40_TDMODE BIT(1) /* 2D-Mode */ +#define BCM2711_DMA40_WAIT_RESP BIT(2) /* wait for AXI write to be acked */ +#define BCM2711_DMA40_WAIT_RD_RESP BIT(3) /* wait for AXI read to complete */ +#define BCM2711_DMA40_PER_MAP(x) ((x & 31) << 9) /* REQ source */ +#define BCM2711_DMA40_S_DREQ BIT(14) /* enable SREQ for source */ +#define BCM2711_DMA40_D_DREQ BIT(15) /* enable DREQ for destination */ +#define BCM2711_DMA40_S_WAIT(x) ((x & 0xff) << 16) /* add DMA read-wait cycles */ +#define BCM2711_DMA40_D_WAIT(x) ((x & 0xff) << 24) /* add DMA write-wait cycles */ + +/* debug register bits */ +#define BCM2711_DMA40_DEBUG_WRITE_ERR BIT(0) +#define BCM2711_DMA40_DEBUG_FIFO_ERR BIT(1) +#define BCM2711_DMA40_DEBUG_READ_ERR BIT(2) +#define BCM2711_DMA40_DEBUG_READ_CB_ERR BIT(3) +#define BCM2711_DMA40_DEBUG_IN_ON_ERR BIT(8) +#define BCM2711_DMA40_DEBUG_ABORT_ON_ERR BIT(9) +#define BCM2711_DMA40_DEBUG_HALT_ON_ERR BIT(10) +#define BCM2711_DMA40_DEBUG_DISABLE_CLK_GATE BIT(11) +#define BCM2711_DMA40_DEBUG_RSTATE_SHIFT 14 +#define BCM2711_DMA40_DEBUG_RSTATE_BITS 4 +#define BCM2711_DMA40_DEBUG_WSTATE_SHIFT 18 +#define BCM2711_DMA40_DEBUG_WSTATE_BITS 4 +#define BCM2711_DMA40_DEBUG_RESET BIT(23) +#define BCM2711_DMA40_DEBUG_ID_SHIFT 24 +#define BCM2711_DMA40_DEBUG_ID_BITS 4 +#define BCM2711_DMA40_DEBUG_VERSION_SHIFT 28 +#define BCM2711_DMA40_DEBUG_VERSION_BITS 4 + +/* Valid only for channels 0 - 3 (11 - 14) */ +#define BCM2711_DMA40_CHAN(n) (((n) + 11) << 8) /* Base address */ +#define BCM2711_DMA40_CHANIO(base, n) ((base) + BCM2711_DMA_CHAN(n)) + +/* the max dma length for different channels */ +#define MAX_DMA40_LEN SZ_1G + +#define BCM2711_DMA40_BURST_LEN(x) (((x) & 15) << 8) +#define BCM2711_DMA40_INC BIT(12) +#define BCM2711_DMA40_SIZE_32 (0 << 13) +#define BCM2711_DMA40_SIZE_64 (1 << 13) +#define BCM2711_DMA40_SIZE_128 (2 << 13) +#define BCM2711_DMA40_SIZE_256 (3 << 13) +#define BCM2711_DMA40_IGNORE BIT(15) +#define BCM2711_DMA40_STRIDE(x) ((x) << 16) /* For 2D mode */ + +#define BCM2711_DMA40_MEMCPY_FLAGS \ + (BCM2711_DMA40_QOS(0) | \ + BCM2711_DMA40_PANIC_QOS(0) | \ + BCM2711_DMA40_WAIT_FOR_WRITES | \ + BCM2711_DMA40_DISDEBUG) + +#define BCM2711_DMA40_MEMCPY_XFER_INFO \ + (BCM2711_DMA40_SIZE_128 | \ + BCM2711_DMA40_INC | \ + BCM2711_DMA40_BURST_LEN(16)) + +struct bcm2835_dmadev *memcpy_parent; +static void __iomem *memcpy_chan; +static struct bcm2711_dma40_scb *memcpy_scb; +static dma_addr_t memcpy_scb_dma; +DEFINE_SPINLOCK(memcpy_lock); + +static const struct bcm2835_dma_cfg_data bcm2835_dma_cfg = { + .chan_40bit_mask = 0, + .dma_mask = DMA_BIT_MASK(32), +}; + +static const struct bcm2835_dma_cfg_data bcm2711_dma_cfg = { + .chan_40bit_mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), + .dma_mask = DMA_BIT_MASK(36), +}; + +static const struct bcm2835_dma_cfg_data bcm2712_dma_cfg = { + .chan_40bit_mask = BIT(6) | BIT(7) | BIT(8) | BIT(9) | + BIT(10) | BIT(11), + .dma_mask = DMA_BIT_MASK(40), +}; + static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c) { /* lite and normal channels have different max frame length */ @ linux/arch/arm/boot/dts/bcm2708.dtsi:370 @ return container_of(t, struct bcm2835_desc, vd.tx); } +static inline uint32_t to_bcm2711_ti(uint32_t info) +{ + return ((info & BCM2835_DMA_INT_EN) ? BCM2711_DMA40_INTEN : 0) | + ((info & BCM2835_DMA_WAIT_RESP) ? BCM2711_DMA40_WAIT_RESP : 0) | + ((info & BCM2835_DMA_S_DREQ) ? + (BCM2711_DMA40_S_DREQ | BCM2711_DMA40_WAIT_RD_RESP) : 0) | + ((info & BCM2835_DMA_D_DREQ) ? BCM2711_DMA40_D_DREQ : 0) | + BCM2711_DMA40_PER_MAP((info >> 16) & 0x1f); +} + +static inline uint32_t to_bcm2711_srci(uint32_t info) +{ + return ((info & BCM2835_DMA_S_INC) ? BCM2711_DMA40_INC : 0) | + ((info & BCM2835_DMA_S_WIDTH) ? BCM2711_DMA40_SIZE_128 : 0) | + BCM2711_DMA40_BURST_LEN(BCM2835_DMA_GET_BURST_LENGTH(info)); +} + +static inline uint32_t to_bcm2711_dsti(uint32_t info) +{ + return ((info & BCM2835_DMA_D_INC) ? BCM2711_DMA40_INC : 0) | + ((info & BCM2835_DMA_D_WIDTH) ? BCM2711_DMA40_SIZE_128 : 0) | + BCM2711_DMA40_BURST_LEN(BCM2835_DMA_GET_BURST_LENGTH(info)); +} + +static inline uint32_t to_40bit_cbaddr(dma_addr_t addr) +{ + BUG_ON(addr & 0x1f); + return (addr >> 5); +} + static void bcm2835_dma_free_cb_chain(struct bcm2835_desc *desc) { size_t i; @ linux/arch/arm/boot/dts/bcm2708.dtsi:418 @ } static void bcm2835_dma_create_cb_set_length( - struct bcm2835_chan *chan, + struct bcm2835_chan *c, struct bcm2835_dma_cb *control_block, size_t len, size_t period_len, size_t *total_len, u32 finalextrainfo) { - size_t max_len = bcm2835_dma_max_frame_length(chan); + size_t max_len = bcm2835_dma_max_frame_length(c); + uint32_t cb_len; /* set the length taking lite-channel limitations into account */ - control_block->length = min_t(u32, len, max_len); + cb_len = min_t(u32, len, max_len); - /* finished if we have no period_length */ - if (!period_len) - return; + if (period_len) { + /* + * period_len means: that we need to generate + * transfers that are terminating at every + * multiple of period_len - this is typically + * used to set the interrupt flag in info + * which is required during cyclic transfers + */ - /* - * period_len means: that we need to generate - * transfers that are terminating at every - * multiple of period_len - this is typically - * used to set the interrupt flag in info - * which is required during cyclic transfers - */ + /* have we filled in period_length yet? */ + if (*total_len + cb_len < period_len) { + /* update number of bytes in this period so far */ + *total_len += cb_len; + } else { + /* calculate the length that remains to reach period_len */ + cb_len = period_len - *total_len; - /* have we filled in period_length yet? */ - if (*total_len + control_block->length < period_len) { - /* update number of bytes in this period so far */ - *total_len += control_block->length; - return; + /* reset total_length for next period */ + *total_len = 0; + } } - /* calculate the length that remains to reach period_length */ - control_block->length = period_len - *total_len; - - /* reset total_length for next period */ - *total_len = 0; - - /* add extrainfo bits in info */ - control_block->info |= finalextrainfo; + if (c->is_40bit_channel) { + struct bcm2711_dma40_scb *scb = + (struct bcm2711_dma40_scb *)control_block; + + scb->len = cb_len; + /* add extrainfo bits to ti */ + scb->ti |= to_bcm2711_ti(finalextrainfo); + } else { + control_block->length = cb_len; + /* add extrainfo bits to info */ + control_block->info |= finalextrainfo; + } } static inline size_t bcm2835_dma_count_frames_for_sg( @ linux/arch/arm/boot/dts/bcm2708.dtsi:487 @ /** * bcm2835_dma_create_cb_chain - create a control block and fills data in * - * @chan: the @dma_chan for which we run this + * @c: the @bcm2835_chan for which we run this * @direction: the direction in which we transfer * @cyclic: it is a cyclic transfer * @info: the default info bits to apply per controlblock @ linux/arch/arm/boot/dts/bcm2708.dtsi:505 @ * @gfp: the GFP flag to use for allocation */ static struct bcm2835_desc *bcm2835_dma_create_cb_chain( - struct dma_chan *chan, enum dma_transfer_direction direction, + struct bcm2835_chan *c, enum dma_transfer_direction direction, bool cyclic, u32 info, u32 finalextrainfo, size_t frames, dma_addr_t src, dma_addr_t dst, size_t buf_len, size_t period_len, gfp_t gfp) { - struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); size_t len = buf_len, total_len; size_t frame; struct bcm2835_desc *d; @ linux/arch/arm/boot/dts/bcm2708.dtsi:541 @ /* fill in the control block */ control_block = cb_entry->cb; - control_block->info = info; - control_block->src = src; - control_block->dst = dst; - control_block->stride = 0; - control_block->next = 0; + if (c->is_40bit_channel) { + struct bcm2711_dma40_scb *scb = + (struct bcm2711_dma40_scb *)control_block; + scb->ti = to_bcm2711_ti(info); + scb->src = lower_32_bits(src); + scb->srci= upper_32_bits(src) | to_bcm2711_srci(info); + scb->dst = lower_32_bits(dst); + scb->dsti = upper_32_bits(dst) | to_bcm2711_dsti(info); + scb->next_cb = 0; + } else { + control_block->info = info; + control_block->src = src; + control_block->dst = dst; + if (c->is_2712) + control_block->stride = (upper_32_bits(dst) << 8) | + upper_32_bits(src); + else + control_block->stride = 0; + control_block->next = 0; + } + /* set up length in control_block if requested */ if (buf_len) { /* calculate length honoring period_length */ @ linux/arch/arm/boot/dts/bcm2708.dtsi:571 @ cyclic ? finalextrainfo : 0); /* calculate new remaining length */ - len -= control_block->length; + if (c->is_40bit_channel) + len -= ((struct bcm2711_dma40_scb *)control_block)->len; + else + len -= control_block->length; } /* link this the last controlblock */ - if (frame) - d->cb_list[frame - 1].cb->next = cb_entry->paddr; + if (frame && c->is_40bit_channel) + ((struct bcm2711_dma40_scb *) + d->cb_list[frame - 1].cb)->next_cb = + to_40bit_cbaddr(cb_entry->paddr); + if (frame && !c->is_40bit_channel) + d->cb_list[frame - 1].cb->next = c->is_2712 ? + to_40bit_cbaddr(cb_entry->paddr) : cb_entry->paddr; /* update src and dst and length */ - if (src && (info & BCM2835_DMA_S_INC)) - src += control_block->length; - if (dst && (info & BCM2835_DMA_D_INC)) - dst += control_block->length; + if (src && (info & BCM2835_DMA_S_INC)) { + if (c->is_40bit_channel) + src += ((struct bcm2711_dma40_scb *)control_block)->len; + else + src += control_block->length; + } + + if (dst && (info & BCM2835_DMA_D_INC)) { + if (c->is_40bit_channel) + dst += ((struct bcm2711_dma40_scb *)control_block)->len; + else + dst += control_block->length; + } /* Length of total transfer */ - d->size += control_block->length; + if (c->is_40bit_channel) + d->size += ((struct bcm2711_dma40_scb *)control_block)->len; + else + d->size += control_block->length; } /* the last frame requires extra flags */ - d->cb_list[d->frames - 1].cb->info |= finalextrainfo; + if (c->is_40bit_channel) { + struct bcm2711_dma40_scb *scb = + (struct bcm2711_dma40_scb *)d->cb_list[d->frames-1].cb; + + scb->ti |= to_bcm2711_ti(finalextrainfo); + } else { + d->cb_list[d->frames - 1].cb->info |= finalextrainfo; + } /* detect a size missmatch */ if (buf_len && (d->size != buf_len)) @ linux/arch/arm/boot/dts/bcm2708.dtsi:630 @ } static void bcm2835_dma_fill_cb_chain_with_sg( - struct dma_chan *chan, + struct bcm2835_chan *c, enum dma_transfer_direction direction, struct bcm2835_cb_entry *cb, struct scatterlist *sgl, unsigned int sg_len) { - struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); size_t len, max_len; unsigned int i; dma_addr_t addr; @ linux/arch/arm/boot/dts/bcm2708.dtsi:643 @ max_len = bcm2835_dma_max_frame_length(c); for_each_sg(sgl, sgent, sg_len, i) { - for (addr = sg_dma_address(sgent), len = sg_dma_len(sgent); - len > 0; - addr += cb->cb->length, len -= cb->cb->length, cb++) { - if (direction == DMA_DEV_TO_MEM) - cb->cb->dst = addr; - else - cb->cb->src = addr; - cb->cb->length = min(len, max_len); + if (c->is_40bit_channel) { + struct bcm2711_dma40_scb *scb; + + for (addr = sg_dma_address(sgent), + len = sg_dma_len(sgent); + len > 0; + addr += scb->len, len -= scb->len, cb++) { + scb = (struct bcm2711_dma40_scb *)cb->cb; + if (direction == DMA_DEV_TO_MEM) { + scb->dst = lower_32_bits(addr); + scb->dsti = upper_32_bits(addr) | BCM2711_DMA40_INC; + } else { + scb->src = lower_32_bits(addr); + scb->srci = upper_32_bits(addr) | BCM2711_DMA40_INC; + } + scb->len = min(len, max_len); + } + } else { + for (addr = sg_dma_address(sgent), + len = sg_dma_len(sgent); + len > 0; + addr += cb->cb->length, len -= cb->cb->length, + cb++) { + if (direction == DMA_DEV_TO_MEM) + cb->cb->dst = addr; + else + cb->cb->src = addr; + cb->cb->length = min(len, max_len); + } } } } @ linux/arch/arm/boot/dts/bcm2708.dtsi:679 @ static void bcm2835_dma_abort(struct bcm2835_chan *c) { void __iomem *chan_base = c->chan_base; - long int timeout = 10000; + long timeout = 100; - /* - * A zero control block address means the channel is idle. - * (The ACTIVE flag in the CS register is not a reliable indicator.) - */ - if (!readl(chan_base + BCM2835_DMA_ADDR)) - return; + if (c->is_40bit_channel) { + /* + * A zero control block address means the channel is idle. + * (The ACTIVE flag in the CS register is not a reliable indicator.) + */ + if (!readl(chan_base + BCM2711_DMA40_CB)) + return; - /* Write 0 to the active bit - Pause the DMA */ - writel(0, chan_base + BCM2835_DMA_CS); + /* Pause the current DMA */ + writel(readl(chan_base + BCM2711_DMA40_CS) & ~BCM2711_DMA40_ACTIVE, + chan_base + BCM2711_DMA40_CS); + + /* wait for outstanding transactions to complete */ + while ((readl(chan_base + BCM2711_DMA40_CS) & BCM2711_DMA40_TRANSACTIONS) && + --timeout) + cpu_relax(); + + /* Peripheral might be stuck and fail to complete */ + if (!timeout) + dev_err(c->vc.chan.device->dev, + "failed to complete pause on dma %d (CS:%08x)\n", c->ch, + readl(chan_base + BCM2711_DMA40_CS)); + + /* Set CS back to default state */ + writel(BCM2711_DMA40_PROT, chan_base + BCM2711_DMA40_CS); + + /* Reset the DMA */ + writel(readl(chan_base + BCM2711_DMA40_DEBUG) | BCM2711_DMA40_DEBUG_RESET, + chan_base + BCM2711_DMA40_DEBUG); + } else { + /* + * A zero control block address means the channel is idle. + * (The ACTIVE flag in the CS register is not a reliable indicator.) + */ + if (!readl(chan_base + BCM2835_DMA_ADDR)) + return; - /* Wait for any current AXI transfer to complete */ - while ((readl(chan_base + BCM2835_DMA_CS) & - BCM2835_DMA_WAITING_FOR_WRITES) && --timeout) - cpu_relax(); + /* We need to clear the next DMA block pending */ + writel(0, chan_base + BCM2835_DMA_NEXTCB); - /* Peripheral might be stuck and fail to signal AXI write responses */ - if (!timeout) - dev_err(c->vc.chan.device->dev, - "failed to complete outstanding writes\n"); + /* Abort the DMA, which needs to be enabled to complete */ + writel(readl(chan_base + BCM2835_DMA_CS) | BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE, + chan_base + BCM2835_DMA_CS); + + /* wait for DMA to be aborted */ + while ((readl(chan_base + BCM2835_DMA_CS) & BCM2835_DMA_ABORT) && --timeout) + cpu_relax(); + + /* Write 0 to the active bit - Pause the DMA */ + writel(readl(chan_base + BCM2835_DMA_CS) & ~BCM2835_DMA_ACTIVE, + chan_base + BCM2835_DMA_CS); - writel(BCM2835_DMA_RESET, chan_base + BCM2835_DMA_CS); + /* + * Peripheral might be stuck and fail to complete + * This is expected when dreqs are enabled but not asserted + * so only report error in non dreq case + */ + if (!timeout && !(readl(chan_base + BCM2835_DMA_TI) & + (BCM2835_DMA_S_DREQ | BCM2835_DMA_D_DREQ))) + dev_err(c->vc.chan.device->dev, + "failed to complete pause on dma %d (CS:%08x)\n", c->ch, + readl(chan_base + BCM2835_DMA_CS)); + + /* Set CS back to default state and reset the DMA */ + writel(BCM2835_DMA_RESET, chan_base + BCM2835_DMA_CS); + } } static void bcm2835_dma_start_desc(struct bcm2835_chan *c) @ linux/arch/arm/boot/dts/bcm2708.dtsi:763 @ c->desc = d = to_bcm2835_dma_desc(&vd->tx); - writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR); - writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); + if (c->is_40bit_channel) { + writel(to_40bit_cbaddr(d->cb_list[0].paddr), + c->chan_base + BCM2711_DMA40_CB); + writel(BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT | BCM2711_DMA40_CS_FLAGS(c->dreq), + c->chan_base + BCM2711_DMA40_CS); + } else { + writel(BIT(31), c->chan_base + BCM2835_DMA_CS); + + writel(c->is_2712 ? to_40bit_cbaddr(d->cb_list[0].paddr) : d->cb_list[0].paddr, + c->chan_base + BCM2835_DMA_ADDR); + writel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq), + c->chan_base + BCM2835_DMA_CS); + } } static irqreturn_t bcm2835_dma_callback(int irq, void *data) @ linux/arch/arm/boot/dts/bcm2708.dtsi:802 @ * if this IRQ handler is threaded.) If the channel is finished, it * will remain idle despite the ACTIVE flag being set. */ - writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE, - c->chan_base + BCM2835_DMA_CS); + if (c->is_40bit_channel) + writel(BCM2835_DMA_INT | BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT | + BCM2711_DMA40_CS_FLAGS(c->dreq), + c->chan_base + BCM2711_DMA40_CS); + else + writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq), + c->chan_base + BCM2835_DMA_CS); d = c->desc; @ linux/arch/arm/boot/dts/bcm2708.dtsi:870 @ unsigned int i; size_t size; - for (size = i = 0; i < d->frames; i++) { - struct bcm2835_dma_cb *control_block = d->cb_list[i].cb; - size_t this_size = control_block->length; - dma_addr_t dma; + if (d->c->is_40bit_channel) { + for (size = i = 0; i < d->frames; i++) { + struct bcm2711_dma40_scb *control_block = + (struct bcm2711_dma40_scb *)d->cb_list[i].cb; + size_t this_size = control_block->len; + dma_addr_t dma; - if (d->dir == DMA_DEV_TO_MEM) - dma = control_block->dst; - else - dma = control_block->src; + if (d->dir == DMA_DEV_TO_MEM) + dma = control_block->dst; + else + dma = control_block->src; - if (size) - size += this_size; - else if (addr >= dma && addr < dma + this_size) - size += dma + this_size - addr; + if (size) + size += this_size; + else if (addr >= dma && addr < dma + this_size) + size += dma + this_size - addr; + } + } else { + for (size = i = 0; i < d->frames; i++) { + struct bcm2835_dma_cb *control_block = d->cb_list[i].cb; + size_t this_size = control_block->length; + dma_addr_t dma; + + if (d->dir == DMA_DEV_TO_MEM) + dma = control_block->dst; + else + dma = control_block->src; + + if (size) + size += this_size; + else if (addr >= dma && addr < dma + this_size) + size += dma + this_size - addr; + } } return size; @ linux/arch/arm/boot/dts/bcm2708.dtsi:929 @ struct bcm2835_desc *d = c->desc; dma_addr_t pos; - if (d->dir == DMA_MEM_TO_DEV) + if (d->dir == DMA_MEM_TO_DEV && c->is_40bit_channel) { + u64 lo_bits, hi_bits; + + lo_bits = readl(c->chan_base + BCM2711_DMA40_SRC); + hi_bits = readl(c->chan_base + BCM2711_DMA40_SRCI) & 0xff; + pos = (hi_bits << 32) | lo_bits; + } else if (d->dir == DMA_MEM_TO_DEV && !c->is_40bit_channel) { pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD); - else if (d->dir == DMA_DEV_TO_MEM) + } else if (d->dir == DMA_DEV_TO_MEM && c->is_40bit_channel) { + u64 lo_bits, hi_bits; + + lo_bits = readl(c->chan_base + BCM2711_DMA40_DEST); + hi_bits = readl(c->chan_base + BCM2711_DMA40_DESTI) & 0xff; + pos = (hi_bits << 32) | lo_bits; + } else if (d->dir == DMA_DEV_TO_MEM && !c->is_40bit_channel) { pos = readl(c->chan_base + BCM2835_DMA_DEST_AD); - else + } else { pos = 0; + } txstate->residue = bcm2835_dma_desc_size_pos(d, pos); } else { @ linux/arch/arm/boot/dts/bcm2708.dtsi:977 @ { struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); struct bcm2835_desc *d; - u32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC; - u32 extra = BCM2835_DMA_INT_EN | BCM2835_DMA_WAIT_RESP; + u32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC | + WAIT_RESP(c->dreq) | WIDE_SOURCE(c->dreq) | + WIDE_DEST(c->dreq) | BURST_LENGTH(c->dreq); + u32 extra = BCM2835_DMA_INT_EN; size_t max_len = bcm2835_dma_max_frame_length(c); size_t frames; @ linux/arch/arm/boot/dts/bcm2708.dtsi:992 @ frames = bcm2835_dma_frames_for_length(len, max_len); /* allocate the CB chain - this also fills in the pointers */ - d = bcm2835_dma_create_cb_chain(chan, DMA_MEM_TO_MEM, false, + d = bcm2835_dma_create_cb_chain(c, DMA_MEM_TO_MEM, false, info, extra, frames, src, dst, len, 0, GFP_KERNEL); if (!d) @ linux/arch/arm/boot/dts/bcm2708.dtsi:1010 @ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); struct bcm2835_desc *d; dma_addr_t src = 0, dst = 0; - u32 info = BCM2835_DMA_WAIT_RESP; + u32 info = WAIT_RESP(c->dreq) | WIDE_SOURCE(c->dreq) | + WIDE_DEST(c->dreq) | BURST_LENGTH(c->dreq); u32 extra = BCM2835_DMA_INT_EN; size_t frames; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1027 @ if (direction == DMA_DEV_TO_MEM) { if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) return NULL; - src = c->cfg.src_addr; + src = phys_to_dma(chan->device->dev, c->cfg.src_addr); info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC; } else { if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) return NULL; - dst = c->cfg.dst_addr; + dst = phys_to_dma(chan->device->dev, c->cfg.dst_addr); info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC; } @ linux/arch/arm/boot/dts/bcm2708.dtsi:1040 @ frames = bcm2835_dma_count_frames_for_sg(c, sgl, sg_len); /* allocate the CB chain */ - d = bcm2835_dma_create_cb_chain(chan, direction, false, + d = bcm2835_dma_create_cb_chain(c, direction, false, info, extra, frames, src, dst, 0, 0, GFP_NOWAIT); @ linux/arch/arm/boot/dts/bcm2708.dtsi:1048 @ return NULL; /* fill in frames with scatterlist pointers */ - bcm2835_dma_fill_cb_chain_with_sg(chan, direction, d->cb_list, + bcm2835_dma_fill_cb_chain_with_sg(c, direction, d->cb_list, sgl, sg_len); return vchan_tx_prep(&c->vc, &d->vd, flags); @ linux/arch/arm/boot/dts/bcm2708.dtsi:1063 @ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); struct bcm2835_desc *d; dma_addr_t src, dst; - u32 info = BCM2835_DMA_WAIT_RESP; + u32 info = WAIT_RESP(c->dreq) | WIDE_SOURCE(c->dreq) | + WIDE_DEST(c->dreq) | BURST_LENGTH(c->dreq); u32 extra = 0; size_t max_len = bcm2835_dma_max_frame_length(c); size_t frames; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1102 @ if (direction == DMA_DEV_TO_MEM) { if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) return NULL; - src = c->cfg.src_addr; + src = phys_to_dma(chan->device->dev, c->cfg.src_addr); dst = buf_addr; info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC; } else { if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) return NULL; - dst = c->cfg.dst_addr; + dst = phys_to_dma(chan->device->dev, c->cfg.dst_addr); src = buf_addr; info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1128 @ * note that we need to use GFP_NOWAIT, as the ALSA i2s dmaengine * implementation calls prep_dma_cyclic with interrupts disabled. */ - d = bcm2835_dma_create_cb_chain(chan, direction, true, + d = bcm2835_dma_create_cb_chain(c, direction, true, info, extra, frames, src, dst, buf_len, period_len, GFP_NOWAIT); @ linux/arch/arm/boot/dts/bcm2708.dtsi:1136 @ return NULL; /* wrap around into a loop */ - d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr; + if (c->is_40bit_channel) + ((struct bcm2711_dma40_scb *) + d->cb_list[frames - 1].cb)->next_cb = + to_40bit_cbaddr(d->cb_list[0].paddr); + else + d->cb_list[d->frames - 1].cb->next = c->is_2712 ? + to_40bit_cbaddr(d->cb_list[0].paddr) : d->cb_list[0].paddr; return vchan_tx_prep(&c->vc, &d->vd, flags); } @ linux/arch/arm/boot/dts/bcm2708.dtsi:1203 @ c->irq_number = irq; c->irq_flags = irq_flags; - /* check in DEBUG register if this is a LITE channel */ - if (readl(c->chan_base + BCM2835_DMA_DEBUG) & - BCM2835_DMA_DEBUG_LITE) + /* check for 40bit and lite channels */ + if (d->cfg_data->chan_40bit_mask & BIT(chan_id)) + c->is_40bit_channel = true; + else if (readl(c->chan_base + BCM2835_DMA_DEBUG) & + BCM2835_DMA_DEBUG_LITE) c->is_lite_channel = true; + if (d->cfg_data->dma_mask == DMA_BIT_MASK(40)) + c->is_2712 = true; return 0; } @ linux/arch/arm/boot/dts/bcm2708.dtsi:1229 @ DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); } +int bcm2711_dma40_memcpy_init(void) +{ + if (!memcpy_parent) + return -EPROBE_DEFER; + + if (!memcpy_chan) + return -EINVAL; + + if (!memcpy_scb) + return -ENOMEM; + + return 0; +} +EXPORT_SYMBOL(bcm2711_dma40_memcpy_init); + +void bcm2711_dma40_memcpy(dma_addr_t dst, dma_addr_t src, size_t size) +{ + struct bcm2711_dma40_scb *scb = memcpy_scb; + unsigned long flags; + + if (!scb) { + pr_err("bcm2711_dma40_memcpy not initialised!\n"); + return; + } + + spin_lock_irqsave(&memcpy_lock, flags); + + scb->ti = 0; + scb->src = lower_32_bits(src); + scb->srci = upper_32_bits(src) | BCM2711_DMA40_MEMCPY_XFER_INFO; + scb->dst = lower_32_bits(dst); + scb->dsti = upper_32_bits(dst) | BCM2711_DMA40_MEMCPY_XFER_INFO; + scb->len = size; + scb->next_cb = 0; + + writel(to_40bit_cbaddr(memcpy_scb_dma), memcpy_chan + BCM2711_DMA40_CB); + writel(BCM2711_DMA40_MEMCPY_FLAGS | BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT, + memcpy_chan + BCM2711_DMA40_CS); + + /* Poll for completion */ + while (!(readl(memcpy_chan + BCM2711_DMA40_CS) & BCM2711_DMA40_END)) + cpu_relax(); + + writel(BCM2711_DMA40_END | BCM2711_DMA40_PROT, memcpy_chan + BCM2711_DMA40_CS); + + spin_unlock_irqrestore(&memcpy_lock, flags); +} +EXPORT_SYMBOL(bcm2711_dma40_memcpy); + static const struct of_device_id bcm2835_dma_of_match[] = { - { .compatible = "brcm,bcm2835-dma", }, + { .compatible = "brcm,bcm2835-dma", .data = &bcm2835_dma_cfg }, + { .compatible = "brcm,bcm2711-dma", .data = &bcm2711_dma_cfg }, + { .compatible = "brcm,bcm2712-dma", .data = &bcm2712_dma_cfg }, {}, }; MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match); @ linux/arch/arm/boot/dts/bcm2708.dtsi:1304 @ static int bcm2835_dma_probe(struct platform_device *pdev) { + const struct bcm2835_dma_cfg_data *cfg_data; + const struct of_device_id *of_id; struct bcm2835_dmadev *od; struct resource *res; void __iomem *base; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1315 @ int irq_flags; uint32_t chans_available; char chan_name[BCM2835_DMA_CHAN_NAME_SIZE]; + int chan_count, chan_start, chan_end; + + of_id = of_match_node(bcm2835_dma_of_match, pdev->dev.of_node); + if (!of_id) { + dev_err(&pdev->dev, "Failed to match compatible string\n"); + return -EINVAL; + } + + cfg_data = of_id->data; if (!pdev->dev.dma_mask) pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; - rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + rc = dma_set_mask_and_coherent(&pdev->dev, cfg_data->dma_mask); if (rc) { dev_err(&pdev->dev, "Unable to set DMA mask\n"); return rc; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1345 @ if (IS_ERR(base)) return PTR_ERR(base); + /* The set of channels can be split across multiple instances. */ + chan_start = ((u32)(uintptr_t)base / BCM2835_DMA_CHAN_SIZE) & 0xf; + base -= BCM2835_DMA_CHAN(chan_start); + chan_count = resource_size(res) / BCM2835_DMA_CHAN_SIZE; + chan_end = min(chan_start + chan_count, + BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED + 1); + od->base = base; dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); @ linux/arch/arm/boot/dts/bcm2708.dtsi:1387 @ return -ENOMEM; } + of_id = of_match_node(bcm2835_dma_of_match, pdev->dev.of_node); + if (!of_id) { + dev_err(&pdev->dev, "Failed to match compatible string\n"); + return -EINVAL; + } + + od->cfg_data = cfg_data; + /* Request DMA channel mask from device tree */ if (of_property_read_u32(pdev->dev.of_node, "brcm,dma-channel-mask", @ linux/arch/arm/boot/dts/bcm2708.dtsi:1404 @ goto err_no_dma; } +#ifdef CONFIG_DMA_BCM2708 + /* One channel is reserved for the legacy API */ + if (chans_available & BCM2835_DMA_BULK_MASK) { + rc = bcm_dmaman_probe(pdev, base, + chans_available & BCM2835_DMA_BULK_MASK); + if (rc) + dev_err(&pdev->dev, + "Failed to initialize the legacy API\n"); + + chans_available &= ~BCM2835_DMA_BULK_MASK; + } +#endif + + /* And possibly one for the 40-bit DMA memcpy API */ + if (chans_available & od->cfg_data->chan_40bit_mask & + BIT(BCM2711_DMA_MEMCPY_CHAN)) { + memcpy_parent = od; + memcpy_chan = BCM2835_DMA_CHANIO(base, BCM2711_DMA_MEMCPY_CHAN); + memcpy_scb = dma_alloc_coherent(memcpy_parent->ddev.dev, + sizeof(*memcpy_scb), + &memcpy_scb_dma, GFP_KERNEL); + if (!memcpy_scb) + dev_warn(&pdev->dev, + "Failed to allocated memcpy scb\n"); + + chans_available &= ~BIT(BCM2711_DMA_MEMCPY_CHAN); + } + /* get irqs for each channel that we support */ - for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) { + for (i = chan_start; i < chan_end; i++) { /* skip masked out channels */ if (!(chans_available & (1 << i))) { irq[i] = -1; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1456 @ irq[i] = platform_get_irq(pdev, i < 11 ? i : 11); } + chan_count = 0; + /* get irqs for each channel */ - for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) { + for (i = chan_start; i < chan_end; i++) { /* skip channels without irq */ if (irq[i] < 0) continue; /* check if there are other channels that also use this irq */ + /* FIXME: This will fail if interrupts are shared across + instances */ irq_flags = 0; for (j = 0; j <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; j++) if ((i != j) && (irq[j] == irq[i])) { @ linux/arch/arm/boot/dts/bcm2708.dtsi:1478 @ rc = bcm2835_dma_chan_init(od, i, irq[i], irq_flags); if (rc) goto err_no_dma; + chan_count++; } - dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i); + dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", chan_count); /* Device-tree DMA controller registration */ rc = of_dma_controller_register(pdev->dev.of_node, @ linux/arch/arm/boot/dts/bcm2708.dtsi:1511 @ { struct bcm2835_dmadev *od = platform_get_drvdata(pdev); + bcm_dmaman_remove(pdev); dma_async_device_unregister(&od->ddev); + if (memcpy_parent == od) { + dma_free_coherent(&pdev->dev, sizeof(*memcpy_scb), memcpy_scb, + memcpy_scb_dma); + memcpy_parent = NULL; + memcpy_scb = NULL; + memcpy_chan = NULL; + } bcm2835_dma_free(od); return 0; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1534 @ }, }; -module_platform_driver(bcm2835_dma_driver); +static int bcm2835_dma_init(void) +{ + return platform_driver_register(&bcm2835_dma_driver); +} + +static void bcm2835_dma_exit(void) +{ + platform_driver_unregister(&bcm2835_dma_driver); +} + +/* + * Load after serial driver (arch_initcall) so we see the messages if it fails, + * but before drivers (module_init) that need a DMA channel. + */ +subsys_initcall(bcm2835_dma_init); +module_exit(bcm2835_dma_exit); MODULE_ALIAS("platform:bcm2835-dma"); MODULE_DESCRIPTION("BCM2835 DMA engine driver"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/dma/dw-axi-dmac/dw-axi-dmac.h linux/drivers/dma/dw-axi-dmac/dw-axi-dmac.h --- linux-6.1.66/drivers/dma/dw-axi-dmac/dw-axi-dmac.h 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/dma/dw-axi-dmac/dw-axi-dmac.h 2023-12-13 11:50:53.606973062 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:35 @ u32 axi_rw_burst_len; /* Register map for DMAX_NUM_CHANNELS <= 8 */ bool reg_map_8_channels; + /* Register map for DMAX_NUM_CHANNELS > 8 || DMAX_NUM_HS_IF > 16*/ + bool reg_map_cfg2; bool restrict_axi_burst_len; }; @ linux/arch/arm/boot/dts/bcm2708.dtsi:105 @ struct virt_dma_desc vd; struct axi_dma_chan *chan; + u32 hw_desc_count; u32 completed_blocks; u32 length; u32 period_len; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c linux/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c --- linux-6.1.66/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c 2023-12-13 11:50:53.605973059 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:15 @ #include <linux/device.h> #include <linux/dmaengine.h> #include <linux/dmapool.h> +#include <linux/dma-direct.h> #include <linux/dma-mapping.h> #include <linux/err.h> #include <linux/interrupt.h> @ linux/arch/arm/boot/dts/bcm2708.dtsi:83 @ iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4); } +static inline u64 +axi_chan_ioread64(struct axi_dma_chan *chan, u32 reg) +{ + /* + * We split one 64 bit read into two 32 bit reads as some HW doesn't + * support 64 bit access. + */ + return ((u64)ioread32(chan->chan_regs + reg + 4) << 32) + + ioread32(chan->chan_regs + reg); +} + static inline void axi_chan_config_write(struct axi_dma_chan *chan, struct axi_dma_chan_config *config) { @ linux/arch/arm/boot/dts/bcm2708.dtsi:101 @ cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS | config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS); - if (chan->chip->dw->hdata->reg_map_8_channels) { + if (!chan->chip->dw->hdata->reg_map_cfg2) { cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS | config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS | config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS | @ linux/arch/arm/boot/dts/bcm2708.dtsi:229 @ { int ret; u32 i; + int retries = 1000; + axi_dma_iowrite32(chip, DMAC_RESET, 1); + while (axi_dma_ioread32(chip, DMAC_RESET)) { + retries--; + if (!retries) { + dev_err(chip->dev, "%s: DMAC failed to reset\n", + __func__); + return; + } + cpu_relax(); + } for (i = 0; i < chip->dw->hdata->nr_channels; i++) { axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); axi_chan_disable(&chip->dw->chan[i]); @ linux/arch/arm/boot/dts/bcm2708.dtsi:302 @ static void axi_desc_put(struct axi_dma_desc *desc) { struct axi_dma_chan *chan = desc->chan; - int count = atomic_read(&chan->descs_allocated); + u32 count = desc->hw_desc_count; struct axi_dma_hw_desc *hw_desc; int descs_put; @ linux/arch/arm/boot/dts/bcm2708.dtsi:324 @ axi_desc_put(vd_to_axi_desc(vdesc)); } +static u32 axi_dma_desc_src_pos(struct axi_dma_desc *desc, dma_addr_t addr) +{ + unsigned int idx = 0; + u32 pos = 0; + + while (pos < desc->length) { + struct axi_dma_hw_desc *hw_desc = &desc->hw_desc[idx++]; + u32 len = hw_desc->len; + dma_addr_t start = le64_to_cpu(hw_desc->lli->sar); + + if (addr >= start && addr <= (start + len)) { + pos += addr - start; + break; + } + + pos += len; + } + + return pos; +} + +static u32 axi_dma_desc_dst_pos(struct axi_dma_desc *desc, dma_addr_t addr) +{ + unsigned int idx = 0; + u32 pos = 0; + + while (pos < desc->length) { + struct axi_dma_hw_desc *hw_desc = &desc->hw_desc[idx++]; + u32 len = hw_desc->len; + dma_addr_t start = le64_to_cpu(hw_desc->lli->dar); + + if (addr >= start && addr <= (start + len)) { + pos += addr - start; + break; + } + + pos += len; + } + + return pos; +} + static enum dma_status dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie, struct dma_tx_state *txstate) @ linux/arch/arm/boot/dts/bcm2708.dtsi:375 @ enum dma_status status; u32 completed_length; unsigned long flags; - u32 completed_blocks; size_t bytes = 0; - u32 length; - u32 len; status = dma_cookie_status(dchan, cookie, txstate); if (status == DMA_COMPLETE || !txstate) @ linux/arch/arm/boot/dts/bcm2708.dtsi:384 @ spin_lock_irqsave(&chan->vc.lock, flags); vdesc = vchan_find_desc(&chan->vc, cookie); - if (vdesc) { - length = vd_to_axi_desc(vdesc)->length; - completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks; - len = vd_to_axi_desc(vdesc)->hw_desc[0].len; - completed_length = completed_blocks * len; - bytes = length - completed_length; + if (vdesc && vdesc == vchan_next_desc(&chan->vc)) { + /* This descriptor is in-progress */ + struct axi_dma_desc *desc = vd_to_axi_desc(vdesc); + dma_addr_t addr; + + if (chan->direction == DMA_MEM_TO_DEV) { + addr = axi_chan_ioread64(chan, CH_SAR); + completed_length = axi_dma_desc_src_pos(desc, addr); + } else if (chan->direction == DMA_DEV_TO_MEM) { + addr = axi_chan_ioread64(chan, CH_DAR); + completed_length = axi_dma_desc_dst_pos(desc, addr); + } else { + completed_length = 0; + } + bytes = desc->length - completed_length; + } else if (vdesc) { + /* Still in the queue so not started */ + bytes = vd_to_axi_desc(vdesc)->length; } - spin_unlock_irqrestore(&chan->vc.lock, flags); + if (chan->is_paused && status == DMA_IN_PROGRESS) + status = DMA_PAUSED; + dma_set_residue(txstate, bytes); + spin_unlock_irqrestore(&chan->vc.lock, flags); return status; } @ linux/arch/arm/boot/dts/bcm2708.dtsi:596 @ unsigned long reg_value, val; if (!chip->apb_regs) { - dev_err(chip->dev, "apb_regs not initialized\n"); + dev_dbg(chip->dev, "apb_regs not initialized\n"); return; } @ linux/arch/arm/boot/dts/bcm2708.dtsi:700 @ switch (chan->direction) { case DMA_MEM_TO_DEV: reg_width = __ffs(chan->config.dst_addr_width); - device_addr = chan->config.dst_addr; + device_addr = phys_to_dma(chan->chip->dev, chan->config.dst_addr); ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS | mem_width << CH_CTL_L_SRC_WIDTH_POS | + DWAXIDMAC_BURST_TRANS_LEN_1 << CH_CTL_L_DST_MSIZE_POS | + DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS | DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS | DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS; block_ts = len >> mem_width; break; case DMA_DEV_TO_MEM: reg_width = __ffs(chan->config.src_addr_width); - device_addr = chan->config.src_addr; + /* Prevent partial access units getting lost */ + if (mem_width > reg_width) + mem_width = reg_width; + device_addr = phys_to_dma(chan->chip->dev, chan->config.src_addr); ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS | mem_width << CH_CTL_L_DST_WIDTH_POS | + DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS | + DWAXIDMAC_BURST_TRANS_LEN_1 << CH_CTL_L_SRC_MSIZE_POS | DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS; block_ts = len >> reg_width; @ linux/arch/arm/boot/dts/bcm2708.dtsi:754 @ } hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1); - - ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS | - DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS; hw_desc->lli->ctl_lo = cpu_to_le32(ctllo); set_desc_src_master(hw_desc); @ linux/arch/arm/boot/dts/bcm2708.dtsi:848 @ src_addr += segment_len; } + desc->hw_desc_count = total_segments; + llp = desc->hw_desc[0].llp; /* Managed transfer list */ @ linux/arch/arm/boot/dts/bcm2708.dtsi:929 @ } while (len >= segment_len); } + desc->hw_desc_count = loop; + /* Set end-of-link to the last link descriptor of list */ set_desc_last(&desc->hw_desc[num_sgs - 1]); @ linux/arch/arm/boot/dts/bcm2708.dtsi:1038 @ num++; } + desc->hw_desc_count = num; + /* Set end-of-link to the last link descriptor of list */ set_desc_last(&desc->hw_desc[num - 1]); /* Managed transfer list */ @ linux/arch/arm/boot/dts/bcm2708.dtsi:1088 @ static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, struct axi_dma_desc *desc_head) { - int count = atomic_read(&chan->descs_allocated); + u32 count = desc_head->hw_desc_count; int i; for (i = 0; i < count; i++) @ linux/arch/arm/boot/dts/bcm2708.dtsi:1131 @ static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan) { - int count = atomic_read(&chan->descs_allocated); struct axi_dma_hw_desc *hw_desc; struct axi_dma_desc *desc; struct virt_dma_desc *vd; unsigned long flags; + u32 count; u64 llp; int i; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1157 @ if (chan->cyclic) { desc = vd_to_axi_desc(vd); if (desc) { + count = desc->hw_desc_count; llp = lo_hi_readq(chan->chan_regs + CH_LLP); for (i = 0; i < count; i++) { hw_desc = &desc->hw_desc[i]; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1401 @ chip->dw->hdata->nr_channels = tmp; if (tmp <= DMA_REG_MAP_CH_REF) chip->dw->hdata->reg_map_8_channels = true; + else + chip->dw->hdata->reg_map_cfg2 = true; ret = device_property_read_u32(dev, "snps,dma-masters", &tmp); if (ret) @ linux/arch/arm/boot/dts/bcm2708.dtsi:1412 @ chip->dw->hdata->nr_masters = tmp; + ret = device_property_read_u32(dev, "snps,dma-targets", &tmp); + if (!ret && tmp > 16) + chip->dw->hdata->reg_map_cfg2 = true; + ret = device_property_read_u32(dev, "snps,data-width", &tmp); if (ret) return ret; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/dma/Kconfig linux/drivers/dma/Kconfig --- linux-6.1.66/drivers/dma/Kconfig 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/dma/Kconfig 2023-12-13 11:50:53.593973031 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:708 @ UniPhier platform. This DMA controller can transfer data from memory to memory, memory to peripheral and peripheral to memory. +config DMA_BCM2708 + tristate "BCM2708 DMA legacy API support" + depends on DMA_BCM2835 + config XGENE_DMA tristate "APM X-Gene DMA support" depends on ARCH_XGENE || COMPILE_TEST diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/dma/Makefile linux/drivers/dma/Makefile --- linux-6.1.66/drivers/dma/Makefile 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/dma/Makefile 2023-12-13 11:50:53.593973031 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:25 @ obj-$(CONFIG_AT_XDMAC) += at_xdmac.o obj-$(CONFIG_AXI_DMAC) += dma-axi-dmac.o obj-$(CONFIG_BCM_SBA_RAID) += bcm-sba-raid.o +obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o obj-$(CONFIG_DMA_JZ4780) += dma-jz4780.o obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/firmware/psci/psci.c linux/drivers/firmware/psci/psci.c --- linux-6.1.66/drivers/firmware/psci/psci.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/firmware/psci/psci.c 2023-12-13 11:50:53.767973441 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:317 @ * reset_type[30:0] = 0 (SYSTEM_WARM_RESET) * cookie = 0 (ignored by the implementation) */ - invoke_psci_fn(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2), 0, 0, 0); + // Allow extra arguments separated by spaces after + // the partition number. + unsigned long val; + u8 partition = 0; + + if (data && sscanf(data, "%lu", &val) == 1 && val < 63) + partition = val; + invoke_psci_fn(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2), 0, partition, 0); } else { invoke_psci_fn(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0); } diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/firmware/raspberrypi.c linux/drivers/firmware/raspberrypi.c --- linux-6.1.66/drivers/firmware/raspberrypi.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/firmware/raspberrypi.c 2023-12-13 11:50:53.769973446 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:15 @ #include <linux/module.h> #include <linux/of_platform.h> #include <linux/platform_device.h> +#include <linux/reboot.h> #include <linux/slab.h> #include <soc/bcm2835/raspberrypi-firmware.h> @ linux/arch/arm/boot/dts/bcm2708.dtsi:34 @ u32 enabled; struct kref consumers; + u32 get_throttled; }; +static struct platform_device *g_pdev; + static DEFINE_MUTEX(transaction_lock); static void response_callback(struct mbox_client *cl, void *msg) @ linux/arch/arm/boot/dts/bcm2708.dtsi:180 @ kfree(data); + if ((tag == RPI_FIRMWARE_GET_THROTTLED) && + memcmp(&fw->get_throttled, tag_data, sizeof(fw->get_throttled))) { + memcpy(&fw->get_throttled, tag_data, sizeof(fw->get_throttled)); + sysfs_notify(&fw->cl.dev->kobj, NULL, "get_throttled"); + } + return ret; } EXPORT_SYMBOL_GPL(rpi_firmware_property); +static int rpi_firmware_notify_reboot(struct notifier_block *nb, + unsigned long action, + void *data) +{ + struct rpi_firmware *fw; + struct platform_device *pdev = g_pdev; + u32 reboot_flags = 0; + + if (!pdev) + return 0; + + fw = platform_get_drvdata(pdev); + if (!fw) + return 0; + + // The partition id is the first parameter followed by zero or + // more flags separated by spaces indicating the reason for the reboot. + // + // 'tryboot': Sets a one-shot flag which is cleared upon reboot and + // causes the tryboot.txt to be loaded instead of config.txt + // by the bootloader and the start.elf firmware. + // + // This is intended to allow automatic fallback to a known + // good image if an OS/FW upgrade fails. + // + // N.B. The firmware mechanism for storing reboot flags may vary + // on different Raspberry Pi models. + if (data && strstr(data, " tryboot")) + reboot_flags |= 0x1; + + // The mailbox might have been called earlier, directly via vcmailbox + // so only overwrite if reboot flags are passed to the reboot command. + if (reboot_flags) + (void)rpi_firmware_property(fw, RPI_FIRMWARE_SET_REBOOT_FLAGS, + &reboot_flags, sizeof(reboot_flags)); + + (void)rpi_firmware_property(fw, RPI_FIRMWARE_NOTIFY_REBOOT, NULL, 0); + + return 0; +} + +static ssize_t get_throttled_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct rpi_firmware *fw = dev_get_drvdata(dev); + + WARN_ONCE(1, "deprecated, use hwmon sysfs instead\n"); + + return sprintf(buf, "%x\n", fw->get_throttled); +} + +static DEVICE_ATTR_RO(get_throttled); + +static struct attribute *rpi_firmware_dev_attrs[] = { + &dev_attr_get_throttled.attr, + NULL, +}; + +static const struct attribute_group rpi_firmware_dev_group = { + .attrs = rpi_firmware_dev_attrs, +}; + static void rpi_firmware_print_firmware_revision(struct rpi_firmware *fw) { time64_t date_and_time; u32 packet; + static const char * const variant_strs[] = { + "unknown", + "start", + "start_x", + "start_db", + "start_cd", + }; + const char *variant_str = "cmd unsupported"; + u32 variant; int ret = rpi_firmware_property(fw, RPI_FIRMWARE_GET_FIRMWARE_REVISION, &packet, sizeof(packet)); @ linux/arch/arm/boot/dts/bcm2708.dtsi:275 @ /* This is not compatible with y2038 */ date_and_time = packet; - dev_info(fw->cl.dev, "Attached to firmware from %ptT\n", &date_and_time); + + ret = rpi_firmware_property(fw, RPI_FIRMWARE_GET_FIRMWARE_VARIANT, + &variant, sizeof(variant)); + + if (!ret) { + if (variant >= ARRAY_SIZE(variant_strs)) + variant = 0; + variant_str = variant_strs[variant]; + } + + dev_info(fw->cl.dev, + "Attached to firmware from %ptT, variant %s\n", + &date_and_time, variant_str); +} + +static void +rpi_firmware_print_firmware_hash(struct rpi_firmware *fw) +{ + u32 hash[5]; + int ret = rpi_firmware_property(fw, + RPI_FIRMWARE_GET_FIRMWARE_HASH, + hash, sizeof(hash)); + + if (ret) + return; + + dev_info(fw->cl.dev, + "Firmware hash is %08x%08x%08x%08x%08x\n", + hash[0], hash[1], hash[2], hash[3], hash[4]); } static void @ linux/arch/arm/boot/dts/bcm2708.dtsi:318 @ rpi_hwmon = platform_device_register_data(dev, "raspberrypi-hwmon", -1, NULL, 0); + + if (!IS_ERR_OR_NULL(rpi_hwmon)) { + if (devm_device_add_group(dev, &rpi_firmware_dev_group)) + dev_err(dev, "Failed to create get_trottled attr\n"); + } } static void rpi_register_clk_driver(struct device *dev) @ linux/arch/arm/boot/dts/bcm2708.dtsi:345 @ -1, NULL, 0); } +unsigned int rpi_firmware_clk_get_max_rate(struct rpi_firmware *fw, unsigned int id) +{ + struct rpi_firmware_clk_rate_request msg = + RPI_FIRMWARE_CLK_RATE_REQUEST(id); + int ret; + + ret = rpi_firmware_property(fw, RPI_FIRMWARE_GET_MAX_CLOCK_RATE, + &msg, sizeof(msg)); + if (ret) + /* + * If our firmware doesn't support that operation, or fails, we + * assume the maximum clock rate is absolute maximum we can + * store over our type. + */ + return UINT_MAX; + + return le32_to_cpu(msg.rate); +} +EXPORT_SYMBOL_GPL(rpi_firmware_clk_get_max_rate); + static void rpi_firmware_delete(struct kref *kref) { struct rpi_firmware *fw = container_of(kref, struct rpi_firmware, @ linux/arch/arm/boot/dts/bcm2708.dtsi:417 @ kref_init(&fw->consumers); platform_set_drvdata(pdev, fw); + g_pdev = pdev; rpi_firmware_print_firmware_revision(fw); + rpi_firmware_print_firmware_hash(fw); rpi_register_hwmon_driver(dev, fw); rpi_register_clk_driver(dev); @ linux/arch/arm/boot/dts/bcm2708.dtsi:447 @ rpi_clk = NULL; rpi_firmware_put(fw); + g_pdev = NULL; return 0; } +static const struct of_device_id rpi_firmware_of_match[] = { + { .compatible = "raspberrypi,bcm2835-firmware", }, + {}, +}; +MODULE_DEVICE_TABLE(of, rpi_firmware_of_match); + +struct device_node *rpi_firmware_find_node(void) +{ + return of_find_matching_node(NULL, rpi_firmware_of_match); +} +EXPORT_SYMBOL_GPL(rpi_firmware_find_node); + /** * rpi_firmware_get - Get pointer to rpi_firmware structure. * @firmware_node: Pointer to the firmware Device Tree node. @ linux/arch/arm/boot/dts/bcm2708.dtsi:519 @ } EXPORT_SYMBOL_GPL(devm_rpi_firmware_get); -static const struct of_device_id rpi_firmware_of_match[] = { - { .compatible = "raspberrypi,bcm2835-firmware", }, - {}, -}; -MODULE_DEVICE_TABLE(of, rpi_firmware_of_match); - static struct platform_driver rpi_firmware_driver = { .driver = { .name = "raspberrypi-firmware", @ linux/arch/arm/boot/dts/bcm2708.dtsi:528 @ .shutdown = rpi_firmware_shutdown, .remove = rpi_firmware_remove, }; -module_platform_driver(rpi_firmware_driver); + +static struct notifier_block rpi_firmware_reboot_notifier = { + .notifier_call = rpi_firmware_notify_reboot, +}; + +static int __init rpi_firmware_init(void) +{ + int ret = register_reboot_notifier(&rpi_firmware_reboot_notifier); + if (ret) + goto out1; + ret = platform_driver_register(&rpi_firmware_driver); + if (ret) + goto out2; + + return 0; + +out2: + unregister_reboot_notifier(&rpi_firmware_reboot_notifier); +out1: + return ret; +} +core_initcall(rpi_firmware_init); + +static void __init rpi_firmware_exit(void) +{ + platform_driver_unregister(&rpi_firmware_driver); + unregister_reboot_notifier(&rpi_firmware_reboot_notifier); +} +module_exit(rpi_firmware_exit); MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); MODULE_DESCRIPTION("Raspberry Pi firmware driver"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpio/gpio-bcm-virt.c linux/drivers/gpio/gpio-bcm-virt.c --- linux-6.1.66/drivers/gpio/gpio-bcm-virt.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpio/gpio-bcm-virt.c 2023-12-13 11:50:53.801973521 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* + * brcmvirt GPIO driver + * + * Copyright (C) 2012,2013 Dom Cobley <popcornmix@gmail.com> + * Based on gpio-clps711x.c by Alexander Shiyan <shc_work@mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/err.h> +#include <linux/gpio.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <soc/bcm2835/raspberrypi-firmware.h> + +#define MODULE_NAME "brcmvirt-gpio" +#define NUM_GPIO 2 + +struct brcmvirt_gpio { + struct gpio_chip gc; + u32 __iomem *ts_base; + /* two packed 16-bit counts of enabled and disables + Allows host to detect a brief enable that was missed */ + u32 enables_disables[NUM_GPIO]; + dma_addr_t bus_addr; +}; + +static int brcmvirt_gpio_dir_in(struct gpio_chip *gc, unsigned off) +{ + struct brcmvirt_gpio *gpio; + gpio = container_of(gc, struct brcmvirt_gpio, gc); + return -EINVAL; +} + +static int brcmvirt_gpio_dir_out(struct gpio_chip *gc, unsigned off, int val) +{ + struct brcmvirt_gpio *gpio; + gpio = container_of(gc, struct brcmvirt_gpio, gc); + return 0; +} + +static int brcmvirt_gpio_get(struct gpio_chip *gc, unsigned off) +{ + struct brcmvirt_gpio *gpio; + unsigned v; + gpio = container_of(gc, struct brcmvirt_gpio, gc); + v = readl(gpio->ts_base + off); + return (s16)((v >> 16) - v) > 0; +} + +static void brcmvirt_gpio_set(struct gpio_chip *gc, unsigned off, int val) +{ + struct brcmvirt_gpio *gpio; + u16 enables, disables; + s16 diff; + bool lit; + gpio = container_of(gc, struct brcmvirt_gpio, gc); + enables = gpio->enables_disables[off] >> 16; + disables = gpio->enables_disables[off] >> 0; + diff = (s16)(enables - disables); + lit = diff > 0; + if ((val && lit) || (!val && !lit)) + return; + if (val) + enables++; + else + disables++; + diff = (s16)(enables - disables); + BUG_ON(diff != 0 && diff != 1); + gpio->enables_disables[off] = (enables << 16) | (disables << 0); + writel(gpio->enables_disables[off], gpio->ts_base + off); +} + +static int brcmvirt_gpio_probe(struct platform_device *pdev) +{ + int err = 0; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *fw_node; + struct rpi_firmware *fw; + struct brcmvirt_gpio *ucb; + u32 gpiovirtbuf; + + fw_node = of_parse_phandle(np, "firmware", 0); + if (!fw_node) { + dev_err(dev, "Missing firmware node\n"); + return -ENOENT; + } + + fw = rpi_firmware_get(fw_node); + if (!fw) + return -EPROBE_DEFER; + + ucb = devm_kzalloc(dev, sizeof *ucb, GFP_KERNEL); + if (!ucb) { + err = -EINVAL; + goto out; + } + + ucb->ts_base = dma_alloc_coherent(dev, PAGE_SIZE, &ucb->bus_addr, GFP_KERNEL); + if (!ucb->ts_base) { + pr_err("[%s]: failed to dma_alloc_coherent(%ld)\n", + __func__, PAGE_SIZE); + err = -ENOMEM; + goto out; + } + + gpiovirtbuf = (u32)ucb->bus_addr; + err = rpi_firmware_property(fw, RPI_FIRMWARE_FRAMEBUFFER_SET_GPIOVIRTBUF, + &gpiovirtbuf, sizeof(gpiovirtbuf)); + + if (err || gpiovirtbuf != 0) { + dev_warn(dev, "Failed to set gpiovirtbuf, trying to get err:%x\n", err); + dma_free_coherent(dev, PAGE_SIZE, ucb->ts_base, ucb->bus_addr); + ucb->ts_base = 0; + ucb->bus_addr = 0; + } + + if (!ucb->ts_base) { + err = rpi_firmware_property(fw, RPI_FIRMWARE_FRAMEBUFFER_GET_GPIOVIRTBUF, + &gpiovirtbuf, sizeof(gpiovirtbuf)); + + if (err) { + dev_err(dev, "Failed to get gpiovirtbuf\n"); + goto out; + } + + if (!gpiovirtbuf) { + dev_err(dev, "No virtgpio buffer\n"); + err = -ENOENT; + goto out; + } + + // mmap the physical memory + gpiovirtbuf &= ~0xc0000000; + ucb->ts_base = ioremap(gpiovirtbuf, 4096); + if (ucb->ts_base == NULL) { + dev_err(dev, "Failed to map physical address\n"); + err = -ENOENT; + goto out; + } + ucb->bus_addr = 0; + } + ucb->gc.label = MODULE_NAME; + ucb->gc.owner = THIS_MODULE; + //ucb->gc.dev = dev; + ucb->gc.of_node = np; + ucb->gc.base = 100; + ucb->gc.ngpio = NUM_GPIO; + + ucb->gc.direction_input = brcmvirt_gpio_dir_in; + ucb->gc.direction_output = brcmvirt_gpio_dir_out; + ucb->gc.get = brcmvirt_gpio_get; + ucb->gc.set = brcmvirt_gpio_set; + ucb->gc.can_sleep = true; + + err = gpiochip_add(&ucb->gc); + if (err) + goto out; + + platform_set_drvdata(pdev, ucb); + + return 0; +out: + if (ucb->bus_addr) { + dma_free_coherent(dev, PAGE_SIZE, ucb->ts_base, ucb->bus_addr); + ucb->bus_addr = 0; + ucb->ts_base = NULL; + } else if (ucb->ts_base) { + iounmap(ucb->ts_base); + ucb->ts_base = NULL; + } + return err; +} + +static int brcmvirt_gpio_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int err = 0; + struct brcmvirt_gpio *ucb = platform_get_drvdata(pdev); + + gpiochip_remove(&ucb->gc); + if (ucb->bus_addr) + dma_free_coherent(dev, PAGE_SIZE, ucb->ts_base, ucb->bus_addr); + else if (ucb->ts_base) + iounmap(ucb->ts_base); + return err; +} + +static const struct of_device_id __maybe_unused brcmvirt_gpio_ids[] = { + { .compatible = "brcm,bcm2835-virtgpio" }, + { } +}; +MODULE_DEVICE_TABLE(of, brcmvirt_gpio_ids); + +static struct platform_driver brcmvirt_gpio_driver = { + .driver = { + .name = MODULE_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(brcmvirt_gpio_ids), + }, + .probe = brcmvirt_gpio_probe, + .remove = brcmvirt_gpio_remove, +}; +module_platform_driver(brcmvirt_gpio_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Dom Cobley <popcornmix@gmail.com>"); +MODULE_DESCRIPTION("brcmvirt GPIO driver"); +MODULE_ALIAS("platform:brcmvirt-gpio"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpio/gpio-brcmstb.c linux/drivers/gpio/gpio-brcmstb.c --- linux-6.1.66/drivers/gpio/gpio-brcmstb.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpio/gpio-brcmstb.c 2023-12-13 11:50:53.802973523 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:53 @ struct irq_domain *irq_domain; struct irq_chip irq_chip; int parent_irq; - int gpio_base; int num_gpios; int parent_wake_irq; }; @ linux/arch/arm/boot/dts/bcm2708.dtsi:94 @ static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq, struct brcmstb_gpio_bank *bank) { - return hwirq - (bank->gc.base - bank->parent_priv->gpio_base); + return hwirq - bank->id * 32; } static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, @ linux/arch/arm/boot/dts/bcm2708.dtsi:119 @ static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) { struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc); + struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); /* gc_offset is relative to this gpio_chip; want real offset */ - int hwirq = offset + (gc->base - priv->gpio_base); + int hwirq = offset + bank->id * 32; if (hwirq >= priv->num_gpios) return -ENXIO; @ linux/arch/arm/boot/dts/bcm2708.dtsi:266 @ { struct brcmstb_gpio_priv *priv = bank->parent_priv; struct irq_domain *domain = priv->irq_domain; - int hwbase = bank->gc.base - priv->gpio_base; + int hwbase = bank->id * 32; unsigned long status; while ((status = brcmstb_gpio_get_active_irqs(bank))) { @ linux/arch/arm/boot/dts/bcm2708.dtsi:417 @ if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) return -EINVAL; - offset = gpiospec->args[0] - (gc->base - priv->gpio_base); + offset = gpiospec->args[0] - bank->id * 32; if (offset >= gc->ngpio || offset < 0) return -EINVAL; @ linux/arch/arm/boot/dts/bcm2708.dtsi:601 @ const __be32 *p; u32 bank_width; int num_banks = 0; + int num_gpios = 0; int err; - static int gpio_base; unsigned long flags = 0; bool need_wakeup_event = false; @ linux/arch/arm/boot/dts/bcm2708.dtsi:617 @ if (IS_ERR(reg_base)) return PTR_ERR(reg_base); - priv->gpio_base = gpio_base; priv->reg_base = reg_base; priv->pdev = pdev; @ linux/arch/arm/boot/dts/bcm2708.dtsi:642 @ #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN) flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER; #endif + if (of_property_read_bool(np, "brcm,gpio-direct")) + flags |= BGPIOF_REG_DIRECT; of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p, bank_width) { @ linux/arch/arm/boot/dts/bcm2708.dtsi:658 @ dev_dbg(dev, "Width 0 found: Empty bank @ %d\n", num_banks); num_banks++; - gpio_base += MAX_GPIO_PER_BANK; + num_gpios += MAX_GPIO_PER_BANK; continue; } @ linux/arch/arm/boot/dts/bcm2708.dtsi:693 @ } gc->owner = THIS_MODULE; - gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np); + gc->label = devm_kasprintf(dev, GFP_KERNEL, "gpio-brcmstb@%zx", + (size_t)res->start + + GIO_BANK_OFF(bank->id, 0)); if (!gc->label) { err = -ENOMEM; goto fail; } - gc->base = gpio_base; + gc->base = -1; gc->of_gpio_n_cells = 2; gc->of_xlate = brcmstb_gpio_of_xlate; /* not all ngpio lines are valid, will use bank width later */ - gc->ngpio = MAX_GPIO_PER_BANK; + gc->ngpio = bank_width; gc->offset = bank->id * MAX_GPIO_PER_BANK; if (priv->parent_irq > 0) gc->to_irq = brcmstb_gpio_to_irq; @ linux/arch/arm/boot/dts/bcm2708.dtsi:713 @ * Mask all interrupts by default, since wakeup interrupts may * be retained from S5 cold boot */ - need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); - gc->write_reg(reg_base + GIO_MASK(bank->id), 0); + if (priv->parent_irq > 0) { + need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); + gc->write_reg(reg_base + GIO_MASK(bank->id), 0); + } err = gpiochip_add_data(gc, bank); if (err) { @ linux/arch/arm/boot/dts/bcm2708.dtsi:724 @ bank->id); goto fail; } - gpio_base += gc->ngpio; + num_gpios += gc->ngpio; dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id, gc->base, gc->ngpio, bank->width); @ linux/arch/arm/boot/dts/bcm2708.dtsi:735 @ num_banks++; } - priv->num_gpios = gpio_base - priv->gpio_base; + priv->num_gpios = num_gpios; if (priv->parent_irq > 0) { err = brcmstb_gpio_irq_setup(pdev, priv); if (err) diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpio/gpio-fsm.c linux/drivers/gpio/gpio-fsm.c --- linux-6.1.66/drivers/gpio/gpio-fsm.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpio/gpio-fsm.c 2023-12-13 11:50:53.807973535 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0+ +/* + * GPIO FSM driver + * + * This driver implements simple state machines that allow real GPIOs to be + * controlled in response to inputs from other GPIOs - real and soft/virtual - + * and time delays. It can: + * + create dummy GPIOs for drivers that demand them + * + drive multiple GPIOs from a single input, with optional delays + * + add a debounce circuit to an input + * + drive pattern sequences onto LEDs + * etc. + * + * Copyright (C) 2020 Raspberry Pi (Trading) Ltd. + */ + +#include <linux/err.h> +#include <linux/gpio.h> +#include <linux/gpio/driver.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/sysfs.h> + +#include <dt-bindings/gpio/gpio-fsm.h> + +#define MODULE_NAME "gpio-fsm" + +#define GF_IO_TYPE(x) ((u32)(x) & 0xffff) +#define GF_IO_INDEX(x) ((u32)(x) >> 16) + +enum { + SIGNAL_GPIO, + SIGNAL_SOFT +}; + +enum { + INPUT_GPIO, + INPUT_SOFT +}; + +enum { + SYM_UNDEFINED, + SYM_NAME, + SYM_SET, + SYM_START, + SYM_SHUTDOWN, + + SYM_MAX +}; + +struct soft_gpio { + int dir; + int value; +}; + +struct input_gpio_state { + struct gpio_fsm *gf; + struct gpio_desc *desc; + struct fsm_state *target; + int index; + int value; + int irq; + bool enabled; + bool active_low; +}; + +struct gpio_event { + int index; + int value; + struct fsm_state *target; +}; + +struct symtab_entry { + const char *name; + void *value; + struct symtab_entry *next; +}; + +struct output_signal { + u8 type; + u8 value; + u16 index; +}; + +struct fsm_state { + const char *name; + struct output_signal *signals; + struct gpio_event *gpio_events; + struct gpio_event *soft_events; + struct fsm_state *delay_target; + struct fsm_state *shutdown_target; + unsigned int num_signals; + unsigned int num_gpio_events; + unsigned int num_soft_events; + unsigned int delay_ms; + unsigned int shutdown_ms; +}; + +struct gpio_fsm { + struct gpio_chip gc; + struct device *dev; + spinlock_t spinlock; + struct work_struct work; + struct timer_list timer; + wait_queue_head_t shutdown_event; + struct fsm_state *states; + struct input_gpio_state *input_gpio_states; + struct gpio_descs *input_gpios; + struct gpio_descs *output_gpios; + struct soft_gpio *soft_gpios; + struct fsm_state *start_state; + struct fsm_state *shutdown_state; + unsigned int num_states; + unsigned int num_output_gpios; + unsigned int num_input_gpios; + unsigned int num_soft_gpios; + unsigned int shutdown_timeout_ms; + unsigned int shutdown_jiffies; + + struct fsm_state *current_state; + struct fsm_state *next_state; + struct fsm_state *delay_target_state; + unsigned long delay_jiffies; + int delay_ms; + unsigned int debug; + bool shutting_down; + struct symtab_entry *symtab; +}; + +static struct symtab_entry *do_add_symbol(struct symtab_entry **symtab, + const char *name, void *value) +{ + struct symtab_entry **p = symtab; + + while (*p && strcmp((*p)->name, name)) + p = &(*p)->next; + + if (*p) { + /* This is an existing symbol */ + if ((*p)->value) { + /* Already defined */ + if (value) { + if ((uintptr_t)value < SYM_MAX) + return ERR_PTR(-EINVAL); + else + return ERR_PTR(-EEXIST); + } + } else { + /* Undefined */ + (*p)->value = value; + } + } else { + /* This is a new symbol */ + *p = kmalloc(sizeof(struct symtab_entry), GFP_KERNEL); + if (*p) { + (*p)->name = name; + (*p)->value = value; + (*p)->next = NULL; + } + } + return *p; +} + +static int add_symbol(struct symtab_entry **symtab, + const char *name, void *value) +{ + struct symtab_entry *sym = do_add_symbol(symtab, name, value); + + return PTR_ERR_OR_ZERO(sym); +} + +static struct symtab_entry *get_symbol(struct symtab_entry **symtab, + const char *name) +{ + struct symtab_entry *sym = do_add_symbol(symtab, name, NULL); + + if (IS_ERR(sym)) + return NULL; + return sym; +} + +static void free_symbols(struct symtab_entry **symtab) +{ + struct symtab_entry *sym = *symtab; + void *p; + + *symtab = NULL; + while (sym) { + p = sym; + sym = sym->next; + kfree(p); + } +} + +static void gpio_fsm_set_soft(struct gpio_fsm *gf, + unsigned int off, int val); + +static void gpio_fsm_enter_state(struct gpio_fsm *gf, + struct fsm_state *state) +{ + struct input_gpio_state *inp_state; + struct output_signal *signal; + struct gpio_event *event; + struct gpio_desc *gpiod; + struct soft_gpio *soft; + int value; + int i; + + dev_dbg(gf->dev, "enter_state(%s)\n", state->name); + + gf->current_state = state; + gf->delay_target_state = NULL; + + // 1. Apply any listed signals + for (i = 0; i < state->num_signals; i++) { + signal = &state->signals[i]; + + if (gf->debug) + dev_info(gf->dev, " set %s %d->%d\n", + (signal->type == SIGNAL_GPIO) ? "GF_OUT" : + "GF_SOFT", + signal->index, signal->value); + switch (signal->type) { + case SIGNAL_GPIO: + gpiod = gf->output_gpios->desc[signal->index]; + gpiod_set_value_cansleep(gpiod, signal->value); + break; + case SIGNAL_SOFT: + soft = &gf->soft_gpios[signal->index]; + gpio_fsm_set_soft(gf, signal->index, signal->value); + break; + } + } + + // 2. Exit if successfully reached shutdown state + if (gf->shutting_down && state == state->shutdown_target) { + wake_up(&gf->shutdown_event); + return; + } + + // 3. Schedule a timer callback if shutting down + if (state->shutdown_target) { + // Remember the absolute shutdown time in case remove is called + // at a later time. + gf->shutdown_jiffies = + jiffies + msecs_to_jiffies(state->shutdown_ms); + + if (gf->shutting_down) { + gf->delay_jiffies = gf->shutdown_jiffies; + gf->delay_target_state = state->shutdown_target; + gf->delay_ms = state->shutdown_ms; + mod_timer(&gf->timer, gf->delay_jiffies); + } + } + + // During shutdown, skip everything else + if (gf->shutting_down) + return; + + // Otherwise record what the shutdown time would be + gf->shutdown_jiffies = jiffies + msecs_to_jiffies(state->shutdown_ms); + + // 4. Check soft inputs for transitions to take + for (i = 0; i < state->num_soft_events; i++) { + event = &state->soft_events[i]; + if (gf->soft_gpios[event->index].value == event->value) { + if (gf->debug) + dev_info(gf->dev, + "GF_SOFT %d=%d -> %s\n", event->index, + event->value, event->target->name); + gpio_fsm_enter_state(gf, event->target); + return; + } + } + + // 5. Check GPIOs for transitions to take, enabling the IRQs + for (i = 0; i < state->num_gpio_events; i++) { + event = &state->gpio_events[i]; + inp_state = &gf->input_gpio_states[event->index]; + inp_state->target = event->target; + inp_state->value = event->value; + inp_state->enabled = true; + + value = gpiod_get_value_cansleep(gf->input_gpios->desc[event->index]); + + // Clear stale event state + disable_irq(inp_state->irq); + + irq_set_irq_type(inp_state->irq, + (inp_state->value ^ inp_state->active_low) ? + IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING); + enable_irq(inp_state->irq); + + if (value == event->value && inp_state->target) { + if (gf->debug) + dev_info(gf->dev, + "GF_IN %d=%d -> %s\n", event->index, + event->value, event->target->name); + gpio_fsm_enter_state(gf, event->target); + return; + } + } + + // 6. Schedule a timer callback if delay_target + if (state->delay_target) { + gf->delay_target_state = state->delay_target; + gf->delay_jiffies = jiffies + + msecs_to_jiffies(state->delay_ms); + gf->delay_ms = state->delay_ms; + mod_timer(&gf->timer, gf->delay_jiffies); + } +} + +static void gpio_fsm_go_to_state(struct gpio_fsm *gf, + struct fsm_state *new_state) +{ + struct input_gpio_state *inp_state; + struct gpio_event *gp_ev; + struct fsm_state *state; + int i; + + dev_dbg(gf->dev, "go_to_state(%s)\n", + new_state ? new_state->name : "<unset>"); + + state = gf->current_state; + + /* Disable any enabled GPIO IRQs */ + for (i = 0; i < state->num_gpio_events; i++) { + gp_ev = &state->gpio_events[i]; + inp_state = &gf->input_gpio_states[gp_ev->index]; + if (inp_state->enabled) { + inp_state->enabled = false; + irq_set_irq_type(inp_state->irq, + IRQF_TRIGGER_NONE); + } + } + + gpio_fsm_enter_state(gf, new_state); +} + +static void gpio_fsm_go_to_state_deferred(struct gpio_fsm *gf, + struct fsm_state *new_state) +{ + struct input_gpio_state *inp_state; + struct gpio_event *gp_ev; + struct fsm_state *state; + int i; + + dev_dbg(gf->dev, "go_to_state_deferred(%s)\n", + new_state ? new_state->name : "<unset>"); + + spin_lock(&gf->spinlock); + + if (gf->next_state) { + /* Something else has already requested a transition */ + spin_unlock(&gf->spinlock); + return; + } + + gf->next_state = new_state; + state = gf->current_state; + + /* Disarm any GPIO IRQs */ + for (i = 0; i < state->num_gpio_events; i++) { + gp_ev = &state->gpio_events[i]; + inp_state = &gf->input_gpio_states[gp_ev->index]; + inp_state->target = NULL; + } + + spin_unlock(&gf->spinlock); + + schedule_work(&gf->work); +} + +static void gpio_fsm_work(struct work_struct *work) +{ + struct fsm_state *new_state; + struct gpio_fsm *gf; + + gf = container_of(work, struct gpio_fsm, work); + spin_lock(&gf->spinlock); + new_state = gf->next_state; + gf->next_state = NULL; + spin_unlock(&gf->spinlock); + + gpio_fsm_go_to_state(gf, new_state); +} + +static irqreturn_t gpio_fsm_gpio_irq_handler(int irq, void *dev_id) +{ + struct input_gpio_state *inp_state = dev_id; + struct gpio_fsm *gf = inp_state->gf; + struct fsm_state *target; + + target = inp_state->target; + if (!target) + return IRQ_NONE; + + /* If the IRQ has fired then the desired state _must_ have occurred */ + inp_state->enabled = false; + irq_set_irq_type(inp_state->irq, IRQF_TRIGGER_NONE); + if (gf->debug) + dev_info(gf->dev, "GF_IN %d->%d -> %s\n", + inp_state->index, inp_state->value, target->name); + gpio_fsm_go_to_state_deferred(gf, target); + return IRQ_HANDLED; +} + +static void gpio_fsm_timer(struct timer_list *timer) +{ + struct gpio_fsm *gf = container_of(timer, struct gpio_fsm, timer); + struct fsm_state *target; + + target = gf->delay_target_state; + if (!target) + return; + if (gf->debug) + dev_info(gf->dev, "GF_DELAY %d -> %s\n", gf->delay_ms, + target->name); + + gpio_fsm_go_to_state_deferred(gf, target); +} + +int gpio_fsm_parse_signals(struct gpio_fsm *gf, struct fsm_state *state, + struct property *prop) +{ + const __be32 *cells = prop->value; + struct output_signal *signal; + u32 io; + u32 type; + u32 index; + u32 value; + int ret = 0; + int i; + + if (prop->length % 8) { + dev_err(gf->dev, "malformed set in state %s\n", + state->name); + return -EINVAL; + } + + state->num_signals = prop->length/8; + state->signals = devm_kcalloc(gf->dev, state->num_signals, + sizeof(struct output_signal), + GFP_KERNEL); + for (i = 0; i < state->num_signals; i++) { + signal = &state->signals[i]; + io = be32_to_cpu(cells[0]); + type = GF_IO_TYPE(io); + index = GF_IO_INDEX(io); + value = be32_to_cpu(cells[1]); + + if (type != GF_OUT && type != GF_SOFT) { + dev_err(gf->dev, + "invalid set type %d in state %s\n", + type, state->name); + ret = -EINVAL; + break; + } + if (type == GF_OUT && index >= gf->num_output_gpios) { + dev_err(gf->dev, + "invalid GF_OUT number %d in state %s\n", + index, state->name); + ret = -EINVAL; + break; + } + if (type == GF_SOFT && index >= gf->num_soft_gpios) { + dev_err(gf->dev, + "invalid GF_SOFT number %d in state %s\n", + index, state->name); + ret = -EINVAL; + break; + } + if (value != 0 && value != 1) { + dev_err(gf->dev, + "invalid set value %d in state %s\n", + value, state->name); + ret = -EINVAL; + break; + } + signal->type = (type == GF_OUT) ? SIGNAL_GPIO : SIGNAL_SOFT; + signal->index = index; + signal->value = value; + cells += 2; + } + + return ret; +} + +struct gpio_event *new_event(struct gpio_event **events, int *num_events) +{ + int num = ++(*num_events); + *events = krealloc(*events, num * sizeof(struct gpio_event), + GFP_KERNEL); + return *events ? *events + (num - 1) : NULL; +} + +int gpio_fsm_parse_events(struct gpio_fsm *gf, struct fsm_state *state, + struct property *prop) +{ + const __be32 *cells = prop->value; + struct symtab_entry *sym; + int num_cells; + int ret = 0; + int i; + + if (prop->length % 8) { + dev_err(gf->dev, + "malformed transitions from state %s to state %s\n", + state->name, prop->name); + return -EINVAL; + } + + sym = get_symbol(&gf->symtab, prop->name); + num_cells = prop->length / 4; + i = 0; + while (i < num_cells) { + struct gpio_event *gp_ev; + u32 event, param; + u32 index; + + event = be32_to_cpu(cells[i++]); + param = be32_to_cpu(cells[i++]); + index = GF_IO_INDEX(event); + + switch (GF_IO_TYPE(event)) { + case GF_IN: + if (index >= gf->num_input_gpios) { + dev_err(gf->dev, + "invalid GF_IN %d in transitions from state %s to state %s\n", + index, state->name, prop->name); + return -EINVAL; + } + if (param > 1) { + dev_err(gf->dev, + "invalid GF_IN value %d in transitions from state %s to state %s\n", + param, state->name, prop->name); + return -EINVAL; + } + gp_ev = new_event(&state->gpio_events, + &state->num_gpio_events); + if (!gp_ev) + return -ENOMEM; + gp_ev->index = index; + gp_ev->value = param; + gp_ev->target = (struct fsm_state *)sym; + break; + + case GF_SOFT: + if (index >= gf->num_soft_gpios) { + dev_err(gf->dev, + "invalid GF_SOFT %d in transitions from state %s to state %s\n", + index, state->name, prop->name); + return -EINVAL; + } + if (param > 1) { + dev_err(gf->dev, + "invalid GF_SOFT value %d in transitions from state %s to state %s\n", + param, state->name, prop->name); + return -EINVAL; + } + gp_ev = new_event(&state->soft_events, + &state->num_soft_events); + if (!gp_ev) + return -ENOMEM; + gp_ev->index = index; + gp_ev->value = param; + gp_ev->target = (struct fsm_state *)sym; + break; + + case GF_DELAY: + if (state->delay_target) { + dev_err(gf->dev, + "state %s has multiple GF_DELAYs\n", + state->name); + return -EINVAL; + } + state->delay_target = (struct fsm_state *)sym; + state->delay_ms = param; + break; + + case GF_SHUTDOWN: + if (state->shutdown_target == state) { + dev_err(gf->dev, + "shutdown state %s has GF_SHUTDOWN\n", + state->name); + return -EINVAL; + } else if (state->shutdown_target) { + dev_err(gf->dev, + "state %s has multiple GF_SHUTDOWNs\n", + state->name); + return -EINVAL; + } + state->shutdown_target = + (struct fsm_state *)sym; + state->shutdown_ms = param; + break; + + default: + dev_err(gf->dev, + "invalid event %08x in transitions from state %s to state %s\n", + event, state->name, prop->name); + return -EINVAL; + } + } + if (i != num_cells) { + dev_err(gf->dev, + "malformed transitions from state %s to state %s\n", + state->name, prop->name); + return -EINVAL; + } + + return ret; +} + +int gpio_fsm_parse_state(struct gpio_fsm *gf, + struct fsm_state *state, + struct device_node *np) +{ + struct symtab_entry *sym; + struct property *prop; + int ret; + + state->name = np->name; + ret = add_symbol(&gf->symtab, np->name, state); + if (ret) { + switch (ret) { + case -EINVAL: + dev_err(gf->dev, "'%s' is not a valid state name\n", + np->name); + break; + case -EEXIST: + dev_err(gf->dev, "state %s already defined\n", + np->name); + break; + default: + dev_err(gf->dev, "error %d adding state %s symbol\n", + ret, np->name); + break; + } + return ret; + } + + for_each_property_of_node(np, prop) { + sym = get_symbol(&gf->symtab, prop->name); + if (!sym) { + ret = -ENOMEM; + break; + } + + switch ((uintptr_t)sym->value) { + case SYM_SET: + ret = gpio_fsm_parse_signals(gf, state, prop); + break; + case SYM_START: + if (gf->start_state) { + dev_err(gf->dev, "multiple start states\n"); + ret = -EINVAL; + } else { + gf->start_state = state; + } + break; + case SYM_SHUTDOWN: + state->shutdown_target = state; + gf->shutdown_state = state; + break; + case SYM_NAME: + /* Ignore */ + break; + default: + /* A set of transition events to this state */ + ret = gpio_fsm_parse_events(gf, state, prop); + break; + } + } + + return ret; +} + +static void dump_all(struct gpio_fsm *gf) +{ + int i, j; + + dev_info(gf->dev, "Input GPIOs:\n"); + for (i = 0; i < gf->num_input_gpios; i++) + dev_info(gf->dev, " %d: %p\n", i, + gf->input_gpios->desc[i]); + + dev_info(gf->dev, "Output GPIOs:\n"); + for (i = 0; i < gf->num_output_gpios; i++) + dev_info(gf->dev, " %d: %p\n", i, + gf->output_gpios->desc[i]); + + dev_info(gf->dev, "Soft GPIOs:\n"); + for (i = 0; i < gf->num_soft_gpios; i++) + dev_info(gf->dev, " %d: %s %d\n", i, + (gf->soft_gpios[i].dir == GPIOF_DIR_IN) ? "IN" : "OUT", + gf->soft_gpios[i].value); + + dev_info(gf->dev, "Start state: %s\n", + gf->start_state ? gf->start_state->name : "-"); + + dev_info(gf->dev, "Shutdown timeout: %d ms\n", + gf->shutdown_timeout_ms); + + for (i = 0; i < gf->num_states; i++) { + struct fsm_state *state = &gf->states[i]; + + dev_info(gf->dev, "State %s:\n", state->name); + + if (state->shutdown_target == state) + dev_info(gf->dev, " Shutdown state\n"); + + dev_info(gf->dev, " Signals:\n"); + for (j = 0; j < state->num_signals; j++) { + struct output_signal *signal = &state->signals[j]; + + dev_info(gf->dev, " %d: %s %d=%d\n", j, + (signal->type == SIGNAL_GPIO) ? "GPIO" : + "SOFT", + signal->index, signal->value); + } + + dev_info(gf->dev, " GPIO events:\n"); + for (j = 0; j < state->num_gpio_events; j++) { + struct gpio_event *event = &state->gpio_events[j]; + + dev_info(gf->dev, " %d: %d=%d -> %s\n", j, + event->index, event->value, + event->target->name); + } + + dev_info(gf->dev, " Soft events:\n"); + for (j = 0; j < state->num_soft_events; j++) { + struct gpio_event *event = &state->soft_events[j]; + + dev_info(gf->dev, " %d: %d=%d -> %s\n", j, + event->index, event->value, + event->target->name); + } + + if (state->delay_target) + dev_info(gf->dev, " Delay: %d ms -> %s\n", + state->delay_ms, state->delay_target->name); + + if (state->shutdown_target && state->shutdown_target != state) + dev_info(gf->dev, " Shutdown: %d ms -> %s\n", + state->shutdown_ms, + state->shutdown_target->name); + } + dev_info(gf->dev, "\n"); +} + +static int resolve_sym_to_state(struct gpio_fsm *gf, struct fsm_state **pstate) +{ + struct symtab_entry *sym = (struct symtab_entry *)*pstate; + + if (!sym) + return -ENOMEM; + + *pstate = sym->value; + + if (!*pstate) { + dev_err(gf->dev, "state %s not defined\n", + sym->name); + return -EINVAL; + } + + return 0; +} + +static void gpio_fsm_set_soft(struct gpio_fsm *gf, + unsigned int off, int val) +{ + struct soft_gpio *sg = &gf->soft_gpios[off]; + struct gpio_event *gp_ev; + struct fsm_state *state; + int i; + + dev_dbg(gf->dev, "set(%d,%d)\n", off, val); + state = gf->current_state; + sg->value = val; + for (i = 0; i < state->num_soft_events; i++) { + gp_ev = &state->soft_events[i]; + if (gp_ev->index == off && gp_ev->value == val) { + if (gf->debug) + dev_info(gf->dev, + "GF_SOFT %d->%d -> %s\n", gp_ev->index, + gp_ev->value, gp_ev->target->name); + gpio_fsm_go_to_state(gf, gp_ev->target); + break; + } + } +} + +static int gpio_fsm_get(struct gpio_chip *gc, unsigned int off) +{ + struct gpio_fsm *gf = gpiochip_get_data(gc); + struct soft_gpio *sg; + + if (off >= gf->num_soft_gpios) + return -EINVAL; + sg = &gf->soft_gpios[off]; + + return sg->value; +} + +static void gpio_fsm_set(struct gpio_chip *gc, unsigned int off, int val) +{ + struct gpio_fsm *gf; + + gf = gpiochip_get_data(gc); + if (off < gf->num_soft_gpios) + gpio_fsm_set_soft(gf, off, val); +} + +static int gpio_fsm_get_direction(struct gpio_chip *gc, unsigned int off) +{ + struct gpio_fsm *gf = gpiochip_get_data(gc); + struct soft_gpio *sg; + + if (off >= gf->num_soft_gpios) + return -EINVAL; + sg = &gf->soft_gpios[off]; + + return sg->dir; +} + +static int gpio_fsm_direction_input(struct gpio_chip *gc, unsigned int off) +{ + struct gpio_fsm *gf = gpiochip_get_data(gc); + struct soft_gpio *sg; + + if (off >= gf->num_soft_gpios) + return -EINVAL; + sg = &gf->soft_gpios[off]; + sg->dir = GPIOF_DIR_IN; + + return 0; +} + +static int gpio_fsm_direction_output(struct gpio_chip *gc, unsigned int off, + int value) +{ + struct gpio_fsm *gf = gpiochip_get_data(gc); + struct soft_gpio *sg; + + if (off >= gf->num_soft_gpios) + return -EINVAL; + sg = &gf->soft_gpios[off]; + sg->dir = GPIOF_DIR_OUT; + gpio_fsm_set_soft(gf, off, value); + + return 0; +} + +/* + * /sys/class/gpio-fsm/<fsm-name>/ + * /state ... the current state + */ + +static ssize_t state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + const struct gpio_fsm *gf = dev_get_drvdata(dev); + + return sprintf(buf, "%s\n", gf->current_state->name); +} +static DEVICE_ATTR_RO(state); + +static ssize_t delay_state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + const struct gpio_fsm *gf = dev_get_drvdata(dev); + + return sprintf(buf, "%s\n", + gf->delay_target_state ? gf->delay_target_state->name : + "-"); +} + +static DEVICE_ATTR_RO(delay_state); + +static ssize_t delay_ms_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + const struct gpio_fsm *gf = dev_get_drvdata(dev); + int jiffies_left; + + jiffies_left = max((int)(gf->delay_jiffies - jiffies), 0); + return sprintf(buf, + gf->delay_target_state ? "%u\n" : "-\n", + jiffies_to_msecs(jiffies_left)); +} +static DEVICE_ATTR_RO(delay_ms); + +static struct attribute *gpio_fsm_attrs[] = { + &dev_attr_state.attr, + &dev_attr_delay_state.attr, + &dev_attr_delay_ms.attr, + NULL, +}; + +static const struct attribute_group gpio_fsm_group = { + .attrs = gpio_fsm_attrs, + //.is_visible = gpio_is_visible, +}; + +static const struct attribute_group *gpio_fsm_groups[] = { + &gpio_fsm_group, + NULL +}; + +static struct attribute *gpio_fsm_class_attrs[] = { + // There are no top-level attributes + NULL, +}; +ATTRIBUTE_GROUPS(gpio_fsm_class); + +static struct class gpio_fsm_class = { + .name = MODULE_NAME, + .owner = THIS_MODULE, + + .class_groups = gpio_fsm_class_groups, +}; + +static int gpio_fsm_probe(struct platform_device *pdev) +{ + struct input_gpio_state *inp_state; + struct device *dev = &pdev->dev; + struct device *sysfs_dev; + struct device_node *np = dev->of_node; + struct device_node *cp; + struct gpio_fsm *gf; + u32 debug = 0; + int num_states; + u32 num_soft_gpios; + int ret; + int i; + static const char *const reserved_symbols[] = { + [SYM_NAME] = "name", + [SYM_SET] = "set", + [SYM_START] = "start_state", + [SYM_SHUTDOWN] = "shutdown_state", + }; + + if (of_property_read_u32(np, "num-swgpios", &num_soft_gpios) && + of_property_read_u32(np, "num-soft-gpios", &num_soft_gpios)) { + dev_err(dev, "missing 'num-swgpios' property\n"); + return -EINVAL; + } + + of_property_read_u32(np, "debug", &debug); + + gf = devm_kzalloc(dev, sizeof(*gf), GFP_KERNEL); + if (!gf) + return -ENOMEM; + + gf->dev = dev; + gf->debug = debug; + + if (of_property_read_u32(np, "shutdown-timeout-ms", + &gf->shutdown_timeout_ms)) + gf->shutdown_timeout_ms = 5000; + + gf->num_soft_gpios = num_soft_gpios; + gf->soft_gpios = devm_kcalloc(dev, num_soft_gpios, + sizeof(struct soft_gpio), GFP_KERNEL); + if (!gf->soft_gpios) + return -ENOMEM; + for (i = 0; i < num_soft_gpios; i++) { + struct soft_gpio *sg = &gf->soft_gpios[i]; + + sg->dir = GPIOF_DIR_IN; + sg->value = 0; + } + + gf->input_gpios = devm_gpiod_get_array_optional(dev, "input", GPIOD_IN); + if (IS_ERR(gf->input_gpios)) { + ret = PTR_ERR(gf->input_gpios); + dev_err(dev, "failed to get input gpios from DT - %d\n", ret); + return ret; + } + gf->num_input_gpios = (gf->input_gpios ? gf->input_gpios->ndescs : 0); + + gf->input_gpio_states = devm_kcalloc(dev, gf->num_input_gpios, + sizeof(struct input_gpio_state), + GFP_KERNEL); + if (!gf->input_gpio_states) + return -ENOMEM; + for (i = 0; i < gf->num_input_gpios; i++) { + inp_state = &gf->input_gpio_states[i]; + inp_state->desc = gf->input_gpios->desc[i]; + inp_state->gf = gf; + inp_state->index = i; + inp_state->irq = gpiod_to_irq(inp_state->desc); + inp_state->active_low = gpiod_is_active_low(inp_state->desc); + if (inp_state->irq >= 0) + ret = devm_request_irq(gf->dev, inp_state->irq, + gpio_fsm_gpio_irq_handler, + IRQF_TRIGGER_NONE, + dev_name(dev), + inp_state); + else + ret = inp_state->irq; + + if (ret) { + dev_err(dev, + "failed to get IRQ for input gpio - %d\n", + ret); + return ret; + } + } + + gf->output_gpios = devm_gpiod_get_array_optional(dev, "output", + GPIOD_OUT_LOW); + if (IS_ERR(gf->output_gpios)) { + ret = PTR_ERR(gf->output_gpios); + dev_err(dev, "failed to get output gpios from DT - %d\n", ret); + return ret; + } + gf->num_output_gpios = (gf->output_gpios ? gf->output_gpios->ndescs : + 0); + + num_states = of_get_child_count(np); + if (!num_states) { + dev_err(dev, "no states declared\n"); + return -EINVAL; + } + gf->states = devm_kcalloc(dev, num_states, + sizeof(struct fsm_state), GFP_KERNEL); + if (!gf->states) + return -ENOMEM; + + // add reserved words to the symbol table + for (i = 0; i < ARRAY_SIZE(reserved_symbols); i++) { + if (reserved_symbols[i]) + add_symbol(&gf->symtab, reserved_symbols[i], + (void *)(uintptr_t)i); + } + + // parse the state + for_each_child_of_node(np, cp) { + struct fsm_state *state = &gf->states[gf->num_states]; + + ret = gpio_fsm_parse_state(gf, state, cp); + if (ret) + return ret; + gf->num_states++; + } + + if (!gf->start_state) { + dev_err(gf->dev, "no start state defined\n"); + return -EINVAL; + } + + // resolve symbol pointers into state pointers + for (i = 0; !ret && i < gf->num_states; i++) { + struct fsm_state *state = &gf->states[i]; + int j; + + for (j = 0; !ret && j < state->num_gpio_events; j++) { + struct gpio_event *ev = &state->gpio_events[j]; + + ret = resolve_sym_to_state(gf, &ev->target); + } + + for (j = 0; !ret && j < state->num_soft_events; j++) { + struct gpio_event *ev = &state->soft_events[j]; + + ret = resolve_sym_to_state(gf, &ev->target); + } + + if (!ret) { + resolve_sym_to_state(gf, &state->delay_target); + if (state->shutdown_target != state) + resolve_sym_to_state(gf, + &state->shutdown_target); + } + } + + if (!ret && gf->debug > 1) + dump_all(gf); + + free_symbols(&gf->symtab); + + if (ret) + return ret; + + gf->gc.parent = dev; + gf->gc.label = np->name; + gf->gc.owner = THIS_MODULE; + gf->gc.of_node = np; + gf->gc.base = -1; + gf->gc.ngpio = num_soft_gpios; + + gf->gc.get_direction = gpio_fsm_get_direction; + gf->gc.direction_input = gpio_fsm_direction_input; + gf->gc.direction_output = gpio_fsm_direction_output; + gf->gc.get = gpio_fsm_get; + gf->gc.set = gpio_fsm_set; + gf->gc.can_sleep = true; + spin_lock_init(&gf->spinlock); + INIT_WORK(&gf->work, gpio_fsm_work); + timer_setup(&gf->timer, gpio_fsm_timer, 0); + init_waitqueue_head(&gf->shutdown_event); + + platform_set_drvdata(pdev, gf); + + sysfs_dev = device_create_with_groups(&gpio_fsm_class, dev, + MKDEV(0, 0), gf, + gpio_fsm_groups, + "%s", np->name); + if (IS_ERR(sysfs_dev)) + dev_err(gf->dev, "Error creating sysfs entry\n"); + + if (gf->debug) + dev_info(gf->dev, "Start -> %s\n", gf->start_state->name); + + gpio_fsm_enter_state(gf, gf->start_state); + + return devm_gpiochip_add_data(dev, &gf->gc, gf); +} + +static int gpio_fsm_remove(struct platform_device *pdev) +{ + struct gpio_fsm *gf = platform_get_drvdata(pdev); + int i; + + if (gf->shutdown_state) { + if (gf->debug) + dev_info(gf->dev, "Shutting down...\n"); + + spin_lock(&gf->spinlock); + gf->shutting_down = true; + if (gf->current_state->shutdown_target && + gf->current_state->shutdown_target != gf->current_state) { + gf->delay_target_state = + gf->current_state->shutdown_target; + mod_timer(&gf->timer, gf->shutdown_jiffies); + } + spin_unlock(&gf->spinlock); + + wait_event_timeout(gf->shutdown_event, + gf->current_state->shutdown_target == + gf->current_state, + msecs_to_jiffies(gf->shutdown_timeout_ms)); + /* On failure to reach a shutdown state, jump to one */ + if (gf->current_state->shutdown_target != gf->current_state) + gpio_fsm_enter_state(gf, gf->shutdown_state); + } + cancel_work_sync(&gf->work); + del_timer_sync(&gf->timer); + + /* Events aren't allocated from managed storage */ + for (i = 0; i < gf->num_states; i++) { + kfree(gf->states[i].gpio_events); + kfree(gf->states[i].soft_events); + } + if (gf->debug) + dev_info(gf->dev, "Exiting\n"); + + return 0; +} + +static void gpio_fsm_shutdown(struct platform_device *pdev) +{ + gpio_fsm_remove(pdev); +} + +static const struct of_device_id gpio_fsm_ids[] = { + { .compatible = "rpi,gpio-fsm" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpio_fsm_ids); + +static struct platform_driver gpio_fsm_driver = { + .driver = { + .name = MODULE_NAME, + .of_match_table = of_match_ptr(gpio_fsm_ids), + }, + .probe = gpio_fsm_probe, + .remove = gpio_fsm_remove, + .shutdown = gpio_fsm_shutdown, +}; + +static int gpio_fsm_init(void) +{ + int ret; + + ret = class_register(&gpio_fsm_class); + if (ret) + return ret; + + ret = platform_driver_register(&gpio_fsm_driver); + if (ret) + class_unregister(&gpio_fsm_class); + + return ret; +} +module_init(gpio_fsm_init); + +static void gpio_fsm_exit(void) +{ + platform_driver_unregister(&gpio_fsm_driver); + class_unregister(&gpio_fsm_class); +} +module_exit(gpio_fsm_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Phil Elwell <phil@raspberrypi.com>"); +MODULE_DESCRIPTION("GPIO FSM driver"); +MODULE_ALIAS("platform:gpio-fsm"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpio/gpiolib.c linux/drivers/gpio/gpiolib.c --- linux-6.1.66/drivers/gpio/gpiolib.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpio/gpiolib.c 2023-12-13 11:50:53.847973629 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:55 @ #define extra_checks 0 #endif +#define dont_test_bit(b,d) (0) + /* Device and char device-related information */ static DEFINE_IDA(gpio_ida); static dev_t gpio_devt; @ linux/arch/arm/boot/dts/bcm2708.dtsi:2428 @ value = !!value; /* GPIOs used for enabled IRQs shall not be set as output */ - if (test_bit(FLAG_USED_AS_IRQ, &desc->flags) && - test_bit(FLAG_IRQ_IS_ENABLED, &desc->flags)) { + if (dont_test_bit(FLAG_USED_AS_IRQ, &desc->flags) && + dont_test_bit(FLAG_IRQ_IS_ENABLED, &desc->flags)) { gpiod_err(desc, "%s: tried to set a GPIO tied to an IRQ as output\n", __func__); @ linux/arch/arm/boot/dts/bcm2708.dtsi:3307 @ } /* To be valid for IRQ the line needs to be input or open drain */ - if (test_bit(FLAG_IS_OUT, &desc->flags) && - !test_bit(FLAG_OPEN_DRAIN, &desc->flags)) { + if (dont_test_bit(FLAG_IS_OUT, &desc->flags) && + !dont_test_bit(FLAG_OPEN_DRAIN, &desc->flags)) { chip_err(gc, "%s: tried to flag a GPIO set as output for IRQ\n", __func__); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpio/gpio-mmio.c linux/drivers/gpio/gpio-mmio.c --- linux-6.1.66/drivers/gpio/gpio-mmio.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpio/gpio-mmio.c 2023-12-13 11:50:53.817973559 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:235 @ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } +static void bgpio_set_direct(struct gpio_chip *gc, unsigned int gpio, int val) +{ + unsigned long mask = bgpio_line2mask(gc, gpio); + unsigned long flags; + + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + + gc->bgpio_data = gc->read_reg(gc->reg_dat); + + if (val) + gc->bgpio_data |= mask; + else + gc->bgpio_data &= ~mask; + + gc->write_reg(gc->reg_dat, gc->bgpio_data); + + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); +} + static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, int val) { @ linux/arch/arm/boot/dts/bcm2708.dtsi:346 @ gc->write_reg(gc->reg_clr, clear_mask); } +static void bgpio_set_multiple_direct(struct gpio_chip *gc, + unsigned long *mask, + unsigned long *bits) +{ + unsigned long flags; + unsigned long set_mask, clear_mask; + + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + + bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); + + gc->bgpio_data = gc->read_reg(gc->reg_dat); + + gc->bgpio_data |= set_mask; + gc->bgpio_data &= ~clear_mask; + + gc->write_reg(gc->reg_dat, gc->bgpio_data); + + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); +} + static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) { return 0; @ linux/arch/arm/boot/dts/bcm2708.dtsi:404 @ return 0; } +static int bgpio_dir_in_direct(struct gpio_chip *gc, unsigned int gpio) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + + if (gc->reg_dir_in) + gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in); + if (gc->reg_dir_out) + gc->bgpio_dir = gc->read_reg(gc->reg_dir_out); + + gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio); + + if (gc->reg_dir_in) + gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); + if (gc->reg_dir_out) + gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); + + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + + return 0; +} + static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) { /* Return 0 if output, 1 if input */ @ linux/arch/arm/boot/dts/bcm2708.dtsi:465 @ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } +static void bgpio_dir_out_direct(struct gpio_chip *gc, unsigned int gpio, + int val) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + + if (gc->reg_dir_in) + gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in); + if (gc->reg_dir_out) + gc->bgpio_dir = gc->read_reg(gc->reg_dir_out); + + gc->bgpio_dir |= bgpio_line2mask(gc, gpio); + + if (gc->reg_dir_in) + gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); + if (gc->reg_dir_out) + gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); + + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); +} + static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio, int val) { @ linux/arch/arm/boot/dts/bcm2708.dtsi:503 @ return 0; } +static int bgpio_dir_out_dir_first_direct(struct gpio_chip *gc, + unsigned int gpio, int val) +{ + bgpio_dir_out_direct(gc, gpio, val); + gc->set(gc, gpio, val); + return 0; +} + +static int bgpio_dir_out_val_first_direct(struct gpio_chip *gc, + unsigned int gpio, int val) +{ + gc->set(gc, gpio, val); + bgpio_dir_out_direct(gc, gpio, val); + return 0; +} + static int bgpio_setup_accessors(struct device *dev, struct gpio_chip *gc, bool byte_be) @ linux/arch/arm/boot/dts/bcm2708.dtsi:612 @ } else if (flags & BGPIOF_NO_OUTPUT) { gc->set = bgpio_set_none; gc->set_multiple = NULL; + } else if (flags & BGPIOF_REG_DIRECT) { + gc->set = bgpio_set_direct; + gc->set_multiple = bgpio_set_multiple_direct; } else { gc->set = bgpio_set; gc->set_multiple = bgpio_set_multiple; @ linux/arch/arm/boot/dts/bcm2708.dtsi:651 @ if (dirout || dirin) { gc->reg_dir_out = dirout; gc->reg_dir_in = dirin; - if (flags & BGPIOF_NO_SET_ON_INPUT) - gc->direction_output = bgpio_dir_out_dir_first; - else - gc->direction_output = bgpio_dir_out_val_first; - gc->direction_input = bgpio_dir_in; + if (flags & BGPIOF_REG_DIRECT) { + if (flags & BGPIOF_NO_SET_ON_INPUT) + gc->direction_output = + bgpio_dir_out_dir_first_direct; + else + gc->direction_output = + bgpio_dir_out_val_first_direct; + gc->direction_input = bgpio_dir_in_direct; + } else { + if (flags & BGPIOF_NO_SET_ON_INPUT) + gc->direction_output = bgpio_dir_out_dir_first; + else + gc->direction_output = bgpio_dir_out_val_first; + gc->direction_input = bgpio_dir_in; + } gc->get_direction = bgpio_get_dir; } else { if (flags & BGPIOF_NO_OUTPUT) diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpio/gpio-pca953x.c linux/drivers/gpio/gpio-pca953x.c --- linux-6.1.66/drivers/gpio/gpio-pca953x.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpio/gpio-pca953x.c 2023-12-13 11:50:53.821973568 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1361 @ { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, + { .compatible = "ti,tca9554", .data = OF_953X( 8, PCA_INT), }, { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpio/gpio-pwm.c linux/drivers/gpio/gpio-pwm.c --- linux-6.1.66/drivers/gpio/gpio-pwm.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpio/gpio-pwm.c 2023-12-13 11:50:53.823973573 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0+ +/* + * GPIO driver wrapping PWM API + * + * PWM 0% and PWM 100% are equivalent to digital GPIO + * outputs, and there are times where it is useful to use + * PWM outputs as straight GPIOs (eg outputs of NXP PCA9685 + * I2C PWM chip). This driver wraps the PWM API as a GPIO + * controller. + * + * Copyright (C) 2021 Raspberry Pi (Trading) Ltd. + */ + +#include <linux/err.h> +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> + +struct pwm_gpio { + struct gpio_chip gc; + struct pwm_device **pwm; +}; + +static int pwm_gpio_get_direction(struct gpio_chip *gc, unsigned int off) +{ + return GPIO_LINE_DIRECTION_OUT; +} + +static void pwm_gpio_set(struct gpio_chip *gc, unsigned int off, int val) +{ + struct pwm_gpio *pwm_gpio = gpiochip_get_data(gc); + struct pwm_state state; + + pwm_get_state(pwm_gpio->pwm[off], &state); + state.duty_cycle = val ? state.period : 0; + pwm_apply_state(pwm_gpio->pwm[off], &state); +} + +static int pwm_gpio_parse_dt(struct pwm_gpio *pwm_gpio, + struct device *dev) +{ + struct device_node *node = dev->of_node; + struct pwm_state state; + int ret = 0, i, num_gpios; + const char *pwm_name; + + if (!node) + return -ENODEV; + + num_gpios = of_property_count_strings(node, "pwm-names"); + if (num_gpios <= 0) + return 0; + + pwm_gpio->pwm = devm_kzalloc(dev, + sizeof(*pwm_gpio->pwm) * num_gpios, + GFP_KERNEL); + if (!pwm_gpio->pwm) + return -ENOMEM; + + for (i = 0; i < num_gpios; i++) { + ret = of_property_read_string_index(node, "pwm-names", i, + &pwm_name); + if (ret) { + dev_err(dev, "unable to get pwm device index %d, name %s", + i, pwm_name); + goto error; + } + + pwm_gpio->pwm[i] = devm_pwm_get(dev, pwm_name); + if (IS_ERR(pwm_gpio->pwm[i])) { + ret = PTR_ERR(pwm_gpio->pwm[i]); + if (ret != -EPROBE_DEFER) + dev_err(dev, "unable to request PWM\n"); + goto error; + } + + /* Sync up PWM state. */ + pwm_init_state(pwm_gpio->pwm[i], &state); + + state.duty_cycle = 0; + pwm_apply_state(pwm_gpio->pwm[i], &state); + } + + pwm_gpio->gc.ngpio = num_gpios; + +error: + return ret; +} + +static int pwm_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pwm_gpio *pwm_gpio; + int ret; + + pwm_gpio = devm_kzalloc(dev, sizeof(*pwm_gpio), GFP_KERNEL); + if (!pwm_gpio) + return -ENOMEM; + + pwm_gpio->gc.parent = dev; + pwm_gpio->gc.label = "pwm-gpio"; + pwm_gpio->gc.owner = THIS_MODULE; + pwm_gpio->gc.of_node = dev->of_node; + pwm_gpio->gc.base = -1; + + pwm_gpio->gc.get_direction = pwm_gpio_get_direction; + pwm_gpio->gc.set = pwm_gpio_set; + pwm_gpio->gc.can_sleep = true; + + ret = pwm_gpio_parse_dt(pwm_gpio, dev); + if (ret) + return ret; + + if (!pwm_gpio->gc.ngpio) + return 0; + + return devm_gpiochip_add_data(dev, &pwm_gpio->gc, pwm_gpio); +} + +static int pwm_gpio_remove(struct platform_device *pdev) +{ + return 0; +} + +static const struct of_device_id pwm_gpio_of_match[] = { + { .compatible = "pwm-gpio" }, + { } +}; +MODULE_DEVICE_TABLE(of, pwm_gpio_of_match); + +static struct platform_driver pwm_gpio_driver = { + .driver = { + .name = "pwm-gpio", + .of_match_table = of_match_ptr(pwm_gpio_of_match), + }, + .probe = pwm_gpio_probe, + .remove = pwm_gpio_remove, +}; +module_platform_driver(pwm_gpio_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com>"); +MODULE_DESCRIPTION("PWM GPIO driver"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpio/Kconfig linux/drivers/gpio/Kconfig --- linux-6.1.66/drivers/gpio/Kconfig 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpio/Kconfig 2023-12-13 11:50:53.796973509 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:197 @ help Say yes here to enable GPIO support for Broadcom XGS iProc SoCs. +config GPIO_BCM_VIRT + bool "Broadcom Virt GPIO" + depends on OF_GPIO && RASPBERRYPI_FIRMWARE && (ARCH_BCM2835 || COMPILE_TEST) + help + Turn on virtual GPIO support for Broadcom BCM283X chips. + config GPIO_BRCMSTB tristate "BRCMSTB GPIO support" default y if (ARCH_BRCMSTB || BMIPS_GENERIC) - depends on OF_GPIO && (ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST) + depends on OF_GPIO && (ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM2835 || COMPILE_TEST) select GPIO_GENERIC select IRQ_DOMAIN help @ linux/arch/arm/boot/dts/bcm2708.dtsi:503 @ help Say yes here to support Spreadtrum PMIC EIC device. +config GPIO_PWM + tristate "PWM chip GPIO" + depends on OF_GPIO + depends on PWM + help + Turn on support for exposing a PWM chip as a GPIO + driver. + config GPIO_PXA bool "PXA GPIO support" depends on ARCH_PXA || ARCH_MMP || COMPILE_TEST @ linux/arch/arm/boot/dts/bcm2708.dtsi:1254 @ several HTC phones. It provides basic support for input pins, output pins, and IRQs. +config GPIO_FSM + tristate "GPIO FSM support" + help + The GPIO FSM driver allows the creation of state machines for + manipulating GPIOs (both real and virtual), with state transitions + triggered by GPIO edges or delays. + + If unsure, say N. + config GPIO_JANZ_TTL tristate "Janz VMOD-TTL Digital IO Module" depends on MFD_JANZ_CMODIO diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpio/Makefile linux/drivers/gpio/Makefile --- linux-6.1.66/drivers/gpio/Makefile 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpio/Makefile 2023-12-13 11:50:53.796973509 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:40 @ obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o obj-$(CONFIG_GPIO_BCM_XGS_IPROC) += gpio-xgs-iproc.o +obj-$(CONFIG_GPIO_BCM_VIRT) += gpio-bcm-virt.o obj-$(CONFIG_GPIO_BD71815) += gpio-bd71815.o obj-$(CONFIG_GPIO_BD71828) += gpio-bd71828.o obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o @ linux/arch/arm/boot/dts/bcm2708.dtsi:63 @ obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o obj-$(CONFIG_GPIO_FTGPIO010) += gpio-ftgpio010.o +obj-$(CONFIG_GPIO_FSM) += gpio-fsm.o obj-$(CONFIG_GPIO_GE_FPGA) += gpio-ge.o obj-$(CONFIG_GPIO_GPIO_MM) += gpio-gpio-mm.o obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o @ linux/arch/arm/boot/dts/bcm2708.dtsi:125 @ obj-$(CONFIG_GPIO_PISOSR) += gpio-pisosr.o obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o +obj-$(CONFIG_GPIO_PWM) += gpio-pwm.o obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/bridge/Kconfig linux/drivers/gpu/drm/bridge/Kconfig --- linux-6.1.66/drivers/gpu/drm/bridge/Kconfig 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/bridge/Kconfig 2023-12-13 11:50:58.500984586 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:70 @ config DRM_DISPLAY_CONNECTOR tristate "Display connector support" depends on OF + select DRM_KMS_HELPER help Driver for display connectors with support for DDC and hot-plug detection. Most display controllers handle display connectors diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/bridge/panel.c linux/drivers/gpu/drm/bridge/panel.c --- linux-6.1.66/drivers/gpu/drm/bridge/panel.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/bridge/panel.c 2023-12-13 11:50:58.520984633 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:84 @ return ret; } + /* set up connector's "panel orientation" property */ + drm_connector_set_panel_orientation(&panel_bridge->connector, + panel_bridge->panel->orientation); + drm_connector_attach_encoder(&panel_bridge->connector, bridge->encoder); @ linux/arch/arm/boot/dts/bcm2708.dtsi:261 @ panel_bridge->bridge.ops = DRM_BRIDGE_OP_MODES; panel_bridge->bridge.type = connector_type; + panel_bridge->bridge.pre_enable_prev_first = + panel->prepare_upstream_first; + drm_bridge_add(&panel_bridge->bridge); return &panel_bridge->bridge; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/bridge/tc358762.c linux/drivers/gpu/drm/bridge/tc358762.c --- linux-6.1.66/drivers/gpu/drm/bridge/tc358762.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/bridge/tc358762.c 2023-12-13 11:50:58.529984654 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:232 @ ctx->bridge.funcs = &tc358762_bridge_funcs; ctx->bridge.type = DRM_MODE_CONNECTOR_DPI; ctx->bridge.of_node = dev->of_node; + ctx->bridge.pre_enable_prev_first = true; drm_bridge_add(&ctx->bridge); ret = mipi_dsi_attach(dsi); if (ret < 0) { drm_bridge_remove(&ctx->bridge); - dev_err(dev, "failed to attach dsi\n"); + dev_err_probe(dev, ret, "failed to attach dsi\n"); } return ret; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/drm_atomic.c linux/drivers/gpu/drm/drm_atomic.c --- linux-6.1.66/drivers/gpu/drm/drm_atomic.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/drm_atomic.c 2023-12-13 11:50:58.542984685 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:892 @ * or NULL if the private_obj is not part of the global atomic state. */ struct drm_private_state * -drm_atomic_get_old_private_obj_state(struct drm_atomic_state *state, +drm_atomic_get_old_private_obj_state(const struct drm_atomic_state *state, struct drm_private_obj *obj) { int i; @ linux/arch/arm/boot/dts/bcm2708.dtsi:914 @ * or NULL if the private_obj is not part of the global atomic state. */ struct drm_private_state * -drm_atomic_get_new_private_obj_state(struct drm_atomic_state *state, +drm_atomic_get_new_private_obj_state(const struct drm_atomic_state *state, struct drm_private_obj *obj) { int i; @ linux/arch/arm/boot/dts/bcm2708.dtsi:946 @ * not connected. */ struct drm_connector * -drm_atomic_get_old_connector_for_encoder(struct drm_atomic_state *state, +drm_atomic_get_old_connector_for_encoder(const struct drm_atomic_state *state, struct drm_encoder *encoder) { struct drm_connector_state *conn_state; @ linux/arch/arm/boot/dts/bcm2708.dtsi:980 @ * not connected. */ struct drm_connector * -drm_atomic_get_new_connector_for_encoder(struct drm_atomic_state *state, +drm_atomic_get_new_connector_for_encoder(const struct drm_atomic_state *state, struct drm_encoder *encoder) { struct drm_connector_state *conn_state; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1130 @ * the bridge is not part of the global atomic state. */ struct drm_bridge_state * -drm_atomic_get_old_bridge_state(struct drm_atomic_state *state, +drm_atomic_get_old_bridge_state(const struct drm_atomic_state *state, struct drm_bridge *bridge) { struct drm_private_state *obj_state; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1152 @ * the bridge is not part of the global atomic state. */ struct drm_bridge_state * -drm_atomic_get_new_bridge_state(struct drm_atomic_state *state, +drm_atomic_get_new_bridge_state(const struct drm_atomic_state *state, struct drm_bridge *bridge) { struct drm_private_state *obj_state; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/drm_atomic_helper.c linux/drivers/gpu/drm/drm_atomic_helper.c --- linux-6.1.66/drivers/gpu/drm/drm_atomic_helper.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/drm_atomic_helper.c 2023-12-13 11:50:58.543984687 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:446 @ new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); + if (!new_crtc_state->mode_changed && + !new_crtc_state->connectors_changed) { + continue; + } + /* * Each encoder has at most one connector (since we always steal * it away), so we won't call ->mode_fixup twice. @ linux/arch/arm/boot/dts/bcm2708.dtsi:1629 @ int i, ret; unsigned int crtc_mask = 0; - /* - * Legacy cursor ioctls are completely unsynced, and userspace - * relies on that (by doing tons of cursor updates). - */ - if (old_state->legacy_cursor_update) - return; - for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state, new_crtc_state, i) { if (!new_crtc_state->active) continue; @ linux/arch/arm/boot/dts/bcm2708.dtsi:2278 @ complete_all(&commit->flip_done); continue; } - - /* Legacy cursor updates are fully unsynced. */ - if (state->legacy_cursor_update) { - complete_all(&commit->flip_done); - continue; - } if (!new_crtc_state->event) { commit->event = kzalloc(sizeof(*commit->event), diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/drm_atomic_state_helper.c linux/drivers/gpu/drm/drm_atomic_state_helper.c --- linux-6.1.66/drivers/gpu/drm/drm_atomic_state_helper.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/drm_atomic_state_helper.c 2023-12-13 11:50:58.544984689 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:270 @ plane_state->color_range = val; } + if (plane->chroma_siting_h_property) { + if (!drm_object_property_get_default_value(&plane->base, + plane->chroma_siting_h_property, + &val)) + plane_state->chroma_siting_h = val; + } + + if (plane->chroma_siting_v_property) { + if (!drm_object_property_get_default_value(&plane->base, + plane->chroma_siting_v_property, + &val)) + plane_state->chroma_siting_v = val; + } + if (plane->zpos_property) { if (!drm_object_property_get_default_value(&plane->base, plane->zpos_property, diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/drm_atomic_uapi.c linux/drivers/gpu/drm/drm_atomic_uapi.c --- linux-6.1.66/drivers/gpu/drm/drm_atomic_uapi.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/drm_atomic_uapi.c 2023-12-13 11:50:58.544984689 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:565 @ state->color_encoding = val; } else if (property == plane->color_range_property) { state->color_range = val; + } else if (property == plane->chroma_siting_h_property) { + state->chroma_siting_h = val; + } else if (property == plane->chroma_siting_v_property) { + state->chroma_siting_v = val; } else if (property == config->prop_fb_damage_clips) { ret = drm_atomic_replace_property_blob_from_id(dev, &state->fb_damage_clips, @ linux/arch/arm/boot/dts/bcm2708.dtsi:635 @ *val = state->color_encoding; } else if (property == plane->color_range_property) { *val = state->color_range; + } else if (property == plane->chroma_siting_h_property) { + *val = state->chroma_siting_h; + } else if (property == plane->chroma_siting_v_property) { + *val = state->chroma_siting_v; } else if (property == config->prop_fb_damage_clips) { *val = (state->fb_damage_clips) ? state->fb_damage_clips->base.id : 0; @ linux/arch/arm/boot/dts/bcm2708.dtsi:682 @ { struct drm_device *dev = connector->dev; struct drm_mode_config *config = &dev->mode_config; + bool margins_updated = false; bool replaced = false; int ret; @ linux/arch/arm/boot/dts/bcm2708.dtsi:702 @ state->tv.subconnector = val; } else if (property == config->tv_left_margin_property) { state->tv.margins.left = val; + margins_updated = true; } else if (property == config->tv_right_margin_property) { state->tv.margins.right = val; + margins_updated = true; } else if (property == config->tv_top_margin_property) { state->tv.margins.top = val; + margins_updated = true; } else if (property == config->tv_bottom_margin_property) { state->tv.margins.bottom = val; + margins_updated = true; } else if (property == config->tv_mode_property) { state->tv.mode = val; } else if (property == config->tv_brightness_property) { @ linux/arch/arm/boot/dts/bcm2708.dtsi:792 @ return -EINVAL; } + if (margins_updated && state->crtc) { + ret = drm_atomic_add_affected_planes(state->state, state->crtc); + + return ret; + } + return 0; } diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/drm_color_mgmt.c linux/drivers/gpu/drm/drm_color_mgmt.c --- linux-6.1.66/drivers/gpu/drm/drm_color_mgmt.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/drm_color_mgmt.c 2023-12-13 11:50:58.549984701 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:333 @ replaced = drm_property_replace_blob(&crtc_state->degamma_lut, use_gamma_lut ? NULL : blob); replaced |= drm_property_replace_blob(&crtc_state->ctm, NULL); - replaced |= drm_property_replace_blob(&crtc_state->gamma_lut, + if (!crtc_state->gamma_lut || !crtc_state->gamma_lut->data || + memcmp(crtc_state->gamma_lut->data, blob_data, blob->length)) + replaced |= drm_property_replace_blob(&crtc_state->gamma_lut, use_gamma_lut ? blob : NULL); crtc_state->color_mgmt_changed |= replaced; @ linux/arch/arm/boot/dts/bcm2708.dtsi:594 @ EXPORT_SYMBOL(drm_plane_create_color_properties); /** + * drm_plane_create_chroma_siting_properties - chroma siting related plane properties + * @plane: plane object + * + * Create and attach plane specific CHROMA_SITING + * properties to @plane. + */ +int drm_plane_create_chroma_siting_properties(struct drm_plane *plane, + int32_t default_chroma_siting_h, + int32_t default_chroma_siting_v) +{ + struct drm_device *dev = plane->dev; + struct drm_property *prop; + + prop = drm_property_create_range(dev, 0, "CHROMA_SITING_H", + 0, 1<<16); + if (!prop) + return -ENOMEM; + plane->chroma_siting_h_property = prop; + drm_object_attach_property(&plane->base, prop, default_chroma_siting_h); + + prop = drm_property_create_range(dev, 0, "CHROMA_SITING_V", + 0, 1<<16); + if (!prop) + return -ENOMEM; + plane->chroma_siting_v_property = prop; + drm_object_attach_property(&plane->base, prop, default_chroma_siting_v); + + if (plane->state) { + plane->state->chroma_siting_h = default_chroma_siting_h; + plane->state->chroma_siting_v = default_chroma_siting_v; + } + return 0; +} +EXPORT_SYMBOL(drm_plane_create_chroma_siting_properties); + +/** * drm_color_lut_check - check validity of lookup table * @lut: property blob containing LUT to check * @tests: bitmask of tests to run diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/drm_connector.c linux/drivers/gpu/drm/drm_connector.c --- linux-6.1.66/drivers/gpu/drm/drm_connector.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/drm_connector.c 2023-12-13 11:50:58.550984703 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:84 @ int type; const char *name; struct ida ida; + int first_dyn_num; }; /* @ linux/arch/arm/boot/dts/bcm2708.dtsi:114 @ { DRM_MODE_CONNECTOR_USB, "USB" }, }; +#define MAX_DT_NODE_NAME_LEN 20 +#define DT_DRM_NODE_PREFIX "drm-" + +static void drm_connector_get_of_name(int type, char *node_name, int length) +{ + int i = 0; + + strcpy(node_name, DT_DRM_NODE_PREFIX); + + do { + node_name[i + strlen(DT_DRM_NODE_PREFIX)] = + tolower(drm_connector_enum_list[type].name[i]); + + } while (drm_connector_enum_list[type].name[i++] && + i < length); + + node_name[length - 1] = '\0'; +} + void drm_connector_ida_init(void) { - int i; + int i, id; + char node_name[MAX_DT_NODE_NAME_LEN]; - for (i = 0; i < ARRAY_SIZE(drm_connector_enum_list); i++) + for (i = 0; i < ARRAY_SIZE(drm_connector_enum_list); i++) { ida_init(&drm_connector_enum_list[i].ida); + + drm_connector_get_of_name(i, node_name, MAX_DT_NODE_NAME_LEN); + + id = of_alias_get_highest_id(node_name); + if (id > 0) + drm_connector_enum_list[i].first_dyn_num = id + 1; + else + drm_connector_enum_list[i].first_dyn_num = 1; + } } void drm_connector_ida_destroy(void) @ linux/arch/arm/boot/dts/bcm2708.dtsi:255 @ struct i2c_adapter *ddc) { struct drm_mode_config *config = &dev->mode_config; + char node_name[MAX_DT_NODE_NAME_LEN]; int ret; + int id; struct ida *connector_ida = &drm_connector_enum_list[connector_type].ida; @ linux/arch/arm/boot/dts/bcm2708.dtsi:287 @ ret = 0; connector->connector_type = connector_type; - connector->connector_type_id = - ida_alloc_min(connector_ida, 1, GFP_KERNEL); + connector->connector_type_id = 0; + + drm_connector_get_of_name(connector_type, node_name, MAX_DT_NODE_NAME_LEN); + id = of_alias_get_id(dev->dev->of_node, node_name); + if (id > 0) { + /* Try and allocate the requested ID + * Valid range is 1 to 31, hence ignoring 0 as an error + */ + int type_id = ida_alloc_range(connector_ida, id, id, GFP_KERNEL); + + if (type_id > 0) + connector->connector_type_id = type_id; + else + drm_err(dev, "Failed to acquire type ID %d for interface type %s, ret %d\n", + id, drm_connector_enum_list[connector_type].name, + type_id); + } + if (!connector->connector_type_id) + connector->connector_type_id = + ida_alloc_min(connector_ida, + drm_connector_enum_list[connector_type].first_dyn_num, + GFP_KERNEL); if (connector->connector_type_id < 0) { ret = connector->connector_type_id; goto out_put_id; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/drm_fb_helper.c linux/drivers/gpu/drm/drm_fb_helper.c --- linux-6.1.66/drivers/gpu/drm/drm_fb_helper.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/drm_fb_helper.c 2023-12-13 11:50:58.559984724 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1935 @ struct drm_device *dev = fb_helper->dev; struct fb_info *info; unsigned int width, height; - int ret; + int ret, id; width = dev->mode_config.max_width; height = dev->mode_config.max_height; @ linux/arch/arm/boot/dts/bcm2708.dtsi:1970 @ * register the fbdev emulation instance in kernel_fb_helper_list. */ mutex_unlock(&fb_helper->lock); + id = of_alias_get_highest_id("drm-fb"); + if (id >= 0) + fb_set_lowest_dynamic_fb(id + 1); + + id = of_alias_get_id(dev->dev->of_node, "drm-fb"); + if (id >= 0) { + info->node = id; + info->custom_fb_num = true; + } ret = register_framebuffer(info); if (ret < 0) return ret; diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/drm_panel.c linux/drivers/gpu/drm/drm_panel.c --- linux-6.1.66/drivers/gpu/drm/drm_panel.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/drm_panel.c 2023-12-13 11:50:58.573984757 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:64 @ panel->dev = dev; panel->funcs = funcs; panel->connector_type = connector_type; + + panel->orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; + of_drm_get_panel_orientation(dev->of_node, &panel->orientation); } EXPORT_SYMBOL(drm_panel_init); @ linux/arch/arm/boot/dts/bcm2708.dtsi:295 @ if (ret < 0) return ret; - if (rotation == 0) + if (rotation == 0) { *orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL; - else if (rotation == 90) + } else if (rotation == 90) { *orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP; - else if (rotation == 180) + } else if (rotation == 180) { *orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; - else if (rotation == 270) + } else if (rotation == 270) { *orientation = DRM_MODE_PANEL_ORIENTATION_LEFT_UP; - else + } else { + DRM_ERROR("%pOF: invalid orientation %d\n", np, ret); return -EINVAL; + } return 0; } diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/i915/display/intel_display.c linux/drivers/gpu/drm/i915/display/intel_display.c --- linux-6.1.66/drivers/gpu/drm/i915/display/intel_display.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/i915/display/intel_display.c 2023-12-13 11:50:58.657984955 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:7746 @ state->base.legacy_cursor_update = false; } + /* + * FIXME: Cut over to (async) commit helpers instead of hand-rolling + * everything. + */ + if (state->base.legacy_cursor_update) { + struct intel_crtc_state *new_crtc_state; + struct intel_crtc *crtc; + int i; + + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) + complete_all(&new_crtc_state->uapi.commit->flip_done); + } + ret = intel_atomic_prepare_commit(state); if (ret) { drm_dbg_atomic(&dev_priv->drm, diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/Kconfig linux/drivers/gpu/drm/Kconfig --- linux-6.1.66/drivers/gpu/drm/Kconfig 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/Kconfig 2023-12-13 11:50:53.847973629 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:67 @ bytes per callsite, the .data costs can be substantial, and are therefore configurable. +config DRM_KUNIT_TEST_HELPERS + tristate + depends on DRM && KUNIT + help + KUnit Helpers for KMS drivers. + config DRM_KUNIT_TEST tristate "KUnit tests for DRM" if !KUNIT_ALL_TESTS depends on DRM && KUNIT @ linux/arch/arm/boot/dts/bcm2708.dtsi:83 @ select DRM_KMS_HELPER select DRM_BUDDY select DRM_EXPORT_FOR_TESTS if m + select DRM_KUNIT_TEST_HELPERS default KUNIT_ALL_TESTS help This builds unit tests for DRM. This option is not useful for @ linux/arch/arm/boot/dts/bcm2708.dtsi:387 @ source "drivers/gpu/drm/vc4/Kconfig" +source "drivers/gpu/drm/rp1/Kconfig" + source "drivers/gpu/drm/etnaviv/Kconfig" source "drivers/gpu/drm/hisilicon/Kconfig" diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/Makefile linux/drivers/gpu/drm/Makefile --- linux-6.1.66/drivers/gpu/drm/Makefile 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/Makefile 2023-12-13 11:50:53.848973632 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:80 @ # Drivers and the rest # -obj-$(CONFIG_DRM_KUNIT_TEST) += tests/ +obj-y += tests/ obj-$(CONFIG_DRM_MIPI_DBI) += drm_mipi_dbi.o obj-$(CONFIG_DRM_MIPI_DSI) += drm_mipi_dsi.o @ linux/arch/arm/boot/dts/bcm2708.dtsi:151 @ obj-$(CONFIG_DRM_HYPERV) += hyperv/ obj-y += solomon/ obj-$(CONFIG_DRM_SPRD) += sprd/ +obj-y += rp1/ diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/msm/msm_atomic.c linux/drivers/gpu/drm/msm/msm_atomic.c --- linux-6.1.66/drivers/gpu/drm/msm/msm_atomic.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/msm/msm_atomic.c 2023-12-13 11:50:58.971985695 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:225 @ /* async updates are limited to single-crtc updates: */ WARN_ON(crtc_mask != drm_crtc_mask(async_crtc)); + complete_all(&async_crtc->state->commit->flip_done); + /* * Start timer if we don't already have an update pending * on this crtc: diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/panel/Kconfig linux/drivers/gpu/drm/panel/Kconfig --- linux-6.1.66/drivers/gpu/drm/panel/Kconfig 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/panel/Kconfig 2023-12-13 11:50:59.243986335 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:177 @ QVGA (240x320) RGB panels. support serial & parallel rgb interface. +config DRM_PANEL_ILITEK_ILI9806E + tristate "Ilitek ILI9806E-based panels" + depends on OF && SPI + select DRM_KMS_HELPER + depends on DRM_GEM_DMA_HELPER + depends on BACKLIGHT_CLASS_DEVICE + select DRM_MIPI_DBI + help + Say Y if you want to enable support for panels based on the + Ilitek ILI9806e controller. + config DRM_PANEL_ILITEK_ILI9881C tristate "Ilitek ILI9881C-based panels" depends on OF @ linux/arch/arm/boot/dts/bcm2708.dtsi:672 @ 24 bit RGB per pixel. It provides a MIPI DSI interface to the host, a built-in LED backlight and touch controller. +config DRM_PANEL_TPO_Y17P + tristate "TDO Y17P-based panels" + depends on OF && SPI + select DRM_KMS_HELPER + depends on DRM_GEM_DMA_HELPER + depends on BACKLIGHT_CLASS_DEVICE + select DRM_MIPI_DBI + help + Say Y if you want to enable support for panels based on the + TDO Y17P controller. + config DRM_PANEL_TPO_TD028TTEC1 tristate "Toppoly (TPO) TD028TTEC1 panel driver" depends on OF && SPI @ linux/arch/arm/boot/dts/bcm2708.dtsi:723 @ Say Y here if you want to enable support for Visionox RM69299 DSI Video Mode panel. +config DRM_PANEL_WAVESHARE_TOUCHSCREEN + tristate "Waveshare touchscreen panels" + depends on DRM_MIPI_DSI + depends on I2C + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for the Waveshare + DSI Touchscreens. To compile this driver as a module, + choose M here. + config DRM_PANEL_WIDECHIPS_WS2401 tristate "Widechips WS2401 DPI panel driver" depends on SPI && GPIOLIB diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/panel/Makefile linux/drivers/gpu/drm/panel/Makefile --- linux-6.1.66/drivers/gpu/drm/panel/Makefile 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/panel/Makefile 2023-12-13 11:50:59.244986338 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:18 @ obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d.o obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9341) += panel-ilitek-ili9341.o +obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9806E) += panel-ilitek-ili9806e.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) += panel-ilitek-ili9881c.o obj-$(CONFIG_DRM_PANEL_INNOLUX_EJ030NA) += panel-innolux-ej030na.o obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o @ linux/arch/arm/boot/dts/bcm2708.dtsi:70 @ obj-$(CONFIG_DRM_PANEL_SONY_ACX565AKM) += panel-sony-acx565akm.o obj-$(CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521) += panel-sony-tulip-truly-nt35521.o obj-$(CONFIG_DRM_PANEL_TDO_TL070WSH30) += panel-tdo-tl070wsh30.o +obj-$(CONFIG_DRM_PANEL_TPO_Y17P) += panel-tdo-y17p.o obj-$(CONFIG_DRM_PANEL_TPO_TD028TTEC1) += panel-tpo-td028ttec1.o obj-$(CONFIG_DRM_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o +obj-$(CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN) += panel-waveshare-dsi.o obj-$(CONFIG_DRM_PANEL_WIDECHIPS_WS2401) += panel-widechips-ws2401.o obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c linux/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c --- linux-6.1.66/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c 2023-12-13 11:50:59.249986349 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Ilitek ILI9806E TFT LCD drm_panel driver. + * + * Copyright (C) 2022 Raspberry Pi Ltd + * + * Derived from drivers/drm/gpu/panel/panel-sitronix-st7789v.c + * Copyright (C) 2017 Free Electrons + */ + +#include <drm/drm_modes.h> +#include <drm/drm_panel.h> + +#include <linux/bitops.h> +#include <linux/gpio/consumer.h> +#include <linux/media-bus-format.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h> +#include <linux/spi/spi.h> + +#include <video/mipi_display.h> +#include <video/of_videomode.h> +#include <video/videomode.h> + +struct ili9806 { + struct drm_panel panel; + struct spi_device *spi; + struct gpio_desc *reset; + struct regulator *power; + u32 bus_format; +}; + +#define ILI9806_DATA BIT(8) + +#define ILI9806_MAX_MSG_LEN 6 + +struct ili9806e_msg { + unsigned int len; + u16 msg[ILI9806_MAX_MSG_LEN]; +}; + +#define ILI9806_SET_PAGE(page) \ + { \ + .len = 6, \ + .msg = { \ + 0xFF, \ + ILI9806_DATA | 0xFF, \ + ILI9806_DATA | 0x98, \ + ILI9806_DATA | 0x06, \ + ILI9806_DATA | 0x04, \ + ILI9806_DATA | (page) \ + }, \ + } + +#define ILI9806_SET_REG_PARAM(reg, data) \ + { \ + .len = 2, \ + .msg = { \ + (reg), \ + ILI9806_DATA | (data), \ + }, \ + } + +#define ILI9806_SET_REG(reg) \ + { \ + .len = 1, \ + .msg = { (reg) }, \ + } + +static const struct ili9806e_msg panel_init[] = { + ILI9806_SET_PAGE(1), + + /* interface mode + * SEPT_SDIO = 0 (spi interface transfer through SDA pin) + * SDO_STATUS = 1 (always output, but without output tri-state) + */ + ILI9806_SET_REG_PARAM(0x08, 0x10), + /* display control + * VSPL = 1 (vertical sync polarity) + * HSPL = 0 (horizontal sync polarity) + * DPL = 0 (PCLK polarity) + * EPL = 1 (data enable polarity) + */ + ILI9806_SET_REG_PARAM(0x21, 0x0d), + /* resolution control (0x02 = 480x800) */ + ILI9806_SET_REG_PARAM(0x30, 0x02), + /* display inversion control (0x00 = column inversion) */ + ILI9806_SET_REG_PARAM(0x31, 0x00), + /* power control + * EXB1T = 0 (internal charge pump) + * EXT_CPCK_SEL = 1 (pump clock control signal = output 2 x waveform) + * BT = 0 (DDVDH / DDVDL voltage = VCI x 2 / VCI x -2) + */ + ILI9806_SET_REG_PARAM(0x40, 0x10), + /* power control + * DDVDH_CLP = 5.6 (DDVDH clamp leve) + * DDVDL_CLP = -5.6 (DDVDL clamp leve) + */ + ILI9806_SET_REG_PARAM(0x41, 0x55), + /* power control + * VGH_CP = 2DDVDH - DDVDL (step up factor for VGH) + * VGL_CP = DDVDL + VCL - VCIP (step up factor for VGL) + */ + ILI9806_SET_REG_PARAM(0x42, 0x02), + /* power control + * VGH_CLPEN = 0 (disable VGH clamp level) + * VGH_CLP = 9 (15.0 VGH clamp level - but this is disabled so not used?) + */ + ILI9806_SET_REG_PARAM(0x43, 0x84), + /* power control + * VGL_CLPEN = 0 (disable VGL clamp level) + * VGL_CLP = 9 (-11.0 VGL clamp level - but this is disabled so not used?) + */ + ILI9806_SET_REG_PARAM(0x44, 0x84), + + /* power control + * VREG1OUT voltage for positive gamma? + */ + ILI9806_SET_REG_PARAM(0x50, 0x78), + /* power control + * VREG2OUT voltage for negative gamma? + */ + ILI9806_SET_REG_PARAM(0x51, 0x78), + + ILI9806_SET_REG_PARAM(0x52, 0x00), + ILI9806_SET_REG_PARAM(0x53, 0x77), + ILI9806_SET_REG_PARAM(0x57, 0x60), + ILI9806_SET_REG_PARAM(0x60, 0x07), + ILI9806_SET_REG_PARAM(0x61, 0x00), + ILI9806_SET_REG_PARAM(0x62, 0x08), + ILI9806_SET_REG_PARAM(0x63, 0x00), + ILI9806_SET_REG_PARAM(0xA0, 0x00), + ILI9806_SET_REG_PARAM(0xA1, 0x07), + ILI9806_SET_REG_PARAM(0xA2, 0x0C), + ILI9806_SET_REG_PARAM(0xA3, 0x0B), + ILI9806_SET_REG_PARAM(0xA4, 0x03), + ILI9806_SET_REG_PARAM(0xA5, 0x07), + ILI9806_SET_REG_PARAM(0xA6, 0x06), + ILI9806_SET_REG_PARAM(0xA7, 0x04), + ILI9806_SET_REG_PARAM(0xA8, 0x08), + ILI9806_SET_REG_PARAM(0xA9, 0x0C), + ILI9806_SET_REG_PARAM(0xAA, 0x13), + ILI9806_SET_REG_PARAM(0xAB, 0x06), + ILI9806_SET_REG_PARAM(0xAC, 0x0D), + ILI9806_SET_REG_PARAM(0xAD, 0x19), + ILI9806_SET_REG_PARAM(0xAE, 0x10), + ILI9806_SET_REG_PARAM(0xAF, 0x00), + /* negative gamma control + * set the gray scale voltage to adjust the gamma characteristics of the panel + */ + ILI9806_SET_REG_PARAM(0xC0, 0x00), + ILI9806_SET_REG_PARAM(0xC1, 0x07), + ILI9806_SET_REG_PARAM(0xC2, 0x0C), + ILI9806_SET_REG_PARAM(0xC3, 0x0B), + ILI9806_SET_REG_PARAM(0xC4, 0x03), + ILI9806_SET_REG_PARAM(0xC5, 0x07), + ILI9806_SET_REG_PARAM(0xC6, 0x07), + ILI9806_SET_REG_PARAM(0xC7, 0x04), + ILI9806_SET_REG_PARAM(0xC8, 0x08), + ILI9806_SET_REG_PARAM(0xC9, 0x0C), + ILI9806_SET_REG_PARAM(0xCA, 0x13), + ILI9806_SET_REG_PARAM(0xCB, 0x06), + ILI9806_SET_REG_PARAM(0xCC, 0x0D), + ILI9806_SET_REG_PARAM(0xCD, 0x18), + ILI9806_SET_REG_PARAM(0xCE, 0x10), + ILI9806_SET_REG_PARAM(0xCF, 0x00), + + ILI9806_SET_PAGE(6), + + ILI9806_SET_REG_PARAM(0x00, 0x20), + ILI9806_SET_REG_PARAM(0x01, 0x0A), + ILI9806_SET_REG_PARAM(0x02, 0x00), + ILI9806_SET_REG_PARAM(0x03, 0x00), + ILI9806_SET_REG_PARAM(0x04, 0x01), + ILI9806_SET_REG_PARAM(0x05, 0x01), + ILI9806_SET_REG_PARAM(0x06, 0x98), + ILI9806_SET_REG_PARAM(0x07, 0x06), + ILI9806_SET_REG_PARAM(0x08, 0x01), + ILI9806_SET_REG_PARAM(0x09, 0x80), + ILI9806_SET_REG_PARAM(0x0A, 0x00), + ILI9806_SET_REG_PARAM(0x0B, 0x00), + ILI9806_SET_REG_PARAM(0x0C, 0x01), + ILI9806_SET_REG_PARAM(0x0D, 0x01), + ILI9806_SET_REG_PARAM(0x0E, 0x00), + ILI9806_SET_REG_PARAM(0x0F, 0x00), + ILI9806_SET_REG_PARAM(0x10, 0xF0), + ILI9806_SET_REG_PARAM(0x11, 0xF4), + ILI9806_SET_REG_PARAM(0x12, 0x01), + ILI9806_SET_REG_PARAM(0x13, 0x00), + ILI9806_SET_REG_PARAM(0x14, 0x00), + ILI9806_SET_REG_PARAM(0x15, 0xC0), + ILI9806_SET_REG_PARAM(0x16, 0x08), + ILI9806_SET_REG_PARAM(0x17, 0x00), + ILI9806_SET_REG_PARAM(0x18, 0x00), + ILI9806_SET_REG_PARAM(0x19, 0x00), + ILI9806_SET_REG_PARAM(0x1A, 0x00), + ILI9806_SET_REG_PARAM(0x1B, 0x00), + ILI9806_SET_REG_PARAM(0x1C, 0x00), + ILI9806_SET_REG_PARAM(0x1D, 0x00), + ILI9806_SET_REG_PARAM(0x20, 0x01), + ILI9806_SET_REG_PARAM(0x21, 0x23), + ILI9806_SET_REG_PARAM(0x22, 0x45), + ILI9806_SET_REG_PARAM(0x23, 0x67), + ILI9806_SET_REG_PARAM(0x24, 0x01), + ILI9806_SET_REG_PARAM(0x25, 0x23), + ILI9806_SET_REG_PARAM(0x26, 0x45), + ILI9806_SET_REG_PARAM(0x27, 0x67), + ILI9806_SET_REG_PARAM(0x30, 0x11), + ILI9806_SET_REG_PARAM(0x31, 0x11), + ILI9806_SET_REG_PARAM(0x32, 0x00), + ILI9806_SET_REG_PARAM(0x33, 0xEE), + ILI9806_SET_REG_PARAM(0x34, 0xFF), + ILI9806_SET_REG_PARAM(0x35, 0xBB), + ILI9806_SET_REG_PARAM(0x36, 0xAA), + ILI9806_SET_REG_PARAM(0x37, 0xDD), + ILI9806_SET_REG_PARAM(0x38, 0xCC), + ILI9806_SET_REG_PARAM(0x39, 0x66), + ILI9806_SET_REG_PARAM(0x3A, 0x77), + ILI9806_SET_REG_PARAM(0x3B, 0x22), + ILI9806_SET_REG_PARAM(0x3C, 0x22), + ILI9806_SET_REG_PARAM(0x3D, 0x22), + ILI9806_SET_REG_PARAM(0x3E, 0x22), + ILI9806_SET_REG_PARAM(0x3F, 0x22), + ILI9806_SET_REG_PARAM(0x40, 0x22), + /* register doesn't exist on page 6? */ + ILI9806_SET_REG_PARAM(0x52, 0x10), + /* doesn't make sense, not valid according to datasheet */ + ILI9806_SET_REG_PARAM(0x53, 0x10), + /* doesn't make sense, not valid according to datasheet */ + ILI9806_SET_REG_PARAM(0x54, 0x13), + + ILI9806_SET_PAGE(7), + + /* enable VREG */ + ILI9806_SET_REG_PARAM(0x18, 0x1D), + /* enable VGL_REG */ + ILI9806_SET_REG_PARAM(0x17, 0x22), + /* register doesn't exist on page 7? */ + ILI9806_SET_REG_PARAM(0x02, 0x77), + /* register doesn't exist on page 7? */ + ILI9806_SET_REG_PARAM(0x26, 0xB2), + /* register doesn't exist on page 7? */ + ILI9806_SET_REG_PARAM(0xE1, 0x79), + + ILI9806_SET_PAGE(0), + + ILI9806_SET_REG_PARAM(MIPI_DCS_SET_PIXEL_FORMAT, + MIPI_DCS_PIXEL_FMT_18BIT << 4), + ILI9806_SET_REG_PARAM(MIPI_DCS_SET_TEAR_ON, 0x00), + ILI9806_SET_REG(MIPI_DCS_EXIT_SLEEP_MODE), +}; + +#define NUM_INIT_REGS ARRAY_SIZE(panel_init) + +static inline struct ili9806 *panel_to_ili9806(struct drm_panel *panel) +{ + return container_of(panel, struct ili9806, panel); +} + +static int ili9806_write_msg(struct ili9806 *ctx, const struct ili9806e_msg *msg) +{ + struct spi_transfer xfer = { }; + struct spi_message spi; + //u16 txbuf[] = { msg->, ILI9806_DATA | data }; + + spi_message_init(&spi); + + xfer.tx_buf = msg->msg; + xfer.bits_per_word = 9; + xfer.len = sizeof(u16) * msg->len; + + spi_message_add_tail(&xfer, &spi); + return spi_sync(ctx->spi, &spi); +} + +static int ili9806e_write_msg_list(struct ili9806 *ctx, + const struct ili9806e_msg msgs[], + unsigned int num_msgs) +{ + int ret, i; + + for (i = 0; i < num_msgs; i++) { + ret = ili9806_write_msg(ctx, &msgs[i]); + if (ret) + break; + } + + return ret; +} + +static const struct drm_display_mode ili9806e_480x800_mode = { + .clock = 32000, + .hdisplay = 480, + .hsync_start = 480 + 10, + .hsync_end = 480 + 10 + 16, + .htotal = 480 + 10 + 16 + 59, + .vdisplay = 800, + .vsync_start = 800 + 15, + .vsync_end = 800 + 15 + 113, + .vtotal = 800 + 15 + 113 + 15, + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, +}; + +static int ili9806_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct ili9806 *ctx = panel_to_ili9806(panel); + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(connector->dev, &ili9806e_480x800_mode); + if (!mode) { + dev_err(panel->dev, "failed to add mode %ux%ux@%u\n", + ili9806e_480x800_mode.hdisplay, + ili9806e_480x800_mode.vdisplay, + drm_mode_vrefresh(&ili9806e_480x800_mode)); + return -ENOMEM; + } + + drm_mode_set_name(mode); + + mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + drm_mode_probed_add(connector, mode); + + connector->display_info.width_mm = 61; + connector->display_info.height_mm = 103; + drm_display_info_set_bus_formats(&connector->display_info, + &ctx->bus_format, 1); + connector->display_info.bus_flags = + DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE; + + return 1; +} + +static int ili9806_prepare(struct drm_panel *panel) +{ + struct ili9806 *ctx = panel_to_ili9806(panel); + int ret; + + ret = regulator_enable(ctx->power); + if (ret) + return ret; + + ret = ili9806e_write_msg_list(ctx, panel_init, NUM_INIT_REGS); + + return ret; +} + +static int ili9806_enable(struct drm_panel *panel) +{ + struct ili9806 *ctx = panel_to_ili9806(panel); + const struct ili9806e_msg msg = ILI9806_SET_REG(MIPI_DCS_SET_DISPLAY_ON); + int ret; + + ret = ili9806_write_msg(ctx, &msg); + + return ret; +} + +static int ili9806_disable(struct drm_panel *panel) +{ + struct ili9806 *ctx = panel_to_ili9806(panel); + const struct ili9806e_msg msg = ILI9806_SET_REG(MIPI_DCS_SET_DISPLAY_OFF); + int ret; + + ret = ili9806_write_msg(ctx, &msg); + + return ret; +} + +static int ili9806_unprepare(struct drm_panel *panel) +{ + struct ili9806 *ctx = panel_to_ili9806(panel); + const struct ili9806e_msg msg = ILI9806_SET_REG(MIPI_DCS_ENTER_SLEEP_MODE); + int ret; + + ret = ili9806_write_msg(ctx, &msg); + + return ret; +} + +static const struct drm_panel_funcs ili9806_drm_funcs = { + .disable = ili9806_disable, + .enable = ili9806_enable, + .get_modes = ili9806_get_modes, + .prepare = ili9806_prepare, + .unprepare = ili9806_unprepare, +}; + +static const struct of_device_id ili9806_of_match[] = { + { .compatible = "txw,txw397017s2", + .data = (void *)MEDIA_BUS_FMT_RGB888_1X24, + }, { + .compatible = "pimoroni,hyperpixel4", + .data = (void *)MEDIA_BUS_FMT_RGB666_1X24_CPADHI, + }, { + .compatible = "ilitek,ili9806e", + .data = (void *)MEDIA_BUS_FMT_RGB888_1X24, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, ili9806_of_match); + +static int ili9806_probe(struct spi_device *spi) +{ + const struct ili9806e_msg panel_reset[] = { + ILI9806_SET_PAGE(0), + ILI9806_SET_REG_PARAM(0x01, 0x00) + }; + const struct of_device_id *id; + struct ili9806 *ctx; + int ret; + + ctx = devm_kzalloc(&spi->dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + id = of_match_node(ili9806_of_match, spi->dev.of_node); + if (!id) + return -ENODEV; + + ctx->bus_format = (u32)(uintptr_t)id->data; + + spi_set_drvdata(spi, ctx); + ctx->spi = spi; + + drm_panel_init(&ctx->panel, &spi->dev, &ili9806_drm_funcs, + DRM_MODE_CONNECTOR_DPI); + + ctx->power = devm_regulator_get(&spi->dev, "power"); + if (IS_ERR(ctx->power)) + return PTR_ERR(ctx->power); + + ctx->reset = devm_gpiod_get_optional(&spi->dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(ctx->reset)) { + dev_err(&spi->dev, "Couldn't get our reset line\n"); + return PTR_ERR(ctx->reset); + } + + /* Soft reset */ + ili9806e_write_msg_list(ctx, panel_reset, ARRAY_SIZE(panel_reset)); + msleep(200); + + ret = drm_panel_of_backlight(&ctx->panel); + if (ret) + return ret; + + drm_panel_add(&ctx->panel); + + return 0; +} + +static void ili9806_remove(struct spi_device *spi) +{ + struct ili9806 *ctx = spi_get_drvdata(spi); + + drm_panel_remove(&ctx->panel); +} + +static const struct spi_device_id ili9806_ids[] = { + { "txw397017s2", 0 }, + { "ili9806e", 0 }, + { "hyperpixel4", 0 }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(spi, ili9806_ids); + +static struct spi_driver ili9806_driver = { + .probe = ili9806_probe, + .remove = ili9806_remove, + .driver = { + .name = "ili9806e", + .of_match_table = ili9806_of_match, + }, + .id_table = ili9806_ids, +}; +module_spi_driver(ili9806_driver); + +MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com>"); +MODULE_DESCRIPTION("ili9806 LCD panel driver"); +MODULE_LICENSE("GPL v2"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c linux/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c --- linux-6.1.66/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c 2023-12-13 11:50:59.250986352 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2017-2018, Bootlin + * Copyright (C) 2021, Henson Li <henson@cutiepi.io> + * Copyright (C) 2021, Penk Chen <penk@cutiepi.io> + * Copyright (C) 2022, Mark Williams <mark@crystalfontz.com> */ #include <linux/delay.h> @ linux/arch/arm/boot/dts/bcm2708.dtsi:462 @ ILI9881C_COMMAND_INSTR(0xD3, 0x3F), /* VN0 */ }; +static const struct ili9881c_instr nwe080_init[] = { + ILI9881C_SWITCH_PAGE_INSTR(3), + //GIP_1 + ILI9881C_COMMAND_INSTR(0x01, 0x00), + ILI9881C_COMMAND_INSTR(0x02, 0x00), + ILI9881C_COMMAND_INSTR(0x03, 0x73), + ILI9881C_COMMAND_INSTR(0x04, 0x00), + ILI9881C_COMMAND_INSTR(0x05, 0x00), + ILI9881C_COMMAND_INSTR(0x06, 0x0A), + ILI9881C_COMMAND_INSTR(0x07, 0x00), + ILI9881C_COMMAND_INSTR(0x08, 0x00), + ILI9881C_COMMAND_INSTR(0x09, 0x20), + ILI9881C_COMMAND_INSTR(0x0a, 0x20), + ILI9881C_COMMAND_INSTR(0x0b, 0x00), + ILI9881C_COMMAND_INSTR(0x0c, 0x00), + ILI9881C_COMMAND_INSTR(0x0d, 0x00), + ILI9881C_COMMAND_INSTR(0x0e, 0x00), + ILI9881C_COMMAND_INSTR(0x0f, 0x1E), + ILI9881C_COMMAND_INSTR(0x10, 0x1E), + ILI9881C_COMMAND_INSTR(0x11, 0x00), + ILI9881C_COMMAND_INSTR(0x12, 0x00), + ILI9881C_COMMAND_INSTR(0x13, 0x00), + ILI9881C_COMMAND_INSTR(0x14, 0x00), + ILI9881C_COMMAND_INSTR(0x15, 0x00), + ILI9881C_COMMAND_INSTR(0x16, 0x00), + ILI9881C_COMMAND_INSTR(0x17, 0x00), + ILI9881C_COMMAND_INSTR(0x18, 0x00), + ILI9881C_COMMAND_INSTR(0x19, 0x00), + ILI9881C_COMMAND_INSTR(0x1A, 0x00), + ILI9881C_COMMAND_INSTR(0x1B, 0x00), + ILI9881C_COMMAND_INSTR(0x1C, 0x00), + ILI9881C_COMMAND_INSTR(0x1D, 0x00), + ILI9881C_COMMAND_INSTR(0x1E, 0x40), + ILI9881C_COMMAND_INSTR(0x1F, 0x80), + ILI9881C_COMMAND_INSTR(0x20, 0x06), + ILI9881C_COMMAND_INSTR(0x21, 0x01), + ILI9881C_COMMAND_INSTR(0x22, 0x00), + ILI9881C_COMMAND_INSTR(0x23, 0x00), + ILI9881C_COMMAND_INSTR(0x24, 0x00), + ILI9881C_COMMAND_INSTR(0x25, 0x00), + ILI9881C_COMMAND_INSTR(0x26, 0x00), + ILI9881C_COMMAND_INSTR(0x27, 0x00), + ILI9881C_COMMAND_INSTR(0x28, 0x33), + ILI9881C_COMMAND_INSTR(0x29, 0x03), + ILI9881C_COMMAND_INSTR(0x2A, 0x00), + ILI9881C_COMMAND_INSTR(0x2B, 0x00), + ILI9881C_COMMAND_INSTR(0x2C, 0x00), + ILI9881C_COMMAND_INSTR(0x2D, 0x00), + ILI9881C_COMMAND_INSTR(0x2E, 0x00), + ILI9881C_COMMAND_INSTR(0x2F, 0x00), + + ILI9881C_COMMAND_INSTR(0x30, 0x00), + ILI9881C_COMMAND_INSTR(0x31, 0x00), + ILI9881C_COMMAND_INSTR(0x32, 0x00), + ILI9881C_COMMAND_INSTR(0x33, 0x00), + ILI9881C_COMMAND_INSTR(0x34, 0x04), + ILI9881C_COMMAND_INSTR(0x35, 0x00), + ILI9881C_COMMAND_INSTR(0x36, 0x00), + ILI9881C_COMMAND_INSTR(0x37, 0x00), + ILI9881C_COMMAND_INSTR(0x38, 0x3C), + ILI9881C_COMMAND_INSTR(0x39, 0x00), + ILI9881C_COMMAND_INSTR(0x3A, 0x00), + ILI9881C_COMMAND_INSTR(0x3B, 0x00), + ILI9881C_COMMAND_INSTR(0x3C, 0x00), + ILI9881C_COMMAND_INSTR(0x3D, 0x00), + ILI9881C_COMMAND_INSTR(0x3E, 0x00), + ILI9881C_COMMAND_INSTR(0x3F, 0x00), + + ILI9881C_COMMAND_INSTR(0x40, 0x00), + ILI9881C_COMMAND_INSTR(0x41, 0x00), + ILI9881C_COMMAND_INSTR(0x42, 0x00), + ILI9881C_COMMAND_INSTR(0x43, 0x00), + ILI9881C_COMMAND_INSTR(0x44, 0x00), + + ILI9881C_COMMAND_INSTR(0x50, 0x10), + ILI9881C_COMMAND_INSTR(0x51, 0x32), + ILI9881C_COMMAND_INSTR(0x52, 0x54), + ILI9881C_COMMAND_INSTR(0x53, 0x76), + ILI9881C_COMMAND_INSTR(0x54, 0x98), + ILI9881C_COMMAND_INSTR(0x55, 0xba), + ILI9881C_COMMAND_INSTR(0x56, 0x10), + ILI9881C_COMMAND_INSTR(0x57, 0x32), + ILI9881C_COMMAND_INSTR(0x58, 0x54), + ILI9881C_COMMAND_INSTR(0x59, 0x76), + ILI9881C_COMMAND_INSTR(0x5A, 0x98), + ILI9881C_COMMAND_INSTR(0x5B, 0xba), + ILI9881C_COMMAND_INSTR(0x5C, 0xdc), + ILI9881C_COMMAND_INSTR(0x5D, 0xfe), + + //GIP_3 + ILI9881C_COMMAND_INSTR(0x5E, 0x00), + ILI9881C_COMMAND_INSTR(0x5F, 0x01), + ILI9881C_COMMAND_INSTR(0x60, 0x00), + ILI9881C_COMMAND_INSTR(0x61, 0x15), + ILI9881C_COMMAND_INSTR(0x62, 0x14), + ILI9881C_COMMAND_INSTR(0x63, 0x0E), + ILI9881C_COMMAND_INSTR(0x64, 0x0F), + ILI9881C_COMMAND_INSTR(0x65, 0x0C), + ILI9881C_COMMAND_INSTR(0x66, 0x0D), + ILI9881C_COMMAND_INSTR(0x67, 0x06), + ILI9881C_COMMAND_INSTR(0x68, 0x02), + ILI9881C_COMMAND_INSTR(0x69, 0x02), + ILI9881C_COMMAND_INSTR(0x6A, 0x02), + ILI9881C_COMMAND_INSTR(0x6B, 0x02), + ILI9881C_COMMAND_INSTR(0x6C, 0x02), + ILI9881C_COMMAND_INSTR(0x6D, 0x02), + ILI9881C_COMMAND_INSTR(0x6E, 0x07), + ILI9881C_COMMAND_INSTR(0x6F, 0x02), + + ILI9881C_COMMAND_INSTR(0x70, 0x02), + ILI9881C_COMMAND_INSTR(0x71, 0x02), + ILI9881C_COMMAND_INSTR(0x72, 0x02), + ILI9881C_COMMAND_INSTR(0x73, 0x02), + ILI9881C_COMMAND_INSTR(0x74, 0x02), + ILI9881C_COMMAND_INSTR(0x75, 0x01), + ILI9881C_COMMAND_INSTR(0x76, 0x00), + ILI9881C_COMMAND_INSTR(0x77, 0x14), + ILI9881C_COMMAND_INSTR(0x78, 0x15), + ILI9881C_COMMAND_INSTR(0x79, 0x0E), + ILI9881C_COMMAND_INSTR(0x7A, 0x0F), + ILI9881C_COMMAND_INSTR(0x7B, 0x0C), + ILI9881C_COMMAND_INSTR(0x7C, 0x0D), + ILI9881C_COMMAND_INSTR(0x7D, 0x06), + ILI9881C_COMMAND_INSTR(0x7E, 0x02), + ILI9881C_COMMAND_INSTR(0x7F, 0x02), + + ILI9881C_COMMAND_INSTR(0x80, 0x02), + ILI9881C_COMMAND_INSTR(0x81, 0x02), + ILI9881C_COMMAND_INSTR(0x82, 0x02), + ILI9881C_COMMAND_INSTR(0x83, 0x02), + ILI9881C_COMMAND_INSTR(0x84, 0x07), + ILI9881C_COMMAND_INSTR(0x85, 0x02), + ILI9881C_COMMAND_INSTR(0x86, 0x02), + ILI9881C_COMMAND_INSTR(0x87, 0x02), + ILI9881C_COMMAND_INSTR(0x88, 0x02), + ILI9881C_COMMAND_INSTR(0x89, 0x02), + ILI9881C_COMMAND_INSTR(0x8A, 0x02), + + ILI9881C_SWITCH_PAGE_INSTR(4), + ILI9881C_COMMAND_INSTR(0x6C, 0x15), + ILI9881C_COMMAND_INSTR(0x6E, 0x2A), + + //clamp 15V + ILI9881C_COMMAND_INSTR(0x6F, 0x35), + ILI9881C_COMMAND_INSTR(0x3A, 0x92), + ILI9881C_COMMAND_INSTR(0x8D, 0x1F), + ILI9881C_COMMAND_INSTR(0x87, 0xBA), + ILI9881C_COMMAND_INSTR(0x26, 0x76), + ILI9881C_COMMAND_INSTR(0xB2, 0xD1), + ILI9881C_COMMAND_INSTR(0xB5, 0x27), + ILI9881C_COMMAND_INSTR(0x31, 0x75), + ILI9881C_COMMAND_INSTR(0x30, 0x03), + ILI9881C_COMMAND_INSTR(0x3B, 0x98), + ILI9881C_COMMAND_INSTR(0x35, 0x17), + ILI9881C_COMMAND_INSTR(0x33, 0x14), + ILI9881C_COMMAND_INSTR(0x38, 0x01), + ILI9881C_COMMAND_INSTR(0x39, 0x00), + + ILI9881C_SWITCH_PAGE_INSTR(1), + // direction rotate + //ILI9881C_COMMAND_INSTR(0x22, 0x0B), + ILI9881C_COMMAND_INSTR(0x22, 0x0A), + ILI9881C_COMMAND_INSTR(0x31, 0x00), + ILI9881C_COMMAND_INSTR(0x53, 0x63), + ILI9881C_COMMAND_INSTR(0x55, 0x69), + ILI9881C_COMMAND_INSTR(0x50, 0xC7), + ILI9881C_COMMAND_INSTR(0x51, 0xC2), + ILI9881C_COMMAND_INSTR(0x60, 0x26), + + ILI9881C_COMMAND_INSTR(0xA0, 0x08), + ILI9881C_COMMAND_INSTR(0xA1, 0x0F), + ILI9881C_COMMAND_INSTR(0xA2, 0x25), + ILI9881C_COMMAND_INSTR(0xA3, 0x01), + ILI9881C_COMMAND_INSTR(0xA4, 0x23), + ILI9881C_COMMAND_INSTR(0xA5, 0x18), + ILI9881C_COMMAND_INSTR(0xA6, 0x11), + ILI9881C_COMMAND_INSTR(0xA7, 0x1A), + ILI9881C_COMMAND_INSTR(0xA8, 0x81), + ILI9881C_COMMAND_INSTR(0xA9, 0x19), + ILI9881C_COMMAND_INSTR(0xAA, 0x26), + ILI9881C_COMMAND_INSTR(0xAB, 0x7C), + ILI9881C_COMMAND_INSTR(0xAC, 0x24), + ILI9881C_COMMAND_INSTR(0xAD, 0x1E), + ILI9881C_COMMAND_INSTR(0xAE, 0x5C), + ILI9881C_COMMAND_INSTR(0xAF, 0x2A), + ILI9881C_COMMAND_INSTR(0xB0, 0x2B), + ILI9881C_COMMAND_INSTR(0xB1, 0x50), + ILI9881C_COMMAND_INSTR(0xB2, 0x5C), + ILI9881C_COMMAND_INSTR(0xB3, 0x39), + + ILI9881C_COMMAND_INSTR(0xC0, 0x08), + ILI9881C_COMMAND_INSTR(0xC1, 0x1F), + ILI9881C_COMMAND_INSTR(0xC2, 0x24), + ILI9881C_COMMAND_INSTR(0xC3, 0x1D), + ILI9881C_COMMAND_INSTR(0xC4, 0x04), + ILI9881C_COMMAND_INSTR(0xC5, 0x32), + ILI9881C_COMMAND_INSTR(0xC6, 0x24), + ILI9881C_COMMAND_INSTR(0xC7, 0x1F), + ILI9881C_COMMAND_INSTR(0xC8, 0x90), + ILI9881C_COMMAND_INSTR(0xC9, 0x20), + ILI9881C_COMMAND_INSTR(0xCA, 0x2C), + ILI9881C_COMMAND_INSTR(0xCB, 0x82), + ILI9881C_COMMAND_INSTR(0xCC, 0x19), + ILI9881C_COMMAND_INSTR(0xCD, 0x22), + ILI9881C_COMMAND_INSTR(0xCE, 0x4E), + ILI9881C_COMMAND_INSTR(0xCF, 0x28), + ILI9881C_COMMAND_INSTR(0xD0, 0x2D), + ILI9881C_COMMAND_INSTR(0xD1, 0x51), + ILI9881C_COMMAND_INSTR(0xD2, 0x5D), + ILI9881C_COMMAND_INSTR(0xD3, 0x39), + + ILI9881C_SWITCH_PAGE_INSTR(0), + //PWM + ILI9881C_COMMAND_INSTR(0x51, 0x0F), + ILI9881C_COMMAND_INSTR(0x52, 0xFF), + ILI9881C_COMMAND_INSTR(0x53, 0x2C), + + ILI9881C_COMMAND_INSTR(0x11, 0x00), + ILI9881C_COMMAND_INSTR(0x29, 0x00), + ILI9881C_COMMAND_INSTR(0x35, 0x00), +}; + static const struct ili9881c_instr w552946ab_init[] = { ILI9881C_SWITCH_PAGE_INSTR(3), ILI9881C_COMMAND_INSTR(0x01, 0x00), @ linux/arch/arm/boot/dts/bcm2708.dtsi:891 @ ILI9881C_SWITCH_PAGE_INSTR(0), }; +static const struct ili9881c_instr cfaf7201280a0_050tx_init[] = { + //ILI9881C PAGE3 + ILI9881C_SWITCH_PAGE_INSTR(3), + //GIP_1 + ILI9881C_COMMAND_INSTR(0x01, 0x00), //added + ILI9881C_COMMAND_INSTR(0x02, 0x00), + ILI9881C_COMMAND_INSTR(0x03, 0x73), + ILI9881C_COMMAND_INSTR(0x04, 0x00), + ILI9881C_COMMAND_INSTR(0x05, 0x00), + ILI9881C_COMMAND_INSTR(0x06, 0x0A), + ILI9881C_COMMAND_INSTR(0x07, 0x00), + ILI9881C_COMMAND_INSTR(0x08, 0x00), + ILI9881C_COMMAND_INSTR(0x09, 0x01), + ILI9881C_COMMAND_INSTR(0x0A, 0x00), + ILI9881C_COMMAND_INSTR(0x0B, 0x00), + ILI9881C_COMMAND_INSTR(0x0C, 0x01), + ILI9881C_COMMAND_INSTR(0x0D, 0x00), + ILI9881C_COMMAND_INSTR(0x0E, 0x00), + ILI9881C_COMMAND_INSTR(0x0F, 0x1D), + ILI9881C_COMMAND_INSTR(0x10, 0x1D), + ILI9881C_COMMAND_INSTR(0x11, 0x00), + ILI9881C_COMMAND_INSTR(0x12, 0x00), + ILI9881C_COMMAND_INSTR(0x13, 0x00), + ILI9881C_COMMAND_INSTR(0x14, 0x00), + ILI9881C_COMMAND_INSTR(0x15, 0x00), + ILI9881C_COMMAND_INSTR(0x16, 0x00), + ILI9881C_COMMAND_INSTR(0x17, 0x00), + ILI9881C_COMMAND_INSTR(0x18, 0x00), + ILI9881C_COMMAND_INSTR(0x19, 0x00), + ILI9881C_COMMAND_INSTR(0x1A, 0x00), + ILI9881C_COMMAND_INSTR(0x1B, 0x00), + ILI9881C_COMMAND_INSTR(0x1C, 0x00), + ILI9881C_COMMAND_INSTR(0x1D, 0x00), + ILI9881C_COMMAND_INSTR(0x1E, 0x40), + ILI9881C_COMMAND_INSTR(0x1F, 0x80), + ILI9881C_COMMAND_INSTR(0x20, 0x06), + ILI9881C_COMMAND_INSTR(0x21, 0x02), + ILI9881C_COMMAND_INSTR(0x22, 0x00), + ILI9881C_COMMAND_INSTR(0x23, 0x00), + ILI9881C_COMMAND_INSTR(0x24, 0x00), + ILI9881C_COMMAND_INSTR(0x25, 0x00), + ILI9881C_COMMAND_INSTR(0x26, 0x00), + ILI9881C_COMMAND_INSTR(0x27, 0x00), + ILI9881C_COMMAND_INSTR(0x28, 0x33), + ILI9881C_COMMAND_INSTR(0x29, 0x03), + ILI9881C_COMMAND_INSTR(0x2A, 0x00), + ILI9881C_COMMAND_INSTR(0x2B, 0x00), + ILI9881C_COMMAND_INSTR(0x2C, 0x00), + ILI9881C_COMMAND_INSTR(0x2D, 0x00), + ILI9881C_COMMAND_INSTR(0x2E, 0x00), + ILI9881C_COMMAND_INSTR(0x2F, 0x00), + ILI9881C_COMMAND_INSTR(0x30, 0x00), + ILI9881C_COMMAND_INSTR(0x31, 0x00), + ILI9881C_COMMAND_INSTR(0x32, 0x00), + ILI9881C_COMMAND_INSTR(0x33, 0x00), + ILI9881C_COMMAND_INSTR(0x34, 0x04), + ILI9881C_COMMAND_INSTR(0x35, 0x00), + ILI9881C_COMMAND_INSTR(0x36, 0x00), + ILI9881C_COMMAND_INSTR(0x37, 0x00), + ILI9881C_COMMAND_INSTR(0x38, 0x3C), + ILI9881C_COMMAND_INSTR(0x39, 0x00), + ILI9881C_COMMAND_INSTR(0x3A, 0x40), + ILI9881C_COMMAND_INSTR(0x3B, 0x40), + ILI9881C_COMMAND_INSTR(0x3C, 0x00), + ILI9881C_COMMAND_INSTR(0x3D, 0x00), + ILI9881C_COMMAND_INSTR(0x3E, 0x00), + ILI9881C_COMMAND_INSTR(0x3F, 0x00), + ILI9881C_COMMAND_INSTR(0x40, 0x00), + ILI9881C_COMMAND_INSTR(0x41, 0x00), + ILI9881C_COMMAND_INSTR(0x42, 0x00), + ILI9881C_COMMAND_INSTR(0x43, 0x00), + ILI9881C_COMMAND_INSTR(0x44, 0x00), + //GIP_2 + ILI9881C_COMMAND_INSTR(0x50, 0x01), + ILI9881C_COMMAND_INSTR(0x51, 0x23), + ILI9881C_COMMAND_INSTR(0x52, 0x45), + ILI9881C_COMMAND_INSTR(0x53, 0x67), + ILI9881C_COMMAND_INSTR(0x54, 0x89), + ILI9881C_COMMAND_INSTR(0x55, 0xAB), + ILI9881C_COMMAND_INSTR(0x56, 0x01), + ILI9881C_COMMAND_INSTR(0x57, 0x23), + ILI9881C_COMMAND_INSTR(0x58, 0x45), + ILI9881C_COMMAND_INSTR(0x59, 0x67), + ILI9881C_COMMAND_INSTR(0x5A, 0x89), + ILI9881C_COMMAND_INSTR(0x5B, 0xAB), + ILI9881C_COMMAND_INSTR(0x5C, 0xCD), + ILI9881C_COMMAND_INSTR(0x5D, 0xEF), + //GIP_3 + ILI9881C_COMMAND_INSTR(0x5E, 0x11), + ILI9881C_COMMAND_INSTR(0x5F, 0x01), + ILI9881C_COMMAND_INSTR(0x60, 0x00), + ILI9881C_COMMAND_INSTR(0x61, 0x15), + ILI9881C_COMMAND_INSTR(0x62, 0x14), + ILI9881C_COMMAND_INSTR(0x63, 0x0E), + ILI9881C_COMMAND_INSTR(0x64, 0x0F), + ILI9881C_COMMAND_INSTR(0x65, 0x0C), + ILI9881C_COMMAND_INSTR(0x66, 0x0D), + ILI9881C_COMMAND_INSTR(0x67, 0x06), + ILI9881C_COMMAND_INSTR(0x68, 0x02), + ILI9881C_COMMAND_INSTR(0x69, 0x07), + ILI9881C_COMMAND_INSTR(0x6A, 0x02), + ILI9881C_COMMAND_INSTR(0x6B, 0x02), + ILI9881C_COMMAND_INSTR(0x6C, 0x02), + ILI9881C_COMMAND_INSTR(0x6D, 0x02), + ILI9881C_COMMAND_INSTR(0x6E, 0x02), + ILI9881C_COMMAND_INSTR(0x6F, 0x02), + ILI9881C_COMMAND_INSTR(0x70, 0x02), + ILI9881C_COMMAND_INSTR(0x71, 0x02), + ILI9881C_COMMAND_INSTR(0x72, 0x02), + ILI9881C_COMMAND_INSTR(0x73, 0x02), + ILI9881C_COMMAND_INSTR(0x74, 0x02), + ILI9881C_COMMAND_INSTR(0x75, 0x01), + ILI9881C_COMMAND_INSTR(0x76, 0x00), + ILI9881C_COMMAND_INSTR(0x77, 0x14), + ILI9881C_COMMAND_INSTR(0x78, 0x15), + ILI9881C_COMMAND_INSTR(0x79, 0x0E), + ILI9881C_COMMAND_INSTR(0x7A, 0x0F), + ILI9881C_COMMAND_INSTR(0x7B, 0x0C), + ILI9881C_COMMAND_INSTR(0x7C, 0x0D), + ILI9881C_COMMAND_INSTR(0x7D, 0x06), + ILI9881C_COMMAND_INSTR(0x7E, 0x02), + ILI9881C_COMMAND_INSTR(0x7F, 0x07), + ILI9881C_COMMAND_INSTR(0x80, 0x02), + ILI9881C_COMMAND_INSTR(0x81, 0x02), + ILI9881C_COMMAND_INSTR(0x82, 0x02), + ILI9881C_COMMAND_INSTR(0x83, 0x02), + ILI9881C_COMMAND_INSTR(0x84, 0x02), + ILI9881C_COMMAND_INSTR(0x85, 0x02), + ILI9881C_COMMAND_INSTR(0x86, 0x02), + ILI9881C_COMMAND_INSTR(0x87, 0x02), + ILI9881C_COMMAND_INSTR(0x88, 0x02), + ILI9881C_COMMAND_INSTR(0x89, 0x02), + ILI9881C_COMMAND_INSTR(0x8A, 0x02), + //ILI9881C PAGE4 + ILI9881C_SWITCH_PAGE_INSTR(4), + ILI9881C_COMMAND_INSTR(0x6C, 0x15), + ILI9881C_COMMAND_INSTR(0x6E, 0x2B), + // VGH & VGL OUTPUT + ILI9881C_COMMAND_INSTR(0x6F, 0x33), + ILI9881C_COMMAND_INSTR(0x8D, 0x18), + ILI9881C_COMMAND_INSTR(0x87, 0xBA), + ILI9881C_COMMAND_INSTR(0x26, 0x76), + //Reload Gamma setting + ILI9881C_COMMAND_INSTR(0xB2, 0xD1), + ILI9881C_COMMAND_INSTR(0xB5, 0x06), + ILI9881C_COMMAND_INSTR(0x3A, 0x24), + ILI9881C_COMMAND_INSTR(0x35, 0x1F), + + //ILI9881C PAGE1 + ILI9881C_SWITCH_PAGE_INSTR(1), + ILI9881C_COMMAND_INSTR(0x22, 0x09), + //Column inversion + ILI9881C_COMMAND_INSTR(0x31, 0x00), + ILI9881C_COMMAND_INSTR(0x40, 0x33), + ILI9881C_COMMAND_INSTR(0x53, 0xA2), + ILI9881C_COMMAND_INSTR(0x55, 0x92), + ILI9881C_COMMAND_INSTR(0x50, 0x96), + ILI9881C_COMMAND_INSTR(0x51, 0x96), + ILI9881C_COMMAND_INSTR(0x60, 0x22), + ILI9881C_COMMAND_INSTR(0x61, 0x00), + ILI9881C_COMMAND_INSTR(0x62, 0x19), + ILI9881C_COMMAND_INSTR(0x63, 0x00), + //---P-GAMMA START--- + ILI9881C_COMMAND_INSTR(0xA0, 0x08), + ILI9881C_COMMAND_INSTR(0xA1, 0x11), + ILI9881C_COMMAND_INSTR(0xA2, 0x19), + ILI9881C_COMMAND_INSTR(0xA3, 0x0D), + ILI9881C_COMMAND_INSTR(0xA4, 0x0D), + ILI9881C_COMMAND_INSTR(0xA5, 0x1E), + ILI9881C_COMMAND_INSTR(0xA6, 0x14), + ILI9881C_COMMAND_INSTR(0xA7, 0x17), + ILI9881C_COMMAND_INSTR(0xA8, 0x4F), + ILI9881C_COMMAND_INSTR(0xA9, 0x1A), + ILI9881C_COMMAND_INSTR(0xAA, 0x27), + ILI9881C_COMMAND_INSTR(0xAB, 0x49), + ILI9881C_COMMAND_INSTR(0xAC, 0x1A), + ILI9881C_COMMAND_INSTR(0xAD, 0x18), + ILI9881C_COMMAND_INSTR(0xAE, 0x4C), + ILI9881C_COMMAND_INSTR(0xAF, 0x22), + ILI9881C_COMMAND_INSTR(0xB0, 0x27), + ILI9881C_COMMAND_INSTR(0xB1, 0x4B), + ILI9881C_COMMAND_INSTR(0xB2, 0x60), + ILI9881C_COMMAND_INSTR(0xB3, 0x39), + //--- N-GAMMA START--- + ILI9881C_COMMAND_INSTR(0xC0, 0x08), + ILI9881C_COMMAND_INSTR(0xC1, 0x11), + ILI9881C_COMMAND_INSTR(0xC2, 0x19), + ILI9881C_COMMAND_INSTR(0xC3, 0x0D), + ILI9881C_COMMAND_INSTR(0xC4, 0x0D), + ILI9881C_COMMAND_INSTR(0xC5, 0x1E), + ILI9881C_COMMAND_INSTR(0xC6, 0x14), + ILI9881C_COMMAND_INSTR(0xC7, 0x17), + ILI9881C_COMMAND_INSTR(0xC8, 0x4F), + ILI9881C_COMMAND_INSTR(0xC9, 0x1A), + ILI9881C_COMMAND_INSTR(0xCA, 0x27), + ILI9881C_COMMAND_INSTR(0xCB, 0x49), + ILI9881C_COMMAND_INSTR(0xCC, 0x1A), + ILI9881C_COMMAND_INSTR(0xCD, 0x18), + ILI9881C_COMMAND_INSTR(0xCE, 0x4C), + ILI9881C_COMMAND_INSTR(0xCF, 0x33), + ILI9881C_COMMAND_INSTR(0xD0, 0x27), + ILI9881C_COMMAND_INSTR(0xD1, 0x4B), + ILI9881C_COMMAND_INSTR(0xD2, 0x60), + ILI9881C_COMMAND_INSTR(0xD3, 0x39), +}; + static inline struct ili9881c *panel_to_ili9881c(struct drm_panel *panel) { return container_of(panel, struct ili9881c, panel); @ linux/arch/arm/boot/dts/bcm2708.dtsi:1150 @ msleep(5); /* And reset it */ - gpiod_set_value(ctx->reset, 1); + gpiod_set_value_cansleep(ctx->reset, 1); msleep(20); - gpiod_set_value(ctx->reset, 0); + gpiod_set_value_cansleep(ctx->reset, 0); msleep(20); for (i = 0; i < ctx->desc->init_length; i++) { @ linux/arch/arm/boot/dts/bcm2708.dtsi:1208 @ mipi_dsi_dcs_enter_sleep_mode(ctx->dsi); regulator_disable(ctx->power); - gpiod_set_value(ctx->reset, 1); + gpiod_set_value_cansleep(ctx->reset, 1); return 0; } @ linux/arch/arm/boot/dts/bcm2708.dtsi:1247 @ .height_mm = 217, }; +static const struct drm_display_mode nwe080_default_mode = { + .clock = 71750, + + .hdisplay = 800, + .hsync_start = 800 + 52, + .hsync_end = 800 + 52 + 8, + .htotal = 800 + 52 + 8 + 48, + + .vdisplay = 1280, + .vsync_start = 1280 + 16, + .vsync_end = 1280 + 16 + 6, + .vtotal = 1280 + 16 + 6 + 15, + + .width_mm = 107, + .height_mm = 170, +}; + static const struct drm_display_mode w552946aba_default_mode = { .clock = 64000, @ linux/arch/arm/boot/dts/bcm2708.dtsi:1281 @ .height_mm = 121, }; +static const struct drm_display_mode cfaf7201280a0_050tx_default_mode = { + .clock = 72830, + .hdisplay = 720, + .hsync_start = 720 + 87, + .hsync_end = 720 + 87 + 20, + .htotal = 720 + 87 + 20 + 87, + .vdisplay = 1280, + .vsync_start = 1280 + 16, + .vsync_end = 1280 + 16 + 8, + .vtotal = 1280 + 16 + 8 + 16, + .width_mm = 62, + .height_mm = 1108 +}; + static int ili9881c_get_modes(struct drm_panel *panel, struct drm_connector *connector) { @ linux/arch/arm/boot/dts/bcm2708.dtsi:1355 @ ctx->dsi = dsi; ctx->desc = of_device_get_match_data(&dsi->dev); + ctx->panel.prepare_upstream_first = true; drm_panel_init(&ctx->panel, &dsi->dev, &ili9881c_funcs, DRM_MODE_CONNECTOR_DSI); @ linux/arch/arm/boot/dts/bcm2708.dtsi:1386 @ dsi->format = MIPI_DSI_FMT_RGB888; dsi->lanes = 4; - return mipi_dsi_attach(dsi); + ret = mipi_dsi_attach(dsi); + if (ret) + drm_panel_remove(&ctx->panel); + + return ret; } static void ili9881c_dsi_remove(struct mipi_dsi_device *dsi) @ linux/arch/arm/boot/dts/bcm2708.dtsi:1415 @ .mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE, }; +static const struct ili9881c_desc nwe080_desc = { + .init = nwe080_init, + .init_length = ARRAY_SIZE(nwe080_init), + .mode = &nwe080_default_mode, + .mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_VIDEO, +}; + static const struct ili9881c_desc w552946aba_desc = { .init = w552946ab_init, .init_length = ARRAY_SIZE(w552946ab_init), @ linux/arch/arm/boot/dts/bcm2708.dtsi:1430 @ MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET, }; +static const struct ili9881c_desc cfaf7201280a0_050tx_desc = { + .init = cfaf7201280a0_050tx_init, + .init_length = ARRAY_SIZE(cfaf7201280a0_050tx_init), + .mode = &cfaf7201280a0_050tx_default_mode, + .mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_VIDEO, +}; + static const struct of_device_id ili9881c_of_match[] = { { .compatible = "bananapi,lhr050h41", .data = &lhr050h41_desc }, { .compatible = "feixin,k101-im2byl02", .data = &k101_im2byl02_desc }, + { .compatible = "nwe,nwe080", .data = &nwe080_desc }, { .compatible = "wanchanglong,w552946aba", .data = &w552946aba_desc }, + { .compatible = "crystalfontz,cfaf7201280a0_050tx", .data = &cfaf7201280a0_050tx_desc }, { } }; MODULE_DEVICE_TABLE(of, ili9881c_of_match); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/panel/panel-jdi-lt070me05000.c linux/drivers/gpu/drm/panel/panel-jdi-lt070me05000.c --- linux-6.1.66/drivers/gpu/drm/panel/panel-jdi-lt070me05000.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/panel/panel-jdi-lt070me05000.c 2023-12-13 11:50:59.251986354 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:208 @ if (ret < 0) dev_err(dev, "regulator disable failed, %d\n", ret); - gpiod_set_value(jdi->enable_gpio, 0); + gpiod_set_value_cansleep(jdi->enable_gpio, 0); - gpiod_set_value(jdi->reset_gpio, 1); + gpiod_set_value_cansleep(jdi->reset_gpio, 1); - gpiod_set_value(jdi->dcdc_en_gpio, 0); + gpiod_set_value_cansleep(jdi->dcdc_en_gpio, 0); jdi->prepared = false; @ linux/arch/arm/boot/dts/bcm2708.dtsi:236 @ msleep(20); - gpiod_set_value(jdi->dcdc_en_gpio, 1); + gpiod_set_value_cansleep(jdi->dcdc_en_gpio, 1); usleep_range(10, 20); - gpiod_set_value(jdi->reset_gpio, 0); + gpiod_set_value_cansleep(jdi->reset_gpio, 0); usleep_range(10, 20); - gpiod_set_value(jdi->enable_gpio, 1); + gpiod_set_value_cansleep(jdi->enable_gpio, 1); usleep_range(10, 20); ret = jdi_panel_init(jdi); @ linux/arch/arm/boot/dts/bcm2708.dtsi:266 @ if (ret < 0) dev_err(dev, "regulator disable failed, %d\n", ret); - gpiod_set_value(jdi->enable_gpio, 0); + gpiod_set_value_cansleep(jdi->enable_gpio, 0); - gpiod_set_value(jdi->reset_gpio, 1); + gpiod_set_value_cansleep(jdi->reset_gpio, 1); - gpiod_set_value(jdi->dcdc_en_gpio, 0); + gpiod_set_value_cansleep(jdi->dcdc_en_gpio, 0); return ret; } @ linux/arch/arm/boot/dts/bcm2708.dtsi:440 @ return ret; } + jdi->base.prepare_upstream_first = true; drm_panel_init(&jdi->base, &jdi->dsi->dev, &jdi_panel_funcs, DRM_MODE_CONNECTOR_DSI); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c linux/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c --- linux-6.1.66/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c 2023-12-13 11:50:59.256986366 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:223 @ static int rpi_touchscreen_i2c_read(struct rpi_touchscreen *ts, u8 reg) { - return i2c_smbus_read_byte_data(ts->i2c, reg); + struct i2c_client *client = ts->i2c; + struct i2c_msg msgs[1]; + u8 addr_buf[1] = { reg }; + u8 data_buf[1] = { 0, }; + int ret; + + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = ARRAY_SIZE(addr_buf); + msgs[0].buf = addr_buf; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + usleep_range(100, 300); + + /* Read data from register */ + msgs[0].addr = client->addr; + msgs[0].flags = I2C_M_RD; + msgs[0].len = 1; + msgs[0].buf = data_buf; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + return data_buf[0]; } static void rpi_touchscreen_i2c_write(struct rpi_touchscreen *ts, @ linux/arch/arm/boot/dts/bcm2708.dtsi:300 @ static int rpi_touchscreen_prepare(struct drm_panel *panel) { struct rpi_touchscreen *ts = panel_to_ts(panel); - int i; + int i, data; + /* + * Power up the Toshiba bridge. The Atmel device can misbehave + * over I2C for a few ms after writes to REG_POWERON (including the + * write in rpi_touchscreen_disable()), so sleep before and after. + * Also to ensure that the bridge has been off for at least 100ms. + */ + msleep(100); rpi_touchscreen_i2c_write(ts, REG_POWERON, 1); + usleep_range(20000, 25000); /* Wait for nPWRDWN to go low to indicate poweron is done. */ for (i = 0; i < 100; i++) { - if (rpi_touchscreen_i2c_read(ts, REG_PORTB) & 1) + data = rpi_touchscreen_i2c_read(ts, REG_PORTB); + if (data >= 0 && (data & 1)) break; } @ linux/arch/arm/boot/dts/bcm2708.dtsi:441 @ /* Turn off at boot, so we can cleanly sequence powering on. */ rpi_touchscreen_i2c_write(ts, REG_POWERON, 0); + usleep_range(20000, 25000); /* Look up the DSI host. It needs to probe before we do. */ endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/panel/panel-simple.c linux/drivers/gpu/drm/panel/panel-simple.c --- linux-6.1.66/drivers/gpu/drm/panel/panel-simple.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/panel/panel-simple.c 2023-12-13 11:50:59.264986385 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:43 @ #include <drm/drm_edid.h> #include <drm/drm_mipi_dsi.h> #include <drm/drm_panel.h> +#include <drm/drm_of.h> /** * struct panel_desc - Describes a simple panel. @ linux/arch/arm/boot/dts/bcm2708.dtsi:158 @ struct edid *edid; struct drm_display_mode override_mode; - - enum drm_panel_orientation orientation; }; static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) @ linux/arch/arm/boot/dts/bcm2708.dtsi:416 @ /* add hard-coded panel modes */ num += panel_simple_get_non_edid_modes(p, connector); - /* - * TODO: Remove once all drm drivers call - * drm_connector_set_orientation_from_panel() - */ - drm_connector_set_panel_orientation(connector, p->orientation); - return num; } @ linux/arch/arm/boot/dts/bcm2708.dtsi:438 @ static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) { - struct panel_simple *p = to_panel_simple(panel); + //struct panel_simple *p = to_panel_simple(panel); - return p->orientation; + return DRM_MODE_PANEL_ORIENTATION_UNKNOWN; } static const struct drm_panel_funcs panel_simple_funcs = { @ linux/arch/arm/boot/dts/bcm2708.dtsi:486 @ of_property_read_u32(np, "width-mm", &desc->size.width); of_property_read_u32(np, "height-mm", &desc->size.height); + of_property_read_u32(np, "bus-format", &desc->bus_format); /* Extract bus_flags from display_timing */ bus_flags = 0; @ linux/arch/arm/boot/dts/bcm2708.dtsi:496 @ /* We do not know the connector for the DT node, so guess it */ desc->connector_type = DRM_MODE_CONNECTOR_DPI; + /* Likewise for the bit depth. */ + desc->bpc = 8; panel->desc = desc; @ linux/arch/arm/boot/dts/bcm2708.dtsi:578 @ return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), "failed to request GPIO\n"); - err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); - if (err) { - dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); - return err; - } - ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); if (ddc) { panel->ddc = of_find_i2c_adapter_by_node(ddc); @ linux/arch/arm/boot/dts/bcm2708.dtsi:1936 @ }, }; +static const struct drm_display_mode geekworm_mzp280_mode = { + .clock = 32000, + .hdisplay = 480, + .hsync_start = 480 + 41, + .hsync_end = 480 + 41 + 20, + .htotal = 480 + 41 + 20 + 60, + .vdisplay = 640, + .vsync_start = 640 + 5, + .vsync_end = 640 + 5 + 10, + .vtotal = 640 + 5 + 10 + 10, + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, +}; + +static const struct panel_desc geekworm_mzp280 = { + .modes = &geekworm_mzp280_mode, + .num_modes = 1, + .bpc = 6, + .size = { + .width = 47, + .height = 61, + }, + .bus_format = MEDIA_BUS_FMT_RGB565_1X24_CPADHI, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, + .connector_type = DRM_MODE_CONNECTOR_DPI, +}; + static const struct drm_display_mode giantplus_gpg482739qs5_mode = { .clock = 9000, .hdisplay = 480, @ linux/arch/arm/boot/dts/bcm2708.dtsi:2142 @ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, }; +static const struct display_timing innolux_at056tn53v1_timing = { + .pixelclock = { 39700000, 39700000, 39700000}, + .hactive = { 640, 640, 640 }, + .hfront_porch = { 16, 16, 16 }, + .hback_porch = { 134, 134, 134 }, + .hsync_len = { 10, 10, 10}, + .vactive = { 480, 480, 480 }, + .vfront_porch = { 32, 32, 32}, + .vback_porch = { 11, 11, 11 }, + .vsync_len = { 2, 2, 2 }, + .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, +}; + +static const struct panel_desc innolux_at056tn53v1 = { + .timings = &innolux_at056tn53v1_timing, + .num_timings = 1, + .bpc = 6, + .size = { + .width = 112, + .height = 84, + }, + .delay = { + .prepare = 50, + .enable = 200, + .disable = 110, + .unprepare = 200, + }, + .bus_format = MEDIA_BUS_FMT_BGR666_1X24_CPADHI, + .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, + .connector_type = DRM_MODE_CONNECTOR_DPI, +}; + static const struct drm_display_mode innolux_at070tn92_mode = { .clock = 33333, .hdisplay = 800, @ linux/arch/arm/boot/dts/bcm2708.dtsi:3244 @ .connector_type = DRM_MODE_CONNECTOR_DPI, }; +static const struct drm_display_mode raspberrypi_7inch_mode = { + .clock = 27777, + .hdisplay = 800, + .hsync_start = 800 + 59, + .hsync_end = 800 + 59 + 2, + .htotal = 800 + 59 + 2 + 46, + .vdisplay = 480, + .vsync_start = 480 + 7, + .vsync_end = 480 + 7 + 2, + .vtotal = 480 + 7 + 2 + 21, + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, +}; + +static const struct panel_desc raspberrypi_7inch = { + .modes = &raspberrypi_7inch_mode, + .num_modes = 1, + .bpc = 8, + .size = { + .width = 154, + .height = 86, + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X24, + .connector_type = DRM_MODE_CONNECTOR_DSI, +}; + static const struct display_timing rocktech_rk070er9427_timing = { .pixelclock = { 26400000, 33300000, 46800000 }, .hactive = { 800, 800, 800 }, @ linux/arch/arm/boot/dts/bcm2708.dtsi:4156 @ .compatible = "friendlyarm,hd702e", .data = &friendlyarm_hd702e, }, { + .compatible = "geekworm,mzp280", + .data = &geekworm_mzp280, + }, { .compatible = "giantplus,gpg482739qs5", .data = &giantplus_gpg482739qs5 }, { @ linux/arch/arm/boot/dts/bcm2708.dtsi:4180 @ .compatible = "innolux,at043tn24", .data = &innolux_at043tn24, }, { + .compatible = "innolux,at056tn53v1", + .data = &innolux_at056tn53v1, + }, { .compatible = "innolux,at070tn92", .data = &innolux_at070tn92, }, { @ linux/arch/arm/boot/dts/bcm2708.dtsi:4306 @ .compatible = "qishenglong,gopher2b-lcd", .data = &qishenglong_gopher2b_lcd, }, { + .compatible = "raspberrypi,7inch-dsi", + .data = &raspberrypi_7inch, + }, { .compatible = "rocktech,rk070er9427", .data = &rocktech_rk070er9427, }, { @ linux/arch/arm/boot/dts/bcm2708.dtsi:4664 @ .lanes = 4, }; +// for panels using generic panel-dsi binding +static struct panel_desc_dsi panel_dsi; + static const struct of_device_id dsi_of_match[] = { { .compatible = "auo,b080uan01", @ linux/arch/arm/boot/dts/bcm2708.dtsi:4690 @ .compatible = "osddisplays,osd101t2045-53ts", .data = &osd101t2045_53ts }, { + /* Must be the last entry */ + .compatible = "panel-dsi", + .data = &panel_dsi, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, dsi_of_match); + +/* Checks for DSI panel definition in device-tree, analog to panel_dpi */ +static int panel_dsi_dt_probe(struct device *dev, + struct panel_desc_dsi *desc_dsi) +{ + struct panel_desc *desc; + struct display_timing *timing; + const struct device_node *np; + const char *dsi_color_format; + const char *dsi_mode_flags; + struct property *prop; + int dsi_lanes, ret; + + np = dev->of_node; + + desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); + if (!desc) + return -ENOMEM; + + timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); + if (!timing) + return -ENOMEM; + + ret = of_get_display_timing(np, "panel-timing", timing); + if (ret < 0) { + dev_err(dev, "%pOF: no panel-timing node found for \"panel-dsi\" binding\n", + np); + return ret; + } + + desc->timings = timing; + desc->num_timings = 1; + + of_property_read_u32(np, "width-mm", &desc->size.width); + of_property_read_u32(np, "height-mm", &desc->size.height); + + dsi_lanes = drm_of_get_data_lanes_count_ep(np, 0, 0, 1, 4); + + if (dsi_lanes < 0) { + dev_err(dev, "%pOF: no or too many data-lanes defined", np); + return dsi_lanes; + } + + desc_dsi->lanes = dsi_lanes; + + of_property_read_string(np, "dsi-color-format", &dsi_color_format); + if (!strcmp(dsi_color_format, "RGB888")) { + desc_dsi->format = MIPI_DSI_FMT_RGB888; + desc->bpc = 8; + } else if (!strcmp(dsi_color_format, "RGB565")) { + desc_dsi->format = MIPI_DSI_FMT_RGB565; + desc->bpc = 6; + } else if (!strcmp(dsi_color_format, "RGB666")) { + desc_dsi->format = MIPI_DSI_FMT_RGB666; + desc->bpc = 6; + } else if (!strcmp(dsi_color_format, "RGB666_PACKED")) { + desc_dsi->format = MIPI_DSI_FMT_RGB666_PACKED; + desc->bpc = 6; + } else { + dev_err(dev, "%pOF: no valid dsi-color-format defined", np); + return -EINVAL; + } + + + of_property_for_each_string(np, "mode", prop, dsi_mode_flags) { + if (!strcmp(dsi_mode_flags, "MODE_VIDEO")) + desc_dsi->flags |= MIPI_DSI_MODE_VIDEO; + else if (!strcmp(dsi_mode_flags, "MODE_VIDEO_BURST")) + desc_dsi->flags |= MIPI_DSI_MODE_VIDEO_BURST; + else if (!strcmp(dsi_mode_flags, "MODE_VIDEO_SYNC_PULSE")) + desc_dsi->flags |= MIPI_DSI_MODE_VIDEO_SYNC_PULSE; + else if (!strcmp(dsi_mode_flags, "MODE_VIDEO_AUTO_VERT")) + desc_dsi->flags |= MIPI_DSI_MODE_VIDEO_AUTO_VERT; + else if (!strcmp(dsi_mode_flags, "MODE_VIDEO_HSE")) + desc_dsi->flags |= MIPI_DSI_MODE_VIDEO_HSE; + else if (!strcmp(dsi_mode_flags, "MODE_VIDEO_NO_HFP")) + desc_dsi->flags |= MIPI_DSI_MODE_VIDEO_NO_HFP; + else if (!strcmp(dsi_mode_flags, "MODE_VIDEO_NO_HBP")) + desc_dsi->flags |= MIPI_DSI_MODE_VIDEO_NO_HBP; + else if (!strcmp(dsi_mode_flags, "MODE_VIDEO_NO_HSA")) + desc_dsi->flags |= MIPI_DSI_MODE_VIDEO_NO_HSA; + else if (!strcmp(dsi_mode_flags, "MODE_VSYNC_FLUSH")) + desc_dsi->flags |= MIPI_DSI_MODE_VSYNC_FLUSH; + else if (!strcmp(dsi_mode_flags, "MODE_NO_EOT_PACKET")) + desc_dsi->flags |= MIPI_DSI_MODE_NO_EOT_PACKET; + else if (!strcmp(dsi_mode_flags, "CLOCK_NON_CONTINUOUS")) + desc_dsi->flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; + else if (!strcmp(dsi_mode_flags, "MODE_LPM")) + desc_dsi->flags |= MIPI_DSI_MODE_LPM; + else if (!strcmp(dsi_mode_flags, "HS_PKT_END_ALIGNED")) + desc_dsi->flags |= MIPI_DSI_HS_PKT_END_ALIGNED; + } + + desc->connector_type = DRM_MODE_CONNECTOR_DSI; + desc_dsi->desc = *desc; + + return 0; +} + static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) { const struct panel_desc_dsi *desc; + struct panel_desc_dsi *dt_desc; const struct of_device_id *id; int err; @ linux/arch/arm/boot/dts/bcm2708.dtsi:4809 @ if (!id) return -ENODEV; - desc = id->data; + if (id->data == &panel_dsi) { + /* Handle the generic panel-dsi binding */ + dt_desc = devm_kzalloc(&dsi->dev, sizeof(*dt_desc), GFP_KERNEL); + if (!dt_desc) + return -ENOMEM; + + err = panel_dsi_dt_probe(&dsi->dev, dt_desc); + if (err < 0) + return err; + + desc = dt_desc; + } else { + desc = id->data; + } err = panel_simple_probe(&dsi->dev, &desc->desc); if (err < 0) diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/panel/panel-sitronix-st7701.c linux/drivers/gpu/drm/panel/panel-sitronix-st7701.c --- linux-6.1.66/drivers/gpu/drm/panel/panel-sitronix-st7701.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/panel/panel-sitronix-st7701.c 2023-12-13 11:50:59.264986385 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:10 @ #include <drm/drm_mipi_dsi.h> #include <drm/drm_modes.h> #include <drm/drm_panel.h> +#include <drm/drm_print.h> #include <linux/bitfield.h> #include <linux/gpio/consumer.h> #include <linux/delay.h> +#include <linux/media-bus-format.h> #include <linux/module.h> #include <linux/of_device.h> #include <linux/regulator/consumer.h> +#include <linux/spi/spi.h> #include <video/mipi_display.h> +#define SPI_DATA_FLAG 0x100 + /* Command2 BKx selection command */ #define DSI_CMD2BKX_SEL 0xFF @ linux/arch/arm/boot/dts/bcm2708.dtsi:61 @ #define DSI_CMD2BK1_SEL 0x11 #define DSI_CMD2BK3_SEL 0x13 #define DSI_CMD2BKX_SEL_NONE 0x00 +#define SPI_CMD2BK3_SEL (SPI_DATA_FLAG | DSI_CMD2BK3_SEL) +#define SPI_CMD2BK1_SEL (SPI_DATA_FLAG | DSI_CMD2BK1_SEL) +#define SPI_CMD2BK0_SEL (SPI_DATA_FLAG | DSI_CMD2BK0_SEL) +#define SPI_CMD2BKX_SEL_NONE (SPI_DATA_FLAG | DSI_CMD2BKX_SEL_NONE) /* Command2, BK0 bytes */ #define DSI_CMD2_BK0_GAMCTRL_AJ_MASK GENMASK(7, 6) @ linux/arch/arm/boot/dts/bcm2708.dtsi:124 @ struct st7701; +struct st7701; + +enum st7701_ctrl_if { + ST7701_CTRL_DSI, + ST7701_CTRL_SPI, +}; + struct st7701_panel_desc { const struct drm_display_mode *mode; unsigned int lanes; enum mipi_dsi_pixel_format format; + u32 mediabus_format; unsigned int panel_sleep_delay; + void (*init_sequence)(struct st7701 *st7701); + unsigned int conn_type; + enum st7701_ctrl_if interface; + u32 bus_flags; /* TFT matrix driver configuration, panel specific. */ const u8 pv_gamma[16]; /* Positive voltage gamma control */ @ linux/arch/arm/boot/dts/bcm2708.dtsi:166 @ struct st7701 { struct drm_panel panel; struct mipi_dsi_device *dsi; + struct spi_device *spi; + const struct device *dev; + const struct st7701_panel_desc *desc; struct regulator_bulk_data supplies[2]; @ linux/arch/arm/boot/dts/bcm2708.dtsi:218 @ return 0; } -static void st7701_init_sequence(struct st7701 *st7701) +#define ST7701_SPI(st7701, seq...) \ + { \ + const u16 d[] = { seq }; \ + struct spi_transfer xfer = { }; \ + struct spi_message spi; \ + \ + spi_message_init(&spi); \ + \ + xfer.tx_buf = d; \ + xfer.bits_per_word = 9; \ + xfer.len = sizeof(u16) * ARRAY_SIZE(d); \ + \ + spi_message_add_tail(&xfer, &spi); \ + spi_sync((st7701)->spi, &spi); \ + } + +static void ts8550b_init_sequence(struct st7701 *st7701) { const struct st7701_panel_desc *desc = st7701->desc; const struct drm_display_mode *mode = desc->mode; @ linux/arch/arm/boot/dts/bcm2708.dtsi:447 @ ST7701_DSI(st7701, 0x3A, 0x70); } +static void txw210001b0_init_sequence(struct st7701 *st7701) +{ + ST7701_SPI(st7701, MIPI_DCS_SOFT_RESET); + + usleep_range(5000, 7000); + + ST7701_SPI(st7701, DSI_CMD2BKX_SEL, + 0x177, 0x101, 0x100, 0x100, SPI_CMD2BK0_SEL); + + ST7701_SPI(st7701, DSI_CMD2_BK0_LNESET, 0x13B, 0x100); + + ST7701_SPI(st7701, DSI_CMD2_BK0_PORCTRL, 0x10B, 0x102); + + ST7701_SPI(st7701, DSI_CMD2_BK0_INVSEL, 0x100, 0x102); + + ST7701_SPI(st7701, 0xCC, 0x110); + + /* + * Gamma option B: + * Positive Voltage Gamma Control + */ + ST7701_SPI(st7701, DSI_CMD2_BK0_PVGAMCTRL, + 0x102, 0x113, 0x11B, 0x10D, 0x110, 0x105, 0x108, 0x107, + 0x107, 0x124, 0x104, 0x111, 0x10E, 0x12C, 0x133, 0x11D); + + /* Negative Voltage Gamma Control */ + ST7701_SPI(st7701, DSI_CMD2_BK0_NVGAMCTRL, + 0x105, 0x113, 0x11B, 0x10D, 0x111, 0x105, 0x108, 0x107, + 0x107, 0x124, 0x104, 0x111, 0x10E, 0x12C, 0x133, 0x11D); + + ST7701_SPI(st7701, DSI_CMD2BKX_SEL, + 0x177, 0x101, 0x100, 0x100, SPI_CMD2BK1_SEL); + + ST7701_SPI(st7701, DSI_CMD2_BK1_VRHS, 0x15D); + + ST7701_SPI(st7701, DSI_CMD2_BK1_VCOM, 0x143); + + ST7701_SPI(st7701, DSI_CMD2_BK1_VGHSS, 0x181); + + ST7701_SPI(st7701, DSI_CMD2_BK1_TESTCMD, 0x180); + + ST7701_SPI(st7701, DSI_CMD2_BK1_VGLS, 0x143); + + ST7701_SPI(st7701, DSI_CMD2_BK1_PWCTLR1, 0x185); + + ST7701_SPI(st7701, DSI_CMD2_BK1_PWCTLR2, 0x120); + + ST7701_SPI(st7701, DSI_CMD2_BK1_SPD1, 0x178); + + ST7701_SPI(st7701, DSI_CMD2_BK1_SPD2, 0x178); + + ST7701_SPI(st7701, DSI_CMD2_BK1_MIPISET1, 0x188); + + ST7701_SPI(st7701, 0xE0, 0x100, 0x100, 0x102); + + ST7701_SPI(st7701, 0xE1, + 0x103, 0x1A0, 0x100, 0x100, 0x104, 0x1A0, 0x100, 0x100, + 0x100, 0x120, 0x120); + + ST7701_SPI(st7701, 0xE2, + 0x100, 0x100, 0x100, 0x100, 0x100, 0x100, 0x100, 0x100, + 0x100, 0x100, 0x100, 0x100, 0x100); + + ST7701_SPI(st7701, 0xE3, 0x100, 0x100, 0x111, 0x100); + + ST7701_SPI(st7701, 0xE4, 0x122, 0x100); + + ST7701_SPI(st7701, 0xE5, + 0x105, 0x1EC, 0x1A0, 0x1A0, 0x107, 0x1EE, 0x1A0, 0x1A0, + 0x100, 0x100, 0x100, 0x100, 0x100, 0x100, 0x100, 0x100); + + ST7701_SPI(st7701, 0xE6, 0x100, 0x100, 0x111, 0x100); + + ST7701_SPI(st7701, 0xE7, 0x122, 0x100); + + ST7701_SPI(st7701, 0xE8, + 0x106, 0x1ED, 0x1A0, 0x1A0, 0x108, 0x1EF, 0x1A0, 0x1A0, + 0x100, 0x100, 0x100, 0x100, 0x100, 0x100, 0x100, 0x100); + + ST7701_SPI(st7701, 0xEB, + 0x100, 0x100, 0x140, 0x140, 0x100, 0x100, 0x100); + + ST7701_SPI(st7701, 0xED, + 0x1FF, 0x1FF, 0x1FF, 0x1BA, 0x10A, 0x1BF, 0x145, 0x1FF, + 0x1FF, 0x154, 0x1FB, 0x1A0, 0x1AB, 0x1FF, 0x1FF, 0x1FF); + + ST7701_SPI(st7701, 0xEF, 0x110, 0x10D, 0x104, 0x108, 0x13F, 0x11F); + + ST7701_SPI(st7701, DSI_CMD2BKX_SEL, + 0x177, 0x101, 0x100, 0x100, SPI_CMD2BK3_SEL); + + ST7701_SPI(st7701, 0xEF, 0x108); + + ST7701_SPI(st7701, DSI_CMD2BKX_SEL, + 0x177, 0x101, 0x100, 0x100, SPI_CMD2BKX_SEL_NONE); + + ST7701_SPI(st7701, 0xCD, 0x108); /* RGB format COLCTRL */ + + ST7701_SPI(st7701, 0x36, 0x108); /* MadCtl */ + + ST7701_SPI(st7701, 0x3A, 0x166); /* Colmod */ + + ST7701_SPI(st7701, MIPI_DCS_EXIT_SLEEP_MODE); +} + static int st7701_prepare(struct drm_panel *panel) { struct st7701 *st7701 = panel_to_st7701(panel); @ linux/arch/arm/boot/dts/bcm2708.dtsi:568 @ gpiod_set_value(st7701->reset, 1); msleep(150); - st7701_init_sequence(st7701); + st7701->desc->init_sequence(st7701); if (st7701->desc->gip_sequence) st7701->desc->gip_sequence(st7701); /* Disable Command2 */ - ST7701_DSI(st7701, DSI_CMD2BKX_SEL, - 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); + switch (st7701->desc->interface) { + case ST7701_CTRL_DSI: + ST7701_DSI(st7701, DSI_CMD2BKX_SEL, + 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); + break; + case ST7701_CTRL_SPI: + ST7701_SPI(st7701, DSI_CMD2BKX_SEL, + 0x177, 0x101, 0x100, 0x100, SPI_CMD2BKX_SEL_NONE); + break; + } return 0; } @ linux/arch/arm/boot/dts/bcm2708.dtsi:592 @ { struct st7701 *st7701 = panel_to_st7701(panel); - ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00); + switch (st7701->desc->interface) { + case ST7701_CTRL_DSI: + ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00); + break; + case ST7701_CTRL_SPI: + ST7701_SPI(st7701, MIPI_DCS_SET_DISPLAY_ON); + msleep(30); + break; + } return 0; } @ linux/arch/arm/boot/dts/bcm2708.dtsi:609 @ { struct st7701 *st7701 = panel_to_st7701(panel); - ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00); + switch (st7701->desc->interface) { + case ST7701_CTRL_DSI: + ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00); + break; + case ST7701_CTRL_SPI: + ST7701_SPI(st7701, MIPI_DCS_SET_DISPLAY_OFF); + break; + } return 0; } @ linux/arch/arm/boot/dts/bcm2708.dtsi:625 @ { struct st7701 *st7701 = panel_to_st7701(panel); - ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00); + switch (st7701->desc->interface) { + case ST7701_CTRL_DSI: + ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00); + break; + case ST7701_CTRL_SPI: + ST7701_SPI(st7701, MIPI_DCS_ENTER_SLEEP_MODE); + break; + } msleep(st7701->sleep_delay); @ linux/arch/arm/boot/dts/bcm2708.dtsi:663 @ mode = drm_mode_duplicate(connector->dev, desc_mode); if (!mode) { - dev_err(&st7701->dsi->dev, "failed to add mode %ux%u@%u\n", + dev_err(st7701->dev, "failed to add mode %ux%u@%u\n", desc_mode->hdisplay, desc_mode->vdisplay, drm_mode_vrefresh(desc_mode)); return -ENOMEM; @ linux/arch/arm/boot/dts/bcm2708.dtsi:672 @ drm_mode_set_name(mode); drm_mode_probed_add(connector, mode); + if (st7701->desc->mediabus_format) + drm_display_info_set_bus_formats(&connector->display_info, + &st7701->desc->mediabus_format, + 1); + connector->display_info.bus_flags = 0; + connector->display_info.width_mm = desc_mode->width_mm; connector->display_info.height_mm = desc_mode->height_mm; + if (st7701->desc->bus_flags) + connector->display_info.bus_flags = st7701->desc->bus_flags; + return 1; } @ linux/arch/arm/boot/dts/bcm2708.dtsi:719 @ .lanes = 2, .format = MIPI_DSI_FMT_RGB888, .panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */ + .init_sequence = ts8550b_init_sequence, + .conn_type = DRM_MODE_CONNECTOR_DSI, + .interface = ST7701_CTRL_DSI, .pv_gamma = { CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | @ linux/arch/arm/boot/dts/bcm2708.dtsi:898 @ .gip_sequence = dmt028vghmcmi_1a_gip_sequence, }; -static int st7701_dsi_probe(struct mipi_dsi_device *dsi) +static const struct drm_display_mode txw210001b0_mode = { + .clock = 19200, + + .hdisplay = 480, + .hsync_start = 480 + 10, + .hsync_end = 480 + 10 + 16, + .htotal = 480 + 10 + 16 + 56, + + .vdisplay = 480, + .vsync_start = 480 + 15, + .vsync_end = 480 + 15 + 60, + .vtotal = 480 + 15 + 60 + 15, + + .width_mm = 53, + .height_mm = 53, + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, + + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct st7701_panel_desc txw210001b0_desc = { + .mode = &txw210001b0_mode, + .mediabus_format = MEDIA_BUS_FMT_RGB888_1X24, + .init_sequence = txw210001b0_init_sequence, + .conn_type = DRM_MODE_CONNECTOR_DPI, + .interface = ST7701_CTRL_SPI, + .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, +}; + +static const struct st7701_panel_desc hyperpixel2r_desc = { + .mode = &txw210001b0_mode, + .mediabus_format = MEDIA_BUS_FMT_RGB666_1X24_CPADHI, + .init_sequence = txw210001b0_init_sequence, + .conn_type = DRM_MODE_CONNECTOR_DPI, + .interface = ST7701_CTRL_SPI, + .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, +}; + +static int st7701_probe(struct device *dev, struct st7701 **ret_st7701) { const struct st7701_panel_desc *desc; struct st7701 *st7701; int ret; - st7701 = devm_kzalloc(&dsi->dev, sizeof(*st7701), GFP_KERNEL); + st7701 = devm_kzalloc(dev, sizeof(*st7701), GFP_KERNEL); if (!st7701) return -ENOMEM; - desc = of_device_get_match_data(&dsi->dev); - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; - dsi->format = desc->format; - dsi->lanes = desc->lanes; + desc = of_device_get_match_data(dev); + if (!desc) + return -EINVAL; st7701->supplies[0].supply = "VCC"; st7701->supplies[1].supply = "IOVCC"; - ret = devm_regulator_bulk_get(&dsi->dev, ARRAY_SIZE(st7701->supplies), + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st7701->supplies), st7701->supplies); if (ret < 0) return ret; - st7701->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW); + st7701->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(st7701->reset)) { - dev_err(&dsi->dev, "Couldn't get our reset GPIO\n"); + dev_err(dev, "Couldn't get our reset GPIO\n"); return PTR_ERR(st7701->reset); } - drm_panel_init(&st7701->panel, &dsi->dev, &st7701_funcs, - DRM_MODE_CONNECTOR_DSI); + drm_panel_init(&st7701->panel, dev, &st7701_funcs, + desc->conn_type); /** * Once sleep out has been issued, ST7701 IC required to wait 120ms @ linux/arch/arm/boot/dts/bcm2708.dtsi:984 @ drm_panel_add(&st7701->panel); + st7701->desc = desc; + st7701->dev = dev; + + *ret_st7701 = st7701; + + return 0; +} + +static int st7701_dsi_probe(struct mipi_dsi_device *dsi) +{ + struct st7701 *st7701; + int ret; + + ret = st7701_probe(&dsi->dev, &st7701); + + if (ret) + return ret; + + dsi->mode_flags = MIPI_DSI_MODE_VIDEO; + dsi->format = st7701->desc->format; + dsi->lanes = st7701->desc->lanes; + mipi_dsi_set_drvdata(dsi, st7701); st7701->dsi = dsi; - st7701->desc = desc; ret = mipi_dsi_attach(dsi); if (ret) @ linux/arch/arm/boot/dts/bcm2708.dtsi:1028 @ drm_panel_remove(&st7701->panel); } -static const struct of_device_id st7701_of_match[] = { +static const struct of_device_id st7701_dsi_of_match[] = { { .compatible = "densitron,dmt028vghmcmi-1a", .data = &dmt028vghmcmi_1a_desc }, { .compatible = "techstar,ts8550b", .data = &ts8550b_desc }, { } }; -MODULE_DEVICE_TABLE(of, st7701_of_match); +MODULE_DEVICE_TABLE(of, st7701_dsi_of_match); static struct mipi_dsi_driver st7701_dsi_driver = { .probe = st7701_dsi_probe, .remove = st7701_dsi_remove, .driver = { .name = "st7701", - .of_match_table = st7701_of_match, + .of_match_table = st7701_dsi_of_match, + }, +}; + +/* SPI display probe */ +static const struct of_device_id st7701_spi_of_match[] = { + { .compatible = "txw,txw210001b0", + .data = &txw210001b0_desc, + }, { + .compatible = "pimoroni,hyperpixel2round", + .data = &hyperpixel2r_desc, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, st7701_spi_of_match); + +static int st7701_spi_probe(struct spi_device *spi) +{ + struct st7701 *st7701; + int ret; + + spi->mode = SPI_MODE_3; + spi->bits_per_word = 9; + ret = spi_setup(spi); + if (ret < 0) { + dev_err(&spi->dev, "failed to setup SPI: %d\n", ret); + return ret; + } + + ret = st7701_probe(&spi->dev, &st7701); + + if (ret) + return ret; + + spi_set_drvdata(spi, st7701); + st7701->spi = spi; + + return 0; +} + +static void st7701_spi_remove(struct spi_device *spi) +{ + struct st7701 *ctx = spi_get_drvdata(spi); + + drm_panel_remove(&ctx->panel); +} + +static const struct spi_device_id st7701_spi_ids[] = { + { "txw210001b0", 0 }, + { "hyperpixel2round", 0 }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(spi, st7701_spi_ids); + +static struct spi_driver st7701_spi_driver = { + .probe = st7701_spi_probe, + .remove = st7701_spi_remove, + .driver = { + .name = "st7701", + .of_match_table = st7701_spi_of_match, }, + .id_table = st7701_spi_ids, }; -module_mipi_dsi_driver(st7701_dsi_driver); + +static int __init panel_st7701_init(void) +{ + int err; + + err = spi_register_driver(&st7701_spi_driver); + if (err < 0) + return err; + + if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { + err = mipi_dsi_driver_register(&st7701_dsi_driver); + if (err < 0) + goto err_did_spi_register; + } + + return 0; + +err_did_spi_register: + spi_unregister_driver(&st7701_spi_driver); + + return err; +} +module_init(panel_st7701_init); + +static void __exit panel_st7701_exit(void) +{ + if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) + mipi_dsi_driver_unregister(&st7701_dsi_driver); + + spi_unregister_driver(&st7701_spi_driver); +} +module_exit(panel_st7701_exit); MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>"); MODULE_DESCRIPTION("Sitronix ST7701 LCD Panel Driver"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/panel/panel-tdo-y17p.c linux/drivers/gpu/drm/panel/panel-tdo-y17p.c --- linux-6.1.66/drivers/gpu/drm/panel/panel-tdo-y17p.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/panel/panel-tdo-y17p.c 2023-12-13 11:50:59.266986389 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-only +/* + * TDO Y17P TFT LCD drm_panel driver. + * + * SPI configured DPI display controller + * Copyright (C) 2022 Raspberry Pi Ltd + * + * Derived from drivers/drm/gpu/panel/panel-sitronix-st7789v.c + * Copyright (C) 2017 Free Electrons + */ + +#include <drm/drm_modes.h> +#include <drm/drm_panel.h> + +#include <linux/bitops.h> +#include <linux/gpio/consumer.h> +#include <linux/media-bus-format.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h> +#include <linux/spi/spi.h> + +#include <video/mipi_display.h> +#include <video/of_videomode.h> +#include <video/videomode.h> + +struct tdo_y17p { + struct drm_panel panel; + struct spi_device *spi; + struct gpio_desc *reset; + struct regulator *power; + u32 bus_format; +}; + +static const u16 panel_init[] = { + 0x0ff, 0x1ff, 0x198, 0x106, 0x104, 0x101, 0x008, 0x110, + 0x021, 0x109, 0x030, 0x102, 0x031, 0x100, 0x040, 0x110, + 0x041, 0x155, 0x042, 0x102, 0x043, 0x109, 0x044, 0x107, + 0x050, 0x178, 0x051, 0x178, 0x052, 0x100, 0x053, 0x16d, + 0x060, 0x107, 0x061, 0x100, 0x062, 0x108, 0x063, 0x100, + 0x0a0, 0x100, 0x0a1, 0x107, 0x0a2, 0x10c, 0x0a3, 0x10b, + 0x0a4, 0x103, 0x0a5, 0x107, 0x0a6, 0x106, 0x0a7, 0x104, + 0x0a8, 0x108, 0x0a9, 0x10c, 0x0aa, 0x113, 0x0ab, 0x106, + 0x0ac, 0x10d, 0x0ad, 0x119, 0x0ae, 0x110, 0x0af, 0x100, + 0x0c0, 0x100, 0x0c1, 0x107, 0x0c2, 0x10c, 0x0c3, 0x10b, + 0x0c4, 0x103, 0x0c5, 0x107, 0x0c6, 0x107, 0x0c7, 0x104, + 0x0c8, 0x108, 0x0c9, 0x10c, 0x0ca, 0x113, 0x0cb, 0x106, + 0x0cc, 0x10d, 0x0cd, 0x118, 0x0ce, 0x110, 0x0cf, 0x100, + 0x0ff, 0x1ff, 0x198, 0x106, 0x104, 0x106, 0x000, 0x120, + 0x001, 0x10a, 0x002, 0x100, 0x003, 0x100, 0x004, 0x101, + 0x005, 0x101, 0x006, 0x198, 0x007, 0x106, 0x008, 0x101, + 0x009, 0x180, 0x00a, 0x100, 0x00b, 0x100, 0x00c, 0x101, + 0x00d, 0x101, 0x00e, 0x100, 0x00f, 0x100, 0x010, 0x1f0, + 0x011, 0x1f4, 0x012, 0x101, 0x013, 0x100, 0x014, 0x100, + 0x015, 0x1c0, 0x016, 0x108, 0x017, 0x100, 0x018, 0x100, + 0x019, 0x100, 0x01a, 0x100, 0x01b, 0x100, 0x01c, 0x100, + 0x01d, 0x100, 0x020, 0x101, 0x021, 0x123, 0x022, 0x145, + 0x023, 0x167, 0x024, 0x101, 0x025, 0x123, 0x026, 0x145, + 0x027, 0x167, 0x030, 0x111, 0x031, 0x111, 0x032, 0x100, + 0x033, 0x1ee, 0x034, 0x1ff, 0x035, 0x1bb, 0x036, 0x1aa, + 0x037, 0x1dd, 0x038, 0x1cc, 0x039, 0x166, 0x03a, 0x177, + 0x03b, 0x122, 0x03c, 0x122, 0x03d, 0x122, 0x03e, 0x122, + 0x03f, 0x122, 0x040, 0x122, 0x052, 0x110, 0x053, 0x110, + 0x0ff, 0x1ff, 0x198, 0x106, 0x104, 0x107, 0x018, 0x11d, + 0x017, 0x122, 0x002, 0x177, 0x026, 0x1b2, 0x0e1, 0x179, + 0x0ff, 0x1ff, 0x198, 0x106, 0x104, 0x100, 0x03a, 0x160, + 0x035, 0x100, 0x011, 0x100, +}; + +#define NUM_INIT_REGS ARRAY_SIZE(panel_init) + +static inline struct tdo_y17p *panel_to_tdo_y17p(struct drm_panel *panel) +{ + return container_of(panel, struct tdo_y17p, panel); +} + +static int tdo_y17p_write_msg(struct tdo_y17p *ctx, const u16 *msg, unsigned int len) +{ + struct spi_transfer xfer = { }; + struct spi_message spi; + + spi_message_init(&spi); + + xfer.tx_buf = msg; + xfer.bits_per_word = 9; + xfer.len = sizeof(u16) * len; + + spi_message_add_tail(&xfer, &spi); + return spi_sync(ctx->spi, &spi); +} + +static const struct drm_display_mode tdo_y17pe_720x720_mode = { + .clock = 36720, + .hdisplay = 720, + .hsync_start = 720 + 20, + .hsync_end = 720 + 20 + 20, + .htotal = 720 + 20 + 20 + 40, + .vdisplay = 720, + .vsync_start = 720 + 15, + .vsync_end = 720 + 15 + 15, + .vtotal = 720 + 15 + 15 + 15, + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, +}; + +static int tdo_y17p_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct tdo_y17p *ctx = panel_to_tdo_y17p(panel); + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(connector->dev, &tdo_y17pe_720x720_mode); + if (!mode) { + dev_err(panel->dev, "failed to add mode %ux%ux@%u\n", + tdo_y17pe_720x720_mode.hdisplay, + tdo_y17pe_720x720_mode.vdisplay, + drm_mode_vrefresh(&tdo_y17pe_720x720_mode)); + return -ENOMEM; + } + + drm_mode_set_name(mode); + + mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + drm_mode_probed_add(connector, mode); + + connector->display_info.width_mm = 72; + connector->display_info.height_mm = 72; + drm_display_info_set_bus_formats(&connector->display_info, + &ctx->bus_format, 1); + connector->display_info.bus_flags = 0; + + return 1; +} + +static int tdo_y17p_prepare(struct drm_panel *panel) +{ + struct tdo_y17p *ctx = panel_to_tdo_y17p(panel); + int ret; + + ret = regulator_enable(ctx->power); + if (ret) + return ret; + + ret = tdo_y17p_write_msg(ctx, panel_init, NUM_INIT_REGS); + + msleep(120); + + return ret; +} + +static int tdo_y17p_enable(struct drm_panel *panel) +{ + struct tdo_y17p *ctx = panel_to_tdo_y17p(panel); + const u16 msg[] = { MIPI_DCS_SET_DISPLAY_ON }; + int ret; + + ret = tdo_y17p_write_msg(ctx, msg, ARRAY_SIZE(msg)); + + return ret; +} + +static int tdo_y17p_disable(struct drm_panel *panel) +{ + struct tdo_y17p *ctx = panel_to_tdo_y17p(panel); + const u16 msg[] = { MIPI_DCS_SET_DISPLAY_OFF }; + int ret; + + ret = tdo_y17p_write_msg(ctx, msg, ARRAY_SIZE(msg)); + + return ret; +} + +static int tdo_y17p_unprepare(struct drm_panel *panel) +{ + struct tdo_y17p *ctx = panel_to_tdo_y17p(panel); + const u16 msg[] = { MIPI_DCS_ENTER_SLEEP_MODE }; + int ret; + + ret = tdo_y17p_write_msg(ctx, msg, ARRAY_SIZE(msg)); + + return ret; +} + +static const struct drm_panel_funcs tdo_y17p_drm_funcs = { + .disable = tdo_y17p_disable, + .enable = tdo_y17p_enable, + .get_modes = tdo_y17p_get_modes, + .prepare = tdo_y17p_prepare, + .unprepare = tdo_y17p_unprepare, +}; + +static const struct of_device_id tdo_y17p_of_match[] = { + { .compatible = "tdo,tl040hds20ct", + .data = (void *)MEDIA_BUS_FMT_BGR888_1X24, + }, { + .compatible = "pimoroni,hyperpixel4square", + .data = (void *)MEDIA_BUS_FMT_BGR666_1X24_CPADHI, + }, { + .compatible = "tdo,y17p", + .data = (void *)MEDIA_BUS_FMT_BGR888_1X24, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, tdo_y17p_of_match); + +static int tdo_y17p_probe(struct spi_device *spi) +{ + const struct of_device_id *id; + struct tdo_y17p *ctx; + int ret; + + ctx = devm_kzalloc(&spi->dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + id = of_match_node(tdo_y17p_of_match, spi->dev.of_node); + if (!id) + return -ENODEV; + + ctx->bus_format = (u32)(uintptr_t)id->data; + + spi_set_drvdata(spi, ctx); + ctx->spi = spi; + + drm_panel_init(&ctx->panel, &spi->dev, &tdo_y17p_drm_funcs, + DRM_MODE_CONNECTOR_DPI); + + ctx->power = devm_regulator_get(&spi->dev, "power"); + if (IS_ERR(ctx->power)) + return PTR_ERR(ctx->power); + + ctx->reset = devm_gpiod_get_optional(&spi->dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(ctx->reset)) { + dev_err(&spi->dev, "Couldn't get our reset line\n"); + return PTR_ERR(ctx->reset); + } + + ret = drm_panel_of_backlight(&ctx->panel); + if (ret) + return ret; + + drm_panel_add(&ctx->panel); + + return 0; +} + +static void tdo_y17p_remove(struct spi_device *spi) +{ + struct tdo_y17p *ctx = spi_get_drvdata(spi); + + drm_panel_remove(&ctx->panel); +} + +static const struct spi_device_id tdo_y17p_ids[] = { + { "tl040hds20ct", 0 }, + { "hyperpixel4square", 0 }, + { "y17p", 0 }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(spi, tdo_y17p_ids); + +static struct spi_driver tdo_y17p_driver = { + .probe = tdo_y17p_probe, + .remove = tdo_y17p_remove, + .driver = { + .name = "tdo_y17p", + .of_match_table = tdo_y17p_of_match, + }, + .id_table = tdo_y17p_ids, +}; +module_spi_driver(tdo_y17p_driver); + +MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com>"); +MODULE_DESCRIPTION("TDO Y17P LCD panel driver"); +MODULE_LICENSE("GPL v2"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/panel/panel-waveshare-dsi.c linux/drivers/gpu/drm/panel/panel-waveshare-dsi.c --- linux-6.1.66/drivers/gpu/drm/panel/panel-waveshare-dsi.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/panel/panel-waveshare-dsi.c 2023-12-13 11:50:59.268986394 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright © 2023 Raspberry Pi Ltd + * + * Based on panel-raspberrypi-touchscreen by Broadcom + */ + +#include <linux/backlight.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/fb.h> +#include <linux/i2c.h> +#include <linux/media-bus-format.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_graph.h> +#include <linux/pm.h> + +#include <drm/drm_crtc.h> +#include <drm/drm_device.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_panel.h> + +#define WS_DSI_DRIVER_NAME "ws-ts-dsi" + +struct ws_panel { + struct drm_panel base; + struct mipi_dsi_device *dsi; + struct i2c_client *i2c; + const struct drm_display_mode *mode; + enum drm_panel_orientation orientation; +}; + +/* 2.8inch 480x640 + * https://www.waveshare.com/product/raspberry-pi/displays/2.8inch-dsi-lcd.htm + */ +static const struct drm_display_mode ws_panel_2_8_mode = { + .clock = 50000, + .hdisplay = 480, + .hsync_start = 480 + 150, + .hsync_end = 480 + 150 + 50, + .htotal = 480 + 150 + 50 + 150, + .vdisplay = 640, + .vsync_start = 640 + 150, + .vsync_end = 640 + 150 + 50, + .vtotal = 640 + 150 + 50 + 150, +}; + +/* 3.4inch 800x800 Round + * https://www.waveshare.com/product/displays/lcd-oled/3.4inch-dsi-lcd-c.htm + */ +static const struct drm_display_mode ws_panel_3_4_mode = { + .clock = 50000, + .hdisplay = 800, + .hsync_start = 800 + 32, + .hsync_end = 800 + 32 + 6, + .htotal = 800 + 32 + 6 + 120, + .vdisplay = 800, + .vsync_start = 800 + 8, + .vsync_end = 800 + 8 + 4, + .vtotal = 800 + 8 + 4 + 16, +}; + +/* 4.0inch 480x800 + * https://www.waveshare.com/product/raspberry-pi/displays/4inch-dsi-lcd.htm + */ +static const struct drm_display_mode ws_panel_4_0_mode = { + .clock = 50000, + .hdisplay = 480, + .hsync_start = 480 + 150, + .hsync_end = 480 + 150 + 100, + .htotal = 480 + 150 + 100 + 150, + .vdisplay = 800, + .vsync_start = 800 + 20, + .vsync_end = 800 + 20 + 100, + .vtotal = 800 + 20 + 100 + 20, +}; + +/* 7.0inch C 1024x600 + * https://www.waveshare.com/product/raspberry-pi/displays/lcd-oled/7inch-dsi-lcd-c-with-case-a.htm + */ +static const struct drm_display_mode ws_panel_7_0_c_mode = { + .clock = 50000, + .hdisplay = 1024, + .hsync_start = 1024 + 100, + .hsync_end = 1024 + 100 + 100, + .htotal = 1024 + 100 + 100 + 100, + .vdisplay = 600, + .vsync_start = 600 + 10, + .vsync_end = 600 + 10 + 10, + .vtotal = 600 + 10 + 10 + 10, +}; + +/* 7.9inch 400x1280 + * https://www.waveshare.com/product/raspberry-pi/displays/7.9inch-dsi-lcd.htm + */ +static const struct drm_display_mode ws_panel_7_9_mode = { + .clock = 50000, + .hdisplay = 400, + .hsync_start = 400 + 40, + .hsync_end = 400 + 40 + 30, + .htotal = 400 + 40 + 30 + 40, + .vdisplay = 1280, + .vsync_start = 1280 + 20, + .vsync_end = 1280 + 20 + 10, + .vtotal = 1280 + 20 + 10 + 20, +}; + +/* 8.0inch or 10.1inch 1280x800 + * https://www.waveshare.com/product/raspberry-pi/displays/8inch-dsi-lcd-c.htm + * https://www.waveshare.com/product/raspberry-pi/displays/10.1inch-dsi-lcd-c.htm + */ +static const struct drm_display_mode ws_panel_10_1_mode = { + .clock = 83333, + .hdisplay = 1280, + .hsync_start = 1280 + 156, + .hsync_end = 1280 + 156 + 20, + .htotal = 1280 + 156 + 20 + 40, + .vdisplay = 800, + .vsync_start = 800 + 40, + .vsync_end = 800 + 40 + 48, + .vtotal = 800 + 40 + 48 + 40, +}; + +/* 11.9inch 320x1480 + * https://www.waveshare.com/product/raspberry-pi/displays/11.9inch-dsi-lcd.htm + */ +static const struct drm_display_mode ws_panel_11_9_mode = { + .clock = 50000, + .hdisplay = 320, + .hsync_start = 320 + 60, + .hsync_end = 320 + 60 + 60, + .htotal = 320 + 60 + 60 + 120, + .vdisplay = 1480, + .vsync_start = 1480 + 60, + .vsync_end = 1480 + 60 + 60, + .vtotal = 1480 + 60 + 60 + 60, +}; + +static struct ws_panel *panel_to_ts(struct drm_panel *panel) +{ + return container_of(panel, struct ws_panel, base); +} + +static void ws_panel_i2c_write(struct ws_panel *ts, u8 reg, u8 val) +{ + int ret; + + ret = i2c_smbus_write_byte_data(ts->i2c, reg, val); + if (ret) + dev_err(&ts->i2c->dev, "I2C write failed: %d\n", ret); +} + +static int ws_panel_disable(struct drm_panel *panel) +{ + struct ws_panel *ts = panel_to_ts(panel); + + ws_panel_i2c_write(ts, 0xad, 0x00); + + return 0; +} + +static int ws_panel_unprepare(struct drm_panel *panel) +{ + return 0; +} + +static int ws_panel_prepare(struct drm_panel *panel) +{ + return 0; +} + +static int ws_panel_enable(struct drm_panel *panel) +{ + struct ws_panel *ts = panel_to_ts(panel); + + ws_panel_i2c_write(ts, 0xad, 0x01); + + return 0; +} + +static int ws_panel_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + static const u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; + struct ws_panel *ts = panel_to_ts(panel); + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(connector->dev, ts->mode); + if (!mode) { + dev_err(panel->dev, "failed to add mode %ux%u@%u\n", + ts->mode->hdisplay, + ts->mode->vdisplay, + drm_mode_vrefresh(ts->mode)); + } + + mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + + drm_mode_set_name(mode); + + drm_mode_probed_add(connector, mode); + + connector->display_info.bpc = 8; + connector->display_info.width_mm = 154; + connector->display_info.height_mm = 86; + drm_display_info_set_bus_formats(&connector->display_info, + &bus_format, 1); + + /* + * TODO: Remove once all drm drivers call + * drm_connector_set_orientation_from_panel() + */ + drm_connector_set_panel_orientation(connector, ts->orientation); + + return 1; +} + +static enum drm_panel_orientation ws_panel_get_orientation(struct drm_panel *panel) +{ + struct ws_panel *ts = panel_to_ts(panel); + + return ts->orientation; +} + +static const struct drm_panel_funcs ws_panel_funcs = { + .disable = ws_panel_disable, + .unprepare = ws_panel_unprepare, + .prepare = ws_panel_prepare, + .enable = ws_panel_enable, + .get_modes = ws_panel_get_modes, + .get_orientation = ws_panel_get_orientation, +}; + +static int ws_panel_bl_update_status(struct backlight_device *bl) +{ + struct ws_panel *ts = bl_get_data(bl); + + ws_panel_i2c_write(ts, 0xab, 0xff - backlight_get_brightness(bl)); + ws_panel_i2c_write(ts, 0xaa, 0x01); + + return 0; +} + +static const struct backlight_ops ws_panel_bl_ops = { + .update_status = ws_panel_bl_update_status, +}; + +static struct backlight_device * +ws_panel_create_backlight(struct ws_panel *ts) +{ + struct device *dev = ts->base.dev; + const struct backlight_properties props = { + .type = BACKLIGHT_RAW, + .brightness = 255, + .max_brightness = 255, + }; + + return devm_backlight_device_register(dev, dev_name(dev), dev, ts, + &ws_panel_bl_ops, &props); +} + +static int ws_panel_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct device *dev = &i2c->dev; + struct ws_panel *ts; + struct device_node *endpoint, *dsi_host_node; + struct mipi_dsi_host *host; + struct mipi_dsi_device_info info = { + .type = WS_DSI_DRIVER_NAME, + .channel = 0, + .node = NULL, + }; + int ret; + + ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL); + if (!ts) + return -ENOMEM; + + ts->mode = of_device_get_match_data(dev); + if (!ts->mode) + return -EINVAL; + + i2c_set_clientdata(i2c, ts); + + ts->i2c = i2c; + + ws_panel_i2c_write(ts, 0xc0, 0x01); + ws_panel_i2c_write(ts, 0xc2, 0x01); + ws_panel_i2c_write(ts, 0xac, 0x01); + + ret = of_drm_get_panel_orientation(dev->of_node, &ts->orientation); + if (ret) { + dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, ret); + return ret; + } + + /* Look up the DSI host. It needs to probe before we do. */ + endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); + if (!endpoint) + return -ENODEV; + + dsi_host_node = of_graph_get_remote_port_parent(endpoint); + if (!dsi_host_node) + goto error; + + host = of_find_mipi_dsi_host_by_node(dsi_host_node); + of_node_put(dsi_host_node); + if (!host) { + of_node_put(endpoint); + return -EPROBE_DEFER; + } + + info.node = of_graph_get_remote_port(endpoint); + if (!info.node) + goto error; + + of_node_put(endpoint); + + ts->dsi = devm_mipi_dsi_device_register_full(dev, host, &info); + if (IS_ERR(ts->dsi)) { + dev_err(dev, "DSI device registration failed: %ld\n", + PTR_ERR(ts->dsi)); + return PTR_ERR(ts->dsi); + } + + drm_panel_init(&ts->base, dev, &ws_panel_funcs, + DRM_MODE_CONNECTOR_DSI); + + ts->base.backlight = ws_panel_create_backlight(ts); + if (IS_ERR(ts->base.backlight)) { + ret = PTR_ERR(ts->base.backlight); + dev_err(dev, "Failed to create backlight: %d\n", ret); + return ret; + } + + /* This appears last, as it's what will unblock the DSI host + * driver's component bind function. + */ + drm_panel_add(&ts->base); + + ts->dsi->mode_flags = (MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM); + ts->dsi->format = MIPI_DSI_FMT_RGB888; + ts->dsi->lanes = 2; + + ret = devm_mipi_dsi_attach(dev, ts->dsi); + + if (ret) + dev_err(dev, "failed to attach dsi to host: %d\n", ret); + + return 0; + +error: + of_node_put(endpoint); + return -ENODEV; +} + +static void ws_panel_remove(struct i2c_client *i2c) +{ + struct ws_panel *ts = i2c_get_clientdata(i2c); + + ws_panel_disable(&ts->base); + + drm_panel_remove(&ts->base); +} + +static void ws_panel_shutdown(struct i2c_client *i2c) +{ + struct ws_panel *ts = i2c_get_clientdata(i2c); + + ws_panel_disable(&ts->base); +} + +static const struct of_device_id ws_panel_of_ids[] = { + { + .compatible = "waveshare,2.8inch-panel", + .data = &ws_panel_2_8_mode, + }, { + .compatible = "waveshare,3.4inch-panel", + .data = &ws_panel_3_4_mode, + }, { + .compatible = "waveshare,4.0inch-panel", + .data = &ws_panel_4_0_mode, + }, { + .compatible = "waveshare,7.0inch-c-panel", + .data = &ws_panel_7_0_c_mode, + }, { + .compatible = "waveshare,7.9inch-panel", + .data = &ws_panel_7_9_mode, + }, { + .compatible = "waveshare,8.0inch-panel", + .data = &ws_panel_10_1_mode, + }, { + .compatible = "waveshare,10.1inch-panel", + .data = &ws_panel_10_1_mode, + }, { + .compatible = "waveshare,11.9inch-panel", + .data = &ws_panel_11_9_mode, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, ws_panel_of_ids); + +static struct i2c_driver ws_panel_driver = { + .driver = { + .name = "ws_touchscreen", + .of_match_table = ws_panel_of_ids, + }, + .probe = ws_panel_probe, + .remove = ws_panel_remove, + .shutdown = ws_panel_shutdown, +}; +module_i2c_driver(ws_panel_driver); + +MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com>"); +MODULE_DESCRIPTION("Waveshare DSI panel driver"); +MODULE_LICENSE("GPL"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/Kconfig linux/drivers/gpu/drm/rp1/Kconfig --- linux-6.1.66/drivers/gpu/drm/rp1/Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/Kconfig 2023-12-13 11:50:59.406986719 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:2 @ +source "drivers/gpu/drm/rp1/rp1-dsi/Kconfig" + +source "drivers/gpu/drm/rp1/rp1-dpi/Kconfig" + +source "drivers/gpu/drm/rp1/rp1-vec/Kconfig" diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/Makefile linux/drivers/gpu/drm/rp1/Makefile --- linux-6.1.66/drivers/gpu/drm/rp1/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/Makefile 2023-12-13 11:50:59.406986719 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:1 @ +obj-$(CONFIG_DRM_RP1_DSI) += rp1-dsi/ +obj-$(CONFIG_DRM_RP1_DPI) += rp1-dpi/ +obj-$(CONFIG_DRM_RP1_VEC) += rp1-vec/ + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-dpi/Kconfig linux/drivers/gpu/drm/rp1/rp1-dpi/Kconfig --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-dpi/Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-dpi/Kconfig 2023-12-13 11:50:59.406986719 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: GPL-2.0-only +config DRM_RP1_DPI + tristate "DRM Support for RP1 DPI" + depends on DRM + select MFD_RP1 + select DRM_GEM_DMA_HELPER + select DRM_KMS_HELPER + select DRM_VRAM_HELPER + select DRM_TTM + select DRM_TTM_HELPER + help + Choose this option to enable Video Out on RP1 diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-dpi/Makefile linux/drivers/gpu/drm/rp1/rp1-dpi/Makefile --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-dpi/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-dpi/Makefile 2023-12-13 11:50:59.406986719 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:2 @ +# SPDX-License-Identifier: GPL-2.0-only + +drm-rp1-dpi-y := rp1_dpi.o rp1_dpi_hw.o rp1_dpi_cfg.o + +obj-$(CONFIG_DRM_RP1_DPI) += drm-rp1-dpi.o diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.c linux/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.c --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.c 2023-12-13 11:50:59.407986721 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DRM Driver for DPI output on Raspberry Pi RP1 + * + * Copyright (c) 2023 Raspberry Pi Limited. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/mm.h> +#include <linux/fb.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/list.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/printk.h> +#include <linux/console.h> +#include <linux/debugfs.h> +#include <linux/uaccess.h> +#include <linux/io.h> +#include <linux/dma-mapping.h> +#include <linux/cred.h> +#include <linux/media-bus-format.h> +#include <linux/pinctrl/consumer.h> +#include <drm/drm_drv.h> +#include <drm/drm_mm.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_gem_atomic_helper.h> +#include <drm/drm_gem_dma_helper.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_managed.h> +#include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_encoder.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_framebuffer.h> +#include <drm/drm_gem.h> +#include <drm/drm_gem_framebuffer_helper.h> +#include <drm/drm_simple_kms_helper.h> +#include <drm/drm_probe_helper.h> +#include <drm/drm_modeset_helper_vtables.h> +#include <drm/drm_vblank.h> +#include <drm/drm_of.h> + +#include "rp1_dpi.h" + +/* + * Default bus format, where not specified by a connector/bridge + * and not overridden by the OF property "default_bus_fmt". + * This value is for compatibility with vc4 and VGA666-style boards, + * even though RP1 hardware cannot achieve the full 18-bit depth + * with that pinout (MEDIA_BUS_FMT_RGB666_1X24_CPADHI is preferred). + */ +static unsigned int default_bus_fmt = MEDIA_BUS_FMT_RGB666_1X18; +module_param(default_bus_fmt, uint, 0644); + +/* -------------------------------------------------------------- */ + +static void rp1dpi_pipe_update(struct drm_simple_display_pipe *pipe, + struct drm_plane_state *old_state) +{ + struct drm_pending_vblank_event *event; + unsigned long flags; + struct drm_framebuffer *fb = pipe->plane.state->fb; + struct rp1_dpi *dpi = pipe->crtc.dev->dev_private; + struct drm_gem_object *gem = fb ? drm_gem_fb_get_obj(fb, 0) : NULL; + struct drm_gem_dma_object *dma_obj = gem ? to_drm_gem_dma_obj(gem) : NULL; + bool can_update = fb && dma_obj && dpi && dpi->pipe_enabled; + + /* (Re-)start DPI-DMA where required; and update FB address */ + if (can_update) { + if (!dpi->dpi_running || fb->format->format != dpi->cur_fmt) { + if (dpi->dpi_running && + fb->format->format != dpi->cur_fmt) { + rp1dpi_hw_stop(dpi); + dpi->dpi_running = false; + } + if (!dpi->dpi_running) { + rp1dpi_hw_setup(dpi, + fb->format->format, + dpi->bus_fmt, + dpi->de_inv, + &pipe->crtc.state->mode); + dpi->dpi_running = true; + } + dpi->cur_fmt = fb->format->format; + drm_crtc_vblank_on(&pipe->crtc); + } + rp1dpi_hw_update(dpi, dma_obj->dma_addr, fb->offsets[0], fb->pitches[0]); + } + + /* Arm VBLANK event (or call it immediately in some error cases) */ + spin_lock_irqsave(&pipe->crtc.dev->event_lock, flags); + event = pipe->crtc.state->event; + if (event) { + pipe->crtc.state->event = NULL; + if (can_update && drm_crtc_vblank_get(&pipe->crtc) == 0) + drm_crtc_arm_vblank_event(&pipe->crtc, event); + else + drm_crtc_send_vblank_event(&pipe->crtc, event); + } + spin_unlock_irqrestore(&pipe->crtc.dev->event_lock, flags); +} + +static void rp1dpi_pipe_enable(struct drm_simple_display_pipe *pipe, + struct drm_crtc_state *crtc_state, + struct drm_plane_state *plane_state) +{ + static const unsigned int M = 1000000; + struct rp1_dpi *dpi = pipe->crtc.dev->dev_private; + struct drm_connector *conn; + struct drm_connector_list_iter conn_iter; + unsigned int fpix, fdiv, fvco; + int ret; + + /* Look up the connector attached to DPI so we can get the + * bus_format. Ideally the bridge would tell us the + * bus_format we want, but it doesn't yet, so assume that it's + * uniform throughout the bridge chain. + */ + dev_info(&dpi->pdev->dev, __func__); + drm_connector_list_iter_begin(pipe->encoder.dev, &conn_iter); + drm_for_each_connector_iter(conn, &conn_iter) { + if (conn->encoder == &pipe->encoder) { + dpi->de_inv = !!(conn->display_info.bus_flags & + DRM_BUS_FLAG_DE_LOW); + dpi->clk_inv = !!(conn->display_info.bus_flags & + DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); + if (conn->display_info.num_bus_formats) + dpi->bus_fmt = conn->display_info.bus_formats[0]; + break; + } + } + drm_connector_list_iter_end(&conn_iter); + + /* Set DPI clock to desired frequency. Currently (experimentally) + * we take control of the VideoPLL, to ensure we can generate it + * accurately. NB: this prevents concurrent use of DPI and VEC! + * Magic numbers ensure the parent clock is within [100MHz, 200MHz] + * with VCO in [1GHz, 1.33GHz]. The initial divide is by 6, 8 or 10. + */ + fpix = 1000 * pipe->crtc.state->mode.clock; + fpix = clamp(fpix, 1 * M, 200 * M); + fdiv = fpix; + while (fdiv < 100 * M) + fdiv *= 2; + fvco = fdiv * 2 * DIV_ROUND_UP(500 * M, fdiv); + ret = clk_set_rate(dpi->clocks[RP1DPI_CLK_PLLCORE], fvco); + if (ret) + dev_err(&dpi->pdev->dev, "Failed to set PLL VCO to %u (%d)", fvco, ret); + ret = clk_set_rate(dpi->clocks[RP1DPI_CLK_PLLDIV], fdiv); + if (ret) + dev_err(&dpi->pdev->dev, "Failed to set PLL output to %u (%d)", fdiv, ret); + ret = clk_set_rate(dpi->clocks[RP1DPI_CLK_DPI], fpix); + if (ret) + dev_err(&dpi->pdev->dev, "Failed to set DPI clock to %u (%d)", fpix, ret); + + rp1dpi_vidout_setup(dpi, dpi->clk_inv); + clk_prepare_enable(dpi->clocks[RP1DPI_CLK_PLLCORE]); + clk_prepare_enable(dpi->clocks[RP1DPI_CLK_PLLDIV]); + pinctrl_pm_select_default_state(&dpi->pdev->dev); + clk_prepare_enable(dpi->clocks[RP1DPI_CLK_DPI]); + dev_info(&dpi->pdev->dev, "Want %u /%u %u /%u %u; got VCO=%lu DIV=%lu DPI=%lu", + fvco, fvco / fdiv, fdiv, fdiv / fpix, fpix, + clk_get_rate(dpi->clocks[RP1DPI_CLK_PLLCORE]), + clk_get_rate(dpi->clocks[RP1DPI_CLK_PLLDIV]), + clk_get_rate(dpi->clocks[RP1DPI_CLK_DPI])); + + /* Start DPI-DMA. pipe already has the new crtc and plane state. */ + dpi->pipe_enabled = true; + dpi->cur_fmt = 0xdeadbeef; + rp1dpi_pipe_update(pipe, 0); +} + +static void rp1dpi_pipe_disable(struct drm_simple_display_pipe *pipe) +{ + struct rp1_dpi *dpi = pipe->crtc.dev->dev_private; + + dev_info(&dpi->pdev->dev, __func__); + drm_crtc_vblank_off(&pipe->crtc); + if (dpi->dpi_running) { + rp1dpi_hw_stop(dpi); + dpi->dpi_running = false; + } + clk_disable_unprepare(dpi->clocks[RP1DPI_CLK_DPI]); + pinctrl_pm_select_sleep_state(&dpi->pdev->dev); + clk_disable_unprepare(dpi->clocks[RP1DPI_CLK_PLLDIV]); + clk_disable_unprepare(dpi->clocks[RP1DPI_CLK_PLLCORE]); + dpi->pipe_enabled = false; +} + +static int rp1dpi_pipe_enable_vblank(struct drm_simple_display_pipe *pipe) +{ + struct rp1_dpi *dpi = pipe->crtc.dev->dev_private; + + if (dpi) + rp1dpi_hw_vblank_ctrl(dpi, 1); + + return 0; +} + +static void rp1dpi_pipe_disable_vblank(struct drm_simple_display_pipe *pipe) +{ + struct rp1_dpi *dpi = pipe->crtc.dev->dev_private; + + if (dpi) + rp1dpi_hw_vblank_ctrl(dpi, 0); +} + +static const struct drm_simple_display_pipe_funcs rp1dpi_pipe_funcs = { + .enable = rp1dpi_pipe_enable, + .update = rp1dpi_pipe_update, + .disable = rp1dpi_pipe_disable, + .prepare_fb = drm_gem_simple_display_pipe_prepare_fb, + .enable_vblank = rp1dpi_pipe_enable_vblank, + .disable_vblank = rp1dpi_pipe_disable_vblank, +}; + +static const struct drm_mode_config_funcs rp1dpi_mode_funcs = { + .fb_create = drm_gem_fb_create, + .atomic_check = drm_atomic_helper_check, + .atomic_commit = drm_atomic_helper_commit, +}; + +static void rp1dpi_stopall(struct drm_device *drm) +{ + if (drm->dev_private) { + struct rp1_dpi *dpi = drm->dev_private; + + if (dpi->dpi_running || rp1dpi_hw_busy(dpi)) { + rp1dpi_hw_stop(dpi); + clk_disable_unprepare(dpi->clocks[RP1DPI_CLK_DPI]); + dpi->dpi_running = false; + } + rp1dpi_vidout_poweroff(dpi); + pinctrl_pm_select_sleep_state(&dpi->pdev->dev); + } +} + +DEFINE_DRM_GEM_DMA_FOPS(rp1dpi_fops); + +static struct drm_driver rp1dpi_driver = { + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, + .fops = &rp1dpi_fops, + .name = "drm-rp1-dpi", + .desc = "drm-rp1-dpi", + .date = "0", + .major = 1, + .minor = 0, + DRM_GEM_DMA_DRIVER_OPS, + .release = rp1dpi_stopall, +}; + +static const u32 rp1dpi_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565 +}; + +static int rp1dpi_platform_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct drm_device *drm; + struct rp1_dpi *dpi; + struct drm_bridge *bridge = NULL; + struct drm_panel *panel; + int i, ret; + + dev_info(dev, __func__); + ret = drm_of_find_panel_or_bridge(pdev->dev.of_node, 0, 0, + &panel, &bridge); + if (ret) { + dev_info(dev, "%s: bridge not found\n", __func__); + return -EPROBE_DEFER; + } + if (panel) { + bridge = devm_drm_panel_bridge_add(dev, panel); + if (IS_ERR(bridge)) + return PTR_ERR(bridge); + } + + drm = drm_dev_alloc(&rp1dpi_driver, dev); + if (IS_ERR(drm)) { + dev_info(dev, "%s %d", __func__, (int)__LINE__); + ret = PTR_ERR(drm); + return ret; + } + dpi = drmm_kzalloc(drm, sizeof(*dpi), GFP_KERNEL); + if (!dpi) { + dev_info(dev, "%s %d", __func__, (int)__LINE__); + drm_dev_put(drm); + return -ENOMEM; + } + + init_completion(&dpi->finished); + dpi->drm = drm; + dpi->pdev = pdev; + drm->dev_private = dpi; + platform_set_drvdata(pdev, drm); + + dpi->bus_fmt = default_bus_fmt; + ret = of_property_read_u32(dev->of_node, "default_bus_fmt", &dpi->bus_fmt); + + for (i = 0; i < RP1DPI_NUM_HW_BLOCKS; i++) { + dpi->hw_base[i] = + devm_ioremap_resource(dev, + platform_get_resource(dpi->pdev, IORESOURCE_MEM, i)); + if (IS_ERR(dpi->hw_base[i])) { + ret = PTR_ERR(dpi->hw_base[i]); + dev_err(dev, "Error memory mapping regs[%d]\n", i); + goto err_free_drm; + } + } + ret = platform_get_irq(dpi->pdev, 0); + if (ret > 0) + ret = devm_request_irq(dev, ret, rp1dpi_hw_isr, + IRQF_SHARED, "rp1-dpi", dpi); + if (ret) { + dev_err(dev, "Unable to request interrupt\n"); + ret = -EINVAL; + goto err_free_drm; + } + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + + for (i = 0; i < RP1DPI_NUM_CLOCKS; i++) { + static const char * const myclocknames[RP1DPI_NUM_CLOCKS] = { + "dpiclk", "plldiv", "pllcore" + }; + dpi->clocks[i] = devm_clk_get(dev, myclocknames[i]); + if (IS_ERR(dpi->clocks[i])) { + ret = PTR_ERR(dpi->clocks[i]); + goto err_free_drm; + } + } + + ret = drmm_mode_config_init(drm); + if (ret) + goto err_free_drm; + + drm->mode_config.max_width = 4096; + drm->mode_config.max_height = 4096; + drm->mode_config.fb_base = 0; + drm->mode_config.preferred_depth = 32; + drm->mode_config.prefer_shadow = 0; + drm->mode_config.prefer_shadow_fbdev = 1; + drm->mode_config.quirk_addfb_prefer_host_byte_order = true; + drm->mode_config.funcs = &rp1dpi_mode_funcs; + drm_vblank_init(drm, 1); + + ret = drm_simple_display_pipe_init(drm, + &dpi->pipe, + &rp1dpi_pipe_funcs, + rp1dpi_formats, + ARRAY_SIZE(rp1dpi_formats), + NULL, NULL); + if (!ret) + ret = drm_simple_display_pipe_attach_bridge(&dpi->pipe, bridge); + if (ret) + goto err_free_drm; + + drm_mode_config_reset(drm); + + ret = drm_dev_register(drm, 0); + if (ret) + goto err_free_drm; + + drm_fbdev_generic_setup(drm, 32); + + dev_info(dev, "%s success\n", __func__); + return ret; + +err_free_drm: + dev_err(dev, "%s fail %d\n", __func__, ret); + drm_dev_put(drm); + return ret; +} + +static int rp1dpi_platform_remove(struct platform_device *pdev) +{ + struct drm_device *drm = platform_get_drvdata(pdev); + + rp1dpi_stopall(drm); + drm_dev_unregister(drm); + drm_atomic_helper_shutdown(drm); + drm_dev_put(drm); + + return 0; +} + +static void rp1dpi_platform_shutdown(struct platform_device *pdev) +{ + struct drm_device *drm = platform_get_drvdata(pdev); + + rp1dpi_stopall(drm); +} + +static const struct of_device_id rp1dpi_of_match[] = { + { + .compatible = "raspberrypi,rp1dpi", + }, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, rp1dpi_of_match); + +static struct platform_driver rp1dpi_platform_driver = { + .probe = rp1dpi_platform_probe, + .remove = rp1dpi_platform_remove, + .shutdown = rp1dpi_platform_shutdown, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = rp1dpi_of_match, + }, +}; + +module_platform_driver(rp1dpi_platform_driver); + +MODULE_AUTHOR("Nick Hollinghurst"); +MODULE_DESCRIPTION("DRM driver for DPI output on Raspberry Pi RP1"); +MODULE_LICENSE("GPL"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_cfg.c linux/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_cfg.c --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_cfg.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_cfg.c 2023-12-13 11:50:59.407986721 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DRM Driver for DPI output on Raspberry Pi RP1 + * + * Copyright (c) 2023 Raspberry Pi Limited. + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/mm.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/printk.h> +#include <linux/rp1_platform.h> + +#include "rp1_dpi.h" + +// ============================================================================= +// Register : VIDEO_OUT_CFG_SEL +// JTAG access : synchronous +// Description : Selects source: VEC or DPI +#define VIDEO_OUT_CFG_SEL_OFFSET 0x00000000 +#define VIDEO_OUT_CFG_SEL_BITS 0x00000013 +#define VIDEO_OUT_CFG_SEL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_SEL_PCLK_INV +// Description : Select dpi_pclk output port polarity inversion. +#define VIDEO_OUT_CFG_SEL_PCLK_INV_RESET 0x0 +#define VIDEO_OUT_CFG_SEL_PCLK_INV_BITS 0x00000010 +#define VIDEO_OUT_CFG_SEL_PCLK_INV_MSB 4 +#define VIDEO_OUT_CFG_SEL_PCLK_INV_LSB 4 +#define VIDEO_OUT_CFG_SEL_PCLK_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_SEL_PAD_MUX +// Description : VEC 1 DPI 0 +#define VIDEO_OUT_CFG_SEL_PAD_MUX_RESET 0x0 +#define VIDEO_OUT_CFG_SEL_PAD_MUX_BITS 0x00000002 +#define VIDEO_OUT_CFG_SEL_PAD_MUX_MSB 1 +#define VIDEO_OUT_CFG_SEL_PAD_MUX_LSB 1 +#define VIDEO_OUT_CFG_SEL_PAD_MUX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_SEL_VDAC_MUX +// Description : VEC 1 DPI 0 +#define VIDEO_OUT_CFG_SEL_VDAC_MUX_RESET 0x0 +#define VIDEO_OUT_CFG_SEL_VDAC_MUX_BITS 0x00000001 +#define VIDEO_OUT_CFG_SEL_VDAC_MUX_MSB 0 +#define VIDEO_OUT_CFG_SEL_VDAC_MUX_LSB 0 +#define VIDEO_OUT_CFG_SEL_VDAC_MUX_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_VDAC_CFG +// JTAG access : synchronous +// Description : Configure SNPS VDAC +#define VIDEO_OUT_CFG_VDAC_CFG_OFFSET 0x00000004 +#define VIDEO_OUT_CFG_VDAC_CFG_BITS 0x1fffffff +#define VIDEO_OUT_CFG_VDAC_CFG_RESET 0x0003ffff +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_ENCTR +// Description : None +#define VIDEO_OUT_CFG_VDAC_CFG_ENCTR_RESET 0x0 +#define VIDEO_OUT_CFG_VDAC_CFG_ENCTR_BITS 0x1c000000 +#define VIDEO_OUT_CFG_VDAC_CFG_ENCTR_MSB 28 +#define VIDEO_OUT_CFG_VDAC_CFG_ENCTR_LSB 26 +#define VIDEO_OUT_CFG_VDAC_CFG_ENCTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_ENSC +// Description : None +#define VIDEO_OUT_CFG_VDAC_CFG_ENSC_RESET 0x0 +#define VIDEO_OUT_CFG_VDAC_CFG_ENSC_BITS 0x03800000 +#define VIDEO_OUT_CFG_VDAC_CFG_ENSC_MSB 25 +#define VIDEO_OUT_CFG_VDAC_CFG_ENSC_LSB 23 +#define VIDEO_OUT_CFG_VDAC_CFG_ENSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_ENDAC +// Description : None +#define VIDEO_OUT_CFG_VDAC_CFG_ENDAC_RESET 0x0 +#define VIDEO_OUT_CFG_VDAC_CFG_ENDAC_BITS 0x00700000 +#define VIDEO_OUT_CFG_VDAC_CFG_ENDAC_MSB 22 +#define VIDEO_OUT_CFG_VDAC_CFG_ENDAC_LSB 20 +#define VIDEO_OUT_CFG_VDAC_CFG_ENDAC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_ENVBG +// Description : None +#define VIDEO_OUT_CFG_VDAC_CFG_ENVBG_RESET 0x0 +#define VIDEO_OUT_CFG_VDAC_CFG_ENVBG_BITS 0x00080000 +#define VIDEO_OUT_CFG_VDAC_CFG_ENVBG_MSB 19 +#define VIDEO_OUT_CFG_VDAC_CFG_ENVBG_LSB 19 +#define VIDEO_OUT_CFG_VDAC_CFG_ENVBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF +// Description : None +#define VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF_RESET 0x0 +#define VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF_BITS 0x00040000 +#define VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF_MSB 18 +#define VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF_LSB 18 +#define VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_DAC2GC +// Description : dac2 gain control +#define VIDEO_OUT_CFG_VDAC_CFG_DAC2GC_RESET 0x3f +#define VIDEO_OUT_CFG_VDAC_CFG_DAC2GC_BITS 0x0003f000 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC2GC_MSB 17 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC2GC_LSB 12 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC2GC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_DAC1GC +// Description : dac1 gain control +#define VIDEO_OUT_CFG_VDAC_CFG_DAC1GC_RESET 0x3f +#define VIDEO_OUT_CFG_VDAC_CFG_DAC1GC_BITS 0x00000fc0 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC1GC_MSB 11 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC1GC_LSB 6 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC1GC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_DAC0GC +// Description : dac0 gain control +#define VIDEO_OUT_CFG_VDAC_CFG_DAC0GC_RESET 0x3f +#define VIDEO_OUT_CFG_VDAC_CFG_DAC0GC_BITS 0x0000003f +#define VIDEO_OUT_CFG_VDAC_CFG_DAC0GC_MSB 5 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC0GC_LSB 0 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC0GC_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_VDAC_STATUS +// JTAG access : synchronous +// Description : Read VDAC status +#define VIDEO_OUT_CFG_VDAC_STATUS_OFFSET 0x00000008 +#define VIDEO_OUT_CFG_VDAC_STATUS_BITS 0x00000017 +#define VIDEO_OUT_CFG_VDAC_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3 +// Description : None +#define VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3_RESET 0x0 +#define VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3_BITS 0x00000010 +#define VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3_MSB 4 +#define VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3_LSB 4 +#define VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT +// Description : None +#define VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT_RESET "-" +#define VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT_BITS 0x00000007 +#define VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT_MSB 2 +#define VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT_LSB 0 +#define VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT_ACCESS "RO" +// ============================================================================= +// Register : VIDEO_OUT_CFG_MEM_PD +// JTAG access : synchronous +// Description : Control memory power down +#define VIDEO_OUT_CFG_MEM_PD_OFFSET 0x0000000c +#define VIDEO_OUT_CFG_MEM_PD_BITS 0x00000003 +#define VIDEO_OUT_CFG_MEM_PD_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_MEM_PD_VEC +// Description : None +#define VIDEO_OUT_CFG_MEM_PD_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_MEM_PD_VEC_BITS 0x00000002 +#define VIDEO_OUT_CFG_MEM_PD_VEC_MSB 1 +#define VIDEO_OUT_CFG_MEM_PD_VEC_LSB 1 +#define VIDEO_OUT_CFG_MEM_PD_VEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_MEM_PD_DPI +// Description : None +#define VIDEO_OUT_CFG_MEM_PD_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_MEM_PD_DPI_BITS 0x00000001 +#define VIDEO_OUT_CFG_MEM_PD_DPI_MSB 0 +#define VIDEO_OUT_CFG_MEM_PD_DPI_LSB 0 +#define VIDEO_OUT_CFG_MEM_PD_DPI_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_TEST_OVERRIDE +// JTAG access : synchronous +// Description : None +#define VIDEO_OUT_CFG_TEST_OVERRIDE_OFFSET 0x00000010 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_BITS 0xffffffff +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_TEST_OVERRIDE_PAD +// Description : None +#define VIDEO_OUT_CFG_TEST_OVERRIDE_PAD_RESET 0x0 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_PAD_BITS 0x80000000 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_PAD_MSB 31 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_PAD_LSB 31 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_PAD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC +// Description : None +#define VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_RESET 0x0 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_BITS 0x40000000 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_MSB 30 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_LSB 30 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL +// Description : None +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL_RESET 0x00000000 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL_BITS 0x3fffffff +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL_MSB 29 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL_LSB 0 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_INTR +// JTAG access : synchronous +// Description : Raw Interrupts +#define VIDEO_OUT_CFG_INTR_OFFSET 0x00000014 +#define VIDEO_OUT_CFG_INTR_BITS 0x00000003 +#define VIDEO_OUT_CFG_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTR_DPI +// Description : None +#define VIDEO_OUT_CFG_INTR_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_INTR_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_INTR_DPI_MSB 1 +#define VIDEO_OUT_CFG_INTR_DPI_LSB 1 +#define VIDEO_OUT_CFG_INTR_DPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTR_VEC +// Description : None +#define VIDEO_OUT_CFG_INTR_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_INTR_VEC_BITS 0x00000001 +#define VIDEO_OUT_CFG_INTR_VEC_MSB 0 +#define VIDEO_OUT_CFG_INTR_VEC_LSB 0 +#define VIDEO_OUT_CFG_INTR_VEC_ACCESS "RO" +// ============================================================================= +// Register : VIDEO_OUT_CFG_INTE +// JTAG access : synchronous +// Description : Interrupt Enable +#define VIDEO_OUT_CFG_INTE_OFFSET 0x00000018 +#define VIDEO_OUT_CFG_INTE_BITS 0x00000003 +#define VIDEO_OUT_CFG_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTE_DPI +// Description : None +#define VIDEO_OUT_CFG_INTE_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_INTE_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_INTE_DPI_MSB 1 +#define VIDEO_OUT_CFG_INTE_DPI_LSB 1 +#define VIDEO_OUT_CFG_INTE_DPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTE_VEC +// Description : None +#define VIDEO_OUT_CFG_INTE_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_INTE_VEC_BITS 0x00000001 +#define VIDEO_OUT_CFG_INTE_VEC_MSB 0 +#define VIDEO_OUT_CFG_INTE_VEC_LSB 0 +#define VIDEO_OUT_CFG_INTE_VEC_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_INTF +// JTAG access : synchronous +// Description : Interrupt Force +#define VIDEO_OUT_CFG_INTF_OFFSET 0x0000001c +#define VIDEO_OUT_CFG_INTF_BITS 0x00000003 +#define VIDEO_OUT_CFG_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTF_DPI +// Description : None +#define VIDEO_OUT_CFG_INTF_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_INTF_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_INTF_DPI_MSB 1 +#define VIDEO_OUT_CFG_INTF_DPI_LSB 1 +#define VIDEO_OUT_CFG_INTF_DPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTF_VEC +// Description : None +#define VIDEO_OUT_CFG_INTF_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_INTF_VEC_BITS 0x00000001 +#define VIDEO_OUT_CFG_INTF_VEC_MSB 0 +#define VIDEO_OUT_CFG_INTF_VEC_LSB 0 +#define VIDEO_OUT_CFG_INTF_VEC_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_INTS +// JTAG access : synchronous +// Description : Interrupt status after masking & forcing +#define VIDEO_OUT_CFG_INTS_OFFSET 0x00000020 +#define VIDEO_OUT_CFG_INTS_BITS 0x00000003 +#define VIDEO_OUT_CFG_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTS_DPI +// Description : None +#define VIDEO_OUT_CFG_INTS_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_INTS_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_INTS_DPI_MSB 1 +#define VIDEO_OUT_CFG_INTS_DPI_LSB 1 +#define VIDEO_OUT_CFG_INTS_DPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTS_VEC +// Description : None +#define VIDEO_OUT_CFG_INTS_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_INTS_VEC_BITS 0x00000001 +#define VIDEO_OUT_CFG_INTS_VEC_MSB 0 +#define VIDEO_OUT_CFG_INTS_VEC_LSB 0 +#define VIDEO_OUT_CFG_INTS_VEC_ACCESS "RO" +// ============================================================================= +// Register : VIDEO_OUT_CFG_BLOCK_ID +// JTAG access : synchronous +// Description : Block Identifier +// Hexadecimal representation of "VOCF" +#define VIDEO_OUT_CFG_BLOCK_ID_OFFSET 0x00000024 +#define VIDEO_OUT_CFG_BLOCK_ID_BITS 0xffffffff +#define VIDEO_OUT_CFG_BLOCK_ID_RESET 0x564f4346 +#define VIDEO_OUT_CFG_BLOCK_ID_MSB 31 +#define VIDEO_OUT_CFG_BLOCK_ID_LSB 0 +#define VIDEO_OUT_CFG_BLOCK_ID_ACCESS "RO" +// ============================================================================= +// Register : VIDEO_OUT_CFG_INSTANCE_ID +// JTAG access : synchronous +// Description : Block Instance Identifier +#define VIDEO_OUT_CFG_INSTANCE_ID_OFFSET 0x00000028 +#define VIDEO_OUT_CFG_INSTANCE_ID_BITS 0x0000000f +#define VIDEO_OUT_CFG_INSTANCE_ID_RESET 0x00000000 +#define VIDEO_OUT_CFG_INSTANCE_ID_MSB 3 +#define VIDEO_OUT_CFG_INSTANCE_ID_LSB 0 +#define VIDEO_OUT_CFG_INSTANCE_ID_ACCESS "RO" +// ============================================================================= +// Register : VIDEO_OUT_CFG_RSTSEQ_AUTO +// JTAG access : synchronous +// Description : None +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_OFFSET 0x0000002c +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BITS 0x00000007 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_RESET 0x00000007 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC +// Description : 1 = reset is controlled by the sequencer +// 0 = reset is controlled by rstseq_ctrl +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC_RESET 0x1 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC_BITS 0x00000004 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC_MSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC_LSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI +// Description : 1 = reset is controlled by the sequencer +// 0 = reset is controlled by rstseq_ctrl +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI_RESET 0x1 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI_MSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI_LSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER +// Description : 1 = reset is controlled by the sequencer +// 0 = reset is controlled by rstseq_ctrl +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER_RESET 0x1 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER_BITS 0x00000001 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER_MSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER_LSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_RSTSEQ_PARALLEL +// JTAG access : synchronous +// Description : None +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_OFFSET 0x00000030 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BITS 0x00000007 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_RESET 0x00000006 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC +// Description : Is this reset parallel (i.e. not part of the sequence) +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC_RESET 0x1 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC_BITS 0x00000004 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC_MSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC_LSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI +// Description : Is this reset parallel (i.e. not part of the sequence) +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI_RESET 0x1 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI_MSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI_LSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER +// Description : Is this reset parallel (i.e. not part of the sequence) +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER_BITS 0x00000001 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER_MSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER_LSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER_ACCESS "RO" +// ============================================================================= +// Register : VIDEO_OUT_CFG_RSTSEQ_CTRL +// JTAG access : synchronous +// Description : None +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_OFFSET 0x00000034 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BITS 0x00000007 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC +// Description : 1 = keep the reset asserted +// 0 = keep the reset deasserted +// This is ignored if rstseq_auto=1 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC_BITS 0x00000004 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC_MSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC_LSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI +// Description : 1 = keep the reset asserted +// 0 = keep the reset deasserted +// This is ignored if rstseq_auto=1 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI_MSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI_LSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER +// Description : 1 = keep the reset asserted +// 0 = keep the reset deasserted +// This is ignored if rstseq_auto=1 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER_BITS 0x00000001 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER_MSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER_LSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_RSTSEQ_TRIG +// JTAG access : synchronous +// Description : None +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_OFFSET 0x00000038 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BITS 0x00000007 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC +// Description : Pulses the reset output +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC_BITS 0x00000004 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC_MSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC_LSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI +// Description : Pulses the reset output +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI_MSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI_LSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER +// Description : Pulses the reset output +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER_BITS 0x00000001 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER_MSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER_LSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER_ACCESS "SC" +// ============================================================================= +// Register : VIDEO_OUT_CFG_RSTSEQ_DONE +// JTAG access : synchronous +// Description : None +#define VIDEO_OUT_CFG_RSTSEQ_DONE_OFFSET 0x0000003c +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BITS 0x00000007 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_DONE_VEC +// Description : Indicates the current state of the reset +#define VIDEO_OUT_CFG_RSTSEQ_DONE_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_VEC_BITS 0x00000004 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_VEC_MSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_VEC_LSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_VEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_DONE_DPI +// Description : Indicates the current state of the reset +#define VIDEO_OUT_CFG_RSTSEQ_DONE_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_DPI_MSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_DPI_LSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_DPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER +// Description : Indicates the current state of the reset +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER_BITS 0x00000001 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER_MSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER_LSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER_ACCESS "RO" +// ============================================================================= + +#define CFG_WRITE(reg, val) writel((val), dpi->hw_base[RP1DPI_HW_BLOCK_CFG] + (reg ## _OFFSET)) +#define CFG_READ(reg) readl(dpi->hw_base[RP1DPI_HW_BLOCK_CFG] + (reg ## _OFFSET)) + +void rp1dpi_vidout_setup(struct rp1_dpi *dpi, bool drive_negedge) +{ + /* + * We assume DPI and VEC can't be used at the same time (due to + * clashing requirements for PLL_VIDEO, and potentially for VDAC). + * We therefore leave VEC memories powered down. + */ + CFG_WRITE(VIDEO_OUT_CFG_MEM_PD, VIDEO_OUT_CFG_MEM_PD_VEC_BITS); + CFG_WRITE(VIDEO_OUT_CFG_TEST_OVERRIDE, + VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_BITS); + + /* DPI->Pads; DPI->VDAC; optionally flip PCLK polarity */ + CFG_WRITE(VIDEO_OUT_CFG_SEL, + drive_negedge ? VIDEO_OUT_CFG_SEL_PCLK_INV_BITS : 0); + + /* configure VDAC for 3 channels, bandgap on, 710mV swing */ + CFG_WRITE(VIDEO_OUT_CFG_VDAC_CFG, 0); + + /* enable DPI interrupt */ + CFG_WRITE(VIDEO_OUT_CFG_INTE, VIDEO_OUT_CFG_INTE_DPI_BITS); +} + +void rp1dpi_vidout_poweroff(struct rp1_dpi *dpi) +{ + /* disable DPI interrupt */ + CFG_WRITE(VIDEO_OUT_CFG_INTE, 0); + + /* Ensure VDAC is turned off; power down DPI,VEC memories */ + CFG_WRITE(VIDEO_OUT_CFG_VDAC_CFG, 0); + CFG_WRITE(VIDEO_OUT_CFG_MEM_PD, VIDEO_OUT_CFG_MEM_PD_BITS); +} diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.h linux/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.h --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.h 2023-12-13 11:50:59.407986721 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * DRM Driver for DSI output on Raspberry Pi RP1 + * + * Copyright (c) 2023 Raspberry Pi Limited. + */ + +#include <linux/types.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <drm/drm_device.h> +#include <drm/drm_simple_kms_helper.h> + +#define MODULE_NAME "drm-rp1-dpi" +#define DRIVER_NAME "drm-rp1-dpi" + +/* ---------------------------------------------------------------------- */ + +#define RP1DPI_HW_BLOCK_DPI 0 +#define RP1DPI_HW_BLOCK_CFG 1 +#define RP1DPI_NUM_HW_BLOCKS 2 + +#define RP1DPI_CLK_DPI 0 +#define RP1DPI_CLK_PLLDIV 1 +#define RP1DPI_CLK_PLLCORE 2 +#define RP1DPI_NUM_CLOCKS 3 + +/* ---------------------------------------------------------------------- */ + +struct rp1_dpi { + /* DRM and platform device pointers */ + struct drm_device *drm; + struct platform_device *pdev; + + /* Framework and helper objects */ + struct drm_simple_display_pipe pipe; + struct drm_connector connector; + + /* Clocks: Video PLL, its primary divider, and DPI clock. */ + struct clk *clocks[RP1DPI_NUM_CLOCKS]; + + /* Block (DPI, VOCFG) base addresses, and current state */ + void __iomem *hw_base[RP1DPI_NUM_HW_BLOCKS]; + u32 cur_fmt; + u32 bus_fmt; + bool de_inv, clk_inv; + bool dpi_running, pipe_enabled; + struct completion finished; +}; + +/* ---------------------------------------------------------------------- */ +/* Functions to control the DPI/DMA block */ + +void rp1dpi_hw_setup(struct rp1_dpi *dpi, + u32 in_format, + u32 bus_format, + bool de_inv, + struct drm_display_mode const *mode); +void rp1dpi_hw_update(struct rp1_dpi *dpi, dma_addr_t addr, u32 offset, u32 stride); +void rp1dpi_hw_stop(struct rp1_dpi *dpi); +int rp1dpi_hw_busy(struct rp1_dpi *dpi); +irqreturn_t rp1dpi_hw_isr(int irq, void *dev); +void rp1dpi_hw_vblank_ctrl(struct rp1_dpi *dpi, int enable); + +/* ---------------------------------------------------------------------- */ +/* Functions to control the VIDEO OUT CFG block and check RP1 platform */ + +void rp1dpi_vidout_setup(struct rp1_dpi *dpi, bool drive_negedge); +void rp1dpi_vidout_poweroff(struct rp1_dpi *dpi); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_hw.c linux/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_hw.c --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_hw.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_hw.c 2023-12-13 11:50:59.408986724 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DRM Driver for DPI output on Raspberry Pi RP1 + * + * Copyright (c) 2023 Raspberry Pi Limited. + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/mm.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/media-bus-format.h> +#include <linux/platform_device.h> +#include <linux/printk.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_print.h> +#include <drm/drm_vblank.h> + +#include "rp1_dpi.h" + +// --- DPI DMA REGISTERS --- + +// Control +#define DPI_DMA_CONTROL 0x0 +#define DPI_DMA_CONTROL_ARM_SHIFT 0 +#define DPI_DMA_CONTROL_ARM_MASK BIT(DPI_DMA_CONTROL_ARM_SHIFT) +#define DPI_DMA_CONTROL_ALIGN16_SHIFT 2 +#define DPI_DMA_CONTROL_ALIGN16_MASK BIT(DPI_DMA_CONTROL_ALIGN16_SHIFT) +#define DPI_DMA_CONTROL_AUTO_REPEAT_SHIFT 1 +#define DPI_DMA_CONTROL_AUTO_REPEAT_MASK BIT(DPI_DMA_CONTROL_AUTO_REPEAT_SHIFT) +#define DPI_DMA_CONTROL_HIGH_WATER_SHIFT 3 +#define DPI_DMA_CONTROL_HIGH_WATER_MASK (0x1FF << DPI_DMA_CONTROL_HIGH_WATER_SHIFT) +#define DPI_DMA_CONTROL_DEN_POL_SHIFT 12 +#define DPI_DMA_CONTROL_DEN_POL_MASK BIT(DPI_DMA_CONTROL_DEN_POL_SHIFT) +#define DPI_DMA_CONTROL_HSYNC_POL_SHIFT 13 +#define DPI_DMA_CONTROL_HSYNC_POL_MASK BIT(DPI_DMA_CONTROL_HSYNC_POL_SHIFT) +#define DPI_DMA_CONTROL_VSYNC_POL_SHIFT 14 +#define DPI_DMA_CONTROL_VSYNC_POL_MASK BIT(DPI_DMA_CONTROL_VSYNC_POL_SHIFT) +#define DPI_DMA_CONTROL_COLORM_SHIFT 15 +#define DPI_DMA_CONTROL_COLORM_MASK BIT(DPI_DMA_CONTROL_COLORM_SHIFT) +#define DPI_DMA_CONTROL_SHUTDN_SHIFT 16 +#define DPI_DMA_CONTROL_SHUTDN_MASK BIT(DPI_DMA_CONTROL_SHUTDN_SHIFT) +#define DPI_DMA_CONTROL_HBP_EN_SHIFT 17 +#define DPI_DMA_CONTROL_HBP_EN_MASK BIT(DPI_DMA_CONTROL_HBP_EN_SHIFT) +#define DPI_DMA_CONTROL_HFP_EN_SHIFT 18 +#define DPI_DMA_CONTROL_HFP_EN_MASK BIT(DPI_DMA_CONTROL_HFP_EN_SHIFT) +#define DPI_DMA_CONTROL_VBP_EN_SHIFT 19 +#define DPI_DMA_CONTROL_VBP_EN_MASK BIT(DPI_DMA_CONTROL_VBP_EN_SHIFT) +#define DPI_DMA_CONTROL_VFP_EN_SHIFT 20 +#define DPI_DMA_CONTROL_VFP_EN_MASK BIT(DPI_DMA_CONTROL_VFP_EN_SHIFT) +#define DPI_DMA_CONTROL_HSYNC_EN_SHIFT 21 +#define DPI_DMA_CONTROL_HSYNC_EN_MASK BIT(DPI_DMA_CONTROL_HSYNC_EN_SHIFT) +#define DPI_DMA_CONTROL_VSYNC_EN_SHIFT 22 +#define DPI_DMA_CONTROL_VSYNC_EN_MASK BIT(DPI_DMA_CONTROL_VSYNC_EN_SHIFT) +#define DPI_DMA_CONTROL_FORCE_IMMED_SHIFT 23 +#define DPI_DMA_CONTROL_FORCE_IMMED_MASK BIT(DPI_DMA_CONTROL_FORCE_IMMED_SHIFT) +#define DPI_DMA_CONTROL_FORCE_DRAIN_SHIFT 24 +#define DPI_DMA_CONTROL_FORCE_DRAIN_MASK BIT(DPI_DMA_CONTROL_FORCE_DRAIN_SHIFT) +#define DPI_DMA_CONTROL_FORCE_EMPTY_SHIFT 25 +#define DPI_DMA_CONTROL_FORCE_EMPTY_MASK BIT(DPI_DMA_CONTROL_FORCE_EMPTY_SHIFT) + +// IRQ_ENABLES +#define DPI_DMA_IRQ_EN 0x04 +#define DPI_DMA_IRQ_EN_DMA_READY_SHIFT 0 +#define DPI_DMA_IRQ_EN_DMA_READY_MASK BIT(DPI_DMA_IRQ_EN_DMA_READY_SHIFT) +#define DPI_DMA_IRQ_EN_UNDERFLOW_SHIFT 1 +#define DPI_DMA_IRQ_EN_UNDERFLOW_MASK BIT(DPI_DMA_IRQ_EN_UNDERFLOW_SHIFT) +#define DPI_DMA_IRQ_EN_FRAME_START_SHIFT 2 +#define DPI_DMA_IRQ_EN_FRAME_START_MASK BIT(DPI_DMA_IRQ_EN_FRAME_START_SHIFT) +#define DPI_DMA_IRQ_EN_AFIFO_EMPTY_SHIFT 3 +#define DPI_DMA_IRQ_EN_AFIFO_EMPTY_MASK BIT(DPI_DMA_IRQ_EN_AFIFO_EMPTY_SHIFT) +#define DPI_DMA_IRQ_EN_TE_SHIFT 4 +#define DPI_DMA_IRQ_EN_TE_MASK BIT(DPI_DMA_IRQ_EN_TE_SHIFT) +#define DPI_DMA_IRQ_EN_ERROR_SHIFT 5 +#define DPI_DMA_IRQ_EN_ERROR_MASK BIT(DPI_DMA_IRQ_EN_ERROR_SHIFT) +#define DPI_DMA_IRQ_EN_MATCH_SHIFT 6 +#define DPI_DMA_IRQ_EN_MATCH_MASK BIT(DPI_DMA_IRQ_EN_MATCH_SHIFT) +#define DPI_DMA_IRQ_EN_MATCH_LINE_SHIFT 16 +#define DPI_DMA_IRQ_EN_MATCH_LINE_MASK (0xFFF << DPI_DMA_IRQ_EN_MATCH_LINE_SHIFT) + +// IRQ_FLAGS +#define DPI_DMA_IRQ_FLAGS 0x08 +#define DPI_DMA_IRQ_FLAGS_DMA_READY_SHIFT 0 +#define DPI_DMA_IRQ_FLAGS_DMA_READY_MASK BIT(DPI_DMA_IRQ_FLAGS_DMA_READY_SHIFT) +#define DPI_DMA_IRQ_FLAGS_UNDERFLOW_SHIFT 1 +#define DPI_DMA_IRQ_FLAGS_UNDERFLOW_MASK BIT(DPI_DMA_IRQ_FLAGS_UNDERFLOW_SHIFT) +#define DPI_DMA_IRQ_FLAGS_FRAME_START_SHIFT 2 +#define DPI_DMA_IRQ_FLAGS_FRAME_START_MASK BIT(DPI_DMA_IRQ_FLAGS_FRAME_START_SHIFT) +#define DPI_DMA_IRQ_FLAGS_AFIFO_EMPTY_SHIFT 3 +#define DPI_DMA_IRQ_FLAGS_AFIFO_EMPTY_MASK BIT(DPI_DMA_IRQ_FLAGS_AFIFO_EMPTY_SHIFT) +#define DPI_DMA_IRQ_FLAGS_TE_SHIFT 4 +#define DPI_DMA_IRQ_FLAGS_TE_MASK BIT(DPI_DMA_IRQ_FLAGS_TE_SHIFT) +#define DPI_DMA_IRQ_FLAGS_ERROR_SHIFT 5 +#define DPI_DMA_IRQ_FLAGS_ERROR_MASK BIT(DPI_DMA_IRQ_FLAGS_ERROR_SHIFT) +#define DPI_DMA_IRQ_FLAGS_MATCH_SHIFT 6 +#define DPI_DMA_IRQ_FLAGS_MATCH_MASK BIT(DPI_DMA_IRQ_FLAGS_MATCH_SHIFT) + +// QOS +#define DPI_DMA_QOS 0xC +#define DPI_DMA_QOS_DQOS_SHIFT 0 +#define DPI_DMA_QOS_DQOS_MASK (0xF << DPI_DMA_QOS_DQOS_SHIFT) +#define DPI_DMA_QOS_ULEV_SHIFT 4 +#define DPI_DMA_QOS_ULEV_MASK (0xF << DPI_DMA_QOS_ULEV_SHIFT) +#define DPI_DMA_QOS_UQOS_SHIFT 8 +#define DPI_DMA_QOS_UQOS_MASK (0xF << DPI_DMA_QOS_UQOS_SHIFT) +#define DPI_DMA_QOS_LLEV_SHIFT 12 +#define DPI_DMA_QOS_LLEV_MASK (0xF << DPI_DMA_QOS_LLEV_SHIFT) +#define DPI_DMA_QOS_LQOS_SHIFT 16 +#define DPI_DMA_QOS_LQOS_MASK (0xF << DPI_DMA_QOS_LQOS_SHIFT) + +// Panics +#define DPI_DMA_PANICS 0x38 +#define DPI_DMA_PANICS_UPPER_COUNT_SHIFT 0 +#define DPI_DMA_PANICS_UPPER_COUNT_MASK \ + (0x0000FFFF << DPI_DMA_PANICS_UPPER_COUNT_SHIFT) +#define DPI_DMA_PANICS_LOWER_COUNT_SHIFT 16 +#define DPI_DMA_PANICS_LOWER_COUNT_MASK \ + (0x0000FFFF << DPI_DMA_PANICS_LOWER_COUNT_SHIFT) + +// DMA Address Lower: +#define DPI_DMA_DMA_ADDR_L 0x10 + +// DMA Address Upper: +#define DPI_DMA_DMA_ADDR_H 0x40 + +// DMA stride +#define DPI_DMA_DMA_STRIDE 0x14 + +// Visible Area +#define DPI_DMA_VISIBLE_AREA 0x18 +#define DPI_DMA_VISIBLE_AREA_ROWSM1_SHIFT 0 +#define DPI_DMA_VISIBLE_AREA_ROWSM1_MASK (0x0FFF << DPI_DMA_VISIBLE_AREA_ROWSM1_SHIFT) +#define DPI_DMA_VISIBLE_AREA_COLSM1_SHIFT 16 +#define DPI_DMA_VISIBLE_AREA_COLSM1_MASK (0x0FFF << DPI_DMA_VISIBLE_AREA_COLSM1_SHIFT) + +// Sync width +#define DPI_DMA_SYNC_WIDTH 0x1C +#define DPI_DMA_SYNC_WIDTH_ROWSM1_SHIFT 0 +#define DPI_DMA_SYNC_WIDTH_ROWSM1_MASK (0x0FFF << DPI_DMA_SYNC_WIDTH_ROWSM1_SHIFT) +#define DPI_DMA_SYNC_WIDTH_COLSM1_SHIFT 16 +#define DPI_DMA_SYNC_WIDTH_COLSM1_MASK (0x0FFF << DPI_DMA_SYNC_WIDTH_COLSM1_SHIFT) + +// Back porch +#define DPI_DMA_BACK_PORCH 0x20 +#define DPI_DMA_BACK_PORCH_ROWSM1_SHIFT 0 +#define DPI_DMA_BACK_PORCH_ROWSM1_MASK (0x0FFF << DPI_DMA_BACK_PORCH_ROWSM1_SHIFT) +#define DPI_DMA_BACK_PORCH_COLSM1_SHIFT 16 +#define DPI_DMA_BACK_PORCH_COLSM1_MASK (0x0FFF << DPI_DMA_BACK_PORCH_COLSM1_SHIFT) + +// Front porch +#define DPI_DMA_FRONT_PORCH 0x24 +#define DPI_DMA_FRONT_PORCH_ROWSM1_SHIFT 0 +#define DPI_DMA_FRONT_PORCH_ROWSM1_MASK (0x0FFF << DPI_DMA_FRONT_PORCH_ROWSM1_SHIFT) +#define DPI_DMA_FRONT_PORCH_COLSM1_SHIFT 16 +#define DPI_DMA_FRONT_PORCH_COLSM1_MASK (0x0FFF << DPI_DMA_FRONT_PORCH_COLSM1_SHIFT) + +// Input masks +#define DPI_DMA_IMASK 0x2C +#define DPI_DMA_IMASK_R_SHIFT 0 +#define DPI_DMA_IMASK_R_MASK (0x3FF << DPI_DMA_IMASK_R_SHIFT) +#define DPI_DMA_IMASK_G_SHIFT 10 +#define DPI_DMA_IMASK_G_MASK (0x3FF << DPI_DMA_IMASK_G_SHIFT) +#define DPI_DMA_IMASK_B_SHIFT 20 +#define DPI_DMA_IMASK_B_MASK (0x3FF << DPI_DMA_IMASK_B_SHIFT) + +// Output Masks +#define DPI_DMA_OMASK 0x30 +#define DPI_DMA_OMASK_R_SHIFT 0 +#define DPI_DMA_OMASK_R_MASK (0x3FF << DPI_DMA_OMASK_R_SHIFT) +#define DPI_DMA_OMASK_G_SHIFT 10 +#define DPI_DMA_OMASK_G_MASK (0x3FF << DPI_DMA_OMASK_G_SHIFT) +#define DPI_DMA_OMASK_B_SHIFT 20 +#define DPI_DMA_OMASK_B_MASK (0x3FF << DPI_DMA_OMASK_B_SHIFT) + +// Shifts +#define DPI_DMA_SHIFT 0x28 +#define DPI_DMA_SHIFT_IR_SHIFT 0 +#define DPI_DMA_SHIFT_IR_MASK (0x1F << DPI_DMA_SHIFT_IR_SHIFT) +#define DPI_DMA_SHIFT_IG_SHIFT 5 +#define DPI_DMA_SHIFT_IG_MASK (0x1F << DPI_DMA_SHIFT_IG_SHIFT) +#define DPI_DMA_SHIFT_IB_SHIFT 10 +#define DPI_DMA_SHIFT_IB_MASK (0x1F << DPI_DMA_SHIFT_IB_SHIFT) +#define DPI_DMA_SHIFT_OR_SHIFT 15 +#define DPI_DMA_SHIFT_OR_MASK (0x1F << DPI_DMA_SHIFT_OR_SHIFT) +#define DPI_DMA_SHIFT_OG_SHIFT 20 +#define DPI_DMA_SHIFT_OG_MASK (0x1F << DPI_DMA_SHIFT_OG_SHIFT) +#define DPI_DMA_SHIFT_OB_SHIFT 25 +#define DPI_DMA_SHIFT_OB_MASK (0x1F << DPI_DMA_SHIFT_OB_SHIFT) + +// Scaling +#define DPI_DMA_RGBSZ 0x34 +#define DPI_DMA_RGBSZ_BPP_SHIFT 16 +#define DPI_DMA_RGBSZ_BPP_MASK (0x3 << DPI_DMA_RGBSZ_BPP_SHIFT) +#define DPI_DMA_RGBSZ_R_SHIFT 0 +#define DPI_DMA_RGBSZ_R_MASK (0xF << DPI_DMA_RGBSZ_R_SHIFT) +#define DPI_DMA_RGBSZ_G_SHIFT 4 +#define DPI_DMA_RGBSZ_G_MASK (0xF << DPI_DMA_RGBSZ_G_SHIFT) +#define DPI_DMA_RGBSZ_B_SHIFT 8 +#define DPI_DMA_RGBSZ_B_MASK (0xF << DPI_DMA_RGBSZ_B_SHIFT) + +// Status +#define DPI_DMA_STATUS 0x3c + +#define BITS(field, val) (((val) << (field ## _SHIFT)) & (field ## _MASK)) + +static unsigned int rp1dpi_hw_read(struct rp1_dpi *dpi, unsigned int reg) +{ + void __iomem *addr = dpi->hw_base[RP1DPI_HW_BLOCK_DPI] + reg; + + return readl(addr); +} + +static void rp1dpi_hw_write(struct rp1_dpi *dpi, unsigned int reg, unsigned int val) +{ + void __iomem *addr = dpi->hw_base[RP1DPI_HW_BLOCK_DPI] + reg; + + writel(val, addr); +} + +int rp1dpi_hw_busy(struct rp1_dpi *dpi) +{ + return (rp1dpi_hw_read(dpi, DPI_DMA_STATUS) & 0xF8F) ? 1 : 0; +} + +/* Table of supported input (in-memory/DMA) pixel formats. */ +struct rp1dpi_ipixfmt { + u32 format; /* DRM format code */ + u32 mask; /* RGB masks (10 bits each, left justified) */ + u32 shift; /* RGB MSB positions in the memory word */ + u32 rgbsz; /* Shifts used for scaling; also (BPP/8-1) */ +}; + +#define IMASK_RGB(r, g, b) (BITS(DPI_DMA_IMASK_R, r) | \ + BITS(DPI_DMA_IMASK_G, g) | \ + BITS(DPI_DMA_IMASK_B, b)) +#define OMASK_RGB(r, g, b) (BITS(DPI_DMA_OMASK_R, r) | \ + BITS(DPI_DMA_OMASK_G, g) | \ + BITS(DPI_DMA_OMASK_B, b)) +#define ISHIFT_RGB(r, g, b) (BITS(DPI_DMA_SHIFT_IR, r) | \ + BITS(DPI_DMA_SHIFT_IG, g) | \ + BITS(DPI_DMA_SHIFT_IB, b)) +#define OSHIFT_RGB(r, g, b) (BITS(DPI_DMA_SHIFT_OR, r) | \ + BITS(DPI_DMA_SHIFT_OG, g) | \ + BITS(DPI_DMA_SHIFT_OB, b)) + +static const struct rp1dpi_ipixfmt my_formats[] = { + { + .format = DRM_FORMAT_XRGB8888, + .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc), + .shift = ISHIFT_RGB(23, 15, 7), + .rgbsz = BITS(DPI_DMA_RGBSZ_BPP, 3), + }, + { + .format = DRM_FORMAT_XBGR8888, + .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc), + .shift = ISHIFT_RGB(7, 15, 23), + .rgbsz = BITS(DPI_DMA_RGBSZ_BPP, 3), + }, + { + .format = DRM_FORMAT_RGB888, + .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc), + .shift = ISHIFT_RGB(23, 15, 7), + .rgbsz = BITS(DPI_DMA_RGBSZ_BPP, 2), + }, + { + .format = DRM_FORMAT_BGR888, + .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc), + .shift = ISHIFT_RGB(7, 15, 23), + .rgbsz = BITS(DPI_DMA_RGBSZ_BPP, 2), + }, + { + .format = DRM_FORMAT_RGB565, + .mask = IMASK_RGB(0x3e0, 0x3f0, 0x3e0), + .shift = ISHIFT_RGB(15, 10, 4), + .rgbsz = BITS(DPI_DMA_RGBSZ_R, 5) | BITS(DPI_DMA_RGBSZ_G, 6) | + BITS(DPI_DMA_RGBSZ_B, 5) | BITS(DPI_DMA_RGBSZ_BPP, 1), + }, + { + .format = DRM_FORMAT_BGR565, + .mask = IMASK_RGB(0x3e0, 0x3f0, 0x3e0), + .shift = ISHIFT_RGB(4, 10, 15), + .rgbsz = BITS(DPI_DMA_RGBSZ_R, 5) | BITS(DPI_DMA_RGBSZ_G, 6) | + BITS(DPI_DMA_RGBSZ_B, 5) | BITS(DPI_DMA_RGBSZ_BPP, 1), + } +}; + +static u32 set_output_format(u32 bus_format, u32 *shift, u32 *imask, u32 *rgbsz) +{ + switch (bus_format) { + case MEDIA_BUS_FMT_RGB565_1X16: + if (*shift == ISHIFT_RGB(15, 10, 4)) { + /* When framebuffer is RGB565, we can output RGB565 */ + *shift = ISHIFT_RGB(15, 7, 0) | OSHIFT_RGB(19, 9, 0); + *rgbsz &= DPI_DMA_RGBSZ_BPP_MASK; + return OMASK_RGB(0x3fc, 0x3fc, 0); + } + + /* due to a HW limitation, bit-depth is effectively RGB535 */ + *shift |= OSHIFT_RGB(19, 14, 6); + *imask &= IMASK_RGB(0x3e0, 0x380, 0x3e0); + *rgbsz = BITS(DPI_DMA_RGBSZ_G, 5) | (*rgbsz & DPI_DMA_RGBSZ_BPP_MASK); + return OMASK_RGB(0x3e0, 0x39c, 0x3e0); + + case MEDIA_BUS_FMT_RGB666_1X18: + case MEDIA_BUS_FMT_BGR666_1X18: + /* due to a HW limitation, bit-depth is effectively RGB444 */ + *shift |= OSHIFT_RGB(23, 15, 7); + *imask &= IMASK_RGB(0x3c0, 0x3c0, 0x3c0); + *rgbsz = BITS(DPI_DMA_RGBSZ_R, 2) | (*rgbsz & DPI_DMA_RGBSZ_BPP_MASK); + return OMASK_RGB(0x330, 0x3c0, 0x3c0); + + case MEDIA_BUS_FMT_RGB888_1X24: + case MEDIA_BUS_FMT_BGR888_1X24: + case MEDIA_BUS_FMT_RGB101010_1X30: + /* The full 24 bits can be output. Note that RP1's internal wiring means + * that 8.8.8 to GPIO pads can share with 10.10.10 to the onboard VDAC. + */ + *shift |= OSHIFT_RGB(29, 19, 9); + return OMASK_RGB(0x3fc, 0x3fc, 0x3fc); + + default: + /* RGB666_1x24_CPADHI, BGR666_1X24_CPADHI and "RGB565_666" formats */ + *shift |= OSHIFT_RGB(27, 17, 7); + *rgbsz &= DPI_DMA_RGBSZ_BPP_MASK; + return OMASK_RGB(0x3f0, 0x3f0, 0x3f0); + } +} + +#define BUS_FMT_IS_BGR(fmt) ( \ + ((fmt) == MEDIA_BUS_FMT_BGR666_1X18) || \ + ((fmt) == MEDIA_BUS_FMT_BGR666_1X24_CPADHI) || \ + ((fmt) == MEDIA_BUS_FMT_BGR888_1X24)) + +void rp1dpi_hw_setup(struct rp1_dpi *dpi, + u32 in_format, u32 bus_format, bool de_inv, + struct drm_display_mode const *mode) +{ + u32 shift, imask, omask, rgbsz; + int i; + + pr_info("%s: in_fmt=\'%c%c%c%c\' bus_fmt=0x%x mode=%dx%d total=%dx%d %dkHz %cH%cV%cD%cC", + __func__, in_format, in_format >> 8, in_format >> 16, in_format >> 24, bus_format, + mode->hdisplay, mode->vdisplay, + mode->htotal, mode->vtotal, + mode->clock, + (mode->flags & DRM_MODE_FLAG_NHSYNC) ? '-' : '+', + (mode->flags & DRM_MODE_FLAG_NVSYNC) ? '-' : '+', + de_inv ? '-' : '+', + dpi->clk_inv ? '-' : '+'); + + /* + * Configure all DPI/DMA block registers, except base address. + * DMA will not actually start until a FB base address is specified + * using rp1dpi_hw_update(). + */ + rp1dpi_hw_write(dpi, DPI_DMA_VISIBLE_AREA, + BITS(DPI_DMA_VISIBLE_AREA_ROWSM1, mode->vdisplay - 1) | + BITS(DPI_DMA_VISIBLE_AREA_COLSM1, mode->hdisplay - 1)); + + rp1dpi_hw_write(dpi, DPI_DMA_SYNC_WIDTH, + BITS(DPI_DMA_SYNC_WIDTH_ROWSM1, mode->vsync_end - mode->vsync_start - 1) | + BITS(DPI_DMA_SYNC_WIDTH_COLSM1, mode->hsync_end - mode->hsync_start - 1)); + + /* In these registers, "back porch" time includes sync width */ + rp1dpi_hw_write(dpi, DPI_DMA_BACK_PORCH, + BITS(DPI_DMA_BACK_PORCH_ROWSM1, mode->vtotal - mode->vsync_start - 1) | + BITS(DPI_DMA_BACK_PORCH_COLSM1, mode->htotal - mode->hsync_start - 1)); + + rp1dpi_hw_write(dpi, DPI_DMA_FRONT_PORCH, + BITS(DPI_DMA_FRONT_PORCH_ROWSM1, mode->vsync_start - mode->vdisplay - 1) | + BITS(DPI_DMA_FRONT_PORCH_COLSM1, mode->hsync_start - mode->hdisplay - 1)); + + /* Input to output pixel format conversion */ + for (i = 0; i < ARRAY_SIZE(my_formats); ++i) { + if (my_formats[i].format == in_format) + break; + } + if (i >= ARRAY_SIZE(my_formats)) { + pr_err("%s: bad input format\n", __func__); + i = 4; + } + if (BUS_FMT_IS_BGR(bus_format)) + i ^= 1; + shift = my_formats[i].shift; + imask = my_formats[i].mask; + rgbsz = my_formats[i].rgbsz; + omask = set_output_format(bus_format, &shift, &imask, &rgbsz); + + rp1dpi_hw_write(dpi, DPI_DMA_IMASK, imask); + rp1dpi_hw_write(dpi, DPI_DMA_OMASK, omask); + rp1dpi_hw_write(dpi, DPI_DMA_SHIFT, shift); + rp1dpi_hw_write(dpi, DPI_DMA_RGBSZ, rgbsz); + + rp1dpi_hw_write(dpi, DPI_DMA_QOS, + BITS(DPI_DMA_QOS_DQOS, 0x0) | + BITS(DPI_DMA_QOS_ULEV, 0xb) | + BITS(DPI_DMA_QOS_UQOS, 0x2) | + BITS(DPI_DMA_QOS_LLEV, 0x8) | + BITS(DPI_DMA_QOS_LQOS, 0x7)); + + rp1dpi_hw_write(dpi, DPI_DMA_IRQ_FLAGS, -1); + rp1dpi_hw_vblank_ctrl(dpi, 1); + + i = rp1dpi_hw_busy(dpi); + if (i) + pr_warn("%s: Unexpectedly busy at start!", __func__); + + rp1dpi_hw_write(dpi, DPI_DMA_CONTROL, + BITS(DPI_DMA_CONTROL_ARM, !i) | + BITS(DPI_DMA_CONTROL_AUTO_REPEAT, 1) | + BITS(DPI_DMA_CONTROL_HIGH_WATER, 448) | + BITS(DPI_DMA_CONTROL_DEN_POL, de_inv) | + BITS(DPI_DMA_CONTROL_HSYNC_POL, !!(mode->flags & DRM_MODE_FLAG_NHSYNC)) | + BITS(DPI_DMA_CONTROL_VSYNC_POL, !!(mode->flags & DRM_MODE_FLAG_NVSYNC)) | + BITS(DPI_DMA_CONTROL_COLORM, 0) | + BITS(DPI_DMA_CONTROL_SHUTDN, 0) | + BITS(DPI_DMA_CONTROL_HBP_EN, (mode->htotal != mode->hsync_end)) | + BITS(DPI_DMA_CONTROL_HFP_EN, (mode->hsync_start != mode->hdisplay)) | + BITS(DPI_DMA_CONTROL_VBP_EN, (mode->vtotal != mode->vsync_end)) | + BITS(DPI_DMA_CONTROL_VFP_EN, (mode->vsync_start != mode->vdisplay)) | + BITS(DPI_DMA_CONTROL_HSYNC_EN, (mode->hsync_end != mode->hsync_start)) | + BITS(DPI_DMA_CONTROL_VSYNC_EN, (mode->vsync_end != mode->vsync_start))); +} + +void rp1dpi_hw_update(struct rp1_dpi *dpi, dma_addr_t addr, u32 offset, u32 stride) +{ + u64 a = addr + offset; + + /* + * Update STRIDE, DMAH and DMAL only. When called after rp1dpi_hw_setup(), + * DMA starts immediately; if already running, the buffer will flip at + * the next vertical sync event. + */ + rp1dpi_hw_write(dpi, DPI_DMA_DMA_STRIDE, stride); + rp1dpi_hw_write(dpi, DPI_DMA_DMA_ADDR_H, a >> 32); + rp1dpi_hw_write(dpi, DPI_DMA_DMA_ADDR_L, a & 0xFFFFFFFFu); +} + +void rp1dpi_hw_stop(struct rp1_dpi *dpi) +{ + u32 ctrl; + + /* + * Stop DMA by turning off the Auto-Repeat flag, and wait up to 100ms for + * the current and any queued frame to end. "Force drain" flags are not used, + * as they seem to prevent DMA from re-starting properly; it's safer to wait. + */ + reinit_completion(&dpi->finished); + ctrl = rp1dpi_hw_read(dpi, DPI_DMA_CONTROL); + ctrl &= ~(DPI_DMA_CONTROL_ARM_MASK | DPI_DMA_CONTROL_AUTO_REPEAT_MASK); + rp1dpi_hw_write(dpi, DPI_DMA_CONTROL, ctrl); + if (!wait_for_completion_timeout(&dpi->finished, HZ / 10)) + drm_err(dpi->drm, "%s: timed out waiting for idle\n", __func__); + rp1dpi_hw_write(dpi, DPI_DMA_IRQ_EN, 0); +} + +void rp1dpi_hw_vblank_ctrl(struct rp1_dpi *dpi, int enable) +{ + rp1dpi_hw_write(dpi, DPI_DMA_IRQ_EN, + BITS(DPI_DMA_IRQ_EN_AFIFO_EMPTY, 1) | + BITS(DPI_DMA_IRQ_EN_UNDERFLOW, 1) | + BITS(DPI_DMA_IRQ_EN_DMA_READY, !!enable) | + BITS(DPI_DMA_IRQ_EN_MATCH_LINE, 4095)); +} + +irqreturn_t rp1dpi_hw_isr(int irq, void *dev) +{ + struct rp1_dpi *dpi = dev; + u32 u = rp1dpi_hw_read(dpi, DPI_DMA_IRQ_FLAGS); + + if (u) { + rp1dpi_hw_write(dpi, DPI_DMA_IRQ_FLAGS, u); + if (dpi) { + if (u & DPI_DMA_IRQ_FLAGS_UNDERFLOW_MASK) + drm_err_ratelimited(dpi->drm, + "Underflow! (panics=0x%08x)\n", + rp1dpi_hw_read(dpi, DPI_DMA_PANICS)); + if (u & DPI_DMA_IRQ_FLAGS_DMA_READY_MASK) + drm_crtc_handle_vblank(&dpi->pipe.crtc); + if (u & DPI_DMA_IRQ_FLAGS_AFIFO_EMPTY_MASK) + complete(&dpi->finished); + } + } + return u ? IRQ_HANDLED : IRQ_NONE; +} diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-dsi/Kconfig linux/drivers/gpu/drm/rp1/rp1-dsi/Kconfig --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-dsi/Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-dsi/Kconfig 2023-12-13 11:50:59.408986724 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: GPL-2.0-only +config DRM_RP1_DSI + tristate "DRM Support for RP1 DSI" + depends on DRM + select MFD_RP1 + select DRM_GEM_DMA_HELPER + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_VRAM_HELPER + select DRM_TTM + select DRM_TTM_HELPER + select GENERIC_PHY + select GENERIC_PHY_MIPI_DPHY + help + Choose this option to enable DSI display on RP1 diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-dsi/Makefile linux/drivers/gpu/drm/rp1/rp1-dsi/Makefile --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-dsi/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-dsi/Makefile 2023-12-13 11:50:59.408986724 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:2 @ +# SPDX-License-Identifier: GPL-2.0-only + +drm-rp1-dsi-y := rp1_dsi.o rp1_dsi_dma.o rp1_dsi_dsi.o + +obj-$(CONFIG_DRM_RP1_DSI) += drm-rp1-dsi.o diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.c linux/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.c --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.c 2023-12-13 11:50:59.408986724 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DRM Driver for DSI output on Raspberry Pi RP1 + * + * Copyright (c) 2023 Raspberry Pi Limited. + */ + +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/phy/phy-mipi-dphy.h> +#include <linux/string.h> + +#include <drm/drm_atomic_helper.h> +#include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_drv.h> +#include <drm/drm_encoder.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_framebuffer.h> +#include <drm/drm_gem.h> +#include <drm/drm_gem_atomic_helper.h> +#include <drm/drm_gem_dma_helper.h> +#include <drm/drm_gem_framebuffer_helper.h> +#include <drm/drm_managed.h> +#include <drm/drm_modeset_helper_vtables.h> +#include <drm/drm_of.h> +#include <drm/drm_print.h> +#include <drm/drm_probe_helper.h> +#include <drm/drm_simple_kms_helper.h> +#include <drm/drm_vblank.h> + +#include "rp1_dsi.h" + +static inline struct rp1_dsi * +bridge_to_rp1_dsi(struct drm_bridge *bridge) +{ + return container_of(bridge, struct rp1_dsi, bridge); +} + +static void rp1_dsi_bridge_pre_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_state) +{ + struct rp1_dsi *dsi = bridge_to_rp1_dsi(bridge); + + rp1dsi_dsi_setup(dsi, &dsi->pipe.crtc.state->adjusted_mode); +} + +static void rp1_dsi_bridge_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_state) +{ +} + +static void rp1_dsi_bridge_disable(struct drm_bridge *bridge, + struct drm_bridge_state *state) +{ +} + +static void rp1_dsi_bridge_post_disable(struct drm_bridge *bridge, + struct drm_bridge_state *state) +{ + struct rp1_dsi *dsi = bridge_to_rp1_dsi(bridge); + + if (dsi->dsi_running) { + rp1dsi_dsi_stop(dsi); + dsi->dsi_running = false; + } +} + +static int rp1_dsi_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct rp1_dsi *dsi = bridge_to_rp1_dsi(bridge); + + /* Attach the panel or bridge to the dsi bridge */ + return drm_bridge_attach(bridge->encoder, dsi->out_bridge, + &dsi->bridge, flags); + return 0; +} + +static const struct drm_bridge_funcs rp1_dsi_bridge_funcs = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_pre_enable = rp1_dsi_bridge_pre_enable, + .atomic_enable = rp1_dsi_bridge_enable, + .atomic_disable = rp1_dsi_bridge_disable, + .atomic_post_disable = rp1_dsi_bridge_post_disable, + .attach = rp1_dsi_bridge_attach, +}; + +static void rp1dsi_pipe_update(struct drm_simple_display_pipe *pipe, + struct drm_plane_state *old_state) +{ + struct drm_pending_vblank_event *event; + unsigned long flags; + struct drm_framebuffer *fb = pipe->plane.state->fb; + struct rp1_dsi *dsi = pipe->crtc.dev->dev_private; + struct drm_gem_object *gem = fb ? drm_gem_fb_get_obj(fb, 0) : NULL; + struct drm_gem_dma_object *dma_obj = gem ? to_drm_gem_dma_obj(gem) : NULL; + bool can_update = fb && dma_obj && dsi && dsi->pipe_enabled; + + /* (Re-)start DSI,DMA where required; and update FB address */ + if (can_update) { + if (!dsi->dma_running || fb->format->format != dsi->cur_fmt) { + if (dsi->dma_running && fb->format->format != dsi->cur_fmt) { + rp1dsi_dma_stop(dsi); + dsi->dma_running = false; + } + if (!dsi->dma_running) { + rp1dsi_dma_setup(dsi, + fb->format->format, dsi->display_format, + &pipe->crtc.state->adjusted_mode); + dsi->dma_running = true; + } + dsi->cur_fmt = fb->format->format; + drm_crtc_vblank_on(&pipe->crtc); + } + rp1dsi_dma_update(dsi, dma_obj->dma_addr, fb->offsets[0], fb->pitches[0]); + } + + /* Arm VBLANK event (or call it immediately in some error cases) */ + spin_lock_irqsave(&pipe->crtc.dev->event_lock, flags); + event = pipe->crtc.state->event; + if (event) { + pipe->crtc.state->event = NULL; + if (can_update && drm_crtc_vblank_get(&pipe->crtc) == 0) + drm_crtc_arm_vblank_event(&pipe->crtc, event); + else + drm_crtc_send_vblank_event(&pipe->crtc, event); + } + spin_unlock_irqrestore(&pipe->crtc.dev->event_lock, flags); +} + +static inline struct rp1_dsi * +encoder_to_rp1_dsi(struct drm_encoder *encoder) +{ + struct drm_simple_display_pipe *pipe = + container_of(encoder, struct drm_simple_display_pipe, encoder); + return container_of(pipe, struct rp1_dsi, pipe); +} + +static void rp1dsi_encoder_enable(struct drm_encoder *encoder) +{ + struct rp1_dsi *dsi = encoder_to_rp1_dsi(encoder); + + /* Put DSI into video mode before starting video */ + rp1dsi_dsi_set_cmdmode(dsi, 0); + + /* Start DMA -> DPI */ + dsi->pipe_enabled = true; + dsi->cur_fmt = 0xdeadbeef; + rp1dsi_pipe_update(&dsi->pipe, 0); +} + +static void rp1dsi_encoder_disable(struct drm_encoder *encoder) +{ + struct rp1_dsi *dsi = encoder_to_rp1_dsi(encoder); + + drm_crtc_vblank_off(&dsi->pipe.crtc); + if (dsi->dma_running) { + rp1dsi_dma_stop(dsi); + dsi->dma_running = false; + } + dsi->pipe_enabled = false; + + /* Return to command mode after stopping video */ + rp1dsi_dsi_set_cmdmode(dsi, 1); +} + +static const struct drm_encoder_helper_funcs rp1_dsi_encoder_funcs = { + .enable = rp1dsi_encoder_enable, + .disable = rp1dsi_encoder_disable, +}; + +static void rp1dsi_pipe_enable(struct drm_simple_display_pipe *pipe, + struct drm_crtc_state *crtc_state, + struct drm_plane_state *plane_state) +{ +} + +static void rp1dsi_pipe_disable(struct drm_simple_display_pipe *pipe) +{ +} + +static int rp1dsi_pipe_enable_vblank(struct drm_simple_display_pipe *pipe) +{ + struct rp1_dsi *dsi = pipe->crtc.dev->dev_private; + + if (dsi) + rp1dsi_dma_vblank_ctrl(dsi, 1); + + return 0; +} + +static void rp1dsi_pipe_disable_vblank(struct drm_simple_display_pipe *pipe) +{ + struct rp1_dsi *dsi = pipe->crtc.dev->dev_private; + + if (dsi) + rp1dsi_dma_vblank_ctrl(dsi, 0); +} + +static const struct drm_simple_display_pipe_funcs rp1dsi_pipe_funcs = { + .enable = rp1dsi_pipe_enable, + .update = rp1dsi_pipe_update, + .disable = rp1dsi_pipe_disable, + .prepare_fb = drm_gem_simple_display_pipe_prepare_fb, + .enable_vblank = rp1dsi_pipe_enable_vblank, + .disable_vblank = rp1dsi_pipe_disable_vblank, +}; + +static const struct drm_mode_config_funcs rp1dsi_mode_funcs = { + .fb_create = drm_gem_fb_create, + .atomic_check = drm_atomic_helper_check, + .atomic_commit = drm_atomic_helper_commit, +}; + +static const u32 rp1dsi_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565 +}; + +static void rp1dsi_stopall(struct drm_device *drm) +{ + if (drm->dev_private) { + struct rp1_dsi *dsi = drm->dev_private; + + if (dsi->dma_running || rp1dsi_dma_busy(dsi)) { + rp1dsi_dma_stop(dsi); + dsi->dma_running = false; + } + if (dsi->dsi_running) { + rp1dsi_dsi_stop(dsi); + dsi->dsi_running = false; + } + if (dsi->clocks[RP1DSI_CLOCK_CFG]) + clk_disable_unprepare(dsi->clocks[RP1DSI_CLOCK_CFG]); + } +} + +DEFINE_DRM_GEM_DMA_FOPS(rp1dsi_fops); + +static struct drm_driver rp1dsi_driver = { + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, + .fops = &rp1dsi_fops, + .name = "drm-rp1-dsi", + .desc = "drm-rp1-dsi", + .date = "0", + .major = 1, + .minor = 0, + DRM_GEM_DMA_DRIVER_OPS, + .release = rp1dsi_stopall, +}; + +static int rp1dsi_bind(struct rp1_dsi *dsi) +{ + struct platform_device *pdev = dsi->pdev; + struct drm_device *drm = dsi->drm; + int ret; + + dsi->out_bridge = drmm_of_get_bridge(drm, pdev->dev.of_node, 0, 0); + if (IS_ERR(dsi->out_bridge)) + return PTR_ERR(dsi->out_bridge); + + ret = drmm_mode_config_init(drm); + if (ret) + goto rtn; + + drm->mode_config.max_width = 4096; + drm->mode_config.max_height = 4096; + drm->mode_config.fb_base = 0; + drm->mode_config.preferred_depth = 32; + drm->mode_config.prefer_shadow = 0; + drm->mode_config.prefer_shadow_fbdev = 1; + drm->mode_config.quirk_addfb_prefer_host_byte_order = true; + drm->mode_config.funcs = &rp1dsi_mode_funcs; + drm_vblank_init(drm, 1); + + ret = drm_simple_display_pipe_init(drm, + &dsi->pipe, + &rp1dsi_pipe_funcs, + rp1dsi_formats, + ARRAY_SIZE(rp1dsi_formats), + NULL, NULL); + if (ret) + goto rtn; + + /* We need slightly more complex encoder handling (enabling/disabling + * video mode), so add encoder helper functions. + */ + drm_encoder_helper_add(&dsi->pipe.encoder, &rp1_dsi_encoder_funcs); + + ret = drm_simple_display_pipe_attach_bridge(&dsi->pipe, &dsi->bridge); + if (ret) + goto rtn; + + drm_bridge_add(&dsi->bridge); + + drm_mode_config_reset(drm); + + if (dsi->clocks[RP1DSI_CLOCK_CFG]) + clk_prepare_enable(dsi->clocks[RP1DSI_CLOCK_CFG]); + + ret = drm_dev_register(drm, 0); + + if (ret == 0) + drm_fbdev_generic_setup(drm, 32); + +rtn: + if (ret) + dev_err(&pdev->dev, "%s returned %d\n", __func__, ret); + else + dev_info(&pdev->dev, "%s succeeded", __func__); + + return ret; +} + +static void rp1dsi_unbind(struct rp1_dsi *dsi) +{ + struct drm_device *drm = dsi->drm; + + rp1dsi_stopall(drm); + drm_dev_unregister(drm); + drm_atomic_helper_shutdown(drm); +} + +int rp1dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *dsi_dev) +{ + struct rp1_dsi *dsi = container_of(host, struct rp1_dsi, dsi_host); + + dev_info(&dsi->pdev->dev, "%s: Attach DSI device name=%s channel=%d lanes=%d format=%d flags=0x%lx hs_rate=%lu lp_rate=%lu", + __func__, dsi_dev->name, dsi_dev->channel, dsi_dev->lanes, + dsi_dev->format, dsi_dev->mode_flags, dsi_dev->hs_rate, + dsi_dev->lp_rate); + dsi->vc = dsi_dev->channel & 3; + dsi->lanes = dsi_dev->lanes; + + switch (dsi_dev->format) { + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + case MIPI_DSI_FMT_RGB565: + case MIPI_DSI_FMT_RGB888: + break; + default: + return -EINVAL; + } + dsi->display_format = dsi_dev->format; + dsi->display_flags = dsi_dev->mode_flags; + dsi->display_hs_rate = dsi_dev->hs_rate; + dsi->display_lp_rate = dsi_dev->lp_rate; + + /* + * Previously, we added a separate component to handle panel/bridge + * discovery and DRM registration, but now it's just a function call. + * The downstream/attaching device should deal with -EPROBE_DEFER + */ + return rp1dsi_bind(dsi); +} + +int rp1dsi_host_detach(struct mipi_dsi_host *host, struct mipi_dsi_device *dsi_dev) +{ + struct rp1_dsi *dsi = container_of(host, struct rp1_dsi, dsi_host); + + /* + * Unregister the DRM driver. + * TODO: Check we are cleaning up correctly and not doing things multiple times! + */ + rp1dsi_unbind(dsi); + return 0; +} + +ssize_t rp1dsi_host_transfer(struct mipi_dsi_host *host, const struct mipi_dsi_msg *msg) +{ + struct rp1_dsi *dsi = container_of(host, struct rp1_dsi, dsi_host); + struct mipi_dsi_packet packet; + int ret = 0; + + /* Write */ + ret = mipi_dsi_create_packet(&packet, msg); + if (ret) { + dev_err(dsi->drm->dev, "RP1DSI: failed to create packet: %d\n", ret); + return ret; + } + + rp1dsi_dsi_send(dsi, *(u32 *)(&packet.header), packet.payload_length, packet.payload); + + /* Optional read back */ + if (msg->rx_len && msg->rx_buf) + ret = rp1dsi_dsi_recv(dsi, msg->rx_len, msg->rx_buf); + + return (ssize_t)ret; +} + +static const struct mipi_dsi_host_ops rp1dsi_mipi_dsi_host_ops = { + .attach = rp1dsi_host_attach, + .detach = rp1dsi_host_detach, + .transfer = rp1dsi_host_transfer +}; + +static int rp1dsi_platform_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct drm_device *drm; + struct rp1_dsi *dsi; + int i, ret; + + drm = drm_dev_alloc(&rp1dsi_driver, dev); + if (IS_ERR(drm)) { + ret = PTR_ERR(drm); + return ret; + } + dsi = drmm_kzalloc(drm, sizeof(*dsi), GFP_KERNEL); + if (!dsi) { + ret = -ENOMEM; + goto err_free_drm; + } + init_completion(&dsi->finished); + dsi->drm = drm; + dsi->pdev = pdev; + drm->dev_private = dsi; + platform_set_drvdata(pdev, drm); + + dsi->bridge.funcs = &rp1_dsi_bridge_funcs; + dsi->bridge.of_node = dev->of_node; + dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; + + /* Safe default values for DSI mode */ + dsi->lanes = 1; + dsi->display_format = MIPI_DSI_FMT_RGB888; + dsi->display_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM; + + /* Hardware resources */ + for (i = 0; i < RP1DSI_NUM_CLOCKS; i++) { + static const char * const myclocknames[RP1DSI_NUM_CLOCKS] = { + "cfgclk", "dpiclk", "byteclk", "refclk" + }; + dsi->clocks[i] = devm_clk_get(dev, myclocknames[i]); + if (IS_ERR(dsi->clocks[i])) { + ret = PTR_ERR(dsi->clocks[i]); + dev_err(dev, "Error getting clocks[%d]\n", i); + goto err_free_drm; + } + } + + for (i = 0; i < RP1DSI_NUM_HW_BLOCKS; i++) { + dsi->hw_base[i] = + devm_ioremap_resource(dev, + platform_get_resource(dsi->pdev, + IORESOURCE_MEM, + i)); + if (IS_ERR(dsi->hw_base[i])) { + ret = PTR_ERR(dsi->hw_base[i]); + dev_err(dev, "Error memory mapping regs[%d]\n", i); + goto err_free_drm; + } + } + ret = platform_get_irq(dsi->pdev, 0); + if (ret > 0) + ret = devm_request_irq(dev, ret, rp1dsi_dma_isr, + IRQF_SHARED, "rp1-dsi", dsi); + if (ret) { + dev_err(dev, "Unable to request interrupt\n"); + ret = -EINVAL; + goto err_free_drm; + } + rp1dsi_mipicfg_setup(dsi); + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + + /* Create the MIPI DSI Host and wait for the panel/bridge to attach to it */ + dsi->dsi_host.ops = &rp1dsi_mipi_dsi_host_ops; + dsi->dsi_host.dev = dev; + ret = mipi_dsi_host_register(&dsi->dsi_host); + if (ret) + goto err_free_drm; + + return ret; + +err_free_drm: + dev_err(dev, "%s fail %d\n", __func__, ret); + drm_dev_put(drm); + return ret; +} + +static int rp1dsi_platform_remove(struct platform_device *pdev) +{ + struct drm_device *drm = platform_get_drvdata(pdev); + struct rp1_dsi *dsi = drm->dev_private; + + mipi_dsi_host_unregister(&dsi->dsi_host); + return 0; +} + +static void rp1dsi_platform_shutdown(struct platform_device *pdev) +{ + struct drm_device *drm = platform_get_drvdata(pdev); + + rp1dsi_stopall(drm); +} + +static const struct of_device_id rp1dsi_of_match[] = { + { + .compatible = "raspberrypi,rp1dsi", + }, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, rp1dsi_of_match); + +static struct platform_driver rp1dsi_platform_driver = { + .probe = rp1dsi_platform_probe, + .remove = rp1dsi_platform_remove, + .shutdown = rp1dsi_platform_shutdown, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = rp1dsi_of_match, + }, +}; + +module_platform_driver(rp1dsi_platform_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MIPI DSI driver for Raspberry Pi RP1"); +MODULE_AUTHOR("Nick Hollinghurst"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dma.c linux/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dma.c --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dma.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dma.c 2023-12-13 11:50:59.409986726 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DRM Driver for DSI output on Raspberry Pi RP1 + * + * Copyright (c) 2023 Raspberry Pi Limited. + */ + +#include <linux/interrupt.h> +#include <linux/platform_device.h> + +#include <drm/drm_fourcc.h> +#include <drm/drm_print.h> +#include <drm/drm_vblank.h> + +#include "rp1_dsi.h" + +// --- DPI DMA REGISTERS (derived from Argon firmware, via RP1 drivers/mipi, with corrections) --- + +// Control +#define DPI_DMA_CONTROL 0x0 +#define DPI_DMA_CONTROL_ARM_SHIFT 0 +#define DPI_DMA_CONTROL_ARM_MASK BIT(DPI_DMA_CONTROL_ARM_SHIFT) +#define DPI_DMA_CONTROL_ALIGN16_SHIFT 2 +#define DPI_DMA_CONTROL_ALIGN16_MASK BIT(DPI_DMA_CONTROL_ALIGN16_SHIFT) +#define DPI_DMA_CONTROL_AUTO_REPEAT_SHIFT 1 +#define DPI_DMA_CONTROL_AUTO_REPEAT_MASK BIT(DPI_DMA_CONTROL_AUTO_REPEAT_SHIFT) +#define DPI_DMA_CONTROL_HIGH_WATER_SHIFT 3 +#define DPI_DMA_CONTROL_HIGH_WATER_MASK (0x1FF << DPI_DMA_CONTROL_HIGH_WATER_SHIFT) +#define DPI_DMA_CONTROL_DEN_POL_SHIFT 12 +#define DPI_DMA_CONTROL_DEN_POL_MASK BIT(DPI_DMA_CONTROL_DEN_POL_SHIFT) +#define DPI_DMA_CONTROL_HSYNC_POL_SHIFT 13 +#define DPI_DMA_CONTROL_HSYNC_POL_MASK BIT(DPI_DMA_CONTROL_HSYNC_POL_SHIFT) +#define DPI_DMA_CONTROL_VSYNC_POL_SHIFT 14 +#define DPI_DMA_CONTROL_VSYNC_POL_MASK BIT(DPI_DMA_CONTROL_VSYNC_POL_SHIFT) +#define DPI_DMA_CONTROL_COLORM_SHIFT 15 +#define DPI_DMA_CONTROL_COLORM_MASK BIT(DPI_DMA_CONTROL_COLORM_SHIFT) +#define DPI_DMA_CONTROL_SHUTDN_SHIFT 16 +#define DPI_DMA_CONTROL_SHUTDN_MASK BIT(DPI_DMA_CONTROL_SHUTDN_SHIFT) +#define DPI_DMA_CONTROL_HBP_EN_SHIFT 17 +#define DPI_DMA_CONTROL_HBP_EN_MASK BIT(DPI_DMA_CONTROL_HBP_EN_SHIFT) +#define DPI_DMA_CONTROL_HFP_EN_SHIFT 18 +#define DPI_DMA_CONTROL_HFP_EN_MASK BIT(DPI_DMA_CONTROL_HFP_EN_SHIFT) +#define DPI_DMA_CONTROL_VBP_EN_SHIFT 19 +#define DPI_DMA_CONTROL_VBP_EN_MASK BIT(DPI_DMA_CONTROL_VBP_EN_SHIFT) +#define DPI_DMA_CONTROL_VFP_EN_SHIFT 20 +#define DPI_DMA_CONTROL_VFP_EN_MASK BIT(DPI_DMA_CONTROL_VFP_EN_SHIFT) +#define DPI_DMA_CONTROL_HSYNC_EN_SHIFT 21 +#define DPI_DMA_CONTROL_HSYNC_EN_MASK BIT(DPI_DMA_CONTROL_HSYNC_EN_SHIFT) +#define DPI_DMA_CONTROL_VSYNC_EN_SHIFT 22 +#define DPI_DMA_CONTROL_VSYNC_EN_MASK BIT(DPI_DMA_CONTROL_VSYNC_EN_SHIFT) +#define DPI_DMA_CONTROL_FORCE_IMMED_SHIFT 23 +#define DPI_DMA_CONTROL_FORCE_IMMED_MASK BIT(DPI_DMA_CONTROL_FORCE_IMMED_SHIFT) +#define DPI_DMA_CONTROL_FORCE_DRAIN_SHIFT 24 +#define DPI_DMA_CONTROL_FORCE_DRAIN_MASK BIT(DPI_DMA_CONTROL_FORCE_DRAIN_SHIFT) +#define DPI_DMA_CONTROL_FORCE_EMPTY_SHIFT 25 +#define DPI_DMA_CONTROL_FORCE_EMPTY_MASK BIT(DPI_DMA_CONTROL_FORCE_EMPTY_SHIFT) + +// IRQ_ENABLES +#define DPI_DMA_IRQ_EN 0x04 +#define DPI_DMA_IRQ_EN_DMA_READY_SHIFT 0 +#define DPI_DMA_IRQ_EN_DMA_READY_MASK BIT(DPI_DMA_IRQ_EN_DMA_READY_SHIFT) +#define DPI_DMA_IRQ_EN_UNDERFLOW_SHIFT 1 +#define DPI_DMA_IRQ_EN_UNDERFLOW_MASK BIT(DPI_DMA_IRQ_EN_UNDERFLOW_SHIFT) +#define DPI_DMA_IRQ_EN_FRAME_START_SHIFT 2 +#define DPI_DMA_IRQ_EN_FRAME_START_MASK BIT(DPI_DMA_IRQ_EN_FRAME_START_SHIFT) +#define DPI_DMA_IRQ_EN_AFIFO_EMPTY_SHIFT 3 +#define DPI_DMA_IRQ_EN_AFIFO_EMPTY_MASK BIT(DPI_DMA_IRQ_EN_AFIFO_EMPTY_SHIFT) +#define DPI_DMA_IRQ_EN_TE_SHIFT 4 +#define DPI_DMA_IRQ_EN_TE_MASK BIT(DPI_DMA_IRQ_EN_TE_SHIFT) +#define DPI_DMA_IRQ_EN_ERROR_SHIFT 5 +#define DPI_DMA_IRQ_EN_ERROR_MASK BIT(DPI_DMA_IRQ_EN_ERROR_SHIFT) +#define DPI_DMA_IRQ_EN_MATCH_SHIFT 6 +#define DPI_DMA_IRQ_EN_MATCH_MASK BIT(DPI_DMA_IRQ_EN_MATCH_SHIFT) +#define DPI_DMA_IRQ_EN_MATCH_LINE_SHIFT 16 +#define DPI_DMA_IRQ_EN_MATCH_LINE_MASK (0xFFF << DPI_DMA_IRQ_EN_MATCH_LINE_SHIFT) + +// IRQ_FLAGS +#define DPI_DMA_IRQ_FLAGS 0x08 +#define DPI_DMA_IRQ_FLAGS_DMA_READY_SHIFT 0 +#define DPI_DMA_IRQ_FLAGS_DMA_READY_MASK BIT(DPI_DMA_IRQ_FLAGS_DMA_READY_SHIFT) +#define DPI_DMA_IRQ_FLAGS_UNDERFLOW_SHIFT 1 +#define DPI_DMA_IRQ_FLAGS_UNDERFLOW_MASK BIT(DPI_DMA_IRQ_FLAGS_UNDERFLOW_SHIFT) +#define DPI_DMA_IRQ_FLAGS_FRAME_START_SHIFT 2 +#define DPI_DMA_IRQ_FLAGS_FRAME_START_MASK BIT(DPI_DMA_IRQ_FLAGS_FRAME_START_SHIFT) +#define DPI_DMA_IRQ_FLAGS_AFIFO_EMPTY_SHIFT 3 +#define DPI_DMA_IRQ_FLAGS_AFIFO_EMPTY_MASK BIT(DPI_DMA_IRQ_FLAGS_AFIFO_EMPTY_SHIFT) +#define DPI_DMA_IRQ_FLAGS_TE_SHIFT 4 +#define DPI_DMA_IRQ_FLAGS_TE_MASK BIT(DPI_DMA_IRQ_FLAGS_TE_SHIFT) +#define DPI_DMA_IRQ_FLAGS_ERROR_SHIFT 5 +#define DPI_DMA_IRQ_FLAGS_ERROR_MASK BIT(DPI_DMA_IRQ_FLAGS_ERROR_SHIFT) +#define DPI_DMA_IRQ_FLAGS_MATCH_SHIFT 6 +#define DPI_DMA_IRQ_FLAGS_MATCH_MASK BIT(DPI_DMA_IRQ_FLAGS_MATCH_SHIFT) + +// QOS +#define DPI_DMA_QOS 0xC +#define DPI_DMA_QOS_DQOS_SHIFT 0 +#define DPI_DMA_QOS_DQOS_MASK (0xF << DPI_DMA_QOS_DQOS_SHIFT) +#define DPI_DMA_QOS_ULEV_SHIFT 4 +#define DPI_DMA_QOS_ULEV_MASK (0xF << DPI_DMA_QOS_ULEV_SHIFT) +#define DPI_DMA_QOS_UQOS_SHIFT 8 +#define DPI_DMA_QOS_UQOS_MASK (0xF << DPI_DMA_QOS_UQOS_SHIFT) +#define DPI_DMA_QOS_LLEV_SHIFT 12 +#define DPI_DMA_QOS_LLEV_MASK (0xF << DPI_DMA_QOS_LLEV_SHIFT) +#define DPI_DMA_QOS_LQOS_SHIFT 16 +#define DPI_DMA_QOS_LQOS_MASK (0xF << DPI_DMA_QOS_LQOS_SHIFT) + +// Panics +#define DPI_DMA_PANICS 0x38 +#define DPI_DMA_PANICS_UPPER_COUNT_SHIFT 0 +#define DPI_DMA_PANICS_UPPER_COUNT_MASK \ + (0x0000FFFF << DPI_DMA_PANICS_UPPER_COUNT_SHIFT) +#define DPI_DMA_PANICS_LOWER_COUNT_SHIFT 16 +#define DPI_DMA_PANICS_LOWER_COUNT_MASK \ + (0x0000FFFF << DPI_DMA_PANICS_LOWER_COUNT_SHIFT) + +// DMA Address Lower: +#define DPI_DMA_DMA_ADDR_L 0x10 + +// DMA Address Upper: +#define DPI_DMA_DMA_ADDR_H 0x40 + +// DMA stride +#define DPI_DMA_DMA_STRIDE 0x14 + +// Visible Area +#define DPI_DMA_VISIBLE_AREA 0x18 +#define DPI_DMA_VISIBLE_AREA_ROWSM1_SHIFT 0 +#define DPI_DMA_VISIBLE_AREA_ROWSM1_MASK (0x0FFF << DPI_DMA_VISIBLE_AREA_ROWSM1_SHIFT) +#define DPI_DMA_VISIBLE_AREA_COLSM1_SHIFT 16 +#define DPI_DMA_VISIBLE_AREA_COLSM1_MASK (0x0FFF << DPI_DMA_VISIBLE_AREA_COLSM1_SHIFT) + +// Sync width +#define DPI_DMA_SYNC_WIDTH 0x1C +#define DPI_DMA_SYNC_WIDTH_ROWSM1_SHIFT 0 +#define DPI_DMA_SYNC_WIDTH_ROWSM1_MASK (0x0FFF << DPI_DMA_SYNC_WIDTH_ROWSM1_SHIFT) +#define DPI_DMA_SYNC_WIDTH_COLSM1_SHIFT 16 +#define DPI_DMA_SYNC_WIDTH_COLSM1_MASK (0x0FFF << DPI_DMA_SYNC_WIDTH_COLSM1_SHIFT) + +// Back porch +#define DPI_DMA_BACK_PORCH 0x20 +#define DPI_DMA_BACK_PORCH_ROWSM1_SHIFT 0 +#define DPI_DMA_BACK_PORCH_ROWSM1_MASK (0x0FFF << DPI_DMA_BACK_PORCH_ROWSM1_SHIFT) +#define DPI_DMA_BACK_PORCH_COLSM1_SHIFT 16 +#define DPI_DMA_BACK_PORCH_COLSM1_MASK (0x0FFF << DPI_DMA_BACK_PORCH_COLSM1_SHIFT) + +// Front porch +#define DPI_DMA_FRONT_PORCH 0x24 +#define DPI_DMA_FRONT_PORCH_ROWSM1_SHIFT 0 +#define DPI_DMA_FRONT_PORCH_ROWSM1_MASK (0x0FFF << DPI_DMA_FRONT_PORCH_ROWSM1_SHIFT) +#define DPI_DMA_FRONT_PORCH_COLSM1_SHIFT 16 +#define DPI_DMA_FRONT_PORCH_COLSM1_MASK (0x0FFF << DPI_DMA_FRONT_PORCH_COLSM1_SHIFT) + +// Input masks +#define DPI_DMA_IMASK 0x2C +#define DPI_DMA_IMASK_R_SHIFT 0 +#define DPI_DMA_IMASK_R_MASK (0x3FF << DPI_DMA_IMASK_R_SHIFT) +#define DPI_DMA_IMASK_G_SHIFT 10 +#define DPI_DMA_IMASK_G_MASK (0x3FF << DPI_DMA_IMASK_G_SHIFT) +#define DPI_DMA_IMASK_B_SHIFT 20 +#define DPI_DMA_IMASK_B_MASK (0x3FF << DPI_DMA_IMASK_B_SHIFT) + +// Output Masks +#define DPI_DMA_OMASK 0x30 +#define DPI_DMA_OMASK_R_SHIFT 0 +#define DPI_DMA_OMASK_R_MASK (0x3FF << DPI_DMA_OMASK_R_SHIFT) +#define DPI_DMA_OMASK_G_SHIFT 10 +#define DPI_DMA_OMASK_G_MASK (0x3FF << DPI_DMA_OMASK_G_SHIFT) +#define DPI_DMA_OMASK_B_SHIFT 20 +#define DPI_DMA_OMASK_B_MASK (0x3FF << DPI_DMA_OMASK_B_SHIFT) + +// Shifts +#define DPI_DMA_SHIFT 0x28 +#define DPI_DMA_SHIFT_IR_SHIFT 0 +#define DPI_DMA_SHIFT_IR_MASK (0x1F << DPI_DMA_SHIFT_IR_SHIFT) +#define DPI_DMA_SHIFT_IG_SHIFT 5 +#define DPI_DMA_SHIFT_IG_MASK (0x1F << DPI_DMA_SHIFT_IG_SHIFT) +#define DPI_DMA_SHIFT_IB_SHIFT 10 +#define DPI_DMA_SHIFT_IB_MASK (0x1F << DPI_DMA_SHIFT_IB_SHIFT) +#define DPI_DMA_SHIFT_OR_SHIFT 15 +#define DPI_DMA_SHIFT_OR_MASK (0x1F << DPI_DMA_SHIFT_OR_SHIFT) +#define DPI_DMA_SHIFT_OG_SHIFT 20 +#define DPI_DMA_SHIFT_OG_MASK (0x1F << DPI_DMA_SHIFT_OG_SHIFT) +#define DPI_DMA_SHIFT_OB_SHIFT 25 +#define DPI_DMA_SHIFT_OB_MASK (0x1F << DPI_DMA_SHIFT_OB_SHIFT) + +// Scaling +#define DPI_DMA_RGBSZ 0x34 +#define DPI_DMA_RGBSZ_BPP_SHIFT 16 +#define DPI_DMA_RGBSZ_BPP_MASK (0x3 << DPI_DMA_RGBSZ_BPP_SHIFT) +#define DPI_DMA_RGBSZ_R_SHIFT 0 +#define DPI_DMA_RGBSZ_R_MASK (0xF << DPI_DMA_RGBSZ_R_SHIFT) +#define DPI_DMA_RGBSZ_G_SHIFT 4 +#define DPI_DMA_RGBSZ_G_MASK (0xF << DPI_DMA_RGBSZ_G_SHIFT) +#define DPI_DMA_RGBSZ_B_SHIFT 8 +#define DPI_DMA_RGBSZ_B_MASK (0xF << DPI_DMA_RGBSZ_B_SHIFT) + +// Status +#define DPI_DMA_STATUS 0x3c + +#define BITS(field, val) (((val) << (field ## _SHIFT)) & (field ## _MASK)) + +static unsigned int rp1dsi_dma_read(struct rp1_dsi *dsi, unsigned int reg) +{ + void __iomem *addr = dsi->hw_base[RP1DSI_HW_BLOCK_DMA] + reg; + + return readl(addr); +} + +static void rp1dsi_dma_write(struct rp1_dsi *dsi, unsigned int reg, unsigned int val) +{ + void __iomem *addr = dsi->hw_base[RP1DSI_HW_BLOCK_DMA] + reg; + + writel(val, addr); +} + +int rp1dsi_dma_busy(struct rp1_dsi *dsi) +{ + return (rp1dsi_dma_read(dsi, DPI_DMA_STATUS) & 0xF8F) ? 1 : 0; +} + +/* Table of supported input (in-memory/DMA) pixel formats. */ +struct rp1dsi_ipixfmt { + u32 format; /* DRM format code */ + u32 mask; /* RGB masks (10 bits each, left justified) */ + u32 shift; /* RGB MSB positions in the memory word */ + u32 rgbsz; /* Shifts used for scaling; also (BPP/8-1) */ +}; + +#define IMASK_RGB(r, g, b) (BITS(DPI_DMA_IMASK_R, r) | \ + BITS(DPI_DMA_IMASK_G, g) | \ + BITS(DPI_DMA_IMASK_B, b)) +#define ISHIFT_RGB(r, g, b) (BITS(DPI_DMA_SHIFT_IR, r) | \ + BITS(DPI_DMA_SHIFT_IG, g) | \ + BITS(DPI_DMA_SHIFT_IB, b)) + +static const struct rp1dsi_ipixfmt my_formats[] = { + { + .format = DRM_FORMAT_XRGB8888, + .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc), + .shift = ISHIFT_RGB(23, 15, 7), + .rgbsz = BITS(DPI_DMA_RGBSZ_BPP, 3), + }, + { + .format = DRM_FORMAT_XBGR8888, + .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc), + .shift = ISHIFT_RGB(7, 15, 23), + .rgbsz = BITS(DPI_DMA_RGBSZ_BPP, 3), + }, + { + .format = DRM_FORMAT_RGB888, + .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc), + .shift = ISHIFT_RGB(23, 15, 7), + .rgbsz = BITS(DPI_DMA_RGBSZ_BPP, 2), + }, + { + .format = DRM_FORMAT_BGR888, + .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc), + .shift = ISHIFT_RGB(7, 15, 23), + .rgbsz = BITS(DPI_DMA_RGBSZ_BPP, 2), + }, + { + .format = DRM_FORMAT_RGB565, + .mask = IMASK_RGB(0x3e0, 0x3f0, 0x3e0), + .shift = ISHIFT_RGB(15, 10, 4), + .rgbsz = BITS(DPI_DMA_RGBSZ_R, 5) | BITS(DPI_DMA_RGBSZ_G, 6) | + BITS(DPI_DMA_RGBSZ_B, 5) | BITS(DPI_DMA_RGBSZ_BPP, 1), + } +}; + +/* Choose the internal on-the-bus DPI format as expected by DSI Host. */ +static u32 get_omask_oshift(enum mipi_dsi_pixel_format fmt, u32 *oshift) +{ + switch (fmt) { + case MIPI_DSI_FMT_RGB565: + *oshift = BITS(DPI_DMA_SHIFT_OR, 15) | + BITS(DPI_DMA_SHIFT_OG, 10) | + BITS(DPI_DMA_SHIFT_OB, 4); + return BITS(DPI_DMA_OMASK_R, 0x3e0) | + BITS(DPI_DMA_OMASK_G, 0x3f0) | + BITS(DPI_DMA_OMASK_B, 0x3e0); + case MIPI_DSI_FMT_RGB666_PACKED: + *oshift = BITS(DPI_DMA_SHIFT_OR, 17) | + BITS(DPI_DMA_SHIFT_OG, 11) | + BITS(DPI_DMA_SHIFT_OB, 5); + return BITS(DPI_DMA_OMASK_R, 0x3f0) | + BITS(DPI_DMA_OMASK_G, 0x3f0) | + BITS(DPI_DMA_OMASK_B, 0x3f0); + case MIPI_DSI_FMT_RGB666: + *oshift = BITS(DPI_DMA_SHIFT_OR, 21) | + BITS(DPI_DMA_SHIFT_OG, 13) | + BITS(DPI_DMA_SHIFT_OB, 5); + return BITS(DPI_DMA_OMASK_R, 0x3f0) | + BITS(DPI_DMA_OMASK_G, 0x3f0) | + BITS(DPI_DMA_OMASK_B, 0x3f0); + default: + *oshift = BITS(DPI_DMA_SHIFT_OR, 23) | + BITS(DPI_DMA_SHIFT_OG, 15) | + BITS(DPI_DMA_SHIFT_OB, 7); + return BITS(DPI_DMA_OMASK_R, 0x3fc) | + BITS(DPI_DMA_OMASK_G, 0x3fc) | + BITS(DPI_DMA_OMASK_B, 0x3fc); + } +} + +void rp1dsi_dma_setup(struct rp1_dsi *dsi, + u32 in_format, enum mipi_dsi_pixel_format out_format, + struct drm_display_mode const *mode) +{ + u32 oshift; + int i; + + /* + * Configure all DSI/DPI/DMA block registers, except base address. + * DMA will not actually start until a FB base address is specified + * using rp1dsi_dma_update(). + */ + + rp1dsi_dma_write(dsi, DPI_DMA_VISIBLE_AREA, + BITS(DPI_DMA_VISIBLE_AREA_ROWSM1, mode->vdisplay - 1) | + BITS(DPI_DMA_VISIBLE_AREA_COLSM1, mode->hdisplay - 1)); + + rp1dsi_dma_write(dsi, DPI_DMA_SYNC_WIDTH, + BITS(DPI_DMA_SYNC_WIDTH_ROWSM1, mode->vsync_end - mode->vsync_start - 1) | + BITS(DPI_DMA_SYNC_WIDTH_COLSM1, mode->hsync_end - mode->hsync_start - 1)); + + /* In the DPIDMA registers, "back porch" time includes sync width */ + rp1dsi_dma_write(dsi, DPI_DMA_BACK_PORCH, + BITS(DPI_DMA_BACK_PORCH_ROWSM1, mode->vtotal - mode->vsync_start - 1) | + BITS(DPI_DMA_BACK_PORCH_COLSM1, mode->htotal - mode->hsync_start - 1)); + + rp1dsi_dma_write(dsi, DPI_DMA_FRONT_PORCH, + BITS(DPI_DMA_FRONT_PORCH_ROWSM1, mode->vsync_start - mode->vdisplay - 1) | + BITS(DPI_DMA_FRONT_PORCH_COLSM1, mode->hsync_start - mode->hdisplay - 1)); + + /* Input to output pixel format conversion */ + for (i = 0; i < ARRAY_SIZE(my_formats); ++i) { + if (my_formats[i].format == in_format) + break; + } + if (i >= ARRAY_SIZE(my_formats)) { + drm_err(dsi->drm, "%s: bad input format\n", __func__); + i = 0; + } + rp1dsi_dma_write(dsi, DPI_DMA_IMASK, my_formats[i].mask); + rp1dsi_dma_write(dsi, DPI_DMA_OMASK, get_omask_oshift(out_format, &oshift)); + rp1dsi_dma_write(dsi, DPI_DMA_SHIFT, my_formats[i].shift | oshift); + if (out_format == MIPI_DSI_FMT_RGB888) + rp1dsi_dma_write(dsi, DPI_DMA_RGBSZ, my_formats[i].rgbsz); + else + rp1dsi_dma_write(dsi, DPI_DMA_RGBSZ, my_formats[i].rgbsz & DPI_DMA_RGBSZ_BPP_MASK); + + rp1dsi_dma_write(dsi, DPI_DMA_QOS, + BITS(DPI_DMA_QOS_DQOS, 0x0) | + BITS(DPI_DMA_QOS_ULEV, 0xb) | + BITS(DPI_DMA_QOS_UQOS, 0x2) | + BITS(DPI_DMA_QOS_LLEV, 0x8) | + BITS(DPI_DMA_QOS_LQOS, 0x7)); + + rp1dsi_dma_write(dsi, DPI_DMA_IRQ_FLAGS, -1); + rp1dsi_dma_vblank_ctrl(dsi, 1); + + i = rp1dsi_dma_busy(dsi); + if (i) + drm_err(dsi->drm, "RP1DSI: Unexpectedly busy at start!"); + + rp1dsi_dma_write(dsi, DPI_DMA_CONTROL, + BITS(DPI_DMA_CONTROL_ARM, (i == 0)) | + BITS(DPI_DMA_CONTROL_AUTO_REPEAT, 1) | + BITS(DPI_DMA_CONTROL_HIGH_WATER, 448) | + BITS(DPI_DMA_CONTROL_DEN_POL, 0) | + BITS(DPI_DMA_CONTROL_HSYNC_POL, 0) | + BITS(DPI_DMA_CONTROL_VSYNC_POL, 0) | + BITS(DPI_DMA_CONTROL_COLORM, 0) | + BITS(DPI_DMA_CONTROL_SHUTDN, 0) | + BITS(DPI_DMA_CONTROL_HBP_EN, 1) | + BITS(DPI_DMA_CONTROL_HFP_EN, 1) | + BITS(DPI_DMA_CONTROL_VBP_EN, 1) | + BITS(DPI_DMA_CONTROL_VFP_EN, 1) | + BITS(DPI_DMA_CONTROL_HSYNC_EN, 1) | + BITS(DPI_DMA_CONTROL_VSYNC_EN, 1)); +} + +void rp1dsi_dma_update(struct rp1_dsi *dsi, dma_addr_t addr, u32 offset, u32 stride) +{ + /* + * Update STRIDE, DMAH and DMAL only. When called after rp1dsi_dma_setup(), + * DMA starts immediately; if already running, the buffer will flip at + * the next vertical sync event. + */ + u64 a = addr + offset; + + rp1dsi_dma_write(dsi, DPI_DMA_DMA_STRIDE, stride); + rp1dsi_dma_write(dsi, DPI_DMA_DMA_ADDR_H, a >> 32); + rp1dsi_dma_write(dsi, DPI_DMA_DMA_ADDR_L, a & 0xFFFFFFFFu); +} + +void rp1dsi_dma_stop(struct rp1_dsi *dsi) +{ + /* + * Stop DMA by turning off the Auto-Repeat flag, and wait up to 100ms for + * the current and any queued frame to end. "Force drain" flags are not used, + * as they seem to prevent DMA from re-starting properly; it's safer to wait. + */ + u32 ctrl; + + reinit_completion(&dsi->finished); + ctrl = rp1dsi_dma_read(dsi, DPI_DMA_CONTROL); + ctrl &= ~(DPI_DMA_CONTROL_ARM_MASK | DPI_DMA_CONTROL_AUTO_REPEAT_MASK); + rp1dsi_dma_write(dsi, DPI_DMA_CONTROL, ctrl); + if (!wait_for_completion_timeout(&dsi->finished, HZ / 10)) + drm_err(dsi->drm, "%s: timed out waiting for idle\n", __func__); + rp1dsi_dma_write(dsi, DPI_DMA_IRQ_EN, 0); +} + +void rp1dsi_dma_vblank_ctrl(struct rp1_dsi *dsi, int enable) +{ + rp1dsi_dma_write(dsi, DPI_DMA_IRQ_EN, + BITS(DPI_DMA_IRQ_EN_AFIFO_EMPTY, 1) | + BITS(DPI_DMA_IRQ_EN_UNDERFLOW, 1) | + BITS(DPI_DMA_IRQ_EN_DMA_READY, !!enable) | + BITS(DPI_DMA_IRQ_EN_MATCH_LINE, 4095)); +} + +irqreturn_t rp1dsi_dma_isr(int irq, void *dev) +{ + struct rp1_dsi *dsi = dev; + u32 u = rp1dsi_dma_read(dsi, DPI_DMA_IRQ_FLAGS); + + if (u) { + rp1dsi_dma_write(dsi, DPI_DMA_IRQ_FLAGS, u); + if (dsi) { + if (u & DPI_DMA_IRQ_FLAGS_UNDERFLOW_MASK) + drm_err_ratelimited(dsi->drm, + "Underflow! (panics=0x%08x)\n", + rp1dsi_dma_read(dsi, DPI_DMA_PANICS)); + if (u & DPI_DMA_IRQ_FLAGS_DMA_READY_MASK) + drm_crtc_handle_vblank(&dsi->pipe.crtc); + if (u & DPI_DMA_IRQ_FLAGS_AFIFO_EMPTY_MASK) + complete(&dsi->finished); + } + } + return u ? IRQ_HANDLED : IRQ_NONE; +} diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c linux/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c 2023-12-13 11:50:59.410986728 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DRM Driver for DSI output on Raspberry Pi RP1 + * + * Copyright (c) 2023 Raspberry Pi Limited. + */ + +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/platform_device.h> +#include <linux/rp1_platform.h> +#include "drm/drm_print.h" + +#include "rp1_dsi.h" + +/* ------------------------------- Synopsis DSI ------------------------ */ +#define DSI_VERSION_CFG 0x000 +#define DSI_PWR_UP 0x004 +#define DSI_CLKMGR_CFG 0x008 +#define DSI_DPI_VCID 0x00C +#define DSI_DPI_COLOR_CODING 0x010 +#define DSI_DPI_CFG_POL 0x014 +#define DSI_DPI_LP_CMD_TIM 0x018 +#define DSI_DBI_VCID 0x01C +#define DSI_DBI_CFG 0x020 +#define DSI_DBI_PARTITIONING_EN 0x024 +#define DSI_DBI_CMDSIZE 0x028 +#define DSI_PCKHDL_CFG 0x02C +#define DSI_GEN_VCID 0x030 +#define DSI_MODE_CFG 0x034 +#define DSI_VID_MODE_CFG 0x038 +#define DSI_VID_PKT_SIZE 0x03C +#define DSI_VID_NUM_CHUNKS 0x040 +#define DSI_VID_NULL_SIZE 0x044 +#define DSI_VID_HSA_TIME 0x048 +#define DSI_VID_HBP_TIME 0x04C +#define DSI_VID_HLINE_TIME 0x050 +#define DSI_VID_VSA_LINES 0x054 +#define DSI_VID_VBP_LINES 0x058 +#define DSI_VID_VFP_LINES 0x05C +#define DSI_VID_VACTIVE_LINES 0x060 +#define DSI_EDPI_CMD_SIZE 0x064 +#define DSI_CMD_MODE_CFG 0x068 +#define DSI_GEN_HDR 0x06C +#define DSI_GEN_PLD_DATA 0x070 +#define DSI_CMD_PKT_STATUS 0x074 +#define DSI_TO_CNT_CFG 0x078 +#define DSI_HS_RD_TO_CNT 0x07C +#define DSI_LP_RD_TO_CNT 0x080 +#define DSI_HS_WR_TO_CNT 0x084 +#define DSI_LP_WR_TO_CNT 0x088 +#define DSI_BTA_TO_CNT 0x08C +#define DSI_SDF_3D 0x090 +#define DSI_LPCLK_CTRL 0x094 +#define DSI_PHY_TMR_LPCLK_CFG 0x098 +#define DSI_PHY_TMR_HS2LP_LSB 16 +#define DSI_PHY_TMR_LP2HS_LSB 0 +#define DSI_PHY_TMR_CFG 0x09C +#define DSI_PHY_TMR_RD_CFG 0x0F4 +#define DSI_PHYRSTZ 0x0A0 +#define DSI_PHY_IF_CFG 0x0A4 +#define DSI_PHY_ULPS_CTRL 0x0A8 +#define DSI_PHY_TX_TRIGGERS 0x0AC +#define DSI_PHY_STATUS 0x0B0 + +#define DSI_PHY_TST_CTRL0 0x0B4 +#define DSI_PHY_TST_CTRL1 0x0B8 +#define DSI_INT_ST0 0x0BC +#define DSI_INT_ST1 0x0C0 +#define DSI_INT_MASK0_CFG 0x0C4 +#define DSI_INT_MASK1_CFG 0x0C8 +#define DSI_PHY_CAL 0x0CC +#define DSI_HEXP_NPKT_CLR 0x104 +#define DSI_HEXP_NPKT_SIZE 0x108 +#define DSI_VID_SHADOW_CTRL 0x100 + +#define DSI_DPI_VCID_ACT 0x10C +#define DSI_DPI_COLOR_CODING_ACT 0x110 +#define DSI_DPI_LP_CMD_TIM_ACT 0x118 +#define DSI_VID_MODE_CFG_ACT 0x138 +#define DSI_VID_PKT_SIZE_ACT 0x13C +#define DSI_VID_NUM_CHUNKS_ACT 0x140 +#define DSI_VID_NULL_SIZE_ACT 0x144 +#define DSI_VID_HSA_TIME_ACT 0x148 +#define DSI_VID_HBP_TIME_ACT 0x14C +#define DSI_VID_HLINE_TIME_ACT 0x150 +#define DSI_VID_VSA_LINES_ACT 0x154 +#define DSI_VID_VBP_LINES_ACT 0x158 +#define DSI_VID_VFP_LINES_ACT 0x15C +#define DSI_VID_VACTIVE_LINES_ACT 0x160 +#define DSI_SDF_3D_CFG_ACT 0x190 + +#define DSI_INT_FORCE0 0x0D8 +#define DSI_INT_FORCE1 0x0DC + +#define DSI_AUTO_ULPS_MODE 0x0E0 +#define DSI_AUTO_ULPS_ENTRY_DELAY 0x0E4 +#define DSI_AUTO_ULPS_WAKEUP_TIME 0x0E8 +#define DSI_EDPI_ADV_FEATURES 0x0EC + +#define DSI_DSC_PARAMETER 0x0F0 + +/* And some bitfield definitions */ + +#define DPHY_PWR_UP_SHUTDOWNZ_LSB 0 +#define DPHY_PWR_UP_SHUTDOWNZ_BITS BIT(DPHY_PWR_UP_SHUTDOWNZ_LSB) + +#define DPHY_CTRL0_PHY_TESTCLK_LSB 1 +#define DPHY_CTRL0_PHY_TESTCLK_BITS BIT(DPHY_CTRL0_PHY_TESTCLK_LSB) +#define DPHY_CTRL0_PHY_TESTCLR_LSB 0 +#define DPHY_CTRL0_PHY_TESTCLR_BITS BIT(DPHY_CTRL0_PHY_TESTCLR_LSB) + +#define DPHY_CTRL1_PHY_TESTDIN_LSB 0 +#define DPHY_CTRL1_PHY_TESTDIN_BITS (0xff << DPHY_CTRL1_PHY_TESTDIN_LSB) +#define DPHY_CTRL1_PHY_TESTDOUT_LSB 8 +#define DPHY_CTRL1_PHY_TESTDOUT_BITS (0xff << DPHY_CTRL1_PHY_TESTDOUT_LSB) +#define DPHY_CTRL1_PHY_TESTEN_LSB 16 +#define DPHY_CTRL1_PHY_TESTEN_BITS BIT(DPHY_CTRL1_PHY_TESTEN_LSB) + +#define DSI_PHYRSTZ_SHUTDOWNZ_LSB 0 +#define DSI_PHYRSTZ_SHUTDOWNZ_BITS BIT(DSI_PHYRSTZ_SHUTDOWNZ_LSB) +#define DSI_PHYRSTZ_RSTZ_LSB 1 +#define DSI_PHYRSTZ_RSTZ_BITS BIT(DSI_PHYRSTZ_RSTZ_LSB) +#define DSI_PHYRSTZ_ENABLECLK_LSB 2 +#define DSI_PHYRSTZ_ENABLECLK_BITS BIT(DSI_PHYRSTZ_ENABLECLK_LSB) +#define DSI_PHYRSTZ_FORCEPLL_LSB 3 +#define DSI_PHYRSTZ_FORCEPLL_BITS BIT(DSI_PHYRSTZ_FORCEPLL_LSB) + +#define DPHY_HS_RX_CTRL_LANE0_OFFSET 0x44 +#define DPHY_PLL_INPUT_DIV_OFFSET 0x17 +#define DPHY_PLL_LOOP_DIV_OFFSET 0x18 +#define DPHY_PLL_DIV_CTRL_OFFSET 0x19 + +#define DPHY_PLL_BIAS_OFFSET 0x10 +#define DPHY_PLL_BIAS_VCO_RANGE_LSB 3 +#define DPHY_PLL_BIAS_USE_PROGRAMMED_VCO_RANGE BIT(7) + +#define DPHY_PLL_CHARGE_PUMP_OFFSET 0x11 +#define DPHY_PLL_LPF_OFFSET 0x12 + +#define DSI_WRITE(reg, val) writel((val), dsi->hw_base[RP1DSI_HW_BLOCK_DSI] + (reg)) +#define DSI_READ(reg) readl(dsi->hw_base[RP1DSI_HW_BLOCK_DSI] + (reg)) + +// ================================================================================ +// Register block : RPI_MIPICFG +// Version : 1 +// Bus type : apb +// Description : Register block to control mipi DPHY +// ================================================================================ +#define RPI_MIPICFG_REGS_RWTYPE_MSB 13 +#define RPI_MIPICFG_REGS_RWTYPE_LSB 12 +// ================================================================================ +// Register : RPI_MIPICFG_CLK2FC +// JTAG access : synchronous +// Description : None +#define RPI_MIPICFG_CLK2FC_OFFSET 0x00000000 +#define RPI_MIPICFG_CLK2FC_BITS 0x00000007 +#define RPI_MIPICFG_CLK2FC_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_CLK2FC_SEL +// Description : select a clock to be sent to the frequency counter +// 7 = none +// 6 = none +// 5 = none +// 4 = rxbyteclkhs (187.5MHz) +// 3 = rxclkesc0 (20MHz) +// 2 = txbyteclkhs (187.5MHz) +// 1 = txclkesc (125MHz) +// 0 = none +#define RPI_MIPICFG_CLK2FC_SEL_RESET 0x0 +#define RPI_MIPICFG_CLK2FC_SEL_BITS 0x00000007 +#define RPI_MIPICFG_CLK2FC_SEL_MSB 2 +#define RPI_MIPICFG_CLK2FC_SEL_LSB 0 +#define RPI_MIPICFG_CLK2FC_SEL_ACCESS "RW" +// ================================================================================ +// Register : RPI_MIPICFG_CFG +// JTAG access : asynchronous +// Description : Top level configuration +#define RPI_MIPICFG_CFG_OFFSET 0x00000004 +#define RPI_MIPICFG_CFG_BITS 0x00000111 +#define RPI_MIPICFG_CFG_RESET 0x00000001 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_CFG_DPIUPDATE +// Description : Indicate the DSI block that the next frame will have a new video configuration +#define RPI_MIPICFG_CFG_DPIUPDATE_RESET 0x0 +#define RPI_MIPICFG_CFG_DPIUPDATE_BITS 0x00000100 +#define RPI_MIPICFG_CFG_DPIUPDATE_MSB 8 +#define RPI_MIPICFG_CFG_DPIUPDATE_LSB 8 +#define RPI_MIPICFG_CFG_DPIUPDATE_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_CFG_SEL_TE_EXT +// Description : Select the TE source: 1 - ext, 0 - int +#define RPI_MIPICFG_CFG_SEL_TE_EXT_RESET 0x0 +#define RPI_MIPICFG_CFG_SEL_TE_EXT_BITS 0x00000010 +#define RPI_MIPICFG_CFG_SEL_TE_EXT_MSB 4 +#define RPI_MIPICFG_CFG_SEL_TE_EXT_LSB 4 +#define RPI_MIPICFG_CFG_SEL_TE_EXT_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_CFG_SEL_CSI_DSI_N +// Description : Select PHY direction: input to CSI, output from DSI. CSI 1 DSI 0 +#define RPI_MIPICFG_CFG_SEL_CSI_DSI_N_RESET 0x1 +#define RPI_MIPICFG_CFG_SEL_CSI_DSI_N_BITS 0x00000001 +#define RPI_MIPICFG_CFG_SEL_CSI_DSI_N_MSB 0 +#define RPI_MIPICFG_CFG_SEL_CSI_DSI_N_LSB 0 +#define RPI_MIPICFG_CFG_SEL_CSI_DSI_N_ACCESS "RW" +// ================================================================================ +// Register : RPI_MIPICFG_TE +// JTAG access : synchronous +// Description : Tearing effect processing +#define RPI_MIPICFG_TE_OFFSET 0x00000008 +#define RPI_MIPICFG_TE_BITS 0x10ffffff +#define RPI_MIPICFG_TE_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_TE_ARM +// Description : Tearing effect arm +#define RPI_MIPICFG_TE_ARM_RESET 0x0 +#define RPI_MIPICFG_TE_ARM_BITS 0x10000000 +#define RPI_MIPICFG_TE_ARM_MSB 28 +#define RPI_MIPICFG_TE_ARM_LSB 28 +#define RPI_MIPICFG_TE_ARM_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_TE_HALT_CYC +// Description : When arm pulse has been seen, wait for te; then halt the dpi block +// for this many clk_dpi cycles +#define RPI_MIPICFG_TE_HALT_CYC_RESET 0x000000 +#define RPI_MIPICFG_TE_HALT_CYC_BITS 0x00ffffff +#define RPI_MIPICFG_TE_HALT_CYC_MSB 23 +#define RPI_MIPICFG_TE_HALT_CYC_LSB 0 +#define RPI_MIPICFG_TE_HALT_CYC_ACCESS "RW" +// ================================================================================ +// Register : RPI_MIPICFG_DPHY_MONITOR +// JTAG access : asynchronous +// Description : DPHY status monitors for analog DFT +#define RPI_MIPICFG_DPHY_MONITOR_OFFSET 0x00000010 +#define RPI_MIPICFG_DPHY_MONITOR_BITS 0x00111fff +#define RPI_MIPICFG_DPHY_MONITOR_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_MONITOR_LOCK +// Description : None +#define RPI_MIPICFG_DPHY_MONITOR_LOCK_RESET 0x0 +#define RPI_MIPICFG_DPHY_MONITOR_LOCK_BITS 0x00100000 +#define RPI_MIPICFG_DPHY_MONITOR_LOCK_MSB 20 +#define RPI_MIPICFG_DPHY_MONITOR_LOCK_LSB 20 +#define RPI_MIPICFG_DPHY_MONITOR_LOCK_ACCESS "RO" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_MONITOR_BISTOK +// Description : None +#define RPI_MIPICFG_DPHY_MONITOR_BISTOK_RESET 0x0 +#define RPI_MIPICFG_DPHY_MONITOR_BISTOK_BITS 0x00010000 +#define RPI_MIPICFG_DPHY_MONITOR_BISTOK_MSB 16 +#define RPI_MIPICFG_DPHY_MONITOR_BISTOK_LSB 16 +#define RPI_MIPICFG_DPHY_MONITOR_BISTOK_ACCESS "RO" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK +// Description : None +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK_RESET 0x0 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK_BITS 0x00001000 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK_MSB 12 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK_LSB 12 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK_ACCESS "RO" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA +// Description : None +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA_RESET 0x0 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA_BITS 0x00000f00 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA_MSB 11 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA_LSB 8 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA_ACCESS "RO" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_MONITOR_TESTDOUT +// Description : None +#define RPI_MIPICFG_DPHY_MONITOR_TESTDOUT_RESET 0x00 +#define RPI_MIPICFG_DPHY_MONITOR_TESTDOUT_BITS 0x000000ff +#define RPI_MIPICFG_DPHY_MONITOR_TESTDOUT_MSB 7 +#define RPI_MIPICFG_DPHY_MONITOR_TESTDOUT_LSB 0 +#define RPI_MIPICFG_DPHY_MONITOR_TESTDOUT_ACCESS "RO" +// ================================================================================ +// Register : RPI_MIPICFG_DPHY_CTRL_0 +// JTAG access : asynchronous +// Description : DPHY control for analog DFT +#define RPI_MIPICFG_DPHY_CTRL_0_OFFSET 0x00000014 +#define RPI_MIPICFG_DPHY_CTRL_0_BITS 0x0000003f +#define RPI_MIPICFG_DPHY_CTRL_0_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE +// Description : When set in lpmode, TXCLKESC is driven from clk_vec(driven from clocks block) +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE_BITS 0x00000020 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE_MSB 5 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE_LSB 5 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA +// Description : When set, drive the DPHY from the test registers +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA_BITS 0x00000010 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA_MSB 4 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA_LSB 4 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS +// Description : When test_ena is set, disable cfg_clk +#define RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS_BITS 0x00000008 +#define RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS_MSB 3 +#define RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS_LSB 3 +#define RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS +// Description : When test_ena is set, disable refclk +#define RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS_BITS 0x00000004 +#define RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS_MSB 2 +#define RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS_LSB 2 +#define RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS +// Description : When test_ena is set, disable txclkesc +#define RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS_BITS 0x00000002 +#define RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS_MSB 1 +#define RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS_LSB 1 +#define RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS +// Description : When test_ena is set, disable txbyteclkhs +#define RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS_BITS 0x00000001 +#define RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS_MSB 0 +#define RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS_LSB 0 +#define RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS_ACCESS "RW" +// ================================================================================ +// Register : RPI_MIPICFG_DPHY_CTRL_1 +// JTAG access : asynchronous +// Description : DPHY control for analog DFT +#define RPI_MIPICFG_DPHY_CTRL_1_OFFSET 0x00000018 +#define RPI_MIPICFG_DPHY_CTRL_1_BITS 0x7fffffff +#define RPI_MIPICFG_DPHY_CTRL_1_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL_BITS 0x40000000 +#define RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL_MSB 30 +#define RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL_LSB 30 +#define RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ_BITS 0x20000000 +#define RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ_MSB 29 +#define RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ_LSB 29 +#define RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_RSTZ +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_RSTZ_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_RSTZ_BITS 0x10000000 +#define RPI_MIPICFG_DPHY_CTRL_1_RSTZ_MSB 28 +#define RPI_MIPICFG_DPHY_CTRL_1_RSTZ_LSB 28 +#define RPI_MIPICFG_DPHY_CTRL_1_RSTZ_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ_BITS 0x08000000 +#define RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ_MSB 27 +#define RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ_LSB 27 +#define RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_BISTON +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_BISTON_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_BISTON_BITS 0x04000000 +#define RPI_MIPICFG_DPHY_CTRL_1_BISTON_MSB 26 +#define RPI_MIPICFG_DPHY_CTRL_1_BISTON_LSB 26 +#define RPI_MIPICFG_DPHY_CTRL_1_BISTON_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK_BITS 0x02000000 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK_MSB 25 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK_LSB 25 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK_BITS 0x01000000 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK_MSB 24 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK_LSB 24 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3_BITS 0x00800000 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3_MSB 23 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3_LSB 23 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2_BITS 0x00400000 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2_MSB 22 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2_LSB 22 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1_BITS 0x00200000 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1_MSB 21 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1_LSB 21 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0_BITS 0x00100000 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0_MSB 20 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0_LSB 20 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3_BITS 0x00080000 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3_MSB 19 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3_LSB 19 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2_BITS 0x00040000 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2_MSB 18 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2_LSB 18 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1_BITS 0x00020000 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1_MSB 17 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1_LSB 17 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0_BITS 0x00010000 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0_MSB 16 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0_LSB 16 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3_BITS 0x00008000 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3_MSB 15 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3_LSB 15 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2_BITS 0x00004000 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2_MSB 14 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2_LSB 14 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1_BITS 0x00002000 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1_MSB 13 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1_LSB 13 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0_BITS 0x00001000 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0_MSB 12 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0_LSB 12 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3_BITS 0x00000800 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3_MSB 11 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3_LSB 11 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2_BITS 0x00000400 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2_MSB 10 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2_LSB 10 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1_BITS 0x00000200 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1_MSB 9 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1_LSB 9 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0_BITS 0x00000100 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0_MSB 8 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0_LSB 8 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3_BITS 0x00000080 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3_MSB 7 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3_LSB 7 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2_BITS 0x00000040 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2_MSB 6 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2_LSB 6 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1_BITS 0x00000020 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1_MSB 5 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1_LSB 5 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0_BITS 0x00000010 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0_MSB 4 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0_LSB 4 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3_BITS 0x00000008 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3_MSB 3 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3_LSB 3 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2_BITS 0x00000004 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2_MSB 2 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2_LSB 2 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1_BITS 0x00000002 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1_MSB 1 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1_LSB 1 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0_BITS 0x00000001 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0_MSB 0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0_LSB 0 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0_ACCESS "RW" +// ================================================================================ +// Register : RPI_MIPICFG_DPHY_CTRL_2 +// JTAG access : asynchronous +// Description : DPHY control for analog DFT +#define RPI_MIPICFG_DPHY_CTRL_2_OFFSET 0x0000001c +#define RPI_MIPICFG_DPHY_CTRL_2_BITS 0x000007ff +#define RPI_MIPICFG_DPHY_CTRL_2_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_2_TESTCLK +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLK_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLK_BITS 0x00000400 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLK_MSB 10 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLK_LSB 10 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLK_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_2_TESTEN +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_2_TESTEN_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTEN_BITS 0x00000200 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTEN_MSB 9 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTEN_LSB 9 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTEN_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_2_TESTCLR +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLR_RESET 0x0 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLR_BITS 0x00000100 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLR_MSB 8 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLR_LSB 8 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLR_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_2_TESTDIN +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_2_TESTDIN_RESET 0x00 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTDIN_BITS 0x000000ff +#define RPI_MIPICFG_DPHY_CTRL_2_TESTDIN_MSB 7 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTDIN_LSB 0 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTDIN_ACCESS "RW" +// ================================================================================ +// Register : RPI_MIPICFG_DPHY_CTRL_3 +// JTAG access : asynchronous +// Description : DPHY control for analog DFT +#define RPI_MIPICFG_DPHY_CTRL_3_OFFSET 0x00000020 +#define RPI_MIPICFG_DPHY_CTRL_3_BITS 0xffffffff +#define RPI_MIPICFG_DPHY_CTRL_3_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3_RESET 0x00 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3_BITS 0xff000000 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3_MSB 31 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3_LSB 24 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2_RESET 0x00 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2_BITS 0x00ff0000 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2_MSB 23 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2_LSB 16 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1_RESET 0x00 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1_BITS 0x0000ff00 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1_MSB 15 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1_LSB 8 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0_RESET 0x00 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0_BITS 0x000000ff +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0_MSB 7 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0_LSB 0 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0_ACCESS "RW" +// ================================================================================ +// Register : RPI_MIPICFG_DPHY_CTRL_4 +// JTAG access : asynchronous +// Description : DPHY control for analog DFT +#define RPI_MIPICFG_DPHY_CTRL_4_OFFSET 0x00000024 +#define RPI_MIPICFG_DPHY_CTRL_4_BITS 0xffffffff +#define RPI_MIPICFG_DPHY_CTRL_4_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3_RESET 0x00 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3_BITS 0xff000000 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3_MSB 31 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3_LSB 24 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2_RESET 0x00 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2_BITS 0x00ff0000 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2_MSB 23 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2_LSB 16 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1_RESET 0x00 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1_BITS 0x0000ff00 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1_MSB 15 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1_LSB 8 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0 +// Description : None +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0_RESET 0x00 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0_BITS 0x000000ff +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0_MSB 7 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0_LSB 0 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0_ACCESS "RW" +// ================================================================================ +// Register : RPI_MIPICFG_INTR +// JTAG access : synchronous +// Description : Raw Interrupts +#define RPI_MIPICFG_INTR_OFFSET 0x00000028 +#define RPI_MIPICFG_INTR_BITS 0x0000000f +#define RPI_MIPICFG_INTR_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTR_DSI_HOST +// Description : None +#define RPI_MIPICFG_INTR_DSI_HOST_RESET 0x0 +#define RPI_MIPICFG_INTR_DSI_HOST_BITS 0x00000008 +#define RPI_MIPICFG_INTR_DSI_HOST_MSB 3 +#define RPI_MIPICFG_INTR_DSI_HOST_LSB 3 +#define RPI_MIPICFG_INTR_DSI_HOST_ACCESS "RO" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTR_CSI_HOST +// Description : None +#define RPI_MIPICFG_INTR_CSI_HOST_RESET 0x0 +#define RPI_MIPICFG_INTR_CSI_HOST_BITS 0x00000004 +#define RPI_MIPICFG_INTR_CSI_HOST_MSB 2 +#define RPI_MIPICFG_INTR_CSI_HOST_LSB 2 +#define RPI_MIPICFG_INTR_CSI_HOST_ACCESS "RO" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTR_DSI_DMA +// Description : None +#define RPI_MIPICFG_INTR_DSI_DMA_RESET 0x0 +#define RPI_MIPICFG_INTR_DSI_DMA_BITS 0x00000002 +#define RPI_MIPICFG_INTR_DSI_DMA_MSB 1 +#define RPI_MIPICFG_INTR_DSI_DMA_LSB 1 +#define RPI_MIPICFG_INTR_DSI_DMA_ACCESS "RO" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTR_CSI_DMA +// Description : None +#define RPI_MIPICFG_INTR_CSI_DMA_RESET 0x0 +#define RPI_MIPICFG_INTR_CSI_DMA_BITS 0x00000001 +#define RPI_MIPICFG_INTR_CSI_DMA_MSB 0 +#define RPI_MIPICFG_INTR_CSI_DMA_LSB 0 +#define RPI_MIPICFG_INTR_CSI_DMA_ACCESS "RO" +// ================================================================================ +// Register : RPI_MIPICFG_INTE +// JTAG access : synchronous +// Description : Interrupt Enable +#define RPI_MIPICFG_INTE_OFFSET 0x0000002c +#define RPI_MIPICFG_INTE_BITS 0x0000000f +#define RPI_MIPICFG_INTE_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTE_DSI_HOST +// Description : None +#define RPI_MIPICFG_INTE_DSI_HOST_RESET 0x0 +#define RPI_MIPICFG_INTE_DSI_HOST_BITS 0x00000008 +#define RPI_MIPICFG_INTE_DSI_HOST_MSB 3 +#define RPI_MIPICFG_INTE_DSI_HOST_LSB 3 +#define RPI_MIPICFG_INTE_DSI_HOST_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTE_CSI_HOST +// Description : None +#define RPI_MIPICFG_INTE_CSI_HOST_RESET 0x0 +#define RPI_MIPICFG_INTE_CSI_HOST_BITS 0x00000004 +#define RPI_MIPICFG_INTE_CSI_HOST_MSB 2 +#define RPI_MIPICFG_INTE_CSI_HOST_LSB 2 +#define RPI_MIPICFG_INTE_CSI_HOST_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTE_DSI_DMA +// Description : None +#define RPI_MIPICFG_INTE_DSI_DMA_RESET 0x0 +#define RPI_MIPICFG_INTE_DSI_DMA_BITS 0x00000002 +#define RPI_MIPICFG_INTE_DSI_DMA_MSB 1 +#define RPI_MIPICFG_INTE_DSI_DMA_LSB 1 +#define RPI_MIPICFG_INTE_DSI_DMA_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTE_CSI_DMA +// Description : None +#define RPI_MIPICFG_INTE_CSI_DMA_RESET 0x0 +#define RPI_MIPICFG_INTE_CSI_DMA_BITS 0x00000001 +#define RPI_MIPICFG_INTE_CSI_DMA_MSB 0 +#define RPI_MIPICFG_INTE_CSI_DMA_LSB 0 +#define RPI_MIPICFG_INTE_CSI_DMA_ACCESS "RW" +// ================================================================================ +// Register : RPI_MIPICFG_INTF +// JTAG access : synchronous +// Description : Interrupt Force +#define RPI_MIPICFG_INTF_OFFSET 0x00000030 +#define RPI_MIPICFG_INTF_BITS 0x0000000f +#define RPI_MIPICFG_INTF_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTF_DSI_HOST +// Description : None +#define RPI_MIPICFG_INTF_DSI_HOST_RESET 0x0 +#define RPI_MIPICFG_INTF_DSI_HOST_BITS 0x00000008 +#define RPI_MIPICFG_INTF_DSI_HOST_MSB 3 +#define RPI_MIPICFG_INTF_DSI_HOST_LSB 3 +#define RPI_MIPICFG_INTF_DSI_HOST_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTF_CSI_HOST +// Description : None +#define RPI_MIPICFG_INTF_CSI_HOST_RESET 0x0 +#define RPI_MIPICFG_INTF_CSI_HOST_BITS 0x00000004 +#define RPI_MIPICFG_INTF_CSI_HOST_MSB 2 +#define RPI_MIPICFG_INTF_CSI_HOST_LSB 2 +#define RPI_MIPICFG_INTF_CSI_HOST_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTF_DSI_DMA +// Description : None +#define RPI_MIPICFG_INTF_DSI_DMA_RESET 0x0 +#define RPI_MIPICFG_INTF_DSI_DMA_BITS 0x00000002 +#define RPI_MIPICFG_INTF_DSI_DMA_MSB 1 +#define RPI_MIPICFG_INTF_DSI_DMA_LSB 1 +#define RPI_MIPICFG_INTF_DSI_DMA_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTF_CSI_DMA +// Description : None +#define RPI_MIPICFG_INTF_CSI_DMA_RESET 0x0 +#define RPI_MIPICFG_INTF_CSI_DMA_BITS 0x00000001 +#define RPI_MIPICFG_INTF_CSI_DMA_MSB 0 +#define RPI_MIPICFG_INTF_CSI_DMA_LSB 0 +#define RPI_MIPICFG_INTF_CSI_DMA_ACCESS "RW" +// ================================================================================ +// Register : RPI_MIPICFG_INTS +// JTAG access : synchronous +// Description : Interrupt status after masking & forcing +#define RPI_MIPICFG_INTS_OFFSET 0x00000034 +#define RPI_MIPICFG_INTS_BITS 0x0000000f +#define RPI_MIPICFG_INTS_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTS_DSI_HOST +// Description : None +#define RPI_MIPICFG_INTS_DSI_HOST_RESET 0x0 +#define RPI_MIPICFG_INTS_DSI_HOST_BITS 0x00000008 +#define RPI_MIPICFG_INTS_DSI_HOST_MSB 3 +#define RPI_MIPICFG_INTS_DSI_HOST_LSB 3 +#define RPI_MIPICFG_INTS_DSI_HOST_ACCESS "RO" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTS_CSI_HOST +// Description : None +#define RPI_MIPICFG_INTS_CSI_HOST_RESET 0x0 +#define RPI_MIPICFG_INTS_CSI_HOST_BITS 0x00000004 +#define RPI_MIPICFG_INTS_CSI_HOST_MSB 2 +#define RPI_MIPICFG_INTS_CSI_HOST_LSB 2 +#define RPI_MIPICFG_INTS_CSI_HOST_ACCESS "RO" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTS_DSI_DMA +// Description : None +#define RPI_MIPICFG_INTS_DSI_DMA_RESET 0x0 +#define RPI_MIPICFG_INTS_DSI_DMA_BITS 0x00000002 +#define RPI_MIPICFG_INTS_DSI_DMA_MSB 1 +#define RPI_MIPICFG_INTS_DSI_DMA_LSB 1 +#define RPI_MIPICFG_INTS_DSI_DMA_ACCESS "RO" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_INTS_CSI_DMA +// Description : None +#define RPI_MIPICFG_INTS_CSI_DMA_RESET 0x0 +#define RPI_MIPICFG_INTS_CSI_DMA_BITS 0x00000001 +#define RPI_MIPICFG_INTS_CSI_DMA_MSB 0 +#define RPI_MIPICFG_INTS_CSI_DMA_LSB 0 +#define RPI_MIPICFG_INTS_CSI_DMA_ACCESS "RO" +// ================================================================================ +// Register : RPI_MIPICFG_BLOCK_ID +// JTAG access : asynchronous +// Description : Block Identifier +#define RPI_MIPICFG_BLOCK_ID_OFFSET 0x00000038 +#define RPI_MIPICFG_BLOCK_ID_BITS 0xffffffff +#define RPI_MIPICFG_BLOCK_ID_RESET 0x4d495049 +#define RPI_MIPICFG_BLOCK_ID_MSB 31 +#define RPI_MIPICFG_BLOCK_ID_LSB 0 +#define RPI_MIPICFG_BLOCK_ID_ACCESS "RO" +// ================================================================================ +// Register : RPI_MIPICFG_INSTANCE_ID +// JTAG access : asynchronous +// Description : Block Instance Identifier +#define RPI_MIPICFG_INSTANCE_ID_OFFSET 0x0000003c +#define RPI_MIPICFG_INSTANCE_ID_BITS 0x0000000f +#define RPI_MIPICFG_INSTANCE_ID_RESET 0x00000000 +#define RPI_MIPICFG_INSTANCE_ID_MSB 3 +#define RPI_MIPICFG_INSTANCE_ID_LSB 0 +#define RPI_MIPICFG_INSTANCE_ID_ACCESS "RO" +// ================================================================================ +// Register : RPI_MIPICFG_RSTSEQ_AUTO +// JTAG access : synchronous +// Description : None +#define RPI_MIPICFG_RSTSEQ_AUTO_OFFSET 0x00000040 +#define RPI_MIPICFG_RSTSEQ_AUTO_BITS 0x00000007 +#define RPI_MIPICFG_RSTSEQ_AUTO_RESET 0x00000007 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_RSTSEQ_AUTO_CSI +// Description : 1 = reset is controlled by the sequencer +// 0 = reset is controlled by rstseq_ctrl +#define RPI_MIPICFG_RSTSEQ_AUTO_CSI_RESET 0x1 +#define RPI_MIPICFG_RSTSEQ_AUTO_CSI_BITS 0x00000004 +#define RPI_MIPICFG_RSTSEQ_AUTO_CSI_MSB 2 +#define RPI_MIPICFG_RSTSEQ_AUTO_CSI_LSB 2 +#define RPI_MIPICFG_RSTSEQ_AUTO_CSI_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_RSTSEQ_AUTO_DPI +// Description : 1 = reset is controlled by the sequencer +// 0 = reset is controlled by rstseq_ctrl +#define RPI_MIPICFG_RSTSEQ_AUTO_DPI_RESET 0x1 +#define RPI_MIPICFG_RSTSEQ_AUTO_DPI_BITS 0x00000002 +#define RPI_MIPICFG_RSTSEQ_AUTO_DPI_MSB 1 +#define RPI_MIPICFG_RSTSEQ_AUTO_DPI_LSB 1 +#define RPI_MIPICFG_RSTSEQ_AUTO_DPI_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER +// Description : 1 = reset is controlled by the sequencer +// 0 = reset is controlled by rstseq_ctrl +#define RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER_RESET 0x1 +#define RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER_BITS 0x00000001 +#define RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER_MSB 0 +#define RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER_LSB 0 +#define RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER_ACCESS "RW" +// ================================================================================ +// Register : RPI_MIPICFG_RSTSEQ_PARALLEL +// JTAG access : synchronous +// Description : None +#define RPI_MIPICFG_RSTSEQ_PARALLEL_OFFSET 0x00000044 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_BITS 0x00000007 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_RESET 0x00000006 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_RSTSEQ_PARALLEL_CSI +// Description : Is this reset parallel (i.e. not part of the sequence) +#define RPI_MIPICFG_RSTSEQ_PARALLEL_CSI_RESET 0x1 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_CSI_BITS 0x00000004 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_CSI_MSB 2 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_CSI_LSB 2 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_CSI_ACCESS "RO" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_RSTSEQ_PARALLEL_DPI +// Description : Is this reset parallel (i.e. not part of the sequence) +#define RPI_MIPICFG_RSTSEQ_PARALLEL_DPI_RESET 0x1 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_DPI_BITS 0x00000002 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_DPI_MSB 1 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_DPI_LSB 1 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_DPI_ACCESS "RO" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER +// Description : Is this reset parallel (i.e. not part of the sequence) +#define RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER_RESET 0x0 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER_BITS 0x00000001 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER_MSB 0 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER_LSB 0 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER_ACCESS "RO" +// ================================================================================ +// Register : RPI_MIPICFG_RSTSEQ_CTRL +// JTAG access : synchronous +// Description : None +#define RPI_MIPICFG_RSTSEQ_CTRL_OFFSET 0x00000048 +#define RPI_MIPICFG_RSTSEQ_CTRL_BITS 0x00000007 +#define RPI_MIPICFG_RSTSEQ_CTRL_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_RSTSEQ_CTRL_CSI +// Description : 1 = keep the reset asserted +// 0 = keep the reset deasserted +// This is ignored if rstseq_auto=1 +#define RPI_MIPICFG_RSTSEQ_CTRL_CSI_RESET 0x0 +#define RPI_MIPICFG_RSTSEQ_CTRL_CSI_BITS 0x00000004 +#define RPI_MIPICFG_RSTSEQ_CTRL_CSI_MSB 2 +#define RPI_MIPICFG_RSTSEQ_CTRL_CSI_LSB 2 +#define RPI_MIPICFG_RSTSEQ_CTRL_CSI_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_RSTSEQ_CTRL_DPI +// Description : 1 = keep the reset asserted +// 0 = keep the reset deasserted +// This is ignored if rstseq_auto=1 +#define RPI_MIPICFG_RSTSEQ_CTRL_DPI_RESET 0x0 +#define RPI_MIPICFG_RSTSEQ_CTRL_DPI_BITS 0x00000002 +#define RPI_MIPICFG_RSTSEQ_CTRL_DPI_MSB 1 +#define RPI_MIPICFG_RSTSEQ_CTRL_DPI_LSB 1 +#define RPI_MIPICFG_RSTSEQ_CTRL_DPI_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER +// Description : 1 = keep the reset asserted +// 0 = keep the reset deasserted +// This is ignored if rstseq_auto=1 +#define RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER_RESET 0x0 +#define RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER_BITS 0x00000001 +#define RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER_MSB 0 +#define RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER_LSB 0 +#define RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER_ACCESS "RW" +// ================================================================================ +// Register : RPI_MIPICFG_RSTSEQ_TRIG +// JTAG access : synchronous +// Description : None +#define RPI_MIPICFG_RSTSEQ_TRIG_OFFSET 0x0000004c +#define RPI_MIPICFG_RSTSEQ_TRIG_BITS 0x00000007 +#define RPI_MIPICFG_RSTSEQ_TRIG_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_RSTSEQ_TRIG_CSI +// Description : Pulses the reset output +#define RPI_MIPICFG_RSTSEQ_TRIG_CSI_RESET 0x0 +#define RPI_MIPICFG_RSTSEQ_TRIG_CSI_BITS 0x00000004 +#define RPI_MIPICFG_RSTSEQ_TRIG_CSI_MSB 2 +#define RPI_MIPICFG_RSTSEQ_TRIG_CSI_LSB 2 +#define RPI_MIPICFG_RSTSEQ_TRIG_CSI_ACCESS "SC" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_RSTSEQ_TRIG_DPI +// Description : Pulses the reset output +#define RPI_MIPICFG_RSTSEQ_TRIG_DPI_RESET 0x0 +#define RPI_MIPICFG_RSTSEQ_TRIG_DPI_BITS 0x00000002 +#define RPI_MIPICFG_RSTSEQ_TRIG_DPI_MSB 1 +#define RPI_MIPICFG_RSTSEQ_TRIG_DPI_LSB 1 +#define RPI_MIPICFG_RSTSEQ_TRIG_DPI_ACCESS "SC" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER +// Description : Pulses the reset output +#define RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER_RESET 0x0 +#define RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER_BITS 0x00000001 +#define RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER_MSB 0 +#define RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER_LSB 0 +#define RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER_ACCESS "SC" +// ================================================================================ +// Register : RPI_MIPICFG_RSTSEQ_DONE +// JTAG access : synchronous +// Description : None +#define RPI_MIPICFG_RSTSEQ_DONE_OFFSET 0x00000050 +#define RPI_MIPICFG_RSTSEQ_DONE_BITS 0x00000007 +#define RPI_MIPICFG_RSTSEQ_DONE_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_RSTSEQ_DONE_CSI +// Description : Indicates the current state of the reset +#define RPI_MIPICFG_RSTSEQ_DONE_CSI_RESET 0x0 +#define RPI_MIPICFG_RSTSEQ_DONE_CSI_BITS 0x00000004 +#define RPI_MIPICFG_RSTSEQ_DONE_CSI_MSB 2 +#define RPI_MIPICFG_RSTSEQ_DONE_CSI_LSB 2 +#define RPI_MIPICFG_RSTSEQ_DONE_CSI_ACCESS "RO" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_RSTSEQ_DONE_DPI +// Description : Indicates the current state of the reset +#define RPI_MIPICFG_RSTSEQ_DONE_DPI_RESET 0x0 +#define RPI_MIPICFG_RSTSEQ_DONE_DPI_BITS 0x00000002 +#define RPI_MIPICFG_RSTSEQ_DONE_DPI_MSB 1 +#define RPI_MIPICFG_RSTSEQ_DONE_DPI_LSB 1 +#define RPI_MIPICFG_RSTSEQ_DONE_DPI_ACCESS "RO" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER +// Description : Indicates the current state of the reset +#define RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER_RESET 0x0 +#define RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER_BITS 0x00000001 +#define RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER_MSB 0 +#define RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER_LSB 0 +#define RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER_ACCESS "RO" +// ================================================================================ +// Register : RPI_MIPICFG_DFTSS +// JTAG access : asynchronous +// Description : None +#define RPI_MIPICFG_DFTSS_OFFSET 0x00000054 +#define RPI_MIPICFG_DFTSS_BITS 0x0000001f +#define RPI_MIPICFG_DFTSS_RESET 0x00000000 +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DFTSS_JTAG_COPY +// Description : None +#define RPI_MIPICFG_DFTSS_JTAG_COPY_RESET 0x0 +#define RPI_MIPICFG_DFTSS_JTAG_COPY_BITS 0x00000010 +#define RPI_MIPICFG_DFTSS_JTAG_COPY_MSB 4 +#define RPI_MIPICFG_DFTSS_JTAG_COPY_LSB 4 +#define RPI_MIPICFG_DFTSS_JTAG_COPY_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY +// Description : None +#define RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY_RESET 0x0 +#define RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY_BITS 0x00000008 +#define RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY_MSB 3 +#define RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY_LSB 3 +#define RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS +// Description : None +#define RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS_RESET 0x0 +#define RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS_BITS 0x00000004 +#define RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS_MSB 2 +#define RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS_LSB 2 +#define RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DFTSS_BYPASS_INSYNCS +// Description : None +#define RPI_MIPICFG_DFTSS_BYPASS_INSYNCS_RESET 0x0 +#define RPI_MIPICFG_DFTSS_BYPASS_INSYNCS_BITS 0x00000002 +#define RPI_MIPICFG_DFTSS_BYPASS_INSYNCS_MSB 1 +#define RPI_MIPICFG_DFTSS_BYPASS_INSYNCS_LSB 1 +#define RPI_MIPICFG_DFTSS_BYPASS_INSYNCS_ACCESS "RW" +// -------------------------------------------------------------------------------- +// Field : RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS +// Description : None +#define RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS_RESET 0x0 +#define RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS_BITS 0x00000001 +#define RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS_MSB 0 +#define RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS_LSB 0 +#define RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS_ACCESS "RW" + +#define CFG_WRITE(reg, val) writel((val), dsi->hw_base[RP1DSI_HW_BLOCK_CFG] + (reg ## _OFFSET)) +#define CFG_READ(reg) readl(dsi->hw_base[RP1DSI_HW_BLOCK_CFG] + (reg ## _OFFSET)) + +/* ------------------------------- DPHY setup stuff ------------------------ */ + +static void dphy_transaction(struct rp1_dsi *dsi, uint8_t test_code, uint8_t test_data) +{ + /* + * See pg 101 of mipi dphy bidir databook + * Assume we start with testclk high. + * Each APB write takes at least 10ns and we ignore TESTDOUT + * so there is no need for extra delays between the transitions. + */ + u32 tmp; + + DSI_WRITE(DSI_PHY_TST_CTRL1, test_code | DPHY_CTRL1_PHY_TESTEN_BITS); + DSI_WRITE(DSI_PHY_TST_CTRL0, 0); + tmp = (DSI_READ(DSI_PHY_TST_CTRL1) >> DPHY_CTRL1_PHY_TESTDOUT_LSB) & 0xFF; + DSI_WRITE(DSI_PHY_TST_CTRL1, test_data); + DSI_WRITE(DSI_PHY_TST_CTRL0, DPHY_CTRL0_PHY_TESTCLK_BITS); +} + +static uint8_t dphy_get_div(u32 refclk_khz, u32 vco_freq_khz, u32 *ptr_m, u32 *ptr_n) +{ + /* + * See pg 77-78 of dphy databook + * fvco = m/n * refclk + * with the limit + * 40MHz >= fREFCLK / N >= 5MHz + * M (multiplier) must be an even number between 2 and 300 + * N (input divider) must be an integer between 1 and 100 + * + * In practice, given a 50MHz reference clock, it can produce any + * multiple of 10MHz, 11.1111MHz, 12.5MHz, 14.286MHz or 16.667MHz + * with < 1% error for all frequencies above 495MHz. + */ + + static const u32 REF_DIVN_MAX = 40000u; + static const u32 REF_DIVN_MIN = 5000u; + u32 best_n, best_m, best_err = 0x7fffffff; + unsigned int n; + + for (n = 1 + refclk_khz / REF_DIVN_MAX; n * REF_DIVN_MIN <= refclk_khz && n < 100; ++n) { + u32 half_m = (n * vco_freq_khz + refclk_khz) / (2 * refclk_khz); + + if (half_m < 150) { + u32 f = (2 * half_m * refclk_khz) / n; + u32 err = (f > vco_freq_khz) ? f - vco_freq_khz : vco_freq_khz - f; + + if (err < best_err) { + best_n = n; + best_m = 2 * half_m; + best_err = err; + if (err == 0) + break; + } + } + } + + if (64 * best_err < vco_freq_khz) { /* tolerate small error */ + *ptr_n = best_n; + *ptr_m = best_m; + return 1; + } + return 0; +} + +struct hsfreq_range { + u16 mhz_max; + u8 hsfreqrange; + u8 clk_lp2hs; + u8 clk_hs2lp; + u8 data_lp2hs; /* excluding clk lane entry */ + u8 data_hs2lp; +}; + +/* See Table A-3 on page 258 of dphy databook */ +static const struct hsfreq_range hsfreq_table[] = { + { 89, 0b000000, 32, 20, 26, 13 }, + { 99, 0b010000, 35, 23, 28, 14 }, + { 109, 0b100000, 32, 22, 26, 13 }, + { 129, 0b000001, 31, 20, 27, 13 }, + { 139, 0b010001, 33, 22, 26, 14 }, + { 149, 0b100001, 33, 21, 26, 14 }, + { 169, 0b000010, 32, 20, 27, 13 }, + { 179, 0b010010, 36, 23, 30, 15 }, + { 199, 0b100010, 40, 22, 33, 15 }, + { 219, 0b000011, 40, 22, 33, 15 }, + { 239, 0b010011, 44, 24, 36, 16 }, + { 249, 0b100011, 48, 24, 38, 17 }, + { 269, 0b000100, 48, 24, 38, 17 }, + { 299, 0b010100, 50, 27, 41, 18 }, + { 329, 0b000101, 56, 28, 45, 18 }, + { 359, 0b010101, 59, 28, 48, 19 }, + { 399, 0b100101, 61, 30, 50, 20 }, + { 449, 0b000110, 67, 31, 55, 21 }, + { 499, 0b010110, 73, 31, 59, 22 }, + { 549, 0b000111, 79, 36, 63, 24 }, + { 599, 0b010111, 83, 37, 68, 25 }, + { 649, 0b001000, 90, 38, 73, 27 }, + { 699, 0b011000, 95, 40, 77, 28 }, + { 749, 0b001001, 102, 40, 84, 28 }, + { 799, 0b011001, 106, 42, 87, 30 }, + { 849, 0b101001, 113, 44, 93, 31 }, + { 899, 0b111001, 118, 47, 98, 32 }, + { 949, 0b001010, 124, 47, 102, 34 }, + { 999, 0b011010, 130, 49, 107, 35 }, + { 1049, 0b101010, 135, 51, 111, 37 }, + { 1099, 0b111010, 139, 51, 114, 38 }, + { 1149, 0b001011, 146, 54, 120, 40 }, + { 1199, 0b011011, 153, 57, 125, 41 }, + { 1249, 0b101011, 158, 58, 130, 42 }, + { 1299, 0b111011, 163, 58, 135, 44 }, + { 1349, 0b001100, 168, 60, 140, 45 }, + { 1399, 0b011100, 172, 64, 144, 47 }, + { 1449, 0b101100, 176, 65, 148, 48 }, + { 1500, 0b111100, 181, 66, 153, 50 }, +}; + +static void dphy_set_hsfreqrange(struct rp1_dsi *dsi, u32 freq_mhz) +{ + unsigned int i; + + if (freq_mhz < 80 || freq_mhz > 1500) + drm_err(dsi->drm, "DPHY: Frequency %u MHz out of range\n", + freq_mhz); + + for (i = 0; i < ARRAY_SIZE(hsfreq_table) - 1; i++) { + if (freq_mhz <= hsfreq_table[i].mhz_max) + break; + } + + dsi->hsfreq_index = i; + dphy_transaction(dsi, DPHY_HS_RX_CTRL_LANE0_OFFSET, + hsfreq_table[i].hsfreqrange << 1); +} + +static void dphy_configure_pll(struct rp1_dsi *dsi, u32 refclk_khz, u32 vco_freq_khz) +{ + u32 m = 0; + u32 n = 0; + + if (dphy_get_div(refclk_khz, vco_freq_khz, &m, &n)) { + dphy_set_hsfreqrange(dsi, vco_freq_khz / 1000); + /* Program m,n from registers */ + dphy_transaction(dsi, DPHY_PLL_DIV_CTRL_OFFSET, 0x30); + /* N (program N-1) */ + dphy_transaction(dsi, DPHY_PLL_INPUT_DIV_OFFSET, n - 1); + /* M[8:5] ?? */ + dphy_transaction(dsi, DPHY_PLL_LOOP_DIV_OFFSET, 0x80 | ((m - 1) >> 5)); + /* M[4:0] (program M-1) */ + dphy_transaction(dsi, DPHY_PLL_LOOP_DIV_OFFSET, ((m - 1) & 0x1F)); + drm_dbg_driver(dsi->drm, + "DPHY: vco freq want %dkHz got %dkHz = %d * (%dkHz / %d), hsfreqrange = 0x%02x\r\n", + vco_freq_khz, refclk_khz * m / n, m, refclk_khz, + n, hsfreq_table[dsi->hsfreq_index].hsfreqrange); + } else { + drm_info(dsi->drm, + "rp1dsi: Error configuring DPHY PLL! %dkHz = %d * (%dkHz / %d)\r\n", + vco_freq_khz, m, refclk_khz, n); + } +} + +static void dphy_init_khz(struct rp1_dsi *dsi, u32 ref_freq, u32 vco_freq) +{ + /* Reset the PHY */ + DSI_WRITE(DSI_PHYRSTZ, 0); + DSI_WRITE(DSI_PHY_TST_CTRL0, DPHY_CTRL0_PHY_TESTCLK_BITS); + DSI_WRITE(DSI_PHY_TST_CTRL1, 0); + DSI_WRITE(DSI_PHY_TST_CTRL0, (DPHY_CTRL0_PHY_TESTCLK_BITS | DPHY_CTRL0_PHY_TESTCLR_BITS)); + udelay(1); + DSI_WRITE(DSI_PHY_TST_CTRL0, DPHY_CTRL0_PHY_TESTCLK_BITS); + udelay(1); + /* Since we are in DSI (not CSI2) mode here, start the PLL */ + dphy_configure_pll(dsi, ref_freq, vco_freq); + udelay(1); + /* Unreset */ + DSI_WRITE(DSI_PHYRSTZ, DSI_PHYRSTZ_SHUTDOWNZ_BITS); + udelay(1); + DSI_WRITE(DSI_PHYRSTZ, (DSI_PHYRSTZ_SHUTDOWNZ_BITS | DSI_PHYRSTZ_RSTZ_BITS)); + udelay(1); /* so we can see PLL coming up? */ +} + +void rp1dsi_mipicfg_setup(struct rp1_dsi *dsi) +{ + /* Select DSI rather than CSI-2 */ + CFG_WRITE(RPI_MIPICFG_CFG, 0); + /* Enable DSIDMA interrupt only */ + CFG_WRITE(RPI_MIPICFG_INTE, RPI_MIPICFG_INTE_DSI_DMA_BITS); +} + +static unsigned long rp1dsi_refclk_freq(struct rp1_dsi *dsi) +{ + unsigned long u; + + u = (dsi->clocks[RP1DSI_CLOCK_REF]) ? clk_get_rate(dsi->clocks[RP1DSI_CLOCK_REF]) : 0; + if (u < 1 || u >= (1ul << 30)) + u = 50000000ul; /* default XOSC frequency */ + return u; +} + +static void rp1dsi_dpiclk_start(struct rp1_dsi *dsi, unsigned int bpp, unsigned int lanes) +{ + unsigned long u; + + if (dsi->clocks[RP1DSI_CLOCK_DPI]) { + u = (dsi->clocks[RP1DSI_CLOCK_BYTE]) ? + clk_get_rate(dsi->clocks[RP1DSI_CLOCK_BYTE]) : 0; + drm_info(dsi->drm, + "rp1dsi: Nominal byte clock %lu; scale by %u/%u", + u, 4 * lanes, (bpp >> 1)); + if (u < 1 || u >= (1ul << 28)) + u = 72000000ul; /* default DUMMY frequency for byteclock */ + + clk_set_parent(dsi->clocks[RP1DSI_CLOCK_DPI], dsi->clocks[RP1DSI_CLOCK_BYTE]); + clk_set_rate(dsi->clocks[RP1DSI_CLOCK_DPI], (4 * lanes * u) / (bpp >> 1)); + clk_prepare_enable(dsi->clocks[RP1DSI_CLOCK_DPI]); + } +} + +static void rp1dsi_dpiclk_stop(struct rp1_dsi *dsi) +{ + if (dsi->clocks[RP1DSI_CLOCK_DPI]) + clk_disable_unprepare(dsi->clocks[RP1DSI_CLOCK_DPI]); +} + +/* Choose the internal on-the-bus DPI format, and DSI packing flag. */ +static u32 get_colorcode(enum mipi_dsi_pixel_format fmt) +{ + switch (fmt) { + case MIPI_DSI_FMT_RGB666: + return 0x104; + case MIPI_DSI_FMT_RGB666_PACKED: + return 0x003; + case MIPI_DSI_FMT_RGB565: + return 0x000; + case MIPI_DSI_FMT_RGB888: + return 0x005; + } + + /* This should be impossible as the format is validated in + * rp1dsi_host_attach + */ + WARN_ONCE(1, "Invalid colour format configured for DSI"); + return 0x005; +} + +void rp1dsi_dsi_setup(struct rp1_dsi *dsi, struct drm_display_mode const *mode) +{ + u32 timeout, mask, vid_mode_cfg; + u32 freq_khz; + unsigned int bpp = mipi_dsi_pixel_format_to_bpp(dsi->display_format); + + DSI_WRITE(DSI_PHY_IF_CFG, dsi->lanes - 1); + DSI_WRITE(DSI_DPI_CFG_POL, 0); + DSI_WRITE(DSI_GEN_VCID, dsi->vc); + DSI_WRITE(DSI_DPI_COLOR_CODING, get_colorcode(dsi->display_format)); + /* a conservative guess (LP escape is slow!) */ + DSI_WRITE(DSI_DPI_LP_CMD_TIM, 0x00100000); + + /* Drop to LP where possible */ + vid_mode_cfg = 0xbf00; + if (!(dsi->display_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) + vid_mode_cfg |= 0x01; + if (dsi->display_flags & MIPI_DSI_MODE_VIDEO_BURST) + vid_mode_cfg |= 0x02; + DSI_WRITE(DSI_VID_MODE_CFG, vid_mode_cfg); + + /* Use LP Escape Data signalling for all commands */ + DSI_WRITE(DSI_CMD_MODE_CFG, 0x10F7F00); + /* Select Command Mode */ + DSI_WRITE(DSI_MODE_CFG, 1); + /* XXX magic number */ + DSI_WRITE(DSI_TO_CNT_CFG, 0x02000200); + /* XXX magic number */ + DSI_WRITE(DSI_BTA_TO_CNT, 0x800); + + DSI_WRITE(DSI_VID_PKT_SIZE, mode->hdisplay); + DSI_WRITE(DSI_VID_NUM_CHUNKS, 0); + DSI_WRITE(DSI_VID_NULL_SIZE, 0); + + /* Note, unlike Argon firmware, here we DON'T consider sync to be concurrent with porch */ + DSI_WRITE(DSI_VID_HSA_TIME, + (bpp * (mode->hsync_end - mode->hsync_start)) / (8 * dsi->lanes)); + DSI_WRITE(DSI_VID_HBP_TIME, + (bpp * (mode->htotal - mode->hsync_end)) / (8 * dsi->lanes)); + DSI_WRITE(DSI_VID_HLINE_TIME, (bpp * mode->htotal) / (8 * dsi->lanes)); + DSI_WRITE(DSI_VID_VSA_LINES, (mode->vsync_end - mode->vsync_start)); + DSI_WRITE(DSI_VID_VBP_LINES, (mode->vtotal - mode->vsync_end)); + DSI_WRITE(DSI_VID_VFP_LINES, (mode->vsync_start - mode->vdisplay)); + DSI_WRITE(DSI_VID_VACTIVE_LINES, mode->vdisplay); + + freq_khz = (bpp * mode->clock) / dsi->lanes; + + dphy_init_khz(dsi, rp1dsi_refclk_freq(dsi) / 1000, freq_khz); + + DSI_WRITE(DSI_PHY_TMR_LPCLK_CFG, + (hsfreq_table[dsi->hsfreq_index].clk_lp2hs << DSI_PHY_TMR_LP2HS_LSB) | + (hsfreq_table[dsi->hsfreq_index].clk_hs2lp << DSI_PHY_TMR_HS2LP_LSB)); + DSI_WRITE(DSI_PHY_TMR_CFG, + (hsfreq_table[dsi->hsfreq_index].data_lp2hs << DSI_PHY_TMR_LP2HS_LSB) | + (hsfreq_table[dsi->hsfreq_index].data_hs2lp << DSI_PHY_TMR_HS2LP_LSB)); + + DSI_WRITE(DSI_CLKMGR_CFG, 0x00000505); + + /* Wait for PLL lock */ + for (timeout = (1 << 14); timeout != 0; --timeout) { + usleep_range(10, 50); + if (DSI_READ(DSI_PHY_STATUS) & (1 << 0)) + break; + } + if (timeout == 0) + drm_err(dsi->drm, "RP1DSI: Time out waiting for PLL\n"); + + DSI_WRITE(DSI_LPCLK_CTRL, 0x1); /* configure the requesthsclk */ + DSI_WRITE(DSI_PHY_TST_CTRL0, 0x2); + DSI_WRITE(DSI_PCKHDL_CFG, 1 << 2); /* allow bus turnaround */ + DSI_WRITE(DSI_PWR_UP, 0x1); /* power up */ + + /* Now it should be safe to start the external DPI clock divider */ + rp1dsi_dpiclk_start(dsi, bpp, dsi->lanes); + + /* Wait for all lane(s) to be in Stopstate */ + mask = (1 << 4); + if (dsi->lanes >= 2) + mask |= (1 << 7); + if (dsi->lanes >= 3) + mask |= (1 << 9); + if (dsi->lanes >= 4) + mask |= (1 << 11); + for (timeout = (1 << 10); timeout != 0; --timeout) { + usleep_range(10, 50); + if ((DSI_READ(DSI_PHY_STATUS) & mask) == mask) + break; + } + if (timeout == 0) + drm_err(dsi->drm, "RP1DSI: Time out waiting for lanes (%x %x)\n", + mask, DSI_READ(DSI_PHY_STATUS)); +} + +void rp1dsi_dsi_send(struct rp1_dsi *dsi, u32 hdr, int len, const u8 *buf) +{ + u32 val; + + /* Wait for both FIFOs empty */ + for (val = 256; val > 0; --val) { + if ((DSI_READ(DSI_CMD_PKT_STATUS) & 0xF) == 0x5) + break; + usleep_range(100, 150); + } + + /* Write payload (in 32-bit words) and header */ + for (; len > 0; len -= 4) { + val = *buf++; + if (len > 1) + val |= (*buf++) << 8; + if (len > 2) + val |= (*buf++) << 16; + if (len > 3) + val |= (*buf++) << 24; + DSI_WRITE(DSI_GEN_PLD_DATA, val); + } + DSI_WRITE(DSI_GEN_HDR, hdr); + + /* Wait for both FIFOs empty */ + for (val = 256; val > 0; --val) { + if ((DSI_READ(DSI_CMD_PKT_STATUS) & 0xF) == 0x5) + break; + usleep_range(100, 150); + } +} + +int rp1dsi_dsi_recv(struct rp1_dsi *dsi, int len, u8 *buf) +{ + int i, j; + u32 val; + + /* Wait until not busy and FIFO not empty */ + for (i = 1024; i > 0; --i) { + val = DSI_READ(DSI_CMD_PKT_STATUS); + if ((val & ((1 << 6) | (1 << 4))) == 0) + break; + usleep_range(100, 150); + } + if (i == 0) + return -EIO; + + for (i = 0; i < len; i += 4) { + /* Read fifo must not be empty before all bytes are read */ + if (DSI_READ(DSI_CMD_PKT_STATUS) & (1 << 4)) + break; + + val = DSI_READ(DSI_GEN_PLD_DATA); + for (j = 0; j < 4 && j + i < len; j++) + *buf++ = val >> (8 * j); + } + + return (i >= len) ? len : (i > 0) ? i : -EIO; +} + +void rp1dsi_dsi_stop(struct rp1_dsi *dsi) +{ + DSI_WRITE(DSI_MODE_CFG, 1); /* Return to Command Mode */ + DSI_WRITE(DSI_LPCLK_CTRL, 2); /* Stop the HS clock */ + DSI_WRITE(DSI_PWR_UP, 0x0); /* Power down host controller */ + DSI_WRITE(DSI_PHYRSTZ, 0); /* PHY into reset. */ + rp1dsi_dpiclk_stop(dsi); +} + +void rp1dsi_dsi_set_cmdmode(struct rp1_dsi *dsi, int mode) +{ + DSI_WRITE(DSI_MODE_CFG, mode); +} diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.h linux/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.h --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.h 2023-12-13 11:50:59.408986724 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * DRM Driver for DSI output on Raspberry Pi RP1 + * + * Copyright (c) 2023 Raspberry Pi Limited. + */ +#ifndef _RP1_DSI_H_ +#define _RP1_DSI_H_ + +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/types.h> + +#include <drm/drm_bridge.h> +#include <drm/drm_device.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_simple_kms_helper.h> + +#define MODULE_NAME "drm-rp1-dsi" +#define DRIVER_NAME "drm-rp1-dsi" + +/* ---------------------------------------------------------------------- */ + +#define RP1DSI_HW_BLOCK_DMA 0 +#define RP1DSI_HW_BLOCK_DSI 1 +#define RP1DSI_HW_BLOCK_CFG 2 +#define RP1DSI_NUM_HW_BLOCKS 3 + +#define RP1DSI_CLOCK_CFG 0 +#define RP1DSI_CLOCK_DPI 1 +#define RP1DSI_CLOCK_BYTE 2 +#define RP1DSI_CLOCK_REF 3 +#define RP1DSI_NUM_CLOCKS 4 + +/* ---------------------------------------------------------------------- */ + +struct rp1_dsi { + /* DRM and platform device pointers */ + struct drm_device *drm; + struct platform_device *pdev; + + /* Framework and helper objects */ + struct drm_simple_display_pipe pipe; + struct drm_bridge bridge; + struct drm_bridge *out_bridge; + struct mipi_dsi_host dsi_host; + + /* Clocks. We need DPI clock; the others are frequency references */ + struct clk *clocks[RP1DSI_NUM_CLOCKS]; + + /* Block (DSI DMA, DSI Host) base addresses, and current state */ + void __iomem *hw_base[RP1DSI_NUM_HW_BLOCKS]; + u32 cur_fmt; + bool dsi_running, dma_running, pipe_enabled; + struct completion finished; + + /* Attached display parameters (from mipi_dsi_device) */ + unsigned long display_flags, display_hs_rate, display_lp_rate; + enum mipi_dsi_pixel_format display_format; + u8 vc; + u8 lanes; + + /* DPHY */ + u8 hsfreq_index; +}; + +/* ---------------------------------------------------------------------- */ +/* Functions to control the DSI/DPI/DMA block */ + +void rp1dsi_dma_setup(struct rp1_dsi *dsi, + u32 in_format, enum mipi_dsi_pixel_format out_format, + struct drm_display_mode const *mode); +void rp1dsi_dma_update(struct rp1_dsi *dsi, dma_addr_t addr, u32 offset, u32 stride); +void rp1dsi_dma_stop(struct rp1_dsi *dsi); +int rp1dsi_dma_busy(struct rp1_dsi *dsi); +irqreturn_t rp1dsi_dma_isr(int irq, void *dev); +void rp1dsi_dma_vblank_ctrl(struct rp1_dsi *dsi, int enable); + +/* ---------------------------------------------------------------------- */ +/* Functions to control the MIPICFG block and check RP1 platform */ + +void rp1dsi_mipicfg_setup(struct rp1_dsi *dsi); + +/* ---------------------------------------------------------------------- */ +/* Functions to control the SNPS D-PHY and DSI block setup */ + +void rp1dsi_dsi_setup(struct rp1_dsi *dsi, struct drm_display_mode const *mode); +void rp1dsi_dsi_send(struct rp1_dsi *dsi, u32 header, int len, const u8 *buf); +int rp1dsi_dsi_recv(struct rp1_dsi *dsi, int len, u8 *buf); +void rp1dsi_dsi_set_cmdmode(struct rp1_dsi *dsi, int cmd_mode); +void rp1dsi_dsi_stop(struct rp1_dsi *dsi); + +#endif + diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-vec/Kconfig linux/drivers/gpu/drm/rp1/rp1-vec/Kconfig --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-vec/Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-vec/Kconfig 2023-12-13 11:50:59.410986728 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +# SPDX-License-Identifier: GPL-2.0-only +config DRM_RP1_VEC + tristate "DRM Support for RP1 VEC" + depends on DRM + select MFD_RP1 + select DRM_GEM_DMA_HELPER + select DRM_KMS_HELPER + select DRM_VRAM_HELPER + select DRM_TTM + select DRM_TTM_HELPER + help + Choose this option to enable Video Out on RP1 diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-vec/Makefile linux/drivers/gpu/drm/rp1/rp1-vec/Makefile --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-vec/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-vec/Makefile 2023-12-13 11:50:59.410986728 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:2 @ +# SPDX-License-Identifier: GPL-2.0-only + +drm-rp1-vec-y := rp1_vec.o rp1_vec_hw.o rp1_vec_cfg.o + +obj-$(CONFIG_DRM_RP1_VEC) += drm-rp1-vec.o diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c linux/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c 2023-12-13 11:50:59.410986728 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DRM Driver for VEC output on Raspberry Pi RP1 + * + * Copyright (c) 2023 Raspberry Pi Limited. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/mm.h> +#include <linux/fb.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/list.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/printk.h> +#include <linux/console.h> +#include <linux/debugfs.h> +#include <linux/uaccess.h> +#include <linux/io.h> +#include <linux/dma-mapping.h> +#include <linux/cred.h> +#include <drm/drm_drv.h> +#include <drm/drm_mm.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_managed.h> +#include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_encoder.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_framebuffer.h> +#include <drm/drm_gem.h> +#include <drm/drm_gem_atomic_helper.h> +#include <drm/drm_gem_dma_helper.h> +#include <drm/drm_gem_framebuffer_helper.h> +#include <drm/drm_simple_kms_helper.h> +#include <drm/drm_probe_helper.h> +#include <drm/drm_modeset_helper_vtables.h> +#include <drm/drm_vblank.h> +#include <drm/drm_of.h> + +#include "rp1_vec.h" + +/* + * Default TV standard parameter; it may be overridden by the OF + * property "tv_norm" (which should be one of the strings below). + * + * The default (empty string) supports various 60Hz and 50Hz modes, + * and will automatically select NTSC[-M] or PAL[-BDGHIKL]; the two + * "fake" 60Hz standards NTSC-443 and PAL60 also support 50Hz PAL. + * Other values will restrict the set of video modes offered. + * + * Finally, the DRM connector property "mode" (which is an integer) + * can be used to override this value, but it does not prevent the + * selection of an inapplicable video mode. + */ + +static char *rp1vec_tv_norm_str; +module_param_named(tv_norm, rp1vec_tv_norm_str, charp, 0600); +MODULE_PARM_DESC(tv_norm, "Default TV norm.\n" + "\t\tSupported: NTSC, NTSC-J, NTSC-443, PAL, PAL-M, PAL-N,\n" + "\t\t\tPAL60.\n" + "\t\tDefault: empty string: infer PAL for a 50 Hz mode,\n" + "\t\t\tNTSC otherwise"); + +const char * const rp1vec_tvstd_names[] = { + [RP1VEC_TVSTD_NTSC] = "NTSC", + [RP1VEC_TVSTD_NTSC_J] = "NTSC-J", + [RP1VEC_TVSTD_NTSC_443] = "NTSC-443", + [RP1VEC_TVSTD_PAL] = "PAL", + [RP1VEC_TVSTD_PAL_M] = "PAL-M", + [RP1VEC_TVSTD_PAL_N] = "PAL-N", + [RP1VEC_TVSTD_PAL60] = "PAL60", + [RP1VEC_TVSTD_DEFAULT] = "", +}; + +static int rp1vec_parse_tv_norm(const char *str) +{ + int i; + + if (str && *str) { + for (i = 0; i < ARRAY_SIZE(rp1vec_tvstd_names); ++i) { + if (strcasecmp(str, rp1vec_tvstd_names[i]) == 0) + return i; + } + } + return RP1VEC_TVSTD_DEFAULT; +} + +static void rp1vec_pipe_update(struct drm_simple_display_pipe *pipe, + struct drm_plane_state *old_state) +{ + struct drm_pending_vblank_event *event; + unsigned long flags; + struct drm_framebuffer *fb = pipe->plane.state->fb; + struct rp1_vec *vec = pipe->crtc.dev->dev_private; + struct drm_gem_object *gem = fb ? drm_gem_fb_get_obj(fb, 0) : NULL; + struct drm_gem_dma_object *dma_obj = gem ? to_drm_gem_dma_obj(gem) : NULL; + bool can_update = fb && dma_obj && vec && vec->pipe_enabled; + + /* (Re-)start VEC where required; and update FB address */ + if (can_update) { + if (!vec->vec_running || fb->format->format != vec->cur_fmt) { + if (vec->vec_running && fb->format->format != vec->cur_fmt) { + rp1vec_hw_stop(vec); + vec->vec_running = false; + } + if (!vec->vec_running) { + rp1vec_hw_setup(vec, + fb->format->format, + &pipe->crtc.state->mode, + vec->connector.state->tv.mode); + vec->vec_running = true; + } + vec->cur_fmt = fb->format->format; + drm_crtc_vblank_on(&pipe->crtc); + } + rp1vec_hw_update(vec, dma_obj->dma_addr, fb->offsets[0], fb->pitches[0]); + } + + /* Check if VBLANK callback needs to be armed (or sent immediately in some error cases). + * Note there is a tiny probability of a race between rp1vec_dma_update() and IRQ; + * ordering it this way around is safe, but theoretically might delay an extra frame. + */ + spin_lock_irqsave(&pipe->crtc.dev->event_lock, flags); + event = pipe->crtc.state->event; + if (event) { + pipe->crtc.state->event = NULL; + if (can_update && drm_crtc_vblank_get(&pipe->crtc) == 0) + drm_crtc_arm_vblank_event(&pipe->crtc, event); + else + drm_crtc_send_vblank_event(&pipe->crtc, event); + } + spin_unlock_irqrestore(&pipe->crtc.dev->event_lock, flags); +} + +static void rp1vec_pipe_enable(struct drm_simple_display_pipe *pipe, + struct drm_crtc_state *crtc_state, + struct drm_plane_state *plane_state) +{ + struct rp1_vec *vec = pipe->crtc.dev->dev_private; + + dev_info(&vec->pdev->dev, __func__); + vec->pipe_enabled = true; + vec->cur_fmt = 0xdeadbeef; + rp1vec_vidout_setup(vec); + rp1vec_pipe_update(pipe, 0); +} + +static void rp1vec_pipe_disable(struct drm_simple_display_pipe *pipe) +{ + struct rp1_vec *vec = pipe->crtc.dev->dev_private; + + dev_info(&vec->pdev->dev, __func__); + drm_crtc_vblank_off(&pipe->crtc); + if (vec) { + if (vec->vec_running) { + rp1vec_hw_stop(vec); + vec->vec_running = false; + } + vec->pipe_enabled = false; + } +} + +static int rp1vec_pipe_enable_vblank(struct drm_simple_display_pipe *pipe) +{ + if (pipe && pipe->crtc.dev) { + struct rp1_vec *vec = pipe->crtc.dev->dev_private; + + if (vec) + rp1vec_hw_vblank_ctrl(vec, 1); + } + return 0; +} + +static void rp1vec_pipe_disable_vblank(struct drm_simple_display_pipe *pipe) +{ + if (pipe && pipe->crtc.dev) { + struct rp1_vec *vec = pipe->crtc.dev->dev_private; + + if (vec) + rp1vec_hw_vblank_ctrl(vec, 0); + } +} + +static const struct drm_simple_display_pipe_funcs rp1vec_pipe_funcs = { + .enable = rp1vec_pipe_enable, + .update = rp1vec_pipe_update, + .disable = rp1vec_pipe_disable, + .prepare_fb = drm_gem_simple_display_pipe_prepare_fb, + .enable_vblank = rp1vec_pipe_enable_vblank, + .disable_vblank = rp1vec_pipe_disable_vblank, +}; + +static void rp1vec_connector_destroy(struct drm_connector *connector) +{ + drm_connector_unregister(connector); + drm_connector_cleanup(connector); +} + +static const struct drm_display_mode rp1vec_modes[4] = { + { /* Full size 525/60i with Rec.601 pixel rate */ + DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, + 720, 720 + 14, 720 + 14 + 64, 858, 0, + 480, 480 + 7, 480 + 7 + 6, 525, 0, + DRM_MODE_FLAG_INTERLACE) + }, + { /* Cropped and horizontally squashed to be TV-safe */ + DRM_MODE("704x432i", DRM_MODE_TYPE_DRIVER, 15429, + 704, 704 + 72, 704 + 72 + 72, 980, 0, + 432, 432 + 31, 432 + 31 + 6, 525, 0, + DRM_MODE_FLAG_INTERLACE) + }, + { /* Full size 625/50i with Rec.601 pixel rate */ + DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, + 720, 720 + 20, 720 + 20 + 64, 864, 0, + 576, 576 + 4, 576 + 4 + 6, 625, 0, + DRM_MODE_FLAG_INTERLACE) + }, + { /* Cropped and squashed, for square(ish) pixels */ + DRM_MODE("704x512i", DRM_MODE_TYPE_DRIVER, 15429, + 704, 704 + 80, 704 + 80 + 72, 987, 0, + 512, 512 + 36, 512 + 36 + 6, 625, 0, + DRM_MODE_FLAG_INTERLACE) + } +}; + +static int rp1vec_connector_get_modes(struct drm_connector *connector) +{ + struct rp1_vec *vec = container_of(connector, struct rp1_vec, connector); + bool ok525 = RP1VEC_TVSTD_SUPPORT_525(vec->tv_norm); + bool ok625 = RP1VEC_TVSTD_SUPPORT_625(vec->tv_norm); + int i, prog, n = 0; + + for (i = 0; i < ARRAY_SIZE(rp1vec_modes); i++) { + if ((rp1vec_modes[i].vtotal == 625) ? ok625 : ok525) { + for (prog = 0; prog < 2; prog++) { + struct drm_display_mode *mode = + drm_mode_duplicate(connector->dev, + &rp1vec_modes[i]); + + if (prog) { + mode->flags &= ~DRM_MODE_FLAG_INTERLACE; + mode->vdisplay >>= 1; + mode->vsync_start >>= 1; + mode->vsync_end >>= 1; + mode->vtotal >>= 1; + } + + if (mode->hdisplay == 704 && + mode->vtotal == ((ok525) ? 525 : 625)) + mode->type |= DRM_MODE_TYPE_PREFERRED; + + drm_mode_set_name(mode); + drm_mode_probed_add(connector, mode); + n++; + } + } + } + + return n; +} + +static void rp1vec_connector_reset(struct drm_connector *connector) +{ + struct rp1_vec *vec = container_of(connector, struct rp1_vec, connector); + + drm_atomic_helper_connector_reset(connector); + if (connector->state) + connector->state->tv.mode = vec->tv_norm; +} + +static int rp1vec_connector_atomic_check(struct drm_connector *conn, + struct drm_atomic_state *state) +{ struct drm_connector_state *old_state = + drm_atomic_get_old_connector_state(state, conn); + struct drm_connector_state *new_state = + drm_atomic_get_new_connector_state(state, conn); + + if (new_state->crtc && old_state->tv.mode != new_state->tv.mode) { + struct drm_crtc_state *crtc_state = + drm_atomic_get_new_crtc_state(state, new_state->crtc); + + crtc_state->mode_changed = true; + } + + return 0; +} + +static enum drm_mode_status rp1vec_mode_valid(struct drm_device *dev, + const struct drm_display_mode *mode) +{ + /* + * Check the mode roughly matches one of our standard modes + * (optionally half-height and progressive). Ignore H/V sync + * timings which for interlaced TV are approximate at best. + */ + int i, prog; + + prog = !(mode->flags & DRM_MODE_FLAG_INTERLACE); + + for (i = 0; i < ARRAY_SIZE(rp1vec_modes); i++) { + const struct drm_display_mode *ref = rp1vec_modes + i; + + if (mode->hdisplay == ref->hdisplay && + mode->vdisplay == (ref->vdisplay >> prog) && + mode->clock + 2 >= ref->clock && + mode->clock <= ref->clock + 2 && + mode->htotal + 2 >= ref->htotal && + mode->htotal <= ref->htotal + 2 && + mode->vtotal + 2 >= (ref->vtotal >> prog) && + mode->vtotal <= (ref->vtotal >> prog) + 2) + return MODE_OK; + } + return MODE_BAD; +} + +static const struct drm_connector_helper_funcs rp1vec_connector_helper_funcs = { + .get_modes = rp1vec_connector_get_modes, + .atomic_check = rp1vec_connector_atomic_check, +}; + +static const struct drm_connector_funcs rp1vec_connector_funcs = { + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = rp1vec_connector_destroy, + .reset = rp1vec_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static const struct drm_mode_config_funcs rp1vec_mode_funcs = { + .fb_create = drm_gem_fb_create, + .atomic_check = drm_atomic_helper_check, + .atomic_commit = drm_atomic_helper_commit, + .mode_valid = rp1vec_mode_valid, +}; + +static const u32 rp1vec_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565 +}; + +static void rp1vec_stopall(struct drm_device *drm) +{ + if (drm->dev_private) { + struct rp1_vec *vec = drm->dev_private; + + if (vec->vec_running || rp1vec_hw_busy(vec)) { + rp1vec_hw_stop(vec); + vec->vec_running = false; + } + rp1vec_vidout_poweroff(vec); + } +} + +DEFINE_DRM_GEM_DMA_FOPS(rp1vec_fops); + +static struct drm_driver rp1vec_driver = { + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, + .fops = &rp1vec_fops, + .name = "drm-rp1-vec", + .desc = "drm-rp1-vec", + .date = "0", + .major = 1, + .minor = 0, + DRM_GEM_DMA_DRIVER_OPS, + .release = rp1vec_stopall, +}; + +static int rp1vec_platform_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct drm_device *drm; + struct rp1_vec *vec; + const char *str; + int i, ret; + + dev_info(dev, __func__); + drm = drm_dev_alloc(&rp1vec_driver, dev); + if (IS_ERR(drm)) { + ret = PTR_ERR(drm); + dev_err(dev, "%s drm_dev_alloc %d", __func__, ret); + return ret; + } + + vec = drmm_kzalloc(drm, sizeof(*vec), GFP_KERNEL); + if (!vec) { + dev_err(dev, "%s drmm_kzalloc failed", __func__); + ret = -ENOMEM; + goto err_free_drm; + } + init_completion(&vec->finished); + vec->drm = drm; + vec->pdev = pdev; + drm->dev_private = vec; + platform_set_drvdata(pdev, drm); + + str = rp1vec_tv_norm_str; + of_property_read_string(dev->of_node, "tv_norm", &str); + vec->tv_norm = rp1vec_parse_tv_norm(str); + + for (i = 0; i < RP1VEC_NUM_HW_BLOCKS; i++) { + vec->hw_base[i] = + devm_ioremap_resource(dev, + platform_get_resource(vec->pdev, IORESOURCE_MEM, i)); + if (IS_ERR(vec->hw_base[i])) { + ret = PTR_ERR(vec->hw_base[i]); + dev_err(dev, "Error memory mapping regs[%d]\n", i); + goto err_free_drm; + } + } + ret = platform_get_irq(vec->pdev, 0); + if (ret > 0) + ret = devm_request_irq(dev, ret, rp1vec_hw_isr, + IRQF_SHARED, "rp1-vec", vec); + if (ret) { + dev_err(dev, "Unable to request interrupt\n"); + ret = -EINVAL; + goto err_free_drm; + } + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + + vec->vec_clock = devm_clk_get(dev, NULL); + if (IS_ERR(vec->vec_clock)) { + ret = PTR_ERR(vec->vec_clock); + goto err_free_drm; + } + ret = clk_prepare_enable(vec->vec_clock); + + ret = drmm_mode_config_init(drm); + if (ret) + goto err_free_drm; + drm->mode_config.max_width = 768; + drm->mode_config.max_height = 576; + drm->mode_config.fb_base = 0; + drm->mode_config.preferred_depth = 32; + drm->mode_config.prefer_shadow = 0; + drm->mode_config.prefer_shadow_fbdev = 1; + //drm->mode_config.fbdev_use_iomem = false; + drm->mode_config.quirk_addfb_prefer_host_byte_order = true; + drm->mode_config.funcs = &rp1vec_mode_funcs; + drm_vblank_init(drm, 1); + + ret = drm_mode_create_tv_properties(drm, ARRAY_SIZE(rp1vec_tvstd_names), + rp1vec_tvstd_names); + if (ret) + goto err_free_drm; + + drm_connector_init(drm, &vec->connector, &rp1vec_connector_funcs, + DRM_MODE_CONNECTOR_Composite); + if (ret) + goto err_free_drm; + + vec->connector.interlace_allowed = true; + drm_connector_helper_add(&vec->connector, &rp1vec_connector_helper_funcs); + + drm_object_attach_property(&vec->connector.base, + drm->mode_config.tv_mode_property, + vec->tv_norm); + + ret = drm_simple_display_pipe_init(drm, + &vec->pipe, + &rp1vec_pipe_funcs, + rp1vec_formats, + ARRAY_SIZE(rp1vec_formats), + NULL, + &vec->connector); + if (ret) + goto err_free_drm; + + drm_mode_config_reset(drm); + + ret = drm_dev_register(drm, 0); + if (ret) + goto err_free_drm; + + drm_fbdev_generic_setup(drm, 32); /* the "32" is preferred BPP */ + return ret; + +err_free_drm: + dev_info(dev, "%s fail %d", __func__, ret); + drm_dev_put(drm); + return ret; +} + +static int rp1vec_platform_remove(struct platform_device *pdev) +{ + struct drm_device *drm = platform_get_drvdata(pdev); + + rp1vec_stopall(drm); + drm_dev_unregister(drm); + drm_atomic_helper_shutdown(drm); + drm_dev_put(drm); + + return 0; +} + +static void rp1vec_platform_shutdown(struct platform_device *pdev) +{ + struct drm_device *drm = platform_get_drvdata(pdev); + + rp1vec_stopall(drm); +} + +static const struct of_device_id rp1vec_of_match[] = { + { + .compatible = "raspberrypi,rp1vec", + }, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, rp1vec_of_match); + +static struct platform_driver rp1vec_platform_driver = { + .probe = rp1vec_platform_probe, + .remove = rp1vec_platform_remove, + .shutdown = rp1vec_platform_shutdown, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = rp1vec_of_match, + }, +}; + +module_platform_driver(rp1vec_platform_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("DRM driver for Composite Video on Raspberry Pi RP1"); +MODULE_AUTHOR("Nick Hollinghurst"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-vec/rp1_vec_cfg.c linux/drivers/gpu/drm/rp1/rp1-vec/rp1_vec_cfg.c --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-vec/rp1_vec_cfg.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-vec/rp1_vec_cfg.c 2023-12-13 11:50:59.411986731 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DRM Driver for DSI output on Raspberry Pi RP1 + * + * Copyright (c) 2023 Raspberry Pi Limited. + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/mm.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/printk.h> +#include <linux/rp1_platform.h> + +#include "rp1_vec.h" + +// ============================================================================= +// Register : VIDEO_OUT_CFG_SEL +// JTAG access : synchronous +// Description : Selects source: VEC or DPI +#define VIDEO_OUT_CFG_SEL_OFFSET 0x00000000 +#define VIDEO_OUT_CFG_SEL_BITS 0x00000013 +#define VIDEO_OUT_CFG_SEL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_SEL_PCLK_INV +// Description : Select dpi_pclk output port polarity inversion. +#define VIDEO_OUT_CFG_SEL_PCLK_INV_RESET 0x0 +#define VIDEO_OUT_CFG_SEL_PCLK_INV_BITS 0x00000010 +#define VIDEO_OUT_CFG_SEL_PCLK_INV_MSB 4 +#define VIDEO_OUT_CFG_SEL_PCLK_INV_LSB 4 +#define VIDEO_OUT_CFG_SEL_PCLK_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_SEL_PAD_MUX +// Description : VEC 1 DPI 0 +#define VIDEO_OUT_CFG_SEL_PAD_MUX_RESET 0x0 +#define VIDEO_OUT_CFG_SEL_PAD_MUX_BITS 0x00000002 +#define VIDEO_OUT_CFG_SEL_PAD_MUX_MSB 1 +#define VIDEO_OUT_CFG_SEL_PAD_MUX_LSB 1 +#define VIDEO_OUT_CFG_SEL_PAD_MUX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_SEL_VDAC_MUX +// Description : VEC 1 DPI 0 +#define VIDEO_OUT_CFG_SEL_VDAC_MUX_RESET 0x0 +#define VIDEO_OUT_CFG_SEL_VDAC_MUX_BITS 0x00000001 +#define VIDEO_OUT_CFG_SEL_VDAC_MUX_MSB 0 +#define VIDEO_OUT_CFG_SEL_VDAC_MUX_LSB 0 +#define VIDEO_OUT_CFG_SEL_VDAC_MUX_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_VDAC_CFG +// JTAG access : synchronous +// Description : Configure SNPS VDAC +#define VIDEO_OUT_CFG_VDAC_CFG_OFFSET 0x00000004 +#define VIDEO_OUT_CFG_VDAC_CFG_BITS 0x1fffffff +#define VIDEO_OUT_CFG_VDAC_CFG_RESET 0x0003ffff +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_ENCTR +// Description : None +#define VIDEO_OUT_CFG_VDAC_CFG_ENCTR_RESET 0x0 +#define VIDEO_OUT_CFG_VDAC_CFG_ENCTR_BITS 0x1c000000 +#define VIDEO_OUT_CFG_VDAC_CFG_ENCTR_MSB 28 +#define VIDEO_OUT_CFG_VDAC_CFG_ENCTR_LSB 26 +#define VIDEO_OUT_CFG_VDAC_CFG_ENCTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_ENSC +// Description : None +#define VIDEO_OUT_CFG_VDAC_CFG_ENSC_RESET 0x0 +#define VIDEO_OUT_CFG_VDAC_CFG_ENSC_BITS 0x03800000 +#define VIDEO_OUT_CFG_VDAC_CFG_ENSC_MSB 25 +#define VIDEO_OUT_CFG_VDAC_CFG_ENSC_LSB 23 +#define VIDEO_OUT_CFG_VDAC_CFG_ENSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_ENDAC +// Description : None +#define VIDEO_OUT_CFG_VDAC_CFG_ENDAC_RESET 0x0 +#define VIDEO_OUT_CFG_VDAC_CFG_ENDAC_BITS 0x00700000 +#define VIDEO_OUT_CFG_VDAC_CFG_ENDAC_MSB 22 +#define VIDEO_OUT_CFG_VDAC_CFG_ENDAC_LSB 20 +#define VIDEO_OUT_CFG_VDAC_CFG_ENDAC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_ENVBG +// Description : None +#define VIDEO_OUT_CFG_VDAC_CFG_ENVBG_RESET 0x0 +#define VIDEO_OUT_CFG_VDAC_CFG_ENVBG_BITS 0x00080000 +#define VIDEO_OUT_CFG_VDAC_CFG_ENVBG_MSB 19 +#define VIDEO_OUT_CFG_VDAC_CFG_ENVBG_LSB 19 +#define VIDEO_OUT_CFG_VDAC_CFG_ENVBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF +// Description : None +#define VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF_RESET 0x0 +#define VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF_BITS 0x00040000 +#define VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF_MSB 18 +#define VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF_LSB 18 +#define VIDEO_OUT_CFG_VDAC_CFG_ENEXTREF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_DAC2GC +// Description : dac2 gain control +#define VIDEO_OUT_CFG_VDAC_CFG_DAC2GC_RESET 0x3f +#define VIDEO_OUT_CFG_VDAC_CFG_DAC2GC_BITS 0x0003f000 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC2GC_MSB 17 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC2GC_LSB 12 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC2GC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_DAC1GC +// Description : dac1 gain control +#define VIDEO_OUT_CFG_VDAC_CFG_DAC1GC_RESET 0x3f +#define VIDEO_OUT_CFG_VDAC_CFG_DAC1GC_BITS 0x00000fc0 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC1GC_MSB 11 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC1GC_LSB 6 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC1GC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_CFG_DAC0GC +// Description : dac0 gain control +#define VIDEO_OUT_CFG_VDAC_CFG_DAC0GC_RESET 0x3f +#define VIDEO_OUT_CFG_VDAC_CFG_DAC0GC_BITS 0x0000003f +#define VIDEO_OUT_CFG_VDAC_CFG_DAC0GC_MSB 5 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC0GC_LSB 0 +#define VIDEO_OUT_CFG_VDAC_CFG_DAC0GC_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_VDAC_STATUS +// JTAG access : synchronous +// Description : Read VDAC status +#define VIDEO_OUT_CFG_VDAC_STATUS_OFFSET 0x00000008 +#define VIDEO_OUT_CFG_VDAC_STATUS_BITS 0x00000017 +#define VIDEO_OUT_CFG_VDAC_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3 +// Description : None +#define VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3_RESET 0x0 +#define VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3_BITS 0x00000010 +#define VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3_MSB 4 +#define VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3_LSB 4 +#define VIDEO_OUT_CFG_VDAC_STATUS_ENCTR3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT +// Description : None +#define VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT_RESET "-" +#define VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT_BITS 0x00000007 +#define VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT_MSB 2 +#define VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT_LSB 0 +#define VIDEO_OUT_CFG_VDAC_STATUS_CABLEOUT_ACCESS "RO" +// ============================================================================= +// Register : VIDEO_OUT_CFG_MEM_PD +// JTAG access : synchronous +// Description : Control memory power down +#define VIDEO_OUT_CFG_MEM_PD_OFFSET 0x0000000c +#define VIDEO_OUT_CFG_MEM_PD_BITS 0x00000003 +#define VIDEO_OUT_CFG_MEM_PD_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_MEM_PD_VEC +// Description : None +#define VIDEO_OUT_CFG_MEM_PD_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_MEM_PD_VEC_BITS 0x00000002 +#define VIDEO_OUT_CFG_MEM_PD_VEC_MSB 1 +#define VIDEO_OUT_CFG_MEM_PD_VEC_LSB 1 +#define VIDEO_OUT_CFG_MEM_PD_VEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_MEM_PD_DPI +// Description : None +#define VIDEO_OUT_CFG_MEM_PD_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_MEM_PD_DPI_BITS 0x00000001 +#define VIDEO_OUT_CFG_MEM_PD_DPI_MSB 0 +#define VIDEO_OUT_CFG_MEM_PD_DPI_LSB 0 +#define VIDEO_OUT_CFG_MEM_PD_DPI_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_TEST_OVERRIDE +// JTAG access : synchronous +// Description : None +#define VIDEO_OUT_CFG_TEST_OVERRIDE_OFFSET 0x00000010 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_BITS 0xffffffff +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_TEST_OVERRIDE_PAD +// Description : None +#define VIDEO_OUT_CFG_TEST_OVERRIDE_PAD_RESET 0x0 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_PAD_BITS 0x80000000 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_PAD_MSB 31 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_PAD_LSB 31 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_PAD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC +// Description : None +#define VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_RESET 0x0 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_BITS 0x40000000 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_MSB 30 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_LSB 30 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_VDAC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL +// Description : None +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL_RESET 0x00000000 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL_BITS 0x3fffffff +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL_MSB 29 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL_LSB 0 +#define VIDEO_OUT_CFG_TEST_OVERRIDE_RGBVAL_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_INTR +// JTAG access : synchronous +// Description : Raw Interrupts +#define VIDEO_OUT_CFG_INTR_OFFSET 0x00000014 +#define VIDEO_OUT_CFG_INTR_BITS 0x00000003 +#define VIDEO_OUT_CFG_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTR_DPI +// Description : None +#define VIDEO_OUT_CFG_INTR_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_INTR_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_INTR_DPI_MSB 1 +#define VIDEO_OUT_CFG_INTR_DPI_LSB 1 +#define VIDEO_OUT_CFG_INTR_DPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTR_VEC +// Description : None +#define VIDEO_OUT_CFG_INTR_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_INTR_VEC_BITS 0x00000001 +#define VIDEO_OUT_CFG_INTR_VEC_MSB 0 +#define VIDEO_OUT_CFG_INTR_VEC_LSB 0 +#define VIDEO_OUT_CFG_INTR_VEC_ACCESS "RO" +// ============================================================================= +// Register : VIDEO_OUT_CFG_INTE +// JTAG access : synchronous +// Description : Interrupt Enable +#define VIDEO_OUT_CFG_INTE_OFFSET 0x00000018 +#define VIDEO_OUT_CFG_INTE_BITS 0x00000003 +#define VIDEO_OUT_CFG_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTE_DPI +// Description : None +#define VIDEO_OUT_CFG_INTE_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_INTE_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_INTE_DPI_MSB 1 +#define VIDEO_OUT_CFG_INTE_DPI_LSB 1 +#define VIDEO_OUT_CFG_INTE_DPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTE_VEC +// Description : None +#define VIDEO_OUT_CFG_INTE_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_INTE_VEC_BITS 0x00000001 +#define VIDEO_OUT_CFG_INTE_VEC_MSB 0 +#define VIDEO_OUT_CFG_INTE_VEC_LSB 0 +#define VIDEO_OUT_CFG_INTE_VEC_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_INTF +// JTAG access : synchronous +// Description : Interrupt Force +#define VIDEO_OUT_CFG_INTF_OFFSET 0x0000001c +#define VIDEO_OUT_CFG_INTF_BITS 0x00000003 +#define VIDEO_OUT_CFG_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTF_DPI +// Description : None +#define VIDEO_OUT_CFG_INTF_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_INTF_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_INTF_DPI_MSB 1 +#define VIDEO_OUT_CFG_INTF_DPI_LSB 1 +#define VIDEO_OUT_CFG_INTF_DPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTF_VEC +// Description : None +#define VIDEO_OUT_CFG_INTF_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_INTF_VEC_BITS 0x00000001 +#define VIDEO_OUT_CFG_INTF_VEC_MSB 0 +#define VIDEO_OUT_CFG_INTF_VEC_LSB 0 +#define VIDEO_OUT_CFG_INTF_VEC_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_INTS +// JTAG access : synchronous +// Description : Interrupt status after masking & forcing +#define VIDEO_OUT_CFG_INTS_OFFSET 0x00000020 +#define VIDEO_OUT_CFG_INTS_BITS 0x00000003 +#define VIDEO_OUT_CFG_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTS_DPI +// Description : None +#define VIDEO_OUT_CFG_INTS_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_INTS_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_INTS_DPI_MSB 1 +#define VIDEO_OUT_CFG_INTS_DPI_LSB 1 +#define VIDEO_OUT_CFG_INTS_DPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_INTS_VEC +// Description : None +#define VIDEO_OUT_CFG_INTS_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_INTS_VEC_BITS 0x00000001 +#define VIDEO_OUT_CFG_INTS_VEC_MSB 0 +#define VIDEO_OUT_CFG_INTS_VEC_LSB 0 +#define VIDEO_OUT_CFG_INTS_VEC_ACCESS "RO" +// ============================================================================= +// Register : VIDEO_OUT_CFG_BLOCK_ID +// JTAG access : synchronous +// Description : Block Identifier +// Hexadecimal representation of "VOCF" +#define VIDEO_OUT_CFG_BLOCK_ID_OFFSET 0x00000024 +#define VIDEO_OUT_CFG_BLOCK_ID_BITS 0xffffffff +#define VIDEO_OUT_CFG_BLOCK_ID_RESET 0x564f4346 +#define VIDEO_OUT_CFG_BLOCK_ID_MSB 31 +#define VIDEO_OUT_CFG_BLOCK_ID_LSB 0 +#define VIDEO_OUT_CFG_BLOCK_ID_ACCESS "RO" +// ============================================================================= +// Register : VIDEO_OUT_CFG_INSTANCE_ID +// JTAG access : synchronous +// Description : Block Instance Identifier +#define VIDEO_OUT_CFG_INSTANCE_ID_OFFSET 0x00000028 +#define VIDEO_OUT_CFG_INSTANCE_ID_BITS 0x0000000f +#define VIDEO_OUT_CFG_INSTANCE_ID_RESET 0x00000000 +#define VIDEO_OUT_CFG_INSTANCE_ID_MSB 3 +#define VIDEO_OUT_CFG_INSTANCE_ID_LSB 0 +#define VIDEO_OUT_CFG_INSTANCE_ID_ACCESS "RO" +// ============================================================================= +// Register : VIDEO_OUT_CFG_RSTSEQ_AUTO +// JTAG access : synchronous +// Description : None +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_OFFSET 0x0000002c +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BITS 0x00000007 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_RESET 0x00000007 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC +// Description : 1 = reset is controlled by the sequencer +// 0 = reset is controlled by rstseq_ctrl +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC_RESET 0x1 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC_BITS 0x00000004 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC_MSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC_LSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_VEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI +// Description : 1 = reset is controlled by the sequencer +// 0 = reset is controlled by rstseq_ctrl +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI_RESET 0x1 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI_MSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI_LSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_DPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER +// Description : 1 = reset is controlled by the sequencer +// 0 = reset is controlled by rstseq_ctrl +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER_RESET 0x1 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER_BITS 0x00000001 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER_MSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER_LSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_AUTO_BUSADAPTER_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_RSTSEQ_PARALLEL +// JTAG access : synchronous +// Description : None +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_OFFSET 0x00000030 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BITS 0x00000007 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_RESET 0x00000006 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC +// Description : Is this reset parallel (i.e. not part of the sequence) +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC_RESET 0x1 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC_BITS 0x00000004 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC_MSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC_LSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_VEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI +// Description : Is this reset parallel (i.e. not part of the sequence) +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI_RESET 0x1 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI_MSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI_LSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_DPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER +// Description : Is this reset parallel (i.e. not part of the sequence) +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER_BITS 0x00000001 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER_MSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER_LSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_PARALLEL_BUSADAPTER_ACCESS "RO" +// ============================================================================= +// Register : VIDEO_OUT_CFG_RSTSEQ_CTRL +// JTAG access : synchronous +// Description : None +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_OFFSET 0x00000034 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BITS 0x00000007 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC +// Description : 1 = keep the reset asserted +// 0 = keep the reset deasserted +// This is ignored if rstseq_auto=1 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC_BITS 0x00000004 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC_MSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC_LSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_VEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI +// Description : 1 = keep the reset asserted +// 0 = keep the reset deasserted +// This is ignored if rstseq_auto=1 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI_MSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI_LSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_DPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER +// Description : 1 = keep the reset asserted +// 0 = keep the reset deasserted +// This is ignored if rstseq_auto=1 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER_BITS 0x00000001 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER_MSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER_LSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_CTRL_BUSADAPTER_ACCESS "RW" +// ============================================================================= +// Register : VIDEO_OUT_CFG_RSTSEQ_TRIG +// JTAG access : synchronous +// Description : None +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_OFFSET 0x00000038 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BITS 0x00000007 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC +// Description : Pulses the reset output +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC_BITS 0x00000004 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC_MSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC_LSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_VEC_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI +// Description : Pulses the reset output +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI_MSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI_LSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_DPI_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER +// Description : Pulses the reset output +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER_BITS 0x00000001 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER_MSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER_LSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_TRIG_BUSADAPTER_ACCESS "SC" +// ============================================================================= +// Register : VIDEO_OUT_CFG_RSTSEQ_DONE +// JTAG access : synchronous +// Description : None +#define VIDEO_OUT_CFG_RSTSEQ_DONE_OFFSET 0x0000003c +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BITS 0x00000007 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_DONE_VEC +// Description : Indicates the current state of the reset +#define VIDEO_OUT_CFG_RSTSEQ_DONE_VEC_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_VEC_BITS 0x00000004 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_VEC_MSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_VEC_LSB 2 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_VEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_DONE_DPI +// Description : Indicates the current state of the reset +#define VIDEO_OUT_CFG_RSTSEQ_DONE_DPI_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_DPI_BITS 0x00000002 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_DPI_MSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_DPI_LSB 1 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_DPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER +// Description : Indicates the current state of the reset +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER_RESET 0x0 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER_BITS 0x00000001 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER_MSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER_LSB 0 +#define VIDEO_OUT_CFG_RSTSEQ_DONE_BUSADAPTER_ACCESS "RO" +// ============================================================================= + +#define CFG_WRITE(reg, val) writel((val), vec->hw_base[RP1VEC_HW_BLOCK_CFG] + (reg ## _OFFSET)) +#define CFG_READ(reg) readl(vec->hw_base[RP1VEC_HW_BLOCK_CFG] + (reg ## _OFFSET)) + +void rp1vec_vidout_setup(struct rp1_vec *vec) +{ + /* + * We assume DPI and VEC can't be used at the same time (due to + * clashing requirements for PLL_VIDEO, and potentially for VDAC). + * We therefore leave DPI memories powered down. + */ + CFG_WRITE(VIDEO_OUT_CFG_MEM_PD, VIDEO_OUT_CFG_MEM_PD_DPI_BITS); + CFG_WRITE(VIDEO_OUT_CFG_TEST_OVERRIDE, 0x00000000); + + /* DPI->Pads; VEC->VDAC */ + CFG_WRITE(VIDEO_OUT_CFG_SEL, VIDEO_OUT_CFG_SEL_VDAC_MUX_BITS); + + /* configure VDAC for 1 channel, bandgap on, 1.28V swing */ + CFG_WRITE(VIDEO_OUT_CFG_VDAC_CFG, 0x0019ffff); + + /* enable VEC interrupt */ + CFG_WRITE(VIDEO_OUT_CFG_INTE, VIDEO_OUT_CFG_INTE_VEC_BITS); +} + +void rp1vec_vidout_poweroff(struct rp1_vec *vec) +{ + /* disable VEC interrupt */ + CFG_WRITE(VIDEO_OUT_CFG_INTE, 0); + + /* Ensure VDAC is turned off; power down DPI,VEC memories */ + CFG_WRITE(VIDEO_OUT_CFG_VDAC_CFG, 0); + CFG_WRITE(VIDEO_OUT_CFG_MEM_PD, VIDEO_OUT_CFG_MEM_PD_BITS); +} diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.h linux/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.h --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.h 2023-12-13 11:50:59.411986731 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * DRM Driver for DSI output on Raspberry Pi RP1 + * + * Copyright (c) 2023 Raspberry Pi Limited. + */ + +#include <linux/types.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <drm/drm_device.h> +#include <drm/drm_simple_kms_helper.h> + +#define MODULE_NAME "drm-rp1-vec" +#define DRIVER_NAME "drm-rp1-vec" + +/* ---------------------------------------------------------------------- */ + +#define RP1VEC_HW_BLOCK_VEC 0 +#define RP1VEC_HW_BLOCK_CFG 1 +#define RP1VEC_NUM_HW_BLOCKS 2 + +enum { + RP1VEC_TVSTD_NTSC = 0, /* +525 => NTSC 625 => PAL */ + RP1VEC_TVSTD_NTSC_J, /* +525 => NTSC-J 625 => PAL */ + RP1VEC_TVSTD_NTSC_443, /* +525 => NTSC-443 +625 => PAL */ + RP1VEC_TVSTD_PAL, /* 525 => NTSC +625 => PAL */ + RP1VEC_TVSTD_PAL_M, /* +525 => PAL-M 625 => PAL */ + RP1VEC_TVSTD_PAL_N, /* 525 => NTSC +625 => PAL-N */ + RP1VEC_TVSTD_PAL60, /* +525 => PAL60 +625 => PAL */ + RP1VEC_TVSTD_DEFAULT, /* +525 => NTSC +625 => PAL */ +}; + +/* Which standards support which modes? Those marked with + above */ +#define RP1VEC_TVSTD_SUPPORT_525(n) ((0xD7 >> (n)) & 1) +#define RP1VEC_TVSTD_SUPPORT_625(n) ((0xEC >> (n)) & 1) + +/* ---------------------------------------------------------------------- */ + +struct rp1_vec { + /* DRM and platform device pointers */ + struct drm_device *drm; + struct platform_device *pdev; + + /* Framework and helper objects */ + struct drm_simple_display_pipe pipe; + struct drm_connector connector; + + /* Clock. We assume this is always at 108 MHz. */ + struct clk *vec_clock; + + /* Block (VCC, CFG) base addresses, and current state */ + void __iomem *hw_base[RP1VEC_NUM_HW_BLOCKS]; + u32 cur_fmt; + int tv_norm; + bool vec_running, pipe_enabled; + struct completion finished; +}; + +extern const char * const rp1vec_tvstd_names[]; + +/* ---------------------------------------------------------------------- */ +/* Functions to control the VEC/DMA block */ + +void rp1vec_hw_setup(struct rp1_vec *vec, + u32 in_format, + struct drm_display_mode const *mode, + int tvstd); +void rp1vec_hw_update(struct rp1_vec *vec, dma_addr_t addr, u32 offset, u32 stride); +void rp1vec_hw_stop(struct rp1_vec *vec); +int rp1vec_hw_busy(struct rp1_vec *vec); +irqreturn_t rp1vec_hw_isr(int irq, void *dev); +void rp1vec_hw_vblank_ctrl(struct rp1_vec *vec, int enable); + +/* ---------------------------------------------------------------------- */ +/* Functions to control the VIDEO OUT CFG block and check RP1 platform */ + +void rp1vec_vidout_setup(struct rp1_vec *vec); +void rp1vec_vidout_poweroff(struct rp1_vec *vec); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c linux/drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c 2023-12-13 11:50:59.411986731 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DRM Driver for VEC output on Raspberry Pi RP1 + * + * Copyright (c) 2023 Raspberry Pi Limited. + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/mm.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/printk.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_print.h> +#include <drm/drm_vblank.h> + +#include "rp1_vec.h" +#include "vec_regs.h" + +#define BITS(field, val) (((val) << (field ## _LSB)) & (field ## _BITS)) + +#define VEC_WRITE(reg, val) writel((val), vec->hw_base[RP1VEC_HW_BLOCK_VEC] + (reg ## _OFFSET)) +#define VEC_READ(reg) readl(vec->hw_base[RP1VEC_HW_BLOCK_VEC] + (reg ## _OFFSET)) + +int rp1vec_hw_busy(struct rp1_vec *vec) +{ + /* Read the undocumented "pline_busy" flag */ + return VEC_READ(VEC_STATUS) & 1; +} + +/* Table of supported input (in-memory/DMA) pixel formats. */ +struct rp1vec_ipixfmt { + u32 format; /* DRM format code */ + u32 mask; /* RGB masks (10 bits each, left justified) */ + u32 shift; /* RGB MSB positions in the memory word */ + u32 rgbsz; /* Shifts used for scaling; also (BPP/8-1) */ +}; + +#define MASK_RGB(r, g, b) \ + (BITS(VEC_IMASK_MASK_R, r) | BITS(VEC_IMASK_MASK_G, g) | BITS(VEC_IMASK_MASK_B, b)) +#define SHIFT_RGB(r, g, b) \ + (BITS(VEC_SHIFT_SHIFT_R, r) | BITS(VEC_SHIFT_SHIFT_G, g) | BITS(VEC_SHIFT_SHIFT_B, b)) + +static const struct rp1vec_ipixfmt my_formats[] = { + { + .format = DRM_FORMAT_XRGB8888, + .mask = MASK_RGB(0x3fc, 0x3fc, 0x3fc), + .shift = SHIFT_RGB(23, 15, 7), + .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 3), + }, + { + .format = DRM_FORMAT_XBGR8888, + .mask = MASK_RGB(0x3fc, 0x3fc, 0x3fc), + .shift = SHIFT_RGB(7, 15, 23), + .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 3), + }, + { + .format = DRM_FORMAT_RGB888, + .mask = MASK_RGB(0x3fc, 0x3fc, 0x3fc), + .shift = SHIFT_RGB(23, 15, 7), + .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 2), + }, + { + .format = DRM_FORMAT_BGR888, + .mask = MASK_RGB(0x3fc, 0x3fc, 0x3fc), + .shift = SHIFT_RGB(7, 15, 23), + .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 2), + }, + { + .format = DRM_FORMAT_RGB565, + .mask = MASK_RGB(0x3e0, 0x3f0, 0x3e0), + .shift = SHIFT_RGB(15, 10, 4), + .rgbsz = BITS(VEC_RGBSZ_SCALE_R, 5) | + BITS(VEC_RGBSZ_SCALE_G, 6) | + BITS(VEC_RGBSZ_SCALE_B, 5) | + BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 1), + } +}; + +/* + * Hardware mode descriptions (@ 108 MHz clock rate). + * These rely largely on "canned" register settings. + * TODO: Port the generating software from FP to integer, + * or better factorize the differences between modes. + */ + +struct rp1vec_hwmode { + u16 total_cols; /* active columns, plus padding for filter context */ + u16 rows_per_field; /* active lines per field (including partial ones) */ + bool interlaced; /* set for interlaced */ + bool first_field_odd; /* set for interlaced and 30fps */ + u32 yuv_scaling; /* three 10-bit fields {Y, U, V} in 2.8 format */ + u32 back_end_regs[28]; /* All registers 0x80 .. 0xEC */ +}; + +/* { NTSC, PAL, PAL-M } x { progressive, interlaced } x { 13.5 MHz, 15.428571 MHz } */ +static const struct rp1vec_hwmode rp1vec_hwmodes[3][2][2] = { + { + /* NTSC */ + { + { + .total_cols = 724, + .rows_per_field = 240, + .interlaced = false, + .first_field_odd = false, + .yuv_scaling = 0x1071d0cf, + .back_end_regs = { + 0x039f1a3f, 0x03e10cc6, 0x0d6801fb, 0x023d034c, + 0x00f80b6d, 0x00000005, 0x0006000b, 0x000c0011, + 0x000a0106, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00170106, 0x00000000, 0x004c020e, + 0x00000000, 0x007bffff, 0x38518c9a, 0x11195561, + 0x02000200, 0xc1f07c1f, 0x087c1f07, 0x00000000, + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ec, + }, + }, { + .total_cols = 815, + .rows_per_field = 240, + .interlaced = false, + .first_field_odd = false, + .yuv_scaling = 0x1c131962, + .back_end_regs = { + 0x03ce1a17, 0x03e10cc6, 0x0d6801fb, 0x023d034c, + 0x00f80b6d, 0x00000005, 0x0006000b, 0x000c0011, + 0x000a0106, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00170106, 0x00000000, 0x004c020e, + 0x00000000, 0x007bffff, 0x38518c9a, 0x11195561, + 0x02000200, 0xc1f07c1f, 0x087c1f07, 0x00000000, + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ac, + }, + }, + }, { + { + .total_cols = 724, + .rows_per_field = 243, + .interlaced = true, + .first_field_odd = true, + .yuv_scaling = 0x1071d0cf, + .back_end_regs = { + 0x039f1a3f, 0x03e10cc6, 0x0d6801fb, 0x023d034c, + 0x00f80b6d, 0x00000005, 0x0006000b, 0x000c0011, + 0x000a0107, 0x0111020d, 0x00000000, 0x00000000, + 0x011c020d, 0x00150106, 0x0107011b, 0x004c020d, + 0x00000000, 0x007bffff, 0x38518c9a, 0x11195561, + 0x02000200, 0xc1f07c1f, 0x087c1f07, 0x00000000, + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x00094dee, + }, + }, { + .total_cols = 815, + .rows_per_field = 243, + .interlaced = true, + .first_field_odd = true, + .yuv_scaling = 0x1c131962, + .back_end_regs = { + 0x03ce1a17, 0x03e10cc6, 0x0d6801fb, 0x023d034c, + 0x00f80b6d, 0x00000005, 0x0006000b, 0x000c0011, + 0x000a0107, 0x0111020d, 0x00000000, 0x00000000, + 0x011c020d, 0x00150106, 0x0107011b, 0x004c020d, + 0x00000000, 0x007bffff, 0x38518c9a, 0x11195561, + 0x02000200, 0xc1f07c1f, 0x087c1f07, 0x00000000, + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x00094dae, + }, + }, + }, + }, { + /* PAL */ + { + { + .total_cols = 724, + .rows_per_field = 288, + .interlaced = false, + .first_field_odd = false, + .yuv_scaling = 0x11c1f8e0, + .back_end_regs = { + 0x04061aa6, 0x046e0cee, 0x0d8001fb, 0x025c034f, + 0x00fd0b84, 0x026c0270, 0x00000004, 0x00050009, + 0x00070135, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00170136, 0x00000000, 0x000a0270, + 0x00000000, 0x007bffff, 0x3b1389d8, 0x0caf53b5, + 0x02000200, 0xcc48c1d1, 0x0a8262b2, 0x00000000, + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ed, + }, + }, { + .total_cols = 804, + .rows_per_field = 288, + .interlaced = false, + .first_field_odd = false, + .yuv_scaling = 0x1e635d7f, + .back_end_regs = { + 0x045b1a57, 0x046e0cee, 0x0d8001fb, 0x025c034f, + 0x00fd0b84, 0x026c0270, 0x00000004, 0x00050009, + 0x00070135, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00170136, 0x00000000, 0x000a0270, + 0x00000000, 0x007bffff, 0x3b1389d8, 0x0caf53b5, + 0x02000200, 0xcc48c1d1, 0x0a8262b2, 0x00000000, + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ad, + }, + }, + }, { + { + .total_cols = 724, + .rows_per_field = 288, + .interlaced = true, + .first_field_odd = false, + .yuv_scaling = 0x11c1f8e0, + .back_end_regs = { + 0x04061aa6, 0x046e0cee, 0x0d8001fb, 0x025c034f, + 0x00fd0b84, 0x026c0270, 0x00000004, 0x00050009, + 0x00070135, 0x013f026d, 0x00060136, 0x0140026e, + 0x0150026e, 0x00180136, 0x026f0017, 0x000a0271, + 0x00000000, 0x007bffff, 0x3b1389d8, 0x0caf53b5, + 0x02000200, 0xcc48c1d1, 0x0a8262b2, 0x00000000, + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x0009ddef, + }, + }, { + .total_cols = 804, + .rows_per_field = 288, + .interlaced = true, + .first_field_odd = false, + .yuv_scaling = 0x1e635d7f, + .back_end_regs = { + 0x045b1a57, 0x046e0cee, 0x0d8001fb, 0x025c034f, + 0x00fd0b84, 0x026c0270, 0x00000004, 0x00050009, + 0x00070135, 0x013f026d, 0x00060136, 0x0140026e, + 0x0150026e, 0x00180136, 0x026f0017, 0x000a0271, + 0x00000000, 0x007bffff, 0x3b1389d8, 0x0caf53b5, + 0x02000200, 0xcc48c1d1, 0x0a8262b2, 0x00000000, + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x0009ddaf, + }, + }, + }, + }, { + /* PAL-M */ + { + { + .total_cols = 724, + .rows_per_field = 240, + .interlaced = false, + .first_field_odd = false, + .yuv_scaling = 0x11c1f8e0, + .back_end_regs = { + 0x039f1a3f, 0x03e10cc6, 0x0d6801fb, 0x023c034c, + 0x00f80b6e, 0x00000005, 0x0006000b, 0x000c0011, + 0x000a0106, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00170106, 0x00000000, 0x000a020c, + 0x00000000, 0x007bffff, 0x385189d8, 0x0d5c53b5, + 0x02000200, 0xd6d33ea8, 0x0879bbf8, 0x00000000, + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ed, + }, + }, { + .total_cols = 815, + .rows_per_field = 240, + .interlaced = false, + .first_field_odd = false, + .yuv_scaling = 0x1e635d7f, + .back_end_regs = { + 0x03ce1a17, 0x03e10cc6, 0x0d6801fb, 0x023c034c, + 0x00f80b6e, 0x00000005, 0x0006000b, 0x000c0011, + 0x000a0106, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00170106, 0x00000000, 0x000a020c, + 0x00000000, 0x007bffff, 0x385189d8, 0x0d5c53b5, + 0x02000200, 0xd6d33ea8, 0x0879bbf8, 0x00000000, + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ad, + }, + }, + }, { + { + .total_cols = 724, + .rows_per_field = 243, + .interlaced = true, + .first_field_odd = true, + .yuv_scaling = 0x11c1f8e0, + .back_end_regs = { + 0x039f1a3f, 0x03e10cc6, 0x0d6801fb, 0x023c034c, + 0x00f80b6e, 0x00140019, 0x00000005, 0x0006000b, + 0x00090103, 0x010f0209, 0x00080102, 0x010e020a, + 0x0119020a, 0x00120103, 0x01040118, 0x000a020d, + 0x00000000, 0x007bffff, 0x385189d8, 0x0d5c53b5, + 0x02000200, 0xd6d33ea8, 0x0879bbf8, 0x00000000, + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x0009ddef, + }, + }, { + .total_cols = 815, + .rows_per_field = 243, + .interlaced = true, + .first_field_odd = true, + .yuv_scaling = 0x1e635d7f, + .back_end_regs = { + 0x03ce1a17, 0x03e10cc6, 0x0d6801fb, 0x023c034c, + 0x00f80b6e, 0x00140019, 0x00000005, 0x0006000b, + 0x00090103, 0x010f0209, 0x00080102, 0x010e020a, + 0x0119020a, 0x00120103, 0x01040118, 0x000a020d, + 0x00000000, 0x007bffff, 0x385189d8, 0x0d5c53b5, + 0x02000200, 0xd6d33ea8, 0x0879bbf8, 0x00000000, + 0x0be20200, 0x20f0f800, 0x265c7f00, 0x0009ddaf, + }, + }, + }, + }, +}; + +void rp1vec_hw_setup(struct rp1_vec *vec, + u32 in_format, + struct drm_display_mode const *mode, + int tvstd) +{ + unsigned int i, mode_family, mode_ilaced, mode_narrow; + const struct rp1vec_hwmode *hwm; + unsigned int w, h; + + /* Pick the appropriate "base" mode, which we may modify */ + mode_ilaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); + if (mode->vtotal > 263 * (1 + mode_ilaced)) + mode_family = 1; + else + mode_family = (tvstd == RP1VEC_TVSTD_PAL_M || tvstd == RP1VEC_TVSTD_PAL60) ? 2 : 0; + mode_narrow = (mode->clock >= 14336); + hwm = &rp1vec_hwmodes[mode_family][mode_ilaced][mode_narrow]; + dev_info(&vec->pdev->dev, + "%s: in_fmt=\'%c%c%c%c\' mode=%dx%d%s [%d%d%d] tvstd=%d (%s)", + __func__, in_format, in_format >> 8, in_format >> 16, in_format >> 24, + mode->hdisplay, mode->vdisplay, (mode_ilaced) ? "i" : "", + mode_family, mode_ilaced, mode_narrow, + tvstd, rp1vec_tvstd_names[tvstd]); + + w = mode->hdisplay; + h = mode->vdisplay; + if (mode_ilaced) + h >>= 1; + if (w > hwm->total_cols) + w = hwm->total_cols; + if (h > hwm->rows_per_field) + w = hwm->rows_per_field; + + /* Configure the hardware */ + VEC_WRITE(VEC_APB_TIMEOUT, 0x38); + VEC_WRITE(VEC_QOS, + BITS(VEC_QOS_DQOS, 0x0) | + BITS(VEC_QOS_ULEV, 0x8) | + BITS(VEC_QOS_UQOS, 0x2) | + BITS(VEC_QOS_LLEV, 0x4) | + BITS(VEC_QOS_LQOS, 0x7)); + VEC_WRITE(VEC_DMA_AREA, + BITS(VEC_DMA_AREA_COLS_MINUS1, w - 1) | + BITS(VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1, h - 1)); + VEC_WRITE(VEC_YUV_SCALING, hwm->yuv_scaling); + VEC_WRITE(VEC_BACK_PORCH, + BITS(VEC_BACK_PORCH_HBP_MINUS1, (hwm->total_cols - w - 1) >> 1) | + BITS(VEC_BACK_PORCH_VBP_MINUS1, (hwm->rows_per_field - h - 1) >> 1)); + VEC_WRITE(VEC_FRONT_PORCH, + BITS(VEC_FRONT_PORCH_HFP_MINUS1, (hwm->total_cols - w - 2) >> 1) | + BITS(VEC_FRONT_PORCH_VFP_MINUS1, (hwm->rows_per_field - h - 2) >> 1)); + VEC_WRITE(VEC_MODE, + BITS(VEC_MODE_HIGH_WATER, 0xE0) | + BITS(VEC_MODE_ALIGN16, !((w | mode->hdisplay) & 15)) | + BITS(VEC_MODE_VFP_EN, (hwm->rows_per_field > h + 1)) | + BITS(VEC_MODE_VBP_EN, (hwm->rows_per_field > h)) | + BITS(VEC_MODE_HFP_EN, (hwm->total_cols > w + 1)) | + BITS(VEC_MODE_HBP_EN, (hwm->total_cols > w)) | + BITS(VEC_MODE_FIELDS_PER_FRAME_MINUS1, hwm->interlaced) | + BITS(VEC_MODE_FIRST_FIELD_ODD, hwm->first_field_odd)); + for (i = 0; i < ARRAY_SIZE(hwm->back_end_regs); ++i) { + writel(hwm->back_end_regs[i], + vec->hw_base[RP1VEC_HW_BLOCK_VEC] + 0x80 + 4 * i); + } + + /* Apply modifications */ + if (tvstd == RP1VEC_TVSTD_NTSC_J && mode_family == 0) { + /* Reduce pedestal (not quite to zero, for FIR overshoot); increase gain */ + VEC_WRITE(VEC_DAC_BC, + BITS(VEC_DAC_BC_S11_PEDESTAL, 10) | + (hwm->back_end_regs[(0xBC - 0x80) / 4] & ~VEC_DAC_BC_S11_PEDESTAL_BITS)); + VEC_WRITE(VEC_DAC_C8, + BITS(VEC_DAC_C8_U16_SCALE_LUMA, 0x9400) | + (hwm->back_end_regs[(0xC8 - 0x80) / 4] & + ~VEC_DAC_C8_U16_SCALE_LUMA_BITS)); + } else if ((tvstd == RP1VEC_TVSTD_NTSC_443 || tvstd == RP1VEC_TVSTD_PAL60) && + mode_family != 1) { + /* Change colour carrier frequency to 4433618.75 Hz; disable hard sync */ + VEC_WRITE(VEC_DAC_D4, 0xcc48c1d1); + VEC_WRITE(VEC_DAC_D8, 0x0a8262b2); + VEC_WRITE(VEC_DAC_EC, + hwm->back_end_regs[(0xEC - 0x80) / 4] & ~VEC_DAC_EC_SEQ_EN_BITS); + } else if (tvstd == RP1VEC_TVSTD_PAL_N && mode_family == 1) { + /* Change colour carrier frequency to 3582056.25 Hz */ + VEC_WRITE(VEC_DAC_D4, 0x9ce075f7); + VEC_WRITE(VEC_DAC_D8, 0x087da511); + } + + /* Input pixel format conversion */ + for (i = 0; i < ARRAY_SIZE(my_formats); ++i) { + if (my_formats[i].format == in_format) + break; + } + if (i >= ARRAY_SIZE(my_formats)) { + dev_err(&vec->pdev->dev, "%s: bad input format\n", __func__); + i = 0; + } + VEC_WRITE(VEC_IMASK, my_formats[i].mask); + VEC_WRITE(VEC_SHIFT, my_formats[i].shift); + VEC_WRITE(VEC_RGBSZ, my_formats[i].rgbsz); + + VEC_WRITE(VEC_IRQ_FLAGS, 0xffffffff); + rp1vec_hw_vblank_ctrl(vec, 1); + + i = rp1vec_hw_busy(vec); + if (i) + dev_warn(&vec->pdev->dev, + "%s: VEC unexpectedly busy at start (0x%08x)", + __func__, VEC_READ(VEC_STATUS)); + + VEC_WRITE(VEC_CONTROL, + BITS(VEC_CONTROL_START_ARM, (!i)) | + BITS(VEC_CONTROL_AUTO_REPEAT, 1)); +} + +void rp1vec_hw_update(struct rp1_vec *vec, dma_addr_t addr, u32 offset, u32 stride) +{ + /* + * Update STRIDE, DMAH and DMAL only. When called after rp1vec_hw_setup(), + * DMA starts immediately; if already running, the buffer will flip at + * the next vertical sync event. + */ + u64 a = addr + offset; + + VEC_WRITE(VEC_DMA_STRIDE, stride); + VEC_WRITE(VEC_DMA_ADDR_H, a >> 32); + VEC_WRITE(VEC_DMA_ADDR_L, a & 0xFFFFFFFFu); +} + +void rp1vec_hw_stop(struct rp1_vec *vec) +{ + /* + * Stop DMA by turning off the Auto-Repeat flag, and wait up to 100ms for + * the current and any queued frame to end. "Force drain" flags are not used, + * as they seem to prevent DMA from re-starting properly; it's safer to wait. + */ + + reinit_completion(&vec->finished); + VEC_WRITE(VEC_CONTROL, 0); + if (!wait_for_completion_timeout(&vec->finished, HZ / 10)) + drm_err(vec->drm, "%s: timed out waiting for idle\n", __func__); + VEC_WRITE(VEC_IRQ_ENABLES, 0); +} + +void rp1vec_hw_vblank_ctrl(struct rp1_vec *vec, int enable) +{ + VEC_WRITE(VEC_IRQ_ENABLES, + BITS(VEC_IRQ_ENABLES_DONE, 1) | + BITS(VEC_IRQ_ENABLES_DMA, (enable ? 1 : 0)) | + BITS(VEC_IRQ_ENABLES_MATCH_ROW, 1023)); +} + +irqreturn_t rp1vec_hw_isr(int irq, void *dev) +{ + struct rp1_vec *vec = dev; + u32 u = VEC_READ(VEC_IRQ_FLAGS); + + if (u) { + VEC_WRITE(VEC_IRQ_FLAGS, u); + if (u & VEC_IRQ_FLAGS_DMA_BITS) + drm_crtc_handle_vblank(&vec->pipe.crtc); + if (u & VEC_IRQ_FLAGS_DONE_BITS) + complete(&vec->finished); + } + return u ? IRQ_HANDLED : IRQ_NONE; +} diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/rp1/rp1-vec/vec_regs.h linux/drivers/gpu/drm/rp1/rp1-vec/vec_regs.h --- linux-6.1.66/drivers/gpu/drm/rp1/rp1-vec/vec_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/rp1/rp1-vec/vec_regs.h 2023-12-13 11:50:59.412986733 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +// ============================================================================= +// Copyright Raspberry Pi Ltd. 2023 +// vrbuild version: 56aac1a23c016cbbd229108f3b6efc1343842156-clean +// THIS FILE IS GENERATED BY VRBUILD - DO NOT EDIT +// ============================================================================= +// Register block : VEC +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef VEC_REGS_DEFINED +#define VEC_REGS_DEFINED +#define VEC_REGS_RWTYPE_MSB 13 +#define VEC_REGS_RWTYPE_LSB 12 +// ============================================================================= +// Register : VEC_CONTROL +// JTAG access : synchronous +// Description : None +#define VEC_CONTROL_OFFSET 0x00000000 +#define VEC_CONTROL_BITS 0x00000007 +#define VEC_CONTROL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_CONTROL_BARS +// Description : Write '1' to display colour bar test pattern +#define VEC_CONTROL_BARS_RESET 0x0 +#define VEC_CONTROL_BARS_BITS 0x00000004 +#define VEC_CONTROL_BARS_MSB 2 +#define VEC_CONTROL_BARS_LSB 2 +#define VEC_CONTROL_BARS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_CONTROL_AUTO_REPEAT +// Description : Write '1' to re-display same frame continuously +#define VEC_CONTROL_AUTO_REPEAT_RESET 0x0 +#define VEC_CONTROL_AUTO_REPEAT_BITS 0x00000002 +#define VEC_CONTROL_AUTO_REPEAT_MSB 1 +#define VEC_CONTROL_AUTO_REPEAT_LSB 1 +#define VEC_CONTROL_AUTO_REPEAT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_CONTROL_START_ARM +// Description : Write '1' before first DMA address is written This bit always +// reads back as '0' +#define VEC_CONTROL_START_ARM_RESET 0x0 +#define VEC_CONTROL_START_ARM_BITS 0x00000001 +#define VEC_CONTROL_START_ARM_MSB 0 +#define VEC_CONTROL_START_ARM_LSB 0 +#define VEC_CONTROL_START_ARM_ACCESS "SC" +// ============================================================================= +// Register : VEC_IRQ_ENABLES +// JTAG access : synchronous +// Description : None +#define VEC_IRQ_ENABLES_OFFSET 0x00000004 +#define VEC_IRQ_ENABLES_BITS 0x03ff003f +#define VEC_IRQ_ENABLES_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_IRQ_ENABLES_MATCH_ROW +// Description : Raster line at which MATCH interrupt is signalled +#define VEC_IRQ_ENABLES_MATCH_ROW_RESET 0x000 +#define VEC_IRQ_ENABLES_MATCH_ROW_BITS 0x03ff0000 +#define VEC_IRQ_ENABLES_MATCH_ROW_MSB 25 +#define VEC_IRQ_ENABLES_MATCH_ROW_LSB 16 +#define VEC_IRQ_ENABLES_MATCH_ROW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_IRQ_ENABLES_MATCH +// Description : Output raster == match_row reached +#define VEC_IRQ_ENABLES_MATCH_RESET 0x0 +#define VEC_IRQ_ENABLES_MATCH_BITS 0x00000020 +#define VEC_IRQ_ENABLES_MATCH_MSB 5 +#define VEC_IRQ_ENABLES_MATCH_LSB 5 +#define VEC_IRQ_ENABLES_MATCH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_IRQ_ENABLES_ERROR +// Description : DMA address overwritten before it was taken +#define VEC_IRQ_ENABLES_ERROR_RESET 0x0 +#define VEC_IRQ_ENABLES_ERROR_BITS 0x00000010 +#define VEC_IRQ_ENABLES_ERROR_MSB 4 +#define VEC_IRQ_ENABLES_ERROR_LSB 4 +#define VEC_IRQ_ENABLES_ERROR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_IRQ_ENABLES_DONE +// Description : Last word sent to DAC after end of video (= all clear) +#define VEC_IRQ_ENABLES_DONE_RESET 0x0 +#define VEC_IRQ_ENABLES_DONE_BITS 0x00000008 +#define VEC_IRQ_ENABLES_DONE_MSB 3 +#define VEC_IRQ_ENABLES_DONE_LSB 3 +#define VEC_IRQ_ENABLES_DONE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_IRQ_ENABLES_FRAME +// Description : Start of frame +#define VEC_IRQ_ENABLES_FRAME_RESET 0x0 +#define VEC_IRQ_ENABLES_FRAME_BITS 0x00000004 +#define VEC_IRQ_ENABLES_FRAME_MSB 2 +#define VEC_IRQ_ENABLES_FRAME_LSB 2 +#define VEC_IRQ_ENABLES_FRAME_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_IRQ_ENABLES_UNDERFLOW +// Description : Underflow has occurred +#define VEC_IRQ_ENABLES_UNDERFLOW_RESET 0x0 +#define VEC_IRQ_ENABLES_UNDERFLOW_BITS 0x00000002 +#define VEC_IRQ_ENABLES_UNDERFLOW_MSB 1 +#define VEC_IRQ_ENABLES_UNDERFLOW_LSB 1 +#define VEC_IRQ_ENABLES_UNDERFLOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_IRQ_ENABLES_DMA +// Description : DMA ready to accept next frame start address +#define VEC_IRQ_ENABLES_DMA_RESET 0x0 +#define VEC_IRQ_ENABLES_DMA_BITS 0x00000001 +#define VEC_IRQ_ENABLES_DMA_MSB 0 +#define VEC_IRQ_ENABLES_DMA_LSB 0 +#define VEC_IRQ_ENABLES_DMA_ACCESS "RW" +// ============================================================================= +// Register : VEC_IRQ_FLAGS +// JTAG access : synchronous +// Description : None +#define VEC_IRQ_FLAGS_OFFSET 0x00000008 +#define VEC_IRQ_FLAGS_BITS 0x0000003f +#define VEC_IRQ_FLAGS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_IRQ_FLAGS_MATCH +// Description : Output raster == match_row reached +#define VEC_IRQ_FLAGS_MATCH_RESET 0x0 +#define VEC_IRQ_FLAGS_MATCH_BITS 0x00000020 +#define VEC_IRQ_FLAGS_MATCH_MSB 5 +#define VEC_IRQ_FLAGS_MATCH_LSB 5 +#define VEC_IRQ_FLAGS_MATCH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : VEC_IRQ_FLAGS_ERROR +// Description : DMA address overwritten before it was taken +#define VEC_IRQ_FLAGS_ERROR_RESET 0x0 +#define VEC_IRQ_FLAGS_ERROR_BITS 0x00000010 +#define VEC_IRQ_FLAGS_ERROR_MSB 4 +#define VEC_IRQ_FLAGS_ERROR_LSB 4 +#define VEC_IRQ_FLAGS_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : VEC_IRQ_FLAGS_DONE +// Description : Last word sent to DAC after end of video (= all clear) +#define VEC_IRQ_FLAGS_DONE_RESET 0x0 +#define VEC_IRQ_FLAGS_DONE_BITS 0x00000008 +#define VEC_IRQ_FLAGS_DONE_MSB 3 +#define VEC_IRQ_FLAGS_DONE_LSB 3 +#define VEC_IRQ_FLAGS_DONE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : VEC_IRQ_FLAGS_FRAME +// Description : Start of frame +#define VEC_IRQ_FLAGS_FRAME_RESET 0x0 +#define VEC_IRQ_FLAGS_FRAME_BITS 0x00000004 +#define VEC_IRQ_FLAGS_FRAME_MSB 2 +#define VEC_IRQ_FLAGS_FRAME_LSB 2 +#define VEC_IRQ_FLAGS_FRAME_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : VEC_IRQ_FLAGS_UNDERFLOW +// Description : Underflow has occurred +#define VEC_IRQ_FLAGS_UNDERFLOW_RESET 0x0 +#define VEC_IRQ_FLAGS_UNDERFLOW_BITS 0x00000002 +#define VEC_IRQ_FLAGS_UNDERFLOW_MSB 1 +#define VEC_IRQ_FLAGS_UNDERFLOW_LSB 1 +#define VEC_IRQ_FLAGS_UNDERFLOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : VEC_IRQ_FLAGS_DMA +// Description : DMA ready to accept next frame start address +#define VEC_IRQ_FLAGS_DMA_RESET 0x0 +#define VEC_IRQ_FLAGS_DMA_BITS 0x00000001 +#define VEC_IRQ_FLAGS_DMA_MSB 0 +#define VEC_IRQ_FLAGS_DMA_LSB 0 +#define VEC_IRQ_FLAGS_DMA_ACCESS "WC" +// ============================================================================= +// Register : VEC_QOS +// JTAG access : synchronous +// Description : This register configures panic levels for the AXI ar_qos +// quality of service field. Panic status is driven by the number +// of rows held in the SRAM cache: +#define VEC_QOS_OFFSET 0x0000000c +#define VEC_QOS_BITS 0x000fffff +#define VEC_QOS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_QOS_UQOS +// Description : Upper AXI QOS +#define VEC_QOS_UQOS_RESET 0x0 +#define VEC_QOS_UQOS_BITS 0x000f0000 +#define VEC_QOS_UQOS_MSB 19 +#define VEC_QOS_UQOS_LSB 16 +#define VEC_QOS_UQOS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_QOS_ULEV +// Description : Upper trip level (resolution = 1 / 16 of cache size) +#define VEC_QOS_ULEV_RESET 0x0 +#define VEC_QOS_ULEV_BITS 0x0000f000 +#define VEC_QOS_ULEV_MSB 15 +#define VEC_QOS_ULEV_LSB 12 +#define VEC_QOS_ULEV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_QOS_LQOS +// Description : Lower AXI QOS +#define VEC_QOS_LQOS_RESET 0x0 +#define VEC_QOS_LQOS_BITS 0x00000f00 +#define VEC_QOS_LQOS_MSB 11 +#define VEC_QOS_LQOS_LSB 8 +#define VEC_QOS_LQOS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_QOS_LLEV +// Description : Lower trip level (resolution = 1 / 16 of cache size) +#define VEC_QOS_LLEV_RESET 0x0 +#define VEC_QOS_LLEV_BITS 0x000000f0 +#define VEC_QOS_LLEV_MSB 7 +#define VEC_QOS_LLEV_LSB 4 +#define VEC_QOS_LLEV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_QOS_DQOS +// Description : Default QOS +#define VEC_QOS_DQOS_RESET 0x0 +#define VEC_QOS_DQOS_BITS 0x0000000f +#define VEC_QOS_DQOS_MSB 3 +#define VEC_QOS_DQOS_LSB 0 +#define VEC_QOS_DQOS_ACCESS "RW" +// ============================================================================= +// Register : VEC_DMA_ADDR_L +// JTAG access : synchronous +// Description : Lower 32-bits +#define VEC_DMA_ADDR_L_OFFSET 0x00000010 +#define VEC_DMA_ADDR_L_BITS 0xffffffff +#define VEC_DMA_ADDR_L_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DMA_ADDR_L_AXI_ADDR +// Description : Byte address of DMA transfer frame buffer. +#define VEC_DMA_ADDR_L_AXI_ADDR_RESET 0x00000000 +#define VEC_DMA_ADDR_L_AXI_ADDR_BITS 0xffffffff +#define VEC_DMA_ADDR_L_AXI_ADDR_MSB 31 +#define VEC_DMA_ADDR_L_AXI_ADDR_LSB 0 +#define VEC_DMA_ADDR_L_AXI_ADDR_ACCESS "RWF" +// ============================================================================= +// Register : VEC_DMA_STRIDE +// JTAG access : synchronous +// Description : This register sets the line byte stride. +#define VEC_DMA_STRIDE_OFFSET 0x00000014 +#define VEC_DMA_STRIDE_BITS 0xffffffff +#define VEC_DMA_STRIDE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DMA_STRIDE_STRIDE +// Description : Byte stride +#define VEC_DMA_STRIDE_STRIDE_RESET 0x00000000 +#define VEC_DMA_STRIDE_STRIDE_BITS 0xffffffff +#define VEC_DMA_STRIDE_STRIDE_MSB 31 +#define VEC_DMA_STRIDE_STRIDE_LSB 0 +#define VEC_DMA_STRIDE_STRIDE_ACCESS "RW" +// ============================================================================= +// Register : VEC_DMA_AREA +// JTAG access : synchronous +// Description : Interlaced pixel area. See example driver code. +#define VEC_DMA_AREA_OFFSET 0x00000018 +#define VEC_DMA_AREA_BITS 0x03ff03ff +#define VEC_DMA_AREA_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DMA_AREA_COLS_MINUS1 +// Description : Width +#define VEC_DMA_AREA_COLS_MINUS1_RESET 0x000 +#define VEC_DMA_AREA_COLS_MINUS1_BITS 0x03ff0000 +#define VEC_DMA_AREA_COLS_MINUS1_MSB 25 +#define VEC_DMA_AREA_COLS_MINUS1_LSB 16 +#define VEC_DMA_AREA_COLS_MINUS1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1 +// Description : Lines per field = half of lines per interlaced frame +#define VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1_RESET 0x000 +#define VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1_BITS 0x000003ff +#define VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1_MSB 9 +#define VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1_LSB 0 +#define VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1_ACCESS "RW" +// ============================================================================= +// Register : VEC_YUV_SCALING +// JTAG access : synchronous +// Description : None +#define VEC_YUV_SCALING_OFFSET 0x0000001c +#define VEC_YUV_SCALING_BITS 0x3fffffff +#define VEC_YUV_SCALING_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_YUV_SCALING_U10_SCALE_Y +// Description : Y unsigned scaling factor - 8 binary places +#define VEC_YUV_SCALING_U10_SCALE_Y_RESET 0x000 +#define VEC_YUV_SCALING_U10_SCALE_Y_BITS 0x3ff00000 +#define VEC_YUV_SCALING_U10_SCALE_Y_MSB 29 +#define VEC_YUV_SCALING_U10_SCALE_Y_LSB 20 +#define VEC_YUV_SCALING_U10_SCALE_Y_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_YUV_SCALING_S10_SCALE_U +// Description : U signed scaling factor - 8 binary places +#define VEC_YUV_SCALING_S10_SCALE_U_RESET 0x000 +#define VEC_YUV_SCALING_S10_SCALE_U_BITS 0x000ffc00 +#define VEC_YUV_SCALING_S10_SCALE_U_MSB 19 +#define VEC_YUV_SCALING_S10_SCALE_U_LSB 10 +#define VEC_YUV_SCALING_S10_SCALE_U_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_YUV_SCALING_S10_SCALE_V +// Description : V signed scaling factor - 8 binary please +#define VEC_YUV_SCALING_S10_SCALE_V_RESET 0x000 +#define VEC_YUV_SCALING_S10_SCALE_V_BITS 0x000003ff +#define VEC_YUV_SCALING_S10_SCALE_V_MSB 9 +#define VEC_YUV_SCALING_S10_SCALE_V_LSB 0 +#define VEC_YUV_SCALING_S10_SCALE_V_ACCESS "RW" +// ============================================================================= +// Register : VEC_BACK_PORCH +// JTAG access : synchronous +// Description : None +#define VEC_BACK_PORCH_OFFSET 0x00000020 +#define VEC_BACK_PORCH_BITS 0x03ff03ff +#define VEC_BACK_PORCH_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_BACK_PORCH_HBP_MINUS1 +// Description : Horizontal back porch +#define VEC_BACK_PORCH_HBP_MINUS1_RESET 0x000 +#define VEC_BACK_PORCH_HBP_MINUS1_BITS 0x03ff0000 +#define VEC_BACK_PORCH_HBP_MINUS1_MSB 25 +#define VEC_BACK_PORCH_HBP_MINUS1_LSB 16 +#define VEC_BACK_PORCH_HBP_MINUS1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_BACK_PORCH_VBP_MINUS1 +// Description : Vertical back porch +#define VEC_BACK_PORCH_VBP_MINUS1_RESET 0x000 +#define VEC_BACK_PORCH_VBP_MINUS1_BITS 0x000003ff +#define VEC_BACK_PORCH_VBP_MINUS1_MSB 9 +#define VEC_BACK_PORCH_VBP_MINUS1_LSB 0 +#define VEC_BACK_PORCH_VBP_MINUS1_ACCESS "RW" +// ============================================================================= +// Register : VEC_FRONT_PORCH +// JTAG access : synchronous +// Description : None +#define VEC_FRONT_PORCH_OFFSET 0x00000024 +#define VEC_FRONT_PORCH_BITS 0x03ff03ff +#define VEC_FRONT_PORCH_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_FRONT_PORCH_HFP_MINUS1 +// Description : Horizontal front porch +#define VEC_FRONT_PORCH_HFP_MINUS1_RESET 0x000 +#define VEC_FRONT_PORCH_HFP_MINUS1_BITS 0x03ff0000 +#define VEC_FRONT_PORCH_HFP_MINUS1_MSB 25 +#define VEC_FRONT_PORCH_HFP_MINUS1_LSB 16 +#define VEC_FRONT_PORCH_HFP_MINUS1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_FRONT_PORCH_VFP_MINUS1 +// Description : Vertical front porch +#define VEC_FRONT_PORCH_VFP_MINUS1_RESET 0x000 +#define VEC_FRONT_PORCH_VFP_MINUS1_BITS 0x000003ff +#define VEC_FRONT_PORCH_VFP_MINUS1_MSB 9 +#define VEC_FRONT_PORCH_VFP_MINUS1_LSB 0 +#define VEC_FRONT_PORCH_VFP_MINUS1_ACCESS "RW" +// ============================================================================= +// Register : VEC_SHIFT +// JTAG access : synchronous +// Description : Positions of R,G,B MS bits in the memory word. Note: due to an +// unintended red/blue swap, these fields have been renamed since +// a previous version. There is no functional change. +#define VEC_SHIFT_OFFSET 0x00000028 +#define VEC_SHIFT_BITS 0x00007fff +#define VEC_SHIFT_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_SHIFT_SHIFT_R +// Description : Red MSB +#define VEC_SHIFT_SHIFT_R_RESET 0x00 +#define VEC_SHIFT_SHIFT_R_BITS 0x00007c00 +#define VEC_SHIFT_SHIFT_R_MSB 14 +#define VEC_SHIFT_SHIFT_R_LSB 10 +#define VEC_SHIFT_SHIFT_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_SHIFT_SHIFT_G +// Description : Green MSB +#define VEC_SHIFT_SHIFT_G_RESET 0x00 +#define VEC_SHIFT_SHIFT_G_BITS 0x000003e0 +#define VEC_SHIFT_SHIFT_G_MSB 9 +#define VEC_SHIFT_SHIFT_G_LSB 5 +#define VEC_SHIFT_SHIFT_G_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_SHIFT_SHIFT_B +// Description : Blue MSB +#define VEC_SHIFT_SHIFT_B_RESET 0x00 +#define VEC_SHIFT_SHIFT_B_BITS 0x0000001f +#define VEC_SHIFT_SHIFT_B_MSB 4 +#define VEC_SHIFT_SHIFT_B_LSB 0 +#define VEC_SHIFT_SHIFT_B_ACCESS "RW" +// ============================================================================= +// Register : VEC_IMASK +// JTAG access : synchronous +// Description : Masks for R,G,B significant bits, left-justified within 10-bit +// fields. +#define VEC_IMASK_OFFSET 0x0000002c +#define VEC_IMASK_BITS 0x3fffffff +#define VEC_IMASK_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_IMASK_MASK_R +// Description : Red mask +#define VEC_IMASK_MASK_R_RESET 0x000 +#define VEC_IMASK_MASK_R_BITS 0x3ff00000 +#define VEC_IMASK_MASK_R_MSB 29 +#define VEC_IMASK_MASK_R_LSB 20 +#define VEC_IMASK_MASK_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_IMASK_MASK_G +// Description : Green mask +#define VEC_IMASK_MASK_G_RESET 0x000 +#define VEC_IMASK_MASK_G_BITS 0x000ffc00 +#define VEC_IMASK_MASK_G_MSB 19 +#define VEC_IMASK_MASK_G_LSB 10 +#define VEC_IMASK_MASK_G_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_IMASK_MASK_B +// Description : Blue mask +#define VEC_IMASK_MASK_B_RESET 0x000 +#define VEC_IMASK_MASK_B_BITS 0x000003ff +#define VEC_IMASK_MASK_B_MSB 9 +#define VEC_IMASK_MASK_B_LSB 0 +#define VEC_IMASK_MASK_B_ACCESS "RW" +// ============================================================================= +// Register : VEC_MODE +// JTAG access : synchronous +// Description : None +#define VEC_MODE_OFFSET 0x00000030 +#define VEC_MODE_BITS 0x01ff003f +#define VEC_MODE_RESET 0x01c00000 +// ----------------------------------------------------------------------------- +// Field : VEC_MODE_HIGH_WATER +// Description : ALWAYS WRITE 8'hE0 +#define VEC_MODE_HIGH_WATER_RESET 0xe0 +#define VEC_MODE_HIGH_WATER_BITS 0x01fe0000 +#define VEC_MODE_HIGH_WATER_MSB 24 +#define VEC_MODE_HIGH_WATER_LSB 17 +#define VEC_MODE_HIGH_WATER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_MODE_ALIGN16 +// Description : Data: 0=BYTE aligned; 1=BEAT aligned +#define VEC_MODE_ALIGN16_RESET 0x0 +#define VEC_MODE_ALIGN16_BITS 0x00010000 +#define VEC_MODE_ALIGN16_MSB 16 +#define VEC_MODE_ALIGN16_LSB 16 +#define VEC_MODE_ALIGN16_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_MODE_VFP_EN +// Description : Enable vertical front porch +#define VEC_MODE_VFP_EN_RESET 0x0 +#define VEC_MODE_VFP_EN_BITS 0x00000020 +#define VEC_MODE_VFP_EN_MSB 5 +#define VEC_MODE_VFP_EN_LSB 5 +#define VEC_MODE_VFP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_MODE_VBP_EN +// Description : Enable vertical back porch +#define VEC_MODE_VBP_EN_RESET 0x0 +#define VEC_MODE_VBP_EN_BITS 0x00000010 +#define VEC_MODE_VBP_EN_MSB 4 +#define VEC_MODE_VBP_EN_LSB 4 +#define VEC_MODE_VBP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_MODE_HFP_EN +// Description : Enable horizontal front porch +#define VEC_MODE_HFP_EN_RESET 0x0 +#define VEC_MODE_HFP_EN_BITS 0x00000008 +#define VEC_MODE_HFP_EN_MSB 3 +#define VEC_MODE_HFP_EN_LSB 3 +#define VEC_MODE_HFP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_MODE_HBP_EN +// Description : Enable horizontal back porch +#define VEC_MODE_HBP_EN_RESET 0x0 +#define VEC_MODE_HBP_EN_BITS 0x00000004 +#define VEC_MODE_HBP_EN_MSB 2 +#define VEC_MODE_HBP_EN_LSB 2 +#define VEC_MODE_HBP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_MODE_FIELDS_PER_FRAME_MINUS1 +// Description : Interlaced / progressive +#define VEC_MODE_FIELDS_PER_FRAME_MINUS1_RESET 0x0 +#define VEC_MODE_FIELDS_PER_FRAME_MINUS1_BITS 0x00000002 +#define VEC_MODE_FIELDS_PER_FRAME_MINUS1_MSB 1 +#define VEC_MODE_FIELDS_PER_FRAME_MINUS1_LSB 1 +#define VEC_MODE_FIELDS_PER_FRAME_MINUS1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_MODE_FIRST_FIELD_ODD +// Description : Interlacing order: odd/even or even/odd +#define VEC_MODE_FIRST_FIELD_ODD_RESET 0x0 +#define VEC_MODE_FIRST_FIELD_ODD_BITS 0x00000001 +#define VEC_MODE_FIRST_FIELD_ODD_MSB 0 +#define VEC_MODE_FIRST_FIELD_ODD_LSB 0 +#define VEC_MODE_FIRST_FIELD_ODD_ACCESS "RW" +// ============================================================================= +// Register : VEC_RGBSZ +// JTAG access : synchronous +// Description : None +#define VEC_RGBSZ_OFFSET 0x00000034 +#define VEC_RGBSZ_BITS 0x00030fff +#define VEC_RGBSZ_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1 +// Description : Pixel stride +#define VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1_RESET 0x0 +#define VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1_BITS 0x00030000 +#define VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1_MSB 17 +#define VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1_LSB 16 +#define VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_RGBSZ_SCALE_R +// Description : Red number of bits for shift-and-OR scaling +#define VEC_RGBSZ_SCALE_R_RESET 0x0 +#define VEC_RGBSZ_SCALE_R_BITS 0x00000f00 +#define VEC_RGBSZ_SCALE_R_MSB 11 +#define VEC_RGBSZ_SCALE_R_LSB 8 +#define VEC_RGBSZ_SCALE_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_RGBSZ_SCALE_G +// Description : Green number of bits for shift-and-OR scaling +#define VEC_RGBSZ_SCALE_G_RESET 0x0 +#define VEC_RGBSZ_SCALE_G_BITS 0x000000f0 +#define VEC_RGBSZ_SCALE_G_MSB 7 +#define VEC_RGBSZ_SCALE_G_LSB 4 +#define VEC_RGBSZ_SCALE_G_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_RGBSZ_SCALE_B +// Description : Blue number of bits for shift-and-OR scaling +#define VEC_RGBSZ_SCALE_B_RESET 0x0 +#define VEC_RGBSZ_SCALE_B_BITS 0x0000000f +#define VEC_RGBSZ_SCALE_B_MSB 3 +#define VEC_RGBSZ_SCALE_B_LSB 0 +#define VEC_RGBSZ_SCALE_B_ACCESS "RW" +// ============================================================================= +// Register : VEC_PANICS +// JTAG access : synchronous +// Description : None +#define VEC_PANICS_OFFSET 0x00000038 +#define VEC_PANICS_BITS 0xffffffff +#define VEC_PANICS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_PANICS_UCOUNT +// Description : Upper panic count +#define VEC_PANICS_UCOUNT_RESET 0x0000 +#define VEC_PANICS_UCOUNT_BITS 0xffff0000 +#define VEC_PANICS_UCOUNT_MSB 31 +#define VEC_PANICS_UCOUNT_LSB 16 +#define VEC_PANICS_UCOUNT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : VEC_PANICS_LCOUNT +// Description : Lower panic count +#define VEC_PANICS_LCOUNT_RESET 0x0000 +#define VEC_PANICS_LCOUNT_BITS 0x0000ffff +#define VEC_PANICS_LCOUNT_MSB 15 +#define VEC_PANICS_LCOUNT_LSB 0 +#define VEC_PANICS_LCOUNT_ACCESS "WC" +// ============================================================================= +// Register : VEC_STATUS +// JTAG access : synchronous +// Description : None +#define VEC_STATUS_OFFSET 0x0000003c +#define VEC_STATUS_BITS 0xff000000 +#define VEC_STATUS_RESET 0x0d000000 +// ----------------------------------------------------------------------------- +// Field : VEC_STATUS_VERSION +// Description : VEC module version code +#define VEC_STATUS_VERSION_RESET 0x0d +#define VEC_STATUS_VERSION_BITS 0xff000000 +#define VEC_STATUS_VERSION_MSB 31 +#define VEC_STATUS_VERSION_LSB 24 +#define VEC_STATUS_VERSION_ACCESS "RO" +// ============================================================================= +// Register : VEC_DMA_ADDR_H +// JTAG access : synchronous +// Description : Upper 32-bits +#define VEC_DMA_ADDR_H_OFFSET 0x00000040 +#define VEC_DMA_ADDR_H_BITS 0xffffffff +#define VEC_DMA_ADDR_H_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DMA_ADDR_H_AXI_ADDR +// Description : Byte address of DMA transfer frame buffer. +#define VEC_DMA_ADDR_H_AXI_ADDR_RESET 0x00000000 +#define VEC_DMA_ADDR_H_AXI_ADDR_BITS 0xffffffff +#define VEC_DMA_ADDR_H_AXI_ADDR_MSB 31 +#define VEC_DMA_ADDR_H_AXI_ADDR_LSB 0 +#define VEC_DMA_ADDR_H_AXI_ADDR_ACCESS "RW" +// ============================================================================= +// Register : VEC_BURST_ADDR_L +// JTAG access : synchronous +// Description : None +#define VEC_BURST_ADDR_L_OFFSET 0x00000044 +#define VEC_BURST_ADDR_L_BITS 0xffffffff +#define VEC_BURST_ADDR_L_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_BURST_ADDR_L_BURST_ADDR +// Description : the lower 32-bits of the most recent read request sent to AXI +// memory. +#define VEC_BURST_ADDR_L_BURST_ADDR_RESET 0x00000000 +#define VEC_BURST_ADDR_L_BURST_ADDR_BITS 0xffffffff +#define VEC_BURST_ADDR_L_BURST_ADDR_MSB 31 +#define VEC_BURST_ADDR_L_BURST_ADDR_LSB 0 +#define VEC_BURST_ADDR_L_BURST_ADDR_ACCESS "RO" +// ============================================================================= +// Register : VEC_APB_TIMEOUT +// JTAG access : synchronous +// Description : None +#define VEC_APB_TIMEOUT_OFFSET 0x00000048 +#define VEC_APB_TIMEOUT_BITS 0x000103ff +#define VEC_APB_TIMEOUT_RESET 0x00000014 +// ----------------------------------------------------------------------------- +// Field : VEC_APB_TIMEOUT_SLVERR_EN +// Description : 1 = Assert PREADY and PSLVERR on timeout 0 = Assert PREADY only +#define VEC_APB_TIMEOUT_SLVERR_EN_RESET 0x0 +#define VEC_APB_TIMEOUT_SLVERR_EN_BITS 0x00010000 +#define VEC_APB_TIMEOUT_SLVERR_EN_MSB 16 +#define VEC_APB_TIMEOUT_SLVERR_EN_LSB 16 +#define VEC_APB_TIMEOUT_SLVERR_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_APB_TIMEOUT_TIMEOUT +// Description : Maximum AXI clock cycles to wait for responses from DAC clock +// domain APB block +#define VEC_APB_TIMEOUT_TIMEOUT_RESET 0x014 +#define VEC_APB_TIMEOUT_TIMEOUT_BITS 0x000003ff +#define VEC_APB_TIMEOUT_TIMEOUT_MSB 9 +#define VEC_APB_TIMEOUT_TIMEOUT_LSB 0 +#define VEC_APB_TIMEOUT_TIMEOUT_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_80 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_80_OFFSET 0x00000080 +#define VEC_DAC_80_BITS 0x3fff3fff +#define VEC_DAC_80_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_80_U14_DE_BGN +// Description : Beginning of active data enable within each visible line +#define VEC_DAC_80_U14_DE_BGN_RESET 0x0000 +#define VEC_DAC_80_U14_DE_BGN_BITS 0x3fff0000 +#define VEC_DAC_80_U14_DE_BGN_MSB 29 +#define VEC_DAC_80_U14_DE_BGN_LSB 16 +#define VEC_DAC_80_U14_DE_BGN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_80_U14_DE_END +// Description : End of active data enable within each visible line +#define VEC_DAC_80_U14_DE_END_RESET 0x0000 +#define VEC_DAC_80_U14_DE_END_BITS 0x00003fff +#define VEC_DAC_80_U14_DE_END_MSB 13 +#define VEC_DAC_80_U14_DE_END_LSB 0 +#define VEC_DAC_80_U14_DE_END_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_84 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_84_OFFSET 0x00000084 +#define VEC_DAC_84_BITS 0x1fff1fff +#define VEC_DAC_84_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_84_U13_ACTIVE_RISE +// Description : Horizontal blanking interval +#define VEC_DAC_84_U13_ACTIVE_RISE_RESET 0x0000 +#define VEC_DAC_84_U13_ACTIVE_RISE_BITS 0x1fff0000 +#define VEC_DAC_84_U13_ACTIVE_RISE_MSB 28 +#define VEC_DAC_84_U13_ACTIVE_RISE_LSB 16 +#define VEC_DAC_84_U13_ACTIVE_RISE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_84_U13_ACTIVE_FALL +// Description : Horizontal blanking interval +#define VEC_DAC_84_U13_ACTIVE_FALL_RESET 0x0000 +#define VEC_DAC_84_U13_ACTIVE_FALL_BITS 0x00001fff +#define VEC_DAC_84_U13_ACTIVE_FALL_MSB 12 +#define VEC_DAC_84_U13_ACTIVE_FALL_LSB 0 +#define VEC_DAC_84_U13_ACTIVE_FALL_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_88 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_88_OFFSET 0x00000088 +#define VEC_DAC_88_BITS 0x1fff1fff +#define VEC_DAC_88_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_88_U13_HALF_LINE_PERIOD +// Description : Ratio of DAC clock to horizontal line rate, halved +#define VEC_DAC_88_U13_HALF_LINE_PERIOD_RESET 0x0000 +#define VEC_DAC_88_U13_HALF_LINE_PERIOD_BITS 0x1fff0000 +#define VEC_DAC_88_U13_HALF_LINE_PERIOD_MSB 28 +#define VEC_DAC_88_U13_HALF_LINE_PERIOD_LSB 16 +#define VEC_DAC_88_U13_HALF_LINE_PERIOD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_88_U13_HORZ_SYNC +// Description : Width of horizontal sync pulses +#define VEC_DAC_88_U13_HORZ_SYNC_RESET 0x0000 +#define VEC_DAC_88_U13_HORZ_SYNC_BITS 0x00001fff +#define VEC_DAC_88_U13_HORZ_SYNC_MSB 12 +#define VEC_DAC_88_U13_HORZ_SYNC_LSB 0 +#define VEC_DAC_88_U13_HORZ_SYNC_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_8C +// JTAG access : synchronous +// Description : None +#define VEC_DAC_8C_OFFSET 0x0000008c +#define VEC_DAC_8C_BITS 0x1fff1fff +#define VEC_DAC_8C_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_8C_U13_BURST_RISE +// Description : Start of raised-cosine colour burst envelope +#define VEC_DAC_8C_U13_BURST_RISE_RESET 0x0000 +#define VEC_DAC_8C_U13_BURST_RISE_BITS 0x1fff0000 +#define VEC_DAC_8C_U13_BURST_RISE_MSB 28 +#define VEC_DAC_8C_U13_BURST_RISE_LSB 16 +#define VEC_DAC_8C_U13_BURST_RISE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_8C_U13_BURST_FALL +// Description : End of raised-cosine colour burst envelope +#define VEC_DAC_8C_U13_BURST_FALL_RESET 0x0000 +#define VEC_DAC_8C_U13_BURST_FALL_BITS 0x00001fff +#define VEC_DAC_8C_U13_BURST_FALL_MSB 12 +#define VEC_DAC_8C_U13_BURST_FALL_LSB 0 +#define VEC_DAC_8C_U13_BURST_FALL_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_90 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_90_OFFSET 0x00000090 +#define VEC_DAC_90_BITS 0x1fff3fff +#define VEC_DAC_90_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_90_U13_VERT_EQ +// Description : Width of vertical equalisation pulses (= half line minus +// serration) +#define VEC_DAC_90_U13_VERT_EQ_RESET 0x0000 +#define VEC_DAC_90_U13_VERT_EQ_BITS 0x1fff0000 +#define VEC_DAC_90_U13_VERT_EQ_MSB 28 +#define VEC_DAC_90_U13_VERT_EQ_LSB 16 +#define VEC_DAC_90_U13_VERT_EQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_90_U14_VERT_SYNC +// Description : Width of vertical sync pulses +#define VEC_DAC_90_U14_VERT_SYNC_RESET 0x0000 +#define VEC_DAC_90_U14_VERT_SYNC_BITS 0x00003fff +#define VEC_DAC_90_U14_VERT_SYNC_MSB 13 +#define VEC_DAC_90_U14_VERT_SYNC_LSB 0 +#define VEC_DAC_90_U14_VERT_SYNC_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_94 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_94_OFFSET 0x00000094 +#define VEC_DAC_94_BITS 0x03ff03ff +#define VEC_DAC_94_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_94_U10_PRE_EQ_BGN +// Description : Half-lines, inclusive, relative to field datum, where vertical +// pre-equalisation pulses start +#define VEC_DAC_94_U10_PRE_EQ_BGN_RESET 0x000 +#define VEC_DAC_94_U10_PRE_EQ_BGN_BITS 0x03ff0000 +#define VEC_DAC_94_U10_PRE_EQ_BGN_MSB 25 +#define VEC_DAC_94_U10_PRE_EQ_BGN_LSB 16 +#define VEC_DAC_94_U10_PRE_EQ_BGN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_94_U10_PRE_EQ_END +// Description : Half-lines, inclusive, relative to field datum, where vertical +// pre-equalisation pulses end +#define VEC_DAC_94_U10_PRE_EQ_END_RESET 0x000 +#define VEC_DAC_94_U10_PRE_EQ_END_BITS 0x000003ff +#define VEC_DAC_94_U10_PRE_EQ_END_MSB 9 +#define VEC_DAC_94_U10_PRE_EQ_END_LSB 0 +#define VEC_DAC_94_U10_PRE_EQ_END_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_98 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_98_OFFSET 0x00000098 +#define VEC_DAC_98_BITS 0x03ff03ff +#define VEC_DAC_98_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_98_U10_FIELD_SYNC_BGN +// Description : Half-lines containing vertical sync pulses (inclusive) +#define VEC_DAC_98_U10_FIELD_SYNC_BGN_RESET 0x000 +#define VEC_DAC_98_U10_FIELD_SYNC_BGN_BITS 0x03ff0000 +#define VEC_DAC_98_U10_FIELD_SYNC_BGN_MSB 25 +#define VEC_DAC_98_U10_FIELD_SYNC_BGN_LSB 16 +#define VEC_DAC_98_U10_FIELD_SYNC_BGN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_98_U10_FIELD_SYNC_END +// Description : Half-lines containing vertical sync pulses (inclusive) +#define VEC_DAC_98_U10_FIELD_SYNC_END_RESET 0x000 +#define VEC_DAC_98_U10_FIELD_SYNC_END_BITS 0x000003ff +#define VEC_DAC_98_U10_FIELD_SYNC_END_MSB 9 +#define VEC_DAC_98_U10_FIELD_SYNC_END_LSB 0 +#define VEC_DAC_98_U10_FIELD_SYNC_END_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_9C +// JTAG access : synchronous +// Description : None +#define VEC_DAC_9C_OFFSET 0x0000009c +#define VEC_DAC_9C_BITS 0x03ff03ff +#define VEC_DAC_9C_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_9C_U10_POST_EQ_BGN +// Description : Half-lines containing vertical post-equalisation pulses +#define VEC_DAC_9C_U10_POST_EQ_BGN_RESET 0x000 +#define VEC_DAC_9C_U10_POST_EQ_BGN_BITS 0x03ff0000 +#define VEC_DAC_9C_U10_POST_EQ_BGN_MSB 25 +#define VEC_DAC_9C_U10_POST_EQ_BGN_LSB 16 +#define VEC_DAC_9C_U10_POST_EQ_BGN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_9C_U10_POST_EQ_END +// Description : Half-lines containing vertical post-equalisation pulses +#define VEC_DAC_9C_U10_POST_EQ_END_RESET 0x000 +#define VEC_DAC_9C_U10_POST_EQ_END_BITS 0x000003ff +#define VEC_DAC_9C_U10_POST_EQ_END_MSB 9 +#define VEC_DAC_9C_U10_POST_EQ_END_LSB 0 +#define VEC_DAC_9C_U10_POST_EQ_END_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_A0 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_A0_OFFSET 0x000000a0 +#define VEC_DAC_A0_BITS 0x03ff03ff +#define VEC_DAC_A0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_A0_U10_FLD1_BURST_BGN +// Description : First and last full frame lines (1-based numbering) within the +// PAL/NTSC four field sequence which require a colour burst +#define VEC_DAC_A0_U10_FLD1_BURST_BGN_RESET 0x000 +#define VEC_DAC_A0_U10_FLD1_BURST_BGN_BITS 0x03ff0000 +#define VEC_DAC_A0_U10_FLD1_BURST_BGN_MSB 25 +#define VEC_DAC_A0_U10_FLD1_BURST_BGN_LSB 16 +#define VEC_DAC_A0_U10_FLD1_BURST_BGN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_A0_U10_FLD1_BURST_END +// Description : First and last full frame lines (1-based numbering) within the +// PAL/NTSC four field sequence which require a colour burst +#define VEC_DAC_A0_U10_FLD1_BURST_END_RESET 0x000 +#define VEC_DAC_A0_U10_FLD1_BURST_END_BITS 0x000003ff +#define VEC_DAC_A0_U10_FLD1_BURST_END_MSB 9 +#define VEC_DAC_A0_U10_FLD1_BURST_END_LSB 0 +#define VEC_DAC_A0_U10_FLD1_BURST_END_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_A4 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_A4_OFFSET 0x000000a4 +#define VEC_DAC_A4_BITS 0x03ff03ff +#define VEC_DAC_A4_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_A4_U10_FLD2_BURST_BGN +// Description : First and last full frame lines (1-based numbering) within the +// PAL/NTSC four field sequence which require a colour burst +#define VEC_DAC_A4_U10_FLD2_BURST_BGN_RESET 0x000 +#define VEC_DAC_A4_U10_FLD2_BURST_BGN_BITS 0x03ff0000 +#define VEC_DAC_A4_U10_FLD2_BURST_BGN_MSB 25 +#define VEC_DAC_A4_U10_FLD2_BURST_BGN_LSB 16 +#define VEC_DAC_A4_U10_FLD2_BURST_BGN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_A4_U10_FLD2_BURST_END +// Description : First and last full frame lines (1-based numbering) within the +// PAL/NTSC four field sequence which require a colour burst +#define VEC_DAC_A4_U10_FLD2_BURST_END_RESET 0x000 +#define VEC_DAC_A4_U10_FLD2_BURST_END_BITS 0x000003ff +#define VEC_DAC_A4_U10_FLD2_BURST_END_MSB 9 +#define VEC_DAC_A4_U10_FLD2_BURST_END_LSB 0 +#define VEC_DAC_A4_U10_FLD2_BURST_END_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_A8 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_A8_OFFSET 0x000000a8 +#define VEC_DAC_A8_BITS 0x03ff03ff +#define VEC_DAC_A8_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_A8_U10_FLD3_BURST_BGN +// Description : First and last full frame lines (1-based numbering) within the +// PAL/NTSC four field sequence which require a colour burst +#define VEC_DAC_A8_U10_FLD3_BURST_BGN_RESET 0x000 +#define VEC_DAC_A8_U10_FLD3_BURST_BGN_BITS 0x03ff0000 +#define VEC_DAC_A8_U10_FLD3_BURST_BGN_MSB 25 +#define VEC_DAC_A8_U10_FLD3_BURST_BGN_LSB 16 +#define VEC_DAC_A8_U10_FLD3_BURST_BGN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_A8_U10_FLD3_BURST_END +// Description : First and last full frame lines (1-based numbering) within the +// PAL/NTSC four field sequence which require a colour burst +#define VEC_DAC_A8_U10_FLD3_BURST_END_RESET 0x000 +#define VEC_DAC_A8_U10_FLD3_BURST_END_BITS 0x000003ff +#define VEC_DAC_A8_U10_FLD3_BURST_END_MSB 9 +#define VEC_DAC_A8_U10_FLD3_BURST_END_LSB 0 +#define VEC_DAC_A8_U10_FLD3_BURST_END_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_AC +// JTAG access : synchronous +// Description : None +#define VEC_DAC_AC_OFFSET 0x000000ac +#define VEC_DAC_AC_BITS 0x03ff03ff +#define VEC_DAC_AC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_AC_U10_FLD4_BURST_BGN +// Description : First and last full frame lines (1-based numbering) within the +// PAL/NTSC four field sequence which require a colour burst +#define VEC_DAC_AC_U10_FLD4_BURST_BGN_RESET 0x000 +#define VEC_DAC_AC_U10_FLD4_BURST_BGN_BITS 0x03ff0000 +#define VEC_DAC_AC_U10_FLD4_BURST_BGN_MSB 25 +#define VEC_DAC_AC_U10_FLD4_BURST_BGN_LSB 16 +#define VEC_DAC_AC_U10_FLD4_BURST_BGN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_AC_U10_FLD4_BURST_END +// Description : First and last full frame lines (1-based numbering) within the +// PAL/NTSC four field sequence which require a colour burst +#define VEC_DAC_AC_U10_FLD4_BURST_END_RESET 0x000 +#define VEC_DAC_AC_U10_FLD4_BURST_END_BITS 0x000003ff +#define VEC_DAC_AC_U10_FLD4_BURST_END_MSB 9 +#define VEC_DAC_AC_U10_FLD4_BURST_END_LSB 0 +#define VEC_DAC_AC_U10_FLD4_BURST_END_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_B0 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_B0_OFFSET 0x000000b0 +#define VEC_DAC_B0_BITS 0x03ff03ff +#define VEC_DAC_B0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_B0_U10_FLD24_FULL_LINE_BGN +// Description : First and last full visible lines (1-based numbering) in the +// PAL/NTSC four field sequence +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_BGN_RESET 0x000 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_BGN_BITS 0x03ff0000 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_BGN_MSB 25 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_BGN_LSB 16 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_BGN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_B0_U10_FLD24_FULL_LINE_END +// Description : First and last full visible lines (1-based numbering) in the +// PAL/NTSC four field sequence +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_END_RESET 0x000 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_END_BITS 0x000003ff +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_END_MSB 9 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_END_LSB 0 +#define VEC_DAC_B0_U10_FLD24_FULL_LINE_END_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_B4 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_B4_OFFSET 0x000000b4 +#define VEC_DAC_B4_BITS 0x03ff03ff +#define VEC_DAC_B4_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_B4_U10_FLD13_FULL_LINE_BGN +// Description : First and last full visible lines (1-based numbering) in the +// PAL/NTSC four field sequence +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_BGN_RESET 0x000 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_BGN_BITS 0x03ff0000 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_BGN_MSB 25 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_BGN_LSB 16 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_BGN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_B4_U10_FLD13_FULL_LINE_END +// Description : First and last full visible lines (1-based numbering) in the +// PAL/NTSC four field sequence +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_END_RESET 0x000 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_END_BITS 0x000003ff +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_END_MSB 9 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_END_LSB 0 +#define VEC_DAC_B4_U10_FLD13_FULL_LINE_END_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_B8 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_B8_OFFSET 0x000000b8 +#define VEC_DAC_B8_BITS 0x03ff03ff +#define VEC_DAC_B8_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_B8_U10_BOT_HALF_LINE +// Description : Top and bottom visible half-lines in 1-based standard full +// frame numbering, for interlaced modes. Set to zero to disable. +#define VEC_DAC_B8_U10_BOT_HALF_LINE_RESET 0x000 +#define VEC_DAC_B8_U10_BOT_HALF_LINE_BITS 0x03ff0000 +#define VEC_DAC_B8_U10_BOT_HALF_LINE_MSB 25 +#define VEC_DAC_B8_U10_BOT_HALF_LINE_LSB 16 +#define VEC_DAC_B8_U10_BOT_HALF_LINE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_B8_U10_TOP_HALF_LINE +// Description : Top and bottom visible half-lines in 1-based standard full +// frame numbering, for interlaced modes. Set to zero to disable. +#define VEC_DAC_B8_U10_TOP_HALF_LINE_RESET 0x000 +#define VEC_DAC_B8_U10_TOP_HALF_LINE_BITS 0x000003ff +#define VEC_DAC_B8_U10_TOP_HALF_LINE_MSB 9 +#define VEC_DAC_B8_U10_TOP_HALF_LINE_LSB 0 +#define VEC_DAC_B8_U10_TOP_HALF_LINE_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_BC +// JTAG access : synchronous +// Description : None +#define VEC_DAC_BC_OFFSET 0x000000bc +#define VEC_DAC_BC_BITS 0x07ff07ff +#define VEC_DAC_BC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_BC_S11_PEDESTAL +// Description : NTSC pedestal. For 7.5 IRE, this field is 1024 * 7.5/100. For +// PAL, or Japanese NTSC, this field should be zero. +#define VEC_DAC_BC_S11_PEDESTAL_RESET 0x000 +#define VEC_DAC_BC_S11_PEDESTAL_BITS 0x07ff0000 +#define VEC_DAC_BC_S11_PEDESTAL_MSB 26 +#define VEC_DAC_BC_S11_PEDESTAL_LSB 16 +#define VEC_DAC_BC_S11_PEDESTAL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_BC_U11_HALF_LINES_PER_FIELD +// Description : Mode = 625 PAL, Lines per field = 312.5, +// u11_half_lines_per_field = 1+2*312 Mode = 525 NTSC, Lines per +// field = 262.5, u11_half_lines_per_field = 1+2*262 +#define VEC_DAC_BC_U11_HALF_LINES_PER_FIELD_RESET 0x000 +#define VEC_DAC_BC_U11_HALF_LINES_PER_FIELD_BITS 0x000007ff +#define VEC_DAC_BC_U11_HALF_LINES_PER_FIELD_MSB 10 +#define VEC_DAC_BC_U11_HALF_LINES_PER_FIELD_LSB 0 +#define VEC_DAC_BC_U11_HALF_LINES_PER_FIELD_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_C0 +// JTAG access : synchronous +// Description : Synopsis DesignWare control +#define VEC_DAC_C0_OFFSET 0x000000c0 +#define VEC_DAC_C0_BITS 0x000fffff +#define VEC_DAC_C0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C0_DWC_CABLE_ENCTR3 +// Description : Synopsis test input +#define VEC_DAC_C0_DWC_CABLE_ENCTR3_RESET 0x0 +#define VEC_DAC_C0_DWC_CABLE_ENCTR3_BITS 0x00080000 +#define VEC_DAC_C0_DWC_CABLE_ENCTR3_MSB 19 +#define VEC_DAC_C0_DWC_CABLE_ENCTR3_LSB 19 +#define VEC_DAC_C0_DWC_CABLE_ENCTR3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C0_DWC_CABLE_CABLEOUT +// Description : cable detect state +#define VEC_DAC_C0_DWC_CABLE_CABLEOUT_RESET 0x0 +#define VEC_DAC_C0_DWC_CABLE_CABLEOUT_BITS 0x00070000 +#define VEC_DAC_C0_DWC_CABLE_CABLEOUT_MSB 18 +#define VEC_DAC_C0_DWC_CABLE_CABLEOUT_LSB 16 +#define VEC_DAC_C0_DWC_CABLE_CABLEOUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C0_DWC_MUX_2 +// Description : Select DAC channel 2 output +#define VEC_DAC_C0_DWC_MUX_2_RESET 0x0 +#define VEC_DAC_C0_DWC_MUX_2_BITS 0x0000c000 +#define VEC_DAC_C0_DWC_MUX_2_MSB 15 +#define VEC_DAC_C0_DWC_MUX_2_LSB 14 +#define VEC_DAC_C0_DWC_MUX_2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C0_DWC_MUX_1 +// Description : Select DAC channel 1 output +#define VEC_DAC_C0_DWC_MUX_1_RESET 0x0 +#define VEC_DAC_C0_DWC_MUX_1_BITS 0x00003000 +#define VEC_DAC_C0_DWC_MUX_1_MSB 13 +#define VEC_DAC_C0_DWC_MUX_1_LSB 12 +#define VEC_DAC_C0_DWC_MUX_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C0_DWC_MUX_0 +// Description : Select DAC channel 0 output +#define VEC_DAC_C0_DWC_MUX_0_RESET 0x0 +#define VEC_DAC_C0_DWC_MUX_0_BITS 0x00000c00 +#define VEC_DAC_C0_DWC_MUX_0_MSB 11 +#define VEC_DAC_C0_DWC_MUX_0_LSB 10 +#define VEC_DAC_C0_DWC_MUX_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C0_DWC_TEST +// Description : Fixed DAC command word +#define VEC_DAC_C0_DWC_TEST_RESET 0x000 +#define VEC_DAC_C0_DWC_TEST_BITS 0x000003ff +#define VEC_DAC_C0_DWC_TEST_MSB 9 +#define VEC_DAC_C0_DWC_TEST_LSB 0 +#define VEC_DAC_C0_DWC_TEST_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_C4 +// JTAG access : synchronous +// Description : Synopsis DAC control +#define VEC_DAC_C4_OFFSET 0x000000c4 +#define VEC_DAC_C4_BITS 0x1fffffff +#define VEC_DAC_C4_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C4_ENCTR +// Description : Always write3'b000 +#define VEC_DAC_C4_ENCTR_RESET 0x0 +#define VEC_DAC_C4_ENCTR_BITS 0x1c000000 +#define VEC_DAC_C4_ENCTR_MSB 28 +#define VEC_DAC_C4_ENCTR_LSB 26 +#define VEC_DAC_C4_ENCTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C4_ENSC +// Description : Enable cable detect - write 3'b000 +#define VEC_DAC_C4_ENSC_RESET 0x0 +#define VEC_DAC_C4_ENSC_BITS 0x03800000 +#define VEC_DAC_C4_ENSC_MSB 25 +#define VEC_DAC_C4_ENSC_LSB 23 +#define VEC_DAC_C4_ENSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C4_ENDAC +// Description : Enable DAC channel +#define VEC_DAC_C4_ENDAC_RESET 0x0 +#define VEC_DAC_C4_ENDAC_BITS 0x00700000 +#define VEC_DAC_C4_ENDAC_MSB 22 +#define VEC_DAC_C4_ENDAC_LSB 20 +#define VEC_DAC_C4_ENDAC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C4_ENVBG +// Description : Enable internal bandgap reference - write '1' +#define VEC_DAC_C4_ENVBG_RESET 0x0 +#define VEC_DAC_C4_ENVBG_BITS 0x00080000 +#define VEC_DAC_C4_ENVBG_MSB 19 +#define VEC_DAC_C4_ENVBG_LSB 19 +#define VEC_DAC_C4_ENVBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C4_ENEXTREF +// Description : Enable external reference - write '0' +#define VEC_DAC_C4_ENEXTREF_RESET 0x0 +#define VEC_DAC_C4_ENEXTREF_BITS 0x00040000 +#define VEC_DAC_C4_ENEXTREF_MSB 18 +#define VEC_DAC_C4_ENEXTREF_LSB 18 +#define VEC_DAC_C4_ENEXTREF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C4_DAC2GC +// Description : DAC channel 2 gain control - write 6'd63 +#define VEC_DAC_C4_DAC2GC_RESET 0x00 +#define VEC_DAC_C4_DAC2GC_BITS 0x0003f000 +#define VEC_DAC_C4_DAC2GC_MSB 17 +#define VEC_DAC_C4_DAC2GC_LSB 12 +#define VEC_DAC_C4_DAC2GC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C4_DAC1GC +// Description : DAC channel 1 gain control - write 6'd63 +#define VEC_DAC_C4_DAC1GC_RESET 0x00 +#define VEC_DAC_C4_DAC1GC_BITS 0x00000fc0 +#define VEC_DAC_C4_DAC1GC_MSB 11 +#define VEC_DAC_C4_DAC1GC_LSB 6 +#define VEC_DAC_C4_DAC1GC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C4_DAC0GC +// Description : DAC channel 0 gain control - write 6'd63 +#define VEC_DAC_C4_DAC0GC_RESET 0x00 +#define VEC_DAC_C4_DAC0GC_BITS 0x0000003f +#define VEC_DAC_C4_DAC0GC_MSB 5 +#define VEC_DAC_C4_DAC0GC_LSB 0 +#define VEC_DAC_C4_DAC0GC_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_C8 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_C8_OFFSET 0x000000c8 +#define VEC_DAC_C8_BITS 0xffffffff +#define VEC_DAC_C8_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C8_U16_SCALE_SYNC +// Description : Scaling applied prior to final summation to form the DAC +// command word(s) +#define VEC_DAC_C8_U16_SCALE_SYNC_RESET 0x0000 +#define VEC_DAC_C8_U16_SCALE_SYNC_BITS 0xffff0000 +#define VEC_DAC_C8_U16_SCALE_SYNC_MSB 31 +#define VEC_DAC_C8_U16_SCALE_SYNC_LSB 16 +#define VEC_DAC_C8_U16_SCALE_SYNC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_C8_U16_SCALE_LUMA +// Description : Scaling applied prior to final summation to form the DAC +// command word(s) +#define VEC_DAC_C8_U16_SCALE_LUMA_RESET 0x0000 +#define VEC_DAC_C8_U16_SCALE_LUMA_BITS 0x0000ffff +#define VEC_DAC_C8_U16_SCALE_LUMA_MSB 15 +#define VEC_DAC_C8_U16_SCALE_LUMA_LSB 0 +#define VEC_DAC_C8_U16_SCALE_LUMA_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_CC +// JTAG access : synchronous +// Description : None +#define VEC_DAC_CC_OFFSET 0x000000cc +#define VEC_DAC_CC_BITS 0xffffffff +#define VEC_DAC_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_CC_S16_SCALE_BURST +// Description : Scaling applied prior to final summation to form the DAC +// command word(s) +#define VEC_DAC_CC_S16_SCALE_BURST_RESET 0x0000 +#define VEC_DAC_CC_S16_SCALE_BURST_BITS 0xffff0000 +#define VEC_DAC_CC_S16_SCALE_BURST_MSB 31 +#define VEC_DAC_CC_S16_SCALE_BURST_LSB 16 +#define VEC_DAC_CC_S16_SCALE_BURST_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_CC_S16_SCALE_CHROMA +// Description : Scaling applied prior to final summation to form the DAC +// command word(s) +#define VEC_DAC_CC_S16_SCALE_CHROMA_RESET 0x0000 +#define VEC_DAC_CC_S16_SCALE_CHROMA_BITS 0x0000ffff +#define VEC_DAC_CC_S16_SCALE_CHROMA_MSB 15 +#define VEC_DAC_CC_S16_SCALE_CHROMA_LSB 0 +#define VEC_DAC_CC_S16_SCALE_CHROMA_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_D0 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_D0_OFFSET 0x000000d0 +#define VEC_DAC_D0_BITS 0xffffffff +#define VEC_DAC_D0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_D0_S16_OFFSET_LUMA +// Description : These offsets are applied to the chroma and luma channels +// before the final MUX +#define VEC_DAC_D0_S16_OFFSET_LUMA_RESET 0x0000 +#define VEC_DAC_D0_S16_OFFSET_LUMA_BITS 0xffff0000 +#define VEC_DAC_D0_S16_OFFSET_LUMA_MSB 31 +#define VEC_DAC_D0_S16_OFFSET_LUMA_LSB 16 +#define VEC_DAC_D0_S16_OFFSET_LUMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_D0_S16_OFFSET_CHRO +// Description : These offsets are applied to the chroma and luma channels +// before the final MUX +#define VEC_DAC_D0_S16_OFFSET_CHRO_RESET 0x0000 +#define VEC_DAC_D0_S16_OFFSET_CHRO_BITS 0x0000ffff +#define VEC_DAC_D0_S16_OFFSET_CHRO_MSB 15 +#define VEC_DAC_D0_S16_OFFSET_CHRO_LSB 0 +#define VEC_DAC_D0_S16_OFFSET_CHRO_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_D4 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_D4_OFFSET 0x000000d4 +#define VEC_DAC_D4_BITS 0xffffffff +#define VEC_DAC_D4_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_D4_NCO_FREQ +// Description : This 64-bit frequency command is applied to the phase +// accumulator of the NCO (numerically controlled oscillator) +// which generates the colour sub-carrier. This value is computed +// as ratio of sub-carrier frequency to DAC clock multiplied by +// 2^64. +#define VEC_DAC_D4_NCO_FREQ_RESET 0x00000000 +#define VEC_DAC_D4_NCO_FREQ_BITS 0xffffffff +#define VEC_DAC_D4_NCO_FREQ_MSB 31 +#define VEC_DAC_D4_NCO_FREQ_LSB 0 +#define VEC_DAC_D4_NCO_FREQ_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_D8 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_D8_OFFSET 0x000000d8 +#define VEC_DAC_D8_BITS 0xffffffff +#define VEC_DAC_D8_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_D8_NCO_FREQ +// Description : This 64-bit frequency command is applied to the phase +// accumulator of the NCO (numerically controlled oscillator) +// which generates the colour sub-carrier. This value is computed +// as ratio of sub-carrier frequency to DAC clock multiplied by +// 2^64. +#define VEC_DAC_D8_NCO_FREQ_RESET 0x00000000 +#define VEC_DAC_D8_NCO_FREQ_BITS 0xffffffff +#define VEC_DAC_D8_NCO_FREQ_MSB 31 +#define VEC_DAC_D8_NCO_FREQ_LSB 0 +#define VEC_DAC_D8_NCO_FREQ_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_DC +// JTAG access : synchronous +// Description : None +#define VEC_DAC_DC_OFFSET 0x000000dc +#define VEC_DAC_DC_BITS 0xffffffff +#define VEC_DAC_DC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_DC_FIR_COEFF_CHROMA_0_6 +// Description : FIR filter coefficients +#define VEC_DAC_DC_FIR_COEFF_CHROMA_0_6_RESET 0x0000 +#define VEC_DAC_DC_FIR_COEFF_CHROMA_0_6_BITS 0xffff0000 +#define VEC_DAC_DC_FIR_COEFF_CHROMA_0_6_MSB 31 +#define VEC_DAC_DC_FIR_COEFF_CHROMA_0_6_LSB 16 +#define VEC_DAC_DC_FIR_COEFF_CHROMA_0_6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_DC_FIR_COEFF_LUMA_0_6 +// Description : FIR filter coefficients +#define VEC_DAC_DC_FIR_COEFF_LUMA_0_6_RESET 0x0000 +#define VEC_DAC_DC_FIR_COEFF_LUMA_0_6_BITS 0x0000ffff +#define VEC_DAC_DC_FIR_COEFF_LUMA_0_6_MSB 15 +#define VEC_DAC_DC_FIR_COEFF_LUMA_0_6_LSB 0 +#define VEC_DAC_DC_FIR_COEFF_LUMA_0_6_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_E0 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_E0_OFFSET 0x000000e0 +#define VEC_DAC_E0_BITS 0xffffffff +#define VEC_DAC_E0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_E0_FIR_COEFF_CHROMA_1_5 +// Description : FIR filter coefficients +#define VEC_DAC_E0_FIR_COEFF_CHROMA_1_5_RESET 0x0000 +#define VEC_DAC_E0_FIR_COEFF_CHROMA_1_5_BITS 0xffff0000 +#define VEC_DAC_E0_FIR_COEFF_CHROMA_1_5_MSB 31 +#define VEC_DAC_E0_FIR_COEFF_CHROMA_1_5_LSB 16 +#define VEC_DAC_E0_FIR_COEFF_CHROMA_1_5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_E0_FIR_COEFF_LUMA_1_5 +// Description : FIR filter coefficients +#define VEC_DAC_E0_FIR_COEFF_LUMA_1_5_RESET 0x0000 +#define VEC_DAC_E0_FIR_COEFF_LUMA_1_5_BITS 0x0000ffff +#define VEC_DAC_E0_FIR_COEFF_LUMA_1_5_MSB 15 +#define VEC_DAC_E0_FIR_COEFF_LUMA_1_5_LSB 0 +#define VEC_DAC_E0_FIR_COEFF_LUMA_1_5_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_E4 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_E4_OFFSET 0x000000e4 +#define VEC_DAC_E4_BITS 0xffffffff +#define VEC_DAC_E4_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_E4_FIR_COEFF_CHROMA_2_4 +// Description : FIR filter coefficients +#define VEC_DAC_E4_FIR_COEFF_CHROMA_2_4_RESET 0x0000 +#define VEC_DAC_E4_FIR_COEFF_CHROMA_2_4_BITS 0xffff0000 +#define VEC_DAC_E4_FIR_COEFF_CHROMA_2_4_MSB 31 +#define VEC_DAC_E4_FIR_COEFF_CHROMA_2_4_LSB 16 +#define VEC_DAC_E4_FIR_COEFF_CHROMA_2_4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_E4_FIR_COEFF_LUMA_2_4 +// Description : FIR filter coefficients +#define VEC_DAC_E4_FIR_COEFF_LUMA_2_4_RESET 0x0000 +#define VEC_DAC_E4_FIR_COEFF_LUMA_2_4_BITS 0x0000ffff +#define VEC_DAC_E4_FIR_COEFF_LUMA_2_4_MSB 15 +#define VEC_DAC_E4_FIR_COEFF_LUMA_2_4_LSB 0 +#define VEC_DAC_E4_FIR_COEFF_LUMA_2_4_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_E8 +// JTAG access : synchronous +// Description : None +#define VEC_DAC_E8_OFFSET 0x000000e8 +#define VEC_DAC_E8_BITS 0xffffffff +#define VEC_DAC_E8_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_E8_FIR_COEFF_CHROMA_3 +// Description : FIR filter coefficients +#define VEC_DAC_E8_FIR_COEFF_CHROMA_3_RESET 0x0000 +#define VEC_DAC_E8_FIR_COEFF_CHROMA_3_BITS 0xffff0000 +#define VEC_DAC_E8_FIR_COEFF_CHROMA_3_MSB 31 +#define VEC_DAC_E8_FIR_COEFF_CHROMA_3_LSB 16 +#define VEC_DAC_E8_FIR_COEFF_CHROMA_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_E8_FIR_COEFF_LUMA_3 +// Description : FIR filter coefficients +#define VEC_DAC_E8_FIR_COEFF_LUMA_3_RESET 0x0000 +#define VEC_DAC_E8_FIR_COEFF_LUMA_3_BITS 0x0000ffff +#define VEC_DAC_E8_FIR_COEFF_LUMA_3_MSB 15 +#define VEC_DAC_E8_FIR_COEFF_LUMA_3_LSB 0 +#define VEC_DAC_E8_FIR_COEFF_LUMA_3_ACCESS "RW" +// ============================================================================= +// Register : VEC_DAC_EC +// JTAG access : synchronous +// Description : Misc. control +#define VEC_DAC_EC_OFFSET 0x000000ec +#define VEC_DAC_EC_BITS 0x001fffff +#define VEC_DAC_EC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_EC_SLOW_CLOCK +// Description : Doubles the raised-cosine rate +#define VEC_DAC_EC_SLOW_CLOCK_RESET 0x0 +#define VEC_DAC_EC_SLOW_CLOCK_BITS 0x00100000 +#define VEC_DAC_EC_SLOW_CLOCK_MSB 20 +#define VEC_DAC_EC_SLOW_CLOCK_LSB 20 +#define VEC_DAC_EC_SLOW_CLOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_EC_FIR_RMINUS1 +// Description : Select 1, 3, 5 or 7 FIR taps +#define VEC_DAC_EC_FIR_RMINUS1_RESET 0x0 +#define VEC_DAC_EC_FIR_RMINUS1_BITS 0x000c0000 +#define VEC_DAC_EC_FIR_RMINUS1_MSB 19 +#define VEC_DAC_EC_FIR_RMINUS1_LSB 18 +#define VEC_DAC_EC_FIR_RMINUS1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_EC_VERT_FULL_NOT_HALF +// Description : Disable half-line pulses during VBI +#define VEC_DAC_EC_VERT_FULL_NOT_HALF_RESET 0x0 +#define VEC_DAC_EC_VERT_FULL_NOT_HALF_BITS 0x00020000 +#define VEC_DAC_EC_VERT_FULL_NOT_HALF_MSB 17 +#define VEC_DAC_EC_VERT_FULL_NOT_HALF_LSB 17 +#define VEC_DAC_EC_VERT_FULL_NOT_HALF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_EC_SEQ_EN +// Description : Enable NCO reset +#define VEC_DAC_EC_SEQ_EN_RESET 0x0 +#define VEC_DAC_EC_SEQ_EN_BITS 0x00010000 +#define VEC_DAC_EC_SEQ_EN_MSB 16 +#define VEC_DAC_EC_SEQ_EN_LSB 16 +#define VEC_DAC_EC_SEQ_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_EC_U2_FLD_MASK +// Description : Field sequence +#define VEC_DAC_EC_U2_FLD_MASK_RESET 0x0 +#define VEC_DAC_EC_U2_FLD_MASK_BITS 0x0000c000 +#define VEC_DAC_EC_U2_FLD_MASK_MSB 15 +#define VEC_DAC_EC_U2_FLD_MASK_LSB 14 +#define VEC_DAC_EC_U2_FLD_MASK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_EC_U4_SEQ_MASK +// Description : NCO reset sequence +#define VEC_DAC_EC_U4_SEQ_MASK_RESET 0x0 +#define VEC_DAC_EC_U4_SEQ_MASK_BITS 0x00003c00 +#define VEC_DAC_EC_U4_SEQ_MASK_MSB 13 +#define VEC_DAC_EC_U4_SEQ_MASK_LSB 10 +#define VEC_DAC_EC_U4_SEQ_MASK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_EC_INTERP_RATE_MINUS1 +// Description : Interpolation rate 2<=R<=16 +#define VEC_DAC_EC_INTERP_RATE_MINUS1_RESET 0x0 +#define VEC_DAC_EC_INTERP_RATE_MINUS1_BITS 0x000003c0 +#define VEC_DAC_EC_INTERP_RATE_MINUS1_MSB 9 +#define VEC_DAC_EC_INTERP_RATE_MINUS1_LSB 6 +#define VEC_DAC_EC_INTERP_RATE_MINUS1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_EC_INTERP_SHIFT_MINUS1 +// Description : Power-of-2 scaling after interpolation +#define VEC_DAC_EC_INTERP_SHIFT_MINUS1_RESET 0x0 +#define VEC_DAC_EC_INTERP_SHIFT_MINUS1_BITS 0x0000003c +#define VEC_DAC_EC_INTERP_SHIFT_MINUS1_MSB 5 +#define VEC_DAC_EC_INTERP_SHIFT_MINUS1_LSB 2 +#define VEC_DAC_EC_INTERP_SHIFT_MINUS1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_EC_FIELDS_PER_FRAME_MINUS1 +// Description : Interlaced / progressive +#define VEC_DAC_EC_FIELDS_PER_FRAME_MINUS1_RESET 0x0 +#define VEC_DAC_EC_FIELDS_PER_FRAME_MINUS1_BITS 0x00000002 +#define VEC_DAC_EC_FIELDS_PER_FRAME_MINUS1_MSB 1 +#define VEC_DAC_EC_FIELDS_PER_FRAME_MINUS1_LSB 1 +#define VEC_DAC_EC_FIELDS_PER_FRAME_MINUS1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VEC_DAC_EC_PAL_EN +// Description : Enable phase alternate line (PAL) mode +#define VEC_DAC_EC_PAL_EN_RESET 0x0 +#define VEC_DAC_EC_PAL_EN_BITS 0x00000001 +#define VEC_DAC_EC_PAL_EN_MSB 0 +#define VEC_DAC_EC_PAL_EN_LSB 0 +#define VEC_DAC_EC_PAL_EN_ACCESS "RW" +// ============================================================================= +#endif // VEC_REGS_DEFINED diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/tests/drm_kunit_helpers.c linux/drivers/gpu/drm/tests/drm_kunit_helpers.c --- linux-6.1.66/drivers/gpu/drm/tests/drm_kunit_helpers.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/drivers/gpu/drm/tests/drm_kunit_helpers.c 2023-12-13 11:50:59.463986853 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ +// SPDX-License-Identifier: GPL-2.0 + +#include <drm/drm_drv.h> +#include <drm/drm_kunit_helpers.h> +#include <drm/drm_managed.h> + +#include <kunit/resource.h> + +#include <linux/device.h> +#include <linux/platform_device.h> + +#define KUNIT_DEVICE_NAME "drm-kunit-mock-device" + +static const struct drm_mode_config_funcs drm_mode_config_funcs = { +}; + +static int fake_probe(struct platform_device *pdev) +{ + return 0; +} + +static int fake_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver fake_platform_driver = { + .probe = fake_probe, + .remove = fake_remove, + .driver = { + .name = KUNIT_DEVICE_NAME, + }, +}; + +/** + * drm_kunit_helper_alloc_device - Allocate a mock device for a KUnit test + * @test: The test context object + * + * This allocates a fake struct &device to create a mock for a KUnit + * test. The device will also be bound to a fake driver. It will thus be + * able to leverage the usual infrastructure and most notably the + * device-managed resources just like a "real" device. + * + * Callers need to make sure drm_kunit_helper_free_device() on the + * device when done. + * + * Returns: + * A pointer to the new device, or an ERR_PTR() otherwise. + */ +struct device *drm_kunit_helper_alloc_device(struct kunit *test) +{ + struct platform_device *pdev; + int ret; + + ret = platform_driver_register(&fake_platform_driver); + KUNIT_ASSERT_EQ(test, ret, 0); + + pdev = platform_device_alloc(KUNIT_DEVICE_NAME, PLATFORM_DEVID_NONE); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, pdev); + + ret = platform_device_add(pdev); + KUNIT_ASSERT_EQ(test, ret, 0); + + return &pdev->dev; +} +EXPORT_SYMBOL_GPL(drm_kunit_helper_alloc_device); + +/** + * drm_kunit_helper_free_device - Frees a mock device + * @test: The test context object + * @dev: The device to free + * + * Frees a device allocated with drm_kunit_helper_alloc_device(). + */ +void drm_kunit_helper_free_device(struct kunit *test, struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + + platform_device_unregister(pdev); + platform_driver_unregister(&fake_platform_driver); +} +EXPORT_SYMBOL_GPL(drm_kunit_helper_free_device); + +struct drm_device * +__drm_kunit_helper_alloc_drm_device_with_driver(struct kunit *test, + struct device *dev, + size_t size, size_t offset, + const struct drm_driver *driver) +{ + struct drm_device *drm; + void *container; + int ret; + + container = __devm_drm_dev_alloc(dev, driver, size, offset); + if (IS_ERR(container)) + return ERR_CAST(container); + + drm = container + offset; + drm->mode_config.funcs = &drm_mode_config_funcs; + + ret = drmm_mode_config_init(drm); + if (ret) + return ERR_PTR(ret); + + return drm; +} +EXPORT_SYMBOL_GPL(__drm_kunit_helper_alloc_drm_device_with_driver); + +MODULE_AUTHOR("Maxime Ripard <maxime@cerno.tech>"); +MODULE_LICENSE("GPL"); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/tests/Makefile linux/drivers/gpu/drm/tests/Makefile --- linux-6.1.66/drivers/gpu/drm/tests/Makefile 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/tests/Makefile 2023-12-13 11:50:59.461986849 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:4 @ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_DRM_KUNIT_TEST) += drm_format_helper_test.o drm_damage_helper_test.o \ - drm_cmdline_parser_test.o drm_rect_test.o drm_format_test.o drm_plane_helper_test.o \ - drm_dp_mst_helper_test.o drm_framebuffer_test.o drm_buddy_test.o drm_mm_test.o +obj-$(CONFIG_DRM_KUNIT_TEST_HELPERS) += \ + drm_kunit_helpers.o + +obj-$(CONFIG_DRM_KUNIT_TEST) += \ + drm_buddy_test.o \ + drm_cmdline_parser_test.o \ + drm_damage_helper_test.o \ + drm_dp_mst_helper_test.o \ + drm_format_helper_test.o \ + drm_format_test.o \ + drm_framebuffer_test.o \ + drm_mm_test.o \ + drm_plane_helper_test.o \ + drm_rect_test.o diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/tiny/ili9486.c linux/drivers/gpu/drm/tiny/ili9486.c --- linux-6.1.66/drivers/gpu/drm/tiny/ili9486.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/tiny/ili9486.c 2023-12-13 11:50:59.474986879 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:190 @ MODULE_DEVICE_TABLE(of, ili9486_of_match); static const struct spi_device_id ili9486_id[] = { - { "ili9486", 0 }, + { "rpi-lcd-35", 0 }, + { "piscreen", 0 }, { } }; MODULE_DEVICE_TABLE(spi, ili9486_id); diff -Nur '--exclude=.git*' --no-dereference linux-6.1.66/drivers/gpu/drm/v3d/v3d_debugfs.c linux/drivers/gpu/drm/v3d/v3d_debugfs.c --- linux-6.1.66/drivers/gpu/drm/v3d/v3d_debugfs.c 2023-12-08 08:51:20.000000000 +0100 +++ linux/drivers/gpu/drm/v3d/v3d_debugfs.c 2023-12-13 11:50:59.484986903 +0100 @ linux/arch/arm/boot/dts/bcm2708.dtsi:9 @ #include <linux/debugfs.h> #include <linux/seq_file.h> #include <linux/string_helpers.h> +#include <linux/sched/clock.h> #include <drm/drm_debugfs.h> #include "v3d_drv.h" #include "v3d_regs.h" -#define REGDEF(reg) { reg, #reg } +#define REGDEF(min_ver, max_ver, reg) { min_ver, max_ver, reg, #reg } struct v3d_reg_def { + u32 min_ver; + u32 max_ver; u32 reg; const char *name; }; static const struct v3d_reg_def v3d_hub_reg_defs[] = { - REGDEF(V3D_HUB_AXICFG), - REGDEF(V3D_HUB_UIFCFG), - REGDEF(V3D_HUB_IDENT0), - REGDEF(V3D_HUB_IDENT1), - REGDEF(V3D_HUB_IDENT2), - REGDEF(V3D_HUB_IDENT3), - REGDEF(V3D_HUB_INT_STS), - REGDEF(V3D_HUB_INT_MSK_STS), - - REGDEF(V3D_MMU_CTL), - REGDEF(V3D_MMU_VIO_ADDR), - REGDEF(V3D_MMU_VIO_ID), - REGDEF(V3D_MMU_DEBUG_INFO), + REGDEF(33, 42, V3D_HUB_AXICFG), + REGDEF(33, 71, V3D_HUB_UIFCFG), + REGDEF(33, 71, V3D_HUB_IDENT0), + REGDEF(33, 71, V3D_HUB_IDENT1), + REGDEF(33, 71, V3D_HUB_IDENT2), + REGDEF(33, 71, V3D_HUB_IDENT3), + REGDEF(33, 71, V3D_HUB_INT_STS), + REGDEF(33, 71, V3D_HUB_INT_MSK_STS), + + REGDEF(33, 71, V3D_MMU_CTL), + REGDEF(33, 71, V3D_MMU_VIO_ADDR), + REGDEF(33, 71, V3D_MMU_VIO_ID), + REGDEF(33, 71, V3D_MMU_DEBUG_INFO), + + REGDEF(71, 71, V3D_V7_GMP_STATUS), + REGDEF(71, 71, V3D_V7_GMP_CFG), + REGDEF(71, 71, V3D_V7_GMP_VIO_ADDR), }; static const struct v3d_reg_def v3d_gca_reg_defs[] = { - REGDEF(V3D_GCA_SAFE_SHUTDOWN), - REGDEF(V3D_GCA_SAFE_SHUTDOWN_ACK), + REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN), + REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN_ACK), }; static const struct v3d_reg_def v3d_core_reg_defs[] = { - REGDEF(V3D_CTL_IDENT0), - REGDEF(V3D_CTL_IDENT1), - REGDEF(V3D_CTL_IDENT2), - REGDEF(V3D_CTL_MISCCFG), - REGDEF(V3D_CTL_INT_STS), - REGDEF(V3D_CTL_INT_MSK_STS), - REGDEF(V3D_CLE_CT0CS), - REGDEF(V3D_CLE_CT0CA), - REGDEF(V3D_CLE_CT0EA), - REGDEF(V3D_CLE_CT1CS), - REGDEF(V3D_CLE_CT1CA), - REGDEF(V3D_CLE_CT1EA), - - REGDEF(V3D_PTB_BPCA), - REGDEF(V3D_PTB_BPCS), - - REGDEF(V3D_GMP_STATUS), - REGDEF(V3D_GMP_CFG), - REGDEF(V3D_GMP_VIO_ADDR), - - REGDEF(V3D_ERR_FDBGO), - REGDEF(V3D_ERR_FDBGB), - REGDEF(V3D_ERR_FDBGS), - REGDEF(V3D_ERR_STAT), + REGDEF(33, 71, V3D_CTL_IDENT0), + REGDEF(33, 71, V3D_CTL_IDENT1), + REGDEF(33, 71, V3D_CTL_IDENT2), + REGDEF(33, 71, V3D_CTL_MISCCFG), + REGDEF(33, 71, V3D_CTL_INT_STS), + REGDEF(33, 71, V3D_CTL_INT_MSK_STS), + REGDEF(33, 71, V3D_CLE_CT0CS), + REGDEF(33, 71, V3D_CLE_CT0CA), + REGDEF(33, 71, V3D_CLE_CT0EA), + REGDEF(33, 71, V3D_CLE_CT1CS), + REGDEF(33, 71, V3D_CLE_CT1CA), + REGDEF(33, 71, V3D_CLE_CT1EA), + + REGDEF(33, 71, V3D_PTB_BPCA), + REGDEF(33, 71, V3D_PTB_BPCS), + + REGDEF(33, 41, V3D_GMP_STATUS), + REGDEF(33, 41, V3D_GMP_CFG), + REGDEF(33, 41, V3D_GMP_VIO_ADDR), + + REGDEF(33, 71, V3D_ERR_FDBGO), + REGDEF(33, 71, V3D_ERR_FDBGB), + REGDEF(33, 71, V3D_ERR_FDBGS), + REGDEF(33, 71, V3D_ERR_STAT), }; static const struct v3d_reg_def v3d_csd_reg_defs[] = { - REGDEF(V3D_CSD_STATUS), - REGDEF(V3D_CSD_CURRENT_CFG0), - REGDEF(V3D_CSD_CURRENT_CFG1), - REGDEF(V3D_CSD_CURRENT_CFG2), - REGDEF(V3D_CSD_CURRENT_CFG3), - REGDEF(V3D_CSD_CURRENT_CFG4), - REGDEF(V3D_CSD_CURRENT_CFG5), - REGDEF(V3D_CSD_CURRENT_CFG6), + REGDEF(41, 71, V3D_CSD_STATUS), + REGDEF(41, 41, V3D_CSD_CURRENT_CFG0), + REGDEF(41, 41, V3D_CSD_CURRENT_CFG1), + REGDEF(41, 41, V3D_CSD_CURRENT_CFG2), + REGDEF(41, 41, V3D_CSD_CURRENT_CFG3), + REGDEF(41, 41, V3D_CSD_CURRENT_CFG4), + REGDEF(41, 41, V3D_CSD_CURRENT_CFG5), + REGDEF(41, 41, V3D_CSD_CURRENT_CFG6), + REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG0), + REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG1), + REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG2), + REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG3), + REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG4), + REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG5), + REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG6), + REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG7), }; static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused) @ linux/arch/arm/boot/dts/bcm2708.dtsi:103 @ int i, core; for (i = 0; i < ARRAY_SIZE(v3d_hub_reg_defs); i++) { - seq_printf(m, "%s (0x%04x): 0x%08x\n", - v3d_hub_reg_defs[i].name, v3d_hub_reg_defs[i].reg, - V3D_READ(v3d_hub_reg_defs[i].reg)); + const struct v3d_reg_def *def = &v3d_hub_reg_defs[i]; + + if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) { + seq_printf(m, "%s (0x%04x): 0x%08x\n", + def->name, def->reg, V3D_READ(def->reg)); + } } - if (v3d->ver < 41) { - for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) { + for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) { + const struct v3d_reg_def *def = &v3d_gca_reg_defs[i]; + + if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) { seq_printf(m, "%s (0x%04x): 0x%08x\n", - v3d_gca_reg_defs[i].name, - v3d_gca_reg_defs[i].reg, - V3D_GCA_READ(v3d_gca_reg_defs[i].reg)); + def->name, def->reg, V3D_GCA_READ(def->reg)); } } for (core = 0; core < v3d->cores; core++) { for (i = 0; i < ARRAY_SIZE(v3d_core_reg_defs); i++) { - seq_printf(m, "core %d %s (0x%04x): 0x%08x\n", - core, - v3d_core_reg_defs[i].name, - v3d_core_reg_defs[i].reg, - V3D_CORE_READ(core, - v3d_core_reg_defs[i].reg)); + const struct v3d_reg_def *def = &v3d_core_reg_defs[i]; + + if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) { + seq_printf(m, "core %d %s (0x%04x): 0x%08x\n", + core, def->name, def->reg, + V3D_CORE_READ(core, def->reg)); + } } - if (v3d_has_csd(v3d)) { - for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) { + for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) { + const struct v3d_reg_def *def = &v3d_csd_reg_defs[i]; + + if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) { seq_printf(m, "core %d %s (0x%04x): 0x%08x\n", - core, - v3d_csd_reg_defs[i].name, - v3d_csd_reg_defs[i].reg, - V3D_CORE_READ(core, - v3d_csd_reg_defs[i].reg)); + core, def->name, def->reg, + V3D_CORE_READ(core, def->reg)); } } } @ linux/arch/arm/boot/dts/bcm2708.dtsi:168 @ str_yes_no(ident2 & V3D_HUB_IDENT2_WITH_MMU)); seq_printf(m, "TFU: %s\n", str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TFU)); - seq_printf(m, "TSY: %s\n", - str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY)); + if (v3d->ver <= 42) { + seq_printf(m, "TSY: %s\n", + str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY)); + } seq_printf(m, "MSO: %s\n", str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_MSO)); seq_printf(m, "L3C: %s (%dkb)\n", @ linux/arch/arm/boot/dts/bcm2708.dtsi:200 @ seq_printf(m, " QPUs: %d\n", nslc * qups); seq_printf(m, " Semaphores: %d\n", V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM)); - seq_printf(m, " BCG int: %d\n", - (ident2 & V3D_IDENT2_BCG_INT) != 0); - seq_printf(m, " Override TMU: %d\n", - (misccfg & V3D_MISCCFG_OVRTMUOUT) != 0); + if (v3d->ver <= 42) { + seq_printf(m, " BCG int: %d\n", + (ident2 & V3D_IDENT2_BCG_INT) != 0); + } + if (v3d->ver < 40) { + seq_printf(m, " Override TMU: %d\n", + (misccfg & V3D_MISCCFG_OVRTMUOUT) != 0); + } } return 0; @ linux/arch/arm/boot/dts/bcm2708.dtsi:229 @ return 0; } +static int v3d_debugfs_gpu_usage(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct v3d_dev *v3d = to_v3d_dev(dev); + struct v3d_queue_stats *queue_stats; + enum v3d_queue queue; + u64 timestamp = local_clock(); + u64 active_runtime; + + seq_printf(m, "timestamp;%llu;\n", local_clock()); + seq_printf(m, "\"QUEUE\";\"JOBS\";\"RUNTIME\";\"ACTIVE\";\n"); + for (queue = 0; queue < V3D_MAX_QUEUES; queue++) { + if (!v3d->queue[queue].sched.ready) + continue; + + queue_stats = &v3d->gpu_queue_stats[queue]; + mutex_lock(&queue_stats->lock); + v3d_sched_stats_update(queue_stats); + if (queue_stats->last_pid) + active_runtime = timestamp - queue_stats->last_exec_start; + else + active_runtime = 0; + + seq_printf(m, "%s;%d;%llu;%c;\n", + v3d_queue_to_string(queue), + queue_stats->jobs_sent, + queue_stats->runtime + active_runtime, + queue_stats->last_pid?'1':'0'); + mutex_unlock(&queue_stats->lock); + } + + return 0; +} + +static int v3d_debugfs_gpu_pid_usage(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct v3d_dev *v3d = to_v3d_dev(dev); + struct v3d_queue_stats *queue_stats; + struct v3d_queue_pid_stats *cur; + enum v3d_queue queue; + u64 active_runtime; + u64 timestamp = local_clock(); + + seq_printf(m, "timestamp;%llu;\n", timestamp); + seq_printf(m, "\"QUEUE\";\"PID\",\"JOB