From 365d851d4c1c5994300f6660d02c0ab094cc5ff3 Mon Sep 17 00:00:00 2001 From: Afzal Mohammed Date: Tue, 22 Jan 2013 20:33:56 +0530 Subject: [PATCH 07/51] clk: divider: handle minimum divider Some of clocks can have a limit on minimum divider value that can be programmed. Modify basic clock divider to take care of this aspect. Signed-off-by: Afzal Mohammed --- drivers/clk/clk-divider.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index da121ac..9f5f8e7 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -32,6 +32,11 @@ #define div_mask(d) ((1 << ((d)->width)) - 1) +static unsigned int _get_mindiv(struct clk_divider *divider) +{ + return divider->min_div; +} + static unsigned int _get_table_maxdiv(const struct clk_div_table *table) { unsigned int maxdiv = 0; @@ -149,18 +154,19 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, { struct clk_divider *divider = to_clk_divider(hw); int i, bestdiv = 0; - unsigned long parent_rate, best = 0, now, maxdiv; + unsigned long parent_rate, best = 0, now, maxdiv, mindiv; unsigned long parent_rate_saved = *best_parent_rate; if (!rate) rate = 1; maxdiv = _get_maxdiv(divider); + mindiv = _get_mindiv(divider); if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { parent_rate = *best_parent_rate; bestdiv = DIV_ROUND_UP(parent_rate, rate); - bestdiv = bestdiv == 0 ? 1 : bestdiv; + bestdiv = bestdiv == 0 ? mindiv : bestdiv; bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; return bestdiv; } @@ -171,7 +177,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, */ maxdiv = min(ULONG_MAX / rate, maxdiv); - for (i = 1; i <= maxdiv; i++) { + for (i = mindiv; i <= maxdiv; i++) { if (!_is_valid_div(divider, i)) continue; if (rate * i == parent_rate_saved) { -- 1.7.10.4