From 56e918e9f52fc3071cb035772a30da35aaff12e1 Mon Sep 17 00:00:00 2001
From: Torben Hohn <torbenh@linutronix.de>
Date: Tue, 28 May 2013 17:39:46 +0200
Subject: [PATCH 29/51] fixup hwmod stuff

---
 arch/arm/mach-omap2/omap_hwmod.c |   22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

Index: linux-3.12.36-rt50-r4s2/arch/arm/mach-omap2/omap_hwmod.c
===================================================================
--- linux-3.12.36-rt50-r4s2.orig/arch/arm/mach-omap2/omap_hwmod.c
+++ linux-3.12.36-rt50-r4s2/arch/arm/mach-omap2/omap_hwmod.c
@@ -125,7 +125,7 @@
  * XXX error return values should be checked to ensure that they are
  * appropriate
  */
-#define DEBUG
+#undef DEBUG
 
 #include <linux/kernel.h>
 #include <linux/errno.h>
@@ -2171,7 +2171,8 @@ static int _enable(struct omap_hwmod *oh
 	 * can do.
 	 */
 	if (_are_all_hardreset_lines_asserted(oh))
-		return 0;
+//		return 0;
+		;
 
 	/* Mux pins for device runtime if populated */
 	if (oh->mux && (!oh->mux->enabled ||
@@ -2210,6 +2211,23 @@ static int _enable(struct omap_hwmod *oh
 	if (soc_ops.update_context_lost)
 		soc_ops.update_context_lost(oh);
 
+        /*
+         * If an IP contains only one HW reset line, then de-assert it in order
+         * to allow the module state transition. Otherwise the PRCM will return
+         * Intransition status, and the init will failed.
+         *
+         * TODO: Based on observation, on module enable sate, we can safely
+         *      assert the reset signal here (irrespective of idlemode state).
+         */
+        if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
+             oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) {
+                _deassert_hardreset(oh, oh->rst_lines[0].name);
+		_enable_clocks(oh);
+		if (soc_ops.enable_module)
+			soc_ops.enable_module(oh);
+	}
+
+
 	r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) :
 		-EINVAL;
 	if (!r) {