diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi v_kernel/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi 2026-04-21 11:35:27.613912830 +0200 @@ -212,7 +212,7 @@ status = "okay"; clock-frequency = <400000>; - tps: tps@24 { + tps: pmic@24 { reg = <0x24>; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am335x-bonegreen-eco.dts v_kernel/arch/arm/boot/dts/ti/omap/am335x-bonegreen-eco.dts --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am335x-bonegreen-eco.dts 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am335x-bonegreen-eco.dts 2026-04-21 11:35:27.615912836 +0200 @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Bootlin + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-bonegreen-common.dtsi" +#include + +/ { + model = "Seeed Studio BeagleBone Green Eco"; + compatible = "seeed,am335x-bone-green-eco", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&buck1>; + }; + }; + + sys_5v: regulator-sys-5v { + compatible = "regulator-fixed"; + regulator-name = "sys_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-always-on; + }; +}; + +&usb0 { + interrupts-extended = <&intc 18>; + interrupt-names = "mc"; +}; + +&baseboard_eeprom { + vcc-supply = <&v3v3>; +}; + +&i2c0 { + /delete-node/ pmic@24; + + tps65214: pmic@30 { + compatible = "ti,tps65214"; + reg = <0x30>; + buck1-supply = <&sys_5v>; + buck2-supply = <&sys_5v>; + buck3-supply = <&sys_5v>; + ldo1-supply = <&sys_5v>; + ldo2-supply = <&sys_5v>; + + interrupt-parent = <&intc>; + interrupts = <7>; + pinctrl-0 = <&pmic_irq_pins_default>; + + regulators { + buck1: buck1 { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1351500>; + regulator-boot-on; + regulator-always-on; + }; + + buck2: buck2 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + buck3: buck3 { + regulator-name = "vdds_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "vdd_1v8_1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "vdd_1v8_2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-id"; + phy-handle = <&dp83867_0>; + ti,dual-emac-pvid = <1>; +}; + +&mac_sw { + pinctrl-0 = <&cpsw_b_default>; + pinctrl-1 = <&cpsw_b_sleep>; +}; + +&davinci_mdio_sw { + /delete-node/ ethernet-phy@0; + + dp83867_0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + ti,dp83867-rxctrl-strap-quirk; + }; +}; + +&am33xx_pinmux { + cpsw_b_default: cpsw-b-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) + >; + }; + + cpsw_b_sleep: cpsw-b-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(AM335X_PIN_NNMI, PIN_INPUT_PULLUP | MUX_MODE0) + >; + }; +}; + +&uart0 { + wakeup-source; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am335x-bone-hdmi-00a0.dtso v_kernel/arch/arm/boot/dts/ti/omap/am335x-bone-hdmi-00a0.dtso --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am335x-bone-hdmi-00a0.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am335x-bone-hdmi-00a0.dtso 2026-04-21 11:35:27.613912830 +0200 @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * 2017 Copyright (c) Seeed Technology Inc. All right reserved. + * Author:Baozhu Zuo + * (C) Copyright 2025 Köry Maincent + * + * This device tree overlay is compatible with the BeagleBone Black, Green + * and their subversions. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&it66121_out>; + }; + }; + }; + + clk_mcasp0_fixed: clk_mcasp0_fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + clk_mcasp0: clk_mcasp0 { + #clock-cells = <0>; + compatible = "gpio-gate-clock"; + clocks = <&clk_mcasp0_fixed>; + enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "TI BeagleBone Green HDMI cape"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + + sound_master: simple-audio-card,cpu { + sound-dai = <&mcasp0>; + clocks = <&clk_mcasp0>; + }; + + simple-audio-card,codec { + sound-dai = <&it66121>; + }; + }; +}; + +&am33xx_pinmux { + bb_lcd_pins: pinmux_bb_lcd_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT, MUX_MODE7) + >; + }; + mcasp0_pins: mcasp0_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; +}; + +&i2c2 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + it66121: it66121 { + compatible = "ite,it66121"; + reg = <0x4d>; + pinctrl-names = "default"; + pinctrl-0 = <&bb_lcd_pins>; + + #sound-dai-cells = <0>; + + interrupt-parent = <&gpio2>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + it66121_in: endpoint { + bus-width = <24>; + remote-endpoint = <&lcdc_0>; + }; + }; + + port@1 { + reg = <1>; + it66121_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&lcdc { + status = "okay"; + blue-and-red-wiring = "straight"; + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&it66121_in>; + }; + }; +}; + + +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + status = "okay"; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 0 >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am335x-evm.dts v_kernel/arch/arm/boot/dts/ti/omap/am335x-evm.dts --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am335x-evm.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am335x-evm.dts 2026-04-21 11:35:27.616912838 +0200 @@ -388,6 +388,7 @@ &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; + wakeup-source; status = "okay"; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts v_kernel/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts 2026-04-21 11:35:27.617912841 +0200 @@ -29,6 +29,11 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; + aliases { + serial0 = &uart0; + serial1 = &pruss_uart; + }; + chosen { stdout-path = &uart0; }; @@ -441,6 +446,22 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */ >; }; + + pruss_uart_pins: pruss-uart-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* spi0_sclk.pr1_uart0_cts_n */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* spi0_d0.pr1_uart0_rts_n */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE4) /* spi0_d1.pr1_uart0_rxd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT_PULLUP, MUX_MODE4) /* spi0_cs9.pr1_uart0_txd */ + >; + }; +}; + +&pruss_uart { + interrupts = <6 2 2>; + pinctrl-names = "default"; + pinctrl-0 = <&pruss_uart_pins>; + status = "okay"; }; &uart0 { diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am335x-icev2-prueth.dts v_kernel/arch/arm/boot/dts/ti/omap/am335x-icev2-prueth.dts --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am335x-icev2-prueth.dts 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am335x-icev2-prueth.dts 2026-04-21 11:35:27.618912844 +0200 @@ -0,0 +1,533 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/* + * AM335x ICE V2 board + * http://www.ti.com/tool/tmdsice3359 + */ + +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "TI AM3359 ICE-V2 - dual PRUETH"; + compatible = "ti,am3359-icev2", "ti,am33xx"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + chosen { + stdout-path = &uart3; + }; + + vbat: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + vtt_fixed: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + + /* Tricolor status LEDs */ + leds1 { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_leds>; + + led0 { + label = "status0:red:cpu0"; + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + led1 { + label = "status0:green:usr"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led2 { + label = "status0:yellow:usr"; + gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led3 { + label = "status1:red:mmc0"; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + + led4 { + label = "status1:green:usr"; + gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led5 { + label = "status1:yellow:usr"; + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + gpio-decoder { + compatible = "gpio-decoder"; + gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, + <&pca9536 2 GPIO_ACTIVE_HIGH>, + <&pca9536 1 GPIO_ACTIVE_HIGH>, + <&pca9536 0 GPIO_ACTIVE_HIGH>; + linux,axis = <0>; /* ABS_X */ + decoder-max-value = <9>; + }; + + /* Dual-MAC Ethernet application node on PRU-ICSS */ + pruss_eth: pruss-eth { + compatible = "ti,am3359-prueth"; + ti,prus = <&pru0>, <&pru1>; + sram = <&ocmcram>; + ti,mii-rt = <&pruss_mii_rt>; + ti,iep = <&pruss_iep>; + ti,ecap = <&pruss_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss_intc>; + + pinctrl-0 = <&pruss_eth_default>; + pinctrl-names = "default"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 7>, <24 9 7>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; +}; + +&am33xx_pinmux { + user_leds: user-leds-pins { + pinctrl-single,pins = < + /* (J18) gmii1_txd3.gpio0[16] */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, + MUX_MODE7) + /* (K15) gmii1_txd2.gpio0[17] */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, + MUX_MODE7) + /* (A15) xdma_event_intr0.gpio0[19] */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, + MUX_MODE7) + /* (D14) xdma_event_intr1.gpio0[20] */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, + MUX_MODE7) + /* (U9) gpmc_csn1.gpio1[30] */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, + MUX_MODE7) + /* (K18) gmii1_txclk.gpio3[9] */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, + MUX_MODE7) + >; + }; + + mmc0_pins_default: mmc0-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, + MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, + MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, + MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, + MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, + MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, + MUX_MODE0) + >; + }; + + i2c0_pins_default: i2c0-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, + MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, + MUX_MODE0) + >; + }; + + spi0_pins_default: spi0-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, + MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, + MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, + MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, + MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, + MUX_MODE0) + /* (B12) mcasp0_aclkr.gpio3[18] */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, + PIN_INPUT_PULLUP, + MUX_MODE7) + >; + }; + + uart3_pins_default: uart3-default-pins { + pinctrl-single,pins = < + /* (L17) gmii1_rxd3.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, + MUX_MODE1) + /* (L16) gmii1_rxd2.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, + MUX_MODE1) + >; + }; + + pruss_mdio_default: pruss_mdio_default { + pinctrl-single,pins = < + /* gpmc_clk.pr1_mdio_mdclk */ + AM33XX_PADCONF(0x88c, PIN_OUTPUT, MUX_MODE5) + /* gpmc_csn3.pr1_mdio_data */ + AM33XX_PADCONF(0x888, PIN_INPUT, MUX_MODE5) + /* gpmc_ben0_cle.gpio2_5 */ + AM33XX_PADCONF(0x89c, PIN_INPUT_PULLUP, MUX_MODE7) + /* disable CPSW MDIO */ + /* mdio_data.gpio0_0 */ + AM33XX_PADCONF(0x948, PIN_INPUT_PULLUP, MUX_MODE7) + /* mdio_clk.gpio0_1 */ + AM33XX_PADCONF(0x94c, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + + pruss_eth_default: pruss_eth_default { + pinctrl-single,pins = < + /* dss_data0.pr1_mii_mt0_clk */ + AM33XX_PADCONF(0x8a0, PIN_INPUT, MUX_MODE2) + /* dss_data5.pr1_mii0_txd0 */ + AM33XX_PADCONF(0x8b4, PIN_OUTPUT, MUX_MODE2) + /* dss_data4.pr1_mii0_txd1 */ + AM33XX_PADCONF(0x8b0, PIN_OUTPUT, MUX_MODE2) + /* dss_data3.pr1_mii0_txd2 */ + AM33XX_PADCONF(0x8ac, PIN_OUTPUT, MUX_MODE2) + /* dss_data2.pr1_mii0_txd3 */ + AM33XX_PADCONF(0x8a8, PIN_OUTPUT, MUX_MODE2) + /* dss_data11.pr1_mii0_rxd0 */ + AM33XX_PADCONF(0x8cc, PIN_INPUT, MUX_MODE5) + /* dss_data10.pr1_mii0_rxd1 */ + AM33XX_PADCONF(0x8c8, PIN_INPUT, MUX_MODE5) + /* dss_data9.pr1_mii0_rxd2 */ + AM33XX_PADCONF(0x8c4, PIN_INPUT, MUX_MODE5) + /* dss_data8.pr1_mii0_rxd3 */ + AM33XX_PADCONF(0x8c0, PIN_INPUT, MUX_MODE5) + /* dss_data1.pr1_mii0_txen */ + AM33XX_PADCONF(0x8a4, PIN_OUTPUT, MUX_MODE2) + /* dss_data14.pr1_mii_mr0_clk */ + AM33XX_PADCONF(0x8d8, PIN_INPUT, MUX_MODE5) + /* dss_data15.pr1_mii0_rxdv */ + AM33XX_PADCONF(0x8dc, PIN_INPUT, MUX_MODE5) + /* dss_data13.pr1_mii0_rxer */ + AM33XX_PADCONF(0x8d4, PIN_INPUT, MUX_MODE5) + /* dss_data12.pr1_mii0_rxlink */ + AM33XX_PADCONF(0x8d0, PIN_INPUT, MUX_MODE5) + /* dss_pclk.pr1_mii0_crs */ + AM33XX_PADCONF(0x8e8, PIN_INPUT, MUX_MODE2) + + /* gpmc_a0.pr1_mii_mt1_clk */ + AM33XX_PADCONF(0x840, PIN_INPUT, MUX_MODE5) + /* gpmc_a4.pr1_mii1_txd0 */ + AM33XX_PADCONF(0x850, PIN_OUTPUT, MUX_MODE5) + /* gpmc_a3.pr1_mii1_txd1 */ + AM33XX_PADCONF(0x84c, PIN_OUTPUT, MUX_MODE5) + /* gpmc_a2.pr1_mii1_txd2 */ + AM33XX_PADCONF(0x848, PIN_OUTPUT, MUX_MODE5) + /* gpmc_a1.pr1_mii1_txd3 */ + AM33XX_PADCONF(0x844, PIN_OUTPUT, MUX_MODE5) + /* gpmc_a8.pr1_mii1_rxd0 */ + AM33XX_PADCONF(0x860, PIN_INPUT, MUX_MODE5) + /* gpmc_a7.pr1_mii1_rxd1 */ + AM33XX_PADCONF(0x85c, PIN_INPUT, MUX_MODE5) + /* gpmc_a6.pr1_mii1_rxd2 */ + AM33XX_PADCONF(0x858, PIN_INPUT, MUX_MODE5) + /* gpmc_a5.pr1_mii1_rxd3 */ + AM33XX_PADCONF(0x854, PIN_INPUT, MUX_MODE5) + /* gpmc_wpn.pr1_mii1_txen */ + AM33XX_PADCONF(0x874, PIN_OUTPUT, MUX_MODE5) + /* gpmc_a9.pr1_mii_mr1_clk */ + AM33XX_PADCONF(0x864, PIN_INPUT, MUX_MODE5) + /* gpmc_a10.pr1_mii1_rxdv */ + AM33XX_PADCONF(0x868, PIN_INPUT, MUX_MODE5) + /* gpmc_a11.pr1_mii1_rxer */ + AM33XX_PADCONF(0x86c, PIN_INPUT, MUX_MODE5) + /* gpmc_ben1.pr1_mii1_rxlink */ + AM33XX_PADCONF(0x878, PIN_INPUT, MUX_MODE5) + /* lcd_ac_bias_en.pr1_mii1_crs */ + AM33XX_PADCONF(0x8ec, PIN_INPUT, MUX_MODE2) + /* gpmc_wait0.pr1_mii1_col */ + AM33XX_PADCONF(0x870, PIN_INPUT, MUX_MODE5) + >; + }; + +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_default>; + + status = "okay"; + clock-frequency = <400000>; + + tps: power-controller@2d { + reg = <0x2d>; + }; + + tpic2810: gpio@60 { + compatible = "ti,tpic2810"; + reg = <0x60>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9536: gpio@41 { + compatible = "ti,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + }; + +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_default>; + + sn65hvs882@1 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + + reg = <1>; + spi-max-frequency = <1000000>; + spi-cpol; + }; + + spi_nor: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond, w25q64", "jedec,spi-nor"; + spi-max-frequency = <80000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "u-boot"; + reg = <0x80000 0x100000>; + read-only; + }; + + partition@2 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; + read-only; + }; + + partition@3 { + label = "misc"; + reg = <0x1A0000 0x660000>; + }; + }; + +}; + +&tscadc { + status = "okay"; + adc { + ti,adc-channels = <1 2 3 4 5 6 7>; + }; +}; + +#include "../../tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1326000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; +}; + +&gpio0_target { + /* Do not idle the GPIO used for holding the VTT regulator */ + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_default>; + status = "okay"; +}; + +&gpio3 { + pr1-mii-ctl-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PR1_MII_CTRL"; + }; + + mux-mii-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ + output-low; + line-name = "MUX_MII_CTL1"; + }; +}; + +&pruss_tm { + status = "okay"; +}; + +&pruss_mdio { + pinctrl-0 = <&pruss_mdio_default>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; /* PHY datasheet states 1uS min */ + status = "okay"; + + pruss_eth0_phy: ethernet-phy@1 { + reg = <1>; + }; + + pruss_eth1_phy: ethernet-phy@3 { + reg = <3>; + }; +}; + +&rtc { + system-power-controller; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi v_kernel/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi 2026-04-21 11:35:27.628912870 +0200 @@ -891,11 +891,30 @@ }; }; + pruss_uart: serial@28000 { + compatible = "ti,pruss-uart"; + reg = <0x28000 0x38>; + clocks = <&dpll_per_m2_ck>; + interrupt-parent = <&pruss_intc>; + status = "disabled"; + }; + pruss_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x58>; }; + pruss_iep: iep@2e000 { + compatible = "ti,am3356-icss-iep"; + reg = <0x2e000 0x31c>; + clocks = <&pruss_iepclk_mux>; + }; + + pruss_ecap: ecap@30000 { + compatible = "ti,pruss-ecap"; + reg = <0x30000 0x60>; + }; + pruss_intc: interrupt-controller@20000 { compatible = "ti,pruss-intc"; reg = <0x20000 0x2000>; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am4372.dtsi v_kernel/arch/arm/boot/dts/ti/omap/am4372.dtsi --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am4372.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am4372.dtsi 2026-04-21 11:35:27.631912878 +0200 @@ -477,6 +477,17 @@ reg = <0x32000 0x58>; }; + pruss1_iep: iep@2e000 { + compatible = "ti,am4376-icss-iep"; + reg = <0x2e000 0x31c>; + clocks = <&pruss1_iepclk_mux>; + }; + + pruss1_ecap: ecap@30000 { + compatible = "ti,pruss-ecap"; + reg = <0x30000 0x60>; + }; + pruss1_intc: interrupt-controller@20000 { compatible = "ti,pruss-intc"; reg = <0x20000 0x2000>; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am437x-gp-evm-hdmi.dts v_kernel/arch/arm/boot/dts/ti/omap/am437x-gp-evm-hdmi.dts --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am437x-gp-evm-hdmi.dts 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am437x-gp-evm-hdmi.dts 2026-04-21 11:35:27.632912880 +0200 @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/* AM437x GP EVM with HDMI output */ + +#include "am437x-gp-evm.dts" + +/delete-node/ &lcd0; + +/ { + aliases { + display0 = &hdmi; + }; + + hdmi: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "b"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; + + sound@1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&hdmi_dailink_master>; + simple-audio-card,frame-master = <&hdmi_dailink_master>; + hdmi_dailink_master: simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-frequency = <24000000>; + system-clock-direction-out; + }; + + simple-audio-card,codec { + sound-dai = <&sii9022>; + }; + }; + + sii9022_mclk: sii9022-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; +}; + +&lcd_bl { + status = "disabled"; +}; + +&sound0 { + status = "disabled"; +}; + +&tlv320aic3106 { + status = "disabled"; +}; + +&i2c1 { + sii9022: sii9022@3b { + #sound-dai-cells = <0>; + compatible = "sil,sii9022"; + reg = <0x3b>; + + interrupt-parent = <&gpio3>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + + sil,i2s-data-lanes = < 0 >; + clocks = <&sii9022_mclk>; + clock-names = "mclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&dpi_out { + remote-endpoint = <&sii9022_in>; + data-lines = <24>; +}; + +/* Override SelLCDorHDMI from am437x-gp-evm.dts to select HDMI */ +&gpio5 { + sel-lcd-hdmi-hog { + /* + * SelLCDorHDMI selects between display and audio paths: + * Low: HDMI display with audio via HDMI + * High: LCD display with analog audio via aic3111 codec + */ + gpio-hog; + gpios = <8 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "SelLCDorHDMI"; + }; + +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts v_kernel/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts 2026-04-21 11:35:27.633912883 +0200 @@ -168,6 +168,48 @@ default-state = "off"; }; }; + + /* Dual-MAC Ethernet application node on PRU-ICSS1 */ + pruss1_eth: pruss1-eth { + compatible = "ti,am4376-prueth"; + ti,prus = <&pru1_0>, <&pru1_1>; + sram = <&ocmcram>; + ti,mii-rt = <&pruss1_mii_rt>; + ti,iep = <&pruss1_iep>; + ti,ecap = <&pruss1_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss1_intc>; + + pinctrl-0 = <&pruss1_eth_default>; + pinctrl-names = "default"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss1_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss1_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss1_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss1_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 5>, <24 9 5>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; }; &am43xx_pinmux { @@ -303,6 +345,86 @@ >; }; + pruss1_mdio_default: pruss1_mdio_default { + pinctrl-single,pins = < + /* gpmc_clk.pr1_mdio_mdclk */ + AM4372_IOPAD(0x88c, (PIN_OUTPUT | MUX_MODE5)) + /* xdma_event_intr0.pr1_mdio_data */ + AM4372_IOPAD(0xa70, (PIN_INPUT | MUX_MODE8)) + /* cam1_data6.gpio4_20 */ + AM4372_IOPAD(0xa00, (PIN_INPUT_PULLUP | MUX_MODE7)) + >; + }; + + pruss1_eth_default: pruss1_eth_default { + pinctrl-single,pins = < + /* dss_data0.pr1_mii_mt0_clk */ + AM4372_IOPAD(0x8a0, (PIN_INPUT | MUX_MODE2)) + /* dss_data5.pr1_mii0_txd0 */ + AM4372_IOPAD(0x8b4, (PIN_OUTPUT | MUX_MODE2)) + /* dss_data4.pr1_mii0_txd1 */ + AM4372_IOPAD(0x8b0, (PIN_OUTPUT | MUX_MODE2)) + /* dss_data3.pr1_mii0_txd2 */ + AM4372_IOPAD(0x8ac, (PIN_OUTPUT | MUX_MODE2)) + /* dss_data2.pr1_mii0_txd3 */ + AM4372_IOPAD(0x8a8, (PIN_OUTPUT | MUX_MODE2)) + /* dss_data11.pr1_mii0_rxd0 */ + AM4372_IOPAD(0x8cc, (PIN_INPUT | MUX_MODE5)) + /* dss_data10.pr1_mii0_rxd1 */ + AM4372_IOPAD(0x8c8, (PIN_INPUT | MUX_MODE5)) + /* dss_data9.pr1_mii0_rxd2 */ + AM4372_IOPAD(0x8c4, (PIN_INPUT | MUX_MODE5)) + /* dss_data8.pr1_mii0_rxd3 */ + AM4372_IOPAD(0x8c0, (PIN_INPUT | MUX_MODE5)) + /* dss_data1.pr1_mii0_txen */ + AM4372_IOPAD(0x8a4, (PIN_OUTPUT | MUX_MODE2)) + /* dss_data14.pr1_mii_mr0_clk */ + AM4372_IOPAD(0x8d8, (PIN_INPUT | MUX_MODE5)) + /* dss_data15.pr1_mii0_rxdv */ + AM4372_IOPAD(0x8dc, (PIN_INPUT | MUX_MODE5)) + /* dss_data13.pr1_mii0_rxer */ + AM4372_IOPAD(0x8d4, (PIN_INPUT | MUX_MODE5)) + /* dss_data12.pr1_mii0_rxlink */ + AM4372_IOPAD(0x8d0, (PIN_INPUT | MUX_MODE5)) + /* gpio5_10.pr1_mii0_crs */ + AM4372_IOPAD(0xa40, (PIN_INPUT | MUX_MODE5)) + /* gpio5_8.pr1_mii0_col */ + AM4372_IOPAD(0xa38, (PIN_INPUT | MUX_MODE5)) + /* gpmc_a6.pr1_mii_mt1_clk */ + AM4372_IOPAD(0x858, (PIN_INPUT | MUX_MODE5)) + /* gpmc_a5.pr1_mii1_txd0 */ + AM4372_IOPAD(0x854, (PIN_OUTPUT | MUX_MODE5)) + /* gpmc_a4.pr1_mii1_txd1 */ + AM4372_IOPAD(0x850, (PIN_OUTPUT | MUX_MODE5)) + /* gpmc_a3.pr1_mii1_txd2 */ + AM4372_IOPAD(0x84c, (PIN_OUTPUT | MUX_MODE5)) + /* gpmc_a2.pr1_mii1_txd3 */ + AM4372_IOPAD(0x848, (PIN_OUTPUT | MUX_MODE5)) + /* gpmc_a11.pr1_mii1_rxd0 */ + AM4372_IOPAD(0x86c, (PIN_INPUT | MUX_MODE5)) + /* gpmc_a10.pr1_mii1_rxd1 */ + AM4372_IOPAD(0x868, (PIN_INPUT | MUX_MODE5)) + /* gpmc_a9.pr1_mii1_rxd2 */ + AM4372_IOPAD(0x864, (PIN_INPUT | MUX_MODE5)) + /* gpmc_a8.pr1_mii1_rxd3 */ + AM4372_IOPAD(0x860, (PIN_INPUT | MUX_MODE5)) + /* gpmc_a0.pr1_mii1_txen */ + AM4372_IOPAD(0x840, (PIN_OUTPUT | MUX_MODE5)) + /* gpmc_a7.pr1_mii_mr1_clk */ + AM4372_IOPAD(0x85c, (PIN_INPUT | MUX_MODE5)) + /* gpmc_a1.pr1_mii1_rxdv */ + AM4372_IOPAD(0x844, (PIN_INPUT | MUX_MODE5)) + /* gpmc_wpn.pr1_mii1_rxer */ + AM4372_IOPAD(0x874, (PIN_INPUT | MUX_MODE5)) + /* gpio5_13.pr1_mii1_rxlink */ + AM4372_IOPAD(0xa4c, (PIN_INPUT | MUX_MODE5)) + /* gpio5_11.pr1_mii1_crs */ + AM4372_IOPAD(0xa44, (PIN_INPUT | MUX_MODE5)) + /* gpmc_be1n.pr1_mii1_col */ + AM4372_IOPAD(0x878, (PIN_INPUT | MUX_MODE5)) + >; + }; + qspi_pins_default: qspi-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ @@ -539,5 +661,18 @@ }; &pruss1_mdio { - status = "disabled"; + pinctrl-0 = <&pruss1_mdio_default>; + pinctrl-names = "default"; + status = "okay"; + + reset-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; /* PHY datasheet states 1uS min */ + + pruss1_eth0_phy: ethernet-phy@0 { + reg = <0>; + }; + + pruss1_eth1_phy: ethernet-phy@1 { + reg = <1>; + }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am571x-idk.dts v_kernel/arch/arm/boot/dts/ti/omap/am571x-idk.dts --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am571x-idk.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am571x-idk.dts 2026-04-21 11:35:27.637912894 +0200 @@ -165,6 +165,52 @@ default-state = "off"; }; }; + + /* Dual mac ethernet application node on icss1 */ + pruss1_eth { + compatible = "ti,am57-prueth"; + ti,prus = <&pru1_0>, <&pru1_1>; + ti,pruss-gp-mux-sel = <0>, /* GP, default */ + <4>; /* MII2, needed - PRUSS1_MII1 */ + sram = <&ocmcram1>; + ti,mii-rt = <&pruss1_mii_rt>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + ti,iep = <&pruss1_iep>; + interrupt-parent = <&pruss1_intc>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss1_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss1_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss1_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss1_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 7>, <24 9 7>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; +}; + +&pruss1_iep { + interrupt-parent = <&pruss1_intc>; + interrupts = <7 7 8>; + interrupt-names = "iep_cap_cmp"; }; &extcon_usb2 { @@ -210,9 +256,31 @@ }; &pruss1_mdio { - status = "disabled"; + status = "okay"; + reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; /* PHY datasheet states 1uS min */ + #address-cells = <1>; + #size-cells = <0>; + + pruss1_eth0_phy: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio3>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + }; + + pruss1_eth1_phy: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&gpio3>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + }; }; &pruss2_mdio { - status = "disabled"; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; /* PHY datasheet states 1uS min */ +}; + +&pruss2_eth { + ti,pruss-gp-mux-sel = <4>, /* MII2, needed for PRUSS1_MII0 */ + <4>; /* MII2, needed for PRUSS1_MII1 */ }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am572x-idk.dts v_kernel/arch/arm/boot/dts/ti/omap/am572x-idk.dts --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am572x-idk.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am572x-idk.dts 2026-04-21 11:35:27.638912896 +0200 @@ -28,10 +28,12 @@ pinctrl-2 = <&mmc2_pins_ddr_rev20>; }; -&pruss1_mdio { - status = "disabled"; +&pruss2_eth0_phy { + reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <2>; /* PHY datasheet states 1uS min */ }; -&pruss2_mdio { - status = "disabled"; +&pruss2_eth1_phy { + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <2>; /* PHY datasheet states 1uS min */ }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am574x-idk.dts v_kernel/arch/arm/boot/dts/ti/omap/am574x-idk.dts --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am574x-idk.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am574x-idk.dts 2026-04-21 11:35:27.638912896 +0200 @@ -40,10 +40,12 @@ status = "okay"; }; -&pruss1_mdio { - status = "disabled"; +&pruss2_eth0_phy { + reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <2>; /* PHY datasheet states 1uS min */ }; -&pruss2_mdio { - status = "disabled"; +&pruss2_eth1_phy { + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <2>; /* PHY datasheet states 1uS min */ }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am57-pruss.dtsi v_kernel/arch/arm/boot/dts/ti/omap/am57-pruss.dtsi --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am57-pruss.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am57-pruss.dtsi 2026-04-21 11:35:27.636912891 +0200 @@ -61,6 +61,17 @@ }; }; + pruss1_iep: iep@2e000 { + compatible = "ti,am5728-icss-iep"; + reg = <0x2e000 0x31c>; + clocks = <&pruss1_iepclk_mux>; + }; + + pruss1_ecap: ecap@30000 { + compatible = "ti,pruss-ecap"; + reg = <0x30000 0x60>; + }; + pruss1_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x58>; @@ -170,6 +181,17 @@ }; }; + pruss2_iep: iep@2e000 { + compatible = "ti,am5728-icss-iep"; + reg = <0x2e000 0x31c>; + clocks = <&pruss2_iepclk_mux>; + }; + + pruss2_ecap: ecap@30000 { + compatible = "ti,pruss-ecap"; + reg = <0x30000 0x60>; + }; + pruss2_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x58>; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am57xx-evm-ov10635.dtso v_kernel/arch/arm/boot/dts/ti/omap/am57xx-evm-ov10635.dtso --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am57xx-evm-ov10635.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am57xx-evm-ov10635.dtso 2026-04-21 11:35:27.640912901 +0200 @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include + +&vip1 { + status = "okay"; +}; + +&vip2 { + status = "okay"; +}; + + +&vip3 { + status = "okay"; +}; + +/ { + fragment@101 { + target-path = "/"; + + __overlay__ { + clk_ov10635: clock-gate { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_ov10635_fixed>; + enable-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + }; + + clk_ov10635_fixed: clock-fixed { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + #address-cells = <1>; + #size-cells = <0>; + + ov10635@30 { + compatible = "ovti,ov10635"; + reg = <0x30>; + clock-names = "xvclk"; + clocks = <&clk_ov10635>; + powerdown-gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + + port { + cam: endpoint { + remote-endpoint = <&vin3a_ep>; + hsync-active = <1>; + pclk-sample = <1>; + vsync-active = <1>; + bus-width = <8>; + }; + }; + }; +}; + +&vin3a { + vin3a_ep: endpoint { + remote-endpoint = <&cam>; + hsync-active = <1>; + pclk-sample = <1>; + vsync-active = <1>; + }; +}; + +&gpio6 { + p11 { + gpio-hog; + gpios = <11 GPIO_ACTIVE_LOW>; + line-name = "cm-camen-gpio"; + output-high; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi v_kernel/arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi --- linux-6.12.57/arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi 2026-04-21 11:35:27.640912901 +0200 @@ -155,6 +155,52 @@ compatible = "fixed-clock"; clock-frequency = <20000000>; }; + + /* Dual-MAC Ethernet application node on PRU-ICSS2 */ + pruss2_eth: pruss2-eth { + compatible = "ti,am57-prueth"; + ti,prus = <&pru2_0>, <&pru2_1>; + sram = <&ocmcram1>; + ti,mii-rt = <&pruss2_mii_rt>; + ti,iep = <&pruss2_iep>; + ti,ecap = <&pruss2_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss2_intc>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss2_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss2_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss2_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss2_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 7>, <24 9 7>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + +}; + +&pruss2_iep { + interrupt-parent = <&pruss2_intc>; + interrupts = <7 7 8>; + interrupt-names = "iep_cap_cmp"; }; &dra7_pmx_core { @@ -606,3 +652,18 @@ }; }; }; + +&pruss2_mdio { + status = "okay"; + pruss2_eth0_phy: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + }; + + pruss2_eth1_phy: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&gpio3>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/dra74x.dtsi v_kernel/arch/arm/boot/dts/ti/omap/dra74x.dtsi --- linux-6.12.57/arch/arm/boot/dts/ti/omap/dra74x.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/dra74x.dtsi 2026-04-21 11:35:27.651912930 +0200 @@ -229,4 +229,127 @@ }; }; }; + + target-module@190000 { /* 0x48990000, ap 23 2e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x190010 0x4>; + reg-names = "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x190000 0x10000>; + + vip2: vip@0 { + compatible = "ti,dra7-vip"; + status = "disabled"; + label = "vip2"; + reg = <0x0000 0x114>, + <0x5500 0xd8>, + <0x5700 0x18>, + <0x5800 0x80>, + <0x5a00 0xd8>, + <0x5c00 0x18>, + <0x5d00 0x80>, + <0xd000 0x400>; + reg-names = "vip", + "parser0", + "csc0", + "sc0", + "parser1", + "csc1", + "sc1", + "vpdma"; + interrupts = , + ; + /* CTRL_CORE_SMA_SW_1 */ + ti,vip-clk-polarity = <&scm_conf 0x534>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + vin3a: port@0 { + reg = <0>; + label = "vin3a"; + }; + vin4a: port@1 { + reg = <1>; + label = "vin4a"; + }; + vin3b: port@2 { + reg = <2>; + label = "vin3b"; + }; + vin4b: port@3 { + reg = <3>; + label = "vin4b"; + }; + }; + }; + }; + + target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x1b0000 0x4>, + <0x1b0010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b0000 0x10000>; + + vip3: vip@0 { + compatible = "ti,dra7-vip"; + status = "disabled"; + label = "vip3"; + reg = <0x0000 0x114>, + <0x5500 0xd8>, + <0x5700 0x18>, + <0x5800 0x80>, + <0x5a00 0xd8>, + <0x5c00 0x18>, + <0x5d00 0x80>, + <0xd000 0x400>; + reg-names = "vip", + "parser0", + "csc0", + "sc0", + "parser1", + "csc1", + "sc1", + "vpdma"; + interrupts = , + ; + /* CTRL_CORE_SMA_SW_1 */ + ti,vip-clk-polarity = <&scm_conf 0x534>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + vin5a: port@0 { + reg = <0>; + label = "vin5a"; + }; + vin6a: port@1 { + reg = <1>; + label = "vin6a"; + }; + }; + }; + }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi v_kernel/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi --- linux-6.12.57/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi 2026-04-21 11:35:27.647912920 +0200 @@ -4145,7 +4145,50 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x170000 0x10000>; - status = "disabled"; + + vip1: vip@0 { + compatible = "ti,dra7-vip"; + status = "disabled"; + label = "vip1"; + reg = <0x0000 0x114>, + <0x5500 0xd8>, + <0x5700 0x18>, + <0x5800 0x80>, + <0x5a00 0xd8>, + <0x5c00 0x18>, + <0x5d00 0x80>, + <0xd000 0x400>; + reg-names = "vip", + "parser0", + "csc0", + "sc0", + "parser1", + "csc1", + "sc1", + "vpdma"; + interrupts = , + ; + /* CTRL_CORE_SMA_SW_1 */ + ti,vip-clk-polarity = <&scm_conf 0x534>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + vin1a: port@0 { + reg = <0>; + }; + vin2a: port@1 { + reg = <1>; + }; + vin1b: port@2 { + reg = <2>; + }; + vin2b: port@3 { + reg = <3>; + }; + }; + }; }; target-module@190000 { /* 0x48990000, ap 23 2e.0 */ diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/boot/dts/ti/omap/Makefile v_kernel/arch/arm/boot/dts/ti/omap/Makefile --- linux-6.12.57/arch/arm/boot/dts/ti/omap/Makefile 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/boot/dts/ti/omap/Makefile 2026-04-21 11:35:27.612912828 +0200 @@ -82,6 +82,10 @@ omap4-var-stk-om44.dtb \ omap4-xyboard-mz609.dtb \ omap4-xyboard-mz617.dtb + +am335x-bone-hdmi-00a0-dtbs := am335x-bonegreen-eco.dtb \ + am335x-bone-hdmi-00a0.dtbo + dtb-$(CONFIG_SOC_AM33XX) += \ am335x-baltos-ir2110.dtb \ am335x-baltos-ir3220.dtb \ @@ -93,12 +97,15 @@ am335x-boneblue.dtb \ am335x-bonegreen.dtb \ am335x-bonegreen-wireless.dtb \ + am335x-bonegreen-eco.dtb \ + am335x-bone-hdmi-00a0.dtbo \ am335x-chiliboard.dtb \ am335x-cm-t335.dtb \ am335x-evm.dtb \ am335x-evmsk.dtb \ am335x-guardian.dtb \ am335x-icev2.dtb \ + am335x-icev2-prueth.dtb \ am335x-lxm.dtb \ am335x-moxa-uc-2101.dtb \ am335x-moxa-uc-8100-me-t.dtb \ @@ -124,6 +131,7 @@ am43x-epos-evm.dtb \ am437x-cm-t43.dtb \ am437x-gp-evm.dtb \ + am437x-gp-evm-hdmi.dtb \ am437x-idk-evm.dtb \ am437x-sbc-t43.dtb \ am437x-sk-evm.dtb @@ -158,6 +166,7 @@ am57xx-idk-lcd-osd101t2045.dtbo \ am57xx-idk-lcd-osd101t2587.dtbo \ dra7-evm.dtb \ + am57xx-evm-ov10635.dtbo \ dra72-evm.dtb \ dra72-evm-revc.dtb \ dra71-evm.dtb \ @@ -173,3 +182,10 @@ dm8148-t410.dtb \ dm8168-evm.dtb \ dra62x-j5eco-evm.dtb + +# Enable support for device-tree overlays +DTC_FLAGS_am335x-boneblack += -@ +DTC_FLAGS_am335x-boneblack-wireless += -@ +DTC_FLAGS_am335x-bonegreen += -@ +DTC_FLAGS_am335x-bonegreen-wireless += -@ +DTC_FLAGS_am335x-bonegreen-eco += -@ diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/configs/multi_v7_defconfig v_kernel/arch/arm/configs/multi_v7_defconfig --- linux-6.12.57/arch/arm/configs/multi_v7_defconfig 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/configs/multi_v7_defconfig 2026-04-21 11:35:27.712913090 +0200 @@ -1,6 +1,9 @@ CONFIG_SYSVIPC=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_PREEMPT=y CONFIG_CGROUPS=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y @@ -198,6 +201,7 @@ CONFIG_BCM47XX_SPROM=y CONFIG_EFI_CAPSULE_LOADER=m CONFIG_MTD=y +CONFIG_MTD_TESTS=m CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y @@ -230,6 +234,7 @@ CONFIG_QCOM_FASTRPC=m CONFIG_APDS9802ALS=y CONFIG_ISL29003=y +CONFIG_SRAM_DMA_HEAP=y CONFIG_PCI_ENDPOINT_TEST=m CONFIG_EEPROM_AT24=y CONFIG_BLK_DEV_SD=y @@ -309,6 +314,7 @@ CONFIG_USB_NET_SMSC95XX=y CONFIG_WCN36XX=m CONFIG_BRCMFMAC=m +CONFIG_IWLWIFI=m CONFIG_MWIFIEX=m CONFIG_MWIFIEX_SDIO=m CONFIG_RT2X00=m @@ -343,6 +349,7 @@ CONFIG_INPUT_MAX8997_HAPTIC=m CONFIG_INPUT_GPIO_DECODER=m CONFIG_INPUT_CPCAP_PWRBUTTON=m +CONFIG_INPUT_TPS65219_PWRBUTTON=m CONFIG_INPUT_AXP20X_PEK=m CONFIG_INPUT_DA9063_ONKEY=m CONFIG_INPUT_ADXL34X=m @@ -362,6 +369,7 @@ CONFIG_SERIAL_8250_OMAP=y CONFIG_SERIAL_8250_MT6577=y CONFIG_SERIAL_8250_UNIPHIER=y +CONFIG_SERIAL_8250_PRUSS=m CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y @@ -451,6 +459,7 @@ CONFIG_SPI_GPIO=m CONFIG_SPI_FSL_DSPI=m CONFIG_SPI_OMAP24XX=y +CONFIG_SPI_TI_QSPI=m CONFIG_SPI_ORION=y CONFIG_SPI_PL022=y CONFIG_SPI_ROCKCHIP=m @@ -566,6 +575,7 @@ CONFIG_SAMA5D4_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=m CONFIG_DW_WATCHDOG=y +CONFIG_OMAP_WATCHDOG=m CONFIG_DAVINCI_WATCHDOG=m CONFIG_ORION_WATCHDOG=y CONFIG_RN5T618_WATCHDOG=y @@ -617,6 +627,7 @@ CONFIG_MFD_TPS65090=y CONFIG_MFD_TPS65217=y CONFIG_MFD_TPS65218=y +CONFIG_MFD_TPS65219=y CONFIG_MFD_TPS6586X=y CONFIG_MFD_TPS65910=y CONFIG_MFD_STM32_LPTIMER=m @@ -666,6 +677,7 @@ CONFIG_REGULATOR_TPS65090=y CONFIG_REGULATOR_TPS65217=y CONFIG_REGULATOR_TPS65218=y +CONFIG_REGULATOR_TPS65219=y CONFIG_REGULATOR_TPS6586X=y CONFIG_REGULATOR_TPS65910=y CONFIG_REGULATOR_TWL4030=y @@ -676,6 +688,7 @@ CONFIG_MEDIA_SUPPORT=m CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_TI_VIP=m CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_ASPEED=m @@ -707,6 +720,7 @@ CONFIG_VIDEO_VIVID=m CONFIG_VIDEO_S5C73M3=m CONFIG_VIDEO_S5K6A3=m +CONFIG_VIDEO_OV1063X=m CONFIG_VIDEO_ADV7180=m CONFIG_VIDEO_ADV7604=m CONFIG_VIDEO_ADV7604_CEC=y @@ -733,6 +747,7 @@ CONFIG_DRM_SUN4I=m CONFIG_DRM_OMAP=m CONFIG_OMAP5_DSS_HDMI=y +CONFIG_DRM_TILCDC=m CONFIG_DRM_MSM=m CONFIG_DRM_FSL_DCU=m CONFIG_DRM_TEGRA=y @@ -743,11 +758,13 @@ CONFIG_DRM_PANEL_EDP=y CONFIG_DRM_PANEL_SAMSUNG_LD9040=m CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m +CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m CONFIG_DRM_PANEL_RAYDIUM_RM68200=m CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_ITE_IT66121=m CONFIG_DRM_LVDS_CODEC=m CONFIG_DRM_NXP_PTN3460=m CONFIG_DRM_PARADE_PS8622=m @@ -837,6 +854,7 @@ CONFIG_SND_SOC_TEGRA_ALC5632=m CONFIG_SND_SOC_TEGRA_MAX98090=m CONFIG_SND_SOC_DAVINCI_MCASP=m +CONFIG_SND_SOC_OMAP_HDMI=m CONFIG_SND_SOC_AC97_CODEC=m CONFIG_SND_SOC_AK4642=m CONFIG_SND_SOC_CPCAP=m @@ -919,6 +937,7 @@ CONFIG_USB_CONFIGFS_F_HID=y CONFIG_USB_CONFIGFS_F_UVC=y CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ZERO=m CONFIG_USB_ETH=m CONFIG_TYPEC=m CONFIG_TYPEC_UCSI=m @@ -1009,6 +1028,7 @@ CONFIG_RTC_DRV_DA9063=m CONFIG_RTC_DRV_EFI=m CONFIG_RTC_DRV_DIGICOLOR=m +CONFIG_RTC_DRV_OMAP=m CONFIG_RTC_DRV_S3C=m CONFIG_RTC_DRV_SA1100=m CONFIG_RTC_DRV_SH=m @@ -1050,6 +1070,10 @@ CONFIG_RZN1_DMAMUX=m CONFIG_RCAR_DMAC=y CONFIG_RENESAS_USB_DMAC=m +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_DMABUF_HEAPS_CARVEOUT=y CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_MMIO=y CONFIG_STAGING=y @@ -1094,8 +1118,10 @@ CONFIG_EXYNOS_IOMMU=y CONFIG_QCOM_IOMMU=y CONFIG_REMOTEPROC=y +CONFIG_REMOTEPROC_CDEV=y CONFIG_OMAP_REMOTEPROC=m CONFIG_OMAP_REMOTEPROC_WATCHDOG=y +CONFIG_WKUP_M3_RPROC=m CONFIG_KEYSTONE_REMOTEPROC=m CONFIG_QCOM_Q6V5_MSS=m CONFIG_QCOM_SYSMON=m @@ -1147,11 +1173,32 @@ CONFIG_SOC_TI=y CONFIG_KEYSTONE_NAVIGATOR_QMSS=y CONFIG_KEYSTONE_NAVIGATOR_DMA=y +CONFIG_AMX3_PM=m +CONFIG_WKUP_M3_IPC=m CONFIG_RASPBERRYPI_POWER=y CONFIG_QCOM_CPR=y CONFIG_QCOM_RPMHPD=y CONFIG_QCOM_RPMPD=y CONFIG_ROCKCHIP_PM_DOMAINS=y +CONFIG_TI_PRUSS=m +CONFIG_TI_PRUETH=m +CONFIG_HSR=m +CONFIG_NET_SCHED=y +CONFIG_NET_CLS_FLOWER=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y CONFIG_TI_SCI_PM_DOMAINS=y CONFIG_ARM_EXYNOS_BUS_DEVFREQ=m CONFIG_ARM_TEGRA_DEVFREQ=m @@ -1159,8 +1206,10 @@ CONFIG_EXTCON_MAX14577=m CONFIG_EXTCON_MAX77693=m CONFIG_EXTCON_MAX8997=m +CONFIG_EXTCON_PALMAS=m CONFIG_EXTCON_USB_GPIO=y CONFIG_TI_AEMIF=y +CONFIG_TI_EMIF_SRAM=m CONFIG_STM32_FMC2_EBI=y CONFIG_EXYNOS5422_DMC=m CONFIG_IIO=y @@ -1201,6 +1250,8 @@ CONFIG_PWM_BCM2835=y CONFIG_PWM_BRCMSTB=m CONFIG_PWM_FSL_FTM=m +CONFIG_PWM_TIECAP=m +CONFIG_PWM_TIEHRPWM=m CONFIG_PWM_MESON=m CONFIG_PWM_RCAR=m CONFIG_PWM_RENESAS_TPU=y @@ -1293,6 +1344,7 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_XCBC=m CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_USER_API_RNG=m @@ -1309,6 +1361,10 @@ CONFIG_CRYPTO_CRC32_ARM_CE=m CONFIG_CRYPTO_DEV_SUN4I_SS=m CONFIG_CRYPTO_DEV_FSL_CAAM=m +CONFIG_CRYPTO_DEV_OMAP=m +CONFIG_CRYPTO_DEV_OMAP_SHAM=m +CONFIG_CRYPTO_DEV_OMAP_AES=m +CONFIG_CRYPTO_DEV_OMAP_DES=m CONFIG_CRYPTO_DEV_EXYNOS_RNG=m CONFIG_CRYPTO_DEV_S5P=m CONFIG_CRYPTO_DEV_ATMEL_AES=m diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm/configs/omap2plus_defconfig v_kernel/arch/arm/configs/omap2plus_defconfig --- linux-6.12.57/arch/arm/configs/omap2plus_defconfig 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm/configs/omap2plus_defconfig 2026-04-21 11:35:27.714913095 +0200 @@ -386,6 +386,7 @@ CONFIG_INPUT_MISC=y CONFIG_INPUT_CPCAP_PWRBUTTON=m CONFIG_INPUT_TPS65218_PWRBUTTON=m +CONFIG_INPUT_TPS65219_PWRBUTTON=m CONFIG_INPUT_TWL4030_PWRBUTTON=m CONFIG_INPUT_UINPUT=m CONFIG_INPUT_PALMAS_PWRBUTTON=m @@ -454,6 +455,7 @@ CONFIG_MFD_TI_LP873X=y CONFIG_MFD_TI_LP87565=y CONFIG_MFD_TPS65218=y +CONFIG_MFD_TPS65219=y CONFIG_MFD_TPS65910=y CONFIG_TWL6040_CORE=y CONFIG_REGULATOR_CPCAP=y @@ -470,6 +472,7 @@ CONFIG_REGULATOR_TPS6507X=y CONFIG_REGULATOR_TPS65217=y CONFIG_REGULATOR_TPS65218=y +CONFIG_REGULATOR_TPS65219=y CONFIG_REGULATOR_TPS65910=y CONFIG_REGULATOR_TWL4030=y CONFIG_RC_CORE=m @@ -499,6 +502,7 @@ CONFIG_DRM_PANEL_TPO_TD028TTEC1=m CONFIG_DRM_PANEL_TPO_TD043MTEA1=m CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_ITE_IT66121=m CONFIG_DRM_SIMPLE_BRIDGE=m CONFIG_DRM_TI_TFP410=m CONFIG_DRM_TI_TPD12S015=m diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am6254xxl.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am6254xxl.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am6254xxl.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am6254xxl.dtsi 2026-04-21 11:35:28.516915199 +0200 @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * DTS for AM625 SiP SoC family in Quad core configuration and 512MiB RAM. + * + * Webpage: https://www.ti.com/product/AM625SIP + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am625.dtsi" + +/ { + model = "Texas Instruments AM6254xxl SiP"; + compatible = "ti,am6254xxl"; + + memory@80000000 { + device_type = "memory"; + /* 512MiB of integrated RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x20000000>; + bootph-all; + }; + +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am6254xxl-sk.dts v_kernel/arch/arm64/boot/dts/ti/k3-am6254xxl-sk.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am6254xxl-sk.dts 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am6254xxl-sk.dts 2026-04-21 11:35:28.516915199 +0200 @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * AM6254xxl SiP SK: https://www.ti.com/lit/df/sprr482b/sprr482b.zip + * Webpage: https://www.ti.com/tool/SK-AM62-SIP + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am6254xxl.dtsi" +#include "k3-am62x-sk-common.dtsi" + +/ { + model = "Texas Instruments AM6254xxl SK"; + compatible = "ti,am6254xxl-sk", "ti,am6254xxl"; + + vdd_sd_dv: regulator-4 { + /* Output of TLV71033 */ + bootph-all; + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc_5v0>; + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + vcc_1v8: regulator-5 { + /* output of TPS6282518DMQ */ + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&main_pmx0 { + main_mmc0_pins_default: main-mmc0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + main_rgmii2_pins_default: main-rgmii2-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ + AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ + AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ + AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ + AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ + AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ + AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ + AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ + AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ + AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ + >; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ + >; + }; +}; + +&vmain_pd { + bootph-all; +}; + +&vcc_5v0 { + bootph-all; +}; + +&vcc_3v3_sys { + bootph-all; +}; + +&vdd_mmc1 { + bootph-all; +}; + +&main_gpio0 { + bootph-all; +}; + +&main_gpio1 { + bootph-all; +}; + +&main_i2c1 { + bootph-all; + exp1: gpio@22 { + bootph-all; + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "PRU_DETECT", "MMC1_SD_EN", + "VPP_LDO_EN", "EXP_PS_3V3_En", + "EXP_PS_5V0_En", "EXP_HAT_DETECT", + "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", + "UART1_FET_BUF_EN", "WL_LT_EN", + "GPIO_HDMI_RSTn", "CSI_GPIO1", + "CSI_GPIO2", "PRU_3V3_EN", + "HDMI_INTn", "PD_I2C_IRQ", + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", + "MCASP1_FET_SEL", "UART1_FET_SEL", + "TSINT#", "IO_EXP_TEST_LED"; + + interrupt-parent = <&main_gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + }; +}; + +&sdhci0 { + bootph-all; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + disable-wp; +}; + +&sdhci1 { + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&fss { + bootph-all; +}; + +&ospi0 { + bootph-all; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + flash@0 { + bootph-all; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + bootph-all; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-pre-ram; + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts v_kernel/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts 2026-04-21 11:35:28.513915191 +0200 @@ -65,6 +65,14 @@ pmsg-size = <0x8000>; }; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x8000000>; + linux,cma-default; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; no-map; @@ -419,6 +427,12 @@ >; }; + mikrobus_pwm_pins_default: mikrobus-pwm-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01a4, PIN_INPUT, 2) /* (B20) MCASP0_ACLKX.ECAP2_IN_APWM_OUT */ + >; + }; + main_uart0_pins_default: main-uart0-default-pins { bootph-all; pinctrl-single,pins = < @@ -496,6 +510,20 @@ AM62X_IOPAD(0x0078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ >; }; + + touchscreen_pins_default: touchscreen-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b4, PIN_OUTPUT, 7) /* (A13) SPI0_CS0.GPIO1_15 */ + AM62X_IOPAD(0x00a0, PIN_INPUT, 7) /* (K25) GPMC0_WPn.GPIO0_39 */ + >; + }; + + backlight_pins_default: bl-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0000, PIN_OUTPUT, 7) /* (H24) OSPI0_CLK.GPIO0_0 */ + AM62X_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (C13) SPI0_CS1.EHRPWM0_B */ + >; + }; }; &mcu_pmx0 { @@ -604,7 +632,7 @@ reg = <1>; reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>; reset-assert-us = <25>; - reset-deassert-us = <60000>; /* T2 */ + reset-deassert-us = <35>; }; }; @@ -926,3 +954,9 @@ 0 0 0 0 >; }; + +&ecap2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mikrobus_pwm_pins_default>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-beagleplay-lincolntech-lcd185-panel.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am625-beagleplay-lincolntech-lcd185-panel.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-beagleplay-lincolntech-lcd185-panel.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am625-beagleplay-lincolntech-lcd185-panel.dtso 2026-04-21 11:35:28.513915191 +0200 @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * Lincoln tech Solutions OLDI panel (LCD185-101CT) and touch DT overlay for AM625-BeaglePlay + * + * AM625-BeaglePlay: https://www.beagleboard.org/boards/beagleplay + * Panel datasheet: https://lincolntechsolutions.com/wp-content/uploads/2023/04/LCD185-101CTL1ARNTT_DS_R1.3.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins_default>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + enable-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; + pwms = <&epwm0 1 20000 0>; + }; + + lcd { + compatible = "lincolntech,lcd185-101ct", "panel-simple"; + backlight = <&backlight>; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * Swapping them will cause an error in the dss oldi driver. + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_0_out>; + }; + }; + port@1 { + reg = <1>; + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_1_out>; + }; + }; + }; + }; +}; + +&dss { + status = "okay"; +}; + +&oldi0 { + status = "okay"; + ti,companion-oldi = <&oldi1>; +}; + +&oldi1 { + status = "okay"; + ti,secondary-oldi; + ti,companion-oldi = <&oldi0>; +}; + +&oldi0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + oldi_0_in: endpoint { + remote-endpoint = <&dpi0_out0>; + }; + }; + + port@1 { + reg = <1>; + oldi_0_out: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; +}; + +&oldi1_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + oldi_1_in: endpoint { + remote-endpoint = <&dpi0_out1>; + }; + }; + + port@1 { + reg = <1>; + oldi_1_out: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: Output to OLDI */ + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dpi0_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&oldi_0_in>; + }; + dpi0_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&oldi_1_in>; + }; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@57 { + compatible = "atmel,24c256"; + reg = <0x57>; + }; + + touchscreen@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins_default>; + interrupt-parent = <&main_gpio0>; + interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&main_gpio0 39 GPIO_ACTIVE_HIGH>; + reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <1920>; + touchscreen-size-y = <1200>; + }; +}; + +&epwm0 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am625.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am625.dtsi 2026-04-21 11:35:28.516915199 +0200 @@ -108,7 +108,7 @@ a53_opp_table: opp-table { compatible = "operating-points-v2-ti-cpu"; opp-shared; - syscon = <&wkup_conf>; + syscon = <&opp_efuse_table>; opp-200000000 { opp-hz = /bits/ 64 <200000000>; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-minimal.dts v_kernel/arch/arm64/boot/dts/ti/k3-am625-minimal.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-minimal.dts 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am625-minimal.dts 2026-04-21 11:35:28.513915191 +0200 @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM625 Minimal + * + * DT supports loading U-Boot binaries via UART and kernel image, + * initramfs, and kernel devicetree through SD. + * + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "k3-am625.dtsi" + +/ { + compatible = "ti,am625-minimal", "ti,am625"; + model = "Texas Instruments AM625 MINIMAL"; + + aliases { + serial2 = &main_uart0; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@80000000 { + bootph-pre-ram; + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@80000000 { + reg = <0x00 0x80000000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + alignment = <0x1000>; + no-map; + }; + }; +}; + +&main_pmx0 { + /* First pad number is ALW package and second is AMC package */ + main_uart0_pins_default: main-uart0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ + >; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */ + AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */ + AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22/A19) MMC1_DAT0 */ + AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21/B19) MMC1_DAT1 */ + AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21/B20) MMC1_DAT2 */ + AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22/C19) MMC1_DAT3 */ + AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17/C15) MMC1_SDCD */ + >; + }; +}; + +&main_uart0 { + bootph-all; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; +}; + +&sdhci1 { + /* SD/MMC */ + bootph-all; + status = "okay"; + no-1-8-v; + sdhci-caps-mask = <0x00000007 0x00200000>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + disable-wp; +}; + +&cpsw3g { + status = "disabled"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso 1970-01-01 01:00:00.000000000 +0100 @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only OR MIT -/* - * Copyright (C) 2024 PHYTEC America LLC - * Author: Nathan Morrisson - */ - -/dts-v1/; -/plugin/; - -&vdd_core { - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; -}; - -&a53_opp_table { - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-supported-hw = <0x01 0x0004>; - }; -}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-sk.dts v_kernel/arch/arm64/boot/dts/ti/k3-am625-sk.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-sk.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am625-sk.dts 2026-04-21 11:35:28.514915194 +0200 @@ -7,8 +7,11 @@ /dts-v1/; +#include "k3-am625.dtsi" #include "k3-am62x-sk-common.dtsi" +#include "k3-timesync-router.h" + / { compatible = "ti,am625-sk", "ti,am625"; model = "Texas Instruments AM625 SK"; @@ -23,60 +26,13 @@ }; memory@80000000 { + bootph-pre-ram; device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; }; - vmain_pd: regulator-0 { - /* TPS65988 PD CONTROLLER OUTPUT */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vmain_pd"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_5v0: regulator-1 { - /* Output of LM34936 */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vmain_pd>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_3v3_sys: regulator-2 { - /* output of LM61460-Q1 */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vmain_pd>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: regulator-3 { - /* TPS22918DBVR */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vcc_3v3_sys>; - gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; - }; - vdd_sd_dv: regulator-4 { /* Output of TLV71033 */ bootph-all; @@ -105,6 +61,22 @@ }; }; +&vmain_pd { + bootph-all; +}; + +&vcc_5v0 { + bootph-all; +}; + +&vcc_3v3_sys { + bootph-all; +}; + +&vdd_mmc1 { + bootph-all; +}; + &main_pmx0 { main_mmc0_pins_default: main-mmc0-default-pins { bootph-all; @@ -140,23 +112,6 @@ >; }; - ospi0_pins_default: ospi0-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ - AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ - AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ - AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ - AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ - AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ - AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ - AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ - AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ - AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ - AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ - >; - }; - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { bootph-all; pinctrl-single,pins = < @@ -227,6 +182,11 @@ &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; + + cpts@3d000 { + /* MAP HW3_TS_PUSH to GENF1 */ + ti,pps = <2 1>; + }; }; &cpsw_port2 { @@ -243,23 +203,11 @@ }; }; -&mailbox0_cluster0 { - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - &fss { bootph-all; }; &ospi0 { - bootph-all; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ospi0_pins_default>; - flash@0 { bootph-all; compatible = "jedec,spi-nor"; @@ -272,6 +220,7 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + cdns,phy-mode; partitions { bootph-all; @@ -321,3 +270,10 @@ &tlv320aic3106 { DVDD-supply = <&vcc_1v8>; }; + +×ync_router { + mux-reg-masks-state = < + K3_TS_OFFSET(12, 0x0001ffff, 17) + >; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-sk-lincolntech-lcd185-panel.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am625-sk-lincolntech-lcd185-panel.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-sk-lincolntech-lcd185-panel.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am625-sk-lincolntech-lcd185-panel.dtso 2026-04-21 11:35:28.513915191 +0200 @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * Lincoln tech Solutions OLDI panel (LCD185-101CT) and touch DT overlay for AM625-SK + * + * AM625-SKEVM: https://www.ti.com/tool/SK-AM62 + * Panel datasheet: https://lincolntechsolutions.com/wp-content/uploads/2023/04/LCD185-101CTL1ARNTT_DS_R1.3.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + display { + compatible = "lincolntech,lcd185-101ct", "panel-simple"; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * Swapping them will cause an error in the dss oldi driver. + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_0_out>; + }; + }; + port@1 { + reg = <1>; + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_1_out>; + }; + }; + }; + }; +}; + +&dss { + status = "okay"; +}; + +&oldi0 { + status = "okay"; + ti,companion-oldi = <&oldi1>; +}; + +&oldi1 { + status = "okay"; + ti,secondary-oldi; +}; + +&oldi0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + oldi_0_in: endpoint { + remote-endpoint = <&dpi0_out0>; + }; + }; + + port@1 { + reg = <1>; + oldi_0_out: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; +}; + +&oldi1_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + oldi_1_in: endpoint { + remote-endpoint = <&dpi0_out1>; + }; + }; + + port@1 { + reg = <1>; + oldi_1_out: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: Output to OLDI */ + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dpi0_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&oldi_0_in>; + }; + dpi0_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&oldi_1_in>; + }; + }; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@57 { + compatible = "atmel,24c256"; + reg = <0x57>; + }; + + touchscreen@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + interrupt-parent = <&exp1>; + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&exp1 22 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1920>; + touchscreen-size-y = <1200>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-sk-m2-cc3351.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am625-sk-m2-cc3351.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-sk-m2-cc3351.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am625-sk-m2-cc3351.dtso 2026-04-21 11:35:28.514915194 +0200 @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * DT Overlay for M.2-CC3351 board to connect to the M.2 connector on AM625-SK. + * + * Product page for board: https://www.ti.com/tool/M2-CC3351 + * CC3351 Datasheet: https://www.ti.com/lit/ds/symlink/cc3351.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&{/} { + wlan_lten: regulator-30 { + compatible = "regulator-fixed"; + regulator-name = "wlan_lten"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_mmc1>; + gpios = <&exp1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wlan_en: regulator-31 { + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&wlan_lten>; + enable-active-high; + gpios = <&main_gpio0 71 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_pins_default>; + }; +}; + +&main_pmx0 { + wlan_en_pins_default: wlan-en-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x124, PIN_OUTPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */ + >; + }; + + main_mmc2_pins_default: main-mmc2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ + AM62X_IOPAD(0x118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ + AM62X_IOPAD(0x114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */ + AM62X_IOPAD(0x110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */ + AM62X_IOPAD(0x10c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */ + AM62X_IOPAD(0x108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */ + AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ + >; + }; + + main_wlirq_pins_default: main-wlirq-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x128, PIN_INPUT, 7) /* (B23) MMC2_SDWP.GPIO0_72 */ + >; + }; +}; + +&sdhci2 { + status = "okay"; + bootph-all; + vmmc-supply = <&wlan_en>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc2_pins_default>; + bus-width = <4>; + non-removable; + ti,fails-without-test-cd; + cap-power-off-card; + keep-power-in-suspend; + ti,driver-strength-ohm = <50>; + + #address-cells = <1>; + #size-cells = <0>; + wifi: cc3300@2 { + compatible = "ti,cc3300"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&main_wlirq_pins_default>; + interrupt-parent = <&main_gpio0>; + interrupts = <72 IRQ_TYPE_EDGE_FALLING>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-sk-microtips-mf101hie-panel.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am625-sk-microtips-mf101hie-panel.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-sk-microtips-mf101hie-panel.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am625-sk-microtips-mf101hie-panel.dtso 2026-04-21 11:35:28.514915194 +0200 @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * Microtips integrated OLDI panel (MF-101HIEBCAF0) and touch DT overlay for AM625 - SK + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + display { + compatible = "microtips,mf-101hiebcaf0", "panel-simple"; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * Swapping them will cause an error in the dss oldi driver. + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_0_out>; + }; + }; + port@1 { + reg = <1>; + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_1_out>; + }; + }; + }; + }; +}; + +&dss { + status = "okay"; +}; + +&oldi0 { + status = "okay"; + ti,companion-oldi = <&oldi1>; +}; + +&oldi1 { + status = "okay"; + ti,secondary-oldi; + ti,companion-oldi = <&oldi0>; +}; + +&oldi0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + oldi_0_in: endpoint { + remote-endpoint = <&dpi0_out0>; + }; + }; + + port@1 { + reg = <1>; + oldi_0_out: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; +}; + +&oldi1_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + oldi_1_in: endpoint { + remote-endpoint = <&dpi0_out1>; + }; + }; + + port@1 { + reg = <1>; + oldi_1_out: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: Output to OLDI */ + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dpi0_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&oldi_0_in>; + }; + dpi0_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&oldi_1_in>; + }; + }; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&exp1>; + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-sk-rpi-hdr-ehrpwm.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am625-sk-rpi-hdr-ehrpwm.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-sk-rpi-hdr-ehrpwm.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am625-sk-rpi-hdr-ehrpwm.dtso 2026-04-21 11:35:28.514915194 +0200 @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling RPi header with GPIOs and ePWMs for AM625-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0038, PIN_INPUT, 7) /* (E24) OSPI0_CSn3.GPIO0_14 */ + AM62X_IOPAD(0x0088, PIN_INPUT, 7) /* (L24) GPMC0_OEn_REn.GPIO0_33 */ + AM62X_IOPAD(0x0094, PIN_INPUT, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ + AM62X_IOPAD(0x009c, PIN_INPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ + AM62X_IOPAD(0x00a0, PIN_INPUT, 7) /* (K25) GPMC0_WPn.GPIO0_39 */ + AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ + AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ + AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ + >; + }; + + rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins{ + pinctrl-single,pins = < + AM62X_IOPAD(0x01d0, PIN_INPUT, 7) /* (A15) UART0_CTSn.GPIO1_22 */ + >; + }; + + rpi_header_ehrpwm0_pins_default: rpi-header-ehrpwm0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01ac, PIN_OUTPUT, 6) /* (E19) MCASP0_AFSR.EHRPWM0_A */ + AM62X_IOPAD(0x01b0, PIN_OUTPUT, 6) /* (A20) MCASP0_ACLKR.EHRPWM0_B */ + >; + }; + + rpi_header_ehrpwm1_pins_default: rpi-header-ehrpwm1-default-pins{ + pinctrl-single,pins = < + AM62X_IOPAD(0x019c, PIN_OUTPUT, 6) /* (B18) MCASP0_AXR1.EHRPWM1_A */ + AM62X_IOPAD(0x01a0, PIN_OUTPUT, 6) /* (E18) MCASP0_AXR0.EHRPWM1_B */ + >; + }; +}; + +&main_uart1 { + /* Disable FW debug logs */ + status = "disabled"; +}; + +&main_i2c1 { + gpio@22 { + p05-hog { + /* P05 - EXP_PS_3V3_EN */ + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_3V3_EN"; + }; + + p06-hog { + /* P06 - EXP_PS_5V0_EN */ + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_5V0_EN"; + }; + + p25-hog { + /* P25 - UART1_FET_SEL */ + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "UART1_FET_SEL"; + }; + }; +}; + +&epwm0 { + /* Pin 12/40 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm0_pins_default>; + status = "okay"; +}; + +&epwm1 { + /* Pin 36/33 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm1_pins_default>; + status = "okay"; +}; + +&main_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; + +&main_gpio1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio1_pins_default>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-ivy.dts v_kernel/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-ivy.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-ivy.dts 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-ivy.dts 2026-04-21 11:35:28.515915197 +0200 @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/ivy-carrier-board + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-nonwifi.dtsi" +#include "k3-am62-verdin-ivy.dtsi" + +/ { + model = "Toradex Verdin AM62 on Ivy Board"; + compatible = "toradex,verdin-am62-nonwifi-ivy", + "toradex,verdin-am62-nonwifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-ivy.dts v_kernel/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-ivy.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-ivy.dts 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-ivy.dts 2026-04-21 11:35:28.515915197 +0200 @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/ivy-carrier-board + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-wifi.dtsi" +#include "k3-am62-verdin-ivy.dtsi" + +/ { + model = "Toradex Verdin AM62 WB on Ivy Board"; + compatible = "toradex,verdin-am62-wifi-ivy", + "toradex,verdin-am62-wifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62a7.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a7.dtsi 2026-04-21 11:35:28.520915209 +0200 @@ -48,6 +48,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 135 0>; }; cpu1: cpu@1 { @@ -62,6 +64,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 136 0>; }; cpu2: cpu@2 { @@ -76,6 +80,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 137 0>; }; cpu3: cpu@3 { @@ -90,6 +96,51 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 138 0>; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&opp_efuse_table>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-phyboard-lyra-rdk.dts v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-phyboard-lyra-rdk.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-phyboard-lyra-rdk.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-phyboard-lyra-rdk.dts 2026-04-21 11:35:28.518915204 +0200 @@ -16,3 +16,7 @@ "phytec,am62a-phycore-som", "ti,am62a7"; model = "PHYTEC phyBOARD-Lyra AM62A7"; }; + +&cpsw3g_phy3 { + ti,rx-internal-delay = ; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-csi2-ox05b1s.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-csi2-ox05b1s.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-csi2-ox05b1s.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-csi2-ox05b1s.dtso 2026-04-21 11:35:28.518915204 +0200 @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OX05B1S Camera Module + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ox05b1s_fixed: ox05b1s-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + /* CAM port */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ox05b1s: camera@36 { + compatible = "ovti,ox05b"; + reg = <0x36>; + + clocks = <&clk_ox05b1s_fixed>; + clock-names = "inck"; + + pwdn-gpios = <&exp1 13 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <480000000>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts 2026-04-21 11:35:28.520915209 +0200 @@ -12,16 +12,23 @@ #include #include "k3-am62a7.dtsi" +#include "k3-timesync-router.h" + / { compatible = "ti,am62a7-sk", "ti,am62a7"; model = "Texas Instruments AM62A7 SK"; aliases { serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart0; serial3 = &main_uart1; mmc0 = &sdhci0; mmc1 = &sdhci1; + rtc0 = &wkup_rtc0; + rtc1 = &tps659312; + ethernet0 = &cpsw_port1; + spi0 = &ospi0; }; chosen { @@ -33,6 +40,7 @@ /* 4G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>, <0x00000008 0x80000000 0x00000000 0x80000000>; + bootph-all; }; reserved-memory { @@ -49,6 +57,42 @@ linux,cma-default; }; + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99900000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x1e00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; @@ -61,13 +105,22 @@ no-map; }; - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + rtos_ipc_memory_region: ipc-memories@a0000000 { compatible = "shared-dma-pool"; - reg = <0x00 0x9c900000 0x00 0x01e00000>; + reg = <0x00 0xa0000000 0x00 0x01000000>; no-map; }; }; + opp-table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + vmain_pd: regulator-0 { /* TPS25750 PD CONTROLLER OUTPUT */ compatible = "regulator-fixed"; @@ -109,6 +162,7 @@ regulator-boot-on; enable-active-high; gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + bootph-all; }; vcc_3v3_sys: regulator-4 { @@ -250,11 +304,24 @@ >; }; - main_uart0_pins_default: main-uart0-default-pins { + main_uart0_tx_pins_default: main-uart0-tx-default-pins { pinctrl-single,pins = < - AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ >; + bootph-all; + }; + + main_uart0_rx_pins_default: main-uart0-rx-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ + >; + bootph-all; + }; + + main_uart0_rx_pins_wakeup: main-uart0-rx-wakeup-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x1c8, PIN_INPUT | PIN_WKUP_EN, 0) /* (E14) UART0_RXD */ + >; }; main_uart1_pins_default: main-uart1-default-pins { @@ -278,6 +345,7 @@ AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ >; + bootph-all; }; main_i2c2_pins_default: main-i2c2-default-pins { @@ -314,6 +382,7 @@ AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ >; + bootph-all; }; usr_led_pins_default: usr-led-default-pins { @@ -333,6 +402,7 @@ AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ >; + bootph-all; }; main_rgmii1_pins_default: main-rgmii1-default-pins { @@ -350,6 +420,7 @@ AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */ AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */ >; + bootph-all; }; main_mcasp1_pins_default: main-mcasp1-default-pins { @@ -372,6 +443,23 @@ AM62AX_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ >; }; + + ospi0_pins_default: ospi0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62AX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L22) OSPI0_CLK */ + AM62AX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (H21) OSPI0_CSn0 */ + AM62AX_IOPAD(0x000c, PIN_INPUT, 0) /* (J21) OSPI0_D0 */ + AM62AX_IOPAD(0x0010, PIN_INPUT, 0) /* (J18) OSPI0_D1 */ + AM62AX_IOPAD(0x0014, PIN_INPUT, 0) /* (J19) OSPI0_D2 */ + AM62AX_IOPAD(0x0018, PIN_INPUT, 0) /* (H18) OSPI0_D3 */ + AM62AX_IOPAD(0x001c, PIN_INPUT, 0) /* (K21) OSPI0_D4 */ + AM62AX_IOPAD(0x0020, PIN_INPUT, 0) /* (H19) OSPI0_D5 */ + AM62AX_IOPAD(0x0024, PIN_INPUT, 0) /* (J20) OSPI0_D6 */ + AM62AX_IOPAD(0x0028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62AX_IOPAD(0x0008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */ + >; + }; }; &mcu_pmx0 { @@ -511,6 +599,7 @@ #interrupt-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + bootph-all; gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", "BT_EN_SOC", "MMC1_SD_EN", @@ -599,6 +688,7 @@ &sdhci0 { /* eMMC */ + bootph-all; status = "okay"; non-removable; pinctrl-names = "default"; @@ -614,10 +704,12 @@ pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; + bootph-all; }; &main_gpio0 { status = "okay"; + bootph-all; }; &main_gpio1 { @@ -630,8 +722,13 @@ &main_uart0 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&main_uart0_tx_pins_default>, <&main_uart0_rx_pins_default>; + pinctrl-1 = <&main_uart0_tx_pins_default>, <&main_uart0_rx_pins_wakeup>; + wakeup-source = <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; + bootph-all; }; /* Main UART1 is used for TIFS firmware logs */ @@ -641,6 +738,11 @@ status = "reserved"; }; +/* main_timer2 is used by C7x DSP */ +&main_timer2 { + status = "reserved"; +}; + &usbss0 { status = "okay"; ti,vbus-divider; @@ -656,6 +758,10 @@ }; }; +&usb0_phy_ctrl { + bootph-all; +}; + &usbss1 { status = "okay"; }; @@ -670,12 +776,22 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>; + + cpts@3d000 { + /* MAP HW3_TS_PUSH to GENF1 */ + ti,pps = <2 1>; + }; +}; + +&phy_gmii_sel { + bootph-all; }; &cpsw_port1 { status = "okay"; phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy0>; + bootph-all; }; &cpsw_port2 { @@ -692,6 +808,75 @@ ti,rx-internal-delay = ; ti,fifo-depth = ; ti,min-output-impedance; + bootph-all; + }; +}; + +&fss { + status = "okay"; +}; + +&ospi0 { + bootph-all; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + flash@0{ + compatible = "spi-nand"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + cdns,phy-mode; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + partition@0 { + label = "ospi_nand.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi_nand.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi_nand.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi_nand.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi_nand.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@2000000 { + label = "ospi_nand.rootfs"; + reg = <0x2000000 0x5fc0000>; + }; + + partition@7fc0000 { + label = "ospi_nand.phypattern"; + reg = <0x7fc0000 0x40000>; + bootph-all; + }; + }; }; }; @@ -721,7 +906,7 @@ &dss_ports { /* VP2: DPI Output */ - port@1 { + hdmi0_dss: port@1 { reg = <1>; dpi1_out: endpoint { @@ -729,3 +914,68 @@ }; }; }; + +&mailbox0_cluster0 { + ti,mbox-num-fifos = <2>; + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + ti,mbox-num-fifos = <2>; + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + ti,mbox-num-fifos = <2>; + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&c7x_0 { + mboxes = <&mailbox0_cluster1>, <&mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status = "okay"; +}; + +/* main_rti4 is used by C7x DSP */ +&main_rti4 { + status = "reserved"; +}; + +×ync_router { + /* Use Time Sync Router to map GENF1 input to HW3_TS_PUSH output */ + mux-reg-masks-state = < + /* pps [cpsw cpts genf1] in17 -> out12 [cpsw cpts hw3_push] */ + K3_TS_OFFSET(12, 0x0001ffff, 17) + >; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-e3-max-opp.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-e3-max-opp.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-e3-max-opp.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-e3-max-opp.dtso 2026-04-21 11:35:28.518915204 +0200 @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay to run AM62A7-SK Rev E3 board at maximum performance + * Requires VDD_CORE to be at 0.85V + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + opp-table { + /* + * Add 1.4GHz and disable lower OPPs for max A53 performance + * Only for AM62A7-SK Rev E3 board + * Requires VDD_CORE to be at 0.85V + */ + opp-200000000 { + status = "disabled"; + }; + + opp-400000000 { + status = "disabled"; + }; + + opp-600000000 { + status = "disabled"; + }; + + opp-800000000 { + status = "disabled"; + }; + + opp-1000000000 { + status = "disabled"; + }; + + opp-1250000000 { + status = "disabled"; + }; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; +}; + +&c7x_0 { + /* + * Override C7x frequency to 1 GHz for max performance + * Only for AM62A7-SK Rev E3 board + * Requires VDD_CORE to be at 0.85V + */ + clocks = <&k3_clks 208 0>; + assigned-clocks = <&k3_clks 208 0>; + assigned-clock-rates = <1000000000>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-edgeai.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-edgeai.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-edgeai.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-edgeai.dtso 2026-04-21 11:35:28.518915204 +0200 @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT overlay for AM62A edgeAI carveouts + * Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/reserved-memory} { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + edgeai_memory_region: edgeai-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x02000000>; + no-map; + }; + + edgeai_shared_region: edgeai_shared-memories { + compatible = "dma-heap-carveout"; + reg = <0x00 0xa3000000 0x00 0x0ac00000>; + }; + + edgeai_core_heaps: edgeai-core-heap-memory@adc00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xadc00000 0x00 0x12400000>; + no-map; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso 2026-04-21 11:35:28.519915207 +0200 @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for second CPSW3G port in RGMII mode using SK-ETHERNET-DC01 + * Add-On Daughtercard with AM62A7-SK. + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@f0000/ethernet@8000000/ethernet-ports/port@2"; + }; +}; + +&cpsw3g { + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; +}; + +&cpsw_port2 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + #address-cells = <1>; + #size-cells = <0>; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&main_pmx0 { + main_rgmii2_pins_default: main-rgmii2-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x0184, PIN_INPUT, 0) /* (AA21) RGMII2_RD0 */ + AM62AX_IOPAD(0x0188, PIN_INPUT, 0) /* (Y20) RGMII2_RD1 */ + AM62AX_IOPAD(0x018c, PIN_INPUT, 0) /* (AB21) RGMII2_RD2 */ + AM62AX_IOPAD(0x0190, PIN_INPUT, 0) /* (AB20) RGMII2_RD3 */ + AM62AX_IOPAD(0x0180, PIN_INPUT, 0) /* (AA20) RGMII2_RXC */ + AM62AX_IOPAD(0x017c, PIN_INPUT, 0) /* (W18) RGMII2_RX_CTL */ + AM62AX_IOPAD(0x016c, PIN_INPUT, 0) /* (AA19) RGMII2_TD0 */ + AM62AX_IOPAD(0x0170, PIN_INPUT, 0) /* (Y18) RGMII2_TD1 */ + AM62AX_IOPAD(0x0174, PIN_INPUT, 0) /* (AA18) RGMII2_TD2 */ + AM62AX_IOPAD(0x0178, PIN_INPUT, 0) /* (W17) RGMII2_TD3 */ + AM62AX_IOPAD(0x0168, PIN_INPUT, 0) /* (AB19) RGMII2_TXC */ + AM62AX_IOPAD(0x0164, PIN_INPUT, 0) /* (Y19) RGMII2_TX_CTL */ + >; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso 2026-04-21 11:35:28.519915207 +0200 @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * DT Overlay for Fusion 2 (FPD-Link IV) board on SK-AM62A + * https://www.ti.com/tool/J7EXPA01EVM + * + * Copyright (C) 2024 D3 Embedded - https://www.d3embedded.com + */ + + /dts-v1/; + /plugin/; + +#include + +&{/} { + clk_fusion2_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&exp2 { + p9-hog { + /* P9 - CSI_RSTz */ + gpio-hog; + gpios = <9 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI_RSTz"; + }; + + p19-hog { + /* P19 -CSI_SEL2 */ + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "CSI_SEL2"; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + deser@3d { + compatible = "ti,ds90ub9702-q1"; + reg = <0x3d>; + + clock-names = "refclk"; + clocks = <&clk_fusion2_25M_fixed>; + + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub9702_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub9702_0_csi_out>; + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion.dtso 2026-04-21 11:35:28.519915207 +0200 @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Fusion (FPD-Link III) board on SK-AM62A + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&exp2 { + p19-hog { + /* P19 - CSI_SEL2 */ + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "CSI_SEL2"; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deser@3d { + compatible = "ti,ds90ub960-q1"; + reg = <0x3d>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-m2-cc3351.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-m2-cc3351.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-m2-cc3351.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-m2-cc3351.dtso 2026-04-21 11:35:28.519915207 +0200 @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * DT Overlay for M.2-CC3351 board to connect to the M.2 connector on AM625-SK. + * + * Product page for board: https://www.ti.com/tool/M2-CC3351 + * CC3351 Datasheet: https://www.ti.com/lit/ds/symlink/cc3351.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&{/} { + wlan_lten: regulator-30 { + compatible = "regulator-fixed"; + regulator-name = "wlan_lten"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_mmc1>; + gpios = <&exp1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wlan_en: regulator-31 { + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&wlan_lten>; + enable-active-high; + gpios = <&main_gpio0 71 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_pins_default>; + }; +}; + +&main_pmx0 { + wlan_en_pins_default: wlan-en-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x124, PIN_OUTPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */ + >; + }; + + main_mmc2_pins_default: main-mmc2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ + AM62X_IOPAD(0x118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ + AM62X_IOPAD(0x114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */ + AM62X_IOPAD(0x110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */ + AM62X_IOPAD(0x10c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */ + AM62X_IOPAD(0x108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */ + AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ + >; + }; + + main_wlirq_pins_default: main-wlirq-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x128, PIN_INPUT, 7) /* (B23) MMC2_SDWP.GPIO0_72 */ + >; + }; +}; + +&sdhci2 { + status = "okay"; + bootph-all; + vmmc-supply = <&wlan_en>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc2_pins_default>; + bus-width = <4>; + non-removable; + ti,fails-without-test-cd; + cap-power-off-card; + keep-power-in-suspend; + ti,driver-strength-ohm = <50>; + + #address-cells = <1>; + #size-cells = <0>; + wifi: cc33xx@2 { + compatible = "ti,cc3300"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&main_wlirq_pins_default>; + interrupt-parent = <&main_gpio0>; + interrupts = <72 IRQ_TYPE_EDGE_FALLING>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-rpi-hdr-ehrpwm.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-rpi-hdr-ehrpwm.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-rpi-hdr-ehrpwm.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-rpi-hdr-ehrpwm.dtso 2026-04-21 11:35:28.519915207 +0200 @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling RPi header with GPIOs and ePWMs on AM62A-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x0038, PIN_INPUT, 7) /* (G20) OSPI0_CSn3.GPIO0_14 */ + AM62AX_IOPAD(0x0088, PIN_INPUT, 7) /* (L17) GPMC0_OEn_REn.GPIO0_33 */ + AM62AX_IOPAD(0x0094, PIN_INPUT, 7) /* (M18) GPMC0_BE1n.GPIO0_36 */ + AM62AX_IOPAD(0x009c, PIN_INPUT, 7) /* (R17) GPMC0_WAIT1.GPIO0_38 */ + AM62AX_IOPAD(0x00a0, PIN_INPUT, 7) /* (K17) GPMC0_WPn.GPIO0_39 */ + AM62AX_IOPAD(0x00a4, PIN_INPUT, 7) /* (K18) GPMC0_DIR.GPIO0_40 */ + AM62AX_IOPAD(0x00a8, PIN_INPUT, 7) /* (M19) GPMC0_CSn0.GPIO0_41 */ + AM62AX_IOPAD(0x00ac, PIN_INPUT, 7) /* (M21) GPMC0_CSn1.GPIO0_42 */ + >; + }; + + rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins{ + pinctrl-single,pins = < + AM62AX_IOPAD(0x0194, PIN_INPUT, 7) /* (C19) MCASP0_AXR3.GPIO1_7 */ + AM62AX_IOPAD(0x0198, PIN_INPUT, 7) /* (B19) MCASP0_AXR2.GPIO1_8 */ + AM62AX_IOPAD(0x01a4, PIN_INPUT, 7) /* (A19) MCASP0_ACLKX.GPIO1_11 */ + AM62AX_IOPAD(0x01b4, PIN_INPUT, 7) /* (D16) SPI0_CS0.GPIO1_15 */ + AM62AX_IOPAD(0x01b8, PIN_INPUT, 7) /* (C16) SPI0_CS1.GPIO1_16 */ + AM62AX_IOPAD(0x01bc, PIN_INPUT, 7) /* (A17) SPI0_CLK.GPIO1_17 */ + AM62AX_IOPAD(0x01c0, PIN_INPUT, 7) /* (B15) SPI0_D0.GPIO1_18 */ + AM62AX_IOPAD(0x01c4, PIN_INPUT, 7) /* (E15) SPI0_D1.GPIO1_19 */ + AM62AX_IOPAD(0x01d0, PIN_INPUT, 7) /* (F14) UART0_CTSn.GPIO1_22 */ + AM62AX_IOPAD(0x01d8, PIN_INPUT, 7) /* (B17) MCAN0_TX.GPIO1_24 */ + AM62AX_IOPAD(0x01dc, PIN_INPUT, 7) /* (C18) MCAN0_RX.GPIO1_25 */ + >; + }; + + rpi_header_ehrpwm0_pins_default: rpi-header-ehrpwm0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x01ac, PIN_OUTPUT, 6) /* (B21) MCASP0_AFSR.EHRPWM0_A */ + AM62AX_IOPAD(0x01b0, PIN_OUTPUT, 6) /* (A21) MCASP0_ACLKR.EHRPWM0_B */ + >; + }; + + rpi_header_ehrpwm1_pins_default: rpi-header-ehrpwm1-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x019c, PIN_OUTPUT, 6) /* (B18) MCASP0_AXR1.EHRPWM1_A */ + AM62AX_IOPAD(0x01a0, PIN_OUTPUT, 6) /* (B20) MCASP0_AXR0.EHRPWM1_B */ + >; + }; +}; + +&main_uart1 { + /* Disable FW debug logs */ + status = "disabled"; +}; + +&main_i2c1 { + gpio@22 { + p05-hog { + /* P05 - EXP_PS_3V3_EN */ + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_3V3_EN"; + }; + + p06-hog { + /* P06 - EXP_PS_5V0_EN */ + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_5V0_EN"; + }; + + p25-hog { + /* P25 - UART1_FET_SEL */ + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "UART1_FET_SEL"; + }; + }; +}; + +&epwm0 { + /* Pin 35/12 of J3 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm0_pins_default>; +}; + +&epwm1 { + /* Pin 36/33 of J3 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm1_pins_default>; +}; + +&main_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; + +&main_gpio1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio1_pins_default>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-ub954-evm.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-ub954-evm.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a7-sk-ub954-evm.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a7-sk-ub954-evm.dtso 2026-04-21 11:35:28.519915207 +0200 @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for DS90UB954-Q1EVM FPDLink-III deserializer board on SK-AM62A + * https://www.ti.com/tool/DS90UB954-Q1EVM + * + * Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&exp2 { + p19-hog { + /* P19 - CSI_SEL2 */ + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "CSI_SEL2"; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deser@3d { + compatible = "ti,ds90ub954-q1"; + reg = <0x3d>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@2 { + reg = <2>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62a.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a.dtsi 2026-04-21 11:35:28.518915204 +0200 @@ -46,10 +46,38 @@ interrupts = ; }; + system-idle-states { + system_partial_io: system-partial-io { + compatible = "system-idle-state"; + idle-state-name = "off-wake"; + }; + + system_io_ddr: system-io-ddr { + compatible = "system-idle-state"; + idle-state-name = "mem-deep"; + }; + + system_deep_sleep: system-deep-sleep { + compatible = "system-idle-state"; + idle-state-name = "mem"; + }; + + system_mcu_only: system-mcu-only { + compatible = "system-idle-state"; + idle-state-name = "mem-mcu-active"; + }; + + system_standby: system-standby { + compatible = "system-idle-state"; + idle-state-name = "standby"; + }; + }; + cbass_main: bus@f0000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; + bootph-all; ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ @@ -67,6 +95,7 @@ <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30300000 0x00 0x30300000 0x00 0x00001000>, /* MCRC64 */ <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ @@ -104,6 +133,7 @@ <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ + bootph-all; }; cbass_wakeup: bus@b00000 { @@ -115,6 +145,7 @@ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ + bootph-all; }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi 2026-04-21 11:35:28.517915202 +0200 @@ -51,6 +51,7 @@ compatible = "ti,am654-phy-gmii-sel"; reg = <0x4044 0x8>; #phy-cells = <1>; + bootph-all; }; epwm_tbclk: clock-controller@4130 { @@ -76,6 +77,12 @@ assigned-clock-parents = <&k3_clks 157 18>; #clock-cells = <0>; }; + + dss_clk_ctrl: dss_clk_ctrl@8300 { + compatible = "ti,am625-dss-clk-ctrl", "syscon"; + reg = <0x8300 0x4>; + }; + }; dmss: bus@48000000 { @@ -84,6 +91,7 @@ #size-cells = <2>; dma-ranges; ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; + bootph-all; ti,sci-dev-id = <25>; @@ -96,6 +104,7 @@ #mbox-cells = <1>; interrupt-names = "rx_012"; interrupts = ; + bootph-all; }; inta_main_dmss: interrupt-controller@48000000 { @@ -131,6 +140,7 @@ ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ + bootph-all; }; main_pktdma: dma-controller@485c0000 { @@ -167,6 +177,7 @@ <0x2c>, /* FLOW_CPSW_RX_CHAN */ <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ + bootph-all; }; }; @@ -216,20 +227,24 @@ mbox-names = "rx", "tx"; mboxes = <&secure_proxy_main 12>, <&secure_proxy_main 13>; + bootph-all; k3_pds: power-controller { compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; + bootph-all; }; k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; + bootph-all; }; k3_reset: reset-controller { compatible = "ti,sci-reset"; #reset-cells = <2>; + bootph-all; }; }; @@ -239,6 +254,23 @@ dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, <&main_pktdma 0x7507 0>; dma-names = "tx", "rx1", "rx2"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; + + rng: rng@40910000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x00 0x40910000 0x00 0x7d>; + interrupts = ; + status = "reserved"; /* Reserved for OP-TEE */ + }; + }; + + crc: crc@30300000 { + compatible = "ti,am62-mcrc64"; + reg = <0x00 0x30300000 0x00 0x1000>; + clocks = <&k3_clks 116 0>; + power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; }; secure_proxy_sa3: mailbox@43600000 { @@ -254,14 +286,29 @@ * firmware on non-MPU processors */ status = "disabled"; + bootph-all; }; main_pmx0: pinctrl@f4000 { - compatible = "pinctrl-single"; + compatible = "ti,am654-padconf", "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x25c>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; + /* + * pinctrl IP DOES NOT give any functional IRQs when a + * system is in active state. This IRQ is only a dummy IRQ + * that is being used to trick Linux into thinking that + * GIC can potentially recieve an interrupt from this IP. + * This helps us setup the IO daisychain wakeups for deep + * sleep via chained wake IRQs. + * Please feel free to assign a different number here as + * long as it is unused if 99 conflicts with another use case. + */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + bootph-all; }; main_esm: esm@420000 { @@ -282,6 +329,7 @@ assigned-clock-parents = <&k3_clks 36 3>; power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + bootph-all; }; main_timer1: timer@2410000 { @@ -653,6 +701,7 @@ dr_mode = "otg"; snps,usb2-gadget-lpm-disable; snps,usb2-lpm-disable; + bootph-all; }; }; @@ -698,6 +747,7 @@ cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; + cdns,phase-detect-selector = <2>; clocks = <&k3_clks 75 7>; assigned-clocks = <&k3_clks 75 7>; assigned-clock-parents = <&k3_clks 75 8>; @@ -745,6 +795,7 @@ phys = <&phy_gmii_sel 1>; mac-address = [00 00 00 00 00 00]; ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; + bootph-all; }; cpsw_port2: port@2 { @@ -764,6 +815,7 @@ clocks = <&k3_clks 13 0>; clock-names = "fck"; bus_freq = <1000000>; + bootph-all; }; cpts@3d000 { @@ -778,6 +830,13 @@ }; }; + timesync_router: mux-controller@a40000 { + compatible = "reg-mux"; + reg = <0x0 0xa40000 0x0 0x800>; + #mux-control-cells = <1>; + status = "disabled"; + }; + hwspinlock: spinlock@2a000000 { compatible = "ti,am64-hwspinlock"; reg = <0x00 0x2a000000 0x00 0x1000>; @@ -940,6 +999,33 @@ status = "disabled"; }; + eqep0: counter@23200000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23200000 0x00 0x100>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 59 0>; + interrupts = ; + status = "disabled"; + }; + + eqep1: counter@23210000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23210000 0x00 0x100>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 60 0>; + interrupts = ; + status = "disabled"; + }; + + eqep2: counter@23220000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23220000 0x00 0x100>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 62 0>; + interrupts = ; + status = "disabled"; + }; + mcasp0: audio-controller@2b00000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x00 0x02b00000 0x00 0x2000>, @@ -1002,8 +1088,10 @@ ti_csi2rx0: ticsi2rx@30102000 { compatible = "ti,j721e-csi2rx-shim"; - dmas = <&main_bcdma_csi 0 0x5000 0>; - dma-names = "rx0"; + dmas = <&main_bcdma_csi 0 0x5000 0>, <&main_bcdma_csi 0 0x5001 0>, + <&main_bcdma_csi 0 0x5002 0>, <&main_bcdma_csi 0 0x5003 0>, + <&main_bcdma_csi 0 0x5004 0>, <&main_bcdma_csi 0 0x5005 0>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5"; reg = <0x00 0x30102000 0x00 0x1000>; power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; #address-cells = <2>; @@ -1014,6 +1102,9 @@ cdns_csi2rx0: csi-bridge@30101000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30101000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -1079,6 +1170,7 @@ <&k3_clks 186 2>; clock-names = "fck", "vp1", "vp2"; interrupts = ; + ti,clk-ctrl = <&dss_clk_ctrl>; status = "disabled"; dss_ports: ports { @@ -1092,6 +1184,19 @@ reg = <0x00 0x30210000 0x00 0x10000>; clocks = <&k3_clks 204 2>; power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; + sram = <&oc_sram>; + }; + + c7x_0: dsp@7e000000 { + compatible = "ti,am62a-c7xv-dsp"; + reg = <0x00 0x7e000000 0x00 0x00100000>; + reg-names = "l2sram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <208>; + ti,sci-proc-ids = <0x04 0xff>; + resets = <&k3_reset 208 1>; + firmware-name = "am62a-c71_0-fw"; + status = "disabled"; }; e5010: jpeg-encoder@fd20000 { @@ -1103,4 +1208,24 @@ power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; interrupts = ; }; + + memorycontroller: memory-controller@f300000 { + compatible = "ti,am62a-ddrss"; + reg = <0x00 0x0f300000 0x00 0x200>; + reg-names = "ss_cfg"; + ranges = <0x00 0x00 0x00 0x0f308000 0x00 0x5e10>; + interrupts = ; + power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 170 0>; + #address-cells = <2>; + #size-cells = <2>; + + ddr: ddr@0 { + compatible = "cdns,j7-ddr"; + reg = <0x00 0x0000 0x00 0x6cc>, + <0x00 0x2000 0x00 0x6a0>, + <0x00 0x4000 0x00 0x1e10>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + }; + }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi 2026-04-21 11:35:28.517915202 +0200 @@ -6,13 +6,25 @@ */ &cbass_mcu { + mcu_ram: sram@79100000 { + compatible = "mmio-sram"; + reg = <0x00 0x79100000 0x00 0x80000>; + ranges = <0x00 0x00 0x79100000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + + mcu1-sram@0 { + reg = <0x0 0x80000>; + }; + }; + mcu_pmx0: pinctrl@4084000 { compatible = "pinctrl-single"; reg = <0x00 0x04084000 0x00 0x88>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; - status = "disabled"; + bootph-all; }; mcu_esm: esm@4100000 { @@ -175,4 +187,30 @@ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; + + mcu_r5fss0: r5fss@79000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x79000000 0x00 0x79000000 0x8000>, + <0x79020000 0x00 0x79020000 0x8000>; + power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + mcu_r5fss0_core0: r5f@79000000 { + compatible = "ti,am62-r5f"; + reg = <0x79000000 0x00008000>, + <0x79020000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <9>; + ti,sci-proc-ids = <0x03 0xff>; + resets = <&k3_reset 9 1>; + firmware-name = "am62a-mcu-r5f0_0-fw"; + ti,atcm-enable = <0>; + ti,btcm-enable = <1>; + ti,loczrama = <0>; + sram = <&mcu_ram>; + }; + }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi 2026-04-21 11:35:28.518915204 +0200 @@ -2,19 +2,28 @@ /* * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals * - * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ */ +#include + &cbass_wakeup { wkup_conf: bus@43000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x43000000 0x20000>; + bootph-all; chipid: chipid@14 { compatible = "ti,am654-chipid"; reg = <0x14 0x4>; + bootph-all; + }; + + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; }; cpsw_mac_syscon: ethernet-mac-syscon@200 { @@ -31,16 +40,49 @@ compatible = "ti,am62-usb-phy-ctrl", "syscon"; reg = <0x4018 0x4>; }; + + ddr_pmctrl: syscon@80d0 { + compatible = "ti,am62-ddr-pmctrl", "syscon"; + reg = <0x80d0 0x4>; + bootph-pre-ram; + }; + + canuart_wake: syscon@18300 { + compatible = "ti,am62-canuart-wake", "syscon"; + reg = <0x18300 0x44>; + bootph-pre-ram; + }; }; - wkup_uart0: serial@2b300000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x2b300000 0x00 0x100>; - interrupts = ; + wkup_uart_conf: target-module@2b300050 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0 0x2b300050 0 0x4>, + <0 0x2b300054 0 0x4>, + <0 0x2b300058 0 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + ti,no-reset-on-init; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; - clock-names = "fclk"; - status = "disabled"; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2b300000 0x100000>; + + wkup_uart0: serial@0 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0 0x100>; + interrupts = ; + status = "disabled"; + bootph-pre-ram; + }; }; wkup_i2c0: i2c@2b200000 { @@ -76,6 +118,31 @@ status = "reserved"; }; + wkup_r5fss0: r5fss@78000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + wkup_r5fss0_core0: r5f@78000000 { + compatible = "ti,am62-r5f"; + reg = <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <121>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 121 1>; + firmware-name = "am62a-wkup-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + wkup_vtm0: temperature-sensor@b00000 { compatible = "ti,j7200-vtm"; reg = <0x00 0xb00000 0x00 0x400>, diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62d2.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62d2.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62d2.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62d2.dtsi 2026-04-21 11:35:28.520915209 +0200 @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for AM62D2 SoC family in Quad core configuration + * + * TRM: https://www.ti.com/lit/pdf/sprujd4 + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am62a7.dtsi" + +/ { + model = "Texas Instruments K3 AM62D SoC"; + compatible = "ti,am62d2"; +}; + +/delete-node/ &vpu; /* Video Codec is disabled in AM62D2 SoC */ +/delete-node/ &e5010; /* JPEG Encoder is disabled in AM62D2 SoC */ diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts v_kernel/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts 2026-04-21 11:35:28.520915209 +0200 @@ -0,0 +1,1017 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * AM62D2 EVM: https://www.ti.com/lit/zip/sprcal5 + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include +#include +#include +#include "k3-am62d2.dtsi" +#include "k3-timesync-router.h" + +/ { + compatible = "ti,am62d2-evm", "ti,am62d2"; + model = "Texas Instruments AM62D2 EVM"; + + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + rtc0 = &wkup_rtc0; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + spi0 = &ospi0; + }; + + chosen { + stdout-path = &main_uart0; + }; + + memory@80000000 { + device_type = "memory"; + /* 4G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + bootph-all; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + bootph-pre-ram; + + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x2000000>; + alloc-ranges = <0x00 0xc0000000 0x00 0x2000000>; + linux,cma-default; + }; + + secure_tfa_ddr: tfa@80000000 { + reg = <0x00 0x80000000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99900000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0xf00000>; + no-map; + bootph-pre-ram; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x01000000>; + no-map; + }; + }; + + opp-table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + + vout_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vout_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vmain_pd: regulator-1 { + /* Output of TPS22811 */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vout_pd>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_5v0: regulator-2 { + /* Output of TPS630702RNMR */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3v3_main: regulator-3 { + /* output of LM5141-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_main"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vdd_mmc1: regulator-4 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_sys>; + regulator-boot-on; + enable-active-high; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_3v3_sys: regulator-5 { + /* output of TPS222965DSGT */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_main>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vddshv_sdio: regulator-6 { + /* output of TLV7103318QDSERQ1 */ + compatible = "regulator-gpio"; + regulator-name = "vddshv_sdio"; + pinctrl-names = "default"; + pinctrl-0 = <&vddshv_sdio_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v0>; + regulator-boot-on; + gpios = <&main_gpio0 59 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + bootph-all; + }; + + codec_audio: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM62D2-EVM"; + + simple-audio-card,routing = + /* J3A (tad5x1x@50) */ + "J3A IN1 Source Mux", "J3A Playback", + "J3A IN2 Source Mux", "J3A Playback", + /* J3B (tad5x1x@51) */ + "J3B IN1 Source Mux", "J3B Playback", + "J3B IN2 Source Mux", "J3B Playback", + /* J4A (tad5x1x@52) */ + "J4A IN1 Source Mux", "J4A Playback", + "J4A IN2 Source Mux", "J4A Playback", + /* J4B (tad5x1x@53) */ + "J4B IN1 Source Mux", "J4B Playback", + "J4B IN2 Source Mux", "J4B Playback"; + + simple-audio-card,dai-link@0 { + format = "dsp_a"; + bitclock-master = <&master0>; + frame-master = <&master0>; + + master0: cpu { + sound-dai = <&mcasp2>; + system-clock-direction-out; + }; + + codec@0 { + sound-dai = <&pcm6240>; + }; + }; + + simple-audio-card,dai-link@1 { + format = "dsp_a"; + bitclock-master = <&master1>; + frame-master = <&master1>; + + master1: cpu { + sound-dai = <&mcasp2>; + system-clock-direction-out; + }; + + codec@1 { + sound-dai = <&tad5x1x_50>; + playback-only; + }; + }; + + simple-audio-card,dai-link@2 { + format = "dsp_a"; + bitclock-master = <&master2>; + frame-master = <&master2>; + + master2: cpu { + sound-dai = <&mcasp2>; + system-clock-direction-out; + }; + + codec@2 { + sound-dai = <&tad5x1x_51>; + playback-only; + }; + }; + + simple-audio-card,dai-link@3 { + format = "dsp_a"; + bitclock-master = <&master3>; + frame-master = <&master3>; + + master3: cpu { + sound-dai = <&mcasp2>; + system-clock-direction-out; + }; + + codec@3 { + sound-dai = <&tad5x1x_52>; + playback-only; + }; + }; + + simple-audio-card,dai-link@4 { + format = "dsp_a"; + bitclock-master = <&master4>; + frame-master = <&master4>; + + master4: cpu { + sound-dai = <&mcasp2>; + system-clock-direction-out; + }; + + codec@4 { + sound-dai = <&tad5x1x_53>; + playback-only; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pins_default>; + + led-0 { + label = "am62d-evm:green:heartbeat"; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + }; +}; + +&mcu_pmx0 { + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + AM62DX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */ + AM62DX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */ + AM62DX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */ + AM62DX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */ + >; + bootph-all; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + AM62DX_MCU_IOPAD(0x004c, PIN_INPUT, 0) /* (D13) WKUP_I2C0_SCL */ + AM62DX_MCU_IOPAD(0x0050, PIN_INPUT, 0) /* (E13) WKUP_I2C0_SDA */ + >; + bootph-all; + }; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + bootph-all; + status = "reserved"; +}; + +&main_pmx0 { + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x01c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ + AM62DX_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ + >; + bootph-all; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D17) I2C0_SCL */ + AM62DX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (E16) I2C0_SDA */ + >; + bootph-all; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C17) I2C1_SCL */ + AM62DX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (E17) I2C1_SDA */ + >; + bootph-all; + }; + + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (M22) GPMC0_CSn2.I2C2_SCL */ + AM62DX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (M20) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_mmc0_pins_default: main-mmc0-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x0220, PIN_INPUT_PULLUP, 0) /* (Y6) MMC0_CMD */ + AM62DX_IOPAD(0x0218, PIN_OUTPUT, 0) /* (AB7) MMC0_CLK */ + AM62DX_IOPAD(0x0214, PIN_INPUT_PULLUP, 0) /* (AA6) MMC0_DAT0 */ + AM62DX_IOPAD(0x0210, PIN_INPUT_PULLUP, 0) /* (AB6) MMC0_DAT1 */ + AM62DX_IOPAD(0x020c, PIN_INPUT_PULLUP, 0) /* (Y7) MMC0_DAT2 */ + AM62DX_IOPAD(0x0208, PIN_INPUT_PULLUP, 0) /* (AA7) MMC0_DAT3 */ + AM62DX_IOPAD(0x0204, PIN_INPUT_PULLUP, 0) /* (Y8) MMC0_DAT4 */ + AM62DX_IOPAD(0x0200, PIN_INPUT_PULLUP, 0) /* (W7) MMC0_DAT5 */ + AM62DX_IOPAD(0x01fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */ + AM62DX_IOPAD(0x01f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */ + >; + bootph-all; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x023c, PIN_INPUT, 0) /* (C21) MMC1_CMD */ + AM62DX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (E22) MMC1_CLK */ + AM62DX_IOPAD(0x0230, PIN_INPUT, 0) /* (B22) MMC1_DAT0 */ + AM62DX_IOPAD(0x022c, PIN_INPUT, 0) /* (D21) MMC1_DAT1 */ + AM62DX_IOPAD(0x0228, PIN_INPUT, 0) /* (C22) MMC1_DAT2 */ + AM62DX_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ + AM62DX_IOPAD(0x0240, PIN_INPUT, 0) /* (E18) MMC1_SDCD */ + >; + bootph-all; + }; + + main_mdio0_pins_default: main-mdio0-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ + AM62DX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ + >; + bootph-all; + }; + + main_rgmii1_pins_default: main-rgmii1-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */ + AM62DX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */ + AM62DX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */ + AM62DX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */ + AM62DX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */ + AM62DX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */ + AM62DX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */ + AM62DX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */ + AM62DX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */ + AM62DX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */ + AM62DX_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AB17) RGMII1_TXC */ + AM62DX_IOPAD(0x012c, PIN_OUTPUT, 0) /* (W16) RGMII1_TX_CTL */ + >; + bootph-all; + }; + + main_rgmii2_pins_default: main-rgmii2-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x0184, PIN_INPUT, 0) /* (AA21) RGMII2_RD0 */ + AM62DX_IOPAD(0x0188, PIN_INPUT, 0) /* (Y20) RGMII2_RD1 */ + AM62DX_IOPAD(0x018c, PIN_INPUT, 0) /* (AB21) RGMII2_RD2 */ + AM62DX_IOPAD(0x0190, PIN_INPUT, 0) /* (AB20) RGMII2_RD3 */ + AM62DX_IOPAD(0x0180, PIN_INPUT, 0) /* (AA20) RGMII2_RXC */ + AM62DX_IOPAD(0x017c, PIN_INPUT, 0) /* (W18) RGMII2_RX_CTL */ + AM62DX_IOPAD(0x016c, PIN_INPUT, 0) /* (AA19) RGMII2_TD0 */ + AM62DX_IOPAD(0x0170, PIN_INPUT, 0) /* (Y18) RGMII2_TD1 */ + AM62DX_IOPAD(0x0174, PIN_INPUT, 0) /* (AA18) RGMII2_TD2 */ + AM62DX_IOPAD(0x0178, PIN_INPUT, 0) /* (W17) RGMII2_TD3 */ + AM62DX_IOPAD(0x0168, PIN_OUTPUT, 0) /* (AB19) RGMII2_TXC */ + AM62DX_IOPAD(0x0164, PIN_OUTPUT, 0) /* (Y19) RGMII2_TX_CTL */ + >; + bootph-all; + }; + + main_mcasp2_pins_default: main-mcasp2-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x0078, PIN_INPUT, 3) /* (T21) GPMC0_AD15.MCASP2_ACLKR */ + AM62DX_IOPAD(0x0070, PIN_INPUT, 3) /* (R21) GPMC0_AD13.MCASP2_ACLKX */ + AM62DX_IOPAD(0x0074, PIN_INPUT, 3) /* (T20) GPMC0_AD14.MCASP2_AFSR */ + AM62DX_IOPAD(0x006c, PIN_INPUT, 3) /* (T22) GPMC0_AD12.MCASP2_AFSX */ + AM62DX_IOPAD(0x005c, PIN_INPUT, 3) /* (P22) GPMC0_AD8.MCASP2_AXR0 */ + AM62DX_IOPAD(0x0060, PIN_INPUT, 3) /* (R19) GPMC0_AD9.MCASP2_AXR1 */ + AM62DX_IOPAD(0x0068, PIN_INPUT, 3) /* (R22) GPMC0_AD11.MCASP2_AXR3 */ + AM62DX_IOPAD(0x003c, PIN_INPUT, 3) /* (N21) GPMC0_AD0.MCASP2_AXR4 */ + AM62DX_IOPAD(0x00a8, PIN_INPUT, 3) /* (M19) GPMC0_CSn0.MCASP2_AXR14 */ + >; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */ + >; + }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (D19) USB1_DRVVBUS */ + >; + }; + + vddshv_sdio_pins_default: vddshv-sdio-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x00f0, PIN_INPUT, 7) /* (Y21) GPIO0_59 */ + >; + bootph-all; + }; + + usr_led_pins_default: usr-led-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x0244, PIN_INPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L22) OSPI0_CLK */ + AM62DX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (H21) OSPI0_CSn0 */ + AM62DX_IOPAD(0x000c, PIN_INPUT, 0) /* (J21) OSPI0_D0 */ + AM62DX_IOPAD(0x0010, PIN_INPUT, 0) /* (J18) OSPI0_D1 */ + AM62DX_IOPAD(0x0014, PIN_INPUT, 0) /* (J19) OSPI0_D2 */ + AM62DX_IOPAD(0x0018, PIN_INPUT, 0) /* (H18) OSPI0_D3 */ + AM62DX_IOPAD(0x001c, PIN_INPUT, 0) /* (K21) OSPI0_D4 */ + AM62DX_IOPAD(0x0020, PIN_INPUT, 0) /* (H19) OSPI0_D5 */ + AM62DX_IOPAD(0x0024, PIN_INPUT, 0) /* (J20) OSPI0_D6 */ + AM62DX_IOPAD(0x0028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62DX_IOPAD(0x0008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */ + >; + bootph-all; + }; +}; + +&mcu_pmx0 { + status = "okay"; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x01f4, PIN_INPUT, 7) /* (F17) EXTINTn.GPIO1_31 */ + >; + }; +}; + +&mcu_gpio0 { + status = "okay"; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + bootph-all; + status = "okay"; + + typec_pd0: usb-power-controller@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + port { + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; + + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + bootph-all; + + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "","MMC1_SD_EN", + "VPP_EN", "GPIO_DIX_RST", + "IO_EXP_OPT_EN", "DIX_INT", + "GPIO_eMMC_RSTn", "CPLD2_DONE", + "CPLD2_INTN", "CPLD1_DONE", + "CPLD1_INTN", "USB_TYPEA_OC_INDICATION", + "PCM1_INT", "PCM2_INT", + "GPIO_PCM1_RST", "TEST_GPIO2", + "GPIO_PCM2_RST", "", + "IO_MCAN0_STB", "IO_MCAN1_STB", + "PD_I2C_IRQ", "IO_EXP_TEST_LED"; + }; + + exp2: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "PCM6240_BUF_IO_EN", "", + "CPLD1_JTAGENB", "CPLD1_PROGRAMN", + "CPLD2_JTAGENB", "CPLD2_PROGRAMN", + "", "", + "", "CPLD1_TCK", + "CPLD1_TMS", "CPLD1_TDI", + "CPLD1_TDO", "CPLD2_TCK", + "CPLD2_TMS", "CPLD2_TDI", + "CPLD2_TDO", "ADDR1_IO_EXP", + "SoC_I2C0_SCL", "SoC_I2C0_SDA"; + }; + + tad5x1x_50: tad5x1x@50 { + compatible = "ti,tad5212"; + reg = <0x50>; + #sound-dai-cells = <0>; + ti,vref = <0>; + ti,micbias-vg = <3>; + sound-name-prefix = "J3A"; + }; + + tad5x1x_51: tad5x1x@51 { + compatible = "ti,tad5212"; + reg = <0x51>; + #sound-dai-cells = <0>; + ti,vref = <0>; + ti,micbias-vg = <3>; + sound-name-prefix = "J3B"; + }; + + tad5x1x_52: tad5x1x@52 { + compatible = "ti,tad5212"; + reg = <0x52>; + #sound-dai-cells = <0>; + ti,vref = <0>; + ti,micbias-vg = <3>; + sound-name-prefix = "J4A"; + }; + + tad5x1x_53: tad5x1x@53 { + compatible = "ti,tad5212"; + reg = <0x53>; + #sound-dai-cells = <0>; + ti,vref = <0>; + ti,micbias-vg = <3>; + sound-name-prefix = "J4B"; + }; + + pcm6240: adc@48 { + compatible = "ti,pcm6240"; + reg = <0x48>, <0x49>; + #sound-dai-cells = <0>; + sound-name-prefix = "pcm6240-2dev-reg"; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; + status = "okay"; +}; + +&mcasp2 { + status = "okay"; + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp2_pins_default>; + + auxclk-fs-ratio = <2177>; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + tdm-slots-rx = <4>; + slot-width = <32>; + ti,async-mode; + serial-dir = < + 1 1 0 1 + 1 0 0 0 + 0 0 0 0 + 0 0 2 0 + >; +}; + +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + tps65224: pmic@48 { + compatible = "ti,tps65224-q1"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&main_gpio1>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + ti,primary-pmic; + + gpio-controller; + #gpio-cells = <2>; + + buck12-supply = <&vcc_3v3_sys>; + buck3-supply = <&vcc_3v3_sys>; + buck4-supply = <&vcc_3v3_sys>; + ldo1-supply = <&vcc_3v3_sys>; + ldo2-supply = <&vcc_3v3_sys>; + ldo3-supply = <&vcc_3v3_sys>; + + regulators { + buck12: buck12 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + buck3: buck3 { + regulator-name = "dvdd1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + buck4: buck4 { + regulator-name = "vdds_ddr"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldo1: ldo1 { + regulator-name = "vdda_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldo2: ldo2 { + regulator-name = "dvdd3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldo3: ldo3 { + regulator-name = "vddr_core"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + }; + }; +}; + +&sdhci0 { + /* eMMC */ + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + disable-wp; + bootph-all; + status = "okay"; +}; + +&sdhci1 { + /* SD/MMC */ + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vddshv_sdio>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + disable-wp; + bootph-all; + status = "okay"; +}; + +&main_gpio0 { + bootph-all; + status = "okay"; +}; + +&main_gpio1 { + bootph-all; + status = "okay"; +}; + +&main_gpio_intr { + status = "okay"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + bootph-all; + status = "okay"; +}; + +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + usb-role-switch; + + port { + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + +&usbss1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + bootph-pre-ram; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + status = "okay"; + + mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + firmware-name = "am62d-mcu-r5f0_0-fw"; +}; + +&c7x_0 { + status = "okay"; + + mboxes = <&mailbox0_cluster1 &mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + firmware-name = "am62d-c71_0-fw"; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>, + <&main_rgmii2_pins_default>; + status = "okay"; + + cpts@3d000 { + /* MAP HW3_TS_PUSH to GENF1 */ + ti,pps = <2 1>; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; + status = "okay"; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; + status = "okay"; +}; + +&cpsw3g_mdio { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio0_pins_default>; + status = "okay"; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; + + cpsw3g_phy1: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +/* main_rti4 is used by C7x DSP */ +&main_rti4 { + status = "reserved"; +}; + +/* main_timer2 is used by C7x DSP */ +&main_timer2 { + status = "reserved"; +}; + +&fss { + status = "okay"; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + status = "okay"; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + cdns,phy-mode; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + bootph-all; + }; + }; + }; +}; + +×ync_router { + /* Use Time Sync Router to map GENF1 input to HW3_TS_PUSH output */ + mux-reg-masks-state = < + /* pps [cpsw cpts genf1] in17 -> out12 [cpsw cpts hw3_push] */ + K3_TS_OFFSET(12, 0x0001ffff, 17) + >; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62.dtsi 2026-04-21 11:35:28.512915189 +0200 @@ -46,6 +46,28 @@ interrupts = ; }; + system-idle-states { + system_partial_io: system-partial-io { + compatible = "system-idle-state"; + idle-state-name = "off-wake"; + }; + + system_deep_sleep: system-deep-sleep { + compatible = "system-idle-state"; + idle-state-name = "mem"; + }; + + system_mcu_only: system-mcu-only { + compatible = "system-idle-state"; + idle-state-name = "mem-mcu-active"; + }; + + system_standby: system-standby { + compatible = "system-idle-state"; + idle-state-name = "standby"; + }; + }; + cbass_main: bus@f0000 { bootph-all; compatible = "simple-bus"; @@ -66,6 +88,7 @@ <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30300000 0x00 0x30300000 0x00 0x00001000>, /* MCRC64 */ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ @@ -86,7 +109,9 @@ /* Wakeup Domain Range */ <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, - <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ cbass_mcu: bus@4000000 { bootph-all; @@ -103,7 +128,9 @@ #size-cells = <2>; ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ - <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-badge-dsi-rpi-7inch-panel.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-badge-dsi-rpi-7inch-panel.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-badge-dsi-rpi-7inch-panel.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-badge-dsi-rpi-7inch-panel.dtso 2026-04-21 11:35:28.522915215 +0200 @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * DT Overlay for RPi 7inch touchscreen panel interfaced with DSI on + * AM62L3 EVM. + * + * RPi DSI Panel: https://www.raspberrypi.com/products/raspberry-pi-touch-display/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + bridge_reg: bridge-regulator { + compatible = "regulator-fixed"; + regulator-name = "bridge-reg"; + gpio = <&display_reg 0 0>; + vin-supply = <&display_reg>; + enable-active-high; + bootph-all; + }; + + panel0 { + compatible = "raspberrypi,7inch-dsi", "simple-panel"; + backlight = <&display_reg>; + power-supply = <&display_reg>; + bootph-all; + port { + panel_in: endpoint { + remote-endpoint = <&panel_bridge_out>; + }; + }; + }; +}; + +&main_i2c1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + display_reg: regulator@45 { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + bootph-all; + }; + + touch-controller@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + + touchscreen-size-x = < 800 >; + touchscreen-size-y = < 480 >; + + vcc-supply = <&display_reg>; + reset-gpio = <&display_reg 1 1>; + + touchscreen-inverted-x; + touchscreen-inverted-y; + bootph-all; + }; +}; + +&dss { + status = "okay"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_out: endpoint { + remote-endpoint = <&panel_bridge_in>; + }; + }; + + port@1 { + reg = <1>; + dsi0_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + bridge@0 { + compatible = "toshiba,tc358762"; + reg = <0>; + vddc-supply = <&bridge_reg>; + bootph-all; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + panel_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-badge.dts v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-badge.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-badge.dts 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-badge.dts 2026-04-21 11:35:28.523915217 +0200 @@ -0,0 +1,775 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L3 Badge + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "k3-am62l3.dtsi" +#include "k3-pinctrl.h" + +/ { + compatible = "ti,am62l3-badge", "ti,am62l3"; + model = "Texas Instruments AM62L3 Badge"; + + chosen { + stdout-path = &main_uart0; + }; + + aliases { + gpio0 = &main_gpio0; + i2c0 = &main_i2c0; + i2c1 = &main_i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + serial3 = &main_uart1; + usb0 = &usb0; + usb1 = &usb1; + }; + + memory@80000000 { + /* 256MB */ + reg = <0x00000000 0x80000000 0x00000000 0x10000000>; + device_type = "memory"; + bootph-all; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&main_usr_button_default_pins>; + + button-select { + label = "SELECT"; + linux,code = ; + gpios = <&main_gpio0 26 GPIO_ACTIVE_LOW>; + }; + + button-back { + label = "BACK"; + linux,code = ; + gpios = <&main_gpio0 104 GPIO_ACTIVE_LOW>; + }; + + button-up { + label = "UP"; + linux,code = ; + gpios = <&main_gpio0 32 GPIO_ACTIVE_LOW>; + }; + + button-down { + label = "DOWN"; + linux,code = ; + gpios = <&main_gpio0 42 GPIO_ACTIVE_LOW>; + }; + + button-left { + label = "LEFT"; + linux,code = ; + gpios = <&main_gpio0 31 GPIO_ACTIVE_LOW>; + }; + + button-right { + label = "RIGHT"; + linux,code = ; + gpios = <&main_gpio0 95 GPIO_ACTIVE_LOW>; + }; + }; + + multicolor-led { + compatible = "pwm-leds-multicolor"; + pinctrl-names = "default"; + pinctrl-0 = <&rgb_led_default_pins>; + + multi-led { + color = ; + max-brightness = <255>; + + led-red { + pwms = <&ecap2 0 255 0>; + color = ; + }; + + led-green { + pwms = <&ecap1 0 255 0>; + color = ; + }; + + led-blue { + pwms = <&epwm1 1 255 0>; + color = ; + }; + }; + }; + + seven-segment-left { + compatible = "gpio-7-segment"; + segment-gpios = <&mcp23s18 0 GPIO_ACTIVE_LOW>, + <&mcp23s18 1 GPIO_ACTIVE_LOW>, + <&mcp23s18 2 GPIO_ACTIVE_LOW>, + <&mcp23s18 3 GPIO_ACTIVE_LOW>, + <&mcp23s18 4 GPIO_ACTIVE_LOW>, + <&mcp23s18 5 GPIO_ACTIVE_LOW>, + <&mcp23s18 6 GPIO_ACTIVE_LOW>, + <&mcp23s18 7 GPIO_ACTIVE_LOW>; + }; + + seven-segment-right { + compatible = "gpio-7-segment"; + segment-gpios = <&mcp23s18 8 GPIO_ACTIVE_LOW>, + <&mcp23s18 9 GPIO_ACTIVE_LOW>, + <&mcp23s18 10 GPIO_ACTIVE_LOW>, + <&mcp23s18 11 GPIO_ACTIVE_LOW>, + <&mcp23s18 12 GPIO_ACTIVE_LOW>, + <&mcp23s18 13 GPIO_ACTIVE_LOW>, + <&mcp23s18 14 GPIO_ACTIVE_LOW>, + <&mcp23s18 15 GPIO_ACTIVE_LOW>; + }; + + pwm-beeper { + compatible = "pwm-beeper"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_beeper_default_pins>; + pwms = <&epwm0 1 1000000 0>; + amp-supply = <&sensor_3v3>; + }; + + vsys_out: regulator-0 { + /* output of BQ24070 */ + compatible = "regulator-fixed"; + regulator-name = "VSYS_OUT"; + regulator-min-microvolt = <4400000>; + regulator-max-microvolt = <4400000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3v3_main: regulator-1 { + /* output of TPS62A06 */ + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_MAIN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_out>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vdd_3v3: regulator-2 { + /* output of TPS22965 */ + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_out>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vdd_3v3_sd: regulator-3 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3>; + regulator-boot-on; + enable-active-high; + gpio = <&main_gpio0 16 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_3v3_sd_ena_default_pins>; + bootph-all; + }; + + sensor_3v3: regulator-4 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "Sensor_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&wkup_gpio0 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sensor_3v3_ena_default_pins>; + bootph-all; + }; + + wlan_en: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpios = <&main_gpio0 51 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_pins_default>; + }; +}; + +&pmx0 { + main_uart0_default_pins: main-uart0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */ + AM62LX_IOPAD(0x01b4, PIN_INPUT, 0) /* (D13) UART0_RXD */ + >; + bootph-all; + }; + + main_uart0_wakeup_pins: main-uart0-wakeup-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */ + AM62LX_IOPAD(0x01b4, PIN_INPUT | PIN_WKUP_EN, 0) /* (D13) UART0_RXD */ + >; + }; + + main_uart1_default_pins: main-uart1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x019c, PIN_OUTPUT, 2) /* (A12) UART1_TXD */ + AM62LX_IOPAD(0x0198, PIN_INPUT, 2) /* (C11) UART1_RXD */ + AM62LX_IOPAD(0x0180, PIN_INPUT, 2) /* (A8) UART1_CTS */ + AM62LX_IOPAD(0x0184, PIN_OUTPUT, 2) /* (B10) UART1_RTS */ + >; + }; + + main_usr_button_default_pins: main-usr-button-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00a4, PIN_INPUT, 7) /* (H18) GPMC0_AD11.GPIO0_26 | SELECT */ + AM62LX_IOPAD(0x01e4, PIN_INPUT, 7) /* (D16) EXT_REFCLK1.GPIO0_104 | BACK*/ + AM62LX_IOPAD(0x00c0, PIN_INPUT, 7) /* (N19) GPMC0_ADVn_ALE.GPIO0_32 | UP */ + AM62LX_IOPAD(0x00e8, PIN_INPUT, 7) /* (L19) GPMC0_CSn1.GPIO0_42 | DOWN */ + AM62LX_IOPAD(0x00b8, PIN_INPUT, 7) /* (L21) GPMC0_CLK.GPIO0_31 | LEFT */ + AM62LX_IOPAD(0x01c0, PIN_INPUT, 7) /* (B13) UART0_RTSn.GPIO0_95 | RIGHT */ + >; + }; + + main_i2c0_default_pins: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01cc, PIN_INPUT_PULLUP, 0) /* (B7) I2C0_SCL */ + AM62LX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 0) /* (A7) I2C0_SDA */ + >; + }; + + main_i2c1_default_pins: main-i2c1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 0) /* (D7) I2C1_SCL */ + AM62LX_IOPAD(0x01d8, PIN_INPUT_PULLUP, 0) /* (A6) I2C1_SDA */ + >; + }; + + vdd_3v3_sd_ena_default_pins: vdd-3v3-sd-ena-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x07c, PIN_OUTPUT, 7) /* (L23) GPMC0_AD1.GPIO0_16 */ + >; + bootph-all; + }; + + sensor_3v3_ena_default_pins: sensor-3v3-ena-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x004, PIN_OUTPUT, 7) /* (AA23) WKUP_UART0_TXD.WKUP_GPIO0_1 */ + >; + }; + + main_mmc0_default_pins: main-mmc0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0214, PIN_INPUT, 0) /* (D2) MMC0_CMD */ + AM62LX_IOPAD(0x020c, PIN_OUTPUT, 0) /* (B2) MMC0_CLK */ + AM62LX_IOPAD(0x0208, PIN_INPUT, 0) /* (D3) MMC0_DAT0 */ + AM62LX_IOPAD(0x0204, PIN_INPUT_PULLUP, 0) /* (D4) MMC0_DAT1 */ + AM62LX_IOPAD(0x0200, PIN_INPUT_PULLUP, 0) /* (C1) MMC0_DAT2 */ + AM62LX_IOPAD(0x01fc, PIN_INPUT_PULLUP, 0) /* (C2) MMC0_DAT3 */ + AM62LX_IOPAD(0x01f8, PIN_INPUT_PULLUP, 0) /* (C4) MMC0_DAT4 */ + AM62LX_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (B3) MMC0_DAT5 */ + AM62LX_IOPAD(0x01f0, PIN_INPUT_PULLUP, 0) /* (A3) MMC0_DAT6 */ + AM62LX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B4) MMC0_DAT7 */ + >; + bootph-all; + }; + + main_mmc1_default_pins: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0230, PIN_INPUT, 0) /* (Y3) MMC1_CMD */ + AM62LX_IOPAD(0x0228, PIN_OUTPUT, 0) /* (Y2) MMC1_CLK */ + AM62LX_IOPAD(0x0224, PIN_INPUT, 0) /* (AA1) MMC1_DAT0 */ + AM62LX_IOPAD(0x0220, PIN_INPUT, 0) /* (Y4) MMC1_DAT1 */ + AM62LX_IOPAD(0x021c, PIN_INPUT, 0) /* (AA2) MMC1_DAT2 */ + AM62LX_IOPAD(0x0218, PIN_INPUT, 0) /* (AB2) MMC1_DAT3 */ + AM62LX_IOPAD(0x0234, PIN_INPUT, 0) /* (B6) MMC1_SDCD */ + >; + bootph-all; + }; + + main_mmc2_pins_default: main-mmc2-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x010c, PIN_INPUT, 0) /* (U23) MMC2_CMD */ + AM62LX_IOPAD(0x0104, PIN_OUTPUT, 0) /* (R23) MMC2_CLK */ + AM62LX_IOPAD(0x0108, PIN_INPUT, 0) /* () MMC2_CLKLB */ + AM62LX_IOPAD(0x0100, PIN_INPUT, 0) /* (U22) MMC2_DAT0 */ + AM62LX_IOPAD(0x00fc, PIN_INPUT, 0) /* (T22) MMC2_DAT1 */ + AM62LX_IOPAD(0x00f8, PIN_INPUT, 0) /* (T23) MMC2_DAT2 */ + AM62LX_IOPAD(0x00f4, PIN_INPUT, 0) /* (R22) MMC2_DAT3 */ + >; + }; + + wlan_en_pins_default: wlan-en-pins-default { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0110, PIN_OUTPUT, 7) /* (T20) MMC2_SDCD.GPIO0_51 */ + >; + }; + + main_wlirq_pins_default: main-wlirq-pins-default { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0114, PIN_INPUT, 7) /* (T21) MMC2_SDWP.GPIO0_52 */ + >; + }; + + main_usb1_default_pins: main-usb1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0248, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (A5) USB1_DRVVBUS */ + >; + }; + + pwm_beeper_default_pins: pwm-beeper-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00b0, PIN_OUTPUT, 4) /* (F22) GPMC0_AD14.EHRPWM0_B */ + >; + }; + + pmic_irq_default_pins: pmic-irq-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01e8, PIN_INPUT, 0) /* (C8) EXTINTn */ + >; + }; + + wkup_i2c0_default_pins: wkup-i2c0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0010, PIN_INPUT_PULLUP, 0) /* (AB22) WKUP_I2C0_SCL */ + AM62LX_IOPAD(0x0014, PIN_INPUT_PULLUP, 0) /* (AA22) WKUP_I2C0_SDA */ + >; + }; + + rgb_led_default_pins: rgb-led-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0190, PIN_OUTPUT, 2) /* (A11) MCASP0_ACLKX.ECAP2_IN_APWM_OUT */ + AM62LX_IOPAD(0x0188, PIN_OUTPUT, 2) /* (A9) MCASP0_AXR1.ECAP1_IN_APWM_OUT */ + AM62LX_IOPAD(0x018c, PIN_OUTPUT, 5) /* (B9) MCASP0_AXR0.EHRPWM1_B */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62LX_IOPAD(0x003c, PIN_OUTPUT, 0) /* (D22) OSPI0_CLK */ + AM62LX_IOPAD(0x0068, PIN_OUTPUT, 0) /* (C20) OSPI0_CSn0 */ + AM62LX_IOPAD(0x0074, PIN_OUTPUT, 0) /* (C23) OSPI0_CSn3 */ + AM62LX_IOPAD(0x0048, PIN_INPUT, 0) /* (C22) OSPI0_D0 */ + AM62LX_IOPAD(0x004c, PIN_INPUT, 0) /* (D21) OSPI0_D1 */ + AM62LX_IOPAD(0x0050, PIN_INPUT, 0) /* (E23) OSPI0_D2 */ + AM62LX_IOPAD(0x0054, PIN_INPUT, 0) /* (D23) OSPI0_D3 */ + AM62LX_IOPAD(0x0058, PIN_INPUT, 0) /* (F21) OSPI0_D4 */ + AM62LX_IOPAD(0x005c, PIN_INPUT, 0) /* (F19) OSPI0_D5 */ + AM62LX_IOPAD(0x0060, PIN_INPUT, 0) /* (G20) OSPI0_D6 */ + AM62LX_IOPAD(0x0064, PIN_INPUT, 0) /* (F20) OSPI0_D7 */ + AM62LX_IOPAD(0x0044, PIN_INPUT, 0) /* (E22) OSPI0_DQS */ + AM62LX_IOPAD(0x0040, PIN_INPUT, 0) /* (E18) OSPI0_LBCLKO */ + >; + }; + + main_spi1_pins_default: main-spi1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x008c, PIN_OUTPUT, 4) /* (H22) GPMC0_AD5.SPI1_CLK */ + AM62LX_IOPAD(0x0088, PIN_OUTPUT, 4) /* (K23) GPMC0_AD4.SPI1_CS0 */ + AM62LX_IOPAD(0x0080, PIN_INPUT, 4) /* (K22) GPMC0_AD2.SPI1_D0 */ + AM62LX_IOPAD(0x0084, PIN_OUTPUT, 4) /* (J23) GPMC0_AD3.SPI1_D1 */ + >; + }; + + main_spi3_pins_default: main-spi3-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00d0, PIN_OUTPUT, 5) /* (P22) GPMC0_BE1n.SPI3_CLK */ + AM62LX_IOPAD(0x00cc, PIN_OUTPUT, 5) /* (P23) GPMC0_BE0n_CLE.SPI3_CS0 */ + AM62LX_IOPAD(0x00d4, PIN_INPUT, 5) /* (N23) GPMC0_WAIT0.SPI3_D0 */ + AM62LX_IOPAD(0x00d8, PIN_OUTPUT, 5) /* (N22) GPMC0_WAIT1.SPI3_D1 */ + >; + }; + + mcp23s18_reset_pins_default: mcp23s18-reset-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00a0, PIN_OUTPUT, 4) /* (H21) GPMC0_AD10.GPIO0_25 */ + >; + }; + + lora_control_pins_default: lora-control-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (M19) GPMC0_WEn.GPIO0_34 | RESET */ + AM62LX_IOPAD(0x00e4, PIN_OUTPUT, 7) /* (L20) GPMC0_CSn0.GPIO0_41 | RF SW */ + AM62LX_IOPAD(0x01a4, PIN_INPUT, 7) /* (D11) SPI0_CS1.GPIO0_88 | BUSY */ + AM62LX_IOPAD(0x01bc, PIN_INPUT, 7) /* (B14) UART0_CTSn.GPIO0_94 | DIO (IRQ) */ + >; + }; +}; + +&main_uart0 { + status = "okay"; + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&main_uart0_default_pins>; + pinctrl-1 = <&main_uart0_wakeup_pins>; + wakeup-source = <&system_deep_sleep>; + bootph-all; +}; + +&main_uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_default_pins>; + bootph-all; + + bluetooth { + compatible = "ti,cc33xx-bt"; + cc33xx-supply = <&wlan_en>; + max-speed = <115200>; + }; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_default_pins>; + clock-frequency = <400000>; + bootph-all; + + /* EEPROM */ + eeprom@50 { + /* FT24C32A-ELRT */ + compatible = "atmel,24c512"; + reg = <0x50>; + }; + + /* Fuel Gauge */ + /* Todo: Add BQ27220 support */ + fuel-gauge@55 { + compatible = "ti,bq27541"; + reg = <0x55>; + }; + + /* IMU Sensor */ + accelerometer@6a { + compatible = "st,lsm6ds3tr-c"; + reg = <0x6a>; + vdd-supply = <&vcc_3v3_main>; + vddio-supply = <&vcc_3v3_main>; + }; + + /* T&H Sensor */ + th-sensor@44 { + compatible = "sensirion,sht4x"; + reg = <0x44>; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_default_pins>; + clock-frequency = <400000>; + bootph-all; +}; + +&wkup_i2c0 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_default_pins>; + status = "okay"; + + tps65214: pmic@30 { + compatible = "ti,tps65214"; + reg = <0x30>; + interrupt-parent = <&gic500>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_default_pins>; + ti,power-button; + + buck1-supply = <&vcc_3v3_main>; + buck2-supply = <&vcc_3v3_main>; + buck3-supply = <&vcc_3v3_main>; + ldo1-supply = <&vcc_3v3_main>; + ldo2-supply = <&vcc_3v3_main>; + + regulators { + buck1_reg: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: buck2 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: buck3 { + regulator-name = "VDD_LPDDR4"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "PMIC_VDD_RTC"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&lora_control_pins_default>; + status = "okay"; + bootph-all; + gpio-line-names ="","","","","","","","","","", //GPIO0_0->9 + "","","","","","","vdd_3v3_sd_ena","","","", //GPIO0_10->19 + "","","","","","mcp23s18_reset","button_select","","","", //GPIO0_20->29 + "","button_left","button_up","","lora_reset","","","","","", //GPIO0_30->39 + "","lora_rfsw","button_down","","","","","","","", //GPIO0_40->49 + "","wlan_ena","","","","","","","","", //GPIO0_50->59 + "","","","","","","","","","", //GPIO0_60->69 + "","","","","","","","","","", //GPIO0_70->79 + "","","","","","","","","lora_busy","", //GPIO0_80->89 + "","","","","lora_dio","button_right","","","","", //GPIO0_90->99 + "","","","","button_back","","","","",""; //GPIO0_100->109 +}; + +&main_gpio2 { + status = "okay"; + bootph-all; +}; + +&wkup_gpio0 { + status = "okay"; + + gpio-line-names ="","sensor_3v3_ena","","","","","",""; //GPIO0_0->7 +}; + +&sdhci0 { + /* eMMC */ + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_default_pins>; + status = "okay"; + bootph-all; +}; + +&sdhci1 { + /* SD/MMC */ + vmmc-supply = <&vdd_3v3_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_default_pins>; + disable-wp; + status = "okay"; + bootph-all; +}; + +&sdhci2 { + vmmc-supply = <&wlan_en>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc2_pins_default>; + bus-width = <4>; + non-removable; + ti,fails-without-test-cd; + cap-power-off-card; + keep-power-in-suspend; + ti,driver-strength-ohm = <50>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,cc3300"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&main_wlirq_pins_default>; + interrupt-parent = <&main_gpio0>; + interrupts = <52 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&tscadc0 { + status = "okay"; + + adc { + ti,adc-channels = <0 /* V20 (Battery) */ + 1 /* V22 (MikroBus) */ + 2 /* V23 (Light Sensor) */ + 3 /* V21 (J28 Header) */ + >; + }; +}; + +&epwm0 { + /* Used for PWM Beeper */ + status = "okay"; +}; + +&epwm1 { + /* Used for RGB LED */ + status = "okay"; +}; + +&ecap1 { + /* Used for RGB LED */ + status = "okay"; +}; + +&ecap2 { + /* Used for RGB LED */ + status = "okay"; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + usb-role-switch; +}; + +&usbss1 { + ti,vbus-divider; + status = "okay"; + bootph-all; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_default_pins>; + bootph-all; +}; + +&ospi0 { + bootph-all; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + ospi0_nor: flash@0 { + bootph-all; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + cdns,phy-mode; + + partitions { + bootph-all; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + /* Limited to 20 MB */ + reg = <0x700000 0x18c0000>; + }; + + partition@3fc0000 { + bootph-all; + label = "ospi.phypattern"; + reg = <0x1fc0000 0x40000>; + }; + }; + }; +}; + +&main_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi1_pins_default>; + status = "okay"; + + mcp23s18: gpio@0 { + compatible = "microchip,mcp23s18"; + pinctrl-names = "default"; + pinctrl-0 = <&mcp23s18_reset_pins_default>; + reg = <0>; + spi-max-frequency = <10000000>; + gpio-controller; + #gpio-cells = <2>; + microchip,spi-present-mask = <0x01>; + reset-gpios = <&main_gpio0 25 GPIO_ACTIVE_LOW>; + }; +}; + +&main_spi3 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi3_pins_default>; + status = "okay"; + + sx1262_lora: lora@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-badge-eink-gdey042t81.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-badge-eink-gdey042t81.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-badge-eink-gdey042t81.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-badge-eink-gdey042t81.dtso 2026-04-21 11:35:28.522915215 +0200 @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * DT Overlay for GoodDisplay GDEY042T81 E-Ink Display on AM62L Badge + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&pmx0 { + + dc_pins_default: dc-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (E12) SPI0_D0.GPIO0_90 */ + >; + }; + + res_pins_default: res-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x009c, PIN_OUTPUT, 7) /* (H20) GPMC0_AD9.GPIO0_24 */ + >; + }; + + busy_pins_default: busy-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00dc, PIN_INPUT, 7) /* (N21) GPMC0_WPn.GPIO0_39 */ + >; + }; + + main_spi0_pins_default: main-spi0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01a8, PIN_OUTPUT, 0) /* (E13) SPI0_CLK */ + AM62LX_IOPAD(0x01a0, PIN_OUTPUT, 0) /* (E11) SPI0_CS0 */ + AM62LX_IOPAD(0x01b0, PIN_OUTPUT, 0) /* (B12) SPI0_D1 */ + >; + }; + +}; + +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi0_pins_default>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + spidev@0 { + compatible = "gooddisplay,gdey042t81"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&dc_pins_default>, + <&res_pins_default>, + <&busy_pins_default>; + spi-max-frequency = <2000000>; + reset-gpios = <&main_gpio0 24 GPIO_ACTIVE_HIGH>; + dc-gpios = <&main_gpio0 90 GPIO_ACTIVE_HIGH>; + busy-gpios = <&main_gpio0 39 GPIO_ACTIVE_HIGH>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62l3.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3.dtsi 2026-04-21 11:35:28.525915223 +0200 @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L3 SoC family (Dual Core A53) + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +/dts-v1/; + +#include "k3-am62l.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&scmi_clk 356>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&scmi_clk 357>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <256>; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&opp_efuse_table>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0003>; + clock-latency-ns = <6000000>; + opp-suspend; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-dsi-rpi-7inch-panel.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-dsi-rpi-7inch-panel.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-dsi-rpi-7inch-panel.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-dsi-rpi-7inch-panel.dtso 2026-04-21 11:35:28.523915217 +0200 @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * DT Overlay for RPi 7inch touchscreen panel interfaced with DSI on + * AM62L3 EVM. + * + * RPi DSI Panel: https://www.raspberrypi.com/products/raspberry-pi-touch-display/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + bridge_reg: bridge-regulator { + compatible = "regulator-fixed"; + regulator-name = "bridge-reg"; + gpio = <&display_reg 0 0>; + vin-supply = <&display_reg>; + enable-active-high; + }; + + panel0 { + compatible = "raspberrypi,7inch-dsi", "simple-panel"; + backlight = <&display_reg>; + power-supply = <&display_reg>; + port { + panel_in: endpoint { + remote-endpoint = <&panel_bridge_out>; + }; + }; + }; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + display_reg: regulator@45 { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + }; + + touch-controller@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + + touchscreen-size-x = < 800 >; + touchscreen-size-y = < 480 >; + + vcc-supply = <&display_reg>; + reset-gpio = <&display_reg 1 1>; + + touchscreen-inverted-x; + touchscreen-inverted-y; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_out: endpoint { + remote-endpoint = <&panel_bridge_in>; + }; + }; + + port@1 { + reg = <1>; + dsi0_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + bridge@0 { + compatible = "toshiba,tc358762"; + reg = <0>; + vddc-supply = <&bridge_reg>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + panel_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +&sii9022 { + status = "disabled"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts 2026-04-21 11:35:28.525915223 +0200 @@ -0,0 +1,990 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L3 Evaluation Module + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "k3-am62l3.dtsi" +#include "k3-pinctrl.h" + +/ { + compatible = "ti,am62l3-evm", "ti,am62l3"; + model = "Texas Instruments AM62L3 Evaluation Module"; + + aliases { + mmc0 = &sdhci0; + mmc1 = &sdhci1; + serial3 = &main_uart1; + }; + + chosen { + stdout-path = &main_uart0; + }; + + memory@80000000 { + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + device_type = "memory"; + bootph-all; + }; + + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&usr_button_pins_default>; + + usr: button-usr { + label = "User Key"; + linux,code = ; + gpios = <&main_gpio0 90 GPIO_ACTIVE_LOW>; + interrupts-extended = <&main_gpio0 90 IRQ_TYPE_EDGE_RISING>, + <&pmx0 0x01ac>; + interrupt-names = "irq", "wakeup"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pins_default>; + + led-0 { + label = "am62-sk:green:heartbeat"; + gpios = <&main_gpio0 123 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "on"; + }; + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + bootph-all; + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: regulator-1 { + /* output of LM61460-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-2 { + /* TPS22918DBVR */ + bootph-all; + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_sys>; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + }; + + vcc_1v8: regulator-3 { + /* output of TPS6282518DMQ */ + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + regulator-boot-on; + }; + + tlv320_mclk: clk-0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12288000>; + }; + + codec_audio: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM62L-SKEVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&tlv320_mclk>; + }; + }; +}; + +&pmx0 { + main_uart0_tx_pins_default: main-uart0-tx-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */ + >; + bootph-all; + }; + + main_uart0_rx_pins_default: main-uart0-rx-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01b4, PIN_INPUT, 0) /* (D13) UART0_RXD */ + >; + bootph-all; + }; + + main_uart0_rx_pins_wakeup: main-uart0-rx-wakeup-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01b4, PIN_INPUT | PIN_WKUP_EN, 0) /* (D13) UART0_RXD */ + >; + }; + + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0180, PIN_INPUT, 2) /* (A8) MCASP0_AXR3.UART1_CTSn */ + AM62LX_IOPAD(0x0184, PIN_OUTPUT, 2) /* (B10) MCASP0_AXR2.UART1_RTSn */ + AM62LX_IOPAD(0x0198, PIN_INPUT, 2) /* (C11) MCASP0_AFSR.UART1_RXD */ + AM62LX_IOPAD(0x019c, PIN_OUTPUT, 2) /* (A12) MCASP0_ACLKR.UART1_TXD */ + >; + bootph-all; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01cc, PIN_INPUT_PULLUP, 0) /* (B7) I2C0_SCL */ + AM62LX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 0) /* (A7) I2C0_SDA */ + >; + bootph-all; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 0) /* (D7) I2C1_SCL */ + AM62LX_IOPAD(0x01d8, PIN_INPUT_PULLUP, 0) /* (A6) I2C1_SDA */ + >; + bootph-all; + }; + + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01dc, PIN_INPUT_PULLUP, 0) /* (B8) I2C2_SCL */ + AM62LX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D8) I2C2_SDA */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62LX_IOPAD(0x003c, PIN_OUTPUT, 0) /* (D22) OSPI0_CLK */ + AM62LX_IOPAD(0x0068, PIN_OUTPUT, 0) /* (C20) OSPI0_CSn0 */ + AM62LX_IOPAD(0x0074, PIN_OUTPUT, 0) /* (C23) OSPI0_CSn3 */ + AM62LX_IOPAD(0x0048, PIN_INPUT, 0) /* (C22) OSPI0_D0 */ + AM62LX_IOPAD(0x004c, PIN_INPUT, 0) /* (D21) OSPI0_D1 */ + AM62LX_IOPAD(0x0050, PIN_INPUT, 0) /* (E23) OSPI0_D2 */ + AM62LX_IOPAD(0x0054, PIN_INPUT, 0) /* (D23) OSPI0_D3 */ + AM62LX_IOPAD(0x0058, PIN_INPUT, 0) /* (F21) OSPI0_D4 */ + AM62LX_IOPAD(0x005c, PIN_INPUT, 0) /* (F19) OSPI0_D5 */ + AM62LX_IOPAD(0x0060, PIN_INPUT, 0) /* (G20) OSPI0_D6 */ + AM62LX_IOPAD(0x0064, PIN_INPUT, 0) /* (F20) OSPI0_D7 */ + AM62LX_IOPAD(0x0044, PIN_INPUT, 0) /* (E22) OSPI0_DQS */ + AM62LX_IOPAD(0x0040, PIN_INPUT, 0) /* (E18) OSPI0_LBCLKO */ + >; + }; + + main_gpio0_ioexp_intr_pins_default: main-gpio0-ioexp-intr-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01b0, PIN_INPUT, 7) /* (B12) SPI0_D1.GPIO0_91 */ + >; + bootph-all; + }; + + usr_led_pins_default: usr-led-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0238, PIN_OUTPUT, 7) /* (D24) MMC1_SDWP.GPIO0_123 */ + >; + }; + + usr_button_pins_default: usr-button-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01ac, PIN_INPUT, 7) /* (E12) SPI0_D0.GPIO0_90 */ + >; + }; + + main_mmc0_pins_default: main-mmc0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0214, PIN_INPUT, 0) /* (D2) MMC0_CMD */ + AM62LX_IOPAD(0x020c, PIN_OUTPUT, 0) /* (B2) MMC0_CLK */ + AM62LX_IOPAD(0x0208, PIN_INPUT, 0) /* (D3) MMC0_DAT0 */ + AM62LX_IOPAD(0x0204, PIN_INPUT_PULLUP, 0) /* (D4) MMC0_DAT1 */ + AM62LX_IOPAD(0x0200, PIN_INPUT_PULLUP, 0) /* (C1) MMC0_DAT2 */ + AM62LX_IOPAD(0x01fc, PIN_INPUT_PULLUP, 0) /* (C2) MMC0_DAT3 */ + AM62LX_IOPAD(0x01f8, PIN_INPUT_PULLUP, 0) /* (C4) MMC0_DAT4 */ + AM62LX_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (B3) MMC0_DAT5 */ + AM62LX_IOPAD(0x01f0, PIN_INPUT_PULLUP, 0) /* (A3) MMC0_DAT6 */ + AM62LX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B4) MMC0_DAT7 */ + >; + bootph-all; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0230, PIN_INPUT, 0) /* (Y3) MMC1_CMD */ + AM62LX_IOPAD(0x0228, PIN_OUTPUT, 0) /* (Y2) MMC1_CLK */ + AM62LX_IOPAD(0x0224, PIN_INPUT, 0) /* (AA1) MMC1_DAT0 */ + AM62LX_IOPAD(0x0220, PIN_INPUT, 0) /* (Y4) MMC1_DAT1 */ + AM62LX_IOPAD(0x021c, PIN_INPUT, 0) /* (AA2) MMC1_DAT2 */ + AM62LX_IOPAD(0x0218, PIN_INPUT, 0) /* (AB2) MMC1_DAT3 */ + AM62LX_IOPAD(0x0234, PIN_INPUT, 0) /* (B6) MMC1_SDCD */ + >; + bootph-all; + }; + + main_dpi_pins_default: main-dpi-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00e4, PIN_OUTPUT, 1) /* (L20) GPMC0_CSn0.VOUT0_VSYNC */ + AM62LX_IOPAD(0x00dc, PIN_OUTPUT, 1) /* (N21) GPMC0_WPn.VOUT0_HSYNC */ + AM62LX_IOPAD(0x00e8, PIN_OUTPUT, 1) /* (L19) GPMC0_CSn1.VOUT0_PCLK */ + AM62LX_IOPAD(0x00e0, PIN_OUTPUT, 1) /* (M21) GPMC0_DIR.VOUT0_DE */ + AM62LX_IOPAD(0x0078, PIN_OUTPUT, 1) /* (L22) GPMC0_AD0.VOUT0_DATA0 */ + AM62LX_IOPAD(0x007c, PIN_OUTPUT, 1) /* (L23) GPMC0_AD1.VOUT0_DATA1 */ + AM62LX_IOPAD(0x0080, PIN_OUTPUT, 1) /* (K22) GPMC0_AD2.VOUT0_DATA2 */ + AM62LX_IOPAD(0x0084, PIN_OUTPUT, 1) /* (J23) GPMC0_AD3.VOUT0_DATA3 */ + AM62LX_IOPAD(0x0088, PIN_OUTPUT, 1) /* (K23) GPMC0_AD4.VOUT0_DATA4 */ + AM62LX_IOPAD(0x008c, PIN_OUTPUT, 1) /* (H22) GPMC0_AD5.VOUT0_DATA5 */ + AM62LX_IOPAD(0x0090, PIN_OUTPUT, 1) /* (H23) GPMC0_AD6.VOUT0_DATA6 */ + AM62LX_IOPAD(0x0094, PIN_OUTPUT, 1) /* (J22) GPMC0_AD7.VOUT0_DATA7 */ + AM62LX_IOPAD(0x0098, PIN_OUTPUT, 1) /* (H19) GPMC0_AD8.VOUT0_DATA8 */ + AM62LX_IOPAD(0x009c, PIN_OUTPUT, 1) /* (H20) GPMC0_AD9.VOUT0_DATA9 */ + AM62LX_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (H21) GPMC0_AD10.VOUT0_DATA10 */ + AM62LX_IOPAD(0x00a4, PIN_OUTPUT, 1) /* (H18) GPMC0_AD11.VOUT0_DATA11 */ + AM62LX_IOPAD(0x00a8, PIN_OUTPUT, 1) /* (G23) GPMC0_AD12.VOUT0_DATA12 */ + AM62LX_IOPAD(0x00ac, PIN_OUTPUT, 1) /* (G22) GPMC0_AD13.VOUT0_DATA13 */ + AM62LX_IOPAD(0x00b0, PIN_OUTPUT, 1) /* (F22) GPMC0_AD14.VOUT0_DATA14 */ + AM62LX_IOPAD(0x00b4, PIN_OUTPUT, 1) /* (F23) GPMC0_AD15.VOUT0_DATA15 */ + AM62LX_IOPAD(0x00b8, PIN_OUTPUT, 1) /* (L21) GPMC0_CLK.VOUT0_DATA16 */ + AM62LX_IOPAD(0x00c0, PIN_OUTPUT, 1) /* (N19) GPMC0_ADVn_ALE.VOUT0_DATA17 */ + AM62LX_IOPAD(0x00c4, PIN_OUTPUT, 1) /* (N20) GPMC0_OEn_REn.VOUT0_DATA18 */ + AM62LX_IOPAD(0x00c8, PIN_OUTPUT, 1) /* (M19) GPMC0_WEn.VOUT0_DATA19 */ + AM62LX_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (P23) GPMC0_BE0n_CLE.VOUT0_DATA20 */ + AM62LX_IOPAD(0x00d0, PIN_OUTPUT, 1) /* (P22) GPMC0_BE1n.VOUT0_DATA21 */ + AM62LX_IOPAD(0x00d4, PIN_OUTPUT, 1) /* (N23) GPMC0_WAIT0.VOUT0_DATA22 */ + AM62LX_IOPAD(0x00d8, PIN_OUTPUT, 1) /* (N22) GPMC0_WAIT1.VOUT0_DATA23 */ + AM62LX_IOPAD(0x00ec, PIN_OUTPUT, 5) /* (M23) GPMC0_CSn2.VOUT0_EXTPCLKIN */ + >; + bootph-all; + }; + + gpmc0_pins_default: gpmc0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0078, PIN_INPUT, 0) /* (L22) GPMC0_AD0 */ + AM62LX_IOPAD(0x007c, PIN_INPUT, 0) /* (L23) GPMC0_AD1 */ + AM62LX_IOPAD(0x0080, PIN_INPUT, 0) /* (K22) GPMC0_AD2 */ + AM62LX_IOPAD(0x0084, PIN_INPUT, 0) /* (J23) GPMC0_AD3 */ + AM62LX_IOPAD(0x0088, PIN_INPUT, 0) /* (K23) GPMC0_AD4 */ + AM62LX_IOPAD(0x008c, PIN_INPUT, 0) /* (H22) GPMC0_AD5 */ + AM62LX_IOPAD(0x0090, PIN_INPUT, 0) /* (H23) GPMC0_AD6 */ + AM62LX_IOPAD(0x0094, PIN_INPUT, 0) /* (J22) GPMC0_AD7 */ + AM62LX_IOPAD(0x00d4, PIN_INPUT, 0) /* (N23) GPMC0_WAIT0 */ + AM62LX_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (L20) GPMC0_CSn0 */ + AM62LX_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (N19) GPMC0_ADVn_ALE */ + AM62LX_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (N20) GPMC0_OEn_REn */ + AM62LX_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (M19) GPMC0_WEn */ + AM62LX_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (P23) GPMC0_BE0n_CLE */ + AM62LX_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (N21) GPMC0_WPn */ + >; + }; + + rgmii1_pins_default: rgmii1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0138, PIN_INPUT, 0) /* (Y8) RGMII1_RD0 */ + AM62LX_IOPAD(0x013c, PIN_INPUT, 0) /* (AA6) RGMII1_RD1 */ + AM62LX_IOPAD(0x0140, PIN_INPUT, 0) /* (AA8) RGMII1_RD2 */ + AM62LX_IOPAD(0x0144, PIN_INPUT, 0) /* (W8) RGMII1_RD3 */ + AM62LX_IOPAD(0x0134, PIN_INPUT, 0) /* (Y7) RGMII1_RXC */ + AM62LX_IOPAD(0x0130, PIN_INPUT, 0) /* (Y6) RGMII1_RX_CTL */ + AM62LX_IOPAD(0x0120, PIN_OUTPUT, 0) /* (AC10) RGMII1_TD0 */ + AM62LX_IOPAD(0x0124, PIN_OUTPUT, 0) /* (W13) RGMII1_TD1 */ + AM62LX_IOPAD(0x0128, PIN_OUTPUT, 0) /* (Y11) RGMII1_TD2 */ + AM62LX_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AA11) RGMII1_TD3 */ + AM62LX_IOPAD(0x011c, PIN_OUTPUT, 0) /* (W11) RGMII1_TXC */ + AM62LX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (AB11) RGMII1_TX_CTL */ + >; + }; + + rgmii2_pins_default: rgmii2-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0170, PIN_INPUT, 0) /* (AB9) RGMII2_RD0 */ + AM62LX_IOPAD(0x0174, PIN_INPUT, 0) /* (AC9) RGMII2_RD1 */ + AM62LX_IOPAD(0x0178, PIN_INPUT, 0) /* (AB10) RGMII2_RD2 */ + AM62LX_IOPAD(0x017c, PIN_INPUT, 0) /* (AB8) RGMII2_RD3 */ + AM62LX_IOPAD(0x016c, PIN_INPUT, 0) /* (AC7) RGMII2_RXC */ + AM62LX_IOPAD(0x0168, PIN_INPUT, 0) /* (AC8) RGMII2_RX_CTL */ + AM62LX_IOPAD(0x0158, PIN_OUTPUT, 0) /* (AC12) RGMII2_TD0 */ + AM62LX_IOPAD(0x015c, PIN_OUTPUT, 0) /* (AB13) RGMII2_TD1 */ + AM62LX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AA12) RGMII2_TD2 */ + AM62LX_IOPAD(0x0164, PIN_OUTPUT, 0) /* (AA13) RGMII2_TD3 */ + AM62LX_IOPAD(0x0154, PIN_OUTPUT, 0) /* (Y13) RGMII2_TXC */ + AM62LX_IOPAD(0x0150, PIN_OUTPUT, 0) /* (AB12) RGMII2_TX_CTL */ + >; + }; + + mdio1_pins_default: mdio1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x014c, PIN_OUTPUT, 0) /* (AC15) MDIO0_MDC */ + AM62LX_IOPAD(0x0148, PIN_INPUT, 0) /* (AC13) MDIO0_MDIO */ + >; + }; + + main_usb1_default_pins: main-usb1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0248, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (A5) USB1_DRVVBUS */ + >; + }; + + main_mcasp0_pins_default: main-mcasp0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0190, PIN_INPUT, 0) /* (A11) MCASP0_ACLKX */ + AM62LX_IOPAD(0x0194, PIN_INPUT, 0) /* (B11) MCASP0_AFSX */ + AM62LX_IOPAD(0x018c, PIN_INPUT, 0) /* (B9) MCASP0_AXR0 */ + AM62LX_IOPAD(0x0188, PIN_INPUT, 0) /* (A9) MCASP0_AXR1 */ + >; + }; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01e8, PIN_INPUT, 0) /* (C8) EXTINTn */ + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0010, PIN_INPUT_PULLUP, 0) /* (AB22) WKUP_I2C0_SCL */ + AM62LX_IOPAD(0x0014, PIN_INPUT_PULLUP, 0) /* (AA22) WKUP_I2C0_SDA */ + >; + }; +}; + +&main_uart0 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&main_uart0_tx_pins_default>, <&main_uart0_rx_pins_default>; + pinctrl-1 = <&main_uart0_tx_pins_default>, <&main_uart0_rx_pins_wakeup>; + wakeup-source = <&system_deep_sleep>; + status = "okay"; + bootph-all; +}; + +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + status = "okay"; + bootph-all; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + bootph-all; + + eeprom@51 { + /* AT24C512C-MAHM-T or M24512-DFMC6TG */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; + +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <100000>; + bootph-all; + + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "", "", + "UART1_FET_SEL", "MMC1_SD_EN", + "VPP_EN", "EXP_PS_3V3_EN", + "UART1_FET_BUF_EN", "", + "DSI_GPIO0", "DSI_GPIO1", + "", "BT_UART_WAKE_SOC_3V3", + "USB_TYPEA_OC_INDICATION", "", + "", "WLAN_ALERTn", + "HDMI_INTn", "TEST_GPIO2", + "MCASP0_FET_EN", "MCASP0_BUF_BT_EN", + "MCASP0_FET_SEL", "DSI_EDID", + "PD_I2C_IRQ", "IO_EXP_TEST_LED"; + + interrupt-parent = <&main_gpio0>; + interrupts = <91 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio0_ioexp_intr_pins_default>; + bootph-all; + + uart1_fet_buf_en { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "UART1_FET_BUF_EN"; + }; + }; + + exp2: gpio@23 { + compatible = "ti,tca6424"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "BT_EN_SOC", "VOUT0_FET_SEL0", + "", "", + "", "", + "", "", + "WL_LT_EN", "EXP_PS_5V0_EN", + "TP45", "TP48", + "TP46", "TP49", + "TP47", "TP50", + "GPIO_QSPI_NAND_RSTn", "GPIO_HDMI_RSTn", + "GPIO_CPSW1_RST", "GPIO_CPSW2_RST", + "", "GPIO_AUD_RSTn", + "GPIO_eMMC_RSTn", "SoC_WLAN_SDIO_RST"; + bootph-all; + }; + + sii9022: bridge-hdmi@3b { + compatible = "sil,sii9022"; + reg = <0x3b>; + interrupt-parent = <&exp1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = < 0 >; + pinctrl-names = "default"; + pinctrl-0 = <&main_dpi_pins_default>; + bootph-all; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + tlv320aic3106: audio-codec@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + ai3x-micbias-vg = <1>; /* 2.0V */ + + /* Regulators */ + AVDD-supply = <&vcc_3v3_sys>; + IOVDD-supply = <&vcc_3v3_sys>; + DRVDD-supply = <&vcc_3v3_sys>; + DVDD-supply = <&vcc_1v8>; + }; +}; + +&main_i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; + + typec_pd0: tps6598x@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + port { + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; +}; + +&wkup_i2c0 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + status = "okay"; + + tps65214: pmic@30 { + compatible = "ti,tps65214"; + reg = <0x30>; + interrupt-parent = <&gic500>; + interrupts = ; + pinctrl-0 = <&pmic_irq_pins_default>; + ti,power-button; + + buck1-supply = <&vmain_pd>; + buck2-supply = <&vmain_pd>; + buck3-supply = <&vmain_pd>; + ldo1-supply = <&vmain_pd>; + ldo2-supply = <&vmain_pd>; + + regulators { + buck1_reg: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: buck2 { + regulator-name = "DVDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: buck3 { + regulator-name = "VDD_LPDDR4"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "VDDA_V75"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&main_gpio0 { + status = "okay"; + bootph-all; +}; + +&main_gpio2 { + status = "okay"; + bootph-all; +}; + +&sdhci0 { + /* eMMC */ + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + status = "okay"; + bootph-all; +}; + +&sdhci1 { + /* SD/MMC */ + vmmc-supply = <&vdd_mmc1>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + status = "okay"; + bootph-all; + disable-wp; +}; + +&ospi0 { + bootph-all; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + ospi0_nor: flash@0 { + bootph-all; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + cdns,phy-mode; + + partitions { + bootph-all; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-all; + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; + + ospi0_nand: flash@3 { + bootph-all; + compatible = "spi-nand"; + reg = <0x3>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + cdns,phy-mode; + + partitions { + bootph-all; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi_nand.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi_nand.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi_nand.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi_nand.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi_nand.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@2000000 { + label = "ospi_nand.rootfs"; + reg = <0x2000000 0x5fe0000>; + }; + + partition@7fe0000 { + bootph-all; + label = "ospi_nand.phypattern"; + reg = <0x7fe0000 0x20000>; + }; + }; + }; +}; + +&dss { + status = "okay"; + bootph-all; +}; + +&dss_ports { + /* VP1: DPI Output */ + port@0 { + reg = <0>; + + dpi_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; + +&tscadc0 { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3>; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins_default>, + <&rgmii2_pins_default>; + status = "okay"; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default>; + status = "okay"; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&elm0 { + /* + * status = "okay"; + * disable dss when enabling this + */ +}; + +&gpmc0 { + /* + * status = "okay"; + * disable dss when enabling this + */ + pinctrl-names = "default"; + pinctrl-0 = <&gpmc0_pins_default>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */ + + nand@0,0 { + compatible = "ti,am64-nand"; + reg = <0 0 64>; /* device IO registers */ + interrupt-parent = <&gpmc0>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-xfer-type = "prefetch-polled"; + ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */ + ti,elm-id = <&elm0>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <25>; + gpmc,adv-wr-off-ns = <25>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <3>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "NAND.tiboot3"; + reg = <0x00000000 0x00080000>; /* 512KB */ + }; + partition@80000 { + label = "NAND.tispl"; + reg = <0x80000 0x180000>; /* 1.5M */ + }; + partition@200000 { + label = "NAND.u-boot"; + reg = <0x00200000 0x00200000>; /* 2M */ + }; + partition@400000 { + label = "NAND.tiboot3.backup"; /* 512KB */ + reg = <0x00400000 0x00080000>; /* BootROM looks at 4M */ + }; + partition@480000 { + label = "NAND.tispl.bin.backup"; + reg = <0x00480000 0x180000>; /* 1.5M */ + }; + partition@600000 { + label = "NAND.u-boot.backup"; + reg = <0x00600000 0x00200000>; /* 2M */ + }; + partition@800000 { + label = "NAND.u-boot-env"; + reg = <0x00800000 0x00040000>; /* 256K */ + }; + partition@840000 { + label = "NAND.u-boot-env.backup"; + reg = <0x00840000 0x00040000>; /* 256K */ + }; + partition@880000 { + label = "NAND.file-system"; + reg = <0x00880000 0x1f780000>; + }; + }; + }; +}; + +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + usb-role-switch; + + port { + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + +&usbss1 { + status = "okay"; + ti,vbus-divider; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_default_pins>; +}; + +&mcasp0 { + status = "okay"; + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp0_pins_default>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; +}; + +&wkup_uart0_interconnect { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-ecap-capture.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-ecap-capture.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-ecap-capture.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-ecap-capture.dtso 2026-04-21 11:35:28.523915217 +0200 @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for enabling ECAP in capture mode on AM62L3-EVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&pmx0 { + main_ecap2_capture_pins_default: main-ecap2-capture-pins-default { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0184, PIN_INPUT, 4) /* (B10) MCASP0_AXR2.ECAP2_IN_APWM_OUT */ + >; + }; +}; + +&main_uart1 { + status = "disabled"; +}; + +&main_i2c1 { + gpio@22 { + fet_sel { + /* P02 - UART1_FET_SEL */ + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "UART1_FET_SEL"; + }; + }; +}; + +&ecap2 { + /* ECAP in capture mode */ + /* P2 of J6 */ + compatible = "ti,am62-ecap-capture"; + interrupt-parent = <&gic500>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap2_capture_pins_default>; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-eink-gdey042t81.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-eink-gdey042t81.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-eink-gdey042t81.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-eink-gdey042t81.dtso 2026-04-21 11:35:28.523915217 +0200 @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * DT Overlay for GoodDisplay GDEY042T81 E-Ink Display on AM62L3 EVM + * + * Pin mapping (matching k3-am62l3-evm-epaper.dtso): + * P5 --> BUSY + * P25 --> GND + * P26 --> RST + * P27 --> SPI CLK + * P28 --> DC + * P29 --> SPI DAT (MOSI) + * P30 --> SPI CS + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&pmx0 { + dc_pins_default: dc-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0080, PIN_OUTPUT, 7) /* (K22) GPMC0_AD2.GPIO0_17 */ + >; + }; + + res_pins_default: res-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x007c, PIN_OUTPUT, 7) /* (L23) GPMC0_AD1.GPIO0_16 */ + >; + }; + + busy_pins_default: busy-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00b8, PIN_INPUT, 7) /* (L21) GPMC0_AD0.GPIO0_31 */ + >; + }; + + main_spi1_pins_default: main-spi1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x008c, PIN_OUTPUT, 4) /* (H22) GPMC0_AD5.SPI1_CLK */ + AM62LX_IOPAD(0x0088, PIN_OUTPUT, 4) /* (K23) GPMC0_AD4.SPI1_CS0 */ + AM62LX_IOPAD(0x0084, PIN_OUTPUT, 4) /* (J23) GPMC0_AD3.SPI1_D1 */ + >; + }; + + fet_sel_pins_default: fet-sel-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01a8, PIN_OUTPUT, 7) /* (E13) SPI0_CLK.GPIO0_89 */ + >; + }; +}; + +&main_gpio0 { + fet-sel-hog { + /* VOUT0 FET switch selection */ + gpio-hog; + gpios = <89 0>; + output-high; + line-name = "GPIO_EXP_CONN_FET_SEL"; + }; +}; + +&gpmc0 { + status = "disabled"; +}; + +&main_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi1_pins_default>, <&fet_sel_pins_default>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + spidev@0 { + compatible = "gooddisplay,gdey042t81"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&dc_pins_default>, + <&res_pins_default>, + <&busy_pins_default>; + spi-max-frequency = <2000000>; + reset-gpios = <&main_gpio0 16 GPIO_ACTIVE_HIGH>; + dc-gpios = <&main_gpio0 17 GPIO_ACTIVE_HIGH>; + busy-gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-epaper.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-epaper.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-epaper.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-epaper.dtso 2026-04-21 11:35:28.523915217 +0200 @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * DT Overlay for E-Paper screen over SPI1 on AM62L3 EVM. + * + * P24 --> BUSY + * P25 --> GND + * P26 --> RST + * P27 --> SPI CLK + * P28 --> DC + * P29 --> SPI DAT + * P30 --> SPI CS + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&pmx0 { + dc_pins_default: dc-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0080, PIN_OUTPUT, 7) /* (K22) GPMC0_AD2.GPIO0_17 */ + >; + }; + + res_pins_default: res-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x007c, PIN_OUTPUT, 7) /* (L23) GPMC0_AD1.GPIO0_16 */ + >; + }; + + busy_pins_default: busy-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0078, PIN_INPUT, 7) /* (L22) GPMC0_AD0.GPIO0_15 */ + >; + }; + + main_spi1_pins_default: main-spi1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x008c, PIN_OUTPUT, 4) /* (H22) GPMC0_AD5.SPI1_CLK */ + AM62LX_IOPAD(0x0088, PIN_OUTPUT, 4) /* (K23) GPMC0_AD4.SPI1_CS0 */ + AM62LX_IOPAD(0x0084, PIN_OUTPUT, 4) /* (J23) GPMC0_AD3.SPI1_D1 */ + >; + }; + + fet_sel_pins_default: fet-sel-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01a8, PIN_OUTPUT, 7) /* (E13) SPI0_CLK.GPIO0_89 */ + >; + }; +}; + +&main_gpio0 { + fet-sel-hog { + /* VOUT0 FET switch selection */ + gpio-hog; + gpios = <89 0>; + output-high; + line-name = "GPIO_EXP_CONN_FET_SEL"; + }; +}; + +&dss { + status = "disabled"; +}; + +&gpmc0 { + status = "disabled"; +}; + +&main_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi1_pins_default>, <&fet_sel_pins_default>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&dc_pins_default>, + <&res_pins_default>, + <&busy_pins_default>; + spi-max-frequency = <1000000>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-eqep.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-eqep.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-eqep.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-eqep.dtso 2026-04-21 11:35:28.523915217 +0200 @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for enabling EQEP on AM62L3 EVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&pmx0 { + main_eqep0_pins_default: main-eqep0-pins-default { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00cc, PIN_INPUT, 4) /* (P23) GPMC0_BE0n_CLE.EQEP0_A */ + AM62LX_IOPAD(0x00d0, PIN_INPUT, 4) /* (P22) GPMC0_BE1n.EQEP0_B */ + AM62LX_IOPAD(0x00d8, PIN_INPUT, 4) /* (N22) GPMC0_WAIT1.EQEP0_I */ + AM62LX_IOPAD(0x00d4, PIN_INPUT, 4) /* (N23) GPMC0_WAIT0.EQEP0_S */ + >; + }; + + main_eqep1_pins_default: main-eqep1-pins-default { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00dc, PIN_INPUT, 4) /* (N21) GPMC0_WPn.EQEP1_A */ + AM62LX_IOPAD(0x00e0, PIN_INPUT, 4) /* (M21) GPMC0_DIR.EQEP1_B */ + AM62LX_IOPAD(0x00e4, PIN_INPUT, 4) /* (L20) GPMC0_CSn0.EQEP1_S */ + >; + }; +}; + +&dss { + status = "disabled"; +}; + +&main_i2c1 { + gpio@23 { + fet_sel { + /* P01 - VOUT0_FET_SEL0 */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "VOUT0_FET_SEL0"; + }; + }; +}; + +&eqep0 { + status = "okay"; + /* A/B on pins 19/14 of J2 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_eqep0_pins_default>; +}; + +&eqep1 { + status = "okay"; + /* A/B on pins 9/7 of J2 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_eqep1_pins_default>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-lpmdemo.dts v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-lpmdemo.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-lpmdemo.dts 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-lpmdemo.dts 2026-04-21 11:35:28.524915220 +0200 @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Low Power Mode Demo Device Tree file for the AM62L3 Starter Kit + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am62l3-evm.dts" + +/ { + idle-states { + entry-method = "psci"; + + CLST_STBY: STBY { + compatible = "arm,idle-state"; + idle-state-name = "Standby"; + arm,psci-suspend-param = <0x00000001>; + entry-latency-us = <300>; + exit-latency-us = <600>; + min-residency-us = <1000>; + }; + }; + + domain-idle-states { + main_sleep_0: main-deep-sleep { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x2012231>; + entry-latency-us = <1000>; + exit-latency-us = <1000>; + min-residency-us = <500000>; + local-timer-stop; + }; + + main_sleep_1: main-sleep-rtcddr { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x2012232>; + local-timer-stop; + entry-latency-us = <300000>; + exit-latency-us = <600000>; + min-residency-us = <1000000>; + }; + }; + +}; + +&scmi_pds { + /* + * Here's how we group the scmi pd ID of devices into their + * top level power domains, which happens to be the MAIN domain + * in this case. + */ + power-domain-map = <15 &MAIN_PD>, /* TIMER0 */ + <16 &MAIN_PD>, /* TIMER1 */ + <17 &MAIN_PD>, /* TIMER2 */ + <18 &MAIN_PD>; /* TIMER3 */ +}; + +&cpu0 { + power-domains = <&CLUSTER_PD>; + power-domain-names = "psci"; +}; + +&psci { + CLUSTER_PD: power-controller-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLST_STBY>; + power-domains = <&MAIN_PD>; + }; + + MAIN_PD: power-controller-main { + #power-domain-cells = <0>; + domain-idle-states = <&main_sleep_0>, <&main_sleep_1>; + }; +}; + +/delete-node/ &cpu1; + +&cluster0 { + /delete-node/ core1; +}; + +/delete-node/ &main_rti1; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-lpm-wkup-sources.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-lpm-wkup-sources.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-lpm-wkup-sources.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-lpm-wkup-sources.dtso 2026-04-21 11:35:28.523915217 +0200 @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * AM62L3 evm can wakeup from Low Power Modes via + * multiple wakeup sources. This overlay enables WKUP GPIO. + * + * Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + wkup_gpio_key { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&wake_wkupgpio0_pins_default>; + interrupt-parent = <&wkup_gpio0>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + switch { + label = "WKUPGPIO"; + linux,code = <143>; + gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; +}; + +&pmx0 { + wake_wkupgpio0_pins_default: wake-wkupgpio0-pins-default { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0000, PIN_INPUT_PULLUP, 7) /* (Y22) WKUP_UART0_RXD.WKUP_GPIO0_0 */ + >; + }; +}; + +&wkup_gpio0 { + status = "okay"; +}; + +&wkup_uart0_interconnect { + status = "disabled"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-m2-cc3351.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-m2-cc3351.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-m2-cc3351.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-m2-cc3351.dtso 2026-04-21 11:35:28.524915220 +0200 @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * DT Overlay for M.2-CC3351 board to connect to the M.2 connector on AM62L-EVM. + * + * Product page for board: https://www.ti.com/tool/M2-CC3351 + * CC3351 Datasheet: https://www.ti.com/lit/ds/symlink/cc3351.pdf + * + * Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&{/} { + wlan_lten: regulator-30 { + compatible = "regulator-fixed"; + regulator-name = "wlan_lten"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&exp2 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wlan_en: regulator-31 { + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&wlan_lten>; + enable-active-high; + gpios = <&main_gpio0 51 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_pins_default>; + }; +}; + +&pmx0 { + main_mmc2_pins_default: main-mmc2-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x010c, PIN_INPUT, 0) /* (U23) MMC2_CMD */ + AM62LX_IOPAD(0x0104, PIN_OUTPUT, 0) /* (R23) MMC2_CLK */ + AM62LX_IOPAD(0x0108, PIN_INPUT, 0) /* () MMC2_CLKLB */ + AM62LX_IOPAD(0x0100, PIN_INPUT, 0) /* (U22) MMC2_DAT0 */ + AM62LX_IOPAD(0x00fc, PIN_INPUT, 0) /* (T22) MMC2_DAT1 */ + AM62LX_IOPAD(0x00f8, PIN_INPUT, 0) /* (T23) MMC2_DAT2 */ + AM62LX_IOPAD(0x00f4, PIN_INPUT, 0) /* (R22) MMC2_DAT3 */ + >; + }; + + wlan_en_pins_default: wlan-en-pins-default { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0110, PIN_OUTPUT, 7) /* (T20) MMC2_SDCD.GPIO0_51 */ + >; + }; + + main_wlirq_pins_default: main-wlirq-pins-default { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0114, PIN_INPUT, 7) /* (T21) MMC2_SDWP.GPIO0_52 */ + >; + }; +}; + +&sdhci2 { + bootph-all; + vmmc-supply = <&wlan_en>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc2_pins_default>; + bus-width = <4>; + non-removable; + ti,fails-without-test-cd; + cap-power-off-card; + keep-power-in-suspend; + ti,driver-strength-ohm = <50>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,cc3300"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&main_wlirq_pins_default>; + interrupt-parent = <&main_gpio0>; + interrupts = <52 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&main_uart1 { + status = "okay"; + + bluetooth { + compatible = "ti,cc33xx-bt"; + cc33xx-supply = <&wlan_en>; + max-speed = <115200>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-mcan.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-mcan.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-mcan.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-mcan.dtso 2026-04-21 11:35:28.524915220 +0200 @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * DT Overlay for enabling MCAN for AM62L-EVM. + * + * Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&pmx0 { + main_mcan0_pins_default: main-mcan0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01c8, PIN_INPUT, 0) /* (B15) MCAN0_RX */ + AM62LX_IOPAD(0x01c4, PIN_OUTPUT, 0) /* (B16) MCAN0_TX */ + >; + }; + + main_mcan1_pins_default: main-mcan1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0180, PIN_INPUT, 5) /* (A8) MCASP0_AXR3.MCAN1_RX */ + AM62LX_IOPAD(0x0184, PIN_OUTPUT, 5) /* (B10) MCASP0_AXR2.MCAN1_TX */ + >; + }; + + main_mcan2_pins_default: main-mcan2-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01bc, PIN_INPUT, 6) /* (B14) UART0_CTSn.MCAN2_RX */ + AM62LX_IOPAD(0x01c0, PIN_OUTPUT, 6) /* (B13) UART0_RTSn.MCAN2_TX */ + >; + }; +}; + +&main_uart1 { + /* Conflict with main_mcan1 */ + status = "disabled"; +}; + +&main_i2c1 { + /* + * Set UART1_FET_SEL low to route + * MCAN1 signals to MCAN1 HDR + */ + gpio@22 { + p02-hog { + /* P02 - UART1_FET_SEL */ + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "UART1_FET_SEL"; + }; + }; +}; + +&main_mcan0 { + /* RX p3 & TX p2 of J16 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&transceiver1>; + status = "okay"; +}; + +&main_mcan1 { + /* RX p3 & TX p2 of J6 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan1_pins_default>; + phys = <&transceiver2>; + status = "okay"; +}; + +&main_mcan2 { + /* RX p3 & TX p2 of J18 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan2_pins_default>; + phys = <&transceiver3>; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-nand.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-nand.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-nand.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-nand.dtso 2026-04-21 11:35:28.524915220 +0200 @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include +#include +#include "k3-pinctrl.h" + +&dss { + status = "disabled"; +}; + +&pmx0 { + gpmc0_pins_default: gpmc0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0078, PIN_INPUT, 0) /* (L22) GPMC0_AD0 */ + AM62LX_IOPAD(0x007c, PIN_INPUT, 0) /* (L23) GPMC0_AD1 */ + AM62LX_IOPAD(0x0080, PIN_INPUT, 0) /* (K22) GPMC0_AD2 */ + AM62LX_IOPAD(0x0084, PIN_INPUT, 0) /* (J23) GPMC0_AD3 */ + AM62LX_IOPAD(0x0088, PIN_INPUT, 0) /* (K23) GPMC0_AD4 */ + AM62LX_IOPAD(0x008c, PIN_INPUT, 0) /* (H22) GPMC0_AD5 */ + AM62LX_IOPAD(0x0090, PIN_INPUT, 0) /* (H23) GPMC0_AD6 */ + AM62LX_IOPAD(0x0094, PIN_INPUT, 0) /* (J22) GPMC0_AD7 */ + AM62LX_IOPAD(0x00d4, PIN_INPUT, 0) /* (N23) GPMC0_WAIT0 */ + AM62LX_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (L20) GPMC0_CSn0 */ + AM62LX_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (N19) GPMC0_ADVn_ALE */ + AM62LX_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (N20) GPMC0_OEn_REn */ + AM62LX_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (M19) GPMC0_WEn */ + AM62LX_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (P23) GPMC0_BE0n_CLE */ + AM62LX_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (N21) GPMC0_WPn */ + >; + bootph-all; + }; +}; + +&elm0 { + status = "okay"; + bootph-all; +}; + +&gpmc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&gpmc0_pins_default>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */ + + nand@0,0 { + compatible = "ti,am64-nand"; + reg = <0 0 64>; /* device IO registers */ + interrupt-parent = <&gpmc0>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-xfer-type = "prefetch-polled"; + ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */ + ti,elm-id = <&elm0>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <25>; + gpmc,adv-wr-off-ns = <25>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <3>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "NAND.tiboot3"; + reg = <0x00000000 0x00080000>; /* 512KB */ + }; + partition@80000 { + label = "NAND.tispl"; + reg = <0x80000 0x180000>; /* 1.5M */ + }; + partition@200000 { + label = "NAND.u-boot"; + reg = <0x00200000 0x00200000>; /* 2M */ + }; + partition@400000 { + label = "NAND.tiboot3.backup"; /* 512KB */ + reg = <0x00400000 0x00080000>; /* BootROM looks at 4M */ + }; + partition@480000 { + label = "NAND.tispl.backup"; + reg = <0x00480000 0x180000>; /* 1.5M */ + }; + partition@600000 { + label = "NAND.u-boot.backup"; + reg = <0x00600000 0x00200000>; /* 2M */ + }; + partition@800000 { + label = "NAND.u-boot-env"; + reg = <0x00800000 0x00040000>; /* 256K */ + }; + partition@840000 { + label = "NAND.u-boot-env.backup"; + reg = <0x00840000 0x00040000>; /* 256K */ + }; + partition@880000 { + label = "NAND.file-system"; + reg = <0x00880000 0x1f780000>; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-pwm.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-pwm.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-pwm.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-pwm.dtso 2026-04-21 11:35:28.524915220 +0200 @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * + * DT Overlay for enabling PWM output on user expansion connector for AM62L3 EVM + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&pmx0 { + main_epwm0_pins_default: main-epwm0-pins-default { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00ac, PIN_OUTPUT, 4) /* (G22) GPMC0_AD13.EHRPWM0_A */ + AM62LX_IOPAD(0x00b0, PIN_OUTPUT, 4) /* (F22) GPMC0_AD14.EHRPWM0_B */ + >; + }; + + main_epwm1_pins_default: main-epwm1-pins-default { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00b4, PIN_OUTPUT, 4) /* (F23) GPMC0_AD15.EHRPWM1_A */ + AM62LX_IOPAD(0x00b8, PIN_OUTPUT, 4) /* (L21) GPMC0_CLK.EHRPWM1_B */ + >; + }; + + main_epwm2_pins_default: main-epwm2-pins-default { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00c4, PIN_OUTPUT, 4) /* (N20) GPMC0_OEn_REn.EHRPWM2_A */ + AM62LX_IOPAD(0x00c8, PIN_OUTPUT, 4) /* (M19) GPMC0_WEn.EHRPWM2_B */ + >; + }; + + main_ecap0_pins_default: main-ecap0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0078, PIN_OUTPUT, 5) /* (L22) GPMC0_AD0.ECAP0_IN_APWM_OUT */ + >; + }; + + main_ecap1_pins_default: main_ecap1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x007c, PIN_OUTPUT, 5) /* (L23) GPMC0_AD1.ECAP1_IN_APWM_OUT */ + >; + }; + + main_ecap2_pins_default: main-ecap2-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x009c, PIN_OUTPUT, 5) /* (H20) GPMC0_AD9.ECAP2_IN_APWM_OUT */ + >; + }; +}; + +&main_i2c1 { + gpio@23 { + fet_sel { + /* P01 - VOUT0_FET_SEL0 */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "VOUT0_FET_SEL0"; + }; + }; +}; + +&dss { + status = "disabled"; +}; + +&epwm0 { + /* P18 on J2 & P7 on J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm0_pins_default>; + status = "okay"; +}; + +&epwm1 { + /* P10 on J2 & P5 on J2 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm1_pins_default>; + status = "okay"; +}; + +&epwm2 { + /* P4 on J2 & P1 on J2 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm2_pins_default>; + status = "okay"; +}; + +&ecap0 { + /* ECAP0 in APWM mode */ + /* P24 on J2 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap0_pins_default>; + status = "okay"; +}; + +&ecap1 { + /* ECAP1 in APWM mode */ + /* P26 on J2 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap1_pins_default>; + status = "okay"; +}; + +&ecap2 { + /* ECAP2 in APWM mode */ + /* P9 on J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap2_pins_default>; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-tida-010939.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-tida-010939.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-evm-tida-010939.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-evm-tida-010939.dtso 2026-04-21 11:35:28.524915220 +0200 @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * + * DT Overlay for TIDA-010939 Electric vehicle supply equipment + * front-end controller for AM62L3 EVM. + * + * TIDA-010939: https://www.ti.com/tool/EN/TIDA-010939 + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ +*/ + +/dts-v1/; +/plugin/; + +#include + +#include "k3-pinctrl.h" + +/* Enable extension header power */ +&exp1 { + /* Enable 3.3V power */ + exp_3v3_en: exp-3v3-en { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_3V3_EN"; + }; +}; + +&exp2 { + /* Enable 5V power */ + exp_5v0_en: exp-5v0-en { + gpio-hog; + gpios = <9 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_5V0_EN"; + }; +}; + +/* Pinctrl */ +&pmx0 { + /* Extension header mux selects */ + fetswitchselection_pins_default: fetswitchselection-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01a8, PIN_OUTPUT, 7) /* (E13) SPI0_CLK.GPIO0_89 */ + >; + }; + + /* CG5317 pins */ + cg5317_interrupt_pins_default: cg5317-interrupt-pins-default { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0094, PIN_INPUT, 7) /* (J22) GPIO0_22 */ + AM62LX_IOPAD(0x00cc, PIN_INPUT, 7) /* (P23) GPIO0_35 */ + >; + }; + + cg5317_reset_pin_default: cg5317-reset-pin-default { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (N21) GPMC0_WPn.GPIO0_39 */ + >; + }; + + main_spi1_pins_default: main-spi1-pins-default { + pinctrl-single,pins = < + AM62LX_IOPAD(0x008c, PIN_INPUT, 4) /* (H22) SPI1_CLK */ + AM62LX_IOPAD(0x0080, PIN_OUTPUT, 4) /* (K22) SPI1_DO */ + AM62LX_IOPAD(0x0084, PIN_INPUT, 4) /* (J23) SPI1_DI */ + AM62LX_IOPAD(0x0088, PIN_OUTPUT, 4) /* (K23) SPI1_CS0 */ + >; + }; + + /* MSP pins */ + msp_gpio_pins_default: msp-gpio-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00b4, PIN_OUTPUT, 7) /* (F23) GPMC0_AD15.GPIO0_30 */ + AM62LX_IOPAD(0x00d0, PIN_OUTPUT, 7) /* (P22) GPMC0_BE1n.GPIO0_36 */ + >; + }; + + msp_uart_pins_default: msp-uart-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0098, PIN_INPUT, 2) /* (H19) GPMC0_AD8.UART2_RXD */ + AM62LX_IOPAD(0x009c, PIN_OUTPUT, 2) /* (H20) GPMC0_AD9.UART2_TXD */ + >; + }; + + /* CAN pins */ + can_tida939_pins_default: can-tida939-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00d8, PIN_INPUT, 9) /* (N22) GPMC0_WAIT1.MCAN1_RX */ + AM62LX_IOPAD(0x00e0, PIN_OUTPUT, 9) /* (M21) GPMC0_DIR.MCAN1_TX */ + >; + }; + + main_mcan0_pins_default: main-mcan0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01c8, PIN_INPUT, 0) /* (B15) MCAN0_RX */ + AM62LX_IOPAD(0x01c4, PIN_OUTPUT, 0) /* (B16) MCAN0_TX */ + >; + }; + + main_mcan2_pins_default: main-mcan2-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01bc, PIN_INPUT, 6) /* (B14) UART0_CTSn.MCAN2_RX */ + AM62LX_IOPAD(0x01c0, PIN_OUTPUT, 6) /* (B13) UART0_RTSn.MCAN2_TX */ + >; + }; + + /* RS485 */ + rs485_pins_default: rs485-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0090, PIN_INPUT, 7) /* (H23) GPMC0_AD6.GPIO0_21 */ + AM62LX_IOPAD(0x00a8, PIN_INPUT, 2) /* (G23) GPMC0_AD12.UART4_RXD */ + AM62LX_IOPAD(0x00ac, PIN_OUTPUT, 2) /* (G22) GPMC0_AD13.UART4_TXD */ + >; + }; + + /* RS232 */ + rs232_pins_default: rs232-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00a0, PIN_INPUT, 2) /* (H21) GPMC0_AD10.UART3_RXD */ + AM62LX_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (H18) GPMC0_AD11.UART3_TXD */ + >; + }; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&fetswitchselection_pins_default>; + fet-switch-select-hog { + gpio-hog; + gpios = <89 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SOC_VOUT0_FET_SEL0"; + }; +}; + +&main_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi1_pins_default>, + <&cg5317_interrupt_pins_default>, + <&cg5317_reset_pin_default>; + ti,pindir-d0-out-d1-in = <0x01>; + status = "okay"; + + cg5317@0 { + compatible = "cg,cg5317"; + reg = <0>; + interrupts-extended = <&main_gpio0 22 0x1>, + <&main_gpio0 35 0x1>; + interrupt-names = "gp_irq", "rx_irq"; + spi-cpha; + spi-max-frequency = <1000000>; + }; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + status = "okay"; + bootph-all; +}; + +&main_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&can_tida939_pins_default>; + status = "okay"; + bootph-all; +}; + +&main_mcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan2_pins_default>; + status = "okay"; + bootph-all; +}; + +&main_uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&msp_uart_pins_default>, + <&msp_gpio_pins_default>; + status = "okay"; + bootph-all; +}; + +&main_uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&rs232_pins_default>; + status = "okay"; + bootph-all; +}; + +&main_uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&rs485_pins_default>; + status = "okay"; + rts-gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + bootph-all; +}; + +/** + * Disable HDMI bridge, since Video Output pins are used as + * MSP, CAN, RS232 & RS485 pins on TIDA-010939. + */ +&sii9022 { + status = "disabled"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-minimal.dts v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-minimal.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l3-minimal.dts 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l3-minimal.dts 2026-04-21 11:35:28.525915223 +0200 @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * AM62L3 Minimal + * + * DT supports loading U-Boot binaries via UART and kernel image, + * initramfs, and kernel devicetree through SD. + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +/dts-v1/; + +#include "k3-am62l3.dtsi" + +/ { + compatible = "ti,am62l3-minimal", "ti,am62l3"; + model = "Texas Instruments AM62L3 MINIMAL"; + + chosen { + stdout-path = &main_uart0; + }; + + memory@80000000 { + /* Limited to 128MB */ + reg = <0x00000000 0x80000000 0x00000000 0x8000000>; + device_type = "memory"; + bootph-all; + }; +}; + +&pmx0 { + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01b4, PIN_INPUT, 0) /* (D13) UART0_RXD */ + AM62LX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */ + >; + bootph-all; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0230, PIN_INPUT, 0) /* (Y3) MMC1_CMD */ + AM62LX_IOPAD(0x0228, PIN_OUTPUT, 0) /* (Y2) MMC1_CLK */ + AM62LX_IOPAD(0x0224, PIN_INPUT, 0) /* (AA1) MMC1_DAT0 */ + AM62LX_IOPAD(0x0220, PIN_INPUT, 0) /* (Y4) MMC1_DAT1 */ + AM62LX_IOPAD(0x021c, PIN_INPUT, 0) /* (AA2) MMC1_DAT2 */ + AM62LX_IOPAD(0x0218, PIN_INPUT, 0) /* (AB2) MMC1_DAT3 */ + AM62LX_IOPAD(0x0234, PIN_INPUT, 0) /* (B6) MMC1_SDCD */ + >; + bootph-all; + }; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + bootph-all; + status = "okay"; +}; + +&sdhci1 { + /* SD/MMC */ + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + /* Limited to legacy mode */ + sdhci-caps-mask = <0x00000007 0x00200000>; + disable-wp; + bootph-all; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62l.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l.dtsi 2026-04-21 11:35:28.522915215 +0200 @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree Source for AM62L SoC Family + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +#include +#include +#include + +#include "k3-pinctrl.h" + +/ { + model = "Texas Instruments K3 AM62L3 SoC"; + compatible = "ti,am62l3"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82004000>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + bootph-all; + }; + + scmi_pds: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + bootph-all; + }; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + system-idle-states { + system_rtc_ddr: system-rtc-ddr { + compatible = "system-idle-state"; + idle-state-name = "mem-deep"; + }; + + system_deep_sleep: system-deep-sleep { + compatible = "system-idle-state"; + idle-state-name = "mem"; + }; + }; + + cbass_main: bus@f0000 { + compatible = "simple-bus"; + ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00010100>, /* GPIO */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00040000>, /* GTC */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* CPSW */ + <0x00 0x09000000 0x00 0x09000000 0x00 0x00400000>, /* CTRL MMRs */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00400000>, /* DSS */ + <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI Wrapper */ + <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI Config */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00001000>, /* GPMC0 */ + <0x00 0x3b100000 0x00 0x3b100000 0x00 0x0000007d>, /* RNG */ + <0x00 0x47000000 0x00 0x47000000 0x00 0x02000000>, /* DMSS */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC DATA */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x70800000 0x00 0x70800000 0x00 0x00010000>, /* OCSRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + + /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */ + <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */ + <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */ + <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00200200>, /* Peripheral window */ + <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */ + #address-cells = <2>; + #size-cells = <2>; + + cbass_wakeup: bus@43000000 { + compatible = "simple-bus"; + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */ + <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */ + <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */ + <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00200200>, /* Peripheral window */ + <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */ + #address-cells = <2>; + #size-cells = <2>; + bootph-all; + }; + }; + + #include "k3-am62l-thermal.dtsi" +}; + +/* Now include peripherals for each bus segment */ +#include "k3-am62l-main.dtsi" +#include "k3-am62l-wakeup.dtsi" diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi 2026-04-21 11:35:28.522915215 +0200 @@ -0,0 +1,952 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L main domain peripherals + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +&cbass_main { + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01840000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + ranges; + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <3>; + interrupt-controller; + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = ; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_gpio0: gpio@600000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00600000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = , , + , , + , , + , ; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <126>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&scmi_pds 34>; + clocks = <&scmi_clk 140>; + clock-names = "gpio"; + status = "disabled"; + }; + + main_gpio2: gpio@610000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00610000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = , , + , , + , , + , ; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <79>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&scmi_pds 35>; + clocks = <&scmi_clk 141>; + clock-names = "gpio"; + status = "disabled"; + }; + + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&scmi_clk 58>; + clock-names = "fck"; + power-domains = <&scmi_pds 15>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&scmi_clk 63>; + clock-names = "fck"; + power-domains = <&scmi_pds 16>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&scmi_clk 77>; + clock-names = "fck"; + power-domains = <&scmi_pds 17>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&scmi_clk 82>; + clock-names = "fck"; + power-domains = <&scmi_pds 18>; + ti,timer-pwm; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + interrupts = ; + power-domains = <&scmi_pds 89>; + clocks = <&scmi_clk 358>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + interrupts = ; + power-domains = <&scmi_pds 77>; + clocks = <&scmi_clk 312>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart2: serial@2820000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; + interrupts = ; + power-domains = <&scmi_pds 78>; + clocks = <&scmi_clk 314>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart3: serial@2830000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; + interrupts = ; + power-domains = <&scmi_pds 79>; + clocks = <&scmi_clk 316>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart4: serial@2840000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; + interrupts = ; + power-domains = <&scmi_pds 80>; + clocks = <&scmi_clk 318>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart5: serial@2850000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; + interrupts = ; + power-domains = <&scmi_pds 81>; + clocks = <&scmi_clk 320>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart6: serial@2860000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; + interrupts = ; + power-domains = <&scmi_pds 82>; + clocks = <&scmi_clk 322>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_conf: bus@9000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x09000000 0x400000>; + + phy_gmii_sel: phy@1be000 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x1be000 0x8>; + #phy-cells = <1>; + }; + + epwm_tbclk: clock-controller@1e9100 { + compatible = "ti,am62-epwm-tbclk"; + reg = <0x1e9100 0x4>; + #clock-cells = <1>; + }; + }; + + main_rti0: watchdog@e000000 { + compatible = "ti,am62l-rti-wdt"; + reg = <0x00 0x0e000000 0x00 0x100>; + clocks = <&scmi_clk 277>; + power-domains = <&scmi_pds 60>; + assigned-clocks = <&scmi_clk 277>; + assigned-clock-parents = <&scmi_clk 274>; + }; + + main_rti1: watchdog@e010000 { + compatible = "ti,am62l-rti-wdt"; + reg = <0x00 0x0e010000 0x00 0x100>; + clocks = <&scmi_clk 283>; + power-domains = <&scmi_pds 61>; + assigned-clocks = <&scmi_clk 283>; + assigned-clock-parents = <&scmi_clk 280>; + }; + + fss: bus@fc00000 { + compatible = "simple-bus"; + reg = <0x00 0x0fc00000 0x00 0x70000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ospi0: spi@fc40000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + cdns,phase-detect-selector = <2>; + clocks = <&scmi_clk 136>; + assigned-clocks = <&scmi_clk 136>; + assigned-clock-rates = <166666666>; + power-domains = <&scmi_pds 32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usbss0: dwc3-usb@f900000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f900000 0x00 0x800>, + <0x00 0x0f908000 0x00 0x400>; + clocks = <&scmi_clk 331>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&scmi_pds 95>; + ranges; + status = "disabled"; + + usb0: usb@31000000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31000000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + bootph-all; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; + + usbss1: dwc3-usb@f910000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; + clocks = <&scmi_clk 338>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&scmi_pds 96>; + ranges; + status = "disabled"; + + usb1: usb@31100000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31100000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; + + sdhci0: mmc@fa10000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa10000 0x00 0x1000>, <0x00 0xfa18000 0x00 0x400>; + interrupts = ; + power-domains = <&scmi_pds 28>; + clocks = <&scmi_clk 122>, <&scmi_clk 125>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&scmi_clk 125>; + assigned-clock-parents = <&scmi_clk 124>; + bus-width = <8>; + mmc-hs200-1_8v; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-hs200 = <0x6>; + status = "disabled"; + }; + + sdhci1: mmc@fa00000 { + compatible = "ti,j721e-sdhci-4bit"; + reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; + interrupts = ; + power-domains = <&scmi_pds 26>; + clocks = <&scmi_clk 106>, <&scmi_clk 109>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&scmi_clk 109>; + assigned-clock-parents = <&scmi_clk 108>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + status = "disabled"; + }; + + sdhci2: mmc@fa20000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; + interrupts = ; + power-domains = <&scmi_pds 27>; + clocks = <&scmi_clk 114>, <&scmi_clk 117>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&scmi_clk 117>; + assigned-clock-parents = <&scmi_clk 116>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + status = "disabled"; + }; + + main_i2c0: i2c@20000000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20000000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 53>; + clocks = <&scmi_clk 246>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c1: i2c@20010000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20010000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 54>; + clocks = <&scmi_clk 250>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c2: i2c@20020000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20020000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 55>; + clocks = <&scmi_clk 254>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c3: i2c@20030000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20030000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 56>; + clocks = <&scmi_clk 258>; + clock-names = "fck"; + status = "disabled"; + }; + + main_mcan0: can@20701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&scmi_pds 47>; + clocks = <&scmi_clk 179>, <&scmi_clk 178>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan1: can@20711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20711000 0x00 0x200>, + <0x00 0x20718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&scmi_pds 48>; + clocks = <&scmi_clk 185>, <&scmi_clk 184>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan2: can@20721000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20721000 0x00 0x200>, + <0x00 0x20728000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&scmi_pds 49>; + clocks = <&scmi_clk 191>, <&scmi_clk 190>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_spi0: spi@20100000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x20100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 72>; + clocks = <&scmi_clk 299>; + status = "disabled"; + }; + + main_spi1: spi@20110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 73>; + clocks = <&scmi_clk 302>; + status = "disabled"; + }; + + main_spi2: spi@20120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 74>; + clocks = <&scmi_clk 305>; + status = "disabled"; + }; + + main_spi3: spi@20130000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20130000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 75>; + clocks = <&scmi_clk 308>; + status = "disabled"; + }; + + epwm0: pwm@23000000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23000000 0x00 0x100>; + power-domains = <&scmi_pds 40>; + clocks = <&epwm_tbclk 0>, <&scmi_clk 164>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm1: pwm@23010000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23010000 0x00 0x100>; + power-domains = <&scmi_pds 41>; + clocks = <&epwm_tbclk 1>, <&scmi_clk 165>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm2: pwm@23020000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23020000 0x00 0x100>; + power-domains = <&scmi_pds 42>; + clocks = <&epwm_tbclk 2>, <&scmi_clk 166>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + ecap0: pwm@23100000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23100000 0x00 0x100>; + power-domains = <&scmi_pds 23>; + clocks = <&scmi_clk 99>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap1: pwm@23110000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23110000 0x00 0x100>; + power-domains = <&scmi_pds 24>; + clocks = <&scmi_clk 100>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap2: pwm@23120000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23120000 0x00 0x100>; + power-domains = <&scmi_pds 25>; + clocks = <&scmi_clk 101>; + clock-names = "fck"; + status = "disabled"; + }; + + eqep0: counter@23200000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23200000 0x00 0x100>; + power-domains = <&scmi_pds 29>; + clocks = <&scmi_clk 127>; + interrupts = ; + status = "disabled"; + }; + + eqep1: counter@23210000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23210000 0x00 0x100>; + power-domains = <&scmi_pds 30>; + clocks = <&scmi_clk 128>; + interrupts = ; + status = "disabled"; + }; + + eqep2: counter@23220000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23220000 0x00 0x100>; + power-domains = <&scmi_pds 31>; + clocks = <&scmi_clk 129>; + interrupts = ; + status = "disabled"; + }; + + elm0: ecc@25010000 { + compatible = "ti,am64-elm"; + reg = <0x00 0x25010000 0x00 0x2000>; + interrupts = ; + power-domains = <&scmi_pds 25>; + clocks = <&scmi_clk 102>; + clock-names = "fck"; + status = "disabled"; + }; + + tscadc0: tscadc@28001000 { + compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; + reg = <0x00 0x28001000 0x00 0x1000>; + interrupts = ; + power-domains = <&scmi_pds 0>; + clocks = <&scmi_clk 4>; + assigned-clocks = <&scmi_clk 4>; + assigned-clock-parents = <&scmi_clk 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am654-adc", "ti,am3359-adc"; + }; + }; + + dphy_tx0: phy@301c0000 { + compatible = "ti,j721e-dphy"; + reg = <0x0 0x301c0000 0x0 0x1000>; + clocks = <&scmi_clk 348>, <&scmi_clk 343>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&scmi_pds 86>; + assigned-clocks = <&scmi_clk 343>; + assigned-clock-parents = <&scmi_clk 341>; + assigned-clock-rates = <25000000>; + status = "disabled"; + bootph-all; + }; + + dss: dss@30200000 { + compatible = "ti,am62l-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1 */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ + reg-names = "common", "vidl1", "ovr1", "vp1", "common1"; + power-domains = <&scmi_pds 39>; + clocks = <&scmi_clk 162>, + <&scmi_clk 161>; + clock-names = "fck", "vp1"; + interrupts = ; + status = "disabled"; + bootph-all; + + dss_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + dsi0: dsi@30500000 { + compatible = "ti,j721e-dsi"; + reg = <0x0 0x30500000 0x0 0x100000>, <0x0 0x30270000 0x0 0x100>; + clocks = <&scmi_clk 155>, <&scmi_clk 158>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&scmi_pds 38>; + interrupt-parent = <&gic500>; + interrupts = ; + phys = <&dphy_tx0>; + phy-names = "dphy"; + status = "disabled"; + bootph-all; + }; + + gpmc0: memory-controller@3b000000 { + compatible = "ti,am64-gpmc"; + power-domains = <&scmi_pds 37>; + clocks = <&scmi_clk 149>; + clock-names = "fck"; + reg = <0x00 0x3b000000 0x00 0x400>, + <0x00 0x50000000 0x00 0x8000000>; + reg-names = "cfg", "data"; + interrupts = ; + gpmc,num-cs = <3>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + oc_sram: sram@70800000 { + compatible = "mmio-sram"; + reg = <0x00 0x70800000 0x00 0x10000>; + ranges = <0x0 0x00 0x70800000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + bootph-all; + }; + }; + + main_bcdma: dma-controller@485c4000 { + compatible = "ti,am62l-dmss-bcdma"; + reg = <0x00 0x485c4000 0x00 0x4000>, + <0x00 0x48880000 0x00 0x10000>, + <0x00 0x48800000 0x00 0x80000>, + <0x00 0x47000000 0x00 0x200000>; + reg-names = "gcfg", "bchanrt", "chanrt", "ringrt"; + #address-cells = <2>; + #interrupt-cells = <1>; + #dma-cells = <4>; + interrupt-map = <0 0 0 &gic500 0 0 GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <0 0 1 &gic500 0 0 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <0 0 2 &gic500 0 0 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, + <0 0 3 &gic500 0 0 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, + <0 0 4 &gic500 0 0 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <0 0 5 &gic500 0 0 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, + <0 0 6 &gic500 0 0 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, + <0 0 7 &gic500 0 0 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, + <0 0 8 &gic500 0 0 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <0 0 9 &gic500 0 0 GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <0 0 10 &gic500 0 0 GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, + <0 0 11 &gic500 0 0 GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, + <0 0 12 &gic500 0 0 GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <0 0 13 &gic500 0 0 GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <0 0 16 &gic500 0 0 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <0 0 17 &gic500 0 0 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <0 0 24 &gic500 0 0 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <0 0 25 &gic500 0 0 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <0 0 32 &gic500 0 0 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <0 0 33 &gic500 0 0 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <0 0 40 &gic500 0 0 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <0 0 41 &gic500 0 0 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <0 0 48 &gic500 0 0 GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <0 0 49 &gic500 0 0 GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <0 0 50 &gic500 0 0 GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <0 0 51 &gic500 0 0 GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <0 0 52 &gic500 0 0 GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, + <0 0 53 &gic500 0 0 GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, + <0 0 64 &gic500 0 0 GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <0 0 65 &gic500 0 0 GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <0 0 66 &gic500 0 0 GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <0 0 80 &gic500 0 0 GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>, + <0 0 67 &gic500 0 0 GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, + <0 0 128 &gic500 0 0 GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>, + <0 0 129 &gic500 0 0 GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>, + <0 0 130 &gic500 0 0 GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, + <0 0 131 &gic500 0 0 GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, + <0 0 132 &gic500 0 0 GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>, + <0 0 133 &gic500 0 0 GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>, + <0 0 134 &gic500 0 0 GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>, + <0 0 135 &gic500 0 0 GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, + <0 0 136 &gic500 0 0 GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, + <0 0 137 &gic500 0 0 GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>, + <0 0 138 &gic500 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, + <0 0 139 &gic500 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, + <0 0 140 &gic500 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, + <0 0 141 &gic500 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, + <0 0 142 &gic500 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, + <0 0 143 &gic500 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; + }; + + main_pktdma: dma-controller@485c0000 { + compatible = "ti,am62l-dmss-pktdma"; + reg = <0x00 0x485c0000 0x00 0x4000>, + <0x00 0x48900000 0x00 0x80000>, + <0x00 0x47200000 0x00 0x100000>; + reg-names = "gcfg", "chanrt", "ringrt"; + #address-cells = <2>; + #dma-cells = <2>; + #interrupt-cells = <1>; + interrupt-map = <0 0 0 &gic500 0 0 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <0 0 1 &gic500 0 0 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, + <0 0 2 &gic500 0 0 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <0 0 3 &gic500 0 0 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, + <0 0 4 &gic500 0 0 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, + <0 0 5 &gic500 0 0 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, + <0 0 6 &gic500 0 0 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, + <0 0 7 &gic500 0 0 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, + <0 0 8 &gic500 0 0 GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <0 0 9 &gic500 0 0 GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <0 0 10 &gic500 0 0 GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <0 0 11 &gic500 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <0 0 12 &gic500 0 0 GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <0 0 13 &gic500 0 0 GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <0 0 64 &gic500 0 0 GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, + <0 0 65 &gic500 0 0 GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, + <0 0 66 &gic500 0 0 GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, + <0 0 67 &gic500 0 0 GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, + <0 0 68 &gic500 0 0 GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, + <0 0 69 &gic500 0 0 GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, + <0 0 70 &gic500 0 0 GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <0 0 71 &gic500 0 0 GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <0 0 72 &gic500 0 0 GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, + <0 0 73 &gic500 0 0 GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, + <0 0 74 &gic500 0 0 GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, + <0 0 75 &gic500 0 0 GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>, + <0 0 76 &gic500 0 0 GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, + <0 0 77 &gic500 0 0 GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, + <0 0 78 &gic500 0 0 GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>, + <0 0 79 &gic500 0 0 GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>, + <0 0 96 &gic500 0 0 GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>; + }; + + cpsw3g: ethernet@8000000 { + compatible = "ti,am642-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0x08000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; + clocks = <&scmi_clk 9>; + clock-names = "fck"; + power-domains = <&scmi_pds 3>; + dmas = <&main_pktdma 0xc600 15>, + <&main_pktdma 0xc601 15>, + <&main_pktdma 0xc602 15>, + <&main_pktdma 0xc603 15>, + <&main_pktdma 0xc604 15>, + <&main_pktdma 0xc605 15>, + <&main_pktdma 0xc606 15>, + <&main_pktdma 0xc607 15>, + <&main_pktdma 0x4600 15>; + dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", + "tx7", "rx"; + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + phys = <&phy_gmii_sel 1>; + ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; + mac-address = [00 00 00 00 00 00]; + }; + + cpsw_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + phys = <&phy_gmii_sel 2>; + mac-address = [00 00 00 00 00 00]; + }; + }; + + cpsw3g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk 9>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&scmi_clk 10>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + + mcasp0: audio-controller@2b00000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b00000 0x00 0x2000>, + <0x00 0x02b08000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + clocks = <&scmi_clk 194>; + clock-names = "fck"; + assigned-clocks = <&scmi_clk 194>; + assigned-clock-parents = <&scmi_clk 193>; + dmas = <&main_bcdma 0 0 0xc500 0>, <&main_bcdma 0 0 0x4500 0>; + dma-names = "tx", "rx"; + power-domains = <&scmi_pds 50>; + + status = "disabled"; + }; + + mcasp1: audio-controller@2b10000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b10000 0x00 0x2000>, + <0x00 0x02b18000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + clocks = <&scmi_clk 216>; + clock-names = "fck"; + assigned-clocks = <&scmi_clk 216>; + dmas = <&main_bcdma 0 0 0xc501 0>, <&main_bcdma 0 0 0x4501 0>; + dma-names = "tx", "rx"; + power-domains = <&scmi_pds 51>; + + status = "disabled"; + }; + + mcasp2: audio-controller@2b20000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b20000 0x00 0x2000>, + <0x00 0x02b28000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + clocks = <&scmi_clk 230>; + clock-names = "fck"; + assigned-clocks = <&scmi_clk 230>; + dmas = <&main_bcdma 0 0 0xc502 0>, <&main_bcdma 0 0 0x4502 0>; + dma-names = "tx", "rx"; + power-domains = <&scmi_pds 52>; + + status = "disabled"; + }; + + crypto: crypto@40800000 { + compatible = "ti,am62l-dthev2"; + reg = <0x00 0x40800000 0x00 0x14000>; + + dmas = <&main_bcdma 0 0 0x4700 0>, + <&main_bcdma 0 0 0xc701 0>, + <&main_bcdma 0 0 0xc700 0>; + dma-names = "rx", "tx1", "tx2"; + }; + + rng: rng@3b100000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x00 0x3b100000 0x00 0x7d>; + interrupts = ; + status = "reserved"; /* Reserved for OP-TEE */ + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts v_kernel/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts 2026-04-21 11:35:28.508915178 +0200 @@ -7,54 +7,18 @@ /dts-v1/; +#include "k3-am625.dtsi" #include "k3-am62x-sk-common.dtsi" / { compatible = "ti,am62-lp-sk", "ti,am625"; model = "Texas Instruments AM62x LP SK"; - vmain_pd: regulator-0 { - /* TPS65988 PD CONTROLLER OUTPUT */ - compatible = "regulator-fixed"; - regulator-name = "vmain_pd"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_5v0: regulator-1 { - /* Output of TPS630702RNMR */ - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vmain_pd>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_3v3_sys: regulator-2 { - /* output of LM61460-Q1 */ - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vmain_pd>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: regulator-3 { - /* TPS22918DBVR */ - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vcc_3v3_sys>; - gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + memory@80000000 { + bootph-pre-ram; + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; }; vddshv_sdio: regulator-4 { @@ -80,13 +44,13 @@ AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (V3) MMC0_CMD */ AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (Y1) MMC0_CLK */ AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (V2) MMC0_DAT0 */ - AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (V1) MMC0_DAT1 */ - AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (W2) MMC0_DAT2 */ - AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (W1) MMC0_DAT3 */ - AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (Y2) MMC0_DAT4 */ - AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (W3) MMC0_DAT5 */ - AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (W4) MMC0_DAT6 */ - AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (V4) MMC0_DAT7 */ + AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (V1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (W2) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (W1) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (Y2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (W3) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (W4) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (V4) MMC0_DAT7 */ >; }; @@ -265,6 +229,119 @@ bootph-all; }; +&ospi0 { + + flash@0 { + compatible = "spi-nand"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + cdns,phy-mode; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + partition@0 { + label = "ospi_nand.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi_nand.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi_nand.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi_nand.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi_nand.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@2000000 { + label = "ospi_nand.rootfs"; + reg = <0x2000000 0x5fc0000>; + }; + + partition@7fc0000 { + label = "ospi_nand.phypattern"; + reg = <0x7fc0000 0x40000>; + bootph-all; + }; + }; + }; +}; + &gpmc0 { ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */ }; + +&mcu_mcan0 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_default>; + pinctrl-1 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_wakeup>; + status = "okay"; +}; + +&mcu_mcan1 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_default>; + pinctrl-1 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_wakeup>; + status = "okay"; +}; + +&mcu_pmx0 { + mcu_mcan0_tx_pins_default: mcu-mcan0-tx-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan0_rx_pins_default: mcu-mcan0-rx-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan0_rx_pins_wakeup: mcu-mcan0-rx-wakeup-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x038, PIN_INPUT | PIN_WKUP_EN, 0) /* (B3) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan1_tx_pins_default: mcu-mcan1-tx-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x03c, PIN_OUTPUT, 0) /* (E5) MCU_MCAN1_TX */ + >; + }; + + mcu_mcan1_rx_pins_default: mcu-mcan1-rx-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x040, PIN_INPUT, 0) /* (D4) MCU_MCAN1_RX */ + >; + }; + + mcu_mcan1_rx_pins_wakeup: mcu-mcan1-rx-wakeup-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x040, PIN_INPUT | PIN_WKUP_EN, 0) /* (D4) MCU_MCAN1_RX */ + >; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-lp-sk-lincolntech-lcd185-panel.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62-lp-sk-lincolntech-lcd185-panel.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-lp-sk-lincolntech-lcd185-panel.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62-lp-sk-lincolntech-lcd185-panel.dtso 2026-04-21 11:35:28.508915178 +0200 @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-or-late OR MIT +/** + * Lincoln tech Solutions OLDI panel (LCD185-101CT) and touch DT overlay for AM62-LP-SK + * + * AM62-LP SKEVM: https://www.ti.com/tool/SK-AM62-LP + * Panel datasheet: https://lincolntechsolutions.com/wp-content/uploads/2023/04/LCD185-101CTL1ARNTT_DS_R1.3.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + display { + compatible = "lincolntech,lcd185-101ct", "panel-simple"; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * Swapping them will cause an error in the dss oldi driver. + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_0_out>; + }; + }; + port@1 { + reg = <1>; + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_1_out>; + }; + }; + }; + }; +}; + +&dss { + status = "okay"; +}; + +&oldi0 { + status = "okay"; + ti,companion-oldi = <&oldi1>; +}; + +&oldi1 { + status = "okay"; + ti,secondary-oldi; +}; + +&oldi0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + oldi_0_in: endpoint { + remote-endpoint = <&dpi0_out0>; + }; + }; + + port@1 { + reg = <1>; + oldi_0_out: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; +}; + +&oldi1_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + oldi_1_in: endpoint { + remote-endpoint = <&dpi0_out1>; + }; + }; + + port@1 { + reg = <1>; + oldi_1_out: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: Output to OLDI */ + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dpi0_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&oldi_0_in>; + }; + dpi0_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&oldi_1_in>; + }; + }; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@57 { + compatible = "atmel,24c256"; + reg = <0x57>; + }; + + touchscreen@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + interrupt-parent = <&exp1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&exp1 15 GPIO_ACTIVE_LOW>; + reset-gpios = <&exp2 18 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1920>; + touchscreen-size-y = <1200>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-lp-sk-microtips-mf101hie-panel.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62-lp-sk-microtips-mf101hie-panel.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-lp-sk-microtips-mf101hie-panel.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62-lp-sk-microtips-mf101hie-panel.dtso 2026-04-21 11:35:28.508915178 +0200 @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * Microtips integrated OLDI panel (MF-101HIEBCAF0) and touch DT overlay for AM62 LP-SK + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + display { + compatible = "microtips,mf-101hiebcaf0", "panel-simple"; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * Swapping them will cause an error in the dss oldi driver. + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_0_out>; + }; + }; + port@1 { + reg = <1>; + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_1_out>; + }; + }; + }; + }; +}; + +&dss { + status = "okay"; +}; + +&oldi0 { + status = "okay"; + ti,companion-oldi = <&oldi1>; +}; + +&oldi1 { + status = "okay"; + ti,secondary-oldi; + ti,companion-oldi = <&oldi0>; +}; + +&oldi0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + oldi_0_in: endpoint { + remote-endpoint = <&dpi0_out0>; + }; + }; + + port@1 { + reg = <1>; + oldi_0_out: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; +}; + +&oldi1_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + oldi_1_in: endpoint { + remote-endpoint = <&dpi0_out1>; + }; + }; + + port@1 { + reg = <1>; + oldi_1_out: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: Output to OLDI */ + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dpi0_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&oldi_0_in>; + }; + dpi0_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&oldi_1_in>; + }; + }; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&exp1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&exp2 18 GPIO_ACTIVE_LOW>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l-thermal.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62l-thermal.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l-thermal.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l-thermal.dtsi 2026-04-21 11:35:28.522915215 +0200 @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi 2026-04-21 11:35:28.522915215 +0200 @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L wakeup domain peripherals + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +#include + +&cbass_wakeup { + wkup_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&scmi_pds 46>; + #thermal-sensor-cells = <1>; + }; + + pmx0: pinctrl@4084000 { + compatible = "ti,am62l-padconf", "pinctrl-single"; + reg = <0x00 0x4084000 0x00 0x24c>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + #pinctrl-cells = <1>; + /* + * pinctrl IP DOES NOT give any functional IRQs when a + * system is in active state. This IRQ is only a dummy IRQ + * that is being used to trick Linux into thinking that + * GIC can potentially receive an interrupt from this IP. + * This helps us setup the IO daisychain wakeups for deep + * sleep via chained wake IRQs. + * Please feel free to assign a different number here as + * long as it is unused if 95 conflicts with another use case. + */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + bootph-all; + }; + + wkup_gpio0: gpio@4201000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x04201000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = , , + , , + , , + , ; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <7>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&scmi_pds 36>; + clocks = <&scmi_clk 146>; + clock-names = "gpio"; + status = "disabled"; + }; + + wkup_timer0: timer@2b100000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2b100000 0x00 0x400>; + interrupts = ; + clocks = <&scmi_clk 93>; + clock-names = "fck"; + power-domains = <&scmi_pds 19>; + ti,timer-pwm; + }; + + wkup_timer1: timer@2b110000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2b110000 0x00 0x400>; + interrupts = ; + clocks = <&scmi_clk 98>; + clock-names = "fck"; + power-domains = <&scmi_pds 20>; + ti,timer-pwm; + }; + + wkup_i2c0: i2c@2b200000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x2b200000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 57>; + clocks = <&scmi_clk 262>; + clock-names = "fck"; + status = "disabled"; + }; + + wkup_uart0_interconnect: target-module@2b300050 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x00 0x2b300050 0x00 0x4>, + <0x00 0x2b300054 0x00 0x4>, + <0x00 0x2b300058 0x00 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + ti,no-reset-on-init; + power-domains = <&scmi_pds 83>; + clocks = <&scmi_clk 324>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x2b300000 0x100000>; + status = "disabled"; + + wkup_uart0: serial@0 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x0 0x100>; + interrupts = ; + clocks = <&scmi_clk 324>; + assigned-clocks = <&scmi_clk 324>; + clock-names = "fck"; + status = "disabled"; + }; + }; + + wkup_rtc0: rtc@2b1f0000 { + compatible = "ti,am62l-rtc"; + reg = <0x00 0x2b1f0000 0x00 0x100>; + interrupts = ; + clocks = <&scmi_clk 271> , <&scmi_clk 268>; + clock-names = "vbus", "osc32k"; + assigned-clocks = <&scmi_clk 488>; + assigned-clock-parents = <&scmi_clk 487>; + power-domains = <&scmi_pds 59>; + wakeup-source; + }; + + wkup_conf: bus@43000000 { + compatible = "simple-bus"; + ranges = <0x0 0x00 0x43000000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + + chipid: chipid@14 { + compatible = "ti,am654-chipid"; + reg = <0x14 0x4>; + bootph-all; + }; + + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + + cpsw_mac_syscon: ethernet-mac-syscon@2000 { + compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; + reg = <0x2000 0x8>; + }; + + usb0_phy_ctrl: syscon@45000 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x45000 0x4>; + bootph-all; + }; + + usb1_phy_ctrl: syscon@45004 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x45004 0x4>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-main.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62-main.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-main.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62-main.dtsi 2026-04-21 11:35:28.509915181 +0200 @@ -76,6 +76,16 @@ assigned-clock-parents = <&k3_clks 157 18>; #clock-cells = <0>; }; + + dss_oldi_io_ctrl: oldi-io-controller@8600 { + compatible = "ti,am625-dss-oldi-io-ctrl", "syscon"; + reg = <0x8600 0x200>; + }; + + dss_clk_ctrl: dss_clk_ctrl@8300 { + compatible = "ti,am625-dss-clk-ctrl", "syscon"; + reg = <0x8300 0x4>; + }; }; dmss: bus@48000000 { @@ -209,6 +219,23 @@ dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, <&main_pktdma 0x7507 0>; dma-names = "tx", "rx1", "rx2"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; + + rng: rng@40910000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x00 0x40910000 0x00 0x7d>; + interrupts = ; + status = "reserved"; /* Reserved for OP-TEE */ + }; + }; + + crc: crc@30300000 { + compatible = "ti,am62-mcrc64"; + reg = <0x00 0x30300000 0x00 0x1000>; + clocks = <&k3_clks 116 0>; + power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; }; secure_proxy_sa3: mailbox@43600000 { @@ -229,11 +256,24 @@ main_pmx0: pinctrl@f4000 { bootph-all; - compatible = "pinctrl-single"; + compatible = "ti,am654-padconf", "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2ac>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; + /* + * pinctrl IP DOES NOT give any functional IRQs when a + * system is in active state. This IRQ is only a dummy IRQ + * that is being used to trick Linux into thinking that + * GIC can potentially recieve an interrupt from this IP. + * This helps us setup the IO daisychain wakeups for deep + * sleep via chained wake IRQs. + * Please feel free to assign a different number here as + * long as it is unused if 98 conflicts with another use case. + */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; }; main_esm: esm@420000 { @@ -557,10 +597,9 @@ ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x5>; - ti,otap-del-sel-hs200 = <0x5>; - ti,itap-del-sel-legacy = <0xa>; - ti,itap-del-sel-mmc-hs = <0x1>; + ti,otap-del-sel-hs200 = <0x6>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-mmc-hs = <0x0>; status = "disabled"; }; @@ -573,17 +612,17 @@ clock-names = "clk_ahb", "clk_xin"; bus-width = <4>; ti,clkbuf-sel = <0x7>; - ti,otap-del-sel-legacy = <0x8>; + ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0x0>; - ti,otap-del-sel-sdr25 = <0x0>; - ti,otap-del-sel-sdr50 = <0x8>; - ti,otap-del-sel-sdr104 = <0x7>; - ti,otap-del-sel-ddr50 = <0x4>; - ti,itap-del-sel-legacy = <0xa>; - ti,itap-del-sel-sd-hs = <0x1>; - ti,itap-del-sel-sdr12 = <0xa>; - ti,itap-del-sel-sdr25 = <0x1>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; @@ -596,17 +635,17 @@ clock-names = "clk_ahb", "clk_xin"; bus-width = <4>; ti,clkbuf-sel = <0x7>; - ti,otap-del-sel-legacy = <0x8>; + ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0x0>; - ti,otap-del-sel-sdr25 = <0x0>; - ti,otap-del-sel-sdr50 = <0x8>; - ti,otap-del-sel-sdr104 = <0x7>; - ti,otap-del-sel-ddr50 = <0x8>; - ti,itap-del-sel-legacy = <0xa>; - ti,itap-del-sel-sd-hs = <0xa>; - ti,itap-del-sel-sdr12 = <0xa>; - ti,itap-del-sel-sdr25 = <0x1>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; @@ -677,6 +716,7 @@ cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; + cdns,phase-detect-selector = <2>; clocks = <&k3_clks 75 7>; assigned-clocks = <&k3_clks 75 7>; assigned-clock-parents = <&k3_clks 75 8>; @@ -785,14 +825,54 @@ <&k3_clks 186 2>; clock-names = "fck", "vp1", "vp2"; interrupts = ; + ti,clk-ctrl = <&dss_clk_ctrl>; status = "disabled"; + oldi-transmitters { + #address-cells = <1>; + #size-cells = <0>; + + oldi0: oldi@0 { + reg = <0>; + clocks = <&k3_clks 186 0>; + clock-names = "serial"; + ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; + status = "disabled"; + + oldi0_ports: ports { + }; + }; + + /* + * OLDI1 in AM625 SoC can only act as a secondary OLDI, if + * required, hence the clock and io-ctrl properties are not + * required at the moment. + */ + oldi1: oldi@1 { + reg = <1>; + clocks = <&k3_clks 186 0>; + clock-names = "serial"; + ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; + status = "disabled"; + + oldi1_ports: ports { + }; + }; + }; + dss_ports: ports { #address-cells = <1>; #size-cells = <0>; }; }; + timesync_router: mux-controller@a40000 { + compatible = "reg-mux"; + reg = <0x0 0xa40000 0x0 0x800>; + #mux-control-cells = <1>; + status = "disabled"; + }; + hwspinlock: spinlock@2a000000 { compatible = "ti,am64-hwspinlock"; reg = <0x00 0x2a000000 0x00 0x1000>; @@ -839,6 +919,33 @@ status = "disabled"; }; + eqep0: counter@23200000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23200000 0x00 0x100>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 59 0>; + interrupts = ; + status = "disabled"; + }; + + eqep1: counter@23210000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23210000 0x00 0x100>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 60 0>; + interrupts = ; + status = "disabled"; + }; + + eqep2: counter@23220000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23220000 0x00 0x100>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 62 0>; + interrupts = ; + status = "disabled"; + }; + main_mcan0: can@20701000 { compatible = "bosch,m_can"; reg = <0x00 0x20701000 0x00 0x200>, @@ -991,8 +1098,9 @@ ti_csi2rx0: ticsi2rx@30102000 { compatible = "ti,j721e-csi2rx-shim"; - dmas = <&main_bcdma 0 0x4700 0>; - dma-names = "rx0"; + dmas = <&main_bcdma 0 0x4700 0>, <&main_bcdma 0 0x4701 0>, + <&main_bcdma 0 0x4702 0>, <&main_bcdma 0 0x4703 0>; + dma-names = "rx0", "rx1", "rx2", "rx3"; reg = <0x00 0x30102000 0x00 0x1000>; power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; #address-cells = <2>; @@ -1003,6 +1111,9 @@ cdns_csi2rx0: csi-bridge@30101000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30101000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -1050,6 +1161,105 @@ status = "disabled"; }; + pruss: pruss@30040000 { + compatible = "ti,am625-pruss"; + reg = <0x00 0x30040000 0x00 0x80000>; + power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x30040000 0x80000>; + + pruss_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x10000>; + reg-names = "dram0", "dram1", "shrdram2"; + }; + + pruss_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + pruss_coreclk_mux: coreclk-mux@3c { + reg = <0x3c>; + #clock-cells = <0>; + clocks = <&k3_clks 81 0>, /* pruss_core_clk */ + <&k3_clks 81 14>; /* pruss_iclk */ + assigned-clocks = <&pruss_coreclk_mux>; + assigned-clock-parents = <&k3_clks 81 14>; + }; + + pruss_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&k3_clks 81 3>, /* pruss_iep_clk */ + <&pruss_coreclk_mux>; /* pruss_coreclk_mux */ + assigned-clocks = <&pruss_iepclk_mux>; + assigned-clock-parents = <&pruss_coreclk_mux>; + }; + }; + }; + + pruss_intc: interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + }; + + pruss_uart: serial@28000 { + compatible = "ti,pruss-uart"; + reg = <0x28000 0x40>; + clocks = <&k3_clks 81 13>; /* pruss_uart_clk */ + interrupt-parent = <&pruss_intc>; + interrupts = <6 4 4>; + status = "disabled"; + }; + + pru0: pru@34000 { + compatible = "ti,am625-pru"; + reg = <0x34000 0x4000>, + <0x22000 0x100>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am62x-pru0-fw"; + interrupt-parent = <&pruss_intc>; + interrupts = <16 2 2>; + interrupt-names = "vring"; + }; + + pru1: pru@38000 { + compatible = "ti,am625-pru"; + reg = <0x38000 0x4000>, + <0x24000 0x100>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am62x-pru1-fw"; + interrupt-parent = <&pruss_intc>; + interrupts = <18 3 3>; + interrupt-names = "vring"; + }; + }; + gpmc0: memory-controller@3b000000 { compatible = "ti,am64-gpmc"; power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; @@ -1079,4 +1289,24 @@ clock-names = "fck"; status = "disabled"; }; + + memorycontroller: memory-controller@f300000 { + compatible = "ti,am62-ddrss"; + reg = <0x00 0x0f300000 0x00 0x200>; + reg-names = "ss_cfg"; + ranges = <0x00 0x00 0x00 0x0f308000 0x00 0x55f8>; + interrupts = ; + power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 170 0>; + #address-cells = <2>; + #size-cells = <2>; + + ddr: ddr@0 { + compatible = "cdns,j7-ddr"; + reg = <0x00 0x0000 0x00 0x69c>, + <0x00 0x2000 0x00 0x564>, + <0x00 0x4000 0x00 0x15f8>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + }; + }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi 2026-04-21 11:35:28.509915181 +0200 @@ -174,4 +174,17 @@ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; + + mcu_m4fss: m4fss@5000000 { + compatible = "ti,am64-m4fss"; + reg = <0x00 0x5000000 0x00 0x30000>, + <0x00 0x5040000 0x00 0x10000>; + reg-names = "iram", "dram"; + resets = <&k3_reset 9 1>; + firmware-name = "am62-mcu-m4f0_0-fw"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <9>; + ti,sci-proc-ids = <0x18 0xff>; + status = "disabled"; + }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62p5.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p5.dtsi 2026-04-21 11:35:28.528915230 +0200 @@ -47,6 +47,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 135 0>; }; @@ -62,6 +63,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 136 0>; }; @@ -77,6 +79,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 137 0>; }; @@ -92,10 +95,54 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 138 0>; }; }; + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&opp_efuse_table>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; + }; + }; + l2_0: l2-cache0 { compatible = "cache"; cache-unified; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-dsi-rpi-7inch-panel.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-dsi-rpi-7inch-panel.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-dsi-rpi-7inch-panel.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-dsi-rpi-7inch-panel.dtso 2026-04-21 11:35:28.526915225 +0200 @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * DT Overlay for RPi 7inch touchscreen panel interfaced with DSI on + * AM62P5-SK EVM. + * + * RPi DSI Panel: https://www.raspberrypi.com/products/raspberry-pi-touch-display/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + panel0 { + compatible = "raspberrypi,7inch-dsi", "simple-panel"; + backlight = <&display_reg>; + power-supply = <&display_reg>; + + port { + + panel_in: endpoint { + remote-endpoint = <&panel_bridge_out>; + }; + }; + }; + + bridge_reg: bridge-regulator { + compatible = "regulator-fixed"; + regulator-name = "bridge-reg"; + gpio = <&display_reg 0 0>; + vin-supply = <&display_reg>; + enable-active-high; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + display_reg: regulator@45 { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + }; + + touch-controller@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + + touchscreen-size-x = < 800 >; + touchscreen-size-y = < 480 >; + + vcc-supply = <&display_reg>; + reset-gpio = <&display_reg 1 1>; + + touchscreen-inverted-x; + touchscreen-inverted-y; + }; +}; + +&dss1 { + status = "okay"; +}; + +&dss1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* DSS1-VP1: DSI Output */ + port@1 { + reg = <1>; + + dss1_dpi1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&dsi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&panel_bridge_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dss1_dpi1_out>; + }; + }; + }; + + bridge@0 { + status = "okay"; + compatible = "toshiba,tc358762"; + reg = <0>; + vddc-supply = <&bridge_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + panel_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-dss-shared-mode.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-dss-shared-mode.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-dss-shared-mode.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-dss-shared-mode.dtso 2026-04-21 11:35:28.527915228 +0200 @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * DT overlay to enable display sharing mode for AM62P DSS0 + * This is compatible with AM62P Device Manager firmware labelled as + * "dss_display_share.wkup-r5f0_0.release.strip.out" + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&dss0 { + ti,dss-shared-mode; + ti,dss-shared-mode-vp = "vp1"; + ti,dss-shared-mode-vp-owned = <0>; + ti,dss-shared-mode-common = "common1"; + ti,dss-shared-mode-planes = "vid"; + ti,dss-shared-mode-plane-zorder = <0>; + interrupt-parent = <&gic500>; + interrupts = ; +}; + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + rtos_framebuffer_memory_region: rtos-framebuffer-memory@93500000 { + reg = <0x00 0x93500000 0x00 0x08000000>; + no-map; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts 2026-04-21 11:35:28.528915230 +0200 @@ -19,6 +19,7 @@ aliases { serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart0; serial3 = &main_uart1; mmc0 = &sdhci0; @@ -32,7 +33,21 @@ }; chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + stdout-path = &main_uart0; + + framebuffer0: framebuffer@0 { + compatible = "simple-framebuffer"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&dss0_vp1_clk>, + <&k3_clks 186 2>; + display = <&dss0>; + status = "disabled"; + }; }; memory@80000000 { @@ -43,24 +58,55 @@ bootph-pre-ram; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; - secure_tfa_ddr: tfa@9e780000 { - reg = <0x00 0x9e780000 0x00 0x80000>; + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x24000000>; + linux,cma-default; + }; + + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b500000 0x00 0x00300000>; no-map; }; - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0xf00000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { compatible = "shared-dma-pool"; - reg = <0x00 0x9c900000 0x00 0x01e00000>; + reg = <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x1e00000>; + no-map; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ no-map; }; }; @@ -128,6 +174,15 @@ }; }; + opp-table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + tlv320_mclk: clk-0 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -162,6 +217,17 @@ clocks = <&tlv320_mclk>; }; }; + + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; }; &main_gpio0 { @@ -217,6 +283,7 @@ AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */ AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */ >; + bootph-all; }; main_mmc1_pins_default: main-mmc1-default-pins { @@ -224,9 +291,9 @@ AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */ AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */ AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */ - AM62PX_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H23) MMC1_DAT1 */ - AM62PX_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (H22) MMC1_DAT2 */ - AM62PX_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ + AM62PX_IOPAD(0x022c, PIN_INPUT, 0) /* (H23) MMC1_DAT1 */ + AM62PX_IOPAD(0x0228, PIN_INPUT, 0) /* (H22) MMC1_DAT2 */ + AM62PX_IOPAD(0x0224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */ AM62PX_IOPAD(0x0240, PIN_INPUT, 0) /* (D23) MMC1_SDCD */ >; bootph-all; @@ -281,14 +348,26 @@ bootph-all; }; - main_uart0_pins_default: main-uart0-default-pins { + main_uart0_tx_pins_default: main-uart0-tx-default-pins { pinctrl-single,pins = < - AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ >; bootph-all; }; + main_uart0_rx_pins_default: main-uart0-rx-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + >; + bootph-all; + }; + + main_uart0_rx_pins_wakeup: main-uart0-rx-wakeup-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x1c8, PIN_INPUT | PIN_WKUP_EN, 0) /* (A22) UART0_RXD */ + >; + }; + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM62PX_IOPAD(0x0194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3.UART1_CTSn */ @@ -301,7 +380,7 @@ main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < - AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ + AM62PX_IOPAD(0x0258, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (G21) USB1_DRVVBUS */ >; }; @@ -346,6 +425,66 @@ AM62PX_IOPAD(0x0124, PIN_INPUT, 7) /* (J25) MMC2_SDCD.GPIO0_71 */ >; }; + + main_dpi_pins_default: main-dpi-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0100, PIN_OUTPUT, 0) /* (W20) VOUT0_VSYNC */ + AM62PX_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AC20) VOUT0_HSYNC */ + AM62PX_IOPAD(0x0104, PIN_OUTPUT, 0) /* (Y21) VOUT0_PCLK */ + AM62PX_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (W21) VOUT0_DE */ + AM62PX_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (AE24) VOUT0_DATA0 */ + AM62PX_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (W23) VOUT0_DATA1 */ + AM62PX_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA2 */ + AM62PX_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA3 */ + AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (AB23) VOUT0_DATA4 */ + AM62PX_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (AD23) VOUT0_DATA5 */ + AM62PX_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (AC23) VOUT0_DATA6 */ + AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AE23) VOUT0_DATA7 */ + AM62PX_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (AE22) VOUT0_DATA8 */ + AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (AC22) VOUT0_DATA9 */ + AM62PX_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA10 */ + AM62PX_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AE21) VOUT0_DATA11 */ + AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AD21) VOUT0_DATA12 */ + AM62PX_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AC21) VOUT0_DATA13 */ + AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AA20) VOUT0_DATA14 */ + AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (Y20) VOUT0_DATA15 */ + AM62PX_IOPAD(0x005c, PIN_OUTPUT, 1) /* (AC25) GPMC0_AD8.VOUT0_DATA16 */ + AM62PX_IOPAD(0x0060, PIN_OUTPUT, 1) /* (AB25) GPMC0_AD9.VOUT0_DATA17 */ + AM62PX_IOPAD(0x0064, PIN_OUTPUT, 1) /* (AA25) GPMC0_AD10.VOUT0_DATA18 */ + AM62PX_IOPAD(0x0068, PIN_OUTPUT, 1) /* (W24) GPMC0_AD11.VOUT0_DATA19 */ + AM62PX_IOPAD(0x006c, PIN_OUTPUT, 1) /* (Y24) GPMC0_AD12.VOUT0_DATA20 */ + AM62PX_IOPAD(0x0070, PIN_OUTPUT, 1) /* (AD25) GPMC0_AD13.VOUT0_DATA21 */ + AM62PX_IOPAD(0x0074, PIN_OUTPUT, 1) /* (AB24) GPMC0_AD14.VOUT0_DATA22 */ + AM62PX_IOPAD(0x0078, PIN_OUTPUT, 1) /* (AC24) GPMC0_AD15.VOUT0_DATA23 */ + AM62PX_IOPAD(0x009c, PIN_OUTPUT, 1) /* (AD24) GPMC0_WAIT1.VOUT0_EXTPCLKIN */ + >; + }; + + main_epwm0_pins_default: main_epwm0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (D20) SPI0_CS0.EHRPWM0_A */ + AM62PX_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (E20) SPI0_CS1.EHRPWM0_B */ + >; + }; + + main_epwm1_pins_default: main_epwm1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 2) /* (B21) SPI0_CLK.EHRPWM1_A */ + AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 2) /* (B20) SPI0_D0.EHRPWM1_B */ + >; + }; + + main_ecap1_pins_default: main_ecap1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x019c, PIN_OUTPUT, 2) /* (E24) MCASP0_AXR1.ECAP1_IN_APWM_OUT */ + >; + }; + + main_ecap2_pins_default: main-ecap2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01a4, PIN_OUTPUT, 2) /* (F24) MCASP0_ACLKX.ECAP2_IN_APWM_OUT */ + >; + }; }; &main_i2c0 { @@ -433,6 +572,41 @@ "GPIO_OLDI_RSTn", "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", "SoC_WLAN_SDIO_RST"; }; + + sii9022: bridge-hdmi@3b { + compatible = "sil,sii9022"; + reg = <0x3b>; + interrupt-parent = <&exp1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = < 0 >; + + hdmi_tx_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * HDMI can be serviced with 3 potential VPs - + * (DSS0 VP1 / DSS1 VP0 / DSS1 VP1). + * For now, we will service it with DSS0 VP1. + */ + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dss0_dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; }; &main_i2c2 { @@ -486,6 +660,7 @@ cpsw3g_phy0: ethernet-phy@0 { reg = <0>; + bootph-all; ti,rx-internal-delay = ; ti,fifo-depth = ; ti,min-output-impedance; @@ -519,6 +694,10 @@ }; }; +&usb0_phy_ctrl { + bootph-all; +}; + &usb1 { dr_mode = "host"; pinctrl-names = "default"; @@ -564,6 +743,7 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + cdns,phy-mode; bootph-all; partitions { @@ -612,6 +792,8 @@ }; &mailbox0_cluster0 { + status = "okay"; + mbox_r5_0: mbox-r5-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; @@ -619,15 +801,41 @@ }; &mailbox0_cluster1 { + status = "okay"; + mbox_mcu_r5_0: mbox-mcu-r5-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; }; }; +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + &main_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&main_uart0_tx_pins_default>, <&main_uart0_rx_pins_default>; + pinctrl-1 = <&main_uart0_tx_pins_default>, <&main_uart0_rx_pins_wakeup>; + wakeup-source = <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; status = "okay"; bootph-all; }; @@ -668,3 +876,55 @@ &mcu_gpio_intr { status = "reserved"; }; + +&dss_oldi_io_ctrl { + bootph-all; +}; + +&dss0 { + bootph-all; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_dpi_pins_default>; +}; + +&dss0_ports { + /* DSS0-VP2: DPI/HDMI Output */ + hdmi0_dss: port@1 { + reg = <1>; + + dss0_dpi1_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; + +&epwm0 { + /* Pin 24/26 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm0_pins_default>; + status = "okay"; +}; + +&epwm1 { + /* Pin 23/19 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm1_pins_default>; + status = "okay"; +}; + +&ecap1 { + /* ECAP1 in APWM mode */ + /* Pin 36 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap1_pins_default>; + status = "okay"; +}; + +&ecap2 { + /* ECAP2 in APWM mode */ + /* Pin 11 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap2_pins_default>; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-ecap-capture.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-ecap-capture.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-ecap-capture.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-ecap-capture.dtso 2026-04-21 11:35:28.527915228 +0200 @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for enabling ECAP in capture mode on AM62P5-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + main_ecap1_capture_pins_default: main-ecap1-capture-pins-default { + pinctrl-single,pins = < + AM62PX_IOPAD(0x019c, PIN_INPUT, 2) /* (E24) MCASP0_AXR1.ECAP1_IN_APWM_OUT */ + >; + }; + + main_ecap2_capture_pins_default: main-ecap2-capture-pins-default { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01a4, PIN_INPUT, 2) /* (F24) MCASP0_ACLKX.ECAP2_IN_APWM_OUT */ + >; + }; +}; + +&ecap1 { + /* ECAP in capture mode */ + /* Pin 36 of J4 */ + compatible = "ti,am62-ecap-capture"; + interrupt-parent = <&gic500>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap1_capture_pins_default>; + status = "okay"; +}; + +&ecap2 { + /* ECAP in capture mode */ + /* Pin 11 of J4 */ + compatible = "ti,am62-ecap-capture"; + interrupt-parent = <&gic500>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap2_capture_pins_default>; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-eqep.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-eqep.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-eqep.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-eqep.dtso 2026-04-21 11:35:28.527915228 +0200 @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for enabling EQEP on AM62P5-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + main_eqep0_pins_default: main-eqep0-pins-default { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0194, PIN_INPUT, 8) /* (D25) MCASP0_AXR3.EQEP0_A */ + AM62PX_IOPAD(0x0198, PIN_INPUT, 8) /* (E25) MCASP0_AXR2.EQEP0_B */ + AM62PX_IOPAD(0x01a0, PIN_INPUT, 8) /* (F23) MCASP0_AXR0.EQEP0_I */ + AM62PX_IOPAD(0x019c, PIN_INPUT, 8) /* (E24) MCASP0_AXR1.EQEP0_S */ + >; + }; +}; + +&main_i2c1 { + gpio@22 { + p02-hog { + /* P02 - UART1_FET_SEL */ + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "UART1_FET_SEL"; + }; + }; +}; + +&ecap1 { + /* MCASP0_AXR1 pinmux conflict */ + status = "disabled"; +}; + +&main_uart1 { + /* Disable FW debug logs */ + status = "disabled"; +}; + +&eqep0 { + status = "okay"; + /* A/B on pins 40/38 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_eqep0_pins_default>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-ethfw.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-ethfw.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-ethfw.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-ethfw.dtso 2026-04-21 11:35:28.527915228 +0200 @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for CPSW3G functionality with Ethernet Switch Firmware (EthFw) + * and CPSW Proxy Client driver. + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +/* Mark CPSW3G reserved for EthFw. */ +&cpsw3g { + status = "reserved"; +}; + +/* Reserve shared memory for inter-core network communication. */ +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + + wkup_r5fss0_core0_shared_memory_queue_region:r5f-virtual-eth-queues@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x200000>; + no-map; + }; + + wkup_r5fss0_core0_shared_memory_bufpool_region:r5f-virtual-eth-buffers@a4200000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4200000 0x00 0x1e00000>; + no-map; + }; +}; + +&wkup_r5fss0_core0 { + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>, + <&wkup_r5fss0_core0_shared_memory_queue_region>, + <&wkup_r5fss0_core0_shared_memory_bufpool_region>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-m2-cc3351.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-m2-cc3351.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-m2-cc3351.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-m2-cc3351.dtso 2026-04-21 11:35:28.527915228 +0200 @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * DT Overlay for M.2-CC3351 board to connect to the M.2 connector on AM625-SK. + * + * Product page for board: https://www.ti.com/tool/M2-CC3351 + * CC3351 Datasheet: https://www.ti.com/lit/ds/symlink/cc3351.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&{/} { + wlan_lten: regulator-30 { + compatible = "regulator-fixed"; + regulator-name = "wlan_lten"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_mmc1>; + gpios = <&exp1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wlan_en: regulator-31 { + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&wlan_lten>; + enable-active-high; + gpios = <&main_gpio0 71 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_pins_default>; + }; +}; + +&main_pmx0 { + wlan_en_pins_default: wlan-en-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x124, PIN_OUTPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */ + >; + }; + + main_mmc2_pins_default: main-mmc2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ + AM62X_IOPAD(0x118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ + AM62X_IOPAD(0x114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */ + AM62X_IOPAD(0x110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */ + AM62X_IOPAD(0x10c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */ + AM62X_IOPAD(0x108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */ + AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ + >; + }; + + main_wlirq_pins_default: main-wlirq-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x128, PIN_INPUT, 7) /* (B23) MMC2_SDWP.GPIO0_72 */ + >; + }; +}; + +&sdhci2 { + status = "okay"; + bootph-all; + vmmc-supply = <&wlan_en>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc2_pins_default>; + bus-width = <4>; + non-removable; + ti,fails-without-test-cd; + cap-power-off-card; + keep-power-in-suspend; + ti,driver-strength-ohm = <50>; + + #address-cells = <1>; + #size-cells = <0>; + wifi: cc3300@2 { + compatible = "ti,cc3300"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&main_wlirq_pins_default>; + interrupt-parent = <&main_gpio0>; + interrupts = <72 IRQ_TYPE_EDGE_FALLING>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-mcan.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-mcan.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-mcan.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-mcan.dtso 2026-04-21 11:35:28.527915228 +0200 @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for enabling MCAN for AM62P-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver4: can-phy3 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&main_pmx0 { + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01dc, PIN_INPUT, 0) /* (F20) MCAN0_RX */ + AM62PX_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (B23) MCAN0_TX */ + >; + }; + + main_mcan1_pins_default: main-mcan1-pins-default { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00b4, PIN_INPUT, 5) /* (U25) GPMC0_CSn3.MCAN1_RX */ + AM62PX_IOPAD(0x00b0, PIN_OUTPUT, 5) /* (T22) GPMC0_CSn2.MCAN1_TX */ + >; + }; +}; + +&mcu_pmx0 { + mcu_mcan0_pins_default: mcu-mcan0-pins-default { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (D6) MCU_MCAN0_RX */ + AM62PX_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (E8) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0040, PIN_INPUT, 0) /* (E7) MCU_MCAN1_RX */ + AM62PX_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) /* (F8) MCU_MCAN1_TX */ + >; + }; +}; + +&main_i2c2{ + /* + * main_i2c2 is using (U25) and (T22) + * so disable to use main_mcan1 + */ + status = "disabled"; +}; + +&main_i2c1 { + /* + * Unset GPIO SoC_I2C2_MCAN_SEL to + * route MCAN1 signals to MCAN1 HDR + */ + gpio@23 { + p20-hog { + /* P20 - SoC_I2C2_MCAN_SEL */ + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "SoC_I2C2_MCAN_SEL"; + }; + }; +}; + +&main_mcan0 { + /* RX pin 8 & TX pin 10 of J3 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&main_mcan1 { + /* RX pin 2 & TX pin 1 of J1 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&mcu_mcan0 { + /* RX pin 22 & TX pin 16 of J11 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver3>; +}; + +&mcu_mcan1 { + /* RX pin 11 & TX pin 10 of J11 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver4>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf070zima-lcd3.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf070zima-lcd3.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf070zima-lcd3.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf070zima-lcd3.dtso 2026-04-21 11:35:28.527915228 +0200 @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * Microtips integrated DSI panel (MF-070ZIMACAA0) and touch DT overlay for AM62P5-SK + * + * AM62P5-SK EVM: https://www.ti.com/tool/SK-AM62P-LP + * Panel: https://simplespec.microtipsusa.com/uploads/spec/datasheetFile/3004/13-070ZIMACAA0-S_V1.1_20231120.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&dphy_tx0 { + status = "okay"; +}; + +&dss1 { + status = "okay"; +}; + +&dss1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* DSS1-VP1: DSI Output */ + port@1 { + reg = <1>; + + dss1_dpi1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&dsi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dss1_dpi1_out>; + }; + }; + }; + + dsi_panel0: panel-dsi@0 { + compatible = "microtips,mf-070zimacaa0", "ilitek,ili9881c"; + reg = <0>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + reset-gpios = <&exp1 8 GPIO_ACTIVE_LOW>; + interrupt-parent = <&exp1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf101hie-panel.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf101hie-panel.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf101hie-panel.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf101hie-panel.dtso 2026-04-21 11:35:28.528915230 +0200 @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * Microtips integrated OLDI panel (MF-101HIEBCAF0) and touch DT overlay for AM62P5-SK + * + * Panel datasheet: https://simplespec.microtipsusa.com/uploads/spec/datasheetFile/2588/13-101HIEBCAF0-S_V1.1_20221104.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + display { + compatible = "microtips,mf-101hiebcaf0", "panel-simple"; + + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * Swapping them will cause an error in the dss oldi driver. + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + + lcd_in0: endpoint { + remote-endpoint = <&oldi0_dss0_out>; + }; + }; + + port@1 { + reg = <1>; + dual-lvds-even-pixels; + + lcd_in1: endpoint { + remote-endpoint = <&oldi1_dss0_out>; + }; + }; + }; + }; +}; + +&dss0 { + status = "okay"; +}; + +&oldi0_dss0 { + status = "okay"; + ti,companion-oldi = <&oldi1_dss0>; +}; + +&oldi1_dss0 { + status = "okay"; + ti,secondary-oldi; + ti,companion-oldi = <&oldi0_dss0>; +}; + +&oldi0_dss0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + oldi0_dss0_in: endpoint { + remote-endpoint = <&dss0_dpi0_out0>; + }; + }; + + port@1 { + reg = <1>; + + oldi0_dss0_out: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; +}; + +&oldi1_dss0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + oldi1_dss0_in: endpoint { + remote-endpoint = <&dss0_dpi0_out1>; + }; + }; + + port@1 { + reg = <1>; + + oldi1_dss0_out: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&dss0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: Output to OLDI */ + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dss0_dpi0_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&oldi0_dss0_in>; + }; + + dss0_dpi0_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&oldi1_dss0_in>; + }; + }; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&exp1>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&exp2 20 GPIO_ACTIVE_LOW>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf103hie-lcd2.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf103hie-lcd2.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf103hie-lcd2.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf103hie-lcd2.dtso 2026-04-21 11:35:28.528915230 +0200 @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * Microtips integrated OLDI panel (MF-103HIEB0GA0) (SK-LCD2) DT overlay for AM62PS5-SK + * + * Panel datasheet: https://simplespec.microtipsusa.com/uploads/spec/datasheetFile/2660/13-103HIEB0GA0-S_V1.0_20211206.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + display { + compatible = "microtips,mf-103hieb0ga0", "panel-simple"; + + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * Swapping them will cause an error in the dss oldi driver. + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + + lcd_in0: endpoint { + remote-endpoint = <&oldi0_dss0_out>; + }; + }; + + port@1 { + reg = <1>; + dual-lvds-even-pixels; + + lcd_in1: endpoint { + remote-endpoint = <&oldi1_dss0_out>; + }; + }; + }; + }; +}; + +&dss0 { + status = "okay"; +}; + +&oldi0_dss0 { + status = "okay"; + ti,companion-oldi = <&oldi1_dss0>; +}; + +&oldi1_dss0 { + status = "okay"; + ti,secondary-oldi; + ti,companion-oldi = <&oldi0_dss0>; +}; + +&oldi0_dss0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + oldi0_dss0_in: endpoint { + remote-endpoint = <&dss0_dpi0_out0>; + }; + }; + + port@1 { + reg = <1>; + + oldi0_dss0_out: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; +}; + +&oldi1_dss0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + oldi1_dss0_in: endpoint { + remote-endpoint = <&dss0_dpi0_out1>; + }; + }; + + port@1 { + reg = <1>; + + oldi1_dss0_out: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&dss0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: Output to OLDI */ + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dss0_dpi0_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&oldi0_dss0_in>; + }; + + dss0_dpi0_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&oldi1_dss0_in>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-rpi-hdr-ehrpwm.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-rpi-hdr-ehrpwm.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p5-sk-rpi-hdr-ehrpwm.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p5-sk-rpi-hdr-ehrpwm.dtso 2026-04-21 11:35:28.528915230 +0200 @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling RPi header with GPIOs and ePWMs on AM62P-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0038, PIN_INPUT, 7) /* (L23) OSPI0_CSn3.GPIO0_14 */ + AM62PX_IOPAD(0x0088, PIN_INPUT, 7) /* (R24) GPMC0_OEn_REn.GPIO0_33 */ + AM62PX_IOPAD(0x0094, PIN_INPUT, 7) /* (T24) GPMC0_BE1n.GPIO0_36 */ + AM62PX_IOPAD(0x009c, PIN_INPUT, 7) /* (AD24) GPMC0_WAIT1.GPIO0_38 */ + AM62PX_IOPAD(0x00a0, PIN_INPUT, 7) /* (P24) GPMC0_WPn.GPIO0_39 */ + AM62PX_IOPAD(0x00a4, PIN_INPUT, 7) /* (P25) GPMC0_DIR.GPIO0_40 */ + AM62PX_IOPAD(0x00a8, PIN_INPUT, 7) /* (T23) GPMC0_CSn0.GPIO0_41 */ + AM62PX_IOPAD(0x00ac, PIN_INPUT, 7) /* (U23) GPMC0_CSn1.GPIO0_42 */ + >; + }; + + rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01a4, PIN_INPUT, 7) /* (F24) MCASP0_ACLKX.GPIO1_11 */ + AM62PX_IOPAD(0x01c4, PIN_INPUT, 7) /* (C21) SPI0_D1.GPIO1_19 */ + AM62PX_IOPAD(0x01d0, PIN_INPUT, 7) /* (A23) UART0_CTSn.GPIO1_22 */ + AM62PX_IOPAD(0x01d8, PIN_INPUT, 7) /* (B23) MCAN0_TX.GPIO1_24 */ + AM62PX_IOPAD(0x01dc, PIN_INPUT, 7) /* (F20) MCAN0_RX.GPIO1_25 */ + >; + }; + + rpi_header_ehrpwm0_pins_default: rpi-header-ehrpwm0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (D20) SPI0_CS0.EHRPWM0_A */ + AM62PX_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (E20) SPI0_CS1.EHRPWM0_B */ + >; + }; + + rpi_header_ehrpwm1_pins_default: rpi-header-ehrpwm1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 2) /* (B21) SPI0_CLK.EHRPWM1_A */ + AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 2) /* (B20) SPI0_D0.EHRPWM1_B */ + >; + }; +}; + +&main_i2c1 { + gpio@22 { + p02-hog { + /* P02 - UART1_FET_SEL */ + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "UART1_FET_SEL"; + }; + + p05-hog { + /* P05 - EXP_PS_3V3_EN */ + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_3V3_EN"; + }; + }; + + gpio@23 { + p01-hog { + /* P01 - EXP_PS_5V0_EN */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_5V0_EN"; + }; + }; +}; + +&dss0 { + /* Conflict with GPIO0_38 */ + status = "disabled"; +}; + +&main_uart1 { + /* Confict with epwm1 */ + status = "disabled"; +}; + +&ecap2 { + /* Confict with GPIO1_11 */ + status = "disabled"; +}; + +&epwm0 { + /* Pin 24/26 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm0_pins_default>; + status = "okay"; +}; + +&epwm1 { + /* Pin 23/19 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm1_pins_default>; + status = "okay"; +}; + +&main_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; + +&main_gpio1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio1_pins_default>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62p.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p.dtsi 2026-04-21 11:35:28.526915225 +0200 @@ -44,6 +44,33 @@ interrupts = ; }; + system-idle-states { + system_partial_io: system-partial-io { + compatible = "system-idle-state"; + idle-state-name = "off-wake"; + }; + + system_io_ddr: system-io-ddr { + compatible = "system-idle-state"; + idle-state-name = "mem-deep"; + }; + + system_deep_sleep: system-deep-sleep { + compatible = "system-idle-state"; + idle-state-name = "mem"; + }; + + system_mcu_only: system-mcu-only { + compatible = "system-idle-state"; + idle-state-name = "mem-mcu-active"; + }; + + system_standby: system-standby { + compatible = "system-idle-state"; + idle-state-name = "standby"; + }; + }; + cbass_main: bus@f0000 { compatible = "simple-bus"; #address-cells = <2>; @@ -59,12 +86,17 @@ <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ - <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ + <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */ <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ + <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ + <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */ + <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI Wrapper */ + <0x00 0x30300000 0x00 0x30300000 0x00 0x00001000>, /* MCRC64 */ + <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI Config */ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ @@ -116,6 +148,22 @@ }; }; + dss0_vp1_clk: clock-divider-oldi-dss0 { + compatible = "fixed-factor-clock"; + clocks = <&k3_clks 186 0>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + }; + + dss1_vp1_clk: clock-divider-oldi-dss1 { + compatible = "fixed-factor-clock"; + clocks = <&k3_clks 232 0>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + }; + #include "k3-am62p-j722s-common-thermal.dtsi" }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi 2026-04-21 11:35:28.510915183 +0200 @@ -45,6 +45,18 @@ pmsg-size = <0x8000>; }; + mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@9cc00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; @@ -83,6 +95,16 @@ regulator-boot-on; }; + vddshv_3v3: regulator-vddshv-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDSHV0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + regulator-boot-on; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -173,6 +195,13 @@ }; }; +&a53_opp_table { + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + }; +}; + &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>; @@ -196,6 +225,13 @@ }; }; +&mailbox0_cluster0 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; @@ -226,8 +262,8 @@ regulators { vdd_core: buck1 { regulator-name = "VDD_CORE"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; regulator-boot-on; regulator-always-on; }; @@ -287,6 +323,7 @@ compatible = "atmel,24c32"; pagesize = <32>; reg = <0x50>; + vcc-supply = <&vddshv_3v3>; }; i2c_som_rtc: rtc@52 { @@ -295,6 +332,13 @@ }; }; +&mcu_m4fss { + mboxes = <&mailbox0_cluster0 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi 2026-04-21 11:35:28.526915225 +0200 @@ -50,6 +50,7 @@ compatible = "ti,am654-phy-gmii-sel"; reg = <0x4044 0x8>; #phy-cells = <1>; + bootph-all; }; epwm_tbclk: clock-controller@4130 { @@ -57,6 +58,16 @@ reg = <0x4130 0x4>; #clock-cells = <1>; }; + + dss_clk_ctrl: dss_clk_ctrl@8300 { + compatible = "ti,am625-dss-clk-ctrl", "syscon"; + reg = <0x8300 0x4>; + }; + + dss_oldi_io_ctrl: dss-oldi-io-ctrl@8600 { + compatible = "syscon"; + reg = <0x8600 0x200>; + }; }; dmss: bus@48000000 { @@ -232,6 +243,13 @@ dma-names = "tx", "rx1", "rx2"; }; + crc: crc@30300000 { + compatible = "ti,am62-mcrc64"; + reg = <0x00 0x30300000 0x00 0x1000>; + clocks = <&k3_clks 116 0>; + power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; + }; + secure_proxy_sa3: mailbox@43600000 { compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; @@ -569,7 +587,7 @@ mmc-hs200-1_8v; mmc-hs400-1_8v; ti,clkbuf-sel = <0x7>; - ti,strobe-sel = <0x77>; + ti,strobe-sel = <0x66>; ti,trm-icp = <0x8>; ti,otap-del-sel-legacy = <0x1>; ti,otap-del-sel-mmc-hs = <0x1>; @@ -649,6 +667,7 @@ interrupt-names = "host", "peripheral"; maximum-speed = "high-speed"; dr_mode = "otg"; + bootph-all; snps,usb2-gadget-lpm-disable; snps,usb2-lpm-disable; }; @@ -669,6 +688,7 @@ cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; + cdns,phase-detect-selector = <0>; clocks = <&k3_clks 75 7>; assigned-clocks = <&k3_clks 75 7>; assigned-clock-parents = <&k3_clks 75 8>; @@ -718,6 +738,7 @@ mac-address = [00 00 00 00 00 00]; ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; status = "disabled"; + bootph-all; }; cpsw_port2: port@2 { @@ -739,6 +760,7 @@ clock-names = "fck"; bus_freq = <1000000>; status = "disabled"; + bootph-all; }; cpts@3d000 { @@ -753,12 +775,32 @@ }; }; + gpu: gpu@fd80000 { + compatible = "ti,am62p-pvr", "img,pvr-bxs64"; + reg = <0x00 0x0fd80000 0x00 0x80000>; + interrupts = ; + power-domains = <&k3_pds 237 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 237 3>; + assigned-clock-rates = <800000000>; + power-domain-names = "firmware", "dust"; + clocks = <&k3_clks 237 3>; + clock-names = "core"; + }; + hwspinlock: spinlock@2a000000 { compatible = "ti,am64-hwspinlock"; reg = <0x00 0x2a000000 0x00 0x1000>; #hwlock-cells = <1>; }; + timesync_router: mux-controller@a40000 { + compatible = "reg-mux"; + reg = <0x0 0xa40000 0x0 0x800>; + #mux-control-cells = <1>; + status = "disabled"; + }; + mailbox0_cluster0: mailbox@29000000 { compatible = "ti,am64-mailbox"; reg = <0x00 0x29000000 0x00 0x200>; @@ -766,6 +808,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster1: mailbox@29010000 { @@ -775,6 +818,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster2: mailbox@29020000 { @@ -784,6 +828,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster3: mailbox@29030000 { @@ -793,6 +838,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; ecap0: pwm@23100000 { @@ -825,6 +871,33 @@ status = "disabled"; }; + eqep0: counter@23200000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23200000 0x00 0x100>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 59 0>; + interrupts = ; + status = "disabled"; + }; + + eqep1: counter@23210000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23210000 0x00 0x100>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 60 0>; + interrupts = ; + status = "disabled"; + }; + + eqep2: counter@23220000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23220000 0x00 0x100>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 62 0>; + interrupts = ; + status = "disabled"; + }; + main_mcan0: can@20701000 { compatible = "bosch,m_can"; reg = <0x00 0x20701000 0x00 0x200>, @@ -996,14 +1069,19 @@ ranges; #address-cells = <2>; #size-cells = <2>; - dmas = <&main_bcdma_csi 0 0x5000 0>; - dma-names = "rx0"; + dmas = <&main_bcdma_csi 0 0x5000 0>, <&main_bcdma_csi 0 0x5001 0>, + <&main_bcdma_csi 0 0x5002 0>, <&main_bcdma_csi 0 0x5003 0>, + <&main_bcdma_csi 0 0x5004 0>, <&main_bcdma_csi 0 0x5005 0>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5"; power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; cdns_csi2rx0: csi-bridge@30101000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30101000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -1051,11 +1129,186 @@ status = "disabled"; }; + dphy0: phy@30110000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30110000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dss0: dss@30200000 { + compatible = "ti,am62p51-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2", "common1"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>, /* DSS0 */ + <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>, /* OLDI0 */ + <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; /* OLDI1 */ + clocks = <&k3_clks 186 6>, + <&dss0_vp1_clk>, + <&k3_clks 186 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = ; + ti,clk-ctrl = <&dss_clk_ctrl>; + status = "disabled"; + + oldi-transmitters { + #address-cells = <1>; + #size-cells = <0>; + + oldi0_dss0: oldi@0 { + reg = <0>; + clocks = <&k3_clks 186 0>; + clock-names = "serial"; + ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; + status = "disabled"; + + oldi0_dss0_ports: ports { + }; + }; + + oldi1_dss0: oldi@1 { + reg = <1>; + status = "disabled"; + + oldi1_dss0_ports: ports { + }; + }; + }; + + dss0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + dss1: dss@30220000 { + compatible = "ti,am62p52-dss"; + reg = <0x00 0x30220000 0x00 0x1000>, /* common */ + <0x00 0x30222000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30226000 0x00 0x1000>, /* vid */ + <0x00 0x30227000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30228000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3022a000 0x00 0x1000>, /* vp1: Used for OLDI */ + <0x00 0x3022b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30221000 0x00 0x1000>; /* common1 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2", "common1"; + power-domains = <&k3_pds 232 TI_SCI_PD_EXCLUSIVE>, /* DSS0 */ + <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; /* OLDI1 */ + clocks = <&k3_clks 232 8>, + <&dss1_vp1_clk>, + <&k3_clks 232 4>; + clock-names = "fck", "vp1", "vp2"; + interrupts = ; + ti,clk-ctrl = <&dss_clk_ctrl>; + status = "disabled"; + + oldi-transmitters { + #address-cells = <1>; + #size-cells = <0>; + + oldi1_dss1: oldi@1 { + reg = <1>; + clocks = <&k3_clks 232 0>; + clock-names = "serial"; + ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; + status = "disabled"; + + oldi1_dss1_ports: ports { + }; + }; + }; + + dss1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + dphy_tx0: phy@301c0000 { + compatible = "ti,j721e-dphy"; + reg = <0x0 0x301c0000 0x0 0x1000>; + clocks = <&k3_clks 238 16>, <&k3_clks 238 1>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 238 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 238 1>; + assigned-clock-parents = <&k3_clks 238 2>; + assigned-clock-rates = <25000000>; + status = "disabled"; + }; + + dsi0: dsi@30500000 { + compatible = "ti,j721e-dsi"; + reg = <0x0 0x30500000 0x0 0x100000>, <0x0 0x30270000 0x0 0x100>; + clocks = <&k3_clks 231 2>, <&k3_clks 231 5>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 231 TI_SCI_PD_EXCLUSIVE>; + interrupt-parent = <&gic500>; + interrupts = ; + phys = <&dphy_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + vpu: video-codec@30210000 { compatible = "ti,j721s2-wave521c", "cnm,wave521c"; reg = <0x00 0x30210000 0x00 0x10000>; interrupts = ; clocks = <&k3_clks 204 2>; power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; + sram = <&oc_sram>; + operating-points-v2 = <&vpu_opp_table>; + vpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-20000000 { + opp-hz = /bits/ 64 <20000000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + }; + }; + }; + + memorycontroller: memory-controller@f300000 { + compatible = "ti,am62a-ddrss"; + reg = <0x00 0x0f300000 0x00 0x200>; + reg-names = "ss_cfg"; + ranges = <0x00 0x00 0x00 0x0f308000 0x00 0x5e10>; + interrupts = ; + power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 170 0>; + #address-cells = <2>; + #size-cells = <2>; + + ddr: ddr@0 { + compatible = "cdns,j7-ddr"; + reg = <0x00 0x0000 0x00 0x6cc>, + <0x00 0x2000 0x00 0x6a0>, + <0x00 0x4000 0x00 0x1e10>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + }; }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi 2026-04-21 11:35:28.526915225 +0200 @@ -6,21 +6,25 @@ */ &cbass_mcu { + mcu_ram: sram@79100000 { + compatible = "mmio-sram"; + reg = <0x00 0x79100000 0x00 0x80000>; + ranges = <0x00 0x00 0x79100000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + + mcu_sram1@0 { + reg = <0x0 0x80000>; + }; + }; + mcu_pmx0: pinctrl@4084000 { compatible = "pinctrl-single"; reg = <0x00 0x04084000 0x00 0x88>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; - pinctrl-single,gpio-range = - <&mcu_pmx_range 0 21 PIN_GPIO_RANGE_IOPAD>, - <&mcu_pmx_range 23 1 PIN_GPIO_RANGE_IOPAD>, - <&mcu_pmx_range 32 2 PIN_GPIO_RANGE_IOPAD>; bootph-all; - - mcu_pmx_range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; }; mcu_esm: esm@4100000 { @@ -213,6 +217,7 @@ ti,atcm-enable = <0>; ti,btcm-enable = <1>; ti,loczrama = <0>; + sram = <&mcu_ram>; }; }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi 2026-04-21 11:35:28.526915225 +0200 @@ -5,6 +5,8 @@ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ +#include + &cbass_wakeup { wkup_conf: bus@43000000 { compatible = "simple-bus"; @@ -16,10 +18,16 @@ chipid: chipid@14 { compatible = "ti,am654-chipid"; - reg = <0x14 0x4>; + reg = <0x14 0x4>, + <0x230 0x10>; bootph-all; }; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; reg = <0x200 0x8>; @@ -34,16 +42,46 @@ compatible = "ti,am62-usb-phy-ctrl", "syscon"; reg = <0x4018 0x4>; }; + + ddr_pmctrl: syscon@80d0 { + compatible = "ti,am62-ddr-pmctrl", "syscon"; + reg = <0x80d0 0x4>; + }; + + canuart_wake: syscon@18300 { + compatible = "ti,am62-canuart-wake", "syscon"; + reg = <0x18300 0x44>; + }; }; - wkup_uart0: serial@2b300000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x2b300000 0x00 0x100>; - interrupts = ; + target-module@2b300050 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0 0x2b300050 0 0x4>, + <0 0x2b300054 0 0x4>, + <0 0x2b300058 0 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + ti,no-reset-on-init; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; - clock-names = "fclk"; - status = "disabled"; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2b300000 0x100000>; + + wkup_uart0: serial@0 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0 0x100>; + interrupts = ; + status = "disabled"; + }; }; wkup_i2c0: i2c@2b200000 { diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi 2026-04-21 11:35:28.526915225 +0200 @@ -42,20 +42,6 @@ ti,interrupt-ranges = <5 69 35>; }; -&main_pmx0 { - pinctrl-single,gpio-range = - <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 72 22 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>; - - main_pmx0_range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; -}; - &main_gpio0 { gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>, <&main_pmx0 70 72 22>; @@ -68,3 +54,20 @@ gpio-reserved-ranges = <32 10>; ti,ngpio = <52>; }; + +&main_pmx0 { + compatible = "ti,am654-padconf", "pinctrl-single"; + /* + * pinctrl IP DOES NOT give any functional IRQs when a + * system is in active state. This IRQ is only a dummy IRQ + * that is being used to trick Linux into thinking that + * GIC can potentially recieve an interrupt from this IP. + * This helps us setup the IO daisychain wakeups for deep + * sleep via chained wake IRQs. + * Please feel free to assign a different number here as + * long as it is unused if 98 conflicts with another use case. + */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi 2026-04-21 11:35:28.512915189 +0200 @@ -1131,6 +1131,11 @@ }; }; + tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; + pmic@30 { compatible = "ti,tps65219"; reg = <0x30>; @@ -1219,11 +1224,12 @@ reg = <0x48>; }; - adc@49 { - compatible = "ti,ads1015"; + verdin_som_adc: adc@49 { + compatible = "ti,tla2024"; reg = <0x49>; #address-cells = <1>; #size-cells = <0>; + #io-channel-cells = <1>; /* Verdin PMIC_I2C (ADC_4 - ADC_3) */ channel@0 { diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi 2026-04-21 11:35:28.510915183 +0200 @@ -0,0 +1,655 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + * + * Common dtsi for Verdin AM62 SoM on Ivy carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/ivy-carrier-board + */ + +#include +#include +#include + +/ { + /* AIN1 Voltage w/o AIN1_MODE gpio control */ + ain1_voltage_unmanaged: voltage-divider-ain1 { + compatible = "voltage-divider"; + #io-channel-cells = <1>; + io-channels = <&ivy_adc1 0>; + full-ohms = <19>; + output-ohms = <1>; + }; + + /* AIN1 Current w/o AIN1_MODE gpio control */ + ain1_current_unmanaged: current-sense-shunt-ain1 { + compatible = "current-sense-shunt"; + #io-channel-cells = <0>; + io-channels = <&ivy_adc1 1>; + shunt-resistor-micro-ohms = <100000000>; + }; + + /* AIN1_MODE - SODIMM 216 */ + ain1_mode_mux_ctrl: mux-controller-0 { + compatible = "gpio-mux"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_5>; + #mux-control-cells = <0>; + mux-gpios = <&main_gpio0 40 GPIO_ACTIVE_HIGH>; + }; + + ain1-voltage { + compatible = "io-channel-mux"; + channels = "ain1_voltage", ""; + io-channels = <&ain1_voltage_unmanaged 0>; + io-channel-names = "parent"; + mux-controls = <&ain1_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + ain1-current { + compatible = "io-channel-mux"; + channels = "", "ain1_current"; + io-channels = <&ain1_current_unmanaged>; + io-channel-names = "parent"; + mux-controls = <&ain1_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + /* AIN2 Voltage w/o AIN2_MODE gpio control */ + ain2_voltage_unmanaged: voltage-divider-ain2 { + compatible = "voltage-divider"; + #io-channel-cells = <1>; + io-channels = <&ivy_adc2 0>; + full-ohms = <19>; + output-ohms = <1>; + }; + + /* AIN2 Current w/o AIN2_MODE gpio control */ + ain2_current_unmanaged: current-sense-shunt-ain2 { + compatible = "current-sense-shunt"; + #io-channel-cells = <0>; + io-channels = <&ivy_adc2 1>; + shunt-resistor-micro-ohms = <100000000>; + }; + + /* AIN2_MODE - SODIMM 218 */ + ain2_mode_mux_ctrl: mux-controller-1 { + compatible = "gpio-mux"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_6>; + #mux-control-cells = <0>; + mux-gpios = <&main_gpio0 36 GPIO_ACTIVE_HIGH>; + }; + + ain2-voltage { + compatible = "io-channel-mux"; + channels = "ain2_voltage", ""; + io-channels = <&ain2_voltage_unmanaged 0>; + io-channel-names = "parent"; + mux-controls = <&ain2_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + ain2-current { + compatible = "io-channel-mux"; + channels = "", "ain2_current"; + io-channels = <&ain2_current_unmanaged>; + io-channel-names = "parent"; + mux-controls = <&ain2_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ivy_leds>; + + /* D7 Blue - SODIMM 30 - LEDs.GPIO1 */ + led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&main_gpio1 11 GPIO_ACTIVE_HIGH>; + }; + + /* D7 Green - SODIMM 32 - LEDs.GPIO2 */ + led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&main_gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + /* D7 Red - SODIMM 34 - LEDs.GPIO3 */ + led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&main_gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + /* D8 Blue - SODIMM 36 - LEDs.GPIO4 */ + led-3 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + gpios = <&main_gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + /* D8 Green - SODIMM 54 - LEDs.GPIO5 */ + led-4 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + gpios = <&main_gpio0 11 GPIO_ACTIVE_HIGH>; + }; + + /* D8 Red - SODIMM 44 - LEDs.GPIO6 */ + led-5 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + gpios = <&main_gpio0 37 GPIO_ACTIVE_HIGH>; + }; + + /* D9 Blue - SODIMM 46 - LEDs.GPIO7 */ + led-6 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>; + }; + + /* D9 Red - SODIMM 48 - LEDs.GPIO8 */ + led-7 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&main_gpio0 33 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_3v2_ain1: regulator-3v2-ain1 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3200000>; + regulator-min-microvolt = <3200000>; + regulator-name = "+3V2_AIN1"; + }; + + reg_3v2_ain2: regulator-3v2-ain2 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3200000>; + regulator-min-microvolt = <3200000>; + regulator-name = "+3V2_AIN2"; + }; + + /* Ivy Power Supply Input Voltage */ + ivy-input-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_1 */ + io-channels = <&verdin_som_adc 7>; + full-ohms = <204700>; /* 200K + 4.7K */ + output-ohms = <4700>; + }; + + ivy-5v-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_2 */ + io-channels = <&verdin_som_adc 6>; + full-ohms = <39000>; /* 27K + 12K */ + output-ohms = <12000>; + }; + + ivy-3v3-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_3 */ + io-channels = <&verdin_som_adc 5>; + full-ohms = <54000>; /* 27K + 27K */ + output-ohms = <27000>; + }; + + ivy-1v8-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_4 */ + io-channels = <&verdin_som_adc 4>; + full-ohms = <39000>; /* 12K + 27K */ + output-ohms = <27000>; + }; +}; + +&main_pmx0 { + pinctrl_ivy_leds: ivy-leds-default-pins { + pinctrl-single,pins = + , /* (B18) MCASP0_AXR1.GPIO1_9 */ /* SODIMM 36 */ + , /* (B20) MCASP0_AXR0.GPIO1_10 */ /* SODIMM 34 */ + , /* (A19) MCASP0_ACLKX.GPIO1_11 */ /* SODIMM 30 */ + , /* (A20) MCASP0_AFSX.GPIO1_12 */ /* SODIMM 32 */ + , /* (L17) GPMC0_OEn_REn.GPIO0_33 */ /* SODIMM 48 */ + , /* (R18) GPMC0_WAIT0.GPIO0_37 */ /* SODIMM 44 */ + , /* (L25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */ + ; /* (F23) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */ + }; +}; + +/* Verdin ETH */ +&cpsw3g { + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; + + cpsw3g_phy1: ethernet-phy@2 { + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + interrupt-parent = <&main_gpio0>; + interrupts = <38 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + }; +}; + +/* Verdin ETH_1*/ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + phy-handle = <&cpsw3g_phy1>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>, + <&pinctrl_qspi1_cs2_gpio>, + <&pinctrl_qspi1_io0_gpio>, + <&pinctrl_qspi1_io1_gpio>, + <&pinctrl_qspi1_io2_gpio>, + <&pinctrl_qspi1_io3_gpio>; + gpio-line-names = + "", /* 0 */ + "", + "", + "DIGI_1", /* SODIMM 56 */ + "DIGI_2", /* SODIMM 58 */ + "REL1", /* SODIMM 60 */ + "REL2", /* SODIMM 62 */ + "", + "", + "", + "", /* 10 */ + "", + "REL3", /* SODIMM 64 */ + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 30 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 40 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 50 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 60 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 70 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 80 */ + "", + "", + "", + "", + "", + ""; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>; + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "REL4", /* SODIMM 66 */ + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 30 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 40 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 50 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 60 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 70 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 80 */ + "", + "", + "", + "", + "", + "", + ""; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + status = "okay"; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_4 CSI */ +&main_i2c3 { + status = "okay"; + + ivy_adc1: adc@40 { + compatible = "ti,ads1119"; + reg = <0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_7>; + interrupt-parent = <&main_gpio0>; + interrupts = <41 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <®_3v2_ain1>; + dvdd-supply = <®_3v2_ain1>; + vref-supply = <®_3v2_ain1>; + #address-cells = <1>; + #io-channel-cells = <1>; + #size-cells = <0>; + + /* AIN1 0-33V Voltage Input */ + channel@0 { + reg = <0>; + diff-channels = <0 1>; + }; + + /* AIN1 0-20mA Current Input */ + channel@1 { + reg = <1>; + diff-channels = <2 3>; + }; + }; + + ivy_adc2: adc@41 { + compatible = "ti,ads1119"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_8>; + interrupt-parent = <&main_gpio0>; + interrupts = <42 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <®_3v2_ain2>; + dvdd-supply = <®_3v2_ain2>; + vref-supply = <®_3v2_ain2>; + #address-cells = <1>; + #io-channel-cells = <1>; + #size-cells = <0>; + + /* AIN2 0-33V Voltage Input */ + channel@0 { + reg = <0>; + diff-channels = <0 1>; + }; + + /* AIN2 0-20mA Current Input */ + channel@1 { + reg = <1>; + diff-channels = <2 3>; + }; + }; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + pinctrl-0 = <&pinctrl_spi1>, + <&pinctrl_spi1_cs0>, + <&pinctrl_gpio_1>, + <&pinctrl_gpio_4>; + cs-gpios = <0>, + <&mcu_gpio0 1 GPIO_ACTIVE_LOW>, + <&mcu_gpio0 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <18500000>; + }; + + fram@2 { + compatible = "fujitsu,mb85rs256", "atmel,at25"; + reg = <2>; + address-width = <16>; + size = <32768>; + spi-max-frequency = <33000000>; + pagesize = <1>; + }; +}; + +/* Verdin UART_3 */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_pcie_1_reset>; + gpio-line-names = + "", + "", + "GPIO2", /* Verdin GPIO_2 - SODIMM 208 */ + "GPIO3", /* Verdin GPIO_3 - SODIMM 210 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + +/* Verdin CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + status = "okay"; +}; + +/* Verdin USB_1*/ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi 2026-04-21 11:35:28.512915189 +0200 @@ -8,9 +8,9 @@ #include &cbass_wakeup { - wkup_conf: syscon@43000000 { + wkup_conf: bus@43000000 { bootph-all; - compatible = "syscon", "simple-mfd"; + compatible = "simple-bus"; reg = <0x00 0x43000000 0x00 0x20000>; #address-cells = <1>; #size-cells = <1>; @@ -22,6 +22,11 @@ reg = <0x14 0x4>; }; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; reg = <0x200 0x8>; @@ -101,6 +106,31 @@ status = "reserved"; }; + wkup_r5fss0: r5fss@78000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + wkup_r5fss0_core0: r5f@78000000 { + compatible = "ti,am62-r5f"; + reg = <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <121>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 121 1>; + firmware-name = "am62-wkup-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + wkup_vtm0: temperature-sensor@b00000 { compatible = "ti,j7200-vtm"; reg = <0x00 0xb00000 0x00 0x400>, diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi 2026-04-21 11:35:28.529915233 +0200 @@ -82,8 +82,8 @@ }; sound_master: simple-audio-card,codec { - sound-dai = <&audio_codec>; - clocks = <&audio_refclk1>; + sound-dai = <&audio_codec>; + clocks = <&audio_refclk1>; }; }; @@ -112,6 +112,25 @@ regulator-boot-on; }; + vcc_3v3_hdmi: regulator-vcc-3v3-hdmi { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_HDMI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_sw>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_1v2_hdmi: regulator-vcc-1v2-hdmi { + compatible = "regulator-fixed"; + regulator-name = "HDMI_CVCC"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + vcc_3v3_mmc: regulator-vcc-3v3-mmc { compatible = "regulator-fixed"; regulator-name = "VCC_3V3_MMC"; @@ -367,6 +386,9 @@ pinctrl-names = "default"; pinctrl-0 = <&hdmi_int_pins_default>; + iovcc-supply = <&vcc_3v3_hdmi>; + cvcc12-supply = <&vcc_1v2_hdmi>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -376,6 +398,7 @@ sii9022_in: endpoint { remote-endpoint = <&dpi1_out>; + bus-width = <16>; }; }; @@ -393,6 +416,7 @@ compatible = "atmel,24c02"; pagesize = <16>; reg = <0x51>; + vcc-supply = <&vcc_3v3_mmc>; }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi 2026-04-21 11:35:28.529915233 +0200 @@ -8,10 +8,11 @@ #include #include #include -#include "k3-am625.dtsi" / { aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart0; mmc0 = &sdhci0; mmc1 = &sdhci1; @@ -24,14 +25,21 @@ }; chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + stdout-path = "serial2:115200n8"; - }; - memory@80000000 { - bootph-pre-ram; - device_type = "memory"; - /* 2G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + framebuffer0: framebuffer@0 { + compatible = "simple-framebuffer"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&dss_vp1_clk>, + <&k3_clks 186 2>; + display = <&dss>; + status = "disabled"; + }; }; reserved-memory { @@ -39,9 +47,9 @@ #size-cells = <2>; ranges; - ramoops@9ca00000 { + ramoops@9c700000 { compatible = "ramoops"; - reg = <0x00 0x9ca00000 0x00 0x00100000>; + reg = <0x00 0x9c700000 0x00 0x00100000>; record-size = <0x8000>; console-size = <0x8000>; ftrace-size = <0x00>; @@ -56,6 +64,36 @@ linux,cma-default; }; + rtos_ipc_memory_region: ipc-memories@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x00300000>; + no-map; + }; + + mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@9cc00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; @@ -68,11 +106,50 @@ no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9db00000 0x00 0xc00000>; - no-map; - }; + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_5v0: regulator-1 { + /* Output of LM34936 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: regulator-2 { + /* output of LM61460-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-3 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_sys>; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; }; leds { @@ -142,14 +219,26 @@ &main_pmx0 { /* First pad number is ALW package and second is AMC package */ - main_uart0_pins_default: main-uart0-default-pins { + main_uart0_tx_pins_default: main-uart0-tx-default-pins { bootph-all; pinctrl-single,pins = < - AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ >; }; + main_uart0_rx_pins_default: main-uart0-rx-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */ + >; + }; + + main_uart0_rx_pins_wakeup: main-uart0-rx-wakeup-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT | PIN_WKUP_EN, 0) /* (D14/A13) UART0_RXD */ + >; + }; + main_uart1_pins_default: main-uart1-default-pins { bootph-pre-ram; pinctrl-single,pins = < @@ -228,7 +317,7 @@ main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < - AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ + AM62X_IOPAD(0x0258, PIN_OUTPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (F18/E16) USB1_DRVVBUS */ >; }; @@ -273,6 +362,30 @@ AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ >; }; + + ospi0_pins_default: ospi0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24/G19) OSPI0_CLK */ + AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23/F19) OSPI0_CSn0 */ + AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25/F18) OSPI0_D0 */ + AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24/G17) OSPI0_D1 */ + AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25/F21) OSPI0_D2 */ + AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24/F20) OSPI0_D3 */ + AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23/G21) OSPI0_D4 */ + AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25/H21) OSPI0_D5 */ + AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25/G20) OSPI0_D6 */ + AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22/J21) OSPI0_D7 */ + AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24/H20) OSPI0_DQS */ + >; + }; + + pruss_uart_pins: pruss-uart-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d8, PIN_INPUT, 6) /* (C15) MCAN0_TX.PR0_UART0_RXD */ + AM62X_IOPAD(0x01dc, PIN_OUTPUT, 6) /* (E15) MCAN0_RX.PR0_UART0_TXD */ + >; + }; }; &mcu_pmx0 { @@ -287,6 +400,10 @@ }; }; +&cpsw_mac_syscon { + bootph-all; +}; + &wkup_uart0 { /* WKUP UART0 is used by DM firmware */ bootph-pre-ram; @@ -298,8 +415,12 @@ &main_uart0 { bootph-all; status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&main_uart0_tx_pins_default>, <&main_uart0_rx_pins_default>; + pinctrl-1 = <&main_uart0_tx_pins_default>, <&main_uart0_rx_pins_wakeup>; + wakeup-source = <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; }; &main_uart1 { @@ -438,6 +559,28 @@ ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; }; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mcu_m4fss { + mboxes = <&mailbox0_cluster0 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; }; &usbss0 { @@ -462,6 +605,10 @@ }; }; +&usb0_phy_ctrl { + bootph-all; +}; + &usb1 { dr_mode = "host"; pinctrl-names = "default"; @@ -486,7 +633,12 @@ >; }; +&dss_oldi_io_ctrl { + bootph-all; +}; + &dss { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_dss0_pins_default>; @@ -494,7 +646,7 @@ &dss_ports { /* VP2: DPI Output */ - port@1 { + hdmi0_dss: port@1 { reg = <1>; dpi1_out: endpoint { @@ -511,3 +663,16 @@ &mcu_gpio_intr { status = "reserved"; }; + +&ospi0 { + bootph-all; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; +}; + +&pruss_uart { + pinctrl-names = "default"; + pinctrl-0 = <&pruss_uart_pins>; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-v3link-fusion.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-v3link-fusion.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-v3link-fusion.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-v3link-fusion.dtso 2026-04-21 11:35:28.530915236 +0200 @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Arducam V3Link UC-A09 board + * https://www.arducam.com/fpd-link-3-cameras/ + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-dmtimer-pwm.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-dmtimer-pwm.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-dmtimer-pwm.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-dmtimer-pwm.dtso 2026-04-21 11:35:28.530915236 +0200 @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay to enable DM timer in PWM mode on AM625-SK, AM62 LP-SK, and AM62A7-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + leds { + compatible = "pwm-leds"; + pinctrl-names; + pinctrl-0; + + led-0 { + pwms = <&main_pwm7 0 7812500 0>; + max-brightness = <255>; + }; + }; + + main_pwm7: dmtimer-main-pwm-7 { + compatible = "ti,omap-dmtimer-pwm"; + #pwm-cells = <3>; + ti,timers = <&main_timer7>; + pinctrl-0 = <&usr_led_pins_default>; + pinctrl-names = "default"; + }; + + main_pwm3: dmtimer-main-pwm-3 { + /* dmtimer PWM output */ + /* Pin 8 of J3 */ + compatible = "ti,omap-dmtimer-pwm"; + #pwm-cells = <3>; + ti,timers = <&main_timer3>; + pinctrl-names = "default"; + pinctrl-0 = <&main_timer3_pins_default>; + }; +}; + +&main_pmx0 { + usr_led_pins_default: usr-led-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x244, PIN_OUTPUT, 2) /* (C17) MMC1_SDWP.TIMER_IO7 */ + >; + }; + + main_timer3_pins_default: main_timer3-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01dc, PIN_OUTPUT, 2) /* (A15) MCAN0_RX.TIMER_IO3 */ + >; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-ecap-capture.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-ecap-capture.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-ecap-capture.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-ecap-capture.dtso 2026-04-21 11:35:28.530915236 +0200 @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for enabling ECAP in capture mode for AM625-SK, AM62 LP-SK, and AM62A7-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + main_ecap2_capture_pins_default: main-ecap2-capture-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01a4, PIN_INPUT, 2) /* (B20) MCASP0_ACLKX.ECAP2_IN_APWM_OUT */ + >; + }; +}; + +&ecap2 { + /* ECAP in capture mode */ + /* P11 on J3 */ + compatible = "ti,am62-ecap-capture"; + interrupt-parent = <&gic500>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap2_capture_pins_default>; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-eqep.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-eqep.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-eqep.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-eqep.dtso 2026-04-21 11:35:28.530915236 +0200 @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for enabling EQEP on AM625-SK, AM62 LP-SK, and AM62A7-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + main_eqep0_pins_default: main-eqep0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0194, PIN_INPUT, 8) /* (B19/C19) MCASP0_AXR3.EQEP0_A */ + AM62X_IOPAD(0x0198, PIN_INPUT, 8) /* (A19/B19) MCASP0_AXR2.EQEP0_B */ + AM62X_IOPAD(0x01a0, PIN_INPUT, 8) /* (E18/B20) MCASP0_AXR0.EQEP0_I */ + AM62X_IOPAD(0x019c, PIN_INPUT, 8) /* (B18/B18) MCASP0_AXR1.EQEP0_S */ + >; + }; +}; + +&main_i2c1 { + gpio@22 { + p25-hog { + /* P25 - UART1_FET_SEL */ + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "UART1_FET_SEL"; + }; + }; +}; + +&main_uart1 { + /* Disable FW debug logs */ + status = "disabled"; +}; + +&eqep0 { + status = "okay"; + /* A/B on pins 38/35 of J3 on AM625-SK & AM62 LP-SK */ + /* A/B on pins 40/38 of J3 on AM62A7-SK */ + pinctrl-names = "default"; + pinctrl-0 = <&main_eqep0_pins_default>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-fastboot-disable-hdmi.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-fastboot-disable-hdmi.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-fastboot-disable-hdmi.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-fastboot-disable-hdmi.dtso 2026-04-21 11:35:28.530915236 +0200 @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** +* Overlay to remove HDMI support for TI K3 AM62* SK +* +* Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ +*/ + +/dts-v1/; +/plugin/; + +&hdmi0 { + status = "disabled"; +}; + +&sii9022 { + status = "disabled"; +}; + +&hdmi0_dss { + status = "disabled"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-lpm-io-ddr-wkup-sources.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-lpm-io-ddr-wkup-sources.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-lpm-io-ddr-wkup-sources.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-lpm-io-ddr-wkup-sources.dtso 2026-04-21 11:35:28.530915236 +0200 @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * AM62 family of devices can wakeup from I/O Only + DDR low power mode via + * multiple wakeup sources. This overlay enables mcu_mcan pins to be used + * as wakeup source. + * + * Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "k3-pinctrl.h" + +&mcu_pmx0 { + mcu_mcan0_tx_pins_default: mcu-mcan0-tx-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan0_rx_pins_default: mcu-mcan0-rx-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan0_rx_pins_wakeup: mcu-mcan0-rx-pins-wakeup { + pinctrl-single,pins = < + AM62X_IOPAD(0x038, PIN_INPUT | PIN_WKUP_EN, 0) /* (B3) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan1_tx_pins_default: mcu-mcan1-tx-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x03c, PIN_OUTPUT, 0) /* (E5) MCU_MCAN1_TX */ + >; + }; + + mcu_mcan1_rx_pins_default: mcu-mcan1-rx-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x040, PIN_INPUT, 0) /* (D4) MCU_MCAN1_RX */ + >; + }; + + mcu_mcan1_rx_pins_wakeup: mcu-mcan1-rx-pins-wakeup { + pinctrl-single,pins = < + AM62X_IOPAD(0x040, PIN_INPUT | PIN_WKUP_EN, 0) /* (D4) MCU_MCAN1_RX */ + >; + }; +}; + +&mcu_mcan0 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_default>; + pinctrl-1 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_wakeup>; + wakeup-source = "suspend", "poweroff"; + status = "okay"; +}; + +&mcu_mcan1 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_default>; + pinctrl-1 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_wakeup>; + wakeup-source = "suspend", "poweroff"; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-lpm-standby.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-lpm-standby.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-lpm-standby.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-lpm-standby.dtso 2026-04-21 11:35:28.531915238 +0200 @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay to enable standby mode entry in AM62 family of devices. + * + * Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: stby { + compatible = "arm,idle-state"; + idle-state-name = "standby"; + arm,psci-suspend-param = <0x00000001>; + entry-latency-us = <100>; + exit-latency-us = <50>; + min-residency-us = <1000>; + }; + }; +}; + + +&cpu0 { + cpu-idle-states = <&CPU_SLEEP_0>; +}; + +&cpu1 { + cpu-idle-states = <&CPU_SLEEP_0>; +}; + +&cpu2 { + cpu-idle-states = <&CPU_SLEEP_0>; +}; + +&cpu3 { + cpu-idle-states = <&CPU_SLEEP_0>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-lpm-wkup-sources.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-lpm-wkup-sources.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-lpm-wkup-sources.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-lpm-wkup-sources.dtso 2026-04-21 11:35:28.531915238 +0200 @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * AM62 family of devices can wakeup from Low Power Modes via + * multiple wakeup sources. This overlay enables MAIN GPIO, MCU GPIO, + * and MCU MCAN pins. + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + gpio_key { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_pins_default>; + switch { + label = "WKGPIO"; + linux,code = ; + interrupts-extended = <&main_gpio1 10 IRQ_TYPE_EDGE_RISING>, + <&main_pmx0 0x1a0>; + interrupt-names = "irq", "wakeup"; + }; + }; + + mcu_gpio_key { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&wake_mcugpio1_pins_default>; + interrupt-parent = <&mcu_gpio0>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + switch { + label = "MCUGPIO"; + linux,code = <143>; + gpios = <&mcu_gpio0 4 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; +}; + +&main_pmx0 { + main_gpio1_pins_default: main-gpio1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1a0, PIN_INPUT_PULLUP, 7) /* (E18) MCASP0_AXR0.EHRPWM1_B */ + >; + }; +}; + +&mcu_pmx0 { + wake_mcugpio1_pins_default: wake-mcugpio1-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0010, PIN_INPUT, 7) /* (D8) MCU_SPI0_D1.MCU_GPIO0_4 */ + >; + }; + + mcu_mcan0_tx_pins_default: mcu-mcan0-tx-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan0_rx_pins_default: mcu-mcan0-rx-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan0_rx_pins_wakeup: mcu-mcan0-rx-pins-wakeup { + pinctrl-single,pins = < + AM62X_IOPAD(0x038, PIN_INPUT | PIN_WKUP_EN, 0) /* (B3) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan1_tx_pins_default: mcu-mcan1-tx-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x03c, PIN_OUTPUT, 0) /* (E5) MCU_MCAN1_TX */ + >; + }; + + mcu_mcan1_rx_pins_default: mcu-mcan1-rx-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x040, PIN_INPUT, 0) /* (D4) MCU_MCAN1_RX */ + >; + }; + + mcu_mcan1_rx_pins_wakeup: mcu-mcan1-rx-pins-wakeup { + pinctrl-single,pins = < + AM62X_IOPAD(0x040, PIN_INPUT | PIN_WKUP_EN, 0) /* (D4) MCU_MCAN1_RX */ + >; + }; +}; + +&mcu_gpio0 { + status = "okay"; +}; + +&mcu_gpio_intr { + status = "okay"; +}; + +&mcu_mcan0 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_default>; + pinctrl-1 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_wakeup>; + wakeup-source = "suspend", "poweroff"; + status = "okay"; +}; + +&mcu_mcan1 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_default>; + pinctrl-1 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_wakeup>; + wakeup-source = "suspend", "poweroff"; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-mcan.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-mcan.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-mcan.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-mcan.dtso 2026-04-21 11:35:28.531915238 +0200 @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay to enable MCAN on AM625-SK, AM62 LP-SK, and AM62A7-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-pinctrl.h" + +&{/} { + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&main_pmx0 { + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ + AM62X_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ + >; + }; +}; + +&mcu_pmx0 { + mcu_mcan0_pins_default: mcu-mcan0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ + AM62X_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0040, PIN_INPUT, 0) /* (D4) MCU_MCAN1_RX */ + AM62X_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) /* (E5) MCU_MCAN1_TX */ + >; + }; +}; + +&pruss_uart { + /* Conflict with MCAN0 */ + status = "disabled"; +}; + +&main_mcan0 { + /* RX pin 8 & TX pin 10 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&transceiver1>; + status = "okay"; +}; + +&mcu_mcan0 { + /* RX pin 22 & TX pin 16 of J10 */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver2>; + status = "okay"; +}; + +&mcu_mcan1 { + /* RX pin 11 & TX pin 10 of J10 */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver3>; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-mcspi-loopback.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-mcspi-loopback.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-mcspi-loopback.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-mcspi-loopback.dtso 2026-04-21 11:35:28.531915238 +0200 @@ -0,0 +1,65 @@ + + +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for using McSPI on AM62, AM62 SIP, AM62 LP, AM62A, AM62P SK boards + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + main_spi0_pins_default: main-spi0-pins-default { + pinctrl-single,pins = < + /* P19, P21, P23, P24 of J3/J4 */ + AM62X_IOPAD(0x01c0, PIN_INPUT, 0) /* (B13) SPI0_D0 */ + AM62X_IOPAD(0x01c4, PIN_INPUT, 0) /* (B14) SPI0_D1 */ + AM62X_IOPAD(0x01bc, PIN_INPUT, 0) /* (A14) SPI0_CLK */ + AM62X_IOPAD(0x01b4, PIN_INPUT, 0) /* (A13) SPI0_CS0 */ + >; + }; +}; + +&main_i2c1 { + gpio@22 { + en_rpi_3v3 { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_3V3_EN"; + }; + }; +}; + +&epwm0 { + /* Conflict with SPI0_CS0 on am62p SK */ + status = "disabled"; +}; + +&epwm1 { + /* Conflict with SPI0_D0/SPI0_CLK on AM62p SK */ + status = "disabled"; +}; + +&main_spi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&main_spi0_pins_default>; + pinctrl-names = "default"; + spidev@0 { + /* + * Using spidev compatible is warned loudly, + * thus use another equivalent compatible id + * from spidev. + */ + compatible = "rohm,dh2228fv"; + spi-max-frequency = <24000000>; + reg = <0>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-microtips-mf103hie-lcd2.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-microtips-mf103hie-lcd2.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-microtips-mf103hie-lcd2.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-microtips-mf103hie-lcd2.dtso 2026-04-21 11:35:28.531915238 +0200 @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * Microtips integrated OLDI panel (MF-103HIEB0GA0) (SK-LCD2) DT overlay for AM625-SK and AM62-LP SK + * + * AM625-SKEVM: https://www.ti.com/tool/SK-AM62 + * AM62-LP SKEVM: https://www.ti.com/tool/SK-AM62-LP + * Panel datasheet: https://simplespec.microtipsusa.com/uploads/spec/datasheetFile/2660/13-103HIEB0GA0-S_V1.0_20211206.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + display { + compatible = "microtips,mf-103hieb0ga0", "panel-simple"; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * Swapping them will cause an error in the dss oldi driver. + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_0_out>; + }; + }; + port@1 { + reg = <1>; + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_1_out>; + }; + }; + }; + }; +}; + +&dss { + status = "okay"; +}; + +&oldi0 { + status = "okay"; + ti,companion-oldi = <&oldi1>; +}; + +&oldi1 { + status = "okay"; + ti,secondary-oldi; + ti,companion-oldi = <&oldi0>; +}; + +&oldi0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + oldi_0_in: endpoint { + remote-endpoint = <&dpi0_out0>; + }; + }; + + port@1 { + reg = <1>; + oldi_0_out: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; +}; + +&oldi1_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + oldi_1_in: endpoint { + remote-endpoint = <&dpi0_out1>; + }; + }; + + port@1 { + reg = <1>; + oldi_1_out: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: Output to OLDI */ + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dpi0_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&oldi_0_in>; + }; + dpi0_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&oldi_1_in>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-pwm.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-pwm.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am62x-sk-pwm.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am62x-sk-pwm.dtso 2026-04-21 11:35:28.531915238 +0200 @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling PWM output on user expansion connector for AM625-SK, AM62 LP-SK, and AM62A7-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + main_epwm0_pins_default: main-epwm0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01ac, PIN_OUTPUT, 6) /* (E19) MCASP0_AFSR.EHRPWM0_A */ + AM62X_IOPAD(0x01b0, PIN_OUTPUT, 6) /* (A20) MCASP0_ACLKR.EHRPWM0_B */ + >; + }; + main_epwm1_pins_default: main-epwm1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x019c, PIN_OUTPUT, 6) /* (B18) MCASP0_AXR1.EHRPWM1_A */ + AM62X_IOPAD(0x01a0, PIN_OUTPUT, 6) /* (E18) MCASP0_AXR0.EHRPWM1_B */ + >; + }; + main_ecap0_pins_default: main-ecap0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b8, PIN_OUTPUT, 3) /* (C13) SPI0_CS1.ECAP0_IN_APWM_OUT */ + >; + }; + main_ecap1_pins_default: main_ecap1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0194, PIN_OUTPUT, 5) /* (B19) MCASP0_AXR3.ECAP1_IN_APWM_OUT */ + >; + }; + main_ecap2_pins_default: main-ecap2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01a4, PIN_OUTPUT, 2) /* (B20) MCASP0_ACLKX.ECAP2_IN_APWM_OUT */ + >; + }; +}; + +&main_i2c1 { + gpio@22 { + fet_sel { + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "UART1_FET_SEL"; + }; + }; +}; + +&main_uart1 { + /* Disable FW debug logs */ + status = "disabled"; +}; + +&epwm0 { + /* Pin 12/40 of J3 on AM625-SK & AM62 LP-SK */ + /* Pin 35/12 of J3 on AM62A7-SK */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm0_pins_default>; + status = "okay"; +}; + +&epwm1 { + /* Pin 36/33 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm1_pins_default>; + status = "okay"; +}; + +&ecap0 { + /* ECAP0 in APWM mode */ + /* Pin 26 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap0_pins_default>; + status = "okay"; +}; + +&ecap1 { + /* ECAP1 in APWM mode */ + /* Pin 38 of J3 on AM625-SK & AM62 LP-SK */ + /* Pin 40 of J3 on AM62A7-SK */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap1_pins_default>; + status = "okay"; +}; + +&ecap2 { + /* ECAP2 in APWM mode */ + /* Pin 11 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap2_pins_default>; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-eqep.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am642-eqep.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-eqep.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am642-eqep.dtso 2026-04-21 11:35:28.534915246 +0200 @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay to enable EQEP2 on AM642-SK & AM642-EVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-pinctrl.h" + +&main_pmx0 { + main_eqep2_pins_default: main-eqep2-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x258, PIN_INPUT, 8) /* (C17) MCAN1_TX.EQEP2_A */ + AM64X_IOPAD(0x25c, PIN_INPUT, 8) /* (D17) MCAN1_RX.EQEP2_B */ + AM64X_IOPAD(0x250, PIN_INPUT, 8) /* (A17) MCAN0_TX.EQEP2_I */ + AM64X_IOPAD(0x254, PIN_INPUT, 8) /* (B17) MCAN0_RX.EQEP2_S */ + >; + }; +}; + +&main_mcan0 { + status = "disabled"; +}; + +&main_mcan1 { + status = "disabled"; +}; + +&eqep2 { + /* A/B on pins 2/1 of J10 on AM64 EVM */ + /* A/B on pins 10/8 of J4 on AM64 SK */ + pinctrl-names = "default"; + pinctrl-0 = <&main_eqep2_pins_default>; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-evm.dts v_kernel/arch/arm64/boot/dts/ti/k3-am642-evm.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-evm.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am642-evm.dts 2026-04-21 11:35:28.535915249 +0200 @@ -12,6 +12,7 @@ #include "k3-am642.dtsi" #include "k3-serdes.h" +#include "k3-timesync-router.h" / { compatible = "ti,am642-evm", "ti,am642"; @@ -101,6 +102,18 @@ no-map; }; + mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + rtos_ipc_memory_region: ipc-memories@a5000000 { reg = <0x00 0xa5000000 0x00 0x00800000>; alignment = <0x1000>; @@ -253,6 +266,7 @@ ti,mii-g-rt = <&icssg1_mii_g_rt>; ti,mii-rt = <&icssg1_mii_rt>; ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; + ti,pa-stats = <&icssg1_pa_stats>; interrupt-parent = <&icssg1_intc>; interrupts = <24 0 2>, <25 1 3>; interrupt-names = "tx_ts0", "tx_ts1"; @@ -294,12 +308,12 @@ main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ - AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ + AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */ AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ - AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ + AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */ AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ >; @@ -414,6 +428,7 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ >; + bootph-all; }; main_ecap0_pins_default: main-ecap0-default-pins { @@ -450,7 +465,7 @@ >; }; - icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{ + icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ @@ -474,6 +489,10 @@ }; }; +&fss { + bootph-all; +}; + &main_uart0 { bootph-all; status = "okay"; @@ -581,6 +600,7 @@ /* eMMC */ &sdhci0 { + bootph-all; status = "okay"; non-removable; ti,driver-strength-ohm = <50>; @@ -616,6 +636,11 @@ pinctrl-names = "default"; pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; status = "okay"; + + /* Map HW8_TS_PUSH to GENF1 */ + cpts@3d000 { + ti,pps = <7 1>; + }; }; &cpsw_port1 { @@ -649,6 +674,9 @@ /* ADC is reserved for R5 usage */ status = "reserved"; + dmas = <&main_bcdma 0 0x440f 0>, <&main_bcdma 0 0x4410 0>; + dma-names = "fifo0", "fifo1"; + adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; @@ -658,6 +686,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; + bootph-all; flash@0 { compatible = "jedec,spi-nor"; @@ -670,11 +699,14 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + cdns,phy-mode; + bootph-all; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + bootph-all; partition@0 { label = "ospi.tiboot3"; @@ -709,6 +741,7 @@ partition@3fc0000 { label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; + bootph-all; }; }; }; @@ -775,6 +808,30 @@ <&main_r5fss1_core1_memory_region>; }; +&mcu_m4fss { + mboxes = <&mailbox0_cluster6 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; + +/* main domain timers 8 to 11 are used by TI MCU FW */ +&main_timer8 { + status = "reserved"; +}; + +&main_timer9 { + status = "reserved"; +}; + +&main_timer10 { + status = "reserved"; +}; + +&main_timer11 { + status = "reserved"; +}; + &serdes_ln_ctrl { idle-states = ; }; @@ -838,3 +895,22 @@ pinctrl-names = "default"; pinctrl-0 = <&icssg1_iep0_pins_default>; }; + +×ync_router { + /* Use Time Sync Router to map GENF1 input to HW8_TS_PUSH output. */ + mux-reg-masks-state = < + /* pps [cpts genf1] in22 -> out37 [cpts hw8_push] */ + K3_TS_OFFSET(37, 0x0001ffff, 22) + /* iep-pps [iep sync_out0] in29 -> out23 [navss cpts hw8_push] */ + K3_TS_OFFSET(23, 0x0001ffff, 29) + >; + status = "okay"; +}; + +&main_cpts0 { + /* + * Use HW8_TS_PUSH of NAVSS CPTS to generate events for IEP PPS + * signal (PRGx_IEP0_EDC_SYNC_OUT0) + */ + ti,pps = <7 1>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-evm-onboard-clkgen-pcie-serdes.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am642-evm-onboard-clkgen-pcie-serdes.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-evm-onboard-clkgen-pcie-serdes.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am642-evm-onboard-clkgen-pcie-serdes.dtso 2026-04-21 11:35:28.534915246 +0200 @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for utilizing the "PCIe Clock HCSL (100MHz)" onboard clock + * generator. The clock generator outputs two 100 MHz differential clock + * pair signals for the purpose of: + * 1) Supplying the PCIe reference clock to the PCIe connector + * 2) Supplying the Reference clock to SERDES0 + * + * AM642 EVM Product Link: https://www.ti.com/tool/TMDS64EVM + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +/* Onboard clock generator provides 100 MHz reference clock to SERDES0 */ +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + /* + * Remove 'phy_en_refclk' clock since SERDES0 doesn't have to generate the + * PCIe reference clock (provided by the onboard clock generator). + */ + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>; + clock-names = "refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + /* Use onboard clock generator as SERDES0 reference clock */ + assigned-clock-parents = <&serdes_refclk>, + <&serdes_refclk>, + <&serdes_refclk>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso 2026-04-21 11:35:28.534915246 +0200 @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the + * AM642 EVM. + * + * AM642 EVM Product Link: https://www.ti.com/tool/TMDS64EVM + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie0_rc { + status = "disabled"; +}; + +&cbass_main { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + + pcie0_ep: pcie-ep@f102000 { + compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x0f102000 0x00 0x1000>, + <0x00 0x0f100000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x68000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + max-link-speed = <2>; + num-lanes = <1>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "fck"; + max-functions = /bits/ 8 <1>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + bootph-all; + ti,syscon-pcie-ctrl = <&main_conf 0x4070>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-evm-sk-cpsw3g-pps.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am642-evm-sk-cpsw3g-pps.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-evm-sk-cpsw3g-pps.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am642-evm-sk-cpsw3g-pps.dtso 2026-04-21 11:35:28.534915246 +0200 @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for enabling PPS in CPSW3G via SYNC0_OUT signal + * This overlay is applicable for both AM642-EVM and AM642-SK + * boards. + * + * AM642 EVM Product Link: https://www.ti.com/tool/TMDS64EVM + * AM642 SK Product Link: https://www.ti.com/tool/SK-AM64B + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-pinctrl.h" +#include "k3-timesync-router.h" + +&main_pmx0 { + cpsw3g_pps_pins_default: cpsw3g-pps-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0270, PIN_INPUT, 1) /* (D18) SYNC0_OUT */ + >; + }; +}; + +/* + * Since D18 is used by CPSW for SYNC0_OUT, disable ECAP which uses D18 for + * ECAP0_IN_APWM_OUT. + */ + +&ecap0 { + status = "disabled"; +}; + +&cpsw3g { + pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>, + <&cpsw3g_pps_pins_default>; +}; + +×ync_router { + /* Use Time Sync Router to map GENF1 input to HW8_TS_PUSH output. */ + mux-reg-masks-state = < + /* pps [cpts genf1] in22 -> out37 [cpts hw8_push] */ + K3_TS_OFFSET(37, 0x0001ffff, 22) + /* pps [cpts genf1] in22 -> out24 [SYNC0_OUT pin] */ + K3_TS_OFFSET(24, 0x0001ffff, 22) + >; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts v_kernel/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts 2026-04-21 11:35:28.536915252 +0200 @@ -346,6 +346,10 @@ }; }; +&i2c_som_rtc { + trickle-resistor-ohms = <3000>; +}; + &main_i2c1 { status = "okay"; pinctrl-names = "default"; @@ -425,7 +429,6 @@ vmmc-supply = <&vcc_3v3_mmc>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - bus-width = <4>; disable-wp; no-1-8-v; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-sk.dts v_kernel/arch/arm64/boot/dts/ti/k3-am642-sk.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-sk.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am642-sk.dts 2026-04-21 11:35:28.536915252 +0200 @@ -12,6 +12,7 @@ #include "k3-am642.dtsi" #include "k3-serdes.h" +#include "k3-timesync-router.h" / { compatible = "ti,am642-sk", "ti,am642"; @@ -25,6 +26,7 @@ serial0 = &mcu_uart0; serial1 = &main_uart1; serial2 = &main_uart0; + serial3 = &icssg0_uart; i2c0 = &main_i2c0; i2c1 = &main_i2c1; mmc0 = &sdhci0; @@ -99,6 +101,18 @@ no-map; }; + mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + rtos_ipc_memory_region: ipc-memories@a5000000 { reg = <0x00 0xa5000000 0x00 0x00800000>; alignment = <0x1000>; @@ -240,15 +254,15 @@ main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins = < - AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ - AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ - AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ + AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */ + AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */ + AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */ - AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ - AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ - AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ - AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ - AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ + AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */ + AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */ + AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */ + AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */ + AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */ >; }; @@ -350,6 +364,7 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ >; + bootph-all; }; main_ecap0_pins_default: main-ecap0-default-pins { @@ -357,6 +372,16 @@ AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ >; }; + + main_eqep0_pins_default: main-eqep0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x00a0, PIN_INPUT, 3) /* (N16) GPMC0_WPn.EQEP0_A */ + AM64X_IOPAD(0x00a4, PIN_INPUT, 3) /* (N17) GPMC0_DIR.EQEP0_B */ + AM64X_IOPAD(0x00ac, PIN_INPUT, 3) /* (R20) GPMC0_CSn1.EQEP0_I */ + AM64X_IOPAD(0x00a8, PIN_INPUT, 3) /* (R19) GPMC0_CSn0.EQEP0_S */ + >; + }; + main_wlan_en_pins_default: main-wlan-en-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */ @@ -374,6 +399,15 @@ AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ >; }; + + icssg0_uart_pins_default: icssg0-uart-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0184, PIN_INPUT, 2) /* (W6) PRG0_PRU0_GPO9.PRG0_UART0_CTSn */ + AM64X_IOPAD(0x0188, PIN_OUTPUT, 2) /* (AA5) PRG0_PRU0_GPO10.PRG0_UART0_RTSn */ + AM64X_IOPAD(0x01d4, PIN_INPUT, 2) /* (Y5) PRG0_PRU1_GPO9.PRG0_UART0_RXD */ + AM64X_IOPAD(0x01d8, PIN_OUTPUT, 2) /* (V6) PRG0_PRU1_GPO10.PRG0_UART0_TXD */ + >; + }; }; &main_uart0 { @@ -528,6 +562,11 @@ pinctrl-names = "default"; pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; status = "okay"; + + /* Map HW8_TS_PUSH to GENF1 */ + cpts@3d000 { + ti,pps = <7 1>; + }; }; &cpsw_port1 { @@ -564,6 +603,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; + bootph-all; flash@0 { compatible = "jedec,spi-nor"; @@ -576,11 +616,14 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + cdns,phy-mode; + bootph-all; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + bootph-all; partition@0 { label = "ospi.tiboot3"; @@ -615,6 +658,7 @@ partition@3fc0000 { label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; + bootph-all; }; }; }; @@ -681,9 +725,55 @@ <&main_r5fss1_core1_memory_region>; }; +&mcu_m4fss { + mboxes = <&mailbox0_cluster6 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; + +/* main domain timers 8 to 11 are used by TI MCU FW */ +&main_timer8 { + status = "reserved"; +}; + +&main_timer9 { + status = "reserved"; +}; + +&main_timer10 { + status = "reserved"; +}; + +&main_timer11 { + status = "reserved"; +}; + &ecap0 { status = "okay"; /* PWM is available on Pin 1 of header J3 */ pinctrl-names = "default"; pinctrl-0 = <&main_ecap0_pins_default>; }; + +&eqep0 { + status = "okay"; + /* EQEP0 A & B available on pins 18 & 22 of J4 header */ + pinctrl-names = "default"; + pinctrl-0 = <&main_eqep0_pins_default>; +}; + +×ync_router { + /* Use Time Sync Router to map GENF1 input to HW8_TS_PUSH output. */ + mux-reg-masks-state = < + /* pps [cpts genf1] in22 -> out37 [cpts hw8_push] */ + K3_TS_OFFSET(37, 0x0001ffff, 22) + >; + status = "okay"; +}; + +&icssg0_uart { + pinctrl-names = "default"; + pinctrl-0 = <&icssg0_uart_pins_default>; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-sk-pwm.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am642-sk-pwm.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-sk-pwm.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am642-sk-pwm.dtso 2026-04-21 11:35:28.536915252 +0200 @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling PWM output on user expansion connector for AM64 SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-pinctrl.h" + +&main_pmx0 { + main_ecap0_pins_default: main_ecap0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0270, PIN_OUTPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ + >; + }; + main_ecap1_pins_default: main_ecap1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0258, PIN_OUTPUT, 2) /* (C17) MCAN1_TX.ECAP1_IN_APWM_OUT */ + >; + }; + main_ecap2_pins_default: main_ecap2-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x025c, PIN_OUTPUT, 2) /* (D17) MCAN1_RX.ECAP2_IN_APWM_OUT */ + >; + }; + main_epwm4_pins_default: main_epwm4-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0088, PIN_OUTPUT, 3) /* (R18) GPMC0_OEn_REn.EHRPWM4_A */ + AM64X_IOPAD(0x008c, PIN_OUTPUT, 3) /* (T21) GPMC0_WEn.EHRPWM4_B */ + >; + }; + main_epwm5_pins_default: main_epwm5-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0094, PIN_OUTPUT, 3) /* (T19) GPMC0_BE1n.EHRPWM5_A */ + AM64X_IOPAD(0x0098, PIN_OUTPUT, 3) /* (W19) GPMC0_WAIT0.EHRPWM5_B */ + >; + }; + main_epwm6_pins_default: main_epwm6-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x021c, PIN_OUTPUT, 3) /* (B14) SPI1_CS0.EHRPWM6_A */ + AM64X_IOPAD(0x022c, PIN_OUTPUT, 3) /* (A15) SPI1_D1.EHRPWM6_B */ + >; + }; + main_epwm7_pins_default: main_epwm7-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0090, PIN_OUTPUT, 5) /* (P17) GPMC0_BE0n_CLE.EHRPWM7_A */ + AM64X_IOPAD(0x009c, PIN_OUTPUT, 5) /* (Y18) GPMC0_WAIT1.EHRPWM7_B */ + >; + }; + main_epwm8_pins_default: main_epwm8-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x01a8, PIN_OUTPUT, 6) /* (V1) PRG0_PRU0_GPO18.EHRPWM8_A */ + AM64X_IOPAD(0x01ac, PIN_OUTPUT, 6) /* (W1) PRG0_PRU0_GPO19.EHRPWM8_B */ + >; + }; +}; + +&main_mcan1 { + /* For AM64x EVM only */ + status = "disabled"; +}; + +&ecap0 { + /* ECAP0 in APWM mode */ + /* Pin 1 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap0_pins_default>; + status = "okay"; +}; + +&ecap1 { + /* ECAP1 in APWM mode */ + /* Pin 10 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap1_pins_default>; + status = "okay"; +}; + +&ecap2 { + /* ECAP2 in APWM mode */ + /* Pin 8 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap2_pins_default>; + status = "okay"; +}; + +&epwm4 { + /* Pin 32/33 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm4_pins_default>; + status = "okay"; +}; + +&epwm5 { + /* Pin 29/31 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm5_pins_default>; + status = "okay"; +}; + +&epwm6 { + /* Pin 12/35 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm6_pins_default>; + status = "okay"; +}; + +&epwm7 { + /* Pin 7/16 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm7_pins_default>; + status = "okay"; +}; + +&epwm8 { + /* Pin 38/43 of J10 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm8_pins_default>; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts v_kernel/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts 2026-04-21 11:35:28.537915254 +0200 @@ -201,8 +201,6 @@ reset-gpios = <&main_gpio0 44 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <1000>; - ti,rx-fifo-depth = ; - ti,tx-fifo-depth = ; ti,rx-internal-delay = ; ti,clk-output-sel = ; }; @@ -230,8 +228,6 @@ reset-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <1000>; - ti,rx-fifo-depth = ; - ti,tx-fifo-depth = ; ti,rx-internal-delay = ; ti,clk-output-sel = ; }; @@ -242,8 +238,6 @@ reset-gpios = <&main_gpio1 51 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <1000>; - ti,rx-fifo-depth = ; - ti,tx-fifo-depth = ; ti,rx-internal-delay = ; ti,clk-output-sel = ; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am64.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am64.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am64.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am64.dtsi 2026-04-21 11:35:28.533915244 +0200 @@ -19,6 +19,10 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + spi0 = &ospi0; + }; + chosen { }; firmware { diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am64-main.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am64-main.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am64-main.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am64-main.dtsi 2026-04-21 11:35:28.533915244 +0200 @@ -51,6 +51,11 @@ reg = <0x00000014 0x4>; }; + pcie0_ctrl: pcie-ctrl@4070 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4070 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x4080 0x4>; @@ -754,12 +759,11 @@ ti,cpts-ext-ts-inputs = <8>; }; - timesync_router: pinctrl@a40000 { - compatible = "pinctrl-single"; + timesync_router: mux-controller@a40000 { + compatible = "reg-mux"; reg = <0x0 0xa40000 0x0 0x800>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x000107ff>; + #mux-control-cells = <1>; + status = "disabled"; }; usbss0: cdns-usb@f900000 { @@ -825,6 +829,7 @@ cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; + cdns,phase-detect-selector = <2>; #address-cells = <0x1>; #size-cells = <0x0>; clocks = <&k3_clks 75 6>; @@ -1031,12 +1036,12 @@ reg = <0x00 0x0f102000 0x00 0x1000>, <0x00 0x0f100000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x68000000 0x00 0x00001000>; + <0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&main_conf 0x4070>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; max-link-speed = <2>; num-lanes = <1>; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; @@ -1049,8 +1054,8 @@ vendor-id = <0x104c>; device-id = <0xb010>; msi-map = <0x0 &gic_its 0x0 0x10000>; - ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, - <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; status = "disabled"; }; @@ -1175,6 +1180,33 @@ status = "disabled"; }; + eqep0: counter@23200000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23200000 0x00 0x100>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 59 0>; + interrupts = ; + status = "disabled"; + }; + + eqep1: counter@23210000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23210000 0x00 0x100>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 60 0>; + interrupts = ; + status = "disabled"; + }; + + eqep2: counter@23220000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23220000 0x00 0x100>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 62 0>; + interrupts = ; + status = "disabled"; + }; + main_rti0: watchdog@e000000 { compatible = "ti,j7-rti-wdt"; reg = <0x00 0xe000000 0x00 0x100>; @@ -1200,6 +1232,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x30000000 0x80000>; + clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ + <&k3_clks 81 3>, /* icssg0_iep_clk */ + <&k3_clks 81 16>, /* icssg0_rgmii_mhz_250_clk */ + <&k3_clks 81 17>, /* icssg0_rgmii_mhz_50_clk */ + <&k3_clks 81 18>, /* icssg0_rgmii_mhz_5_clk */ + <&k3_clks 81 19>, /* icssg0_uart_clk */ + <&k3_clks 81 20>; /* icssg0_iclk */ + assigned-clocks = <&k3_clks 81 0>; + assigned-clock-parents = <&k3_clks 81 2>; icssg0_mem: memories@0 { reg = <0x0 0x2000>, @@ -1225,7 +1266,7 @@ clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ <&k3_clks 81 20>; /* icssg0_iclk */ assigned-clocks = <&icssg0_coreclk_mux>; - assigned-clock-parents = <&k3_clks 81 20>; + assigned-clock-parents = <&k3_clks 81 0>; }; icssg0_iepclk_mux: iepclk-mux@30 { @@ -1239,6 +1280,15 @@ }; }; + icssg0_uart: serial@28000 { + compatible = "ti,pruss-uart"; + reg = <0x28000 0x40>; + clocks = <&k3_clks 81 19>; + interrupt-parent = <&icssg0_intc>; + interrupts = <6 6 6>; + status = "disabled"; + }; + icssg0_iep0: iep@2e000 { compatible = "ti,am654-icss-iep"; reg = <0x2e000 0x1000>; @@ -1261,6 +1311,11 @@ reg = <0x33000 0x1000>; }; + icssg0_pa_stats: pa-stats@2c000 { + compatible = "ti,pruss-pa-st", "syscon"; + reg = <0x2c000 0x1000>; + }; + icssg0_intc: interrupt-controller@20000 { compatible = "ti,icssg-intc"; reg = <0x20000 0x2000>; @@ -1365,6 +1420,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x30080000 0x80000>; + clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ + <&k3_clks 82 3>, /* icssg1_iep_clk */ + <&k3_clks 82 16>, /* icssg1_rgmii_mhz_250_clk */ + <&k3_clks 82 17>, /* icssg1_rgmii_mhz_50_clk */ + <&k3_clks 82 18>, /* icssg1_rgmii_mhz_5_clk */ + <&k3_clks 82 19>, /* icssg1_uart_clk */ + <&k3_clks 82 20>; /* icssg1_iclk */ + assigned-clocks = <&k3_clks 82 0>; + assigned-clock-parents = <&k3_clks 82 2>; icssg1_mem: memories@0 { reg = <0x0 0x2000>, @@ -1390,7 +1454,7 @@ clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ <&k3_clks 82 20>; /* icssg1_iclk */ assigned-clocks = <&icssg1_coreclk_mux>; - assigned-clock-parents = <&k3_clks 82 20>; + assigned-clock-parents = <&k3_clks 82 0>; }; icssg1_iepclk_mux: iepclk-mux@30 { @@ -1404,6 +1468,15 @@ }; }; + icssg1_uart: serial@28000 { + compatible = "ti,pruss-uart"; + reg = <0x28000 0x40>; + clocks = <&k3_clks 82 19>; + interrupt-parent = <&icssg1_intc>; + interrupts = <6 6 6>; + status = "disabled"; + }; + icssg1_iep0: iep@2e000 { compatible = "ti,am654-icss-iep"; reg = <0x2e000 0x1000>; @@ -1426,6 +1499,11 @@ reg = <0x33000 0x1000>; }; + icssg1_pa_stats: pa-stats@2c000 { + compatible = "ti,pruss-pa-st", "syscon"; + reg = <0x2c000 0x1000>; + }; + icssg1_intc: interrupt-controller@20000 { compatible = "ti,icssg-intc"; reg = <0x20000 0x2000>; @@ -1609,4 +1687,24 @@ power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; }; + + memorycontroller: memory-controller@f300000 { + compatible = "ti,am62-ddrss"; + reg = <0x00 0x0f300000 0x00 0x200>; + reg-names = "ss_cfg"; + ranges = <0x00 0x00 0x00 0x0f308000 0x00 0x55f8>; + interrupts = ; + power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 138 0>; + #address-cells = <2>; + #size-cells = <2>; + + ddr: ddr@0 { + compatible = "cdns,j7-ddr"; + reg = <0x00 0x0000 0x00 0x69c>, + <0x00 0x2000 0x00 0x564>, + <0x00 0x4000 0x00 0x15f8>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + }; + }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi 2026-04-21 11:35:28.533915244 +0200 @@ -161,4 +161,17 @@ /* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */ ti,esm-pins = <0>, <1>, <2>, <85>; }; + + mcu_m4fss: m4fss@5000000 { + compatible = "ti,am64-m4fss"; + reg = <0x00 0x5000000 0x00 0x30000>, + <0x00 0x5040000 0x00 0x10000>; + reg-names = "iram", "dram"; + resets = <&k3_reset 9 1>; + firmware-name = "am64-mcu-m4f0_0-fw"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <9>; + ti,sci-proc-ids = <0x18 0xff>; + status = "disabled"; + }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi 2026-04-21 11:35:28.533915244 +0200 @@ -87,6 +87,18 @@ reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; + + mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; }; leds { @@ -240,6 +252,15 @@ }; }; +&mailbox0_cluster6 { + status = "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; +}; + &main_i2c0 { status = "okay"; pinctrl-names = "default"; @@ -333,6 +354,13 @@ <&main_r5fss1_core1_memory_region>; }; +&mcu_m4fss { + mboxes = <&mailbox0_cluster6 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; + &ospi0 { status = "okay"; pinctrl-names = "default"; @@ -354,7 +382,6 @@ &sdhci0 { status = "okay"; - bus-width = <8>; non-removable; ti,driver-strength-ohm = <50>; disable-wp; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am654-evm-oldi-lcd1evm.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am654-evm-oldi-lcd1evm.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am654-evm-oldi-lcd1evm.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am654-evm-oldi-lcd1evm.dtso 2026-04-21 11:35:28.541915265 +0200 @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * OLDI-LCD1EVM Rocktech integrated panel and touch DT overlay for AM654-EVM. + * + * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + display0 { + compatible = "rocktech,rk101ii01d-ct"; + backlight = <&lcd_bl>; + enable-gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>; + port { + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + }; + lcd_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = + <0 32 64 96 128 160 192 224 255>; + default-brightness-level = <8>; + }; +}; + +&dss { + status = "okay"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; +}; + +&main_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + gt928: touchscreen@14 { + status = "okay"; + compatible = "goodix,gt928"; + reg = <0x14>; + + interrupt-parent = <&pca9554>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + + reset-gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>; + irq-gpios = <&pca9554 3 GPIO_ACTIVE_HIGH>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso 2026-04-21 11:35:28.542915267 +0200 @@ -41,6 +41,7 @@ ti,mii-g-rt = <&icssg2_mii_g_rt>; ti,mii-rt = <&icssg2_mii_rt>; + ti,pa-stats = <&icssg2_pa_stats>; ti,iep = <&icssg2_iep0>, <&icssg2_iep1>; interrupt-parent = <&icssg2_intc>; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am654-idk.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am654-idk.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am654-idk.dtso 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am654-idk.dtso 2026-04-21 11:35:28.542915267 +0200 @@ -43,6 +43,7 @@ ti,mii-g-rt = <&icssg0_mii_g_rt>; ti,mii-rt = <&icssg0_mii_rt>; + ti,pa-stats = <&icssg0_pa_stats>; ti,iep = <&icssg0_iep0>, <&icssg0_iep1>; interrupt-parent = <&icssg0_intc>; @@ -109,6 +110,7 @@ ti,mii-g-rt = <&icssg1_mii_g_rt>; ti,mii-rt = <&icssg1_mii_rt>; + ti,pa-stats = <&icssg1_pa_stats>; ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; interrupt-parent = <&icssg1_intc>; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am65-main.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am65-main.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am65-main.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am65-main.dtsi 2026-04-21 11:35:28.540915262 +0200 @@ -1169,6 +1169,11 @@ reg = <0x33000 0x1000>; }; + icssg0_pa_stats: pa-stats@2c000 { + compatible = "ti,pruss-pa-st", "syscon"; + reg = <0x2c000 0x1000>; + }; + icssg0_intc: interrupt-controller@20000 { compatible = "ti,icssg-intc"; reg = <0x20000 0x2000>; @@ -1335,6 +1340,11 @@ reg = <0x33000 0x1000>; }; + icssg1_pa_stats: pa-stats@2c000 { + compatible = "ti,pruss-pa-st", "syscon"; + reg = <0x2c000 0x1000>; + }; + icssg1_intc: interrupt-controller@20000 { compatible = "ti,icssg-intc"; reg = <0x20000 0x2000>; @@ -1501,6 +1511,11 @@ reg = <0x33000 0x1000>; }; + icssg2_pa_stats: pa-stats@2c000 { + compatible = "ti,pruss-pa-st", "syscon"; + reg = <0x2c000 0x1000>; + }; + icssg2_intc: interrupt-controller@20000 { compatible = "ti,icssg-intc"; reg = <0x20000 0x2000>; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts v_kernel/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts 2026-04-21 11:35:28.544915273 +0200 @@ -50,11 +50,71 @@ no-map; }; + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + c7x_1_memory_region: c7x-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x1c00000>; + alignment = <0x1000>; + no-map; + }; }; vsys_5v0: regulator-1 { @@ -140,6 +200,34 @@ default-state = "on"; }; }; + + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&it66122_out>; + }; + }; + }; + + sound0: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "it66122 HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&hdmi_dailink_master>; + simple-audio-card,frame-master = <&hdmi_dailink_master>; + + hdmi_dailink_master: simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-direction-out; + }; + + simple-audio-card,codec { + sound-dai = <&it66122>; + }; + }; }; &main_pmx0 { @@ -179,6 +267,20 @@ bootph-all; }; + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */ + J722S_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A22) I2C1_SDA */ + >; + bootph-all; + }; + + main_gpio0_ioexp_intr_pins_default: main-gpio0-ioexp-intr-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0110, PIN_INPUT, 7) /* (G27) MMC2_DAT1.GPIO0_67 */ + >; + }; + mdio_pins_default: mdio-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ @@ -221,6 +323,47 @@ J722S_IOPAD(0x0254, PIN_OUTPUT, 7) /* (E25) USB0_DRVVBUS.GPIO1_50 */ >; }; + + dss1_pins_default: dss1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AB23) VOUT0_VSYNC */ + J722S_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ + J722S_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC26) VOUT0_PCLK */ + J722S_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (AC27) VOUT0_DE */ + J722S_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (W27) VOUT0_DATA0 */ + J722S_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA1 */ + J722S_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA2 */ + J722S_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W23) VOUT0_DATA3 */ + J722S_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA4 */ + J722S_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA5 */ + J722S_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y26) VOUT0_DATA6 */ + J722S_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (Y27) VOUT0_DATA7 */ + J722S_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA8 */ + J722S_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (AA27) VOUT0_DATA9 */ + J722S_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA10 */ + J722S_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA11 */ + J722S_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA12 */ + J722S_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA22) VOUT0_DATA13 */ + J722S_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AB26) VOUT0_DATA14 */ + J722S_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AB27) VOUT0_DATA15 */ + J722S_IOPAD(0x005c, PIN_OUTPUT, 1) /* (AC25) GPMC0_AD8.VOUT0_DATA16 */ + J722S_IOPAD(0x0060, PIN_OUTPUT, 1) /* (U26) GPMC0_AD9.VOUT0_DATA17 */ + J722S_IOPAD(0x0064, PIN_OUTPUT, 1) /* (V27) GPMC0_AD10.VOUT0_DATA18 */ + J722S_IOPAD(0x0068, PIN_OUTPUT, 1) /* (V25) GPMC0_AD11.VOUT0_DATA19 */ + J722S_IOPAD(0x006c, PIN_OUTPUT, 1) /* (V26) GPMC0_AD12.VOUT0_DATA20 */ + J722S_IOPAD(0x0070, PIN_OUTPUT, 1) /* (V24) GPMC0_AD13.VOUT0_DATA21 */ + J722S_IOPAD(0x0074, PIN_OUTPUT, 1) /* (V22) GPMC0_AD14.VOUT0_DATA22 */ + J722S_IOPAD(0x0078, PIN_OUTPUT, 1) /* (V23) GPMC0_AD15.VOUT0_DATA23 */ + >; + }; + + main_mcasp1_pins_default: main-mcasp1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0090, PIN_INPUT, 2) /* (P27) GPMC0_BE0n_CLE.MCASP1_ACLKX */ + J722S_IOPAD(0x0098, PIN_INPUT, 2) /* (V21) GPMC0_WAIT0.MCASP1_AFSX */ + J722S_IOPAD(0x008c, PIN_INPUT, 2) /* (N23) GPMC0_WEn.MCASP1_AXR0 */ + >; + }; }; &cpsw3g { @@ -248,10 +391,18 @@ status = "okay"; }; +&main_gpio0 { + status = "okay"; +}; + &main_gpio1 { status = "okay"; }; +&mcu_gpio0 { + status = "okay"; +}; + &main_uart0 { pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; @@ -277,6 +428,13 @@ >; bootph-all; }; + + hdmi_gpio_pins_default: hdmi-gpio-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x0038, PIN_INPUT_PULLUP | PIN_DEBOUNCE_CONF6, 7) /* (D8) MCU_MCAN0_RX.MCU_GPIO0_14 HDMI_INTn */ + J722S_MCU_IOPAD(0x0034, PIN_OUTPUT_PULLUP, 7) /* (B2) MCU_MCAN0_TX.MCU_GPIO0_13 HDMI_RSTn */ + >; + }; }; &wkup_uart0 { @@ -378,6 +536,55 @@ }; }; +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + bootph-all; + + it66122: bridge-hdmi@4c { + compatible = "ite,it66122"; + reg = <0x4c>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_gpio_pins_default>; + vcn33-supply = <&vdd_3v3>; + vcn18-supply = <&buck2_reg>; + vrf12-supply = <&ldo2_reg>; + reset-gpios = <&mcu_gpio0 13 GPIO_ACTIVE_LOW>; + interrupt-parent = <&mcu_gpio0>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * HDMI can be serviced with 3 potential VPs - + * (DSS0 VP1 / DSS1 VP0 / DSS1 VP1). + * For now, we will service it with DSS0 VP1. + */ + port@0 { + reg = <0>; + + it66122_in: endpoint { + bus-width = <24>; + remote-endpoint = <&dss1_dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + + it66122_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + &sdhci1 { /* SD/MMC */ vmmc-supply = <&vdd_mmc1>; @@ -391,3 +598,147 @@ ti,fails-without-test-cd; status = "okay"; }; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_wkup_r5_0: mbox-wkup-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + + mbox_main_r5_0: mbox-main-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c7x_1: mbox-c7x-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&main_r5fss0 { + status = "okay"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&c7x_0 { + mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status = "okay"; +}; + +&c7x_1 { + mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; + memory-region = <&c7x_1_dma_memory_region>, + <&c7x_1_memory_region>; +}; + +&dss1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dss1_pins_default>; + + clocks = <&k3_clks 232 8>, + <&k3_clks 232 0>, + <&k3_clks 232 4>; + + assigned-clocks = <&k3_clks 241 0>, /* DSS1-VP0 */ + <&k3_clks 240 0>, /* DSS1-VP1 */ + <&k3_clks 245 0>; /* DPI Output */ + + assigned-clock-parents = <&k3_clks 241 2>, /* PLL 17 HDMI */ + <&k3_clks 240 1>, /* PLL 18 DSI */ + <&k3_clks 245 2>; /* DSS1-DPI0 */ +}; + +&dss1_ports { + /* DSS1-VP1: DPI/HDMI Output */ + port@0 { + reg = <0>; + + dss1_dpi0_out: endpoint { + remote-endpoint = <&it66122_in>; + }; + }; +}; + +&mcasp1 { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp1_pins_default>; + auxclk-fs-ratio = <2177>; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts v_kernel/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts 2026-04-21 11:35:28.544915273 +0200 @@ -135,6 +135,35 @@ max-bitrate = <5000000>; }; + edp0_refclk: clock-edp0-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + dp0_pwr_3v3: fixedregulator-dp0-pwr { + compatible = "regulator-fixed"; + regulator-name = "dp0-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; /*P0 - DP0_3V3 _EN */ + enable-active-high; + regulator-always-on; + }; + + dp0: dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; + connector-hdmi { compatible = "hdmi-connector"; label = "hdmi"; @@ -195,6 +224,7 @@ J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ >; + bootph-all; }; main_i2c0_pins_default: main-i2c0-default-pins { @@ -222,6 +252,7 @@ J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ >; + bootph-all; }; vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { @@ -324,6 +355,7 @@ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; + bootph-all; }; mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -341,6 +373,7 @@ J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ >; + bootph-all; }; mcu_mdio_pins_default: mcu-mdio-default-pins { @@ -348,6 +381,7 @@ J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; + bootph-all; }; mcu_mcan0_pins_default: mcu-mcan0-default-pins { @@ -383,6 +417,7 @@ J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ >; + bootph-all; }; mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { @@ -424,6 +459,7 @@ status = "reserved"; pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; + bootph-all; }; &wkup_i2c0 { @@ -506,6 +542,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; + bootph-all; }; &main_uart8 { @@ -514,6 +551,7 @@ pinctrl-0 = <&main_uart8_pins_default>; /* Shared with TFA on this platform */ power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; + bootph-all; }; &main_i2c0 { @@ -598,6 +636,39 @@ gpio-line-names = "HDMI_PDn","HDMI_LS_OE", "DP0_3V3_EN","eDP_ENABLE"; }; + + dsi_edp_bridge: dsi-edp-bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + clock-names = "refclk"; + clocks = <&edp0_refclk>; + enable-gpios = <&exp2 3 GPIO_ACTIVE_HIGH>; + vpll-supply = <&vsys_io_1v8>; + vccio-supply = <&vsys_io_1v8>; + vcca-supply = <&vsys_io_1v2>; + vcc-supply = <&vsys_io_1v2>; + + dsi_edp_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dp0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; + }; + }; }; &main_sdhci1 { @@ -608,6 +679,7 @@ disable-wp; vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv>; + bootph-all; }; &mcu_cpsw { @@ -618,6 +690,7 @@ &davinci_mdio { phy0: ethernet-phy@0 { reg = <0>; + bootph-all; ti,rx-internal-delay = ; ti,fifo-depth = ; ti,min-output-impedance; @@ -691,6 +764,15 @@ remote-endpoint = <&tfp410_in>; }; }; + + /* DSI */ + port@2 { + reg = <2>; + + dpi0_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; }; &serdes_ln_ctrl { @@ -748,3 +830,28 @@ phys = <&serdes0_usb_link>; phy-names = "cdns3,usb3-phy"; }; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_ports { + + port@0 { + reg = <0>; + dsi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; + + port@1 { + reg = <1>; + dsi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso 2026-04-21 11:35:28.544915273 +0200 @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the + * AM68-SK board. + * + * AM68-SK Board Product Link: https://www.ti.com/tool/SK-AM68 + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie1_rc { + status = "disabled"; +}; + +&cbass_main { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 41>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am68-sk-bb-csi2-ov5640.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am68-sk-bb-csi2-ov5640.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am68-sk-bb-csi2-ov5640.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am68-sk-bb-csi2-ov5640.dtso 2026-04-21 11:35:28.545915275 +0200 @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * LI OV5640 MIPI Camera module. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&cam0_i2c { + #address-cells = <1>; + #size-cells = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + powerdown-gpios = <&exp3 2 GPIO_ACTIVE_LOW>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi 2026-04-21 11:35:28.545915275 +0200 @@ -22,6 +22,14 @@ #size-cells = <2>; ranges; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x38000000>; + linux,cma-default; + }; + secure_ddr: optee@9e800000 { reg = <0x00 0x9e800000 0x00 0x01800000>; no-map; @@ -156,6 +164,7 @@ J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ >; + bootph-all; }; }; @@ -169,6 +178,7 @@ /* AT24C512C-MAHM-T */ compatible = "atmel,24c512"; reg = <0x51>; + bootph-all; }; }; @@ -190,7 +200,6 @@ cdns,read-delay = <4>; partitions { - bootph-all; compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; @@ -226,9 +235,9 @@ }; partition@3fc0000 { - bootph-pre-ram; label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; + bootph-all; }; }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion.dtso 2026-04-21 11:35:28.545915275 +0200 @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Arducam V3Link UC-A09 board + * https://www.arducam.com/fpd-link-3-cameras/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&csi_mux { + idle-state = <1>; +}; + +&cam0_i2c { + #address-cells = <1>; + #size-cells = <0>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&cam1_i2c { + #address-cells = <1>; + #size-cells = <0>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + deserializer_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + deserializer_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; \ No newline at end of file diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion-dual-csitx.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion-dual-csitx.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion-dual-csitx.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion-dual-csitx.dtso 2026-04-21 11:35:28.545915275 +0200 @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Arducam V3Link UC-A09 board + * https://www.arducam.com/fpd-link-3-cameras/ + * + * Copyright (c) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + + +/dts-v1/; +/plugin/; + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&csi_mux { + idle-state = <1>; +}; + +&cam0_i2c { + #address-cells = <1>; + #size-cells = <0>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&cam1_i2c { + #address-cells = <1>; + #size-cells = <0>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + deserializer_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@5 { + reg = <5>; + ds90ub960_1_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + deserializer_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am69-sk-csi2-ov5640.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am69-sk-csi2-ov5640.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am69-sk-csi2-ov5640.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am69-sk-csi2-ov5640.dtso 2026-04-21 11:35:28.545915275 +0200 @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for OV5640 Camera module on MIPI CSI connector for AM69 SK board. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&cam0_i2c { + #address-cells = <1>; + #size-cells = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + powerdown-gpios = <&exp2 2 GPIO_ACTIVE_LOW>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am69-sk.dts v_kernel/arch/arm64/boot/dts/ti/k3-am69-sk.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am69-sk.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am69-sk.dts 2026-04-21 11:35:28.546915278 +0200 @@ -44,6 +44,14 @@ #size-cells = <2>; ranges; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x70000000>; + linux,cma-default; + }; + secure_ddr: optee@9e800000 { reg = <0x00 0x9e800000 0x00 0x01800000>; no-map; @@ -368,8 +376,8 @@ main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < - J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ - J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ + J784S4_IOPAD(0x0e0, PIN_INPUT, 0) /* (AN36) I2C0_SCL */ + J784S4_IOPAD(0x0e4, PIN_INPUT, 0) /* (AP37) I2C0_SDA */ >; }; @@ -484,6 +492,12 @@ >; }; + main_usbss0_pins_default: main-usbss0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ + >; + }; + }; &wkup_pmx0 { @@ -542,8 +556,8 @@ mcu_i2c0_pins_default: mcu-i2c0-default-pins { pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */ - J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */ + J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (M35) MCU_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (G34) MCU_I2C0_SDA */ >; }; @@ -562,6 +576,7 @@ J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ >; + bootph-all; }; mcu_mdio_pins_default: mcu-mdio-default-pins { @@ -569,6 +584,7 @@ J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ >; + bootph-all; }; mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins { @@ -755,6 +771,7 @@ regulator-max-microvolt = <1100000>; regulator-boot-on; regulator-always-on; + bootph-all; }; bucka3: buck3 { @@ -763,6 +780,7 @@ regulator-max-microvolt = <850000>; regulator-boot-on; regulator-always-on; + bootph-all; }; bucka4: buck4 { @@ -771,6 +789,7 @@ regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; bucka5: buck5 { @@ -779,6 +798,7 @@ regulator-max-microvolt = <850000>; regulator-boot-on; regulator-always-on; + bootph-all; }; ldoa1: ldo1 { @@ -787,6 +807,7 @@ regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; ldoa2: ldo2 { @@ -795,6 +816,7 @@ regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; + bootph-all; }; ldoa3: ldo3 { @@ -803,6 +825,7 @@ regulator-max-microvolt = <800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; ldoa4: ldo4 { @@ -811,6 +834,7 @@ regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; }; }; @@ -954,6 +978,7 @@ &davinci_mdio { mcu_phy0: ethernet-phy@0 { reg = <0>; + bootph-all; ti,rx-internal-delay = ; ti,fifo-depth = ; ti,min-output-impedance; @@ -964,6 +989,7 @@ status = "okay"; phy-mode = "rgmii-rxid"; phy-handle = <&mcu_phy0>; + bootph-all; }; &mcu_r5fss0_core0 { @@ -1131,6 +1157,7 @@ reg = <0>; cdns,num-lanes = <4>; #phy-cells = <0>; + cdns,max-bit-rate = <2700>; cdns,phy-type = ; resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, <&serdes_wiz4 3>, <&serdes_wiz4 4>; @@ -1215,6 +1242,11 @@ phys = <&transceiver4>; }; +&fss { + bootph-all; + status = "okay"; +}; + &ospi0 { status = "okay"; pinctrl-names = "default"; @@ -1231,6 +1263,7 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + cdns,phy-mode; partitions { bootph-all; @@ -1269,7 +1302,7 @@ }; partition@3fc0000 { - bootph-pre-ram; + bootph-all; label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; }; @@ -1280,8 +1313,12 @@ &serdes_ln_ctrl { idle-states = , , , , - , , - , ; + , , + , , + , , + , , + , , + , ; }; &serdes_wiz0 { @@ -1291,12 +1328,28 @@ &serdes0 { status = "okay"; - serdes0_pcie_link: phy@0 { + serdes0_pcie_link1: phy@0 { reg = <0>; - cdns,num-lanes = <3>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + + serdes0_pcie_link2: phy@2 { + reg = <2>; + cdns,num-lanes = <1>; #phy-cells = <0>; cdns,phy-type = ; - resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>; + resets = <&serdes_wiz0 3>; + }; + + serdes0_usb_link: phy@3 { + reg = <3>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 4>; }; }; @@ -1326,7 +1379,7 @@ &pcie1_rc { status = "okay"; reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; + phys = <&serdes0_pcie_link1>; phy-names = "pcie-phy"; num-lanes = <2>; }; @@ -1334,7 +1387,34 @@ &pcie3_rc { status = "okay"; reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; + phys = <&serdes0_pcie_link2>; phy-names = "pcie-phy"; num-lanes = <1>; }; + +&usb_serdes_mux { + idle-states = <0>; /* USB0 to SERDES0 */ +}; + +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; +}; + +&usb0 { + status = "okay"; + dr_mode = "otg"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&phy_gmii_sel { + bootph-all; +}; + +&mcu_udmap { + bootph-all; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am69-sk-fpdlink-fusion-auxport.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am69-sk-fpdlink-fusion-auxport.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am69-sk-fpdlink-fusion-auxport.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am69-sk-fpdlink-fusion-auxport.dtso 2026-04-21 11:35:28.545915275 +0200 @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Fusion (FPD-Link III) board on AM69 SK CSI2 Aux Port + * https://svtronics.com/portfolio/evm577pfusion-v1-0-fusion/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + clk_fusion1_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&cam1_i2c { + #address-cells = <1>; + #size-cells = <0>; + + deser@3d { + compatible = "ti,ds90ub960-q1"; + reg = <0x3d>; + clocks = <&clk_fusion1_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x6a 0x6b 0x6c 0x6d 0x6e 0x6f>; + + ds90ub960_2_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX*/ + port@4 { + reg = <4>; + ds90ub960_2_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy2>; + }; + }; + }; + + ds90ub960_2_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + port@0 { + status = "okay"; + + csi2_phy2: endpoint { + remote-endpoint = <&ds90ub960_2_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx2 { + status = "okay"; +}; + +&dphy_rx2 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtso v_kernel/arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtso 2026-04-21 11:35:28.545915275 +0200 @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling PCIE0 instances of PCIe in Endpoint Configuration + * on AM69-SK. + * + * AM69-SK Product Link: https://www.ti.com/tool/SK-AM69 + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie0_rc { + status = "disabled"; +}; + +&cbass_main { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + + pcie0_ep: pcie-ep@2900000 { + compatible = "ti,j784s4-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 332 0>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-cm-0-0.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-cm-0-0.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-cm-0-0.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-cm-0-0.dtso 2026-04-21 11:35:28.547915280 +0200 @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * Copyright (c) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 0 */ + port@0 { + reg = <0>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@0 { + reg = <0>; + i2c-alias = <0x44>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@21 { + compatible = "sony,imx390"; + reg = <0x21>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 0 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 1 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-cm-0-1.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-cm-0-1.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-cm-0-1.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-cm-0-1.dtso 2026-04-21 11:35:28.547915280 +0200 @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * Copyright (c) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 1 */ + port@1 { + reg = <1>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@1 { + reg = <1>; + i2c-alias = <0x45>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@21 { + compatible = "sony,imx390"; + reg = <0x21>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 0 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 1 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; + diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-0.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-0.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-0.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-0.dtso 2026-04-21 11:35:28.547915280 +0200 @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 0 */ + port@0 { + reg = <0>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@0 { + reg = <0>; + i2c-alias = <0x44>; + + ti,rx-mode = <3>; + ti,cdr-mode = <0>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-1.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-1.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-1.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-1.dtso 2026-04-21 11:35:28.547915280 +0200 @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 1 */ + port@1 { + reg = <1>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@1 { + reg = <1>; + i2c-alias = <0x45>; + + ti,rx-mode = <3>; + ti,cdr-mode = <0>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-2.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-2.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-2.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-2.dtso 2026-04-21 11:35:28.547915280 +0200 @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 2 */ + port@2 { + reg = <2>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@2 { + reg = <2>; + i2c-alias = <0x46>; + + ti,rx-mode = <3>; + ti,cdr-mode = <0>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-3.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-3.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-3.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-3.dtso 2026-04-21 11:35:28.547915280 +0200 @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 3 */ + port@3 { + reg = <3>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@3 { + reg = <3>; + i2c-alias = <0x47>; + + ti,rx-mode = <3>; + ti,cdr-mode = <0>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-0.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-0.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-0.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-0.dtso 2026-04-21 11:35:28.547915280 +0200 @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 0 */ + port@0 { + reg = <0>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_1_links { + #address-cells = <1>; + #size-cells = <0>; + + link@0 { + reg = <0>; + i2c-alias = <0x54>; + + ti,cdr-mode = <0>; + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-1.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-1.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-1.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-1.dtso 2026-04-21 11:35:28.547915280 +0200 @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 1 */ + port@1 { + reg = <1>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_1_links { + #address-cells = <1>; + #size-cells = <0>; + + link@1 { + reg = <1>; + i2c-alias = <0x55>; + + ti,rx-mode = <3>; + ti,cdr-mode = <0>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-2.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-2.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-2.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-2.dtso 2026-04-21 11:35:28.548915283 +0200 @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 2 */ + port@2 { + reg = <2>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_1_links { + #address-cells = <1>; + #size-cells = <0>; + + link@2 { + reg = <2>; + i2c-alias = <0x56>; + + ti,rx-mode = <3>; + ti,cdr-mode = <0>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-3.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-3.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-3.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-3.dtso 2026-04-21 11:35:28.548915283 +0200 @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 3 */ + port@3 { + reg = <3>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_1_links { + #address-cells = <1>; + #size-cells = <0>; + + link@3 { + reg = <3>; + i2c-alias = <0x57>; + + ti,rx-mode = <3>; + ti,cdr-mode = <0>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-0.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-0.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-0.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-0.dtso 2026-04-21 11:35:28.548915283 +0200 @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_2_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 0 */ + port@0 { + reg = <0>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_2_links { + #address-cells = <1>; + #size-cells = <0>; + + link@0 { + reg = <0>; + i2c-alias = <0x64>; + + ti,rx-mode = <3>; + ti,cdr-mode = <0>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-1.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-1.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-1.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-1.dtso 2026-04-21 11:35:28.548915283 +0200 @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_2_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 1 */ + port@1 { + reg = <1>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_2_links { + #address-cells = <1>; + #size-cells = <0>; + + link@1 { + reg = <1>; + i2c-alias = <0x65>; + + ti,rx-mode = <3>; + ti,cdr-mode = <0>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-2.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-2.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-2.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-2.dtso 2026-04-21 11:35:28.548915283 +0200 @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_2_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 2 */ + port@2 { + reg = <2>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_2_links { + #address-cells = <1>; + #size-cells = <0>; + + link@2 { + reg = <2>; + i2c-alias = <0x66>; + + ti,rx-mode = <3>; + ti,cdr-mode = <0>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-3.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-3.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-3.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-3.dtso 2026-04-21 11:35:28.548915283 +0200 @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_2_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 3 */ + port@3 { + reg = <3>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_2_links { + #address-cells = <1>; + #size-cells = <0>; + + link@3 { + reg = <3>; + i2c-alias = <0x67>; + + ti,rx-mode = <3>; + ti,cdr-mode = <0>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx728-rcm-0-0.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx728-rcm-0-0.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-imx728-rcm-0-0.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-imx728-rcm-0-0.dtso 2026-04-21 11:35:28.548915283 +0200 @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * D3 IMX728 FPD-Link 4 Camera Module + * + * Copyright (c) 2024 Define Design Deploy Corp - https://www.d3embedded.com + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx728_fixed_00: imx728-inck-00 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 0 */ + port@0 { + reg = <0>; + ub9702_fpd4_1_in: endpoint { + remote-endpoint = <&ub971_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@0 { + reg = <0>; + i2c-alias = <0x44>; + + ti,cdr-mode = <1>; + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub971-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub971_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub971_1_out: endpoint { + remote-endpoint = <&ub9702_fpd4_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sens_exp: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "IMG_RESET", "IMG_ERR0", + "IMG_ERR1", "IMG_GPI0", + "IMG_GPI1", "NC", + "NC", "NC"; + }; + + sensor@1a { + compatible = "sony,imx728"; + reg = <0x1a>; + + clocks = <&clk_imx728_fixed_00>; + clock-names = "inck"; + + reset-gpios = <&sens_exp 0 GPIO_ACTIVE_LOW>; + error0-gpios = <&sens_exp 1 GPIO_ACTIVE_HIGH>; + error1-gpios = <&sens_exp 2 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub971_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-0.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-0.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-0.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-0.dtso 2026-04-21 11:35:28.549915286 +0200 @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 0 */ + port@0 { + reg = <0>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@0 { + reg = <0>; + i2c-alias = <0x44>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2>; + /*clock-noncontinuous;*/ + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@60 { + compatible = "ovti,ov2312"; + reg = <0x60>; + + clocks = <&serializer>; + clock-names = "xvclk"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <24000000>; + + reset-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-1.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-1.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-1.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-1.dtso 2026-04-21 11:35:28.549915286 +0200 @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 1 */ + port@1 { + reg = <1>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@1 { + reg = <1>; + i2c-alias = <0x45>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2>; + /*clock-noncontinuous;*/ + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@60 { + compatible = "ovti,ov2312"; + reg = <0x60>; + + clocks = <&serializer>; + clock-names = "xvclk"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <24000000>; + + reset-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-2.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-2.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-2.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-2.dtso 2026-04-21 11:35:28.549915286 +0200 @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 2 */ + port@2 { + reg = <2>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@2 { + reg = <2>; + i2c-alias = <0x46>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2>; + /*clock-noncontinuous;*/ + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@60 { + compatible = "ovti,ov2312"; + reg = <0x60>; + + clocks = <&serializer>; + clock-names = "xvclk"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <24000000>; + + reset-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-3.dtso v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-3.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-3.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-3.dtso 2026-04-21 11:35:28.549915286 +0200 @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 3 */ + port@3 { + reg = <3>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@3 { + reg = <3>; + i2c-alias = <0x47>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2>; + /*clock-noncontinuous;*/ + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@60 { + compatible = "ovti,ov2312"; + reg = <0x60>; + + clocks = <&serializer>; + clock-names = "xvclk"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <24000000>; + + reset-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts v_kernel/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts 2026-04-21 11:35:28.549915286 +0200 @@ -11,6 +11,7 @@ #include #include "k3-serdes.h" +#include "k3-timesync-router.h" / { compatible = "ti,j7200-evm", "ti,j7200"; @@ -129,6 +130,7 @@ J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ >; + bootph-all; }; wkup_uart0_pins_default: wkup-uart0-default-pins { @@ -136,6 +138,7 @@ J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ >; + bootph-all; }; mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -204,6 +207,7 @@ J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ >; + bootph-all; }; main_uart1_pins_default: main-uart1-default-pins { @@ -238,6 +242,7 @@ J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ >; + bootph-all; }; vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { @@ -259,6 +264,7 @@ pinctrl-single,pins = < J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ >; + bootph-all; }; }; @@ -267,12 +273,14 @@ status = "reserved"; pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; + bootph-all; }; &mcu_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; + bootph-all; }; &main_uart0 { @@ -281,6 +289,7 @@ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + bootph-all; }; &main_uart1 { @@ -315,6 +324,11 @@ &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + + cpts@3d000 { + /* Map HW4_TS_PUSH to GENF1 */ + ti,pps = <3 1>; + }; }; &davinci_mdio { @@ -379,6 +393,7 @@ /* eMMC */ status = "okay"; non-removable; + bootph-all; ti,driver-strength-ohm = <50>; disable-wp; }; @@ -390,6 +405,7 @@ pinctrl-names = "default"; vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv>; + bootph-all; ti,driver-strength-ohm = <50>; disable-wp; }; @@ -399,13 +415,19 @@ , ; }; +&mcu_spi1 { + mux-controls = <&spi1_linkdis 0>; +}; + &usb_serdes_mux { idle-states = <1>; /* USB0 to SERDES lane 3 */ + bootph-all; }; &usbss0 { pinctrl-names = "default"; pinctrl-0 = <&main_usbss0_pins_default>; + bootph-all; ti,vbus-divider; ti,usb2-only; }; @@ -413,6 +435,7 @@ &usb0 { dr_mode = "otg"; maximum-speed = "high-speed"; + bootph-all; }; &tscadc0 { @@ -471,3 +494,12 @@ pinctrl-0 = <&main_mcan3_pins_default>; phys = <&transceiver3>; }; + +×ync_router { + /* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */ + mux-reg-masks-state = < + /* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */ + K3_TS_OFFSET(25, 0x0001ffff, 17) + >; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j7200-evm-ethfw.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j7200-evm-ethfw.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j7200-evm-ethfw.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j7200-evm-ethfw.dtso 2026-04-21 11:35:28.550915288 +0200 @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for CPSW5G functionality with Ethernet Switch Firmware (EthFw) + * and CPSW Proxy Client driver. + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +/* uart2 is assigned to EthFw running on remote CPU core */ +&main_uart2 { + status = "reserved"; +}; + +/* Reserve shared memory for inter-core network communication */ +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + + main_r5fss0_core0_shared_memory_queue_region:r5f-virtual-eth-queues@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x200000>; + no-map; + }; + + main_r5fss0_core0_shared_memory_bufpool_region:r5f-virtual-eth-buffers@a5200000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5200000 0x00 0x1e00000>; + no-map; + }; +}; + +&main_r5fss0_core0 { + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>, + <&main_r5fss0_core0_shared_memory_queue_region>, + <&main_r5fss0_core0_shared_memory_bufpool_region>; +}; + +/* EthFw uses timers so mark them reserved */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&main_timer3 { + status = "reserved"; +}; + +&main_timer4 { + status = "reserved"; +}; + +&main_timer5 { + status = "reserved"; +}; + +&main_timer6 { + status = "reserved"; +}; + +&main_timer7 { + status = "reserved"; +}; + +&main_timer8 { + status = "reserved"; +}; + +&main_timer9 { + status = "reserved"; +}; + +&main_timer10 { + status = "reserved"; +}; + +&main_timer11 { + status = "reserved"; +}; + +&main_timer12 { + status = "reserved"; +}; + +&main_timer13 { + status = "reserved"; +}; + +&main_timer14 { + status = "reserved"; +}; + +&main_timer15 { + status = "reserved"; +}; + +&main_timer16 { + status = "reserved"; +}; + +&main_timer17 { + status = "reserved"; +}; + +&main_timer18 { + status = "reserved"; +}; + +&main_timer19 { + status = "reserved"; +}; + +/* EthFw configures pin W16 (MCAN3_RX) for PPS demo */ +&main_mcan3 { + status = "disabled"; +}; + +&transceiver3 { + status = "disabled"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j7200-evm-mcspi-loopback.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j7200-evm-mcspi-loopback.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j7200-evm-mcspi-loopback.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j7200-evm-mcspi-loopback.dtso 2026-04-21 11:35:28.550915288 +0200 @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MCSPI internal master-slave loopback example overlay for J7200. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * J7200 has MCSPI4 connected as master to MCU_MCSPI2 by default and not + * pinned out to external pads, This overlay enables spidev on these + * interfaces for userspace testing. + */ + +/dts-v1/; +/plugin/; + +&main_spi4 { + status = "okay"; + #address-cells = <0>; + #size-cells = <0>; + spi-slave; + dmas = <&main_udmap 0xc610>, <&main_udmap 0x4610>; + dma-names = "tx0", "rx0"; + + slave { + /* + * Using spidev compatible is warned loudly, + * thus use another equivalent compatible id + * from spidev. + */ + compatible = "rohm,dh2228fv"; + spi-max-frequency = <24000000>; + }; +}; + +&mcu_spi2 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + spidev@0 { + /* + * Using spidev compatible is warned loudly, + * thus use another equivalent compatible id + * from spidev. + */ + compatible = "rohm,dh2228fv"; + spi-max-frequency = <24000000>; + reg = <0>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso 2026-04-21 11:35:28.550915288 +0200 @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the + * J7 common processor board. + * + * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie1_rc { + status = "disabled"; +}; + +&cbass_main { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 6>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi 2026-04-21 11:35:28.551915291 +0200 @@ -25,13 +25,17 @@ }; }; - scm_conf: scm-conf@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x1c000>; + scm_conf: bus@100000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; + pcie1_ctrl: pcie-ctrl@4074 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4074 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x4080 0x20>; @@ -136,6 +140,7 @@ <0x00 0x32800000 0x00 0x100000>; interrupt-names = "rx_011"; interrupts = ; + bootph-all; }; hwspinlock: spinlock@30e00000 { @@ -758,12 +763,12 @@ reg = <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; + <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; max-link-speed = <3>; num-lanes = <4>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; @@ -777,8 +782,8 @@ device-id = <0xb00f>; msi-map = <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status = "disabled"; }; @@ -1545,6 +1550,35 @@ main_esm: esm@700000 { compatible = "ti,j721e-esm"; reg = <0x0 0x700000 0x0 0x1000>; + bootph-pre-ram; ti,esm-pins = <656>, <657>; }; + + timesync_router: mux-controller@a40000 { + compatible = "reg-mux"; + reg = <0x0 0xa40000 0x0 0x800>; + #mux-control-cells = <1>; + status = "disabled"; + }; + + memorycontroller: memory-controller@2980000 { + compatible = "ti,j7-ddrss"; + reg = <0x00 0x02980000 0x00 0x184>; + reg-names = "ss_cfg"; + ranges = <0x00 0x00 0x00 0x02990000 0x00 0x00004000>; + interrupts = ; + power-domains = <&k3_pds 8 TI_SCI_PD_SHARED>, + <&k3_pds 90 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 8 0>, <&k3_clks 30 9>; + #address-cells = <2>; + #size-cells = <2>; + + ddr: ddr@0 { + compatible = "cdns,j7-ddr"; + reg = <0x00 0x0000 0x00 0x72c>, + <0x00 0x2000 0x00 0x4b0>, + <0x00 0x4000 0x00 0x163c>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + }; + }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi 2026-04-21 11:35:28.551915291 +0200 @@ -21,16 +21,19 @@ k3_pds: power-controller { compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; + bootph-all; }; k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; + bootph-all; }; k3_reset: reset-controller { compatible = "ti,sci-reset"; #reset-cells = <2>; + bootph-all; }; }; @@ -44,6 +47,7 @@ assigned-clocks = <&k3_clks 35 1>; assigned-clock-parents = <&k3_clks 35 2>; power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-pre-ram; ti,timer-pwm; }; @@ -180,6 +184,13 @@ reg = <0x4040 0x4>; #phy-cells = <1>; }; + + spi1_linkdis: mux-controller@4060 { + compatible = "reg-mux"; + reg = <0x4060 0x4>; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x1>; + }; }; wkup_conf: bus@43000000 { @@ -191,6 +202,7 @@ chipid: chipid@14 { compatible = "ti,am654-chipid"; reg = <0x14 0x4>; + bootph-all; }; }; @@ -344,6 +356,7 @@ <0x00 0x28440000 0x00 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + bootph-all; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; @@ -363,6 +376,7 @@ "tchan", "rchan", "rflow"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; + bootph-all; ti,sci = <&dmsc>; ti,sci-dev-id = <236>; @@ -383,6 +397,8 @@ reg = <0x0 0x2a480000 0x0 0x80000>, <0x0 0x2a380000 0x0 0x80000>, <0x0 0x2a400000 0x0 0x80000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -534,6 +550,7 @@ reg = <0x00 0x47000004 0x00 0x4>; #mux-control-cells = <1>; mux-reg-masks = <0x0 0x2>; /* HBMC select */ + bootph-all; }; hbmc: hyperbus@47034000 { @@ -557,6 +574,7 @@ cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; + cdns,phase-detect-selector = <2>; clocks = <&k3_clks 103 0>; assigned-clocks = <&k3_clks 103 0>; assigned-clock-parents = <&k3_clks 103 2>; @@ -589,7 +607,7 @@ mcu_r5fss0: r5fss@41000000 { compatible = "ti,j7200-r5fss"; - ti,cluster-mode = <1>; + ti,cluster-mode = <0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x41000000 0x00 0x41000000 0x20000>, @@ -652,6 +670,7 @@ <0x00 0x42050000 0x00 0x350>; power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; + bootph-pre-ram; }; mcu_esm: esm@40800000 { diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi 2026-04-21 11:35:28.551915291 +0200 @@ -121,6 +121,7 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ >; + bootph-all; }; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { @@ -137,6 +138,7 @@ J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ >; + bootph-all; }; }; @@ -146,6 +148,7 @@ J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ >; + bootph-all; }; }; @@ -186,6 +189,7 @@ flash@0,0 { compatible = "cypress,hyperflash", "cfi-flash"; reg = <0x00 0x00 0x4000000>; + bootph-all; partitions { compatible = "fixed-partitions"; @@ -347,6 +351,7 @@ regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; bucka2: buck2 { @@ -481,6 +486,7 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + cdns,phy-mode; partitions { compatible = "fixed-partitions"; @@ -520,6 +526,7 @@ partition@3fc0000 { label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; + bootph-all; }; }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-dsi-rpi-7inch-panel.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-dsi-rpi-7inch-panel.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-dsi-rpi-7inch-panel.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-dsi-rpi-7inch-panel.dtso 2026-04-21 11:35:28.552915294 +0200 @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * DT Overlay for RPi 7inch touchscreen panel interfaced with DSI on + * J721E based BeagleBone AI-64 (BBAI-64) platform. + * + * BBAI-64: https://www.beagleboard.org/boards/beaglebone-ai-64 + * RPi DSI Panel: https://www.raspberrypi.com/products/raspberry-pi-touch-display/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + bridge_reg: bridge-regulator { + compatible = "regulator-fixed"; + regulator-name = "bridge-reg"; + gpio = <&display_reg 0 0>; + vin-supply = <&display_reg>; + enable-active-high; + }; + + panel0 { + compatible = "raspberrypi,7inch-dsi", "simple-panel"; + backlight = <&display_reg>; + power-supply = <&display_reg>; + port { + panel_in: endpoint { + remote-endpoint = <&panel_bridge_out>; + }; + }; + }; +}; + +&main_pmx0 { + dsi_main_i2c4_pins: dsi-main-i2c4-pins { + pinctrl-single,pins = < + J721E_IOPAD(0xa8, PIN_INPUT_PULLUP, 2) /* (AD19) PRG1_MDIO0_MDIO.I2C4_SCL */ + J721E_IOPAD(0xac, PIN_INPUT_PULLUP, 2) /* (AD18) PRG1_MDIO0_MDC.I2C4_SDA */ + >; + }; +}; + +&main_i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi_main_i2c4_pins>; + #address-cells = <1>; + #size-cells = <0>; + + display_reg: regulator@45 { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + }; + + touch-controller@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + + touchscreen-size-x = < 800 >; + touchscreen-size-y = < 480 >; + + vcc-supply = <&display_reg>; + reset-gpio = <&display_reg 1 1>; + + touchscreen-inverted-x; + touchscreen-inverted-y; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&dphy2 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_out: endpoint { + remote-endpoint = <&panel_bridge_in>; + }; + }; + + port@1 { + reg = <1>; + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; + }; + + bridge@0 { + compatible = "toshiba,tc358762"; + reg = <0>; + vddc-supply = <&bridge_reg>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + panel_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts v_kernel/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts 2026-04-21 11:35:28.552915294 +0200 @@ -698,7 +698,7 @@ resets = <&serdes_wiz4 1>; cdns,phy-type = ; cdns,num-lanes = <4>; - cdns,max-bit-rate = <5400>; + cdns,max-bit-rate = <2700>; #phy-cells = <0>; }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-microtips-mf070zima-lcd3.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-microtips-mf070zima-lcd3.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-microtips-mf070zima-lcd3.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-microtips-mf070zima-lcd3.dtso 2026-04-21 11:35:28.552915294 +0200 @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * DT Overlay for Microtips SK-LCD3 interfaced with DSI on + * J721E based BeagleBone AI-64 (BBAI-64) platform. + * + * BBAI-64: https://www.beagleboard.org/boards/beaglebone-ai-64 + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&main_pmx0 { + dsi_main_i2c4_pins: dsi-main-i2c4-pins { + pinctrl-single,pins = < + J721E_IOPAD(0xa8, PIN_INPUT_PULLUP, 2) /* (AD19) PRG1_MDIO0_MDIO.I2C4_SCL */ + J721E_IOPAD(0xac, PIN_INPUT_PULLUP, 2) /* (AD18) PRG1_MDIO0_MDC.I2C4_SDA */ + >; + }; + + dsi0_gpio_pins_default: dsi0-gpio-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x18c, PIN_OUTPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ + J721E_IOPAD(0x1b4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ + >; + }; +}; + +&main_i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi_main_i2c4_pins>; + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_gpio_pins_default>; + reset-gpios = <&main_gpio0 98 GPIO_ACTIVE_LOW>; + interrupt-parent = <&main_gpio0>; + interrupts = <108 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&dphy2 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + + port@1 { + reg = <1>; + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; + }; + + dsi_panel0: panel-dsi@0 { + compatible = "microtips,mf-070zimacaa0", "ilitek,ili9881c"; + reg = <0>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts v_kernel/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts 2026-04-21 11:35:28.553915296 +0200 @@ -13,6 +13,8 @@ #include #include +#include "k3-timesync-router.h" + / { compatible = "ti,j721e-evm", "ti,j721e"; model = "Texas Instruments J721e EVM"; @@ -193,6 +195,7 @@ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; + bootph-all; }; main_uart1_pins_default: main-uart1-default-pins { @@ -234,6 +237,7 @@ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ >; + bootph-all; }; vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { @@ -247,6 +251,7 @@ J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; + bootph-all; }; main_usbss1_pins_default: main-usbss1-default-pins { @@ -342,6 +347,7 @@ J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ >; + bootph-all; }; mcu_uart0_pins_default: mcu-uart0-default-pins { @@ -351,6 +357,7 @@ J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ >; + bootph-all; }; sw11_button_pins_default: sw11-button-default-pins { @@ -370,6 +377,7 @@ J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ >; + bootph-all; }; mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -435,12 +443,14 @@ status = "reserved"; pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; + bootph-all; }; &mcu_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; + bootph-all; }; &main_uart0 { @@ -449,6 +459,7 @@ pinctrl-0 = <&main_uart0_pins_default>; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; + bootph-all; }; &main_uart1 { @@ -487,6 +498,7 @@ /* eMMC */ status = "okay"; non-removable; + bootph-all; ti,driver-strength-ohm = <50>; disable-wp; }; @@ -498,12 +510,14 @@ vqmmc-supply = <&vdd_sd_dv_alt>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; + bootph-all; ti,driver-strength-ohm = <50>; disable-wp; }; &usb_serdes_mux { idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ + bootph-all; }; &serdes_ln_ctrl { @@ -513,6 +527,7 @@ , , , , , ; + bootph-all; }; &serdes_wiz3 { @@ -533,6 +548,7 @@ &usbss0 { pinctrl-names = "default"; pinctrl-0 = <&main_usbss0_pins_default>; + bootph-all; ti,vbus-divider; }; @@ -541,6 +557,7 @@ maximum-speed = "super-speed"; phys = <&serdes3_usb_link>; phy-names = "cdns3,usb3-phy"; + bootph-all; }; &usbss1 { @@ -555,6 +572,7 @@ }; &ospi1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; status = "okay"; @@ -614,6 +632,7 @@ partition@3fe0000 { label = "qspi.phypattern"; reg = <0x3fe0000 0x20000>; + bootph-all; }; }; }; @@ -752,6 +771,11 @@ &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + + cpts@3d000 { + /* Map HW4_TS_PUSH to GENF1 */ + ti,pps = <3 1>; + }; }; &davinci_mdio { @@ -912,7 +936,7 @@ resets = <&serdes_wiz4 1>; cdns,phy-type = ; cdns,num-lanes = <4>; - cdns,max-bit-rate = <5400>; + cdns,max-bit-rate = <2700>; #phy-cells = <0>; }; }; @@ -975,3 +999,11 @@ pinctrl-0 = <&main_mcan2_pins_default>; phys = <&transceiver4>; }; + +×ync_router { + /* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */ + mux-reg-masks-state = < + K3_TS_OFFSET(25, 0x0001ffff, 17) + >; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j721e.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e.dtsi 2026-04-21 11:35:28.556915304 +0200 @@ -126,6 +126,8 @@ <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ + <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ + <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-evm-csi2-ov5640.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j721e-evm-csi2-ov5640.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-evm-csi2-ov5640.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-evm-csi2-ov5640.dtso 2026-04-21 11:35:28.553915296 +0200 @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LI OV5640 MIPI Camera module on MIPI CSI connector. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&main_i2c6 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + powerdown-gpios = <&exp5 0 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; \ No newline at end of file diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-evm-ethfw.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j721e-evm-ethfw.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-evm-ethfw.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-evm-ethfw.dtso 2026-04-21 11:35:28.553915296 +0200 @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for CPSW9G functionality with Ethernet Switch Firmware (EthFw) + * and CPSW Proxy Client driver. + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-serdes.h" + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , + , ; +}; + +/* uart2 is assigned to EthFw running on remote CPU core */ +&main_uart2 { + status = "reserved"; +}; + +/* Reserve shared memory for inter-core network communication */ +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + + main_r5fss0_core0_shared_memory_queue_region:r5f-virtual-eth-queues@ac000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xac000000 0x00 0x200000>; + no-map; + }; + + main_r5fss0_core0_shared_memory_bufpool_region:r5f-virtual-eth-buffers@ac200000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xac200000 0x00 0x1e00000>; + no-map; + }; +}; + +&main_r5fss0_core0 { + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>, + <&main_r5fss0_core0_shared_memory_queue_region>, + <&main_r5fss0_core0_shared_memory_bufpool_region>; +}; + +/* EthFw uses timers so mark them reserved */ +&main_timer12 { + status = "reserved"; +}; + +&main_timer13 { + status = "reserved"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-evm-fusion.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j721e-evm-fusion.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-evm-fusion.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-evm-fusion.dtso 2026-04-21 11:35:28.553915296 +0200 @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Fusion (FPD-Link III) board on J721E EVM + * https://svtronics.com/portfolio/evm577pfusion-v1-0-fusion/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + + +&main_i2c6 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + deser@3d { + compatible = "ti,ds90ub960-q1"; + reg = <0x3d>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + deser@36 { + compatible = "ti,ds90ub960-q1"; + reg = <0x36>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + deserializer_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + deserializer_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; \ No newline at end of file diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso 2026-04-21 11:35:28.554915299 +0200 @@ -38,7 +38,7 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; max-link-speed = <3>; num-lanes = <1>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso 2026-04-21 11:35:28.554915299 +0200 @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the + * J7 common processor board. + * + * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie1_rc { + status = "disabled"; +}; + +&cbass_main { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 1>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie-ntb.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie-ntb.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie-ntb.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie-ntb.dtso 2026-04-21 11:35:28.554915299 +0200 @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling NTB functionality using PCIE0 and PCIE1 instances of + * PCIe on the J7 common processor board. + * + * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + epf_bus { + compatible = "pci-epf-bus"; + + ntb { + compatible = "pci-epf-ntb"; + epcs = <&pcie0_ep>, <&pcie1_ep>; + epc-names = "primary", "secondary"; + vendor-id = /bits/ 16 <0x104c>; + device-id = /bits/ 16 <0xb00d>; + num-mws = <4>; + mws-size = <0x100000>, <0x100000>, <0x100000>, <0x100000>; + }; + }; +}; + +&pcie0_rc { + status = "disabled"; +}; + +&pcie1_rc { + status = "disabled"; +}; + +&cbass_main { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + + pcie0_ep: pcie-ep@2900000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + max-link-speed = <3>; + num-lanes = <1>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 1>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-evm-ub954.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j721e-evm-ub954.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-evm-ub954.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-evm-ub954.dtso 2026-04-21 11:35:28.554915299 +0200 @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for DS90UB954-Q1EVM FPDLink-III deserializer board on J721E EVM + * https://www.ti.com/tool/DS90UB954-Q1EVM + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + + +&main_i2c6 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + deser@3d { + compatible = "ti,ds90ub954-q1"; + reg = <0x3d>; + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@2 { + reg = <2>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi 2026-04-21 11:35:28.555915301 +0200 @@ -37,13 +37,32 @@ }; }; - scm_conf: scm-conf@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ + scm_conf: bus@100000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; + pcie0_ctrl: pcie-ctrl@4070 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4070 0x4>; + }; + + pcie1_ctrl: pcie-ctrl@4074 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4074 0x4>; + }; + + pcie2_ctrl: pcie-ctrl@4078 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4078 0x4>; + }; + + pcie3_ctrl: pcie-ctrl@407c { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x407c 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x4080 0x50>; @@ -226,6 +245,7 @@ <0x00 0x32800000 0x00 0x100000>; interrupt-names = "rx_011"; interrupts = ; + bootph-all; }; smmu0: iommu@36600000 { @@ -579,18 +599,27 @@ ranges; #address-cells = <2>; #size-cells = <2>; - dmas = <&main_udmap 0x4940>; - dma-names = "rx0"; + dmas = <&main_udmap 0x4940>, <&main_udmap 0x4941>, <&main_udmap 0x4942>, + <&main_udmap 0x4943>, <&main_udmap 0x4944>, <&main_udmap 0x4945>, + <&main_udmap 0x4946>, <&main_udmap 0x4947>, <&main_udmap 0x4948>, + <&main_udmap 0x4949>, <&main_udmap 0x494a>, <&main_udmap 0x494b>, + <&main_udmap 0x494c>, <&main_udmap 0x494d>, <&main_udmap 0x494e>, + <&main_udmap 0x494f>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15"; power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; cdns_csi2rx0: csi-bridge@4504000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x0 0x4504000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, - <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", - "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; phys = <&dphy0>; phy-names = "dphy"; @@ -632,14 +661,23 @@ ranges; #address-cells = <2>; #size-cells = <2>; - dmas = <&main_udmap 0x4960>; - dma-names = "rx0"; + dmas = <&main_udmap 0x4960>, <&main_udmap 0x4961>, <&main_udmap 0x4962>, + <&main_udmap 0x4963>, <&main_udmap 0x4964>, <&main_udmap 0x4965>, + <&main_udmap 0x4966>, <&main_udmap 0x4967>, <&main_udmap 0x4968>, + <&main_udmap 0x4969>, <&main_udmap 0x496a>, <&main_udmap 0x496b>, + <&main_udmap 0x496c>, <&main_udmap 0x496d>, <&main_udmap 0x496e>, + <&main_udmap 0x496f>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15"; power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; cdns_csi2rx1: csi-bridge@4514000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x0 0x4514000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -940,12 +978,12 @@ reg = <0x00 0x02900000 0x00 0x1000>, <0x00 0x02907000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x00001000>; + <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; @@ -958,8 +996,8 @@ device-id = <0xb00d>; msi-map = <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status = "disabled"; }; @@ -969,12 +1007,12 @@ reg = <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; + <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; @@ -987,8 +1025,8 @@ device-id = <0xb00d>; msi-map = <0x0 &gic_its 0x10000 0x10000>; dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status = "disabled"; }; @@ -1003,7 +1041,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; + ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; @@ -1032,7 +1070,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; + ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; @@ -1807,6 +1845,22 @@ status = "disabled"; }; + vxe384: video-encoder@4200000 { + compatible = "img,vxe384"; + reg = <0x00 0x04200000>, + <0x00 0x100000>; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + interrupts = ; + }; + + d5520: video-decoder@4300000 { + compatible = "img,d5500-vxd"; + reg = <0x00 0x04300000>, + <0x00 0x100000>; + power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; + interrupts = ; + }; + ufs_wrapper: ufs-wrapper@4e80000 { compatible = "ti,j721e-ufs"; reg = <0x0 0x4e80000 0x0 0x100>; @@ -1860,6 +1914,37 @@ }; }; + dphy2: phy@4480000 { + compatible = "ti,j721e-dphy"; + reg = <0x0 0x04480000 0x0 0x1000>; + clocks = <&k3_clks 296 1>, <&k3_clks 296 3>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 296 3>; + assigned-clock-parents = <&k3_clks 296 4>; + assigned-clock-rates = <19200000>; + status = "disabled"; + }; + + dsi0: dsi@48000000 { + compatible = "ti,j721e-dsi"; + reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>; + clocks = <&k3_clks 150 1>, <&k3_clks 150 5>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; + interrupt-parent = <&gic500>; + interrupts = ; + phys = <&dphy2>; + phy-names = "dphy"; + status = "disabled"; + + dsi0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = @@ -2268,6 +2353,13 @@ status = "disabled"; }; + timesync_router: mux-controller@a40000 { + compatible = "reg-mux"; + reg = <0x0 0xa40000 0x0 0x800>; + #mux-control-cells = <1>; + status = "disabled"; + }; + icssg0: icssg@b000000 { compatible = "ti,j721e-icssg"; reg = <0x00 0xb000000 0x00 0x80000>; @@ -2552,6 +2644,19 @@ }; }; + gpu: gpu@4e20000000 { + compatible = "ti,j721e-pvr", "img,pvr-ge8430"; + reg = <0x4e 0x20000000 0x00 0x80000>; + interrupts = ; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + power-domain-names = "firmware", "dust"; + clocks = <&k3_clks 125 0>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-rates = <750000000>; + clock-names = "core"; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, @@ -2853,6 +2958,28 @@ main_esm: esm@700000 { compatible = "ti,j721e-esm"; reg = <0x0 0x700000 0x0 0x1000>; + bootph-pre-ram; ti,esm-pins = <344>, <345>; }; + + memorycontroller: memory-controller@2980000 { + compatible = "ti,j7-ddrss"; + reg = <0x00 0x2980000 0x00 0x184>; + reg-names = "ss_cfg"; + ranges = <0x00 0x00 0x00 0x02990000 0x00 0x0000563c>; + interrupts = ; + power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 47 2>, <&k3_clks 30 9>; + #address-cells = <2>; + #size-cells = <2>; + + ddr: ddr@0 { + compatible = "cdns,j7-ddr"; + reg = <0x00 0x0000 0x00 0x72c>, + <0x00 0x2000 0x00 0x4b0>, + <0x00 0x4000 0x00 0x163c>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + }; + }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi 2026-04-21 11:35:28.555915301 +0200 @@ -21,16 +21,19 @@ k3_pds: power-controller { compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; + bootph-all; }; k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; + bootph-all; }; k3_reset: reset-controller { compatible = "ti,sci-reset"; #reset-cells = <2>; + bootph-all; }; }; @@ -61,6 +64,7 @@ chipid: chipid@14 { compatible = "ti,am654-chipid"; reg = <0x14 0x4>; + bootph-all; }; }; @@ -112,6 +116,7 @@ assigned-clocks = <&k3_clks 35 1>; assigned-clock-parents = <&k3_clks 35 2>; power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-pre-ram; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; @@ -362,6 +367,7 @@ reg = <0x00 0x47000004 0x00 0x4>; #mux-control-cells = <1>; mux-reg-masks = <0x0 0x2>; /* HBMC select */ + bootph-all; }; hbmc: hyperbus@47034000 { @@ -386,6 +392,7 @@ cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; + cdns,phase-detect-selector = <2>; clocks = <&k3_clks 103 0>; assigned-clocks = <&k3_clks 103 0>; assigned-clock-parents = <&k3_clks 103 2>; @@ -404,6 +411,7 @@ cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; + cdns,phase-detect-selector = <2>; clocks = <&k3_clks 104 0>; power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; @@ -470,6 +478,7 @@ <0x0 0x2a500000 0x0 0x40000>, <0x0 0x28440000 0x0 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + bootph-all; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; @@ -489,6 +498,7 @@ "tchan", "rchan", "rflow"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; + bootph-all; ti,sci = <&dmsc>; ti,sci-dev-id = <236>; @@ -509,6 +519,7 @@ reg = <0x0 0x2a480000 0x0 0x80000>, <0x0 0x2a380000 0x0 0x80000>, <0x0 0x2a400000 0x0 0x80000>; + bootph-pre-ram; /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -579,7 +590,7 @@ mcu_r5fss0: r5fss@41000000 { compatible = "ti,j721e-r5fss"; - ti,cluster-mode = <1>; + ti,cluster-mode = <0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x41000000 0x00 0x41000000 0x20000>, @@ -687,6 +698,7 @@ <0x00 0x43000300 0x00 0x10>; power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; + bootph-pre-ram; }; mcu_esm: esm@40800000 { diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-ov5640.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-ov5640.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-ov5640.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-ov5640.dtso 2026-04-21 11:35:28.555915301 +0200 @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LI OV5640 MIPI Camera module on MIPI CSI connector. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&main_pmx0 { + csi2_exp_pins_default: csi2-exp-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x140, PIN_OUTPUT, 7) /* (AG29) PRG0_PRU1_GPO16.GPIO0_79 */ + >; + }; +}; + +&cam0_i2c { + #address-cells = <1>; + #size-cells = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&csi2_exp_pins_default>; + powerdown-gpios = <&main_gpio0 79 GPIO_ACTIVE_LOW>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-sk.dts v_kernel/arch/arm64/boot/dts/ti/k3-j721e-sk.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-sk.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-sk.dts 2026-04-21 11:35:28.556915304 +0200 @@ -42,6 +42,14 @@ #size-cells = <2>; ranges; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x20000000>; + linux,cma-default; + }; + secure_ddr: optee@9e800000 { reg = <0x00 0x9e800000 0x00 0x01800000>; alignment = <0x1000>; @@ -371,6 +379,7 @@ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ >; + bootph-all; }; main_uart0_pins_default: main-uart0-default-pins { @@ -380,6 +389,7 @@ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; + bootph-all; }; main_uart1_pins_default: main-uart1-default-pins { @@ -415,12 +425,14 @@ J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; + bootph-all; }; main_usbss1_pins_default: main-usbss1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; + bootph-all; }; main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { @@ -619,6 +631,7 @@ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ >; + bootph-all; }; vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins { @@ -653,6 +666,7 @@ J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ >; + bootph-all; }; wkup_i2c0_pins_default: wkup-i2c0-default-pins { @@ -660,6 +674,7 @@ J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; + bootph-all; }; mcu_mcan0_pins_default: mcu-mcan0-default-pins { @@ -688,6 +703,7 @@ status = "reserved"; pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; + bootph-all; }; &wkup_i2c0 { @@ -852,6 +868,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; + bootph-all; }; &main_uart0 { @@ -860,6 +877,7 @@ pinctrl-0 = <&main_uart0_pins_default>; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; + bootph-all; }; &main_uart1 { @@ -875,6 +893,7 @@ vqmmc-supply = <&vdd_sd_dv_alt>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; + bootph-all; ti,driver-strength-ohm = <50>; disable-wp; }; @@ -939,6 +958,7 @@ partition@3fc0000 { label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; + bootph-all; }; }; }; @@ -1034,6 +1054,7 @@ &usb_serdes_mux { idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ + bootph-all; }; &serdes_ln_ctrl { @@ -1043,6 +1064,7 @@ , , , , , ; + bootph-all; }; &serdes_wiz3 { @@ -1066,7 +1088,7 @@ resets = <&serdes_wiz4 1>; cdns,phy-type = ; cdns,num-lanes = <4>; - cdns,max-bit-rate = <5400>; + cdns,max-bit-rate = <2700>; #phy-cells = <0>; }; }; @@ -1081,6 +1103,7 @@ &usbss0 { pinctrl-names = "default"; pinctrl-0 = <&main_usbss0_pins_default>; + bootph-all; ti,vbus-divider; }; @@ -1089,6 +1112,7 @@ maximum-speed = "super-speed"; phys = <&serdes3_usb_link>; phy-names = "cdns3,usb3-phy"; + bootph-all; }; &serdes2 { @@ -1104,6 +1128,7 @@ &usbss1 { pinctrl-names = "default"; pinctrl-0 = <&main_usbss1_pins_default>; + bootph-all; ti,vbus-divider; }; @@ -1112,6 +1137,7 @@ maximum-speed = "super-speed"; phys = <&serdes2_usb_link>; phy-names = "cdns3,usb3-phy"; + bootph-all; }; &mcu_cpsw { diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-sk-fpdlink-fusion.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j721e-sk-fpdlink-fusion.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-sk-fpdlink-fusion.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-sk-fpdlink-fusion.dtso 2026-04-21 11:35:28.555915301 +0200 @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Fusion (FPD-Link III) board on J721E SK, + * AM68 SK or AM69 SK. + * https://svtronics.com/portfolio/evm577pfusion-v1-0-fusion/ + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + + +&cam0_i2c { + #address-cells = <1>; + #size-cells = <0>; + + deser@3d { + compatible = "ti,ds90ub960-q1"; + reg = <0x3d>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX*/ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + deser@36 { + compatible = "ti,ds90ub960-q1"; + reg = <0x36>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + deserializer_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX*/ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + deserializer_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi 2026-04-21 11:35:28.556915304 +0200 @@ -23,6 +23,14 @@ #size-cells = <2>; ranges; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x20000000>; + linux,cma-default; + }; + secure_ddr: optee@9e800000 { reg = <0x00 0x9e800000 0x00 0x01800000>; alignment = <0x1000>; @@ -151,6 +159,7 @@ J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; + bootph-all; }; pmic_irq_pins_default: pmic-irq-default-pins { @@ -173,6 +182,7 @@ J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ >; + bootph-all; }; mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { @@ -192,6 +202,7 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */ >; + bootph-all; }; }; @@ -378,6 +389,7 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + cdns,phy-mode; partitions { compatible = "fixed-partitions"; @@ -422,6 +434,7 @@ partition@3fe0000 { label = "ospi.phypattern"; reg = <0x3fe0000 0x20000>; + bootph-all; }; }; }; @@ -440,6 +453,7 @@ flash@0,0 { compatible = "cypress,hyperflash", "cfi-flash"; reg = <0x00 0x00 0x4000000>; + bootph-all; partitions { compatible = "fixed-partitions"; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts 2026-04-21 11:35:28.557915307 +0200 @@ -13,6 +13,7 @@ #include #include "k3-serdes.h" +#include "k3-timesync-router.h" / { compatible = "ti,j721s2-evm", "ti,j721s2"; @@ -93,6 +94,29 @@ <3300000 0x1>; }; + dp1_pwr_3v3: regulator-dp1-prw { + compatible = "regulator-fixed"; + regulator-name = "dp1-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; /* P1 - DP1_PWR_SW_EN */ + enable-active-high; + regulator-always-on; + }; + + dp1: connector-dp1 { + compatible = "dp-connector"; + label = "DP1"; + type = "full-size"; + dp-pwr-supply = <&dp1_pwr_3v3>; + + port { + dp1_connector_in: endpoint { + remote-endpoint = <&dp1_out>; + }; + }; + }; + transceiver1: can-phy1 { compatible = "ti,tcan1043"; #phy-cells = <0>; @@ -128,6 +152,64 @@ standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>; mux-states = <&mux1 1>; }; + + dp0_pwr_3v3: fixedregulator-dp0-prw { + compatible = "regulator-fixed"; + regulator-name = "dp0-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 0 0>; /* P0 - DP0_PWR_SW_EN */ + enable-active-high; + }; + + dp0: dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; + + codec_audio: sound { + compatible = "ti,j7200-cpb-audio"; + model = "j721e-cpb"; + + ti,cpb-mcasp = <&mcasp4>; + ti,cpb-codec = <&pcm3168a_1>; + + clocks = <&k3_clks 213 0>, <&k3_clks 213 1>, + <&k3_clks 157 299>, <&k3_clks 157 328>; + clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", + "cpb-codec-scki", "cpb-codec-scki-48000"; + }; + + i2c_mux: mux-controller-2 { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_HIGH>; + idle-state = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c3_mux_pins_default>; + }; +}; + +&main_i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <400000>; + + exp4: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; }; &main_pmx0 { @@ -138,6 +220,7 @@ J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ >; + bootph-all; }; main_i2c3_pins_default: main-i2c3-default-pins { @@ -165,6 +248,7 @@ J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ >; + bootph-all; }; vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { @@ -177,6 +261,7 @@ pinctrl-single,pins = < J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ >; + bootph-all; }; main_mcan3_pins_default: main-mcan3-default-pins { @@ -192,6 +277,35 @@ J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */ >; }; + + main_i2c4_pins_default: main-i2c4-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) I2C4_SCL */ + J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) I2C4_SDA */ + >; + }; + + dp0_pins_default: dp0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0b8, PIN_INPUT, 3) /* (AA24) MCASP1_ACLKX.DP0_HPD */ + >; + }; + + mcasp4_pins_default: mcasp4-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0c8, PIN_OUTPUT_PULLDOWN, 1) /* (AD28) MCASP4_ACLKX */ + J721S2_IOPAD(0x06c, PIN_OUTPUT_PULLDOWN, 1) /* (V26) MCASP4_AFSX */ + J721S2_IOPAD(0x068, PIN_INPUT_PULLDOWN, 1) /* (U28) MCASP4_AXR1 */ + J721S2_IOPAD(0x0c4, PIN_OUTPUT_PULLDOWN, 1) /* (AB26) MCASP4_AXR2 */ + J721S2_IOPAD(0x070, PIN_OUTPUT_PULLDOWN, 1) /* (R27) MCASP4_AXR3 */ + >; + }; + + audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x078, PIN_OUTPUT, 1) /* (Y25) MCAN2_RX.AUDIO_EXT_REFCLK1 */ + >; + }; }; &wkup_pmx2 { @@ -200,6 +314,7 @@ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; + bootph-all; }; mcu_uart0_pins_default: mcu-uart0-default-pins { @@ -209,6 +324,7 @@ J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ >; + bootph-all; }; mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -287,6 +403,18 @@ J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ >; }; + + main_i2c3_mux_pins_default: main-i2c3-mux-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 7) /* (B27) WKUP_GPIO0_54 */ + >; + }; + + wkup_gpio_pins_default: wkup_gpio_pins_default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x080, PIN_INPUT, 7) /* (E38) WKUP_GPIO0_6 */ + >; + }; }; &wkup_pmx1 { @@ -301,6 +429,7 @@ J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ >; + bootph-all; }; }; @@ -316,12 +445,14 @@ status = "reserved"; pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; + bootph-all; }; &mcu_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; + bootph-all; }; &main_uart8 { @@ -330,6 +461,7 @@ pinctrl-0 = <&main_uart8_pins_default>; /* Shared with TFA on this platform */ power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; + bootph-all; }; &main_i2c0 { @@ -358,6 +490,22 @@ "MLB_MUX_SEL", "MCAN_MUX_SEL", "MCASP2/SPI3_MUX_SEL", "PCIe_CLKREQn_MUX_SEL", "CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL", "ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2"; + + p09-hog { + /* P09 - MCASP/TRACE_MUX_S0 */ + gpio-hog; + gpios = <9 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "MCASP/TRACE_MUX_S0"; + }; + + p10-hog { + /* P10 - MCASP/TRACE_MUX_S1 */ + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MCASP/TRACE_MUX_S1"; + }; }; }; @@ -383,6 +531,7 @@ /* eMMC */ status = "okay"; non-removable; + bootph-all; ti,driver-strength-ohm = <50>; disable-wp; }; @@ -395,11 +544,17 @@ disable-wp; vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv>; + bootph-all; }; &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + + cpts@3d000 { + /* Map HW4_TS_PUSH to GENF1 */ + ti,pps = <3 1>; + }; }; &davinci_mdio { @@ -440,10 +595,15 @@ idle-states = <1>; /* USB0 to SERDES lane 1 */ }; +&edp_serdes_mux { + idle-states = <1>; /* EDP0 to SERDES lane 2/3 */ +}; + &usbss0 { status = "okay"; pinctrl-0 = <&main_usbss0_pins_default>; pinctrl-names = "default"; + bootph-all; ti,vbus-divider; ti,usb2-only; }; @@ -451,6 +611,12 @@ &usb0 { dr_mode = "otg"; maximum-speed = "high-speed"; + bootph-all; +}; + +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; }; &ospi1 { @@ -458,17 +624,59 @@ pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - flash@0 { + ospi1_nor: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; + bootph-all; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qspi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "qspi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "qspi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "qspi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "qspi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "qspi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "qspi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; @@ -525,3 +733,182 @@ pinctrl-0 = <&main_mcan5_pins_default>; phys = <&transceiver4>; }; + +&dss { + /* + * DSS on J721S2-EVM supports DP on VP0 and DSI on VP2. + * These clock assignments are chosen to enable the following outputs: + * VP0 - DisplayPort SST + * VP2 - DSI + */ + status = "okay"; + assigned-clocks = <&k3_clks 158 2>, + <&k3_clks 158 14>; + assigned-clock-parents = <&k3_clks 158 3>, + <&k3_clks 158 16>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; + + port@2 { + reg = <2>; + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&dsi0_ports { + port@0 { + reg = <0>; + dsi0_out: endpoint { + remote-endpoint = <&dp1_in>; + }; + }; + + port@1 { + reg = <1>; + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; +}; + +&dsi_edp_bridge_ports { + port@0 { + reg = <0>; + dp1_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + dp1_out: endpoint { + remote-endpoint = <&dp1_connector_in>; + }; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +&mhdp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; + cdns,no-hpd; +}; + +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; +}; + +&mux0 { + idle-state = <0>; +}; + +&mux1 { + idle-state = <0>; +}; + +&exp_som { + p03-hog { + /* P03 - CANUART_MUX_SEL1 */ + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CANUART_MUX_SEL1"; + }; +}; + +&k3_clks { + /* Confiure AUDIO_EXT_REFCLK1 pin as output */ + pinctrl-names = "default"; + pinctrl-0 = <&audio_ext_refclk1_pins_default>; +}; + +&main_i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c3_pins_default>; + clock-frequency = <400000>; + mux-states = <&i2c_mux 1>; + + exp3: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pcm3168a_1: audio-codec@44 { + compatible = "ti,pcm3168a"; + reg = <0x44>; + #sound-dai-cells = <1>; + reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; + /* C_AUDIO_REFCLK1 -> MCAN2_RX (Y25) */ + clocks = <&audio_refclk1>; + clock-names = "scki"; + VDD1-supply = <&vsys_3v3>; + VDD2-supply = <&vsys_3v3>; + VCCAD1-supply = <&vsys_5v0>; + VCCAD2-supply = <&vsys_5v0>; + VCCDA1-supply = <&vsys_5v0>; + VCCDA2-supply = <&vsys_5v0>; + }; +}; + +&mcasp4 { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp4_pins_default>; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + auxclk-fs-ratio = <256>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 2 1 1 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; +}; + +×ync_router { + /* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */ + mux-reg-masks-state = < + /* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */ + K3_TS_OFFSET(25, 0x0001ffff, 17) + >; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j721s2.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721s2.dtsi 2026-04-21 11:35:28.559915312 +0200 @@ -118,6 +118,7 @@ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Time Sync Router */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-evm-csi2-ov5640.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-evm-csi2-ov5640.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-evm-csi2-ov5640.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-evm-csi2-ov5640.dtso 2026-04-21 11:35:28.557915307 +0200 @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LI OV5640 MIPI Camera module on MIPI CSI connector. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&main_i2c5 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + powerdown-gpios = <&exp5 0 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-evm-fusion.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-evm-fusion.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-evm-fusion.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-evm-fusion.dtso 2026-04-21 11:35:28.557915307 +0200 @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Fusion (FPD-Link III) board on J721S2 and J784S4 EVM + * https://svtronics.com/portfolio/evm577pfusion-v1-0-fusion/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + + +&main_i2c5 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + deser@3d { + compatible = "ti,ds90ub960-q1"; + reg = <0x3d>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + deser@36 { + compatible = "ti,ds90ub960-q1"; + reg = <0x36>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + deserializer_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + deserializer_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; \ No newline at end of file diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso 2026-04-21 11:35:28.558915309 +0200 @@ -38,7 +38,7 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; max-link-speed = <3>; num-lanes = <1>; power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-evm-ub954.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-evm-ub954.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-evm-ub954.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-evm-ub954.dtso 2026-04-21 11:35:28.558915309 +0200 @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for DS90UB954-Q1EVM FPDLink-III deserializer board on J721S2 and J784S4 EVM + * https://www.ti.com/tool/DS90UB954-Q1EVM + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + + +&main_i2c5 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + deser@3d { + compatible = "ti,ds90ub954-q1"; + reg = <0x3d>; + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@2 { + reg = <2>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi 2026-04-21 11:35:28.558915309 +0200 @@ -4,6 +4,7 @@ * * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ +#include #include #include @@ -37,9 +38,8 @@ }; }; - scm_conf: syscon@104000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00104000 0x00 0x18000>; + scm_conf: bus@104000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00104000 0x18000>; @@ -57,6 +57,11 @@ #phy-cells = <1>; }; + pcie1_ctrl: pcie-ctrl@74 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x74 0x4>; + }; + serdes_ln_ctrl: mux-controller@80 { compatible = "reg-mux"; reg = <0x80 0x10>; @@ -70,6 +75,23 @@ reg = <0x140 0x18>; #clock-cells = <1>; }; + + edp_serdes_mux: mux-controller@310 { + compatible = "reg-mux"; + reg = <0x310 0x4>; + #mux-control-cells = <1>; + /* EDP0 to SERDES0 lane 0/1 or 2/3 mux */ + mux-reg-masks = <0x0 0x10000000>; + }; + + audio_refclk1: clock-controller@42e4 { + compatible = "ti,am62-audio-refclk"; + reg = <0x42e4 0x4>; + clocks = <&k3_clks 157 299>; + assigned-clocks = <&k3_clks 157 299>; + assigned-clock-parents = <&k3_clks 157 328>; + #clock-cells = <0>; + }; }; main_ehrpwm0: pwm@3000000 { @@ -555,6 +577,19 @@ status = "disabled"; }; + gpu: gpu@4e20000000 { + compatible = "ti,j721s2-pvr", "img,pvr-bxs64"; + reg = <0x4e 0x20000000 0x00 0x80000>; + interrupts = ; + power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>; + power-domain-names = "firmware", "dust"; + clocks = <&k3_clks 130 1>; + assigned-clocks = <&k3_clks 130 1>; + assigned-clock-rates = <800000000>; + clock-names = "core"; + }; + main_gpio0: gpio@600000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x00 0x00600000 0x00 0x100>; @@ -712,6 +747,7 @@ interrupts = ; clocks = <&k3_clks 179 2>; power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + sram = <&main_navss_sram>; }; main_sdhci0: mmc@4f80000 { @@ -780,6 +816,14 @@ dma-coherent; dma-ranges; + main_navss_sram: navss-sram@30000000{ + compatible = "mmio-sram"; + reg = <0x00 0x30000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x30000000 0x10000>; + }; + main_navss_intr: interrupt-controller@310e0000 { compatible = "ti,sci-intr"; reg = <0x00 0x310e0000 0x00 0x4000>; @@ -816,6 +860,7 @@ <0x00 0x32800000 0x00 0x100000>; interrupt-names = "rx_011"; interrupts = ; + bootph-all; }; hwspinlock: spinlock@30e00000 { @@ -1234,18 +1279,24 @@ ranges; #address-cells = <2>; #size-cells = <2>; - dmas = <&main_bcdma_csi 0 0x4940 0>; - dma-names = "rx0"; + dmas = <&main_bcdma_csi 0 0x4940 0>, <&main_bcdma_csi 0 0x4941 0>, + <&main_bcdma_csi 0 0x4942 0>, <&main_bcdma_csi 0 0x4943 0>, + <&main_bcdma_csi 0 0x4944 0>, <&main_bcdma_csi 0 0x4945 0>, + <&main_bcdma_csi 0 0x4946 0>, <&main_bcdma_csi 0 0x4947 0>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7"; power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; cdns_csi2rx0: csi-bridge@4504000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x04504000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>, - <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; + <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", - "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; phys = <&dphy0>; phy-names = "dphy"; @@ -1287,18 +1338,24 @@ ranges; #address-cells = <2>; #size-cells = <2>; - dmas = <&main_bcdma_csi 0 0x4960 0>; - dma-names = "rx0"; + dmas = <&main_bcdma_csi 0 0x4960 0>, <&main_bcdma_csi 0 0x4961 0>, + <&main_bcdma_csi 0 0x4962 0>, <&main_bcdma_csi 0 0x4963 0>, + <&main_bcdma_csi 0 0x4964 0>, <&main_bcdma_csi 0 0x4965 0>, + <&main_bcdma_csi 0 0x4966 0>, <&main_bcdma_csi 0 0x4967 0>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7"; power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; cdns_csi2rx1: csi-bridge@4514000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x04514000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>, - <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; + <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", - "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; phys = <&dphy1>; phy-names = "dphy"; @@ -1360,15 +1417,21 @@ num-lanes = <4>; #reset-cells = <1>; #clock-cells = <1>; - ranges = <0x5060000 0x0 0x5060000 0x10000>; + ranges = <0x5060000 0x0 0x5060000 0x10000>, + <0xa030a00 0x0 0xa030a00 0x40>; /* DPTX PHY */ assigned-clocks = <&k3_clks 365 3>; assigned-clock-parents = <&k3_clks 365 7>; serdes0: serdes@5060000 { + /* + * Note: we also map DPTX PHY registers as the Torrent + * needs to manage those. + */ compatible = "ti,j721e-serdes-10g"; - reg = <0x05060000 0x00010000>; - reg-names = "torrent_phy"; + reg = <0x05060000 0x00010000>, + <0xa030a00 0x40>; /* DPTX PHY */ + reg-names = "torrent_phy", "dptx_phy"; resets = <&serdes_wiz0 0>; reset-names = "torrent_reset"; clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, @@ -1385,6 +1448,15 @@ #clock-cells = <1>; status = "disabled"; /* Needs lane config */ + + torrent_phy_dp: phy@2 { + reg = <2>; + resets = <&serdes_wiz0 3>; + cdns,phy-type = ; + cdns,num-lanes = <2>; + cdns,max-bit-rate = <5400>; + #phy-cells = <0>; + }; }; }; @@ -1393,12 +1465,12 @@ reg = <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x800000>, - <0x00 0x18000000 0x00 0x1000>; + <0x41 0x00000000 0x00 0x1000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; max-link-speed = <3>; num-lanes = <4>; power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; @@ -1411,8 +1483,8 @@ device-id = <0xb013>; msi-map = <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; @@ -1789,6 +1861,78 @@ status = "disabled"; }; + mhdp: dp-bridge@a000000 { + compatible = "ti,j721e-mhdp8546"; + /* + * Note: we do not map DPTX PHY area, as that is handled by + * the PHY driver. + */ + reg = <0x0 0xa000000 0x0 0x30a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ + <0x0 0x4f40000 0x0 0x20>; /* DSS_EDP0_INTG_CFG_VP */ + reg-names = "mhdptx", "j721e-intg"; + + clocks = <&k3_clks 156 19>; + + phys = <&torrent_phy_dp>; + phy-names = "dpphy"; + + interrupt-parent = <&gic500>; + interrupts = ; + + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + + status = "disabled"; + + dp0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + dphy_tx0: phy@4480000 { + compatible = "ti,j721e-dphy"; + reg = <0x0 0x04480000 0x0 0x1000>; + clocks = <&k3_clks 363 8>, <&k3_clks 363 14>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 363 14>; + assigned-clock-parents = <&k3_clks 363 15>; + assigned-clock-rates = <19200000>; + status = "disabled"; + }; + + dsi0: dsi@4800000 { + compatible = "ti,j721e-dsi"; + reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>; + clocks = <&k3_clks 154 4>, <&k3_clks 154 1>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + interrupt-parent = <&gic500>; + interrupts = ; + phys = <&dphy_tx0>; + phy-names = "dphy"; + status = "disabled"; + + dsi0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + }; + }; + + timesync_router: mux-controller@a40000 { + compatible = "reg-mux"; + reg = <0x0 0xa40000 0x0 0x800>; + #mux-control-cells = <1>; + status = "disabled"; + }; + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ @@ -2047,4 +2191,136 @@ /* reserved for MAIN_R5F1_1 */ status = "reserved"; }; + + mcasp0: mcasp@2b00000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x0 0x02b00000 0x0 0x2000>, + <0x0 0x02b08000 0x0 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; + dma-names = "tx", "rx"; + clocks = <&k3_clks 209 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 209 0>; + assigned-clock-parents = <&k3_clks 209 1>; + power-domains = <&k3_pds 209 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp1: mcasp@2b10000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x0 0x02b10000 0x0 0x2000>, + <0x0 0x02b18000 0x0 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; + dma-names = "tx", "rx"; + clocks = <&k3_clks 210 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 210 0>; + assigned-clock-parents = <&k3_clks 210 1>; + power-domains = <&k3_pds 210 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp2: mcasp@2b20000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x0 0x02b20000 0x0 0x2000>, + <0x0 0x02b28000 0x0 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; + dma-names = "tx", "rx"; + clocks = <&k3_clks 211 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 211 0>; + assigned-clock-parents = <&k3_clks 211 1>; + power-domains = <&k3_pds 211 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp3: mcasp@2b30000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x0 0x02b30000 0x0 0x2000>, + <0x0 0x02b38000 0x0 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&main_udmap 0xc403>, <&main_udmap 0x4403>; + dma-names = "tx", "rx"; + clocks = <&k3_clks 212 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 212 0>; + assigned-clock-parents = <&k3_clks 212 1>; + power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp4: mcasp@2b40000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x0 0x02b40000 0x0 0x2000>, + <0x0 0x02b48000 0x0 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&main_udmap 0xc404>, <&main_udmap 0x4404>; + dma-names = "tx", "rx"; + clocks = <&k3_clks 213 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 213 0>; + assigned-clock-parents = <&k3_clks 213 1>; + power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + memorycontroller0: memory-controller@2980000 { + compatible = "ti,j7-ddrss"; + reg = <0x0 0x02980000 0x0 0x200>; + reg-names = "ss_cfg"; + ranges = <0x00 0x00 0x00 0x02990000 0x00 0x00004000>; + interrupts = ; + power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>, + <&k3_pds 96 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 138 2>; + #address-cells = <2>; + #size-cells = <2>; + + ddr0: ddr@0 { + compatible = "cdns,j7-ddr"; + reg = <0x00 0x0000 0x00 0x72c>, + <0x00 0x2000 0x00 0x4b0>, + <0x00 0x4000 0x00 0x163c>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + }; + }; + + memorycontroller1: memory-controller@29a0000 { + compatible = "ti,j7-ddrss"; + reg = <0x0 0x029a0000 0x0 0x200>; + reg-names = "ss_cfg"; + ranges = <0x00 0x00 0x00 0x029b0000 0x00 0x00004000>; + interrupts = ; + power-domains = <&k3_pds 139 TI_SCI_PD_SHARED>, + <&k3_pds 97 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 139 2>; + #address-cells = <2>; + #size-cells = <2>; + + ddr1: ddr@0 { + compatible = "cdns,j7-ddr"; + reg = <0x00 0x0000 0x00 0x72c>, + <0x00 0x2000 0x00 0x4b0>, + <0x00 0x4000 0x00 0x163c>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + }; + }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi 2026-04-21 11:35:28.559915312 +0200 @@ -21,16 +21,19 @@ k3_pds: power-controller { compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; + bootph-all; }; k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; + bootph-all; }; k3_reset: reset-controller { compatible = "ti,sci-reset"; #reset-cells = <2>; + bootph-all; }; }; @@ -43,6 +46,7 @@ chipid: chipid@14 { compatible = "ti,am654-chipid"; reg = <0x14 0x4>; + bootph-all; }; }; @@ -53,6 +57,8 @@ reg = <0x00 0x43600000 0x00 0x10000>, <0x00 0x44880000 0x00 0x20000>, <0x00 0x44860000 0x00 0x20000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -148,12 +154,14 @@ cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; reg = <0x200 0x8>; + bootph-all; }; phy_gmii_sel: phy@4040 { compatible = "ti,am654-phy-gmii-sel"; reg = <0x4040 0x4>; #phy-cells = <1>; + bootph-all; }; }; @@ -167,6 +175,7 @@ assigned-clocks = <&k3_clks 35 1>; assigned-clock-parents = <&k3_clks 35 2>; power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-pre-ram; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; @@ -361,6 +370,7 @@ clocks = <&k3_clks 223 1>; clock-names = "fck"; power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; + bootph-all; status = "disabled"; }; @@ -469,6 +479,7 @@ <0x0 0x2a500000 0x0 0x40000>, <0x0 0x28440000 0x0 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + bootph-all; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; ti,sci = <&sms>; @@ -488,6 +499,7 @@ "tchan", "rchan", "rflow"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; + bootph-all; ti,sci = <&sms>; ti,sci-dev-id = <273>; @@ -507,6 +519,8 @@ reg = <0x00 0x2a480000 0x00 0x80000>, <0x00 0x2a380000 0x00 0x80000>, <0x00 0x2a400000 0x00 0x80000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -526,6 +540,7 @@ clocks = <&k3_clks 29 28>; clock-names = "fck"; power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; + bootph-all; dmas = <&mcu_udmap 0xf000>, <&mcu_udmap 0xf001>, @@ -550,6 +565,7 @@ label = "port1"; ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; phys = <&phy_gmii_sel 1>; + bootph-all; }; }; @@ -633,6 +649,7 @@ cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; + cdns,phase-detect-selector = <2>; clocks = <&k3_clks 109 5>; assigned-clocks = <&k3_clks 109 5>; assigned-clock-parents = <&k3_clks 109 7>; @@ -652,6 +669,7 @@ cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; + cdns,phase-detect-selector = <2>; clocks = <&k3_clks 110 5>; power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; @@ -667,11 +685,12 @@ <0x00 0x42050000 0x0 0x350>; power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; + bootph-pre-ram; }; mcu_r5fss0: r5fss@41000000 { compatible = "ti,j721s2-r5fss"; - ti,cluster-mode = <1>; + ti,cluster-mode = <0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x41000000 0x00 0x41000000 0x20000>, diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi 2026-04-21 11:35:28.559915312 +0200 @@ -25,6 +25,14 @@ #size-cells = <2>; ranges; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x38000000>; + linux,cma-default; + }; + secure_ddr: optee@9e800000 { reg = <0x00 0x9e800000 0x00 0x01800000>; alignment = <0x1000>; @@ -152,6 +160,30 @@ #phy-cells = <0>; max-bitrate = <5000000>; }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + edp1_refclk: clock-edp1-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; }; &wkup_pmx0 { @@ -168,8 +200,8 @@ J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ - J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ >; + bootph-all; }; }; @@ -180,6 +212,13 @@ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 7) >; }; + + mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0_1_default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (B19) MCU_OSPI0_ECC_FAIL */ + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B20) MCU_OSPI0_RESET_OUT0 */ + >; + }; }; &wkup_pmx2 { @@ -188,6 +227,7 @@ J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ >; + bootph-pre-ram; }; }; @@ -432,19 +472,120 @@ &ospi0 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; - flash@0 { + ospi0_nor: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <25000000>; + bootph-all; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + cdns,phy-mode; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; + + ospi0_nand: nand@0 { + compatible = "spi-nand"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + cdns,phy-mode; + status = "disabled"; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi_nand.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi_nand.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi_nand.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi_nand.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi_nand.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@2000000 { + label = "ospi_nand.rootfs"; + reg = <0x2000000 0x5fc0000>; + }; + + partition@7fc0000 { + bootph-all; + label = "ospi_nand.phypattern"; + reg = <0x7fc0000 0x40000>; + }; + }; }; }; @@ -586,3 +727,31 @@ memory-region = <&c71_1_dma_memory_region>, <&c71_1_memory_region>; }; + +&main_i2c4 { + dsi_edp_bridge: dsi-edp-bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clock-names = "refclk"; + clocks = <&edp1_refclk>; + + enable-gpios = <&exp_som 5 0>; + + vpll-supply = <&vsys_io_1v8>; + vccio-supply = <&vsys_io_1v8>; + vcca-supply = <&vsys_io_1v2>; + vcc-supply = <&vsys_io_1v2>; + + dsi_edp_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j722s.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j722s.dtsi 2026-04-21 11:35:28.561915317 +0200 @@ -164,6 +164,7 @@ <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */ <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */ + <0x00 0x30300000 0x00 0x30300000 0x00 0x00001000>, /* MCRC64 */ <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */ @@ -222,6 +223,22 @@ }; }; + dss0_vp1_clk: clock-divider-oldi-dss0 { + compatible = "fixed-factor-clock"; + clocks = <&k3_clks 186 0>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + }; + + dss1_vp1_clk: clock-divider-oldi-dss1 { + compatible = "fixed-factor-clock"; + clocks = <&k3_clks 232 0>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + }; + #include "k3-am62p-j722s-common-thermal.dtsi" }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso 2026-04-21 11:35:28.559915312 +0200 @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * DT Overlay for RPi Camera V2.1 on J722S-EVM board. + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + cam0_reset_pins_default: cam0-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x03c, PIN_OUTPUT, 7) + >; + }; + + cam1_reset_pins_default: cam1-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x044, PIN_OUTPUT, 7) + >; + }; + + cam2_reset_pins_default: cam2-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x04c, PIN_OUTPUT, 7) + >; + }; + + cam3_reset_pins_default: cam3-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x054, PIN_OUTPUT, 7) + >; + }; +}; + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&exp1 { + p06-hog{ + /* P06 - CSI01_MUX_SEL_2 */ + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI01_MUX_SEL_2"; + }; + + p07-hog{ + /* P01 - CSI23_MUX_SEL_2 */ + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI23_MUX_SEL_2"; + }; +}; + +&pca9543_0 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-alias-pool = /bits/ 16 <0x10 0x11>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + imx219_0: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam0_reset_pins_default>; + + reset-gpios = <&main_gpio0 15 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + imx219_1: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam1_reset_pins_default>; + + reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + +&pca9543_1 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-alias-pool = /bits/ 16 <0x10 0x11>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + imx219_2: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam2_reset_pins_default>; + + reset-gpios = <&main_gpio0 19 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam2: endpoint { + remote-endpoint = <&csi2rx2_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + imx219_3: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam3_reset_pins_default>; + + reset-gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam3: endpoint { + remote-endpoint = <&csi2rx3_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx2_in_sensor: endpoint { + remote-endpoint = <&csi2_cam2>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx3 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi3_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx3_in_sensor: endpoint { + remote-endpoint = <&csi2_cam3>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; + +&ti_csi2rx2 { + status = "okay"; +}; + +&dphy2 { + status = "okay"; +}; + +&ti_csi2rx3 { + status = "okay"; +}; + +&dphy3 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso 2026-04-21 11:35:28.559915312 +0200 @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * 4 x TEVI OV5640 MIPI Camera module on RPI camera connector. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + + +&main_pmx0 { + cam0_reset_pins_default: cam0-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x03c, PIN_OUTPUT, 7) + >; + }; + + cam1_reset_pins_default: cam1-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x044, PIN_OUTPUT, 7) + >; + }; + + cam2_reset_pins_default: cam2-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x04c, PIN_OUTPUT, 7) + >; + }; + + cam3_reset_pins_default: cam3-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x054, PIN_OUTPUT, 7) + >; + }; +}; + +&exp1 { + p06-hog{ + /* P06 - CSI01_MUX_SEL_2 */ + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI01_MUX_SEL_2"; + }; + + p07-hog{ + /* P01 - CSI23_MUX_SEL_2 */ + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI23_MUX_SEL_2"; + }; +}; + +&main_gpio0 { + p15-hog { + /* P15 - CSI2_CAMERA_GPIO1 */ + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI2_CAMERA_GPIO1"; + }; + + p17-hog { + /* P17 - CSI2_CAMERA_GPIO2 */ + gpio-hog; + gpios = <17 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI2_CAMERA_GPIO2"; + }; + + p19-hog { + /* P19 - CSI2_CAMERA_GPIO3 */ + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI2_CAMERA_GPIO3"; + }; + + p21-hog { + /* P21 - CSI2_CAMERA_GPIO4 */ + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI2_CAMERA_GPIO4"; + }; +}; + +&pca9543_0 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-alias-pool = /bits/ 16 <0x3c 0x3d>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ov5640_0: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam0_reset_pins_default>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ov5640_1: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam1_reset_pins_default>; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + +&pca9543_1 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-alias-pool = /bits/ 16 <0x3c 0x3d>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ov5640_2: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam2_reset_pins_default>; + + port { + csi2_cam2: endpoint { + remote-endpoint = <&csi2rx2_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ov5640_3: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam3_reset_pins_default>; + + port { + csi2_cam3: endpoint { + remote-endpoint = <&csi2rx3_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx2_in_sensor: endpoint { + remote-endpoint = <&csi2_cam2>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx3 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi3_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx3_in_sensor: endpoint { + remote-endpoint = <&csi2_cam3>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; + + +&ti_csi2rx2 { + status = "okay"; +}; + +&dphy2 { + status = "okay"; +}; + + +&ti_csi2rx3 { + status = "okay"; +}; + +&dphy3 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-dsi-rpi-7inch-panel.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-dsi-rpi-7inch-panel.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-dsi-rpi-7inch-panel.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-dsi-rpi-7inch-panel.dtso 2026-04-21 11:35:28.560915314 +0200 @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for RPi 7inch touchscreen panel interfaced with DSI on + * J722S EVM. + * + * RPi DSI Panel: https://www.raspberrypi.com/products/raspberry-pi-touch-display/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + panel0 { + compatible = "raspberrypi,7inch-dsi", "simple-panel"; + backlight = <&display_reg>; + power-supply = <&display_reg>; + + port { + panel_in: endpoint { + remote-endpoint = <&panel_bridge_out>; + }; + }; + }; + + bridge_reg: bridge-regulator { + compatible = "regulator-fixed"; + regulator-name = "bridge-reg"; + gpio = <&display_reg 0 0>; + vin-supply = <&display_reg>; + enable-active-high; + }; +}; + +&exp2 { + p00-hog { + /* P00 - DSI_Mux_SEL_2 */ + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "DSI_Mux_SEL_2"; + }; +}; + +&dp0 { + status = "disabled"; +}; + +&dsi_edp_bridge { + status = "disabled"; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&main_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + display_reg: regulator@45 { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&dsi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&panel_bridge_in>; + }; + }; + }; + + bridge@0 { + status = "okay"; + compatible = "toshiba,tc358762"; + reg = <0>; + vddc-supply = <&bridge_reg>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + panel_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm.dts v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm.dts 2026-04-21 11:35:28.561915317 +0200 @@ -12,6 +12,7 @@ #include #include "k3-j722s.dtsi" #include "k3-serdes.h" +#include "k3-timesync-router.h" / { compatible = "ti,j722s-evm", "ti,j722s"; @@ -42,6 +43,14 @@ #size-cells = <2>; ranges; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x38000000>; + linux,cma-default; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; no-map; @@ -244,6 +253,46 @@ max-bitrate = <5000000>; standby-gpios = <&exp1 17 GPIO_ACTIVE_HIGH>; }; + + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; + + edp0_refclk: clock-edp0-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + dp0_pwr_3v3: regulator-dp0-prw { + compatible = "regulator-fixed"; + regulator-name = "dp0-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; /* P2 - DP0_PWR_SW_EN */ + enable-active-high; + regulator-always-on; + }; + + dp0: connector-dp0 { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; }; &main_pmx0 { @@ -263,6 +312,21 @@ bootph-all; }; + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */ + J722S_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A22) I2C1_SDA */ + >; + bootph-all; + }; + + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ + J722S_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ + >; + }; + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ @@ -303,6 +367,7 @@ J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ >; + bootph-all; }; ospi0_pins_default: ospi0-default-pins { @@ -337,6 +402,7 @@ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ >; + bootph-all; }; main_usb1_pins_default: main-usb1-default-pins { @@ -359,12 +425,63 @@ J722S_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ >; }; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x030, PIN_INPUT, 7) /* (K23) GPIO0_12 */ + >; + }; + + main_gpio0_ioexp_intr_pins_default: main-gpio0-ioexp-intr-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0110, PIN_INPUT, 7) /* (G27) MMC2_DAT1.GPIO0_67 */ + >; + }; + + main_dpi_pins_default: main-dpi-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AB23) VOUT0_VSYNC */ + J722S_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ + J722S_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC26) VOUT0_PCLK */ + J722S_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (AC27) VOUT0_DE */ + J722S_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (W27) VOUT0_DATA0 */ + J722S_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA1 */ + J722S_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA2 */ + J722S_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W23) VOUT0_DATA3 */ + J722S_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA4 */ + J722S_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA5 */ + J722S_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y26) VOUT0_DATA6 */ + J722S_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (Y27) VOUT0_DATA7 */ + J722S_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA8 */ + J722S_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (AA27) VOUT0_DATA9 */ + J722S_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA10 */ + J722S_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA11 */ + J722S_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA12 */ + J722S_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA22) VOUT0_DATA13 */ + J722S_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AB26) VOUT0_DATA14 */ + J722S_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AB27) VOUT0_DATA15 */ + J722S_IOPAD(0x005c, PIN_OUTPUT, 1) /* (U27) GPMC0_AD8.VOUT0_DATA16 */ + J722S_IOPAD(0x0060, PIN_OUTPUT, 1) /* (U26) GPMC0_AD9.VOUT0_DATA17 */ + J722S_IOPAD(0x0064, PIN_OUTPUT, 1) /* (V27) GPMC0_AD10.VOUT0_DATA18 */ + J722S_IOPAD(0x0068, PIN_OUTPUT, 1) /* (V25) GPMC0_AD11.VOUT0_DATA19 */ + J722S_IOPAD(0x006c, PIN_OUTPUT, 1) /* (V26) GPMC0_AD12.VOUT0_DATA20 */ + J722S_IOPAD(0x0070, PIN_OUTPUT, 1) /* (V24) GPMC0_AD13.VOUT0_DATA21 */ + J722S_IOPAD(0x0074, PIN_OUTPUT, 1) /* (V22) GPMC0_AD14.VOUT0_DATA22 */ + J722S_IOPAD(0x0078, PIN_OUTPUT, 1) /* (V23) GPMC0_AD15.VOUT0_DATA23 */ + J722S_IOPAD(0x009c, PIN_OUTPUT, 1) /* (W26) GPMC0_WAIT1.VOUT0_EXTPCLKIN */ + >; + }; }; &cpsw3g { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&rgmii1_pins_default>; + + cpts@3d000 { + /* MAP HW3_TS_PUSH to GENF1 */ + ti,pps = <2 1>; + }; }; &cpsw3g_mdio { @@ -374,6 +491,7 @@ cpsw3g_phy0: ethernet-phy@0 { reg = <0>; + bootph-all; ti,rx-internal-delay = ; ti,fifo-depth = ; ti,min-output-impedance; @@ -406,6 +524,13 @@ &mcu_pmx0 { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x048, PIN_INPUT, 0) /* (E11) MCU_I2C0_SDA */ + J722S_MCU_IOPAD(0x044, PIN_INPUT, 0) /* (B13) MCU_I2C0_SCL */ + >; + }; + mcu_mcan0_pins_default: mcu-mcan0-default-pins { pinctrl-single,pins = < J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */ @@ -459,6 +584,87 @@ clock-frequency = <400000>; status = "okay"; bootph-all; + + tps65224: pmic@48 { + compatible = "ti,tps65224-q1"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&main_gpio0>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + ti,primary-pmic; + + gpio-controller; + #gpio-cells = <2>; + + buck12-supply = <&vsys_io_3v3>; + buck3-supply = <&vsys_io_3v3>; + buck4-supply = <&vsys_io_3v3>; + + ldo1-supply = <&vsys_io_3v3>; + ldo2-supply = <&vsys_io_3v3>; + ldo3-supply = <&vsys_io_3v3>; + + regulators { + + buck1: buck1 { + regulator-name = "vcc1v8_io_buck1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + buck2: buck2 { + regulator-name = "vcc1v1_ddr_buck2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + buck3: buck3 { + regulator-name = "vcc0v85_ram_buck3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: buck4 { + regulator-name = "vcc0v75_ioret_buck4"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: ldo1 { + regulator-name = "vdda1v8_pll_ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: ldo2 { + regulator-name = "dvdd3v3_ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: ldo3 { + regulator-name = "vdd1v85_phy_ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &k3_clks { @@ -491,6 +697,7 @@ "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; + bootph-all; p05-hog { /* P05 - USB2.0_MUX_SEL */ @@ -536,6 +743,150 @@ }; }; +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <100000>; + + exp2: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "DSI_Mux_SEL_2", "GPIO_eDP_ENABLE", + "DP0_PWR_SW_EN", "GPIO_OLDI_RSTn", + "GPIO_HDMI_RSTn", "HDMI_LS_OE", + "", "", + "DSI_GPIO0", "DSI_GPIO1", + "DSI_EDID", "IO_eDP_IRQ", + "OLDI_INT#", "HDMI_INTn", + "", ""; + + interrupt-parent = <&main_gpio0>; + interrupts = <67 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio0_ioexp_intr_pins_default>; + bootph-all; + + p04-hog { + /* P04 - GPIO_HDMI_RSTn */ + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "GPIO_HDMI_RSTn"; + }; + + p03-hog { + /* P03 - GPIO_OLDI_RSTn */ + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-low; + line-name = "GPIO_OLDI_RSTn"; + }; + + p05-hog { + /* P05 - HDMI_LS_OE */ + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "HDMI_LS_OE"; + }; + }; + + sii9022: bridge-hdmi@3b { + compatible = "sil,sii9022"; + reg = <0x3b>; + interrupt-parent = <&exp2>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = < 0 >; + + hdmi_tx_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * HDMI can be serviced with 3 potential VPs - + * (DSS0 VP1 / DSS1 VP0 / DSS1 VP1). + * For now, we will service it with DSS1 VP0. + */ + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dss1_dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + dsi_edp_bridge: dsi-edp-bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clock-names = "refclk"; + clocks = <&edp0_refclk>; + + enable-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; + + vpll-supply = <&vsys_io_1v8>; + vccio-supply = <&vsys_io_1v8>; + vcca-supply = <&vsys_io_1v2>; + vcc-supply = <&vsys_io_1v2>; + + dsi_edp_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; + }; + }; +}; + +&main_i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; + + pca9543_0: i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + }; + + pca9543_1: i2c-mux@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + }; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; @@ -552,6 +903,7 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + cdns,phy-mode; bootph-all; partitions { @@ -590,12 +942,71 @@ }; partition@3fc0000 { + bootph-all; label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; }; }; }; + ospi0_nand: nand@0 { + compatible = "spi-nand"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + cdns,phy-mode; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi_nand.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi_nand.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi_nand.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi_nand.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi_nand.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@2000000 { + label = "ospi_nand.rootfs"; + reg = <0x2000000 0x5fc0000>; + }; + + partition@7fc0000 { + bootph-all; + label = "ospi_nand.phypattern"; + reg = <0x7fc0000 0x40000>; + }; + }; + }; }; &sdhci0 { @@ -767,6 +1178,10 @@ usb-role-switch; }; +&usb0_phy_ctrl { + bootph-all; +}; + &usbss1 { pinctrl-names = "default"; pinctrl-0 = <&main_usb1_pins_default>; @@ -820,3 +1235,104 @@ &mcu_gpio0 { status = "okay"; }; + +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dss1_dpi1_out>; + }; + }; + }; +}; + +&dss1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_dpi_pins_default>; + + clocks = <&k3_clks 232 8>, + <&k3_clks 232 0>, + <&k3_clks 232 4>; + + assigned-clocks = <&k3_clks 241 0>, /* DSS1-VP0 */ + <&k3_clks 240 0>, /* DSS1-VP1 */ + <&k3_clks 245 0>; /* DPI Output */ + + assigned-clock-parents = <&k3_clks 241 2>, /* PLL 17 HDMI */ + <&k3_clks 240 1>, /* PLL 18 DSI */ + <&k3_clks 245 2>; /* DSS1-DPI0 */ +}; + +&dss1_ports { + /* DSS1-VP0: DPI/HDMI Output */ + port@0 { + reg = <0>; + + dss1_dpi0_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; + + /* DSS1-VP1: DSI Output */ + port@1 { + reg = <1>; + + dss1_dpi1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&mcu_rti0 { + assigned-clock-parents = <&k3_clks 131 4>; +}; + +&main_rti0 { + assigned-clock-parents = <&k3_clks 125 4>; +}; + +&main_rti1 { + assigned-clock-parents = <&k3_clks 126 4>; +}; + +&main_rti2 { + assigned-clock-parents = <&k3_clks 127 4>; +}; + +&main_rti3 { + assigned-clock-parents = <&k3_clks 128 4>; +}; + +×ync_router { + mux-reg-masks-state = < + K3_TS_OFFSET(12, 0x0001ffff, 17) + >; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-ethfw.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-ethfw.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-ethfw.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-ethfw.dtso 2026-04-21 11:35:28.560915314 +0200 @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for CPSW3G functionality with Ethernet Switch Firmware (EthFw) + * and CPSW Proxy Client driver. + * + * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +/* Mark CPSW3G reserved for EthFw. */ +&cpsw3g { + status = "reserved"; +}; + +/* Reserve shared memory for inter-core network communication. */ +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + + main_r5fss0_core0_shared_memory_queue_region:r5f-virtual-eth-queues@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x200000>; + no-map; + }; + + main_r5fss0_core0_shared_memory_bufpool_region:r5f-virtual-eth-buffers@a7200000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7200000 0x00 0x1e00000>; + no-map; + }; +}; + +&main_r5fss0_core0 { + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>, + <&main_r5fss0_core0_shared_memory_queue_region>, + <&main_r5fss0_core0_shared_memory_bufpool_region>; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-fusion.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-fusion.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-fusion.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-fusion.dtso 2026-04-21 11:35:28.560915314 +0200 @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Fusion (FPD-Link III) board on J721E EVM + * https://svtronics.com/portfolio/evm577pfusion-v1-0-fusion/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + + +&pca9543_0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + deser@3d { + compatible = "ti,ds90ub960-q1"; + reg = <0x3d>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + deser@36 { + compatible = "ti,ds90ub960-q1"; + reg = <0x36>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + deserializer_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + deserializer_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-iv-fusion.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-iv-fusion.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-iv-fusion.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-iv-fusion.dtso 2026-04-21 11:35:28.560915314 +0200 @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * DT Overlay for FPDLink IV UB9702 Deserializer on J722S + * https://www.ti.com/tool/J7EXPA01EVM + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&main_pmx0 { + csi_expansion_interface_reset: csi-expansion-interface-reset-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x114, PIN_OUTPUT, 7) /* (G26) GPIO0_68 */ + >; + }; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&csi_expansion_interface_reset>; + + line68-hog{ + gpio-hog; + gpios = <68 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI2_EXP_RSTZ"; + }; +}; + +&pca9543_0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + deser@3d { + compatible = "ti,ds90ub9702-q1"; + reg = <0x3d>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0{ + reg= <0>; + status = "disabled"; + }; + + port@1{ + reg= <1>; + status = "disabled"; + }; + + port@2{ + reg= <2>; + status = "disabled"; + }; + + port@3{ + reg= <3>; + status = "disabled"; + }; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub970_0_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + + port@5{ + reg= <5>; + status = "disabled"; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + deser@30 { + compatible = "ti,ds90ub9702-q1"; + reg = <0x30>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + deserializer_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0{ + reg= <0>; + status = "disabled"; + }; + + port@1{ + reg= <1>; + status = "disabled"; + }; + + port@2{ + reg= <2>; + status = "disabled"; + }; + + port@3{ + reg= <3>; + status = "disabled"; + }; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub970_1_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + + port@5{ + reg= <5>; + status = "disabled"; + }; + }; + + deserializer_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + deser@32 { + compatible = "ti,ds90ub9702-q1"; + reg = <0x32>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x6a 0x6b 0x6c 0x6d 0x6e 0x6f>; + + deserializer_2_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0{ + reg= <0>; + status = "disabled"; + }; + + port@1{ + reg= <1>; + status = "disabled"; + }; + + port@2{ + reg= <2>; + status = "disabled"; + }; + + port@3{ + reg= <3>; + status = "disabled"; + }; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub970_2_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy2>; + }; + }; + + port@5{ + reg= <5>; + status = "disabled"; + }; + }; + + deserializer_2_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub970_0_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub970_1_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy2: endpoint { + remote-endpoint = <&ds90ub970_2_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; + +&ti_csi2rx2 { + status = "okay"; +}; + +&dphy2 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-microtips-mf101hie-panel.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-microtips-mf101hie-panel.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-microtips-mf101hie-panel.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-microtips-mf101hie-panel.dtso 2026-04-21 11:35:28.560915314 +0200 @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Microtips integrated OLDI panel (MF-101HIEBCAF0) and touch DT overlay for J722S-EVM + * + * Panel datasheet: https://simplespec.microtipsusa.com/uploads/spec/datasheetFile/2588/13-101HIEBCAF0-S_V1.1_20221104.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + display { + compatible = "microtips,mf-101hiebcaf0", "panel-simple"; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * Swapping them will cause an error in the dss oldi driver. + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + + lcd_in0: endpoint { + remote-endpoint = <&oldi0_dss0_out>; + }; + }; + port@1 { + reg = <1>; + dual-lvds-even-pixels; + + lcd_in1: endpoint { + remote-endpoint = <&oldi1_dss0_out>; + }; + }; + }; + }; +}; + +&dss0 { + status = "okay"; +}; + +&oldi0_dss0 { + status = "okay"; + ti,companion-oldi = <&oldi1_dss0>; +}; + +&oldi1_dss0 { + status = "okay"; + ti,secondary-oldi; + ti,companion-oldi = <&oldi0_dss0>; +}; + +&oldi0_dss0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + oldi0_dss0_in: endpoint { + remote-endpoint = <&dss0_dpi0_out0>; + }; + }; + + port@1 { + reg = <1>; + + oldi0_dss0_out: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; +}; + +&oldi1_dss0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + oldi1_dss0_in: endpoint { + remote-endpoint = <&dss0_dpi0_out1>; + }; + }; + + port@1 { + reg = <1>; + + oldi1_dss0_out: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&dss0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: Output to OLDI */ + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dss0_dpi0_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&oldi0_dss0_in>; + }; + + dss0_dpi0_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&oldi1_dss0_in>; + }; + }; +}; + +&main_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&exp2>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&exp2 3 GPIO_ACTIVE_LOW>; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-pwm.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-pwm.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-pwm.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-pwm.dtso 2026-04-21 11:35:28.560915314 +0200 @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling PWM output on User Expansion header on J722S-EVM + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + + main_epwm0_pins_default: main-epwm0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (B20) EHRPWM0_A */ + >; + }; + + main_epwm1_pins_default: main-epwm1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01bc, PIN_OUTPUT, 2) /* (D20) EHRPWM1_A */ + J722S_IOPAD(0x01c0, PIN_OUTPUT, 2) /* (E19) EHRPWM1_B */ + >; + }; + + main_ecap0_pins_default: main-ecap0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01b8, PIN_OUTPUT, 3) /* (C20) ECAP0_IN_APWM_OUT */ + >; + }; +}; + +&epwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm0_pins_default>; + status = "okay"; +}; + +&epwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm1_pins_default>; + status = "okay"; +}; + +&ecap0 { + /* ECAP in APWM mode */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap0_pins_default>; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso 2026-04-21 11:35:28.560915314 +0200 @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Arducam V3Link UC-A09 board + * https://www.arducam.com/fpd-link-3-cameras/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&exp1 { + p06-hog { + /* P06 - CSI01_MUX_SEL_2 */ + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI01_MUX_SEL_2"; + }; + + p07-hog { + /* P01 - CSI23_MUX_SEL_2 */ + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI23_MUX_SEL_2"; + }; +}; + +&pca9543_0 { + #address-cells = <1>; + #size-cells = <0>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + deserializer_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + deserializer_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi 2026-04-21 11:35:28.561915317 +0200 @@ -102,10 +102,10 @@ reg = <0x00 0x0f102000 0x00 0x1000>, <0x00 0x0f100000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x68000000 0x00 0x00001000>; + <0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, - <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; interrupt-names = "link_state"; interrupts = ; @@ -139,7 +139,7 @@ ranges; status = "disabled"; - usb1: usb@31200000{ + usb1: usb@31200000 { compatible = "cdns,usb3"; reg = <0x00 0x31200000 0x00 0x10000>, <0x00 0x31210000 0x00 0x10000>, @@ -158,6 +158,201 @@ }; }; + ti_csi2rx1: ticsi2rx@30122000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30122000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x5100 0>, <&main_bcdma_csi 0 0x5101 0>, + <&main_bcdma_csi 0 0x5102 0>, <&main_bcdma_csi 0 0x5103 0>; + dma-names = "rx0", "rx1", "rx2", "rx3"; + power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@30121000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30121000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; + clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>, + <&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@30142000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30142000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; + dmas = <&main_bcdma_csi 0 0x5200 0>, <&main_bcdma_csi 0 0x5201 0>, + <&main_bcdma_csi 0 0x5202 0>, <&main_bcdma_csi 0 0x5203 0>; + dma-names = "rx0", "rx1", "rx2", "rx3"; + status = "disabled"; + + cdns_csi2rx2: csi-bridge@30141000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30141000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; + clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>, + <&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy2>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi2_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi2_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi2_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi2_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx3: ticsi2rx@30162000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30162000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x5300 0>, <&main_bcdma_csi 0 0x5301 0>, + <&main_bcdma_csi 0 0x5302 0>, <&main_bcdma_csi 0 0x5303 0>; + dma-names = "rx0", "rx1", "rx2", "rx3"; + power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx3: csi-bridge@30161000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30161000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; + clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>, + <&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy3>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi3_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi3_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi3_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi3_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi3_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy1: phy@30130000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30130000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy2: phy@30150000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30150000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy3: phy@30170000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30170000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + main_r5fss0: r5fss@78400000 { compatible = "ti,am62-r5fss"; #address-cells = <1>; @@ -184,7 +379,7 @@ }; c7x_0: dsp@7e000000 { - compatible = "ti,am62a-c7xv-dsp"; + compatible = "ti,j722s-c7xv-dsp"; reg = <0x00 0x7e000000 0x00 0x00200000>; reg-names = "l2sram"; resets = <&k3_reset 208 1>; @@ -196,7 +391,7 @@ }; c7x_1: dsp@7e200000 { - compatible = "ti,am62a-c7xv-dsp"; + compatible = "ti,j722s-c7xv-dsp"; reg = <0x00 0x7e200000 0x00 0x00200000>; reg-names = "l2sram"; resets = <&k3_reset 268 1>; @@ -206,6 +401,27 @@ ti,sci-proc-ids = <0x31 0xff>; status = "disabled"; }; + + e5010: e5010@fd20000 { + compatible = "img,e5010-jpeg-enc"; + reg = <0x00 0xfd20000 0x00 0x100>, + <0x00 0xfd20200 0x00 0x200>; + reg-names = "core", "mmu"; + clocks = <&k3_clks 201 0>; + clock-names = "core_clk"; + power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; + interrupts = ; + }; +}; + +&main_bcdma_csi { + compatible = "ti,j722s-dmss-bcdma-csi"; + reg = <0x00 0x4e230000 0x00 0x100>, + <0x00 0x4e180000 0x00 0x20000>, + <0x00 0x4e300000 0x00 0x10000>, + <0x00 0x4e100000 0x00 0x80000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + ti,sci-rm-range-tchan = <0x22>; }; /* MCU domain overrides */ @@ -255,21 +471,6 @@ ti,interrupt-ranges = <7 71 21>; }; -&main_pmx0 { - pinctrl-single,gpio-range = - <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 72 17 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 101 25 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>; - - main_pmx0_range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; -}; - &main_gpio0 { gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>, <&main_pmx0 70 72 17>; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j742s2.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j742s2.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j742s2.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j742s2.dtsi 2026-04-21 11:35:28.562915320 +0200 @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J742S2 SoC Family + * + * TRM: https://www.ti.com/lit/pdf/spruje3 + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + */ +#include "k3-j784s4-j742s2-common.dtsi" + +/ { + model = "Texas Instruments K3 J742S2 SoC"; + compatible = "ti,j742s2"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a72"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a72"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a72"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a72"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + }; +}; + +#include "k3-j742s2-main.dtsi" +#include "k3-j742s2-mcu-wakeup.dtsi" diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j742s2-evm.dts v_kernel/arch/arm64/boot/dts/ti/k3-j742s2-evm.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j742s2-evm.dts 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j742s2-evm.dts 2026-04-21 11:35:28.561915317 +0200 @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * EVM Board Schematics: https://www.ti.com/lit/zip/SPAC001 + */ + +/dts-v1/; + +#include +#include +#include "k3-j742s2.dtsi" +#include "k3-j784s4-j742s2-evm-common.dtsi" + +/ { + model = "Texas Instruments J742S2 EVM"; + compatible = "ti,j742s2-evm", "ti,j742s2"; + + memory@80000000 { + /* 16G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000003 0x80000000>; + device_type = "memory"; + bootph-all; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j742s2-evm-ethfw.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j742s2-evm-ethfw.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j742s2-evm-ethfw.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j742s2-evm-ethfw.dtso 2026-04-21 11:35:28.561915317 +0200 @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for CPSW5G functionality with Ethernet Switch Firmware (EthFw) + * and CPSW Proxy Client driver. + * + * Since the ENET Expansion connector on J742S2-EVM is connected to SERDES4, + * CPSW5G which uses SERDES1 is non-functional on the EVM. This overlay is + * provided as a reference for enabling EthFw with CPSW5G on custom boards + * built with the J742S2 SoC. + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-serdes.h" + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , + , ; +}; + +/* SERDES1 is used by EthFw */ +&serdes_wiz1 { + status = "reserved"; +}; + +/* Since SERDES1 is used by EthFw, PCIE0 is non-functional */ +&pcie0_rc { + status = "disabled"; +}; + +/* uart2 is assigned to EthFw running on remote CPU core */ +&main_uart2 { + status = "reserved"; +}; + +/* Reserve shared memory for inter-core network communication */ +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + + main_r5fss0_core0_shared_memory_queue_region:r5f-virtual-eth-queues@af000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaf000000 0x00 0x200000>; + no-map; + }; + + main_r5fss0_core0_shared_memory_bufpool_region:r5f-virtual-eth-buffers@af200000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaf200000 0x00 0x1e00000>; + no-map; + }; +}; + +&main_r5fss0_core0 { + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>, + <&main_r5fss0_core0_shared_memory_queue_region>, + <&main_r5fss0_core0_shared_memory_bufpool_region>; +}; + +/* EthFw uses timers so mark them reserved */ +&main_timer12 { + status = "reserved"; +}; + +&main_timer13 { + status = "reserved"; +}; + +/* + * Disable the following to avoid overloading exp2. + * Otherwise it will result in PHY read/write errors. + */ +&main_mcan4 { + status = "disabled"; +}; + +&transceiver3 { + status = "disabled"; +}; + +&mux1 { + status = "disabled"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi 2026-04-21 11:35:28.561915317 +0200 @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J742S2 SoC Family + * + * TRM: https://www.ti.com/lit/pdf/spruje3 + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +&c71_0 { + firmware-name = "j742s2-c71_0-fw"; +}; + +&c71_1 { + firmware-name = "j742s2-c71_1-fw"; +}; + +&c71_2 { + firmware-name = "j742s2-c71_2-fw"; +}; + +&main_r5fss0_core0 { + firmware-name = "j742s2-main-r5f0_0-fw"; +}; + +&main_r5fss0_core1 { + firmware-name = "j742s2-main-r5f0_1-fw"; +}; + +&main_r5fss1_core0 { + firmware-name = "j742s2-main-r5f1_0-fw"; +}; + +&main_r5fss1_core1 { + firmware-name = "j742s2-main-r5f1_1-fw"; +}; + +&main_r5fss2_core0 { + firmware-name = "j742s2-main-r5f2_0-fw"; +}; + +&main_r5fss2_core1 { + firmware-name = "j742s2-main-r5f2_1-fw"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi 2026-04-21 11:35:28.562915320 +0200 @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J742S2 SoC Family + * + * TRM: https://www.ti.com/lit/pdf/spruje3 + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +&mcu_r5fss0_core0 { + firmware-name = "j742s2-mcu-r5f0_0-fw"; +}; + +&mcu_r5fss0_core1 { + firmware-name = "j742s2-mcu-r5f0_1-fw"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-evm-csi2-ov5640.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-evm-csi2-ov5640.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-evm-csi2-ov5640.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-evm-csi2-ov5640.dtso 2026-04-21 11:35:28.562915320 +0200 @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LI OV5640 MIPI Camera module on MIPI CSI (CSI2-EXP-AUX) connector. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&main_i2c5 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + powerdown-gpios = <&exp5 0 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx2_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx2_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx2 { + status = "okay"; +}; + +&dphy2 { + status = "okay"; +}; \ No newline at end of file diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts 2026-04-21 11:35:28.563915322 +0200 @@ -10,176 +10,23 @@ #include #include #include "k3-j784s4.dtsi" +#include "k3-j784s4-j742s2-evm-common.dtsi" / { compatible = "ti,j784s4-evm", "ti,j784s4"; model = "Texas Instruments J784S4 EVM"; - chosen { - stdout-path = "serial2:115200n8"; - }; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart8; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - i2c0 = &wkup_i2c0; - i2c3 = &main_i2c0; - ethernet0 = &mcu_cpsw_port1; - ethernet1 = &main_cpsw1_port1; - }; - memory@80000000 { - device_type = "memory"; - bootph-all; /* 32G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>, <0x00000008 0x80000000 0x00000007 0x80000000>; + device_type = "memory"; + bootph-all; }; reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core0_memory_region: r5f-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core1_memory_region: r5f-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a9000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa9000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a9100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa9100000 0x00 0xf00000>; - no-map; - }; - - c71_2_dma_memory_region: c71-dma-memory@aa000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xaa000000 0x00 0x100000>; - no-map; - }; - - c71_2_memory_region: c71-memory@aa100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xaa100000 0x00 0xf00000>; - no-map; - }; c71_3_dma_memory_region: c71-dma-memory@ab000000 { compatible = "shared-dma-pool"; @@ -193,1339 +40,18 @@ no-map; }; }; - - evm_12v0: regulator-evm12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: regulator-vsys3v3 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: regulator-vsys5v0 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: regulator-sd { - /* Output of TPS22918 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: regulator-TLV71033 { - /* Output of TLV71033 */ - compatible = "regulator-gpio"; - regulator-name = "tlv71033"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_pins_default>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_5v0>; - gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - dp0_pwr_3v3: regulator-dp0-prw { - compatible = "regulator-fixed"; - regulator-name = "dp0-pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - dp0: connector-dp0 { - compatible = "dp-connector"; - label = "DP0"; - type = "full-size"; - dp-pwr-supply = <&dp0_pwr_3v3>; - - port { - dp0_connector_in: endpoint { - remote-endpoint = <&dp0_out>; - }; - }; - }; - - transceiver0: can-phy0 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; - standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>; - }; - - transceiver1: can-phy1 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; - standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; - }; - - transceiver2: can-phy2 { - /* standby pin has been grounded by default */ - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; - - transceiver3: can-phy3 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - standby-gpios = <&exp2 7 GPIO_ACTIVE_HIGH>; - mux-states = <&mux1 1>; - }; - - mux1: mux-controller { - compatible = "gpio-mux"; - #mux-state-cells = <1>; - mux-gpios = <&exp2 14 GPIO_ACTIVE_HIGH>; - idle-state = <1>; - }; - - codec_audio: sound { - compatible = "ti,j7200-cpb-audio"; - model = "j784s4-cpb"; - - ti,cpb-mcasp = <&mcasp0>; - ti,cpb-codec = <&pcm3168a_1>; - - clocks = <&k3_clks 265 0>, <&k3_clks 265 1>, - <&k3_clks 157 34>, <&k3_clks 157 63>; - clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", - "cpb-codec-scki", "cpb-codec-scki-48000"; - }; -}; - -&wkup_gpio0 { - status = "okay"; -}; - -&main_pmx0 { - bootph-all; - main_cpsw2g_default_pins: main-cpsw2g-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ - J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ - J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ - J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ - J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ - J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */ - J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ - J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ - J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ - J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ - J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ - J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */ - >; - }; - - main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ - J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ - >; - }; - - main_uart8_pins_default: main-uart8-default-pins { - bootph-all; - pinctrl-single,pins = < - J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ - J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ - J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ - J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ - J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ - >; - }; - - main_i2c5_pins_default: main-i2c5-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ - J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - bootph-all; - pinctrl-single,pins = < - J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ - J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ - J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ - J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ - J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ - J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ - J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ - J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ - >; - }; - - dp0_pins_default: dp0-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ - >; - }; - - main_i2c4_pins_default: main-i2c4-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ - J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ - >; - }; - - main_mcan4_pins_default: main-mcan4-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x088, PIN_INPUT, 0) /* (AF36) MCAN4_RX */ - J784S4_IOPAD(0x084, PIN_OUTPUT, 0) /* (AG38) MCAN4_TX */ - >; - }; - - main_mcan16_pins_default: main-mcan16-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */ - J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - bootph-all; - pinctrl-single,pins = < - J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ - >; - }; - - main_i2c3_pins_default: main-i2c3-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x064, PIN_INPUT, 13) /* (AF38) MCAN0_TX.I2C3_SCL */ - J784S4_IOPAD(0x060, PIN_INPUT, 13) /* (AE36) MCASP2_AXR1.I2C3_SDA */ - >; - }; - - main_mcasp0_pins_default: main-mcasp0-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x038, PIN_OUTPUT_PULLDOWN, 1) /* (AK35) MCASP0_ACLKX */ - J784S4_IOPAD(0x03c, PIN_OUTPUT_PULLDOWN, 1) /* (AK38) MCASP0_AFSX */ - J784S4_IOPAD(0x07c, PIN_OUTPUT_PULLDOWN, 1) /* (AJ38) MCASP0_AXR3 */ - J784S4_IOPAD(0x080, PIN_INPUT_PULLDOWN, 1) /* (AK34) MCASP0_AXR4 */ - >; - }; - - audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */ - >; - }; -}; - -&wkup_pmx2 { - bootph-all; - wkup_uart0_pins_default: wkup-uart0-default-pins { - bootph-all; - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ - J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ - >; - }; - - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - bootph-all; - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ - J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - bootph-all; - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ - J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ - J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ - J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ - >; - }; - - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ - J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ - J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ - J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ - J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ - J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ - J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ - J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ - J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ - J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ - J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ - >; - }; - - mcu_adc0_pins_default: mcu-adc0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ - J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ - J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ - J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ - J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ - J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ - J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ - J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ - >; - }; - - mcu_adc1_pins_default: mcu-adc1-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ - J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ - J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ - J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ - J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ - J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ - J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ - J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ - >; - }; - - mcu_mcan0_pins_default: mcu-mcan0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ - J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ - >; - }; - - mcu_mcan1_pins_default: mcu-mcan1-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ - J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ - >; - }; - - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_69 */ - >; - }; - - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ - >; - }; -}; - -&wkup_pmx1 { - status = "okay"; - - pmic_irq_pins_default: pmic-irq-default-pins { - pinctrl-single,pins = < - /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) - >; - }; -}; - -&wkup_pmx0 { - bootph-all; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - bootph-all; - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ - J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ - J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ - J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ - J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ - J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ - J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ - J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ - J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ - >; - }; -}; - -&wkup_pmx1 { - bootph-all; - mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { - bootph-all; - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ - J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ - >; - }; - - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { - bootph-all; - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ - J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ - J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ - J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ - J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ - J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ - J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ - >; - }; -}; - -&wkup_uart0 { - /* Firmware usage */ - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&wkup_i2c0 { - bootph-all; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@50 { - /* CAV24C256WE-GT3 */ - compatible = "atmel,24c256"; - reg = <0x50>; - }; - - tps659413: pmic@48 { - compatible = "ti,tps6594-q1"; - reg = <0x48>; - system-power-controller; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins_default>; - interrupt-parent = <&wkup_gpio0>; - interrupts = <39 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - #gpio-cells = <2>; - ti,primary-pmic; - buck12-supply = <&vsys_3v3>; - buck3-supply = <&vsys_3v3>; - buck4-supply = <&vsys_3v3>; - buck5-supply = <&vsys_3v3>; - ldo1-supply = <&vsys_3v3>; - ldo2-supply = <&vsys_3v3>; - ldo3-supply = <&vsys_3v3>; - ldo4-supply = <&vsys_3v3>; - - regulators { - bucka12: buck12 { - regulator-name = "vdd_ddr_1v1"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - bucka3: buck3 { - regulator-name = "vdd_ram_0v85"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-boot-on; - regulator-always-on; - }; - - bucka4: buck4 { - regulator-name = "vdd_io_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - bucka5: buck5 { - regulator-name = "vdd_mcu_0v85"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-boot-on; - regulator-always-on; - }; - - ldoa1: ldo1 { - regulator-name = "vdd_mcuio_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldoa2: ldo2 { - regulator-name = "vdd_mcuio_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldoa3: ldo3 { - regulator-name = "vds_dll_0v8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldoa4: ldo4 { - regulator-name = "vda_mcu_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - tps62873a: regulator@40 { - compatible = "ti,tps62873"; - reg = <0x40>; - bootph-pre-ram; - regulator-name = "VDD_CPU_AVS"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1330000>; - regulator-boot-on; - regulator-always-on; - }; - - tps62873b: regulator@43 { - compatible = "ti,tps62873"; - reg = <0x43>; - regulator-name = "VDD_CORE_0V8"; - regulator-min-microvolt = <760000>; - regulator-max-microvolt = <840000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&mcu_uart0 { - bootph-all; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; -}; - -&main_uart8 { - bootph-all; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart8_pins_default>; -}; - -&ufs_wrapper { - status = "okay"; -}; - -&fss { - bootph-all; - status = "okay"; -}; - -&ospi0 { - bootph-all; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; - - flash@0 { - bootph-all; - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ospi.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "ospi.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "ospi.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "ospi.env"; - reg = <0x680000 0x40000>; - }; - - partition@6c0000 { - label = "ospi.env.backup"; - reg = <0x6c0000 0x40000>; - }; - - partition@800000 { - label = "ospi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - bootph-all; - label = "ospi.phypattern"; - reg = <0x3fc0000 0x40000>; - }; - }; - }; -}; - -&ospi1 { - bootph-all; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - - flash@0 { - bootph-all; - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <40000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "qspi.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "qspi.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "qspi.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "qspi.env"; - reg = <0x680000 0x40000>; - }; - - partition@6c0000 { - label = "qspi.env.backup"; - reg = <0x6c0000 0x40000>; - }; - - partition@800000 { - label = "qspi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - bootph-all; - label = "qspi.phypattern"; - reg = <0x3fc0000 0x40000>; - }; - }; - - }; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - - clock-frequency = <400000>; - - exp1: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ", - "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", - "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", - "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", - "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; - - p12-hog { - /* P12 - AUDIO_MUX_SEL */ - gpio-hog; - gpios = <12 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "AUDIO_MUX_SEL"; - }; - }; - - exp2: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN", - "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", - "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", - "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", - "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", - "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", - "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", - "USER_INPUT1", "USER_LED1", "USER_LED2"; - - p13-hog { - /* P13 - CANUART_MUX_SEL0 */ - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "CANUART_MUX_SEL0"; - }; - - p15-hog { - /* P15 - CANUART_MUX1_SEL1 */ - gpio-hog; - gpios = <15 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "CANUART_MUX1_SEL1"; - }; - }; -}; - -&main_i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c5_pins_default>; - clock-frequency = <400000>; - status = "okay"; - - exp5: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", - "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", - "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", - "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; - }; -}; - -&main_sdhci0 { - bootph-all; - /* eMMC */ - status = "okay"; - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci1 { - bootph-all; - /* SD card */ - status = "okay"; - pinctrl-0 = <&main_mmc1_pins_default>; - pinctrl-names = "default"; - disable-wp; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv>; -}; - -&main_gpio0 { - status = "okay"; -}; - -&mcu_cpsw { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>; -}; - -&davinci_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mdio_pins_default>; - - mcu_phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - }; -}; - -&mcu_cpsw_port1 { - status = "okay"; - phy-mode = "rgmii-rxid"; - phy-handle = <&mcu_phy0>; -}; - -&main_cpsw1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_cpsw2g_default_pins>; - status = "okay"; -}; - -&main_cpsw1_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&main_cpsw2g_mdio_default_pins>; - status = "okay"; - - main_cpsw1_phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - }; -}; - -&main_cpsw1_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&main_cpsw1_phy0>; - status = "okay"; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; }; &mailbox0_cluster5 { - status = "okay"; - interrupts = <416>; - - mbox_c71_2: mbox-c71-2 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - mbox_c71_3: mbox-c71-3 { ti,mbox-rx = <2 0 0>; ti,mbox-tx = <3 0 0>; }; }; -&mcu_r5fss0_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; -}; - -&main_r5fss1 { - ti,cluster-mode = <0>; -}; - -&main_r5fss2 { - ti,cluster-mode = <0>; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer3 { - status = "reserved"; -}; - -&main_timer4 { - status = "reserved"; -}; - -&main_timer5 { - status = "reserved"; -}; - -&main_timer6 { - status = "reserved"; -}; - -&main_timer7 { - status = "reserved"; -}; - -&main_timer8 { - status = "reserved"; -}; - -&main_timer9 { - status = "reserved"; -}; - -&main_r5fss0_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&main_r5fss2_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; - memory-region = <&main_r5fss2_core0_dma_memory_region>, - <&main_r5fss2_core0_memory_region>; -}; - -&main_r5fss2_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; - memory-region = <&main_r5fss2_core1_dma_memory_region>, - <&main_r5fss2_core1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; - -&c71_2 { - status = "okay"; - mboxes = <&mailbox0_cluster5 &mbox_c71_2>; - memory-region = <&c71_2_dma_memory_region>, - <&c71_2_memory_region>; -}; - &c71_3 { - status = "okay"; mboxes = <&mailbox0_cluster5 &mbox_c71_3>; memory-region = <&c71_3_dma_memory_region>, <&c71_3_memory_region>; -}; - -&tscadc0 { - pinctrl-0 = <&mcu_adc0_pins_default>; - pinctrl-names = "default"; - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&tscadc1 { - pinctrl-0 = <&mcu_adc1_pins_default>; - pinctrl-names = "default"; - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&serdes_refclk { - status = "okay"; - clock-frequency = <100000000>; -}; - -&dss { - status = "okay"; - assigned-clocks = <&k3_clks 218 2>, - <&k3_clks 218 5>, - <&k3_clks 218 14>, - <&k3_clks 218 18>; - assigned-clock-parents = <&k3_clks 218 3>, - <&k3_clks 218 7>, - <&k3_clks 218 16>, - <&k3_clks 218 22>; -}; - -&serdes0 { - status = "okay"; - - serdes0_pcie1_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; - }; - - serdes0_usb_link: phy@3 { - reg = <3>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz0 4>; - }; -}; - -&serdes_wiz0 { - status = "okay"; -}; - -&usb_serdes_mux { - idle-states = <0>; /* USB0 to SERDES lane 3 */ -}; - -&usbss0 { - status = "okay"; - pinctrl-0 = <&main_usbss0_pins_default>; - pinctrl-names = "default"; - ti,vbus-divider; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "super-speed"; - phys = <&serdes0_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; - -&serdes_wiz4 { - status = "okay"; -}; - -&serdes4 { - status = "okay"; - serdes4_dp_link: phy@0 { - reg = <0>; - cdns,num-lanes = <4>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, - <&serdes_wiz4 3>, <&serdes_wiz4 4>; - }; -}; - -&mhdp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp0_pins_default>; - phys = <&serdes4_dp_link>; - phy-names = "dpphy"; -}; - -&dss_ports { - /* DP */ - port { - dpi0_out: endpoint { - remote-endpoint = <&dp0_in>; - }; - }; -}; - -&main_i2c4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c4_pins_default>; - clock-frequency = <400000>; - - exp4: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&dp0_ports { - port@0 { - reg = <0>; - - dp0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; - - port@4 { - reg = <4>; - - dp0_out: endpoint { - remote-endpoint = <&dp0_connector_in>; - }; - }; -}; - -&mcu_mcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_pins_default>; - phys = <&transceiver0>; -}; - -&mcu_mcan1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_pins_default>; - phys = <&transceiver1>; -}; - -&main_mcan16 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan16_pins_default>; - phys = <&transceiver2>; -}; - -&main_mcan4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan4_pins_default>; - phys = <&transceiver3>; -}; - -&pcie1_rc { - status = "okay"; - num-lanes = <2>; - reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie1_link>; - phy-names = "pcie-phy"; -}; - -&serdes1 { - status = "okay"; - - serdes1_pcie0_link: phy@0 { - reg = <0>; - cdns,num-lanes = <4>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, - <&serdes_wiz1 3>, <&serdes_wiz1 4>; - }; -}; - -&serdes_wiz1 { - status = "okay"; -}; - -&pcie0_rc { - status = "okay"; - reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; - phys = <&serdes1_pcie0_link>; - phy-names = "pcie-phy"; -}; - -&k3_clks { - /* Confiure AUDIO_EXT_REFCLK1 pin as output */ - pinctrl-names = "default"; - pinctrl-0 = <&audio_ext_refclk1_pins_default>; -}; - -&main_i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c3_pins_default>; - clock-frequency = <400000>; - - exp3: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - pcm3168a_1: audio-codec@44 { - compatible = "ti,pcm3168a"; - reg = <0x44>; - #sound-dai-cells = <1>; - reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; - clocks = <&audio_refclk1>; - clock-names = "scki"; - VDD1-supply = <&vsys_3v3>; - VDD2-supply = <&vsys_3v3>; - VCCAD1-supply = <&vsys_5v0>; - VCCAD2-supply = <&vsys_5v0>; - VCCDA1-supply = <&vsys_5v0>; - VCCDA2-supply = <&vsys_5v0>; - }; -}; - -&mcasp0 { status = "okay"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcasp0_pins_default>; - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - auxclk-fs-ratio = <256>; - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 0 1 - 2 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-evm-ethfw.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-evm-ethfw.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-evm-ethfw.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-evm-ethfw.dtso 2026-04-21 11:35:28.562915320 +0200 @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for CPSW9G functionality with Ethernet Switch Firmware (EthFw) + * and CPSW Proxy Client driver. + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-serdes.h" + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , + , , + , , + , ; +}; + +/* uart2 is assigned to EthFw running on remote CPU core */ +&main_uart2 { + status = "reserved"; +}; + +/* Reserve shared memory for inter-core network communication */ +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + + main_r5fss0_core0_shared_memory_queue_region:r5f-virtual-eth-queues@af000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaf000000 0x00 0x200000>; + no-map; + }; + + main_r5fss0_core0_shared_memory_bufpool_region:r5f-virtual-eth-buffers@af200000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaf200000 0x00 0x1e00000>; + no-map; + }; +}; + +&main_r5fss0_core0 { + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>, + <&main_r5fss0_core0_shared_memory_queue_region>, + <&main_r5fss0_core0_shared_memory_bufpool_region>; +}; + +/* EthFw uses timers so mark them reserved */ +&main_timer12 { + status = "reserved"; +}; + +&main_timer13 { + status = "reserved"; +}; + +/* + * Disable the following to avoid overloading exp2. + * Otherwise it will result in PHY read/write errors. + */ +&main_mcan4 { + status = "disabled"; +}; + +&transceiver3 { + status = "disabled"; +}; + +&mux1 { + status = "disabled"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-evm-fpdlink-iv-fusion.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-evm-fpdlink-iv-fusion.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-evm-fpdlink-iv-fusion.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-evm-fpdlink-iv-fusion.dtso 2026-04-21 11:35:28.562915320 +0200 @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * DT Overlay for FPDLink IV UB9702 Deserializer on J784S4 EVM + * https://www.ti.com/tool/J7EXPA01EVM + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&exp5 { + p0-hog{ + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI2_EXP_RSTZ"; + }; +}; + +&main_i2c5 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + deser@3d { + compatible = "ti,ds90ub9702-q1"; + reg = <0x3d>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub970_0_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + deser@30 { + compatible = "ti,ds90ub9702-q1"; + reg = <0x30>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + deserializer_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub970_1_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + deserializer_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + deser@32 { + compatible = "ti,ds90ub9702-q1"; + reg = <0x32>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x6a 0x6b 0x6c 0x6d 0x6e 0x6f>; + + deserializer_2_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub970_2_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy2>; + }; + }; + }; + + deserializer_2_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub970_0_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub970_1_csi_out>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy2: endpoint { + remote-endpoint = <&ds90ub970_2_csi_out>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&ti_csi2rx2 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; + +&dphy2 { + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso 2026-04-21 11:35:28.562915320 +0200 @@ -75,5 +75,6 @@ dma-coherent; phys = <&serdes0_pcie1_link>; phy-names = "pcie-phy"; + bootph-all; }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso 2026-04-21 11:35:28.563915322 +0200 @@ -102,13 +102,6 @@ gpios = <16 GPIO_ACTIVE_HIGH>; output-low; }; - - /* Toggle MUX2 for MDIO lines */ - mux-sel-hog { - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>; - output-high; - }; }; &main_pmx0 { diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi 2026-04-21 11:35:28.563915322 +0200 @@ -80,6 +80,7 @@ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Time Sync Router */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */ <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */ diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi 2026-04-21 11:35:28.564915325 +0200 @@ -0,0 +1,1721 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * EVM Board Schematics(j784s4): https://www.ti.com/lit/zip/sprr458 + * EVM Board Schematics(j742s2): https://www.ti.com/lit/zip/SPAC001 + */ + +#include "k3-timesync-router.h" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + }; + + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart8; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + i2c0 = &wkup_i2c0; + i2c3 = &main_i2c0; + ethernet0 = &mcu_cpsw_port1; + ethernet1 = &main_cpsw1_port1; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x70000000>; + linux,cma-default; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core0_memory_region: r5f-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core1_memory_region: r5f-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a9000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a9100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9100000 0x00 0xf00000>; + no-map; + }; + + c71_2_dma_memory_region: c71-dma-memory@aa000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa000000 0x00 0x100000>; + no-map; + }; + + c71_2_memory_region: c71-memory@aa100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa100000 0x00 0xf00000>; + no-map; + }; + }; + + evm_12v0: regulator-evm12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: regulator-vsys3v3 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_5v0: regulator-vsys5v0 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-sd { + /* Output of TPS22918 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vsys_3v3>; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: regulator-TLV71033 { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + dp0_pwr_3v3: regulator-dp0-prw { + compatible = "regulator-fixed"; + regulator-name = "dp0-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + dp0: connector-dp0 { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; + + transceiver0: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>; + }; + + transceiver1: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy2 { + /* standby pin has been grounded by default */ + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy3 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp2 7 GPIO_ACTIVE_HIGH>; + mux-states = <&mux1 1>; + }; + + mux1: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp2 14 GPIO_ACTIVE_HIGH>; + idle-state = <1>; + }; + + codec_audio: sound { + compatible = "ti,j7200-cpb-audio"; + model = "j784s4-cpb"; + + ti,cpb-mcasp = <&mcasp0>; + ti,cpb-codec = <&pcm3168a_1>; + + clocks = <&k3_clks 265 0>, <&k3_clks 265 1>, + <&k3_clks 157 34>, <&k3_clks 157 63>; + clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", + "cpb-codec-scki", "cpb-codec-scki-48000"; + }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + edp1_refclk: clock-edp1-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + dp1_pwr_3v3: regulator-dp1-prw { + compatible = "regulator-fixed"; + regulator-name = "dp1-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + dp1: connector-dp1 { + compatible = "dp-connector"; + label = "DP1"; + type = "full-size"; + dp-pwr-supply = <&dp1_pwr_3v3>; + + port { + dp1_connector_in: endpoint { + remote-endpoint = <&dp1_out>; + }; + }; + }; +}; + +&wkup_gpio0 { + status = "okay"; +}; + +&main_pmx0 { + bootph-all; + main_cpsw2g_default_pins: main-cpsw2g-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ + J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ + J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ + J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ + J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */ + J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ + J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ + J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ + J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ + J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ + J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */ + >; + }; + + main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ + J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + + main_uart8_pins_default: main-uart8-default-pins { + bootph-all; + pinctrl-single,pins = < + J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ + J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ + J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ + J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0e0, PIN_INPUT, 0) /* (AN36) I2C0_SCL */ + J784S4_IOPAD(0x0e4, PIN_INPUT, 0) /* (AP37) I2C0_SDA */ + >; + }; + + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ + J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ + >; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; + pinctrl-single,pins = < + J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ + J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ + J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ + J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ + J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ + J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ + J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ + J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ + >; + }; + + dp0_pins_default: dp0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ + >; + }; + + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ + J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ + >; + }; + + main_mcan4_pins_default: main-mcan4-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x088, PIN_INPUT, 0) /* (AF36) MCAN4_RX */ + J784S4_IOPAD(0x084, PIN_OUTPUT, 0) /* (AG38) MCAN4_TX */ + >; + }; + + main_mcan16_pins_default: main-mcan16-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */ + J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */ + >; + }; + + main_usbss0_pins_default: main-usbss0-default-pins { + bootph-all; + pinctrl-single,pins = < + J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ + >; + }; + + main_i2c3_pins_default: main-i2c3-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x064, PIN_INPUT, 13) /* (AF38) MCAN0_TX.I2C3_SCL */ + J784S4_IOPAD(0x060, PIN_INPUT, 13) /* (AE36) MCASP2_AXR1.I2C3_SDA */ + >; + }; + + main_mcasp0_pins_default: main-mcasp0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x038, PIN_OUTPUT_PULLDOWN, 1) /* (AK35) MCASP0_ACLKX */ + J784S4_IOPAD(0x03c, PIN_OUTPUT_PULLDOWN, 1) /* (AK38) MCASP0_AFSX */ + J784S4_IOPAD(0x07c, PIN_OUTPUT_PULLDOWN, 1) /* (AJ38) MCASP0_AXR3 */ + J784S4_IOPAD(0x080, PIN_INPUT_PULLDOWN, 1) /* (AK34) MCASP0_AXR4 */ + >; + }; + + audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */ + >; + }; +}; + +&wkup_pmx2 { + bootph-all; + wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-all; + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-all; + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-all; + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ + J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + + mcu_cpsw_pins_default: mcu-cpsw-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ + J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ + J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ + J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ + J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ + J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ + J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + >; + }; + + mcu_adc0_pins_default: mcu-adc0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ + J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ + J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ + J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ + J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ + J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ + J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ + J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ + >; + }; + + mcu_adc1_pins_default: mcu-adc1-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ + J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ + J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ + J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ + J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ + J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ + J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ + J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ + >; + }; + + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ + J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ + >; + }; + + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_69 */ + >; + }; + + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ + >; + }; + + wkup_gpio_pins_default: wkup_gpio_pins_default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 7) /* (L37) WKUP_GPIO0_6 */ + >; + }; +}; + +&wkup_pmx1 { + status = "okay"; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) + >; + }; +}; + +&wkup_pmx0 { + bootph-all; + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + bootph-all; + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ + J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ + >; + }; +}; + +&wkup_pmx1 { + bootph-all; + mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { + bootph-all; + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ + >; + }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + bootph-all; + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ + J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ + J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ + J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ + >; + }; +}; + +&wkup_uart0 { + /* Firmware usage */ + status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&wkup_i2c0 { + bootph-all; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; + + tps659413: pmic@48 { + compatible = "ti,tps6594-q1"; + reg = <0x48>; + system-power-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&wkup_gpio0>; + interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + ti,primary-pmic; + buck12-supply = <&vsys_3v3>; + buck3-supply = <&vsys_3v3>; + buck4-supply = <&vsys_3v3>; + buck5-supply = <&vsys_3v3>; + ldo1-supply = <&vsys_3v3>; + ldo2-supply = <&vsys_3v3>; + ldo3-supply = <&vsys_3v3>; + ldo4-supply = <&vsys_3v3>; + + regulators { + bucka12: buck12 { + regulator-name = "vdd_ddr_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + bucka3: buck3 { + regulator-name = "vdd_ram_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + bucka4: buck4 { + regulator-name = "vdd_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + bucka5: buck5 { + regulator-name = "vdd_mcu_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldoa1: ldo1 { + regulator-name = "vdd_mcuio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldoa2: ldo2 { + regulator-name = "vdd_mcuio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldoa3: ldo3 { + regulator-name = "vds_dll_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldoa4: ldo4 { + regulator-name = "vda_mcu_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + }; + }; + + tps62873a: regulator@40 { + compatible = "ti,tps62873"; + reg = <0x40>; + bootph-pre-ram; + regulator-name = "VDD_CPU_AVS"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1330000>; + regulator-boot-on; + regulator-always-on; + }; + + tps62873b: regulator@43 { + compatible = "ti,tps62873"; + reg = <0x43>; + regulator-name = "VDD_CORE_0V8"; + regulator-min-microvolt = <760000>; + regulator-max-microvolt = <840000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&mcu_uart0 { + bootph-all; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; +}; + +&main_uart8 { + bootph-all; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart8_pins_default>; +}; + +&ufs_wrapper { + status = "okay"; +}; + +&wkup_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; +}; + +&fss { + bootph-all; + status = "okay"; +}; + +&ospi0 { + bootph-all; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; + + ospi0_nor: flash@0 { + bootph-all; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + cdns,phy-mode; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-all; + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; + + ospi0_nand: nand@0 { + compatible = "spi-nand"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + cdns,phy-mode; + status = "disabled"; + bootph-pre-ram; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi_nand.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi_nand.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi_nand.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi_nand.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi_nand.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@2000000 { + label = "ospi_nand.rootfs"; + reg = <0x2000000 0x5fc0000>; + }; + + partition@7fc0000 { + bootph-all; + label = "ospi_nand.phypattern"; + reg = <0x7fc0000 0x40000>; + }; + }; + }; +}; + +&ospi1 { + bootph-all; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + + ospi1_nor: flash@0 { + bootph-all; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qspi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "qspi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "qspi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "qspi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "qspi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "qspi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-all; + label = "qspi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + + }; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + + clock-frequency = <400000>; + + exp1: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ", + "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", + "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", + "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", + "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; + + p12-hog { + /* P12 - AUDIO_MUX_SEL */ + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "AUDIO_MUX_SEL"; + }; + }; + + exp2: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN", + "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", + "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", + "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", + "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", + "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", + "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", + "USER_INPUT1", "USER_LED1", "USER_LED2"; + + p13-hog { + /* P13 - CANUART_MUX_SEL0 */ + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CANUART_MUX_SEL0"; + }; + + p15-hog { + /* P15 - CANUART_MUX1_SEL1 */ + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CANUART_MUX1_SEL1"; + }; + }; +}; + +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + +&main_sdhci0 { + bootph-all; + /* eMMC */ + status = "okay"; + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&main_sdhci1 { + bootph-all; + /* SD card */ + status = "okay"; + pinctrl-0 = <&main_mmc1_pins_default>; + pinctrl-names = "default"; + disable-wp; + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; +}; + +&main_gpio0 { + status = "okay"; +}; + +&mcu_cpsw { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default>; + + cpts@3d000 { + /* Map HW4_TS_PUSH to GENF1 */ + ti,pps = <3 1>; + }; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mdio_pins_default>; + + mcu_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&mcu_cpsw_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&mcu_phy0>; +}; + +&main_cpsw1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw2g_default_pins>; + status = "okay"; +}; + +&main_cpsw1_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw2g_mdio_default_pins>; + status = "okay"; + + main_cpsw1_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&main_cpsw1_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&main_cpsw1_phy0>; + status = "okay"; +}; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + interrupts = <424>; + + mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster5 { + status = "okay"; + interrupts = <416>; + + mbox_c71_2: mbox-c71-2 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mcu_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0 { + ti,cluster-mode = <0>; +}; + +&main_r5fss1 { + ti,cluster-mode = <0>; +}; + +&main_r5fss2 { + ti,cluster-mode = <0>; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&main_timer3 { + status = "reserved"; +}; + +&main_timer4 { + status = "reserved"; +}; + +&main_timer5 { + status = "reserved"; +}; + +&main_timer6 { + status = "reserved"; +}; + +&main_timer7 { + status = "reserved"; +}; + +&main_timer8 { + status = "reserved"; +}; + +&main_timer9 { + status = "reserved"; +}; + +&main_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&main_r5fss2_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; + memory-region = <&main_r5fss2_core0_dma_memory_region>, + <&main_r5fss2_core0_memory_region>; +}; + +&main_r5fss2_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; + memory-region = <&main_r5fss2_core1_dma_memory_region>, + <&main_r5fss2_core1_memory_region>; +}; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; + +&c71_2 { + status = "okay"; + mboxes = <&mailbox0_cluster5 &mbox_c71_2>; + memory-region = <&c71_2_dma_memory_region>, + <&c71_2_memory_region>; +}; + +&tscadc0 { + pinctrl-0 = <&mcu_adc0_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&tscadc1 { + pinctrl-0 = <&mcu_adc1_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&serdes_refclk { + status = "okay"; + clock-frequency = <100000000>; + bootph-all; +}; + +&dss { + status = "okay"; + assigned-clocks = <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + assigned-clock-parents = <&k3_clks 218 3>, + <&k3_clks 218 7>, + <&k3_clks 218 16>, + <&k3_clks 218 22>; +}; + +&pcie1_ctrl { + bootph-all; +}; + +&serdes_ln_ctrl { + bootph-all; +}; + +&serdes0 { + status = "okay"; + + serdes0_pcie1_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + bootph-all; + }; + + serdes0_usb_link: phy@3 { + bootph-all; + reg = <3>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 4>; + }; +}; + +&serdes_wiz0 { + status = "okay"; +}; + +&usb_serdes_mux { + idle-states = <0>; /* USB0 to SERDES lane 3 */ +}; + +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&serdes_wiz4 { + status = "okay"; +}; + +&serdes4 { + status = "okay"; + serdes4_dp_link: phy@0 { + reg = <0>; + cdns,num-lanes = <4>; + #phy-cells = <0>; + cdns,phy-type = ; + cdns,max-bit-rate = <2700>; + resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, + <&serdes_wiz4 3>, <&serdes_wiz4 4>; + }; +}; + +&mhdp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; + phys = <&serdes4_dp_link>; + phy-names = "dpphy"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* DP */ + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; + + /* DSI */ + port@2 { + reg = <2>; + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&main_i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <400000>; + + exp4: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + dsi_edp_bridge: dsi-edp-bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clock-names = "refclk"; + clocks = <&edp1_refclk>; + + enable-gpios = <&exp4 2 GPIO_ACTIVE_HIGH>; + + vpll-supply = <&vsys_io_1v8>; + vccio-supply = <&vsys_io_1v8>; + vcca-supply = <&vsys_io_1v2>; + vcc-supply = <&vsys_io_1v2>; + + dsi_edp_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp1_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + dp1_out: endpoint { + remote-endpoint = <&dp1_connector_in>; + }; + }; + }; + }; +}; + +&dsi0_ports { + port@0 { + reg = <0>; + dsi0_out: endpoint { + remote-endpoint = <&dp1_in>; + }; + }; + + port@1 { + reg = <1>; + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +&dp0_ports { + port@0 { + reg = <0>; + + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + + dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; +}; + +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver0>; +}; + +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver1>; +}; + +&main_mcan16 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan16_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan4_pins_default>; + phys = <&transceiver3>; +}; + +&pcie1_rc { + status = "okay"; + num-lanes = <2>; + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie1_link>; + phy-names = "pcie-phy"; +}; + +&serdes1 { + status = "okay"; + + serdes1_pcie0_link: phy@0 { + reg = <0>; + cdns,num-lanes = <4>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, + <&serdes_wiz1 3>, <&serdes_wiz1 4>; + }; +}; + +&serdes_wiz1 { + status = "okay"; +}; + +&pcie0_rc { + status = "okay"; + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + phys = <&serdes1_pcie0_link>; + phy-names = "pcie-phy"; +}; + +&k3_clks { + /* Confiure AUDIO_EXT_REFCLK1 pin as output */ + pinctrl-names = "default"; + pinctrl-0 = <&audio_ext_refclk1_pins_default>; +}; + +&main_i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c3_pins_default>; + clock-frequency = <400000>; + + exp3: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pcm3168a_1: audio-codec@44 { + compatible = "ti,pcm3168a"; + reg = <0x44>; + #sound-dai-cells = <1>; + reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; + clocks = <&audio_refclk1>; + clock-names = "scki"; + VDD1-supply = <&vsys_3v3>; + VDD2-supply = <&vsys_3v3>; + VCCAD1-supply = <&vsys_5v0>; + VCCAD2-supply = <&vsys_5v0>; + VCCDA1-supply = <&vsys_5v0>; + VCCDA2-supply = <&vsys_5v0>; + }; +}; + +&mcasp0 { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp0_pins_default>; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + auxclk-fs-ratio = <256>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 0 1 + 2 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; +}; + +×ync_router { + /* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */ + mux-reg-masks-state = < + /* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */ + K3_TS_OFFSET(25, 0x0001ffff, 17) + >; + status = "okay"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-pcie-ntb.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-pcie-ntb.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-pcie-ntb.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-pcie-ntb.dtso 2026-04-21 11:35:28.564915325 +0200 @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling NTB functionality using PCIE0 and PCIE1 instances of + * PCIe on the J784S4 EVM and the J742S2 EVM. + * + * J784S4 EVM Product Link: https://www.ti.com/tool/J784S4XEVM + * J742S2 EVM Product Link: https://www.ti.com/tool/J742S2XH01EVM + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + epf_bus { + compatible = "pci-epf-bus"; + + ntb { + compatible = "pci-epf-ntb"; + epcs = <&pcie0_ep>, <&pcie1_ep>; + epc-names = "primary", "secondary"; + vendor-id = /bits/ 16 <0x104c>; + device-id = /bits/ 16 <0xb012>; + num-mws = <4>; + mws-size = <0x100000>, <0x100000>, <0x100000>, <0x100000>; + }; + }; +}; + +&pcie0_rc { + status = "disabled"; +}; + +&pcie1_rc { + status = "disabled"; +}; + +&cbass_main { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + + pcie0_ep: pcie-ep@2900000 { + compatible = "ti,j784s4-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 332 0>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes1_pcie0_link>; + phy-names = "pcie-phy"; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j784s4-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 333 0>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes0_pcie1_link>; + phy-names = "pcie-phy"; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso 2026-04-21 11:35:28.564915325 +0200 @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling USB0 instance of USB on J784S4 and J742S2 EVMs for + * Host Mode of operation with the Type-A Connector. + * + * J784S4 EVM Product Link: https://www.ti.com/tool/J784S4XEVM + * J742S2 EVM Product Link: https://www.ti.com/tool/J742S2XH01EVM + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&exp2 { + p12-hog { + /* P12 - USB2.0_MUX_SEL */ + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "USB2.0_MUX_SEL"; + }; +}; + +&usb0 { + dr_mode = "host"; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi 2026-04-21 11:35:28.564915325 +0200 @@ -7,6 +7,7 @@ #include #include +#include #include #include "k3-serdes.h" @@ -126,6 +127,11 @@ assigned-clock-parents = <&k3_clks 157 63>; #clock-cells = <0>; }; + + acspcie0_proxy_ctrl: clock-controller@1a090 { + compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon"; + reg = <0x1a090 0x4>; + }; }; main_ehrpwm0: pwm@3000000 { @@ -226,7 +232,7 @@ }; main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x11c000 0x00 0x120>; #pinctrl-cells = <1>; @@ -236,7 +242,7 @@ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ main_timerio_input: pinctrl@104200 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x00 0x104200 0x00 0x50>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -245,7 +251,7 @@ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ main_timerio_output: pinctrl@104280 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x00 0x104280 0x00 0x20>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -801,14 +807,20 @@ ranges; #address-cells = <2>; #size-cells = <2>; - dmas = <&main_bcdma_csi 0 0x4940 0>; - dma-names = "rx0"; + dmas = <&main_bcdma_csi 0 0x4940 0>, <&main_bcdma_csi 0 0x4941 0>, + <&main_bcdma_csi 0 0x4942 0>, <&main_bcdma_csi 0 0x4943 0>, + <&main_bcdma_csi 0 0x4944 0>, <&main_bcdma_csi 0 0x4945 0>, + <&main_bcdma_csi 0 0x4946 0>, <&main_bcdma_csi 0 0x4947 0>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7"; power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; cdns_csi2rx0: csi-bridge@4504000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x04504000 0x00 0x00001000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -854,14 +866,20 @@ ranges; #address-cells = <2>; #size-cells = <2>; - dmas = <&main_bcdma_csi 0 0x4960 0>; - dma-names = "rx0"; + dmas = <&main_bcdma_csi 0 0x4960 0>, <&main_bcdma_csi 0 0x4961 0>, + <&main_bcdma_csi 0 0x4962 0>, <&main_bcdma_csi 0 0x4963 0>, + <&main_bcdma_csi 0 0x4964 0>, <&main_bcdma_csi 0 0x4965 0>, + <&main_bcdma_csi 0 0x4966 0>, <&main_bcdma_csi 0 0x4967 0>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7"; power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; cdns_csi2rx1: csi-bridge@4514000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x04514000 0x00 0x00001000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -906,14 +924,20 @@ ranges; #address-cells = <2>; #size-cells = <2>; - dmas = <&main_bcdma_csi 0 0x4980 0>; - dma-names = "rx0"; + dmas = <&main_bcdma_csi 0 0x4980 0>, <&main_bcdma_csi 0 0x4981 0>, + <&main_bcdma_csi 0 0x4982 0>, <&main_bcdma_csi 0 0x4983 0>, + <&main_bcdma_csi 0 0x4984 0>, <&main_bcdma_csi 0 0x4985 0>, + <&main_bcdma_csi 0 0x4986 0>, <&main_bcdma_csi 0 0x4987 0>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7"; power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; cdns_csi2rx2: csi-bridge@4524000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x04524000 0x00 0x00001000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -983,6 +1007,7 @@ interrupts = ; clocks = <&k3_clks 241 2>; power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; + sram = <&main_navss_sram>; }; vpu1: video-codec@4220000 { @@ -991,6 +1016,7 @@ interrupts = ; clocks = <&k3_clks 242 2>; power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + sram = <&main_navss_sram>; }; main_sdhci0: mmc@4f80000 { @@ -1055,7 +1081,7 @@ reg = <0x00 0x02900000 0x00 0x1000>, <0x00 0x02907000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x00001000>; + <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; @@ -1073,8 +1099,8 @@ device-id = <0xb012>; msi-map = <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status = "disabled"; }; @@ -1084,7 +1110,7 @@ reg = <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; + <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; @@ -1093,8 +1119,8 @@ max-link-speed = <3>; num-lanes = <4>; power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 333 0>; - clock-names = "fck"; + clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0xff>; @@ -1102,9 +1128,10 @@ device-id = <0xb012>; msi-map = <0x0 &gic_its 0x10000 0x10000>; dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x1>; status = "disabled"; }; @@ -1235,6 +1262,14 @@ dma-coherent; dma-ranges; + main_navss_sram: navss-sram@30000000{ + compatible = "mmio-sram"; + reg = <0x00 0x30000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x30000000 0x10000>; + }; + main_navss_intr: interrupt-controller@310e0000 { compatible = "ti,sci-intr"; reg = <0x00 0x310e0000 0x00 0x4000>; @@ -2042,7 +2077,7 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 376 1>; + clocks = <&k3_clks 376 0>; status = "disabled"; }; @@ -2053,7 +2088,7 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 377 1>; + clocks = <&k3_clks 377 0>; status = "disabled"; }; @@ -2064,7 +2099,7 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 378 1>; + clocks = <&k3_clks 378 0>; status = "disabled"; }; @@ -2075,7 +2110,7 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 379 1>; + clocks = <&k3_clks 379 0>; status = "disabled"; }; @@ -2086,7 +2121,7 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 380 1>; + clocks = <&k3_clks 380 0>; status = "disabled"; }; @@ -2097,7 +2132,7 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 381 1>; + clocks = <&k3_clks 381 0>; status = "disabled"; }; @@ -2108,7 +2143,7 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 382 1>; + clocks = <&k3_clks 382 0>; status = "disabled"; }; @@ -2119,7 +2154,7 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 383 1>; + clocks = <&k3_clks 383 0>; status = "disabled"; }; @@ -2350,42 +2385,6 @@ assigned-clock-parents = <&k3_clks 351 4>; }; - watchdog4: watchdog@2240000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2240000 0x00 0x100>; - clocks = <&k3_clks 352 0>; - power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 352 0>; - assigned-clock-parents = <&k3_clks 352 4>; - }; - - watchdog5: watchdog@2250000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2250000 0x00 0x100>; - clocks = <&k3_clks 353 0>; - power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 353 0>; - assigned-clock-parents = <&k3_clks 353 4>; - }; - - watchdog6: watchdog@2260000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2260000 0x00 0x100>; - clocks = <&k3_clks 354 0>; - power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 354 0>; - assigned-clock-parents = <&k3_clks 354 4>; - }; - - watchdog7: watchdog@2270000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2270000 0x00 0x100>; - clocks = <&k3_clks 355 0>; - power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 355 0>; - assigned-clock-parents = <&k3_clks 355 4>; - }; - /* * The following RTI instances are coupled with MCU R5Fs, c7x and * GPU so keeping them reserved as these will be used by their @@ -2512,6 +2511,50 @@ status = "reserved"; }; + dphy_tx0: phy@4480000 { + compatible = "ti,j721e-dphy"; + reg = <0x0 0x04480000 0x0 0x1000>; + clocks = <&k3_clks 402 20>, <&k3_clks 402 3>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 402 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 402 3>; + assigned-clock-parents = <&k3_clks 402 4>; + assigned-clock-rates = <19200000>; + status = "disabled"; + }; + + dsi0: dsi@4800000 { + compatible = "ti,j721e-dsi"; + reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>; + clocks = <&k3_clks 215 2>, <&k3_clks 215 5>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; + interrupt-parent = <&gic500>; + interrupts = ; + phys = <&dphy_tx0>; + phy-names = "dphy"; + status = "disabled"; + + dsi0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + }; + }; + + timesync_router: mux-controller@a40000 { + compatible = "reg-mux"; + reg = <0x0 0xa40000 0x0 0x800>; + #mux-control-cells = <1>; + status = "disabled"; + }; + mhdp: bridge@a000000 { compatible = "ti,j721e-mhdp8546"; reg = <0x0 0xa000000 0x0 0x30a00>, @@ -2670,4 +2713,17 @@ power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; + + gpu: gpu@4e20000000 { + compatible = "ti,j721s2-pvr", "img,pvr-bxs64"; + reg = <0x4e 0x20000000 0x00 0x80000>; + interrupts = ; + power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + power-domain-names = "firmware", "dust"; + clocks = <&k3_clks 181 1>; + assigned-clocks = <&k3_clks 181 1>; + assigned-clock-rates = <800000000>; + clock-names = "core"; + }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi 2026-04-21 11:35:28.565915328 +0200 @@ -7,7 +7,6 @@ &cbass_mcu_wakeup { sms: system-controller@44083000 { - bootph-all; compatible = "ti,k2g-sci"; ti,host-id = <12>; @@ -39,7 +38,6 @@ }; wkup_conf: bus@43000000 { - bootph-all; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -59,6 +57,8 @@ reg = <0x00 0x43600000 0x00 0x10000>, <0x00 0x44880000 0x00 0x20000>, <0x00 0x44860000 0x00 0x20000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -76,7 +76,7 @@ }; wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c000 0x00 0x034>; #pinctrl-cells = <1>; @@ -85,7 +85,7 @@ }; wkup_pmx1: pinctrl@4301c038 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c038 0x00 0x02c>; #pinctrl-cells = <1>; @@ -94,7 +94,7 @@ }; wkup_pmx2: pinctrl@4301c068 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c068 0x00 0x120>; #pinctrl-cells = <1>; @@ -103,7 +103,7 @@ }; wkup_pmx3: pinctrl@4301c190 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c190 0x00 0x004>; #pinctrl-cells = <1>; @@ -125,7 +125,7 @@ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ mcu_timerio_input: pinctrl@40f04200 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x00 0x40f04200 0x00 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -136,7 +136,7 @@ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ mcu_timerio_output: pinctrl@40f04280 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x00 0x40f04280 0x00 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -172,13 +172,13 @@ assigned-clocks = <&k3_clks 35 2>; assigned-clock-parents = <&k3_clks 35 3>; power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-all; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; }; mcu_timer1: timer@40410000 { - bootph-all; compatible = "ti,am654-timer"; reg = <0x00 0x40410000 0x00 0x400>; interrupts = ; @@ -458,7 +458,6 @@ }; mcu_navss: bus@28380000 { - bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -515,6 +514,8 @@ reg = <0x00 0x2a480000 0x00 0x80000>, <0x00 0x2a380000 0x00 0x80000>, <0x00 0x2a400000 0x00 0x80000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -588,7 +589,7 @@ mcu_r5fss0: r5fss@41000000 { compatible = "ti,j721s2-r5fss"; - ti,cluster-mode = <1>; + ti,cluster-mode = <0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x41000000 0x00 0x41000000 0x20000>, @@ -632,6 +633,7 @@ <0x00 0x42050000 0x00 0x350>; power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; + bootph-pre-ram; }; tscadc0: tscadc@40200000 { @@ -692,6 +694,7 @@ cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; + cdns,phase-detect-selector = <2>; clocks = <&k3_clks 161 7>; assigned-clocks = <&k3_clks 161 7>; assigned-clock-parents = <&k3_clks 161 9>; @@ -710,6 +713,7 @@ cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; + cdns,phase-detect-selector = <2>; clocks = <&k3_clks 162 7>; power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi 2026-04-21 11:35:28.565915328 +0200 @@ -113,6 +113,126 @@ status = "disabled"; }; }; + + watchdog4: watchdog@2240000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2240000 0x00 0x100>; + clocks = <&k3_clks 352 0>; + power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 352 0>; + assigned-clock-parents = <&k3_clks 352 4>; + }; + + watchdog5: watchdog@2250000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2250000 0x00 0x100>; + clocks = <&k3_clks 353 0>; + power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 353 0>; + assigned-clock-parents = <&k3_clks 353 4>; + }; + + watchdog6: watchdog@2260000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2260000 0x00 0x100>; + clocks = <&k3_clks 354 0>; + power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 354 0>; + assigned-clock-parents = <&k3_clks 354 4>; + }; + + watchdog7: watchdog@2270000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2270000 0x00 0x100>; + clocks = <&k3_clks 355 0>; + power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 355 0>; + assigned-clock-parents = <&k3_clks 355 4>; + }; + + memorycontroller0: memory-controller@2980000 { + compatible = "ti,j7-ddrss"; + reg = <0x0 0x02980000 0x0 0x200>; + reg-names = "ss_cfg"; + ranges = <0x00 0x00 0x00 0x02990000 0x00 0x00004000>; + interrupts = ; + power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>, + <&k3_pds 46 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 191 1>; + #address-cells = <2>; + #size-cells = <2>; + + ddr0: ddr@0 { + compatible = "cdns,j7-ddr"; + reg = <0x00 0x0000 0x00 0x72c>, + <0x00 0x2000 0x00 0x4b0>, + <0x00 0x4000 0x00 0x163c>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + }; + }; + + memorycontroller1: memory-controller@29a0000 { + compatible = "ti,j7-ddrss"; + reg = <0x0 0x029a0000 0x0 0x200>; + reg-names = "ss_cfg"; + ranges = <0x00 0x00 0x00 0x029b0000 0x00 0x00004000>; + interrupts = ; + power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>, + <&k3_pds 47 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 192 1>; + #address-cells = <2>; + #size-cells = <2>; + + ddr1: ddr@0 { + compatible = "cdns,j7-ddr"; + reg = <0x00 0x0000 0x00 0x72c>, + <0x00 0x2000 0x00 0x4b0>, + <0x00 0x4000 0x00 0x163c>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + }; + }; + + memorycontroller2: memory-controller@29c0000 { + compatible = "ti,j7-ddrss"; + reg = <0x0 0x029c0000 0x0 0x200>; + reg-names = "ss_cfg"; + ranges = <0x00 0x00 0x00 0x029d0000 0x00 0x00004000>; + interrupts = ; + power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>, + <&k3_pds 48 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 193 1>; + #address-cells = <2>; + #size-cells = <2>; + + ddr2: ddr@0 { + compatible = "cdns,j7-ddr"; + reg = <0x00 0x0000 0x00 0x72c>, + <0x00 0x2000 0x00 0x4b0>, + <0x00 0x4000 0x00 0x163c>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + }; + }; + + memorycontroller3: memory-controller@29e0000 { + compatible = "ti,j7-ddrss"; + reg = <0x0 0x029e0000 0x0 0x200>; + reg-names = "ss_cfg"; + ranges = <0x00 0x00 0x00 0x029f0000 0x00 0x00004000>; + interrupts = ; + power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>, + <&k3_pds 49 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 194 1>; + #address-cells = <2>; + #size-cells = <2>; + + ddr3: ddr@0 { + compatible = "cdns,j7-ddr"; + reg = <0x00 0x0000 0x00 0x72c>, + <0x00 0x2000 0x00 0x4b0>, + <0x00 0x4000 0x00 0x163c>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + }; + }; }; &scm_conf { diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-pinctrl.h v_kernel/arch/arm64/boot/dts/ti/k3-pinctrl.h --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-pinctrl.h 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-pinctrl.h 2026-04-21 11:35:28.565915328 +0200 @@ -3,16 +3,32 @@ * This header provides constants for pinctrl bindings for TI's K3 SoC * family. * - * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef DTS_ARM64_TI_K3_PINCTRL_H #define DTS_ARM64_TI_K3_PINCTRL_H +#define WKUP_LVL_EN_SHIFT (7) +#define WKUP_LVL_POL_SHIFT (8) #define ST_EN_SHIFT (14) #define PULLUDEN_SHIFT (16) #define PULLTYPESEL_SHIFT (17) #define RXACTIVE_SHIFT (18) +#define DRV_STR_SHIFT (19) +#define ISO_OVERRIDE_EN_SHIFT (22) +#define ISO_BYPASS_EN_SHIFT (23) #define DEBOUNCE_SHIFT (11) +#define FORCE_DS_EN_SHIFT (15) +#define DS_EN_SHIFT (24) +#define DS_OUT_DIS_SHIFT (25) +#define DS_OUT_VAL_SHIFT (26) +#define DS_PULLUD_EN_SHIFT (27) +#define DS_PULLTYPE_SEL_SHIFT (28) +#define WKUP_EN_SHIFT (29) + +/* Schmitt trigger configuration */ +#define ST_DISABLE (0 << ST_EN_SHIFT) +#define ST_ENABLE (1 << ST_EN_SHIFT) /* Schmitt trigger configuration */ #define ST_DISABLE (0 << ST_EN_SHIFT) @@ -27,6 +43,29 @@ #define INPUT_EN (1 << RXACTIVE_SHIFT) #define INPUT_DISABLE (0 << RXACTIVE_SHIFT) +#define DS_PULL_DISABLE (1 << DS_PULLUD_EN_SHIFT) +#define DS_PULL_ENABLE (0 << DS_PULLUD_EN_SHIFT) + +#define DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENABLE) +#define DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENABLE) + +#define DS_STATE_EN (1 << DS_EN_SHIFT) +#define DS_STATE_DISABLE (0 << DS_EN_SHIFT) + +#define DS_INPUT_EN (1 << DS_OUT_DIS_SHIFT | DS_STATE_EN) +#define DS_INPUT_DISABLE (0 << DS_OUT_DIS_SHIFT | DS_STATE_EN) + +#define DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) +#define DS_OUT_VALUE_ONE (1 << DS_OUT_VAL_SHIFT) + +/* Configuration to enable wake-up on pin activity */ +#define WKUP_ENABLE (1 << WKUP_EN_SHIFT) +#define WKUP_DISABLE (0 << WKUP_EN_SHIFT) +#define WKUP_ON_LEVEL (1 << WKUP_LVL_EN_SHIFT) +#define WKUP_ON_EDGE (0 << WKUP_LVL_EN_SHIFT) +#define WKUP_LEVEL_LOW (0 << WKUP_LVL_POL_SHIFT) +#define WKUP_LEVEL_HIGH (1 << WKUP_LVL_POL_SHIFT) + /* Only these macros are expected be used directly in device tree files */ #define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) #define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) @@ -47,15 +86,49 @@ #define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) #define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) +#define PIN_DRIVE_STRENGTH_NOMINAL (0 << DRV_STR_SHIFT) +#define PIN_DRIVE_STRENGTH_SLOW (1 << DRV_STR_SHIFT) +#define PIN_DRIVE_STRENGTH_FAST (2 << DRV_STR_SHIFT) + +#define PIN_DS_FORCE_DISABLE (0 << FORCE_DS_EN_SHIFT) +#define PIN_DS_FORCE_ENABLE (1 << FORCE_DS_EN_SHIFT) +#define PIN_DS_ISO_OVERRIDE_DISABLE (0 << ISO_OVERRIDE_EN_SHIFT) +#define PIN_DS_ISO_OVERRIDE_ENABLE (1 << ISO_OVERRIDE_EN_SHIFT) +#define PIN_DS_OUT_ENABLE (0 << DS_OUT_DIS_SHIFT) +#define PIN_DS_OUT_DISABLE (1 << DS_OUT_DIS_SHIFT) +#define PIN_DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) +#define PIN_DS_OUT_VALUE_ONE (1 << DS_OUT_VAL_SHIFT) +#define PIN_DS_PULLUD_ENABLE (0 << DS_PULLUD_EN_SHIFT) +#define PIN_DS_PULLUD_DISABLE (1 << DS_PULLUD_EN_SHIFT) +#define PIN_DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT) +#define PIN_DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT) +#define PIN_DS_ISO_BYPASS (1 << ISO_BYPASS_EN_SHIFT) +#define PIN_DS_ISO_BYPASS_DISABLE (0 << ISO_BYPASS_EN_SHIFT) + +#define PIN_DS_OUTPUT_LOW (DS_INPUT_DISABLE | DS_OUT_VALUE_ZERO) +#define PIN_DS_OUTPUT_HIGH (DS_INPUT_DISABLE | DS_OUT_VALUE_ONE) +#define PIN_DS_INPUT (DS_INPUT_EN | DS_PULL_DISABLE) +#define PIN_DS_INPUT_PULLUP (DS_INPUT_EN | DS_PULL_UP) +#define PIN_DS_INPUT_PULLDOWN (DS_INPUT_EN | DS_PULL_DOWN) + +#define PIN_WKUP_EN_LEVEL_LOW (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_LOW) +#define PIN_WKUP_EN_LEVEL_HIGH (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_HIGH) +#define PIN_WKUP_EN (WKUP_ENABLE | WKUP_ON_EDGE) + /* Default mux configuration for gpio-ranges to use with pinctrl */ #define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7) #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62DX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62DX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62LX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-timesync-router.h v_kernel/arch/arm64/boot/dts/ti/k3-timesync-router.h --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-timesync-router.h 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-timesync-router.h 2026-04-21 11:35:28.566915330 +0200 @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * This header provides headers for Timesync Router + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef DTS_ARM64_TI_K3_TIMESYNC_ROUTER +#define DTS_ARM64_TI_K3_TIMESYNC_ROUTER + +/* + * The value of the input to be mapped to an output has to be written in + * the register corresponding to the output. + * INT_ENABLE which is BIT(16) i.e. 0x10000 has to be set in addition to + * writing the value of the input in order to begin generating the output + * signal. + */ +#define K3_TS_OFFSET(output_index, mask, input_index) (((0x4 + ((output_index) * 4)))) ((mask)) ((0x10000 | (input_index))) + +#endif /* DTS_ARM64_TI_K3_TIMESYNC_ROUTER */ diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-0.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-0.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-0.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-0.dtso 2026-04-21 11:35:28.566915330 +0200 @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX219 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_00: imx219-xclk-00 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 0 */ + port@0 { + reg = <0>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@0 { + reg = <0>; + i2c-alias = <0x44>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed_00>; + clock-names = "xclk"; + reset-gpios = <&serializer 1 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-1.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-1.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-1.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-1.dtso 2026-04-21 11:35:28.566915330 +0200 @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX219 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_01: imx219-xclk-01 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 1 */ + port@1 { + reg = <1>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@1 { + reg = <1>; + i2c-alias = <0x45>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed_01>; + clock-names = "xclk"; + reset-gpios = <&serializer 1 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-2.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-2.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-2.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-2.dtso 2026-04-21 11:35:28.566915330 +0200 @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX219 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_02: imx219-xclk-02 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 2 */ + port@2 { + reg = <2>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@2 { + reg = <2>; + i2c-alias = <0x46>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed_02>; + clock-names = "xclk"; + reset-gpios = <&serializer 1 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-3.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-3.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-3.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-3.dtso 2026-04-21 11:35:28.566915330 +0200 @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX219 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_03: imx219-xclk-03 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 3 */ + port@3 { + reg = <3>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@3 { + reg = <3>; + i2c-alias = <0x47>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed_03>; + clock-names = "xclk"; + reset-gpios = <&serializer 1 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-0.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-0.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-0.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-0.dtso 2026-04-21 11:35:28.567915333 +0200 @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX219 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_10: imx219-xclk-10 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&deserializer_1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 0 */ + port@0 { + reg = <0>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_1_links { + #address-cells = <1>; + #size-cells = <0>; + + link@0 { + reg = <0>; + i2c-alias = <0x54>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed_10>; + clock-names = "xclk"; + reset-gpios = <&serializer 1 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-1.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-1.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-1.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-1.dtso 2026-04-21 11:35:28.567915333 +0200 @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX219 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_11: imx219-xclk-11 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&deserializer_1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 1 */ + port@1 { + reg = <1>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_1_links { + #address-cells = <1>; + #size-cells = <0>; + + link@1 { + reg = <1>; + i2c-alias = <0x55>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed_11>; + clock-names = "xclk"; + reset-gpios = <&serializer 1 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-2.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-2.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-2.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-2.dtso 2026-04-21 11:35:28.567915333 +0200 @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX219 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_12: imx219-xclk-12 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&deserializer_1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 2 */ + port@2 { + reg = <2>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_1_links { + #address-cells = <1>; + #size-cells = <0>; + + link@2 { + reg = <2>; + i2c-alias = <0x56>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed_12>; + clock-names = "xclk"; + reset-gpios = <&serializer 1 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-3.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-3.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-3.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-imx219-1-3.dtso 2026-04-21 11:35:28.567915333 +0200 @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX219 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_13: imx219-xclk-13 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&deserializer_1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 3 */ + port@3 { + reg = <3>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_1_links { + #address-cells = <1>; + #size-cells = <0>; + + link@3 { + reg = <3>; + i2c-alias = <0x57>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed_13>; + clock-names = "xclk"; + reset-gpios = <&serializer 1 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-0.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-0.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-0.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-0.dtso 2026-04-21 11:35:28.567915333 +0200 @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OV5640 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2025 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_00: imx219-xclk-00 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; +}; + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 0 */ + port@0 { + reg = <0>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@0 { + reg = <0>; + i2c-alias = <0x44>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + p0-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MIPI_CSI_INPUT_GPIO0"; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_imx219_fixed_00>; + clock-names = "xclk"; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-1.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-1.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-1.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-1.dtso 2026-04-21 11:35:28.567915333 +0200 @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OV5640 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2025 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_01: imx219-xclk-01 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; +}; + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 1 */ + port@1 { + reg = <1>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@1 { + reg = <1>; + i2c-alias = <0x45>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + p0-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MIPI_CSI_INPUT_GPIO0"; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_imx219_fixed_01>; + clock-names = "xclk"; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-2.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-2.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-2.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-2.dtso 2026-04-21 11:35:28.567915333 +0200 @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OV5640 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2025 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_02: imx219-xclk-02 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; +}; + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 2 */ + port@2 { + reg = <2>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@2 { + reg = <2>; + i2c-alias = <0x46>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + p0-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MIPI_CSI_INPUT_GPIO0"; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_imx219_fixed_02>; + clock-names = "xclk"; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-3.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-3.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-3.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-ov5640-0-3.dtso 2026-04-21 11:35:28.567915333 +0200 @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OV5640 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2025 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_03: imx219-xclk-03 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; +}; + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 3 */ + port@3 { + reg = <3>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@3 { + reg = <3>; + i2c-alias = <0x47>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + p0-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MIPI_CSI_INPUT_GPIO0"; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_imx219_fixed_03>; + clock-names = "xclk"; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-0.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-0.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-0.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-0.dtso 2026-04-21 11:35:28.568915336 +0200 @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OV5640 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2025 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_00: imx219-xclk-00 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 0 */ + port@0 { + reg = <0>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@0 { + reg = <0>; + i2c-alias = <0x44>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + p0-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MIPI_CSI_INPUT_GPIO0"; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_imx219_fixed_00>; + clock-names = "xclk"; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-1.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-1.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-1.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-1.dtso 2026-04-21 11:35:28.568915336 +0200 @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OV5640 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2025 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_01: imx219-xclk-01 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 1 */ + port@1 { + reg = <1>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@1 { + reg = <1>; + i2c-alias = <0x45>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + p0-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MIPI_CSI_INPUT_GPIO0"; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_imx219_fixed_01>; + clock-names = "xclk"; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-2.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-2.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-2.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-2.dtso 2026-04-21 11:35:28.568915336 +0200 @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OV5640 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2025 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_02: imx219-xclk-02 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 2 */ + port@2 { + reg = <2>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@2 { + reg = <2>; + i2c-alias = <0x46>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + p0-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MIPI_CSI_INPUT_GPIO0"; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_imx219_fixed_02>; + clock-names = "xclk"; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-3.dtso v_kernel/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-3.dtso --- linux-6.12.57/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-3.dtso 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/k3-v3link-tevi-ov5640-0-3.dtso 2026-04-21 11:35:28.568915336 +0200 @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OV5640 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2025 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_03: imx219-xclk-03 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&deserializer_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 3 */ + port@3 { + reg = <3>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&deserializer_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@3 { + reg = <3>; + i2c-alias = <0x47>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + p0-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MIPI_CSI_INPUT_GPIO0"; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_imx219_fixed_03>; + clock-names = "xclk"; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/boot/dts/ti/Makefile v_kernel/arch/arm64/boot/dts/ti/Makefile --- linux-6.12.57/arch/arm64/boot/dts/ti/Makefile 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/boot/dts/ti/Makefile 2026-04-21 11:35:28.507915176 +0200 @@ -12,47 +12,119 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-tevi-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-lincolntech-lcd185-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-minimal.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-lincolntech-lcd185-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-microtips-mf101hie-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-m2-cc3351.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-rpi-hdr-ehrpwm.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-ivy.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb -dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-1-4-ghz-opp.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62x-phyboard-lyra-gpio-fan.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-e3-max-opp.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-lincolntech-lcd185-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-microtips-mf101hie-panel.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am6254xxl-sk.dtb # Boards with AM62Ax SoC +k3-am62a7-sk-ub954-evm-ov2312-dtbs := k3-am62a7-sk.dtb \ + k3-am62a7-sk-ub954-evm.dtbo \ + k3-fpdlink-ov2312-0-0.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-csi2-ox05b1s.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-m2-cc3351.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-ethernet-dc01.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-rpi-hdr-ehrpwm.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-fusion-2.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-edgeai.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-ub954-evm-ov2312.dtb + +# Boards with AM62Dx SoC +dtb-$(CONFIG_ARCH_K3) += k3-am62d2-evm.dtb + +# Boards with AM62Lx SoCs +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-minimal.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm-lpmdemo.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-badge.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-badge-dsi-rpi-7inch-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-badge-eink-gdey042t81.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm-dsi-rpi-7inch-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm-ecap-capture.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm-eink-gdey042t81.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm-epaper.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm-eqep.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm-lpm-wkup-sources.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm-m2-cc3351.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm-mcan.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm-nand.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm-pwm.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm-tida-010939.dtbo # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-ecap-capture.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-eqep.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-ethfw.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-m2-cc3351.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-dsi-rpi-7inch-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-dss-shared-mode.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-mcan.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-microtips-mf101hie-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-microtips-mf103hie-lcd2.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-microtips-mf070zima-lcd3.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-rpi-hdr-ehrpwm.dtbo # Common overlays for SK-AM62* family of boards dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-tevi-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-imx219.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-v3link-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-dmtimer-pwm.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-ecap-capture.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-eqep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-microtips-mf103hie-lcd2.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-mcan.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-mcspi-loopback.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-pwm.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-lpm-wkup-sources.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-lpm-io-ddr-wkup-sources.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-lpm-standby.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-fastboot-disable-hdmi.dtbo # Boards with AM64x SoC dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac-mii.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-onboard-clkgen-pcie-serdes.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-pcie0-ep.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am642-eqep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-pcie.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-usb3.dtb k3-am642-evm-nand-dtbs := k3-am642-evm.dtb k3-am642-evm-nand.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-nand.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-sk-cpsw3g-pps.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-pcie-usb2.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am642-sk-pwm.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo @@ -82,6 +154,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-sm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am654-evm-oldi-lcd1evm.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtb @@ -92,43 +165,84 @@ # Boards with J7200 SoC k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm-ethfw.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm-pcie1-ep.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm-mcspi-loopback.dtbo # Boards with J721e SoC k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64-dsi-rpi-7inch-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64-microtips-mf070zima-lcd3.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board-infotainment.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-ethfw.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-csi2-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie-ntb.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie1-ep.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-ub954.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-fpdlink-fusion.dtbo # Boards with J721s2 SoC dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-bb-csi2-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board-pcie1-ep.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-v3link-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-v3link-fusion-dual-csitx.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-csi2-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo k3-j721s2-evm-dtbs := k3-j721s2-common-proc-board.dtb k3-j721s2-evm-gesi-exp-board.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-ub954.dtbo # Boards with J722s SoC dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai.dtb dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-dsi-rpi-7inch-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-ethfw.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-fpdlink-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-fpdlink-iv-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-microtips-mf101hie-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-pwm.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-v3link-fusion.dtbo # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-csi2-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-fpdlink-fusion-auxport.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-csi2-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-ethfw.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-fpdlink-iv-fusion.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-pcie0-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-j742s2-evm-pcie-ntb.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-j742s2-evm-usb0-type-a.dtbo + +# Boards with J742S2 SoC +dtb-$(CONFIG_ARCH_K3) += k3-j742s2-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j742s2-evm-ethfw.dtbo # Build time test only, enabled by CONFIG_OF_ALL_DTBS k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \ k3-am625-beagleplay-csi2-ov5640.dtbo k3-am625-beagleplay-csi2-tevi-ov5640-dtbs := k3-am625-beagleplay.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtbo -k3-am625-phyboard-lyra-1-4-ghz-opp.dtbs := k3-am625-phyboard-lyra-rdk.dtb \ - k3-am625-phyboard-lyra-1-4-ghz-opp.dtbo +k3-am625-beagleplay-lincolntech-lcd185-panel-dtbs := k3-am625-beagleplay.dtb \ + k3-am625-beagleplay-lincolntech-lcd185-panel.dtbo k3-am625-phyboard-lyra-disable-eth-phy-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am6xx-phycore-disable-eth-phy.dtbo k3-am625-phyboard-lyra-disable-rtc-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ @@ -145,14 +259,34 @@ k3-am62x-sk-csi2-ov5640.dtbo k3-am625-sk-csi2-tevi-ov5640-dtbs := k3-am625-sk.dtb \ k3-am62x-sk-csi2-tevi-ov5640.dtbo +k3-am625-sk-fastboot-disable-hdmi-dtbs := k3-am625-sk.dtb \ + k3-am62x-sk-fastboot-disable-hdmi.dtbo k3-am625-sk-hdmi-audio-dtbs := k3-am625-sk.dtb k3-am62x-sk-hdmi-audio.dtbo +k3-am625-sk-lincolntech-lcd185-panel-dtbs := k3-am625-sk.dtb \ + k3-am625-sk-lincolntech-lcd185-panel.dtbo +k3-am625-sk-microtips-mf101hie-panel-dtbs := k3-am625-sk.dtb \ + k3-am625-sk-microtips-mf101hie-panel.dtbo +k3-am625-sk-microtips-mf103hie-lcd2-dtbs := k3-am625-sk.dtb \ + k3-am62x-sk-microtips-mf103hie-lcd2.dtbo +k3-am62-lp-sk-fastboot-disable-hdmi-dtbs := k3-am62-lp-sk.dtb \ + k3-am62x-sk-fastboot-disable-hdmi.dtbo k3-am62-lp-sk-hdmi-audio-dtbs := k3-am62-lp-sk.dtb k3-am62x-sk-hdmi-audio.dtbo +k3-am62-lp-sk-lincolntech-lcd185-panel-dtbs := k3-am62-lp-sk.dtb \ + k3-am62-lp-sk-lincolntech-lcd185-panel.dtbo +k3-am62-lp-sk-microtips-mf101hie-panel-dtbs := k3-am62-lp-sk.dtb \ + k3-am62-lp-sk-microtips-mf101hie-panel.dtbo +k3-am62-lp-sk-microtips-mf103hie-lcd2-dtbs := k3-am62-lp-sk.dtb \ + k3-am62x-sk-microtips-mf103hie-lcd2.dtbo k3-am62a7-sk-csi2-imx219-dtbs := k3-am62a7-sk.dtb \ k3-am62x-sk-csi2-imx219.dtbo k3-am62a7-sk-csi2-ov5640-dtbs := k3-am62a7-sk.dtb \ k3-am62x-sk-csi2-ov5640.dtbo k3-am62a7-sk-csi2-tevi-ov5640-dtbs := k3-am62a7-sk.dtb \ k3-am62x-sk-csi2-tevi-ov5640.dtbo +k3-am62a7-sk-ethernet-dc01-dtbs := k3-am62a7-sk.dtb \ + k3-am62a7-sk-ethernet-dc01.dtbo +k3-am62a7-sk-fastboot-disable-hdmi-dtbs := k3-am62a7-sk.dtb \ + k3-am62x-sk-fastboot-disable-hdmi.dtbo k3-am62a7-sk-hdmi-audio-dtbs := k3-am62a7-sk.dtb k3-am62x-sk-hdmi-audio.dtbo k3-am62p5-sk-csi2-imx219-dtbs := k3-am62p5-sk.dtb \ k3-am62x-sk-csi2-imx219.dtbo @@ -160,10 +294,28 @@ k3-am62x-sk-csi2-ov5640.dtbo k3-am62p5-sk-csi2-tevi-ov5640-dtbs := k3-am62p5-sk.dtb \ k3-am62x-sk-csi2-tevi-ov5640.dtbo +k3-am62p5-sk-ethfw-dtbs := k3-am62p5-sk.dtb \ + k3-am62p5-sk-ethfw.dtbo +k3-am62p5-sk-dsi-rpi-7inch-panel-dtbs := k3-am62p5-sk.dtb \ + k3-am62p5-sk-dsi-rpi-7inch-panel.dtbo +k3-am62p5-sk-dss-shared-mode-dtbs := k3-am62p5-sk.dtb \ + k3-am62p5-sk-dss-shared-mode.dtbo +k3-am62p5-sk-fastboot-disable-hdmi-dtbs := k3-am62p5-sk.dtb \ + k3-am62x-sk-fastboot-disable-hdmi.dtbo +k3-am62p5-sk-microtips-mf101hie-panel-dtbs := k3-am62p5-sk.dtb \ + k3-am62p5-sk-microtips-mf101hie-panel.dtbo +k3-am62p5-sk-microtips-mf103hie-lcd2-dtbs := k3-am62p5-sk.dtb \ + k3-am62p5-sk-microtips-mf103hie-lcd2.dtbo +k3-am62p5-sk-microtips-mf070zima-lcd3-dtbs := k3-am62p5-sk.dtb \ + k3-am62p5-sk-microtips-mf070zima-lcd3.dtbo k3-am642-evm-icssg1-dualemac-dtbs := \ k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo k3-am642-evm-icssg1-dualemac-mii-dtbs := \ k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac-mii.dtbo +k3-am642-evm-onboard-clkgen-pcie-serdes-dtbs := \ + k3-am642-evm.dtb k3-am642-evm-onboard-clkgen-pcie-serdes.dtbo +k3-am642-evm-pcie0-ep-dtbs := \ + k3-am642-evm.dtb k3-am642-evm-pcie0-ep.dtbo k3-am642-phyboard-electra-disable-eth-phy-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-disable-eth-phy.dtbo k3-am642-phyboard-electra-disable-rtc-dtbs := \ @@ -176,70 +328,223 @@ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-gpio-fan.dtbo k3-am642-phyboard-electra-pcie-usb2-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-pcie-usb2.dtbo +k3-am642-evm-cpsw3g-pps-dtbs := \ + k3-am642-evm.dtb k3-am642-evm-sk-cpsw3g-pps.dtbo +k3-am642-sk-cpsw3g-pps-dtbs := \ + k3-am642-sk.dtb k3-am642-evm-sk-cpsw3g-pps.dtbo k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo +k3-am68-sk-base-board-pcie1-ep-dtbs := k3-am68-sk-base-board.dtb \ + k3-am68-sk-base-board-pcie1-ep.dtbo +k3-am68-sk-base-board-v3link-fusion-dual-csitx-dtbs := k3-am68-sk-base-board.dtb \ + k3-am68-sk-v3link-fusion-dual-csitx.dtbo k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo +k3-am69-sk-pcie0-ep-dtbs := k3-am69-sk.dtb \ + k3-am69-sk-pcie0-ep.dtbo +k3-am69-sk-v3link-fusion-dual-csitx-dtbs := k3-am69-sk.dtb \ + k3-am68-sk-v3link-fusion-dual-csitx.dtbo +k3-j7200-evm-ethfw-dtbs := k3-j7200-common-proc-board.dtb \ + k3-j7200-evm-ethfw.dtbo +k3-j7200-evm-mcspi-loopback-dtbs := k3-j7200-common-proc-board.dtb \ + k3-j7200-evm-mcspi-loopback.dtbo +k3-j7200-evm-pcie1-ep-dtbs := k3-j7200-common-proc-board.dtb \ + k3-j7200-evm-pcie1-ep.dtbo +k3-j721e-beagleboneai64-dsi-rpi-7inch-panel-dtbs := k3-j721e-beagleboneai64.dtb \ + k3-j721e-beagleboneai64-dsi-rpi-7inch-panel.dtbo +k3-j721e-beagleboneai64-microtips-mf070zima-lcd3-dtbs := k3-j721e-beagleboneai64.dtb \ + k3-j721e-beagleboneai64-microtips-mf070zima-lcd3.dtbo k3-j721e-common-proc-board-infotainment-dtbs := k3-j721e-common-proc-board.dtb \ k3-j721e-common-proc-board-infotainment.dtbo +k3-j721e-evm-ethfw-dtbs := k3-j721e-common-proc-board.dtb \ + k3-j721e-evm-ethfw.dtbo +k3-j721e-evm-mcspi-loopback-dtbs := k3-j721e-common-proc-board.dtb \ + k3-j7200-evm-mcspi-loopback.dtbo +k3-j721e-evm-pcie-ntb-dtbs := k3-j721e-common-proc-board.dtb \ + k3-j721e-evm-pcie-ntb.dtbo k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo +k3-j721e-evm-pcie1-ep-dtbs := k3-j721e-common-proc-board.dtb \ + k3-j721e-evm-pcie1-ep.dtbo k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo +k3-j721s2-evm-mcspi-loopback-dtbs := k3-j721s2-common-proc-board.dtb \ + k3-j7200-evm-mcspi-loopback.dtbo +k3-j722s-evm-fpdlink-fusion-dtbs := k3-j722s-evm.dtb \ + k3-j722s-evm-fpdlink-fusion.dtbo +k3-j722s-evm-fpdlink-iv-fusion-dtbs := k3-j722s-evm.dtb \ + k3-j722s-evm-fpdlink-iv-fusion.dtbo +k3-j722s-evm-csi2-quad-rpi-cam-imx219-dtbs := k3-j722s-evm.dtb \ + k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo +k3-j722s-evm-csi2-quad-tevi-ov5640-dtbs := k3-j722s-evm.dtb \ + k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo +k3-j722s-evm-dsi-rpi-7inch-panel-dtbs := k3-j722s-evm.dtb \ + k3-j722s-evm-dsi-rpi-7inch-panel.dtbo +k3-j722s-evm-ethfw-dtbs := k3-j722s-evm.dtb \ + k3-j722s-evm-ethfw.dtbo +k3-j722s-evm-microtips-mf101hie-panel-dtbs := k3-j722s-evm.dtb \ + k3-j722s-evm-microtips-mf101hie-panel.dtbo +k3-j722s-evm-v3link-fusion-dtbs := k3-j722s-evm.dtb \ + k3-j722s-evm-v3link-fusion.dtbo +k3-j742s2-evm-ethfw-dtbs := k3-j742s2-evm.dtb \ + k3-j742s2-evm-ethfw.dtbo +k3-j742s2-evm-mcspi-loopback-dtbs := k3-j742s2-evm.dtb \ + k3-j7200-evm-mcspi-loopback.dtbo +k3-j784s4-evm-mcspi-loopback-dtbs := k3-j784s4-evm.dtb \ + k3-j7200-evm-mcspi-loopback.dtbo +k3-j742s2-evm-pcie-ntb-dtbs := k3-j742s2-evm.dtb \ + k3-j784s4-j742s2-evm-pcie-ntb.dtbo +k3-j742s2-evm-usb0-type-a-dtbs := k3-j742s2-evm.dtb \ + k3-j784s4-j742s2-evm-usb0-type-a.dtbo +k3-j784s4-evm-ethfw-dtbs := k3-j784s4-evm.dtb \ + k3-j784s4-evm-ethfw.dtbo +k3-j784s4-evm-fpdlink-iv-fusion-dtbs := k3-j784s4-evm.dtb \ + k3-j784s4-evm-fpdlink-iv-fusion.dtbo +k3-j784s4-evm-pcie-ntb-dtbs := k3-j784s4-evm.dtb \ + k3-j784s4-j742s2-evm-pcie-ntb.dtbo k3-j784s4-evm-pcie0-pcie1-ep-dtbs := k3-j784s4-evm.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtbo k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtbo +k3-j784s4-evm-usb0-type-a-dtbs := k3-j784s4-evm.dtb \ + k3-j784s4-j742s2-evm-usb0-type-a.dtbo k3-j784s4-evm-usxgmii-exp1-exp2-dtbs := k3-j784s4-evm.dtb \ k3-j784s4-evm-usxgmii-exp1-exp2.dtbo +k3-am62l3-badge-dsi-rpi-7inch-panel-dtbs := k3-am62l3-badge.dtb \ + k3-am62l3-badge-dsi-rpi-7inch-panel.dtbo +k3-am62l3-badge-eink-gdey042t81-dtbs := k3-am62l3-badge.dtb \ + k3-am62l3-badge-eink-gdey042t81.dtbo +k3-am62l3-evm-dsi-rpi-7inch-panel-dtbs := k3-am62l3-evm.dtb \ + k3-am62l3-evm-dsi-rpi-7inch-panel.dtbo +k3-am62l3-evm-eink-gdey042t81-dtbs := k3-am62l3-evm.dtb \ + k3-am62l3-evm-eink-gdey042t81.dtbo +k3-am62l3-evm-nand-dtbs := k3-am62l3-evm.dtb \ + k3-am62l3-evm-nand.dtbo + dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ + k3-am625-beagleplay-lincolntech-lcd185-panel.dtb \ k3-am625-sk-csi2-imx219.dtb \ k3-am625-sk-csi2-ov5640.dtb \ k3-am625-sk-csi2-tevi-ov5640.dtb \ + k3-am625-sk-fastboot-disable-hdmi.dtb \ k3-am625-sk-hdmi-audio.dtb \ + k3-am625-sk-lincolntech-lcd185-panel.dtb \ + k3-am625-sk-microtips-mf101hie-panel.dtb \ + k3-am625-sk-microtips-mf103hie-lcd2.dtb \ + k3-am62-lp-sk-fastboot-disable-hdmi.dtb \ k3-am62-lp-sk-hdmi-audio.dtb \ + k3-am62-lp-sk-lincolntech-lcd185-panel.dtb \ + k3-am62-lp-sk-microtips-mf101hie-panel.dtb \ + k3-am62-lp-sk-microtips-mf103hie-lcd2.dtb \ k3-am62a7-sk-csi2-imx219.dtb \ k3-am62a7-sk-csi2-ov5640.dtb \ + k3-am62a7-sk-fastboot-disable-hdmi.dtb \ k3-am62a7-sk-hdmi-audio.dtb \ k3-am62p5-sk-csi2-imx219.dtb \ k3-am62p5-sk-csi2-ov5640.dtb \ k3-am62p5-sk-csi2-tevi-ov5640.dtb \ + k3-am62p5-sk-ethfw.dtb \ + k3-am62p5-sk-dsi-rpi-7inch-panel.dtb \ + k3-am62p5-sk-dss-shared-mode.dtb \ + k3-am62p5-sk-fastboot-disable-hdmi.dtb \ + k3-am62p5-sk-microtips-mf101hie-panel.dtb \ + k3-am62p5-sk-microtips-mf103hie-lcd2.dtb \ + k3-am62p5-sk-microtips-mf070zima-lcd3.dtb \ k3-am642-evm-icssg1-dualemac.dtb \ k3-am642-evm-icssg1-dualemac-mii.dtb \ + k3-am642-evm-onboard-clkgen-pcie-serdes.dtb \ + k3-am642-evm-pcie0-ep.dtb \ + k3-am642-evm-cpsw3g-pps.dtb \ + k3-am642-sk-cpsw3g-pps.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ + k3-am68-sk-base-board-pcie1-ep.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ + k3-am69-sk-pcie0-ep.dtb \ + k3-j7200-evm-ethfw.dtb \ + k3-j7200-evm-mcspi-loopback.dtb \ + k3-j7200-evm-pcie1-ep.dtb \ + k3-j721e-beagleboneai64-dsi-rpi-7inch-panel.dtb \ + k3-j721e-beagleboneai64-microtips-mf070zima-lcd3.dtb \ k3-j721e-common-proc-board-infotainment.dtb \ + k3-j721e-evm-ethfw.dtb \ + k3-j721e-evm-mcspi-loopback.dtb \ + k3-j721e-evm-pcie-ntb.dtb \ k3-j721e-evm-pcie0-ep.dtb \ + k3-j721e-evm-pcie1-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ + k3-j721s2-evm-mcspi-loopback.dtb \ + k3-j722s-evm-fpdlink-fusion.dtb \ + k3-j722s-evm-fpdlink-iv-fusion.dtb \ + k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \ + k3-j722s-evm-csi2-quad-tevi-ov5640.dtb \ + k3-j722s-evm-dsi-rpi-7inch-panel.dtb \ + k3-j722s-evm-ethfw.dtb \ + k3-j722s-evm-microtips-mf101hie-panel.dtb \ + k3-j722s-evm-v3link-fusion.dtb \ + k3-j742s2-evm-ethfw.dtb \ + k3-j742s2-evm-pcie-ntb.dtb \ + k3-j742s2-evm-usb0-type-a.dtb \ + k3-j742s2-evm-mcspi-loopback.dtb \ + k3-j784s4-evm-ethfw.dtb \ + k3-j784s4-evm-fpdlink-iv-fusion.dtb \ + k3-j784s4-evm-pcie-ntb.dtb \ + k3-j784s4-evm-mcspi-loopback.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtb \ - k3-j784s4-evm-usxgmii-exp1-exp2.dtb + k3-j784s4-evm-usb0-type-a.dtb \ + k3-j784s4-evm-usxgmii-exp1-exp2.dtb \ + k3-am62l3-badge-dsi-rpi-7inch-panel.dtb \ + k3-am62l3-badge-eink-gdey042t81.dtb \ + k3-am62l3-evm-dsi-rpi-7inch-panel.dtb \ + k3-am62l3-evm-eink-gdey042t81.dtb \ + k3-am62l3-evm-nand.dtb + +# FPDLink Sensors +dtb-$(CONFIG_ARCH_K3) += k3-fpdlink-imx728-rcm-0-0.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-fpdlink-imx390-cm-0-0.dtbo \ + k3-fpdlink-imx390-cm-0-1.dtbo \ + k3-fpdlink-imx390-rcm-0-0.dtbo \ + k3-fpdlink-imx390-rcm-0-1.dtbo \ + k3-fpdlink-imx390-rcm-0-2.dtbo \ + k3-fpdlink-imx390-rcm-0-3.dtbo \ + k3-fpdlink-imx390-rcm-1-0.dtbo \ + k3-fpdlink-imx390-rcm-1-1.dtbo \ + k3-fpdlink-imx390-rcm-1-2.dtbo \ + k3-fpdlink-imx390-rcm-1-3.dtbo \ + k3-fpdlink-imx390-rcm-2-0.dtbo \ + k3-fpdlink-imx390-rcm-2-1.dtbo \ + k3-fpdlink-imx390-rcm-2-2.dtbo \ + k3-fpdlink-imx390-rcm-2-3.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-fpdlink-ov2312-0-0.dtbo \ + k3-fpdlink-ov2312-0-1.dtbo \ + k3-fpdlink-ov2312-0-2.dtbo \ + k3-fpdlink-ov2312-0-3.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-v3link-imx219-0-0.dtbo \ + k3-v3link-imx219-0-1.dtbo \ + k3-v3link-imx219-0-2.dtbo \ + k3-v3link-imx219-0-3.dtbo \ + k3-v3link-imx219-1-0.dtbo \ + k3-v3link-imx219-1-1.dtbo \ + k3-v3link-imx219-1-2.dtbo \ + k3-v3link-imx219-1-3.dtbo \ + k3-v3link-ov5640-0-0.dtbo \ + k3-v3link-ov5640-0-1.dtbo \ + k3-v3link-ov5640-0-2.dtbo \ + k3-v3link-ov5640-0-3.dtbo \ + k3-v3link-tevi-ov5640-0-0.dtbo \ + k3-v3link-tevi-ov5640-0-1.dtbo \ + k3-v3link-tevi-ov5640-0-2.dtbo \ + k3-v3link-tevi-ov5640-0-3.dtbo # Enable support for device-tree overlays -DTC_FLAGS_k3-am625-beagleplay += -@ -DTC_FLAGS_k3-am625-phyboard-lyra-rdk += -@ -DTC_FLAGS_k3-am62a7-phyboard-lyra-rdk += -@ -DTC_FLAGS_k3-am625-sk += -@ -DTC_FLAGS_k3-am62-lp-sk += -@ -DTC_FLAGS_k3-am62a7-sk += -@ -DTC_FLAGS_k3-am62p5-sk += -@ -DTC_FLAGS_k3-am642-evm += -@ -DTC_FLAGS_k3-am642-phyboard-electra-rdk += -@ -DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl += -@ -DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ -DTC_FLAGS_k3-am68-sk-base-board += -@ -DTC_FLAGS_k3-am69-sk += -@ -DTC_FLAGS_k3-j721e-common-proc-board += -@ -DTC_FLAGS_k3-j721e-sk += -@ -DTC_FLAGS_k3-j721s2-common-proc-board += -@ -DTC_FLAGS_k3-j784s4-evm += -@ +DTC_FLAGS := -@ diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/arch/arm64/configs/defconfig v_kernel/arch/arm64/configs/defconfig --- linux-6.12.57/arch/arm64/configs/defconfig 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/arch/arm64/configs/defconfig 2026-04-21 11:35:28.576915356 +0200 @@ -1,6 +1,5 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y -CONFIG_AUDIT=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y CONFIG_BPF_SYSCALL=y @@ -17,6 +16,7 @@ CONFIG_NUMA_BALANCING=y CONFIG_MEMCG=y CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y CONFIG_CGROUP_PIDS=y CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_HUGETLB=y @@ -32,7 +32,6 @@ CONFIG_PROFILING=y CONFIG_KEXEC=y CONFIG_KEXEC_FILE=y -CONFIG_CRASH_DUMP=y CONFIG_ARCH_ACTIONS=y CONFIG_ARCH_AIROHA=y CONFIG_ARCH_SUNXI=y @@ -89,12 +88,12 @@ CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=m CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m CONFIG_CPUFREQ_DT=y -CONFIG_ACPI_CPPC_CPUFREQ=m CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m CONFIG_ARM_ARMADA_37XX_CPUFREQ=y CONFIG_ARM_SCPI_CPUFREQ=y @@ -106,6 +105,7 @@ CONFIG_ARM_SCMI_CPUFREQ=y CONFIG_ARM_TEGRA186_CPUFREQ=y CONFIG_QORIQ_CPUFREQ=y +CONFIG_ACPI_CPPC_CPUFREQ=m CONFIG_ACPI=y CONFIG_ACPI_HOTPLUG_MEMORY=y CONFIG_ACPI_HMAT=y @@ -119,7 +119,7 @@ CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_IOSCHED_BFQ=y +CONFIG_BLK_DEV_THROTTLING=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_COMPAT_BRK is not set CONFIG_MEMORY_HOTPLUG=y @@ -129,29 +129,38 @@ CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_NET=y CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y +CONFIG_XFRM_USER=y +CONFIG_XDP_SOCKETS=y CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y +CONFIG_INET_ESP=y CONFIG_IPV6=m CONFIG_NETFILTER=y CONFIG_BRIDGE_NETFILTER=m CONFIG_NF_CONNTRACK=m CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NETFILTER_XT_MARK=m CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_IPVS=m CONFIG_IP_VS=m +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_NFCT=y CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_MANGLE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_FILTER=m @@ -172,13 +181,34 @@ CONFIG_NET_SCH_MQPRIO=m CONFIG_NET_SCH_INGRESS=m CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m CONFIG_NET_ACT_GATE=m +CONFIG_HSR=m CONFIG_QRTR_SMD=m CONFIG_QRTR_TUN=m +CONFIG_CGROUP_NET_PRIO=y CONFIG_CAN=m CONFIG_BT=m CONFIG_BT_HIDP=m @@ -192,13 +222,13 @@ CONFIG_BT_HCIUART_BCM=y CONFIG_BT_HCIUART_QCA=y CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_TI_UART=m CONFIG_BT_MRVL=m CONFIG_BT_MRVL_SDIO=m CONFIG_BT_QCOMSMD=m CONFIG_BT_NXPUART=m CONFIG_CFG80211=m CONFIG_MAC80211=m -CONFIG_MAC80211_LEDS=y CONFIG_RFKILL=m CONFIG_NET_9P=y CONFIG_NET_9P_VIRTIO=y @@ -225,6 +255,8 @@ CONFIG_PCIE_RCAR_EP=y CONFIG_PCIE_ROCKCHIP_HOST=m CONFIG_PCI_XGENE=y +CONFIG_PCI_J721E_HOST=y +CONFIG_PCI_J721E_EP=y CONFIG_PCI_IMX6_HOST=y CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_HISI=y @@ -237,18 +269,22 @@ CONFIG_PCIE_RCAR_GEN4_HOST=m CONFIG_PCIE_RCAR_GEN4_EP=m CONFIG_PCIE_ROCKCHIP_DW_HOST=y +CONFIG_PCI_KEYSTONE_HOST=y +CONFIG_PCI_KEYSTONE_EP=y CONFIG_PCIE_VISCONTI_HOST=y CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_PCI_ENDPOINT=y CONFIG_PCI_ENDPOINT_CONFIGFS=y CONFIG_PCI_EPF_TEST=m +CONFIG_PCI_EPF_NTB=m CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_FW_LOADER_USER_HELPER=y CONFIG_HISILICON_LPC=y CONFIG_TEGRA_ACONNECT=m CONFIG_MHI_BUS_PCI_GENERIC=m -CONFIG_ARM_SCMI_PROTOCOL=y +CONFIG_ARM_SCMI_RAW_MODE_SUPPORT=y +CONFIG_ARM_SCMI_RAW_MODE_SUPPORT_COEX=y CONFIG_ARM_SCPI_PROTOCOL=y CONFIG_RASPBERRYPI_FIRMWARE=y CONFIG_INTEL_STRATIX10_SERVICE=y @@ -277,12 +313,15 @@ CONFIG_MTD_SST25L=y CONFIG_MTD_RAW_NAND=y CONFIG_MTD_NAND_DENALI_DT=y +CONFIG_MTD_NAND_OMAP2=y +CONFIG_MTD_NAND_OMAP_BCH=y CONFIG_MTD_NAND_MARVELL=y CONFIG_MTD_NAND_BRCMNAND=m -CONFIG_MTD_NAND_FSL_IFC=y CONFIG_MTD_NAND_QCOM=y +CONFIG_MTD_SPI_NAND=y CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_UBI=m +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_MTD_UBI=y CONFIG_MTD_HYPERBUS=m CONFIG_HBMC_AM654=m CONFIG_BLK_DEV_LOOP=y @@ -292,6 +331,7 @@ CONFIG_QCOM_COINCELL=m CONFIG_QCOM_FASTRPC=m CONFIG_SRAM=y +CONFIG_SRAM_DMA_HEAP=y CONFIG_PCI_ENDPOINT_TEST=m CONFIG_EEPROM_AT24=m CONFIG_EEPROM_AT25=m @@ -314,7 +354,6 @@ CONFIG_AHCI_QORIQ=y CONFIG_SATA_SIL24=y CONFIG_SATA_RCAR=y -CONFIG_PATA_PLATFORM=y CONFIG_PATA_OF_PLATFORM=y CONFIG_MD=y CONFIG_BLK_DEV_MD=m @@ -322,8 +361,12 @@ CONFIG_DM_MIRROR=m CONFIG_DM_ZERO=m CONFIG_NETDEVICES=y +CONFIG_DUMMY=m CONFIG_MACVLAN=m CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_VXLAN=m +CONFIG_NTB_NETDEV=m CONFIG_TUN=y CONFIG_VETH=m CONFIG_VIRTIO_NET=y @@ -374,7 +417,11 @@ CONFIG_SNI_NETSEC=y CONFIG_STMMAC_ETH=m CONFIG_DWMAC_TEGRA=m +CONFIG_TI_CPSW_PROXY_CLIENT=m CONFIG_TI_K3_AM65_CPSW_NUSS=y +CONFIG_TI_K3_AM65_CPSW_SWITCHDEV=y +CONFIG_TI_K3_AM65_CPTS=y +CONFIG_TI_AM65_CPSW_QOS=y CONFIG_TI_ICSSG_PRUETH=m CONFIG_QCOM_IPA=m CONFIG_MESON_GXL_PHY=m @@ -431,6 +478,8 @@ CONFIG_MT7921E=m CONFIG_RSI_91X=m CONFIG_WL18XX=m +CONFIG_CC33XX=m +CONFIG_CC33XX_SDIO=m CONFIG_WLCORE_SDIO=m CONFIG_WWAN=m CONFIG_MHI_WWAN_CTRL=m @@ -448,6 +497,7 @@ CONFIG_TOUCHSCREEN_ATMEL_MXT=m CONFIG_TOUCHSCREEN_GOODIX=m CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI=m +CONFIG_TOUCHSCREEN_ILI210X=m CONFIG_TOUCHSCREEN_ELAN=m CONFIG_TOUCHSCREEN_EDT_FT5X06=m CONFIG_INPUT_MISC=y @@ -465,7 +515,8 @@ CONFIG_LEGACY_PTY_COUNT=16 CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=8 +CONFIG_SERIAL_8250_NR_UARTS=12 +CONFIG_SERIAL_8250_RUNTIME_UARTS=12 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_BCM2835AUX=y @@ -474,6 +525,7 @@ CONFIG_SERIAL_8250_OMAP=y CONFIG_SERIAL_8250_MT6577=y CONFIG_SERIAL_8250_UNIPHIER=y +CONFIG_SERIAL_8250_PRUSS=m CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y @@ -519,7 +571,6 @@ CONFIG_I2C_BCM2835=m CONFIG_I2C_CADENCE=m CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_GPIO=m CONFIG_I2C_IMX=y CONFIG_I2C_IMX_LPI2C=y @@ -579,6 +630,7 @@ CONFIG_SPMI_MTK_PMIF=m CONFIG_PINCTRL_DA9062=m CONFIG_PINCTRL_MAX77620=y +CONFIG_PINCTRL_MCP23S08=m CONFIG_PINCTRL_RK805=m CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_OWL=y @@ -650,14 +702,15 @@ CONFIG_GPIO_RCAR=y CONFIG_GPIO_SYSCON=y CONFIG_GPIO_UNIPHIER=y +CONFIG_GPIO_VF610=y CONFIG_GPIO_VISCONTI=y CONFIG_GPIO_WCD934X=m -CONFIG_GPIO_VF610=y CONFIG_GPIO_XGENE=y CONFIG_GPIO_XGENE_SB=y CONFIG_GPIO_MAX732X=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCF857X=m CONFIG_GPIO_ADP5585=m CONFIG_GPIO_BD9571MWV=m CONFIG_GPIO_MAX77620=y @@ -687,6 +740,7 @@ CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_RASPBERRYPI_HWMON=m CONFIG_SENSORS_SL28CPLD=m +CONFIG_SENSORS_SHT4x=m CONFIG_SENSORS_INA2XX=m CONFIG_SENSORS_INA3221=m CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y @@ -699,9 +753,6 @@ CONFIG_QORIQ_THERMAL=m CONFIG_SUN8I_THERMAL=y CONFIG_ROCKCHIP_THERMAL=m -CONFIG_RCAR_THERMAL=y -CONFIG_RCAR_GEN3_THERMAL=y -CONFIG_RZG2L_THERMAL=y CONFIG_ARMADA_THERMAL=y CONFIG_MTK_THERMAL=m CONFIG_MTK_LVTS_THERMAL=m @@ -709,6 +760,9 @@ CONFIG_BCM2835_THERMAL=m CONFIG_BRCMSTB_THERMAL=m CONFIG_EXYNOS_THERMAL=y +CONFIG_RCAR_THERMAL=y +CONFIG_RCAR_GEN3_THERMAL=y +CONFIG_RZG2L_THERMAL=y CONFIG_TEGRA_SOCTHERM=m CONFIG_TEGRA_BPMP_THERMAL=m CONFIG_GENERIC_ADC_THERMAL=m @@ -761,7 +815,7 @@ CONFIG_MFD_TI_AM335X_TSCADC=m CONFIG_MFD_TI_LP873X=m CONFIG_MFD_TPS65219=y -CONFIG_MFD_TPS6594_I2C=m +CONFIG_MFD_TPS6594_I2C=y CONFIG_MFD_ROHM_BD718XX=y CONFIG_MFD_WCD934X=m CONFIG_MFD_KHADAS_MCU=m @@ -796,6 +850,7 @@ CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_REGULATOR_QCOM_USB_VBUS=m CONFIG_REGULATOR_RAA215300=y +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m CONFIG_REGULATOR_RK808=y CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_TPS65132=m @@ -823,10 +878,10 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_AMPHION_VPU=m CONFIG_VIDEO_CADENCE_CSI2RX=m -CONFIG_VIDEO_MEDIATEK_JPEG=m -CONFIG_VIDEO_MEDIATEK_VCODEC=m CONFIG_VIDEO_WAVE_VPU=m CONFIG_VIDEO_E5010_JPEG_ENC=m +CONFIG_VIDEO_MEDIATEK_JPEG=m +CONFIG_VIDEO_MEDIATEK_VCODEC=m CONFIG_VIDEO_IMX7_CSI=m CONFIG_VIDEO_IMX_MIPI_CSIS=m CONFIG_VIDEO_IMX8_ISI=m @@ -834,8 +889,8 @@ CONFIG_VIDEO_IMX8_JPEG=m CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_VIDEO_QCOM_VENUS=m -CONFIG_VIDEO_RCAR_ISP=m CONFIG_VIDEO_RCAR_CSI2=m +CONFIG_VIDEO_RCAR_ISP=m CONFIG_VIDEO_RCAR_VIN=m CONFIG_VIDEO_RZG2L_CSI2=m CONFIG_VIDEO_RZG2L_CRU=m @@ -850,9 +905,17 @@ CONFIG_VIDEO_TI_J721E_CSI2RX=m CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX390=m CONFIG_VIDEO_IMX412=m +CONFIG_VIDEO_IMX728=m +CONFIG_VIDEO_OV2312=m CONFIG_VIDEO_OV5640=m CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_OX05B1S=m +CONFIG_VIDEO_DS90UB953=m +CONFIG_VIDEO_DS90UB960=m +CONFIG_AUXDISPLAY=y +CONFIG_SEG_LED_GPIO=m CONFIG_DRM=m CONFIG_DRM_I2C_NXP_TDA998X=m CONFIG_DRM_HDLCD=m @@ -876,19 +939,13 @@ CONFIG_ROCKCHIP_LVDS=y CONFIG_DRM_RCAR_DU=m CONFIG_DRM_RCAR_DW_HDMI=m -CONFIG_DRM_RCAR_MIPI_DSI=m -CONFIG_DRM_RZG2L_MIPI_DSI=m CONFIG_DRM_RZG2L_DU=m +CONFIG_DRM_RZG2L_MIPI_DSI=m CONFIG_DRM_SUN4I=m -CONFIG_DRM_SUN6I_DSI=m -CONFIG_DRM_SUN8I_DW_HDMI=m -CONFIG_DRM_SUN8I_MIXER=m CONFIG_DRM_MSM=m CONFIG_DRM_TEGRA=m CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m CONFIG_DRM_PANEL_LVDS=m -CONFIG_DRM_PANEL_SIMPLE=m -CONFIG_DRM_PANEL_EDP=m CONFIG_DRM_PANEL_ILITEK_ILI9882T=m CONFIG_DRM_PANEL_KHADAS_TS050=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m @@ -896,6 +953,8 @@ CONFIG_DRM_PANEL_RAYDIUM_RM67191=m CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m CONFIG_DRM_PANEL_SITRONIX_ST7703=m +CONFIG_DRM_PANEL_EDP=m +CONFIG_DRM_PANEL_SIMPLE=m CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m CONFIG_DRM_FSL_LDB=m @@ -905,10 +964,10 @@ CONFIG_DRM_ITE_IT66121=m CONFIG_DRM_NWL_MIPI_DSI=m CONFIG_DRM_PARADE_PS8640=m -CONFIG_DRM_SAMSUNG_DSIM=m CONFIG_DRM_SII902X=m CONFIG_DRM_SIMPLE_BRIDGE=m CONFIG_DRM_THINE_THC63LVD1024=m +CONFIG_DRM_TOSHIBA_TC358762=m CONFIG_DRM_TOSHIBA_TC358767=m CONFIG_DRM_TOSHIBA_TC358768=m CONFIG_DRM_TI_TFP410=m @@ -917,6 +976,7 @@ CONFIG_DRM_ANALOGIX_ANX7625=m CONFIG_DRM_I2C_ADV7511=m CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_DRM_CDNS_DSI=m CONFIG_DRM_CDNS_MHDP8546=m CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=m CONFIG_DRM_DW_HDMI_AHB_AUDIO=m @@ -933,6 +993,7 @@ CONFIG_DRM_MXSFB=m CONFIG_DRM_IMX_LCDIF=m CONFIG_DRM_MESON=m +CONFIG_TINYDRM_SSD16XX=m CONFIG_DRM_PL111=m CONFIG_DRM_LIMA=m CONFIG_DRM_PANFROST=m @@ -941,6 +1002,7 @@ CONFIG_DRM_POWERVR=m CONFIG_FB=y CONFIG_FB_EFI=y +CONFIG_FB_SIMPLE=y CONFIG_FB_MODE_HELPERS=y CONFIG_BACKLIGHT_PWM=m CONFIG_BACKLIGHT_LP855X=m @@ -952,6 +1014,7 @@ CONFIG_SND_ALOOP=m CONFIG_SND_HDA_TEGRA=m CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=y CONFIG_SND_BCM2835_SOC_I2S=m CONFIG_SND_SOC_FSL_ASRC=m @@ -1012,7 +1075,6 @@ CONFIG_SND_SOC_TEGRA210_ADX=m CONFIG_SND_SOC_TEGRA210_MIXER=m CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m -CONFIG_SND_SOC_DAVINCI_MCASP=m CONFIG_SND_SOC_J721E_EVM=m CONFIG_SND_SOC_AK4613=m CONFIG_SND_SOC_AK4619=m @@ -1023,20 +1085,20 @@ CONFIG_SND_SOC_GTM601=m CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m -CONFIG_SND_SOC_PCM3168A_I2C=m +CONFIG_SND_SOC_PCM6240=m CONFIG_SND_SOC_RK3308=m CONFIG_SND_SOC_RK817=m CONFIG_SND_SOC_RT5640=m CONFIG_SND_SOC_RT5659=m CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m CONFIG_SND_SOC_SIMPLE_MUX=m +CONFIG_SND_SOC_TAC5X1X_I2C=m CONFIG_SND_SOC_TAS2552=m CONFIG_SND_SOC_TAS571X=m CONFIG_SND_SOC_TLV320AIC32X4_I2C=m CONFIG_SND_SOC_TLV320AIC3X_I2C=m CONFIG_SND_SOC_WCD9335=m CONFIG_SND_SOC_WCD934X=m -CONFIG_SND_SOC_WCD939X=m CONFIG_SND_SOC_WCD939X_SDW=m CONFIG_SND_SOC_WM8524=m CONFIG_SND_SOC_WM8904=m @@ -1049,8 +1111,6 @@ CONFIG_SND_SOC_NAU8822=m CONFIG_SND_SOC_LPASS_WSA_MACRO=m CONFIG_SND_SOC_LPASS_VA_MACRO=m -CONFIG_SND_SOC_LPASS_RX_MACRO=m -CONFIG_SND_SOC_LPASS_TX_MACRO=m CONFIG_SND_SIMPLE_CARD=m CONFIG_SND_AUDIO_GRAPH_CARD=m CONFIG_SND_AUDIO_GRAPH_CARD2=m @@ -1079,12 +1139,10 @@ CONFIG_USB_CDNS3=m CONFIG_USB_CDNS3_GADGET=y CONFIG_USB_CDNS3_HOST=y -CONFIG_USB_CDNS3_IMX=m CONFIG_USB_MTU3=y CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_SUNXI=y CONFIG_USB_DWC3=y -CONFIG_OMAP_USB2=m CONFIG_USB_DWC2=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y @@ -1093,6 +1151,7 @@ CONFIG_USB_SERIAL=m CONFIG_USB_SERIAL_CP210X=m CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_PL2303=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_QCOM_EUD=m CONFIG_USB_HSIC_USB3503=y @@ -1115,7 +1174,13 @@ CONFIG_USB_CONFIGFS_EEM=y CONFIG_USB_CONFIGFS_MASS_STORAGE=y CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_MULTI=m CONFIG_TYPEC=m CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_TCPCI=m @@ -1178,6 +1243,7 @@ CONFIG_LEDS_GPIO=y CONFIG_LEDS_PWM=y CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_PWM_MULTICOLOR=m CONFIG_LEDS_QCOM_LPG=m CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_DISK=y @@ -1243,7 +1309,12 @@ CONFIG_RENESAS_USB_DMAC=m CONFIG_RZ_DMAC=y CONFIG_TI_K3_UDMA=y +CONFIG_TI_K3_UDMA_AM62L=y CONFIG_TI_K3_UDMA_GLUE_LAYER=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_DMABUF_HEAPS_CARVEOUT=y CONFIG_VFIO=y CONFIG_VFIO_PCI=y CONFIG_VIRTIO_PCI=y @@ -1264,7 +1335,6 @@ CONFIG_CROS_KBD_LED_BACKLIGHT=m CONFIG_CROS_EC_CHARDEV=m CONFIG_COMMON_CLK_RK808=y -CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_SCPI=y CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_FSL_SAI=y @@ -1283,18 +1353,6 @@ CONFIG_CLK_IMX8ULP=y CONFIG_CLK_IMX93=y CONFIG_TI_SCI_CLK=y -CONFIG_COMMON_CLK_MT8192_AUDSYS=y -CONFIG_COMMON_CLK_MT8192_CAMSYS=y -CONFIG_COMMON_CLK_MT8192_IMGSYS=y -CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP=y -CONFIG_COMMON_CLK_MT8192_IPESYS=y -CONFIG_COMMON_CLK_MT8192_MDPSYS=y -CONFIG_COMMON_CLK_MT8192_MFGCFG=y -CONFIG_COMMON_CLK_MT8192_MMSYS=y -CONFIG_COMMON_CLK_MT8192_MSDC=y -CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y -CONFIG_COMMON_CLK_MT8192_VDECSYS=y -CONFIG_COMMON_CLK_MT8192_VENCSYS=y CONFIG_COMMON_CLK_QCOM=y CONFIG_CLK_X1E80100_CAMCC=m CONFIG_CLK_X1E80100_DISPCC=m @@ -1307,7 +1365,6 @@ CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_APSS_6018=y -CONFIG_IPQ_APSS_5018=y CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_5332=y CONFIG_IPQ_GCC_6018=y @@ -1323,7 +1380,6 @@ CONFIG_QCM_GCC_2290=y CONFIG_QCM_DISPCC_2290=m CONFIG_QCS_GCC_404=y -CONFIG_QDU_GCC_1000=y CONFIG_SC_CAMCC_8280XP=m CONFIG_SC_DISPCC_7280=m CONFIG_SC_DISPCC_8280XP=m @@ -1337,6 +1393,7 @@ CONFIG_SC_GPUCC_8280XP=m CONFIG_SC_LPASSCC_8280XP=m CONFIG_SDM_CAMCC_845=m +CONFIG_QDU_GCC_1000=y CONFIG_SDM_GPUCC_845=y CONFIG_SDM_VIDEOCC_845=y CONFIG_SDM_DISPCC_845=y @@ -1367,13 +1424,14 @@ CONFIG_CLK_GFM_LPASS_SM8250=m CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_OMAP=m CONFIG_HWSPINLOCK_QCOM=y CONFIG_TEGRA186_TIMER=y CONFIG_RENESAS_OSTM=y CONFIG_ARM_MHU=y CONFIG_IMX_MBOX=y -CONFIG_OMAP2PLUS_MBOX=m CONFIG_PLATFORM_MHU=y +CONFIG_OMAP2PLUS_MBOX=m CONFIG_BCM2835_MBOX=y CONFIG_QCOM_APCS_IPC=y CONFIG_MTK_ADSP_MBOX=m @@ -1385,6 +1443,7 @@ CONFIG_MTK_IOMMU=y CONFIG_QCOM_IOMMU=y CONFIG_REMOTEPROC=y +CONFIG_REMOTEPROC_CDEV=y CONFIG_IMX_REMOTEPROC=y CONFIG_MTK_SCP=m CONFIG_QCOM_Q6V5_ADSP=m @@ -1393,6 +1452,7 @@ CONFIG_QCOM_SYSMON=m CONFIG_QCOM_WCNSS_PIL=m CONFIG_TI_K3_DSP_REMOTEPROC=m +CONFIG_TI_K3_M4_REMOTEPROC=m CONFIG_TI_K3_R5_REMOTEPROC=m CONFIG_RPMSG_CHAR=m CONFIG_RPMSG_CTRL=m @@ -1471,6 +1531,7 @@ CONFIG_EXTCON_PTN5150=m CONFIG_EXTCON_USB_GPIO=y CONFIG_EXTCON_USBC_CROS_EC=y +CONFIG_OMAP_GPMC=y CONFIG_RENESAS_RPCIF=m CONFIG_IIO=y CONFIG_EXYNOS_ADC=y @@ -1493,6 +1554,9 @@ CONFIG_IIO_ST_MAGN_3AXIS=m CONFIG_IIO_CROS_EC_BARO=m CONFIG_MPL3115=m +CONFIG_NTB=m +CONFIG_NTB_EPF=m +CONFIG_NTB_TRANSPORT=m CONFIG_PWM=y CONFIG_PWM_ADP5585=m CONFIG_PWM_BCM2835=m @@ -1502,6 +1566,7 @@ CONFIG_PWM_MESON=m CONFIG_PWM_MTK_DISP=m CONFIG_PWM_MEDIATEK=m +CONFIG_PWM_OMAP_DMTIMER=m CONFIG_PWM_RCAR=m CONFIG_PWM_RENESAS_TPU=m CONFIG_PWM_ROCKCHIP=y @@ -1525,9 +1590,10 @@ CONFIG_PHY_XGENE=y CONFIG_PHY_CAN_TRANSCEIVER=m CONFIG_PHY_SUN4I_USB=y -CONFIG_PHY_CADENCE_TORRENT=m +CONFIG_PHY_CADENCE_TORRENT=y +CONFIG_PHY_CADENCE_DPHY=m CONFIG_PHY_CADENCE_DPHY_RX=m -CONFIG_PHY_CADENCE_SIERRA=m +CONFIG_PHY_CADENCE_SIERRA=y CONFIG_PHY_CADENCE_SALVO=m CONFIG_PHY_MIXEL_MIPI_DPHY=m CONFIG_PHY_FSL_IMX8M_PCIE=y @@ -1569,8 +1635,9 @@ CONFIG_PHY_UNIPHIER_USB2=y CONFIG_PHY_UNIPHIER_USB3=y CONFIG_PHY_TEGRA_XUSB=y -CONFIG_PHY_AM654_SERDES=m -CONFIG_PHY_J721E_WIZ=m +CONFIG_PHY_AM654_SERDES=y +CONFIG_PHY_J721E_WIZ=y +CONFIG_OMAP_USB2=m CONFIG_ARM_CCI_PMU=m CONFIG_ARM_CCN=m CONFIG_ARM_CMN=m @@ -1611,11 +1678,8 @@ CONFIG_TEE=y CONFIG_OPTEE=y CONFIG_MUX_GPIO=m -CONFIG_MUX_MMIO=y -CONFIG_SLIMBUS=m CONFIG_SLIM_QCOM_CTRL=m CONFIG_SLIM_QCOM_NGD_CTRL=m -CONFIG_INTERCONNECT=y CONFIG_INTERCONNECT_IMX=y CONFIG_INTERCONNECT_IMX8MM=m CONFIG_INTERCONNECT_IMX8MN=m @@ -1645,6 +1709,8 @@ CONFIG_INTERCONNECT_QCOM_X1E80100=y CONFIG_COUNTER=m CONFIG_RZ_MTU3_CNT=m +CONFIG_TI_ECAP_CAPTURE=m +CONFIG_TI_EQEP=m CONFIG_HTE=y CONFIG_HTE_TEGRA194=y CONFIG_HTE_TEGRA194_TEST=m @@ -1663,9 +1729,8 @@ CONFIG_VFAT_FS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_HUGETLBFS=y -CONFIG_CONFIGFS_FS=y CONFIG_EFIVAR_FS=y -CONFIG_UBIFS_FS=m +CONFIG_UBIFS_FS=y CONFIG_SQUASHFS=y CONFIG_PSTORE_RAM=m CONFIG_NFS_FS=y @@ -1677,20 +1742,19 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_SECURITY=y +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_APPARMOR=y CONFIG_CRYPTO_USER=y CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_RNG=m -CONFIG_CRYPTO_CHACHA20_NEON=m CONFIG_CRYPTO_GHASH_ARM64_CE=y CONFIG_CRYPTO_SHA1_ARM64_CE=y CONFIG_CRYPTO_SHA2_ARM64_CE=y CONFIG_CRYPTO_SHA512_ARM64_CE=m CONFIG_CRYPTO_SHA3_ARM64=m CONFIG_CRYPTO_SM3_ARM64_CE=m -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_BS=m CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m @@ -1706,6 +1770,8 @@ CONFIG_CRYPTO_DEV_HISI_HPRE=m CONFIG_CRYPTO_DEV_HISI_TRNG=m CONFIG_CRYPTO_DEV_SA2UL=m +CONFIG_CRYPTO_DEV_TI_MCRC64=m +CONFIG_CRYPTO_DEV_TI_DTHEV2=m CONFIG_DMA_RESTRICTED_POOL=y CONFIG_CMA_SIZE_MBYTES=32 CONFIG_PRINTK_TIME=y @@ -1715,7 +1781,6 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y # CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set # CONFIG_FTRACE is not set CONFIG_CORESIGHT=m CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/crypto/aead.c v_kernel/crypto/aead.c --- linux-6.12.57/crypto/aead.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/crypto/aead.c 2026-04-21 11:35:32.023924397 +0200 @@ -202,6 +202,25 @@ } EXPORT_SYMBOL_GPL(crypto_alloc_aead); +struct crypto_sync_aead *crypto_alloc_sync_aead(const char *alg_name, u32 type, u32 mask) +{ + struct crypto_aead *tfm; + + /* Only sync algorithms are allowed. */ + mask |= CRYPTO_ALG_ASYNC; + type &= ~(CRYPTO_ALG_ASYNC); + + tfm = crypto_alloc_tfm(alg_name, &crypto_aead_type, type, mask); + + if (!IS_ERR(tfm) && WARN_ON(crypto_aead_reqsize(tfm) > MAX_SYNC_AEAD_REQSIZE)) { + crypto_free_aead(tfm); + return ERR_PTR(-EINVAL); + } + + return (struct crypto_sync_aead *)tfm; +} +EXPORT_SYMBOL_GPL(crypto_alloc_sync_aead); + int crypto_has_aead(const char *alg_name, u32 type, u32 mask) { return crypto_type_has_alg(alg_name, &crypto_aead_type, type, mask); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/crypto/crc64_iso3309_generic.c v_kernel/crypto/crc64_iso3309_generic.c --- linux-6.12.57/crypto/crc64_iso3309_generic.c 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/crypto/crc64_iso3309_generic.c 2026-04-21 11:35:32.042924447 +0200 @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +static int chksum_cra_init(struct crypto_tfm *tfm) +{ + u64 *key = crypto_tfm_ctx(tfm); + + *key = 0; + return 0; +} + +static int chksum_init(struct shash_desc *desc) +{ + u64 *key = crypto_shash_ctx(desc->tfm); + u64 *crc = shash_desc_ctx(desc); + + *crc = *key; + return 0; +} + +static int chksum_update(struct shash_desc *desc, const u8 *data, + unsigned int length) +{ + u64 *crc = shash_desc_ctx(desc); + + *crc = crc64_iso3309_generic(*crc, data, length); + return 0; +} + +static int chksum_final(struct shash_desc *desc, u8 *out) +{ + u64 *crc = shash_desc_ctx(desc); + + put_unaligned_le64(*crc, out); + return 0; +} + +static int __chksum_finup(u64 crc, const u8 *data, unsigned int len, u8 *out) +{ + crc = crc64_iso3309_generic(crc, data, len); + + put_unaligned_le64(crc, out); + return 0; +} + +static int chksum_finup(struct shash_desc *desc, const u8 *data, + unsigned int len, u8 *out) +{ + u64 *crc = shash_desc_ctx(desc); + + return __chksum_finup(*crc, data, len, out); +} + +static int chksum_digest(struct shash_desc *desc, const u8 *data, + unsigned int length, u8 *out) +{ + u64 *key = crypto_shash_ctx(desc->tfm); + + return __chksum_finup(*key, data, length, out); +} + +/* + * Setting the seed allows arbitrary accumulators and flexible XOR policy + */ +static int chksum_setkey(struct crypto_shash *tfm, const u8 *key, + unsigned int keylen) +{ + u64 *mctx = crypto_shash_ctx(tfm); + + if (keylen != sizeof(u64)) + return -EINVAL; + + *mctx = get_unaligned_le64(key); + return 0; +} + +static struct shash_alg alg = { + .digestsize = sizeof(u64), + .setkey = chksum_setkey, + .init = chksum_init, + .update = chksum_update, + .final = chksum_final, + .finup = chksum_finup, + .digest = chksum_digest, + .descsize = sizeof(u64), + .base = { + .cra_name = CRC64_ISO3309_STRING, + .cra_driver_name = "crc64-iso3309-generic", + .cra_priority = 200, + .cra_flags = CRYPTO_ALG_OPTIONAL_KEY, + .cra_blocksize = 1, + .cra_ctxsize = sizeof(u64), + .cra_module = THIS_MODULE, + .cra_init = chksum_cra_init, + } +}; + +static int __init crc64_iso3309_init(void) +{ + return crypto_register_shash(&alg); +} + +static void __exit crc64_iso3309_exit(void) +{ + crypto_unregister_shash(&alg); +} + +module_init(crc64_iso3309_init); +module_exit(crc64_iso3309_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Kamlesh Gurudasani "); +MODULE_DESCRIPTION("ISO3309 model CRC64 calculation"); +MODULE_ALIAS_CRYPTO("crc64-iso3309"); +MODULE_ALIAS_CRYPTO("crc64-iso3309-generic"); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/crypto/Kconfig v_kernel/crypto/Kconfig --- linux-6.12.57/crypto/Kconfig 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/crypto/Kconfig 2026-04-21 11:35:32.022924395 +0200 @@ -1109,6 +1109,17 @@ CRC algorithm used by the SCSI Block Commands standard. +config CRYPTO_CRC64_ISO3309 + tristate "CRC64 based on ISO 3309 Model algorithm" + depends on CRC64 + select CRYPTO_HASH + help + CRC64 CRC algorithm based on the ISO 3309 Model CRC Algorithm + + Generator polynomial: x^64 + x^4 + x^3 + x + 1 + Polynomial value: 0x000000000000001b + See https://en.wikipedia.org/wiki/Cyclic_redundancy_check + config CRYPTO_CRC64_ROCKSOFT tristate "CRC64 based on Rocksoft Model algorithm" depends on CRC64 diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/crypto/Makefile v_kernel/crypto/Makefile --- linux-6.12.57/crypto/Makefile 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/crypto/Makefile 2026-04-21 11:35:32.022924395 +0200 @@ -153,6 +153,7 @@ obj-$(CONFIG_CRYPTO_CRC32C) += crc32c_generic.o obj-$(CONFIG_CRYPTO_CRC32) += crc32_generic.o obj-$(CONFIG_CRYPTO_CRCT10DIF) += crct10dif_common.o crct10dif_generic.o +obj-$(CONFIG_CRYPTO_CRC64_ISO3309) += crc64_iso3309_generic.o obj-$(CONFIG_CRYPTO_CRC64_ROCKSOFT) += crc64_rocksoft_generic.o obj-$(CONFIG_CRYPTO_AUTHENC) += authenc.o authencesn.o obj-$(CONFIG_CRYPTO_LZO) += lzo.o lzo-rle.o diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/crypto/tcrypt.c v_kernel/crypto/tcrypt.c --- linux-6.12.57/crypto/tcrypt.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/crypto/tcrypt.c 2026-04-21 11:35:32.065924507 +0200 @@ -2314,6 +2314,12 @@ generic_hash_speed_template); if (mode > 300 && mode < 400) break; fallthrough; + case 329: + test_hash_speed("crc64-iso3309", sec, + generic_hash_speed_template); + if (mode > 300 && mode < 400) + break; + fallthrough; case 399: break; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/crypto/testmgr.c v_kernel/crypto/testmgr.c --- linux-6.12.57/crypto/testmgr.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/crypto/testmgr.c 2026-04-21 11:35:32.067924512 +0200 @@ -4704,6 +4704,13 @@ .hash = __VECS(crc32c_tv_template) } }, { + .alg = "crc64-iso3309", + .test = alg_test_hash, + .fips_allowed = 1, + .suite = { + .hash = __VECS(crc64_iso3309_tv_template) + } + }, { .alg = "crc64-rocksoft", .test = alg_test_hash, .fips_allowed = 1, diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/crypto/testmgr.h v_kernel/crypto/testmgr.h --- linux-6.12.57/crypto/testmgr.h 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/crypto/testmgr.h 2026-04-21 11:35:32.086924562 +0200 @@ -5355,6 +5355,410 @@ } }; +static const struct hash_testvec crc64_iso3309_tv_template[] = { + { + .psize = 0, + .digest = "\x00\x00\x00\x00\x00\x00\x00\x00", + }, + { + .plaintext = "\x01\x02\x03\x04\x05\x06\x07\x08" + "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10" + "\x11\x12\x13\x14\x15\x16\x17\x18" + "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20" + "\x21\x22\x23\x24\x25\x26\x27\x28", + .psize = 40, + .digest = "\xaf\x45\xba\x7d\xf2\xda\xa0\xaa", + }, + { + .plaintext = "\x29\x2a\x2b\x2c\x2d\x2e\x2f\x30" + "\x31\x32\x33\x34\x35\x36\x37\x38" + "\x39\x3a\x3b\x3c\x3d\x3e\x3f\x40" + "\x41\x42\x43\x44\x45\x46\x47\x48" + "\x49\x4a\x4b\x4c\x4d\x4e\x4f\x50", + .psize = 40, + .digest = "\x81\x55\x2e\x76\xf8\xd0\xaa\xa0", + }, + { + .plaintext = "\x51\x52\x53\x54\x55\x56\x57\x58" + "\x59\x5a\x5b\x5c\x5d\x5e\x5f\x60" + "\x61\x62\x63\x64\x65\x66\x67\x68" + "\x69\x6a\x6b\x6c\x6d\x6e\x6f\x70" + "\x71\x72\x73\x74\x75\x76\x77\x78", + .psize = 40, + .digest = "\xc6\xb6\x26\x82\x0d\x25\x5f\x55", + }, + { + .plaintext = "\x79\x7a\x7b\x7c\x7d\x7e\x7f\x80" + "\x81\x82\x83\x84\x85\x86\x87\x88" + "\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90" + "\x91\x92\x93\x94\x95\x96\x97\x98" + "\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0", + .psize = 40, + .digest = "\x20\x8a\xe6\x59\xdf\xf7\x8d\x87", + }, + { + .plaintext = "\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8" + "\xa9\xaa\xab\xac\xad\xae\xaf\xb0" + "\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8" + "\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0" + "\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8", + .psize = 40, + .digest = "\x19\x9e\xba\xff\x70\x58\x22\x28", + + }, + { + .plaintext = "\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0" + "\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8" + "\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0" + "\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8" + "\xe9\xea\xeb\xec\xed\xee\xef\xf0", + .psize = 40, + .digest = "\xa3\xdc\x11\x98\x16\x3e\x44\x4e", + }, + { + .plaintext = "\x29\x2a\x2b\x2c\x2d\x2e\x2f\x30" + "\x31\x32\x33\x34\x35\x36\x37\x38" + "\x39\x3a\x3b\x3c\x3d\x3e\x3f\x40" + "\x41\x42\x43\x44\x45\x46\x47\x48" + "\x49\x4a\x4b\x4c\x4d\x4e\x4f\x50", + .psize = 40, + .digest = "\x81\x55\x2e\x76\xf8\xd0\xaa\xa0", + }, + { + .plaintext = "\x51\x52\x53\x54\x55\x56\x57\x58" + "\x59\x5a\x5b\x5c\x5d\x5e\x5f\x60" + "\x61\x62\x63\x64\x65\x66\x67\x68" + "\x69\x6a\x6b\x6c\x6d\x6e\x6f\x70" + "\x71\x72\x73\x74\x75\x76\x77\x78", + .psize = 40, + .digest = "\xc6\xb6\x26\x82\x0d\x25\x5f\x55", + }, + { + .plaintext = "\x79\x7a\x7b\x7c\x7d\x7e\x7f\x80" + "\x81\x82\x83\x84\x85\x86\x87\x88" + "\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90" + "\x91\x92\x93\x94\x95\x96\x97\x98" + "\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0", + .psize = 40, + .digest = "\x20\x8a\xe6\x59\xdf\xf7\x8d\x87", + }, + { + .plaintext = "\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8" + "\xa9\xaa\xab\xac\xad\xae\xaf\xb0" + "\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8" + "\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0" + "\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8", + .psize = 40, + .digest = "\x19\x9e\xba\xff\x70\x58\x22\x28", + }, + { + .plaintext = "\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0" + "\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8" + "\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0" + "\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8" + "\xe9\xea\xeb\xec\xed\xee\xef\xf0", + .psize = 40, + .digest = "\xa3\xdc\x11\x98\x16\x3e\x44\x4e", + }, + { + .key = "\xff\xff\xff\xff\xff\xff\xff\xff", + .ksize = 8, + .plaintext = "\x01\x02\x03\x04\x05\x06\x07\x08" + "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10" + "\x11\x12\x13\x14\x15\x16\x17\x18" + "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20" + "\x21\x22\x23\x24\x25\x26\x27\x28" + "\x29\x2a\x2b\x2c\x2d\x2e\x2f\x30" + "\x31\x32\x33\x34\x35\x36\x37\x38" + "\x39\x3a\x3b\x3c\x3d\x3e\x3f\x40" + "\x41\x42\x43\x44\x45\x46\x47\x48" + "\x49\x4a\x4b\x4c\x4d\x4e\x4f\x50" + "\x51\x52\x53\x54\x55\x56\x57\x58" + "\x59\x5a\x5b\x5c\x5d\x5e\x5f\x60" + "\x61\x62\x63\x64\x65\x66\x67\x68" + "\x69\x6a\x6b\x6c\x6d\x6e\x6f\x70" + "\x71\x72\x73\x74\x75\x76\x77\x78" + "\x79\x7a\x7b\x7c\x7d\x7e\x7f\x80" + "\x81\x82\x83\x84\x85\x86\x87\x88" + "\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90" + "\x91\x92\x93\x94\x95\x96\x97\x98" + "\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0" + "\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8" + "\xa9\xaa\xab\xac\xad\xae\xaf\xb0" + "\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8" + "\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0" + "\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8" + "\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0" + "\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8" + "\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0" + "\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8" + "\xe9\xea\xeb\xec\xed\xee\xef\xf0", + .psize = 240, + .digest = "\x8b\xa6\xd7\x91\xb4\x74\x96\x84", + }, { + .key = "\xff\xff\xff\xff\xff\xff\xff\xff", + .ksize = 8, + .plaintext = "\x6e\x05\x79\x10\xa7\x1b\xb2\x49" + "\xe0\x54\xeb\x82\x19\x8d\x24\xbb" + "\x2f\xc6\x5d\xf4\x68\xff\x96\x0a" + "\xa1\x38\xcf\x43\xda\x71\x08\x7c" + "\x13\xaa\x1e\xb5\x4c\xe3\x57\xee" + "\x85\x1c\x90\x27\xbe\x32\xc9\x60" + "\xf7\x6b\x02\x99\x0d\xa4\x3b\xd2" + "\x46\xdd\x74\x0b\x7f\x16\xad\x21" + "\xb8\x4f\xe6\x5a\xf1\x88\x1f\x93" + "\x2a\xc1\x35\xcc\x63\xfa\x6e\x05" + "\x9c\x10\xa7\x3e\xd5\x49\xe0\x77" + "\x0e\x82\x19\xb0\x24\xbb\x52\xe9" + "\x5d\xf4\x8b\x22\x96\x2d\xc4\x38" + "\xcf\x66\xfd\x71\x08\x9f\x13\xaa" + "\x41\xd8\x4c\xe3\x7a\x11\x85\x1c" + "\xb3\x27\xbe\x55\xec\x60\xf7\x8e" + "\x02\x99\x30\xc7\x3b\xd2\x69\x00" + "\x74\x0b\xa2\x16\xad\x44\xdb\x4f" + "\xe6\x7d\x14\x88\x1f\xb6\x2a\xc1" + "\x58\xef\x63\xfa\x91\x05\x9c\x33" + "\xca\x3e\xd5\x6c\x03\x77\x0e\xa5" + "\x19\xb0\x47\xde\x52\xe9\x80\x17" + "\x8b\x22\xb9\x2d\xc4\x5b\xf2\x66" + "\xfd\x94\x08\x9f\x36\xcd\x41\xd8" + "\x6f\x06\x7a\x11\xa8\x1c\xb3\x4a" + "\xe1\x55\xec\x83\x1a\x8e\x25\xbc" + "\x30\xc7\x5e\xf5\x69\x00\x97\x0b" + "\xa2\x39\xd0\x44\xdb\x72\x09\x7d" + "\x14\xab\x1f\xb6\x4d\xe4\x58\xef" + "\x86\x1d\x91\x28\xbf\x33\xca\x61" + "\xf8\x6c\x03\x9a\x0e\xa5\x3c\xd3" + "\x47\xde\x75\x0c\x80\x17\xae\x22" + "\xb9\x50\xe7\x5b\xf2\x89\x20\x94" + "\x2b\xc2\x36\xcd\x64\xfb\x6f\x06" + "\x9d\x11\xa8\x3f\xd6\x4a\xe1\x78" + "\x0f\x83\x1a\xb1\x25\xbc\x53\xea" + "\x5e\xf5\x8c\x00\x97\x2e\xc5\x39" + "\xd0\x67\xfe\x72\x09\xa0\x14\xab" + "\x42\xd9\x4d\xe4\x7b\x12\x86\x1d" + "\xb4\x28\xbf\x56\xed\x61\xf8\x8f" + "\x03\x9a\x31\xc8\x3c\xd3\x6a\x01" + "\x75\x0c\xa3\x17\xae\x45\xdc\x50" + "\xe7\x7e\x15\x89\x20\xb7\x2b\xc2" + "\x59\xf0\x64\xfb\x92\x06\x9d\x34" + "\xcb\x3f\xd6\x6d\x04\x78\x0f\xa6" + "\x1a\xb1\x48\xdf\x53\xea\x81\x18" + "\x8c\x23\xba\x2e\xc5\x5c\xf3\x67" + "\xfe\x95\x09\xa0\x37\xce\x42\xd9" + "\x70\x07\x7b\x12\xa9\x1d\xb4\x4b" + "\xe2\x56\xed\x84\x1b\x8f\x26\xbd" + "\x31\xc8\x5f\xf6\x6a\x01\x98\x0c" + "\xa3\x3a\xd1\x45\xdc\x73\x0a\x7e" + "\x15\xac\x20\xb7\x4e\xe5\x59\xf0" + "\x87\x1e\x92\x29\xc0\x34\xcb\x62" + "\xf9\x6d\x04\x9b\x0f\xa6\x3d\xd4" + "\x48\xdf\x76\x0d\x81\x18\xaf\x23" + "\xba\x51\xe8\x5c\xf3\x8a\x21\x95" + "\x2c\xc3\x37\xce\x65\xfc\x70\x07" + "\x9e\x12\xa9\x40\xd7\x4b\xe2\x79" + "\x10\x84\x1b\xb2\x26\xbd\x54\xeb" + "\x5f\xf6\x8d\x01\x98\x2f\xc6\x3a" + "\xd1\x68\xff\x73\x0a\xa1\x15\xac" + "\x43\xda\x4e\xe5\x7c\x13\x87\x1e" + "\xb5\x29\xc0\x57\xee\x62\xf9\x90" + "\x04\x9b\x32\xc9\x3d\xd4\x6b\x02" + "\x76\x0d\xa4\x18\xaf\x46\xdd\x51" + "\xe8\x7f\x16\x8a\x21\xb8\x2c\xc3" + "\x5a\xf1\x65\xfc\x93\x07\x9e\x35" + "\xcc\x40\xd7\x6e\x05\x79\x10\xa7" + "\x1b\xb2\x49\xe0\x54\xeb\x82\x19" + "\x8d\x24\xbb\x2f\xc6\x5d\xf4\x68" + "\xff\x96\x0a\xa1\x38\xcf\x43\xda" + "\x71\x08\x7c\x13\xaa\x1e\xb5\x4c" + "\xe3\x57\xee\x85\x1c\x90\x27\xbe" + "\x32\xc9\x60\xf7\x6b\x02\x99\x0d" + "\xa4\x3b\xd2\x46\xdd\x74\x0b\x7f" + "\x16\xad\x21\xb8\x4f\xe6\x5a\xf1" + "\x88\x1f\x93\x2a\xc1\x35\xcc\x63" + "\xfa\x6e\x05\x9c\x10\xa7\x3e\xd5" + "\x49\xe0\x77\x0e\x82\x19\xb0\x24" + "\xbb\x52\xe9\x5d\xf4\x8b\x22\x96" + "\x2d\xc4\x38\xcf\x66\xfd\x71\x08" + "\x9f\x13\xaa\x41\xd8\x4c\xe3\x7a" + "\x11\x85\x1c\xb3\x27\xbe\x55\xec" + "\x60\xf7\x8e\x02\x99\x30\xc7\x3b" + "\xd2\x69\x00\x74\x0b\xa2\x16\xad" + "\x44\xdb\x4f\xe6\x7d\x14\x88\x1f" + "\xb6\x2a\xc1\x58\xef\x63\xfa\x91" + "\x05\x9c\x33\xca\x3e\xd5\x6c\x03" + "\x77\x0e\xa5\x19\xb0\x47\xde\x52" + "\xe9\x80\x17\x8b\x22\xb9\x2d\xc4" + "\x5b\xf2\x66\xfd\x94\x08\x9f\x36" + "\xcd\x41\xd8\x6f\x06\x7a\x11\xa8" + "\x1c\xb3\x4a\xe1\x55\xec\x83\x1a" + "\x8e\x25\xbc\x30\xc7\x5e\xf5\x69" + "\x00\x97\x0b\xa2\x39\xd0\x44\xdb" + "\x72\x09\x7d\x14\xab\x1f\xb6\x4d" + "\xe4\x58\xef\x86\x1d\x91\x28\xbf" + "\x33\xca\x61\xf8\x6c\x03\x9a\x0e" + "\xa5\x3c\xd3\x47\xde\x75\x0c\x80" + "\x17\xae\x22\xb9\x50\xe7\x5b\xf2" + "\x89\x20\x94\x2b\xc2\x36\xcd\x64" + "\xfb\x6f\x06\x9d\x11\xa8\x3f\xd6" + "\x4a\xe1\x78\x0f\x83\x1a\xb1\x25" + "\xbc\x53\xea\x5e\xf5\x8c\x00\x97" + "\x2e\xc5\x39\xd0\x67\xfe\x72\x09" + "\xa0\x14\xab\x42\xd9\x4d\xe4\x7b" + "\x12\x86\x1d\xb4\x28\xbf\x56\xed" + "\x61\xf8\x8f\x03\x9a\x31\xc8\x3c" + "\xd3\x6a\x01\x75\x0c\xa3\x17\xae" + "\x45\xdc\x50\xe7\x7e\x15\x89\x20" + "\xb7\x2b\xc2\x59\xf0\x64\xfb\x92" + "\x06\x9d\x34\xcb\x3f\xd6\x6d\x04" + "\x78\x0f\xa6\x1a\xb1\x48\xdf\x53" + "\xea\x81\x18\x8c\x23\xba\x2e\xc5" + "\x5c\xf3\x67\xfe\x95\x09\xa0\x37" + "\xce\x42\xd9\x70\x07\x7b\x12\xa9" + "\x1d\xb4\x4b\xe2\x56\xed\x84\x1b" + "\x8f\x26\xbd\x31\xc8\x5f\xf6\x6a" + "\x01\x98\x0c\xa3\x3a\xd1\x45\xdc" + "\x73\x0a\x7e\x15\xac\x20\xb7\x4e" + "\xe5\x59\xf0\x87\x1e\x92\x29\xc0" + "\x34\xcb\x62\xf9\x6d\x04\x9b\x0f" + "\xa6\x3d\xd4\x48\xdf\x76\x0d\x81" + "\x18\xaf\x23\xba\x51\xe8\x5c\xf3" + "\x8a\x21\x95\x2c\xc3\x37\xce\x65" + "\xfc\x70\x07\x9e\x12\xa9\x40\xd7" + "\x4b\xe2\x79\x10\x84\x1b\xb2\x26" + "\xbd\x54\xeb\x5f\xf6\x8d\x01\x98" + "\x2f\xc6\x3a\xd1\x68\xff\x73\x0a" + "\xa1\x15\xac\x43\xda\x4e\xe5\x7c" + "\x13\x87\x1e\xb5\x29\xc0\x57\xee" + "\x62\xf9\x90\x04\x9b\x32\xc9\x3d" + "\xd4\x6b\x02\x76\x0d\xa4\x18\xaf" + "\x46\xdd\x51\xe8\x7f\x16\x8a\x21" + "\xb8\x2c\xc3\x5a\xf1\x65\xfc\x93" + "\x07\x9e\x35\xcc\x40\xd7\x6e\x05" + "\x79\x10\xa7\x1b\xb2\x49\xe0\x54" + "\xeb\x82\x19\x8d\x24\xbb\x2f\xc6" + "\x5d\xf4\x68\xff\x96\x0a\xa1\x38" + "\xcf\x43\xda\x71\x08\x7c\x13\xaa" + "\x1e\xb5\x4c\xe3\x57\xee\x85\x1c" + "\x90\x27\xbe\x32\xc9\x60\xf7\x6b" + "\x02\x99\x0d\xa4\x3b\xd2\x46\xdd" + "\x74\x0b\x7f\x16\xad\x21\xb8\x4f" + "\xe6\x5a\xf1\x88\x1f\x93\x2a\xc1" + "\x35\xcc\x63\xfa\x6e\x05\x9c\x10" + "\xa7\x3e\xd5\x49\xe0\x77\x0e\x82" + "\x19\xb0\x24\xbb\x52\xe9\x5d\xf4" + "\x8b\x22\x96\x2d\xc4\x38\xcf\x66" + "\xfd\x71\x08\x9f\x13\xaa\x41\xd8" + "\x4c\xe3\x7a\x11\x85\x1c\xb3\x27" + "\xbe\x55\xec\x60\xf7\x8e\x02\x99" + "\x30\xc7\x3b\xd2\x69\x00\x74\x0b" + "\xa2\x16\xad\x44\xdb\x4f\xe6\x7d" + "\x14\x88\x1f\xb6\x2a\xc1\x58\xef" + "\x63\xfa\x91\x05\x9c\x33\xca\x3e" + "\xd5\x6c\x03\x77\x0e\xa5\x19\xb0" + "\x47\xde\x52\xe9\x80\x17\x8b\x22" + "\xb9\x2d\xc4\x5b\xf2\x66\xfd\x94" + "\x08\x9f\x36\xcd\x41\xd8\x6f\x06" + "\x7a\x11\xa8\x1c\xb3\x4a\xe1\x55" + "\xec\x83\x1a\x8e\x25\xbc\x30\xc7" + "\x5e\xf5\x69\x00\x97\x0b\xa2\x39" + "\xd0\x44\xdb\x72\x09\x7d\x14\xab" + "\x1f\xb6\x4d\xe4\x58\xef\x86\x1d" + "\x91\x28\xbf\x33\xca\x61\xf8\x6c" + "\x03\x9a\x0e\xa5\x3c\xd3\x47\xde" + "\x75\x0c\x80\x17\xae\x22\xb9\x50" + "\xe7\x5b\xf2\x89\x20\x94\x2b\xc2" + "\x36\xcd\x64\xfb\x6f\x06\x9d\x11" + "\xa8\x3f\xd6\x4a\xe1\x78\x0f\x83" + "\x1a\xb1\x25\xbc\x53\xea\x5e\xf5" + "\x8c\x00\x97\x2e\xc5\x39\xd0\x67" + "\xfe\x72\x09\xa0\x14\xab\x42\xd9" + "\x4d\xe4\x7b\x12\x86\x1d\xb4\x28" + "\xbf\x56\xed\x61\xf8\x8f\x03\x9a" + "\x31\xc8\x3c\xd3\x6a\x01\x75\x0c" + "\xa3\x17\xae\x45\xdc\x50\xe7\x7e" + "\x15\x89\x20\xb7\x2b\xc2\x59\xf0" + "\x64\xfb\x92\x06\x9d\x34\xcb\x3f" + "\xd6\x6d\x04\x78\x0f\xa6\x1a\xb1" + "\x48\xdf\x53\xea\x81\x18\x8c\x23" + "\xba\x2e\xc5\x5c\xf3\x67\xfe\x95" + "\x09\xa0\x37\xce\x42\xd9\x70\x07" + "\x7b\x12\xa9\x1d\xb4\x4b\xe2\x56" + "\xed\x84\x1b\x8f\x26\xbd\x31\xc8" + "\x5f\xf6\x6a\x01\x98\x0c\xa3\x3a" + "\xd1\x45\xdc\x73\x0a\x7e\x15\xac" + "\x20\xb7\x4e\xe5\x59\xf0\x87\x1e" + "\x92\x29\xc0\x34\xcb\x62\xf9\x6d" + "\x04\x9b\x0f\xa6\x3d\xd4\x48\xdf" + "\x76\x0d\x81\x18\xaf\x23\xba\x51" + "\xe8\x5c\xf3\x8a\x21\x95\x2c\xc3" + "\x37\xce\x65\xfc\x70\x07\x9e\x12" + "\xa9\x40\xd7\x4b\xe2\x79\x10\x84" + "\x1b\xb2\x26\xbd\x54\xeb\x5f\xf6" + "\x8d\x01\x98\x2f\xc6\x3a\xd1\x68" + "\xff\x73\x0a\xa1\x15\xac\x43\xda" + "\x4e\xe5\x7c\x13\x87\x1e\xb5\x29" + "\xc0\x57\xee\x62\xf9\x90\x04\x9b" + "\x32\xc9\x3d\xd4\x6b\x02\x76\x0d" + "\xa4\x18\xaf\x46\xdd\x51\xe8\x7f" + "\x16\x8a\x21\xb8\x2c\xc3\x5a\xf1" + "\x65\xfc\x93\x07\x9e\x35\xcc\x40" + "\xd7\x6e\x05\x79\x10\xa7\x1b\xb2" + "\x49\xe0\x54\xeb\x82\x19\x8d\x24" + "\xbb\x2f\xc6\x5d\xf4\x68\xff\x96" + "\x0a\xa1\x38\xcf\x43\xda\x71\x08" + "\x7c\x13\xaa\x1e\xb5\x4c\xe3\x57" + "\xee\x85\x1c\x90\x27\xbe\x32\xc9" + "\x60\xf7\x6b\x02\x99\x0d\xa4\x3b" + "\xd2\x46\xdd\x74\x0b\x7f\x16\xad" + "\x21\xb8\x4f\xe6\x5a\xf1\x88\x1f" + "\x93\x2a\xc1\x35\xcc\x63\xfa\x6e" + "\x05\x9c\x10\xa7\x3e\xd5\x49\xe0" + "\x77\x0e\x82\x19\xb0\x24\xbb\x52" + "\xe9\x5d\xf4\x8b\x22\x96\x2d\xc4" + "\x38\xcf\x66\xfd\x71\x08\x9f\x13" + "\xaa\x41\xd8\x4c\xe3\x7a\x11\x85" + "\x1c\xb3\x27\xbe\x55\xec\x60\xf7" + "\x8e\x02\x99\x30\xc7\x3b\xd2\x69" + "\x00\x74\x0b\xa2\x16\xad\x44\xdb" + "\x4f\xe6\x7d\x14\x88\x1f\xb6\x2a" + "\xc1\x58\xef\x63\xfa\x91\x05\x9c" + "\x33\xca\x3e\xd5\x6c\x03\x77\x0e" + "\xa5\x19\xb0\x47\xde\x52\xe9\x80" + "\x17\x8b\x22\xb9\x2d\xc4\x5b\xf2" + "\x66\xfd\x94\x08\x9f\x36\xcd\x41" + "\xd8\x6f\x06\x7a\x11\xa8\x1c\xb3" + "\x4a\xe1\x55\xec\x83\x1a\x8e\x25" + "\xbc\x30\xc7\x5e\xf5\x69\x00\x97" + "\x0b\xa2\x39\xd0\x44\xdb\x72\x09" + "\x7d\x14\xab\x1f\xb6\x4d\xe4\x58" + "\xef\x86\x1d\x91\x28\xbf\x33\xca" + "\x61\xf8\x6c\x03\x9a\x0e\xa5\x3c" + "\xd3\x47\xde\x75\x0c\x80\x17\xae" + "\x22\xb9\x50\xe7\x5b\xf2\x89\x20" + "\x94\x2b\xc2\x36\xcd\x64\xfb\x6f" + "\x06\x9d\x11\xa8\x3f\xd6\x4a\xe1" + "\x78\x0f\x83\x1a\xb1\x25\xbc\x53" + "\xea\x5e\xf5\x8c\x00\x97\x2e\xc5" + "\x39\xd0\x67\xfe\x72\x09\xa0\x14" + "\xab\x42\xd9\x4d\xe4\x7b\x12\x86" + "\x1d\xb4\x28\xbf\x56\xed\x61\xf8" + "\x8f\x03\x9a\x31\xc8\x3c\xd3\x6a" + "\x01\x75\x0c\xa3\x17\xae\x45\xdc" + "\x50\xe7\x7e\x15\x89\x20\xb7\x2b" + "\xc2\x59\xf0\x64\xfb\x92\x06\x9d" + "\x34\xcb\x3f\xd6\x6d\x04\x78\x0f" + "\xa6\x1a\xb1\x48\xdf\x53\xea\x81" + "\x18\x8c\x23\xba\x2e\xc5\x5c\xf3" + "\x67\xfe\x95\x09\xa0\x37\xce\x42" + "\xd9\x70\x07\x7b\x12\xa9\x1d\xb4" + "\x4b\xe2\x56\xed\x84\x1b\x8f\x26" + "\xbd\x31\xc8\x5f\xf6\x6a\x01\x98", + .psize = 2048, + .digest = "\x4b\x82\xa5\x0e\x72\x01\x0b\xc6", + } +}; + static const u8 zeroes[4096] = { [0 ... 4095] = 0 }; static const u8 ones[4096] = { [0 ... 4095] = 0xff }; @@ -20824,6 +21228,62 @@ }; static const struct aead_testvec aes_gcm_tv_template[] = { + { + .key = "\x16\xe1\x23\x12\x22\x08\xa7\xd6" + "\x59\xe8\xbc\x5f\x87\x7c\xe4\x8c" + "\xb2\x1a\x45\xa8\x65\x15\x70\x2d" + "\x61\x96\x35\xf2\x08\xf9\x3b\x46", + .klen = 32, + .iv = "\x75\x9e\xb4\x01\x75\x63\x1b\x68" + "\xfd\xb7\xa7\xaa", + .ptext = "\x9d\xa1", + .plen = 2, + .assoc = "\x9d", + .alen = 1, + .ctext = "\xb8\xd6\x41\x86\xde\x36\x88\x71" + "\xf8\xf8\x23\xe7\x93\x8a\x8b\x33" + "\xc0\xfc", + .clen = 18, + }, { + .key = "\xdd\xee\xdd\xee\xdd\xee\xdd\xee" + "\xdd\xee\xdd\xee\xdd\xee\xdd\xee", + .klen = 16, + .iv = "\xbb\xcc\xbb\xcc\xbb\xcc\xbb\xcc" + "\xbb\xcc\xbb\xcc", + .ptext = "\xff\x00\xff\x00", + .plen = 4, + .assoc = "\xaa\xdd\xaa\xdd\xaa\xdd\xaa\xdd" + "\xaa\xdd\xaa\xdd\xaa\xdd\xaa\xdd", + .alen = 16, + .ctext = "\x38\x17\x1f\x91\xc0\x5a\x02\x7c" + "\x7c\x5f\xe3\xd1\x7d\x9a\x90\x14" + "\xfe\xbe\xb9\x6a", + .clen = 20, + }, { + .key = "\xdd\xee\xdd\xee\xdd\xee\xdd\xee" + "\xdd\xee\xdd\xee\xdd\xee\xdd\xee", + .klen = 16, + .iv = "\xbb\xcc\xbb\xcc\xbb\xcc\xbb\xcc" + "\xbb\xcc\xbb\xcc", + .ptext = "\xff\x00\xff\x00", + .plen = 4, + .ctext = "\x38\x17\x1f\x91\xc6\xc3\x92\xf5" + "\xd8\xf4\x9c\x34\x2c\x67\x1c\x97" + "\x4f\x23\xb3\xcd", + .clen = 20, + }, { + .key = "\xff\xff\xff\xff\xff\xff\xff\xff" + "\xff\xff\xff\xff\xff\xff\xff\xff", + .klen = 16, + .iv = "\xff\xff\xff\xff\xff\xff\xff\xff" + "\xff\xff\xff\xff", + .ptext = "\xff\x00\xff\x00", + .plen = 4, + .ctext = "\x24\x24\xab\x37" + "\xfd\x64\x3d\x2a\x76\x31\x4e\x34" + "\xdf\x5e\x3f\xdd\x95\xee\x1a\x97", + .clen = 20, + }, { /* From McGrew & Viega - http://citeseer.ist.psu.edu/656989.html */ .key = zeroed_string, .klen = 16, diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/admin-guide/pm/cpuidle.rst v_kernel/Documentation/admin-guide/pm/cpuidle.rst --- linux-6.12.57/Documentation/admin-guide/pm/cpuidle.rst 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/admin-guide/pm/cpuidle.rst 2026-04-21 11:35:24.562904828 +0200 @@ -585,6 +585,13 @@ they are allowed to select for that CPU. They should never select any idle states with exit latency beyond that limit. +While the above CPU QoS constraints applies to a running system, user space may +also request a CPU system-wakeup latency QoS limit, via the `cpu_wakeup_latency` +file. This QoS constraint is respected when selecting a suitable idle state +for the CPUs, while entering the system-wide suspend-to-idle sleep state. + +Note that, in regards how to manage the QoS request from user space for the +`cpu_wakeup_latency` file, it works according to the `cpu_dma_latency` file. Idle States Control Via Kernel Command Line =========================================== diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/arm/ti/k3.yaml v_kernel/Documentation/devicetree/bindings/arm/ti/k3.yaml --- linux-6.12.57/Documentation/devicetree/bindings/arm/ti/k3.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/arm/ti/k3.yaml 2026-04-21 11:35:24.727905261 +0200 @@ -31,6 +31,19 @@ - const: phytec,am62a-phycore-som - const: ti,am62a7 + - description: K3 AM62D2 SoC and Boards + items: + - enum: + - ti,am62d2-evm + - const: ti,am62d2 + + - description: K3 AM62L3 SoC and Boards + items: + - enum: + - ti,am62l3-evm + - ti,am62l3-badge + - const: ti,am62l3 + - description: K3 AM62P5 SoC and Boards items: - enum: @@ -51,11 +64,18 @@ - ti,am62-lp-sk - const: ti,am625 + - description: K3 AM6254xxl SiP + items: + - enum: + - ti,am6254xxl-sk + - const: ti,am6254xxl + - description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards items: - enum: - toradex,verdin-am62-nonwifi-dahlia # Verdin AM62 Module on Dahlia - toradex,verdin-am62-nonwifi-dev # Verdin AM62 Module on Verdin Development Board + - toradex,verdin-am62-nonwifi-ivy # Verdin AM62 Module on Ivy - toradex,verdin-am62-nonwifi-mallow # Verdin AM62 Module on Mallow - toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia - const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT @@ -67,6 +87,7 @@ - enum: - toradex,verdin-am62-wifi-dahlia # Verdin AM62 Wi-Fi / BT Module on Dahlia - toradex,verdin-am62-wifi-dev # Verdin AM62 Wi-Fi / BT M. on Verdin Development B. + - toradex,verdin-am62-wifi-ivy # Verdin AM62 Wi-Fi / BT Module on Ivy - toradex,verdin-am62-wifi-mallow # Verdin AM62 Wi-Fi / BT Module on Mallow - toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia - const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module @@ -144,6 +165,12 @@ - ti,j722s-evm - const: ti,j722s + - description: K3 J742S2 SoC + items: + - enum: + - ti,j742s2-evm + - const: ti,j742s2 + - description: K3 J784s4 SoC items: - enum: diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/arm/ti/omap.yaml v_kernel/Documentation/devicetree/bindings/arm/ti/omap.yaml --- linux-6.12.57/Documentation/devicetree/bindings/arm/ti/omap.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/arm/ti/omap.yaml 2026-04-21 11:35:24.727905261 +0200 @@ -107,6 +107,7 @@ - compulab,cm-t335 - moxa,uc-8100-me-t - novatech,am335x-lxm + - seeed,am335x-bone-green-eco - ti,am335x-bone - ti,am335x-evm - ti,am3359-icev2 diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/crypto/ti,dthev2.yaml v_kernel/Documentation/devicetree/bindings/crypto/ti,dthev2.yaml --- linux-6.12.57/Documentation/devicetree/bindings/crypto/ti,dthev2.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/crypto/ti,dthev2.yaml 2026-04-21 11:35:24.837905549 +0200 @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/ti,dthev2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: K3 SoC DTHE V2 crypto module + +maintainers: + - T Pratham + +properties: + compatible: + enum: + - ti,am62l-dthev2 + + reg: + maxItems: 1 + + dmas: + items: + - description: AES Engine RX DMA Channel + - description: AES Engine TX DMA Channel + - description: SHA Engine TX DMA Channel + + dma-names: + items: + - const: rx + - const: tx1 + - const: tx2 + +required: + - compatible + - reg + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + crypto@40800000 { + compatible = "ti,am62l-dthev2"; + reg = <0x00 0x40800000 0x00 0x10000>; + + dmas = <&main_bcdma 0 0 0x4700 0>, + <&main_bcdma 0 0 0xc701 0>, + <&main_bcdma 0 0 0xc700 0>; + dma-names = "rx", "tx1", "tx2"; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml v_kernel/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml --- linux-6.12.57/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml 2026-04-21 11:35:24.837905549 +0200 @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/ti,mcrc64.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments MCRC64 + +description: + The MCRC64 engine calculates 64-bit cyclic redundancy checks + (CRC) according to the ISO 3309 standard. + +maintainers: + - Kamlesh Gurudasani + +properties: + compatible: + const: ti,am62-mcrc64 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - power-domains + +additionalProperties: false + +examples: + - | + #include + + crc@30300000 { + compatible = "ti,am62-mcrc64"; + reg = <0x30300000 0x1000>; + clocks = <&k3_clks 116 0>; + power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml v_kernel/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml --- linux-6.12.57/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml 2026-04-21 11:35:24.846905573 +0200 @@ -57,6 +57,12 @@ interrupts: maxItems: 1 + cdns,no-hpd: + type: boolean + description: + Set if the HPD line on the bridge isn't hooked up to anything or is + otherwise unusable. + ports: $ref: /schemas/graph.yaml#/properties/ports diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml v_kernel/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml --- linux-6.12.57/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml 2026-04-21 11:35:24.848905578 +0200 @@ -19,6 +19,7 @@ compatible: enum: - ite,it66121 + - ite,it66122 - ite,it6610 reg: diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/display/panel/panel-simple.yaml v_kernel/Documentation/devicetree/bindings/display/panel/panel-simple.yaml --- linux-6.12.57/Documentation/devicetree/bindings/display/panel/panel-simple.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/display/panel/panel-simple.yaml 2026-04-21 11:35:24.881905664 +0200 @@ -248,6 +248,8 @@ - qiaodian,qd43003c0-40 # Shenzhen QiShenglong Industrialist Co., Ltd. Gopher 2b 4.3" 480(RGB)x272 TFT LCD panel - qishenglong,gopher2b-lcd + # Raspberry Pi 7" 800x600 LCD Panel + - raspberrypi,7inch-dsi # Rocktech Displays Ltd. RK101II01D-CT 10.1" TFT 1280x800 - rocktech,rk101ii01d-ct # Rocktech Display Ltd. RK070ER9427 800(RGB)x480 TFT LCD panel diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/display/solomon,ssd16xx.yaml v_kernel/Documentation/devicetree/bindings/display/solomon,ssd16xx.yaml --- linux-6.12.57/Documentation/devicetree/bindings/display/solomon,ssd16xx.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/display/solomon,ssd16xx.yaml 2026-04-21 11:35:24.895905701 +0200 @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/solomon,ssd16xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Solomon Systech SSD16xx e-ink display controller family + +maintainers: + - Devarsh Thakkar + +description: + The SSD16xx family includes e-Paper display controllers (SSD1680, SSD1681, SSD1683) + with integrated gate driver, source driver and timing controller. Different panels + use these controllers in either monochrome or 3-color configurations. This driver + uses panel-specific compatibles to distinguish between different display modules + and their required initialization sequences. The controller uses a 4-wire SPI + interface and requires GPIO pins for reset, busy status, and data/command control. + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - gooddisplay,gdey042t81 # 4.2" 400x300 monochrome (SSD1683 controller) + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 2000000 + default: 2000000 + description: + Maximum SPI clock frequency. The SSD16xx family supports up to 2MHz. + + reset-gpios: + maxItems: 1 + description: + GPIO connected to the RSTB (reset) pin. Active low. + + busy-gpios: + maxItems: 1 + description: + GPIO connected to the BUSY pin. Active high when the controller + is busy updating the display. + + dc-gpios: + maxItems: 1 + description: + GPIO connected to the D/C (Data/Command) pin. Low for command, + high for data. + +required: + - compatible + - reg + - reset-gpios + - busy-gpios + - dc-gpios + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + display@0 { + compatible = "gooddisplay,gdey042t81"; + reg = <0>; + spi-max-frequency = <2000000>; + reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + busy-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + dc-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; + }; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/display/ti/ti,am625-oldi.yaml v_kernel/Documentation/devicetree/bindings/display/ti/ti,am625-oldi.yaml --- linux-6.12.57/Documentation/devicetree/bindings/display/ti/ti,am625-oldi.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/display/ti/ti,am625-oldi.yaml 2026-04-21 11:35:24.901905717 +0200 @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/ti/ti,am625-oldi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments AM625 OLDI Transmitter + +maintainers: + - Tomi Valkeinen + - Aradhya Bhatia + +description: + The AM625 TI Keystone OpenLDI transmitter (OLDI TX) supports serialized RGB + pixel data transmission between host and flat panel display over LVDS (Low + Voltage Differential Sampling) interface. The OLDI TX consists of 7-to-1 data + serializers, and 4-data and 1-clock LVDS outputs. It supports the LVDS output + formats "jeida-18", "jeida-24" and "vesa-18", and can accept 24-bit RGB or + padded and un-padded 18-bit RGB bus formats as input. + +properties: + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: serial clock input for the OLDI transmitters + + clock-names: + const: serial + + ti,companion-oldi: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to companion OLDI transmitter. This property is required for both + the OLDI TXes if they are expected to work either in dual-lvds mode or in + clone mode. This property should point to the other OLDI TX's phandle. + + ti,secondary-oldi: + type: boolean + description: + Boolean property to mark the OLDI transmitter as the secondary one, when the + OLDI hardware is expected to run as a companion HW, in cases of dual-lvds + mode or clone mode. The primary OLDI hardware is responsible for all the + hardware configuration. + + ti,oldi-io-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to syscon device node mapping OLDI IO_CTRL registers found in the + control MMR region. These registers are required to toggle the I/O lane + power, and control its electrical characteristics. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Parallel RGB input port + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: LVDS output port + + required: + - port@0 + - port@1 + +allOf: + - if: + required: + - ti,secondary-oldi + then: + properties: + ti,companion-oldi: false + +required: + - reg + - clocks + - clock-names + - ti,oldi-io-ctrl + - ports + +additionalProperties: false + +examples: + - | + #include + + oldi-transmitters { + #address-cells = <1>; + #size-cells = <0>; + oldi: oldi@0 { + reg = <0>; + clocks = <&k3_clks 186 0>; + clock-names = "serial"; + ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + oldi_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + port@1 { + reg = <1>; + oldi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml v_kernel/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml --- linux-6.12.57/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml 2026-04-21 11:35:24.901905717 +0200 @@ -12,19 +12,32 @@ - Tomi Valkeinen description: | - The AM625 and AM65x TI Keystone Display SubSystem with two output + The AM625 and AM65x TI Keystone Display SubSystem has two output ports and two video planes. In AM65x DSS, the first video port supports 1 OLDI TX and in AM625 DSS, the first video port output is internally routed to 2 OLDI TXes. The second video port supports DPI format. The first plane is full video plane with all features and the second is a "lite plane" without scaling support. + The AM62A7 display subsystem has a single output port supporting DPI format + although similar to AM625 and AM65x Socs, it has two video planes where first + is full video plane with all features and second is a video "lite" plane which + does not support scaling. + The AM62L display subsystem also has a single output port which supports DPI + format but it only supports single video "lite plane" which does not support + scaling. The output port is routed to SoC boundary via DPI interface and same + DPI signals are also routed internally to DSI Tx controller present within the + SoC. Due to clocking limitations only one of the interface i.e. either DSI or + DPI can be used at once. properties: compatible: enum: - ti,am625-dss - - ti,am62a7,dss + - ti,am62a7-dss + - ti,am62p51-dss + - ti,am62p52-dss - ti,am65x-dss + - ti,am62l-dss reg: description: @@ -74,7 +87,8 @@ maxItems: 1 power-domains: - maxItems: 1 + minItems: 1 + maxItems: 3 description: phandle to the associated power domain dma-coherent: @@ -88,14 +102,37 @@ $ref: /schemas/graph.yaml#/properties/port description: For AM65x DSS, the OLDI output port node from video port 1. - For AM625 DSS, the internal DPI output port node from video - port 1. + For AM625, and AM62P5-1/2 DSS, the internal DPI output port + node from video port 1. For AM62A7 DSS, the port is tied off inside the SoC. + For AM62L DSS, the DSS DPI output port node from video port 1 + or DSI Tx controller node connected to video port 1. + + properties: + endpoint@0: + $ref: /schemas/graph.yaml#/properties/endpoint + description: + For AM625/AM62P5-1 DSS, VP Connection to OLDI0. + For AM62P5-2 DSS, VP Connection to OLDI1 or the DPI pipe. + For AM65X DSS, OLDI output from the SoC. + + endpoint@1: + $ref: /schemas/graph.yaml#/properties/endpoint + description: + For AM625/AM62P5-1 DSS, VP Connection to OLDI1. + + anyOf: + - required: + - endpoint + - required: + - endpoint@0 + - endpoint@1 port@1: $ref: /schemas/graph.yaml#/properties/port description: - The DSS DPI output port node from video port 2 + The DSS DPI output port node from video port 2. + For AM62P5-2 DSS, VP Connection to DSI Tx or the DPI pipe. ti,am65x-oldi-io-ctrl: $ref: /schemas/types.yaml#/definitions/phandle @@ -106,12 +143,38 @@ and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI interface to work. + ti,clk-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to syscon device node mapping CFG0_CLK_CTRL registers. + This property is needed for proper data sampling edge. + max-memory-bandwidth: $ref: /schemas/types.yaml#/definitions/uint32 description: Input memory (from main memory to dispc) bandwidth limit in bytes per second + oldi-transmitters: + description: + Child node under the DSS, to describe all the OLDI transmitters connected + to the DSS videoports. + type: object + additionalProperties: false + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + '^oldi@[0-1]$': + type: object + $ref: ti,am625-oldi.yaml# + unevaluatedProperties: false + description: OLDI transmitters connected to the DSS VPs + allOf: - if: properties: @@ -123,6 +186,32 @@ ports: properties: port@0: false + oldi-transmitters: false + + - if: + properties: + compatible: + contains: + enum: + - ti,am65x-dss + - ti,am62p52-dss + then: + properties: + oldi-transmitters: false + port@0: + properties: + endpoint@1: false + + - if: + properties: + compatible: + contains: + const: ti,am62l-dss + then: + properties: + ports: + properties: + port@1: false required: - compatible @@ -142,32 +231,134 @@ #include dss: dss@4a00000 { - compatible = "ti,am65x-dss"; - reg = <0x04a00000 0x1000>, /* common */ - <0x04a02000 0x1000>, /* vidl1 */ - <0x04a06000 0x1000>, /* vid */ - <0x04a07000 0x1000>, /* ovr1 */ - <0x04a08000 0x1000>, /* ovr2 */ - <0x04a0a000 0x1000>, /* vp1 */ - <0x04a0b000 0x1000>, /* vp2 */ - <0x04a01000 0x1000>; /* common1 */ + compatible = "ti,am65x-dss"; + reg = <0x04a00000 0x1000>, /* common */ + <0x04a02000 0x1000>, /* vidl1 */ + <0x04a06000 0x1000>, /* vid */ + <0x04a07000 0x1000>, /* ovr1 */ + <0x04a08000 0x1000>, /* ovr2 */ + <0x04a0a000 0x1000>, /* vp1 */ + <0x04a0b000 0x1000>, /* vp2 */ + <0x04a01000 0x1000>; /* common1 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2", "common1"; + ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 67 1>, + <&k3_clks 216 1>, + <&k3_clks 67 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = ; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; + }; + }; + + - | + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + dss1: dss@30200000 { + compatible = "ti,am625-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1 */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2 */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2", "common1"; - ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; - power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 67 1>, - <&k3_clks 216 1>, - <&k3_clks 67 2>; + "ovr1", "ovr2", "vp1", "vp2", "common1"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&vp1_clock>, + <&k3_clks 186 2>; clock-names = "fck", "vp1", "vp2"; - interrupts = ; + interrupts = ; + oldi-transmitters { + #address-cells = <1>; + #size-cells = <0>; + oldi0: oldi@0 { + reg = <0>; + clocks = <&k3_clks 186 0>; + clock-names = "serial"; + ti,companion-oldi = <&oldi1>; + ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + oldi0_in: endpoint { + remote-endpoint = <&dpi0_out0>; + }; + }; + port@1 { + reg = <1>; + oldi0_out: endpoint { + remote-endpoint = <&panel_in0>; + }; + }; + }; + }; + oldi1: oldi@1 { + reg = <1>; + clocks = <&k3_clks 186 0>; + clock-names = "serial"; + ti,secondary-oldi; + ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + oldi1_in: endpoint { + remote-endpoint = <&dpi0_out1>; + }; + }; + port@1 { + reg = <1>; + oldi1_out: endpoint { + remote-endpoint = <&panel_in1>; + }; + }; + }; + }; + }; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { #address-cells = <1>; #size-cells = <0>; - port@0 { - reg = <0>; - oldi_out0: endpoint { - remote-endpoint = <&lcd_in0>; - }; + reg = <0>; + dpi0_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&oldi0_in>; + }; + dpi0_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&oldi1_in>; + }; + }; + port@1 { + reg = <1>; + dpi1_out: endpoint { + remote-endpoint = <&hdmi_bridge>; }; + }; }; + }; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml v_kernel/Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml --- linux-6.12.57/Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml 2026-04-21 11:35:24.915905754 +0200 @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024-2025 Texas Instruments Incorporated +# Author: Sai Sree Kartheek Adivi +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/ti/k3-bcdma-v2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 DMSS BCDMA V2 + +maintainers: + - Sai Sree Kartheek Adivi + +description: | + The BCDMA V2 is intended to perform similar functions as the TR + mode channels of K3 UDMA-P. + BCDMA V2 includes block copy channels and Split channels. + + Block copy channels mainly used for memory to memory transfers, but with + optional triggers a block copy channel can service peripherals by accessing + directly to memory mapped registers or area. + + Split channels can be used to service PSI-L based peripherals. + The peripherals can be PSI-L native or legacy, non PSI-L native peripherals + with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the + legacy peripheral. + +allOf: + - $ref: /schemas/dma/dma-controller.yaml# + +properties: + compatible: + const: ti,am62l-dmss-bcdma + + reg: + items: + - description: BCDMA Control /Status Registers region + - description: Block Copy Channel Realtime Registers region + - description: Channel Realtime Registers region + - description: Ring Realtime Registers region + + reg-names: + items: + - const: gcfg + - const: bchanrt + - const: chanrt + - const: ringrt + + "#dma-cells": + const: 4 + description: | + cell 1: Trigger type for the channel + 0 - disable / no trigger + 1 - internal channel event + 2 - external signal + 3 - timer manager event + + cell 2: parameter for the trigger: + if cell 1 is 0 (disable / no trigger): + Unused, ignored + if cell 1 is 1 (internal channel event): + channel number whose TR event should trigger the current channel. + if cell 1 is 2 or 3 (external signal or timer manager event): + index of global interfaces that come into the DMA. + + Please refer to the device documentation for global interface indexes. + + cell 3: Channel number for the peripheral + + Please refer to the device documentation for the channel map. + + cell 4: ASEL value for the channel + +required: + - compatible + - "#dma-cells" + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - |+ + cbass_main { + #address-cells = <2>; + #size-cells = <2>; + + main_bcdma: dma-controller@485c4000 { + compatible = "ti,am62l-dmss-bcdma"; + reg = <0x00 0x485c4000 0x00 0x4000>, + <0x00 0x48880000 0x00 0x10000>, + <0x00 0x48800000 0x00 0x80000>, + <0x00 0x47000000 0x00 0x200000>; + reg-names = "gcfg", "bchanrt", "chanrt", "ringrt"; + #dma-cells = <4>; + }; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml v_kernel/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml --- linux-6.12.57/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml 2026-04-21 11:35:24.915905754 +0200 @@ -34,6 +34,7 @@ - ti,am62a-dmss-bcdma-csirx - ti,am64-dmss-bcdma - ti,j721s2-dmss-bcdma-csi + - ti,j722s-dmss-bcdma-csi reg: minItems: 3 @@ -196,7 +197,9 @@ properties: compatible: contains: - const: ti,j721s2-dmss-bcdma-csi + enum: + - ti,j721s2-dmss-bcdma-csi + - ti,j722s-dmss-bcdma-csi then: properties: ti,sci-rm-range-bchan: false diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/dma/ti/k3-pktdma-v2.yaml v_kernel/Documentation/devicetree/bindings/dma/ti/k3-pktdma-v2.yaml --- linux-6.12.57/Documentation/devicetree/bindings/dma/ti/k3-pktdma-v2.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/dma/ti/k3-pktdma-v2.yaml 2026-04-21 11:35:24.915905754 +0200 @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024-2025 Texas Instruments Incorporated +# Author: Sai Sree Kartheek Adivi +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/ti/k3-pktdma-v2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 DMSS PKTDMA V2 + +maintainers: + - Sai Sree Kartheek Adivi + +description: | + The PKTDMA V2 is intended to perform similar functions as the packet + mode channels of K3 UDMA-P. + PKTDMA V2 only includes Split channels to service PSI-L based peripherals. + + The peripherals can be PSI-L native or legacy, non PSI-L native peripherals + with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the + legacy peripheral. + +allOf: + - $ref: /schemas/dma/dma-controller.yaml# + +properties: + compatible: + const: ti,am62l-dmss-pktdma + + "#dma-cells": + const: 2 + description: | + cell 1: Channel number for the peripheral + + Please refer to the device documentation for the channel map. + + cell 2: ASEL value for the channel + + reg: + items: + - description: Packet DMA Control /Status Registers region + - description: Channel Realtime Registers region + - description: Ring Realtime Registers region + + reg-names: + items: + - const: gcfg + - const: chanrt + - const: ringrt + +required: + - compatible + - "#dma-cells" + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - |+ + cbass_main { + #address-cells = <2>; + #size-cells = <2>; + + main_pktdma: dma-controller@485c0000 { + compatible = "ti,am62l-dmss-pktdma"; + reg = <0x00 0x485c0000 0x00 0x4000>, + <0x00 0x48900000 0x00 0x80000>, + <0x00 0x47200000 0x00 0x100000>; + reg-names = "gcfg", "chanrt", "ringrt"; + #dma-cells = <2>; + }; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/gpu/ti,rogue.yaml v_kernel/Documentation/devicetree/bindings/gpu/ti,rogue.yaml --- linux-6.12.57/Documentation/devicetree/bindings/gpu/ti,rogue.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/gpu/ti,rogue.yaml 2026-04-21 11:35:24.949905843 +0200 @@ -0,0 +1,191 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/ti,rogue.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments PowerVR Rogue GPU + +description: | + PowerVR Rogue is a family of 3D graphics processing units from Imagination + Technologies. Texas Instruments SoCs have integrated different generations of + PowerVR GPUs and this binding describes the GPU's integrated in Texas + Instruments SoCs in the K3 generation. + +maintainers: + - Darren Etheridge + - Randolph Sapp + - Antonios Christidis + +properties: + $nodename: + pattern: '^gpu@[a-f0-9]+$' + + compatible: + oneOf: + - items: + - enum: + - ti,j721s2-pvr + - const: img,pvr-bxs64 + - items: + - enum: + - ti,j721e-pvr + - const: img,pvr-ge8430 + - items: + - enum: + - ti,am62p-pvr + - const: img,pvr-bxs64 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + power-domains: + minItems: 1 + maxItems: 2 + + power-domain-names: + maxItems: 2 + + assigned-clocks: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + description: | + Allows users to override the default clock value used for the GPU. + Currently ignored on devices other than ti,am62p-pvr. This will be ported + to other devices soon. + +required: + - compatible + - reg + - interrupts + - power-domains + - clocks + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - ti,am62p-pvr + - ti,j721e-pvr + - ti,j721s2-pvr + then: + required: + - power-domain-names + - assigned-clocks + - clock-names + properties: + reg: + minItems: 1 + interrupts: + minItems: 1 + clocks: + minItems: 1 + clock-names: + items: + - const: core + power-domains: + minItems: 2 + power-domain-names: + items: + - const: firmware + - const: dust + assigned-clocks: + minItems: 1 + assigned-clock-rates: + default: [800000000] + else: + properties: + assigned-clocks: false + assigned-clock-rates: false + - if: + properties: + compatible: + contains: + enum: + - ti,j721e-pvr + then: + properties: + assigned-clock-rates: + default: [750000000] + +examples: + - | + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + gpu@4e20000000 { + compatible = "ti,j721s2-pvr", "img,pvr-bxs64"; + reg = <0x4e 0x20000000 0x00 0x80000>; + interrupts = ; + power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>; + power-domain-names = "firmware", "dust"; + clocks = <&k3_clks 130 1>; + assigned-clocks = <&k3_clks 130 1>; + assigned-clock-rates = <800000000>; + clock-names = "core"; + }; + }; + + - | + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + gpu@4e20000000 { + compatible = "ti,j721e-pvr", "img,pvr-ge8430"; + reg = <0x4e 0x20000000 0x00 0x80000>; + interrupts = ; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + power-domain-names = "firmware", "dust"; + clocks = <&k3_clks 125 0>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-rates = <750000000>; + clock-names = "core"; + }; + }; + + - | + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + gpu@fd80000 { + compatible = "ti,am62p-pvr", "img,pvr-bxs64"; + reg = <0x00 0x0fd80000 0x00 0x80000>; + interrupts = ; + power-domains = <&k3_pds 237 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 237 3>; + assigned-clock-rates = <720000000>; + power-domain-names = "firmware", "dust"; + clocks = <&k3_clks 237 3>; + clock-names = "core"; + }; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml v_kernel/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml --- linux-6.12.57/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml 2026-04-21 11:35:24.950905845 +0200 @@ -24,7 +24,7 @@ - const: ti,am654-chipid reg: - maxItems: 1 + minItems: 1 required: - compatible @@ -36,5 +36,6 @@ - | chipid@43000014 { compatible = "ti,am654-chipid"; - reg = <0x43000014 0x4>; + reg = <0x43000014 0x4>, + <0x43000230 0x10>; }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml v_kernel/Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml --- linux-6.12.57/Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml 2026-04-21 11:35:24.976905914 +0200 @@ -47,6 +47,11 @@ $ref: /schemas/types.yaml#/definitions/string deprecated: true + mux-states: + description: + mux controller node to route the I2C signals form SoC to clients. + maxItems: 1 + required: - compatible - reg diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml v_kernel/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml --- linux-6.12.57/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml 2026-04-21 11:35:25.106906255 +0200 @@ -24,6 +24,14 @@ reg: maxItems: 1 + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: error_irq + - const: irq + clocks: items: - description: CSI2Rx system clock diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/media/i2c/ovti,ov1063x.yaml v_kernel/Documentation/devicetree/bindings/media/i2c/ovti,ov1063x.yaml --- linux-6.12.57/Documentation/devicetree/bindings/media/i2c/ovti,ov1063x.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/media/i2c/ovti,ov1063x.yaml 2026-04-21 11:35:25.114906276 +0200 @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov1063x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OmniVision OV10633/OV10635 8/10 bit digital Camera Sensor + +maintainers: + - Benoit Parrot + - Sukrut Bellary + + +description: |- + The OmniVision OV1063x is a 720p(HD) camera sensor which supports resolutions + up to 1280x800(WXGA) and 8/10-bit YUV output formats. + + Each camera nodes should contain a 'port' child node with child + 'endpoint' node. Please refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.yaml. + +properties: + compatible: + enum: + - ovti,ov10633 + - ovti,ov10635 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xvclk + + reset-gpios: + maxItems: 1 + description: + phandle to the GPIO connected to the RESETB pin, if any. + + powerdown-gpios: + maxItems: 1 + description: + phandle for the GPIO connected to the PWDN pin, if any. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + hsync-active: true + vsync-active: true + pclk-sample: true + bus-width: + enum: [ 8, 10 ] + +required: + - compatible + - reg + - clocks + - clock-names + - port + +additionalProperties: false + +examples: + - | + #include + + i2c { + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + camera@30 { + compatible = "ovti,ov10635"; + reg = <0x30>; + + clocks = <&fixed_clock>; + clock-names = "xvclk"; + + reset-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; + + port { + camera1: endpoint { + remote-endpoint = <&vin1a_ep>; + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + bus-width = <8>; + }; + }; + }; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/media/i2c/ovti,ox05b.yaml v_kernel/Documentation/devicetree/bindings/media/i2c/ovti,ox05b.yaml --- linux-6.12.57/Documentation/devicetree/bindings/media/i2c/ovti,ox05b.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/media/i2c/ovti,ox05b.yaml 2026-04-21 11:35:25.117906284 +0200 @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ox05b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OmniVision OX05B1S Camera Sensor + +maintainers: + - Abhishek Sharma + +description: |- + Omnivision OX05B1S is an RGBIR camera sensor with an active array size of + 2592x1944. It is programmable through the I2C interface. The i2c client + address is fixed at 0x36 as per the sensor datasheet. Every alternate frame, + the sensor changes the exposure/gain registers to stream an - + A. IR-dominant frame on CSI-2 virtual channel 0 + B. RGB-dominant frame on CSI-2 virtual channel 1 + + Both streams are captured at a resolution 2592x1944, 30 fps each + (60 fps total). The sensor also supports a few v4l2 controls like + exposure and gain controls. + +properties: + compatible: + enum: + - ovti,ox05b + + reg: + description: I2C address + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: inck + + pwdn-gpios: + maxItems: 1 + description: + Specifier for the GPIO connected to the PWDN pin. + + port: + $ref: /schemas/graph.yaml#/properties/port + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - port + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ox05b1s: camera@36 { + compatible = "ovti,ox05b"; + reg = <0x36>; + + clocks = <&clk_ox05b1s_fixed>; + clock-names = "inck"; + + pwdn-gpios = <&exp1 13 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + }; + }; + }; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml v_kernel/Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml --- linux-6.12.57/Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml 2026-04-21 11:35:25.119906289 +0200 @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/sony,imx728.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony IMX728 Camera Sensor + +maintainers: + - Stuart Burtner + +description: + The Sony IMX728 is a 1/1.72-Inch CMOS Solid-state image sensor with a + color square pixel array and 8.39M active pixels. It is programmed + through an I2C interface. + + The sensor can output up to 3840x2160 at a maximum of 45 frames/s over + a CSI-2 serial interface. It supports RAW24/20/16/12 and 10. + +properties: + compatible: + enum: + - sony,imx728 + + reg: + maxItems: 1 + + clocks: + description: Clock frequency from 18 to 30MHz + maxItems: 1 + + clock-names: + const: inck + + reset-gpios: + maxItems: 1 + description: + XCLR (System Reset) pin. + + error0-gpios: + maxItems: 1 + description: + XWRN pin. + + error1-gpios: + maxItems: 1 + description: + XERR pin. + + port: + $ref: /schemas/graph.yaml#/properties/port + additionalProperties: false + + properties: + endpoint: + $ref: ../video-interfaces.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - port + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera@1a { + compatible = "sony,imx728"; + reg = <0x1a>; + + clocks = <&fixed_clock>; + clock-names = "inck"; + + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + error0-gpios = <&sens_exp 1 GPIO_ACTIVE_HIGH>; + error1-gpios = <&sens_exp 2 GPIO_ACTIVE_HIGH>; + + port { + camera1: endpoint { + remote-endpoint = <&vin1a_ep>; + }; + }; + }; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml v_kernel/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml --- linux-6.12.57/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml 2026-04-21 11:35:25.121906294 +0200 @@ -19,6 +19,7 @@ properties: compatible: enum: + - ti,ds90ub954-q1 - ti,ds90ub960-q1 - ti,ds90ub9702-q1 diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml v_kernel/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml --- linux-6.12.57/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml 2026-04-21 11:35:25.137906336 +0200 @@ -20,11 +20,44 @@ const: ti,j721e-csi2rx-shim dmas: - maxItems: 1 + minItems: 1 + maxItems: 32 dma-names: + minItems: 1 items: - const: rx0 + - const: rx1 + - const: rx2 + - const: rx3 + - const: rx4 + - const: rx5 + - const: rx6 + - const: rx7 + - const: rx8 + - const: rx9 + - const: rx10 + - const: rx11 + - const: rx12 + - const: rx13 + - const: rx14 + - const: rx15 + - const: rx16 + - const: rx17 + - const: rx18 + - const: rx19 + - const: rx20 + - const: rx21 + - const: rx22 + - const: rx23 + - const: rx24 + - const: rx25 + - const: rx26 + - const: rx27 + - const: rx28 + - const: rx29 + - const: rx30 + - const: rx31 reg: maxItems: 1 @@ -62,8 +95,8 @@ ti_csi2rx0: ticsi2rx@4500000 { compatible = "ti,j721e-csi2rx-shim"; - dmas = <&main_udmap 0x4940>; - dma-names = "rx0"; + dmas = <&main_udmap 0x4940>, <&main_udmap 0x4941>; + dma-names = "rx0", "rx1"; reg = <0x4500000 0x1000>; power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/media/ti,vip.yaml v_kernel/Documentation/devicetree/bindings/media/ti,vip.yaml --- linux-6.12.57/Documentation/devicetree/bindings/media/ti,vip.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/media/ti,vip.yaml 2026-04-21 11:35:25.138906339 +0200 @@ -0,0 +1,311 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/ti,vip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DRA7x VIDEO INPUT PORT (VIP). + +maintainers: + - Yemike Abhilash Chandra + +description: |- + The Video Input Port (VIP) is a key component for image capture + applications. The capture module provides the system interface and the + processing capability to connect parallel image-sensor as well as + BT.656/1120 capable encoder chip to DRA7x device. + + Each VIP instance supports 2 independently configurable external video + input capture slices (Slice 0 and Slice 1) each providing up to two video + input ports (Port A and Port B) where Port A can be configured as + 24/16/8-bit port and Port B is fixed as 8-bit port. + Here these ports a represented as follows + port@0 -> Slice 0 Port A + port@1 -> Slice 0 Port B + port@2 -> Slice 1 Port A + port@3 -> Slice 1 Port B + + Each camera port nodes should contain a 'port' child node with child + 'endpoint' node. Please refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.yaml. + +properties: + compatible: + enum: + - ti,dra7-vip + + label: + description: Instance name + + reg: + items: + - description: The VIP main register region + - description: Video Data Parser (PARSER) register region for Slice0 + - description: Color Space Conversion (CSC) register region for Slice0 + - description: Scaler (SC) register region for Slice0 + - description: Video Data Parser (PARSER) register region for Slice1 + - description: Color Space Conversion (CSC) register region for Slice1 + - description: Scaler (SC) register region for Slice1 + - description: Video Port Direct Memory Access (VPDMA) register region + + reg-names: + items: + - const: vip + - const: parser0 + - const: csc0 + - const: sc0 + - const: parser1 + - const: csc1 + - const: sc1 + - const: vpdma + + interrupts: + minItems: 2 + description: + IRQ index 0 is used for Slice0 interrupts + IRQ index 1 is used for Slice1 interrupts + + ti,vip-clk-polarity: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + phandle to the device control module. The 1st argument should + contain the register offset to the CTRL_CORE_SMA_SW_1 register. + 2nd argument contains the bit field to slice 0 port A, + 3rd argument contains the bit field to slice 0 port B, + 4th argument contains the bit field to slice 1 port A, + 5th argument contains the bit field to slice 1 port B. + + ports: + type: object + additionalProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + additionalProperties: false + + properties: + reg: + const: 0 + description: Slice 0 Port A + + label: + description: Port name. Usually the pin group name + + endpoint: + $ref: video-interfaces.yaml# + type: object + unevaluatedProperties: false + + properties: + hsync-active: true + vsync-active: true + pclk-sample: true + bus-width: + enum: [8, 24] + default: 8 + + remote-endpoint: true + + required: + - reg + - label + + port@1: + type: object + additionalProperties: false + + properties: + reg: + const: 1 + description: Slice 0 Port B + + label: + description: Port name. Usually the pin group name + + endpoint: + $ref: /schemas/graph.yaml#/properties/endpoint + type: object + additionalProperties: false + + properties: + hsync-active: true + vsync-active: true + pclk-sample: true + bus-width: + enum: [8, 24] + default: 8 + + remote-endpoint: true + + required: + - reg + - label + + port@2: + type: object + additionalProperties: false + + properties: + reg: + const: 2 + description: Slice 1 Port A + + label: + description: Port name. Usually the pin group name + + endpoint: + $ref: /schemas/graph.yaml#/properties/endpoint + type: object + additionalProperties: false + + properties: + hsync-active: true + vsync-active: true + pclk-sample: true + bus-width: + enum: [8, 24] + default: 8 + + remote-endpoint: true + + required: + - reg + - label + + port@3: + type: object + additionalProperties: false + + properties: + reg: + const: 3 + description: Slice 1 Port B + + label: + description: Port name. Usually the pin group name + + endpoint: + $ref: /schemas/graph.yaml#/properties/endpoint + type: object + additionalProperties: false + + properties: + hsync-active: true + vsync-active: true + pclk-sample: true + bus-width: + enum: [8, 24] + default: 8 + + remote-endpoint: true + + required: + - reg + - label + + required: + - "#address-cells" + - "#size-cells" + - port@0 + +required: + - compatible + - label + - reg + - reg-names + - interrupts + - ti,vip-clk-polarity + +additionalProperties: false + +examples: + - | + #include + + vip1: vip@48970000 { + compatible = "ti,dra7-vip1"; + label = "vip1"; + reg = <0x48970000 0x114>, + <0x48975500 0xD8>, + <0x48975700 0x18>, + <0x48975800 0x80>, + <0x48975a00 0xD8>, + <0x48975c00 0x18>, + <0x48975d00 0x80>, + <0x4897d000 0x400>; + reg-names = "vip", + "parser0", + "csc0", + "sc0", + "parser1", + "csc1", + "sc1", + "vpdma"; + interrupts = , + ; + ti,vip-clk-polarity = <&scm_conf 0x534 0x1 0x4 0x2 0x8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + vin1a: port@0 { + reg = <0>; + label = "vin1a"; + + vin1a_ep: endpoint { + remote-endpoint = <&camera1>; + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + bus-width = <8>; + }; + }; + vin1b: port@1 { + reg = <1>; + label = "vin1b"; + }; + vin2a: port@2 { + reg = <2>; + label = "vin2a"; + }; + vin2b: port@3 { + reg = <3>; + label = "vin2b"; + }; + }; + }; + + i2c { + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + camera@37 { + compatible = "ovti,ov10633"; + reg = <0x37>; + + clocks = <&fixed_clock>; + clocks-names = "xvclk"; + + port { + camera1: endpoint { + remote-endpoint = <&vin1a_ep>; + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + bus-width = <8>; + }; + }; + }; + }; + +... diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/memory-controllers/ti/cdns,j7-ddr.yaml v_kernel/Documentation/devicetree/bindings/memory-controllers/ti/cdns,j7-ddr.yaml --- linux-6.12.57/Documentation/devicetree/bindings/memory-controllers/ti/cdns,j7-ddr.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/memory-controllers/ti/cdns,j7-ddr.yaml 2026-04-21 11:35:25.150906370 +0200 @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ti/cdns,j7-ddr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence DDR controller for K3 devices + +maintainers: + - Gandhar Deshpande + - Santhosh Kumar K + - Neha Malcom Francis + +properties: + compatible: + const: cdns,j7-ddr + + reg: + minItems: 3 + maxItems: 3 + description: | + Address ranges for the different register regions of the DDRSS controller. + - ctl_cfg: Controller configuration registers + - ctl_cfg_pi: PHY Interface configuration registers + - ctl_cfg_phy: PHY configuration registers + + reg-names: + items: + - const: ctl_cfg + - const: ctl_cfg_pi + - const: ctl_cfg_phy + + ti,ctl-data: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Array of controller register values for DDR initialization. + These values configure the DDR controller parameters. + + ti,pi-data: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Array of PHY Interface register values for DDR initialization. + These values configure the interface between controller and PHY. + + ti,phy-data: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Array of PHY register values for DDR initialization. + These values configure the DDR PHY parameters. + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + cbass_main { + #address-cells = <2>; + #size-cells = <2>; + + memorycontroller: memory-controller@298e000 { + compatible = "ti,j7-ddrss"; + reg = <0x00 0x02980000 0x00 0x184>; + reg-names = "ss_cfg"; + ranges = <0x00 0x00 0x00 0x02990000 0x00 0x00004000>; + interrupts = ; + power-domains = <&k3_pds 8 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 90 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 8 0>, <&k3_clks 30 9>; + bootph-pre-ram; + ti,ddr-freq1 = <0x27b9fba0>; + ti,ddr-freq2 = <0x27b9fba0>; + ti,ddr-fhs-cnt = <0xa>; + #address-cells = <2>; + #size-cells = <2>; + + ddr@0 { + compatible = "cdns,j7-ddr"; + reg = <0x00 0x0000 0x00 0x72c>, + <0x00 0x2000 0x00 0x4b0>, + <0x00 0x4000 0x00 0x163c>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + bootph-pre-ram; + + ti,ctl-data = < + 0xb00 + 0x0 + 0x0 + >; + + ti,pi-data = < + 0xb00 + 0x0 + 0x0 + >; + + ti,phy-data = < + 0x4f0 + 0x0 + 0x30200 + >; + }; + }; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/memory-controllers/ti/ti,j7-ddrss.yaml v_kernel/Documentation/devicetree/bindings/memory-controllers/ti/ti,j7-ddrss.yaml --- linux-6.12.57/Documentation/devicetree/bindings/memory-controllers/ti/ti,j7-ddrss.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/memory-controllers/ti/ti,j7-ddrss.yaml 2026-04-21 11:35:25.150906370 +0200 @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ti/ti,j7-ddrss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI wrapper module for the Cadence DDRSS controller + +maintainers: + - Gandhar Deshpande + - Santhosh Kumar K + - Neha Malcom Francis + +description: | + The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper + logic to integrate these blocks in the device. The DDR subsystem is + used to provide an interface to external SDRAM devices which can be + utilized for storing program or data. + +properties: + compatible: + enum: + - ti,j7-ddrss + - ti,am62-ddrss + - ti,am62a-ddrss + + reg: + minItems: 1 + maxItems: 2 + description: | + Address ranges for the different register regions of the DDRSS controller. + - ss_cfg: Subsystem configuration registers + + reg-names: + items: + - const: ss_cfg + + ranges: + minItems: 1 + + interrupts: + maxItems: 1 + description: | + Interrupt line for the DDR subsystem controller. This interrupt is + typically used for temperature monitoring and error reporting. + + power-domains: + minItems: 1 + maxItems: 2 + description: | + Power domains required by the DDR subsystem: + - an entry to TISCI DDR CFG device + - an entry to TISCI DDR DATA. + + clocks: + minItems: 1 + maxItems: 2 + description: | + - An entry to DDRSS clock + - An entry to SoC bypass clock + + ti,ddr-freq1: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Primary DDR frequency setting in Hz. This value is used for + normal operation of the DDR subsystem. + + ti,ddr-freq2: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Secondary DDR frequency setting in Hz. This value can be used + for power saving or performance modes. + + ti,ddr-fhs-cnt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Frequency handover sequence count. This value defines how many + steps to use when switching between frequency settings. + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + +patternProperties: + "^ddr@": + type: object + +required: + - compatible + - reg + - reg-names + - ranges + - interrupts + - power-domains + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + cbass_main { + #address-cells = <2>; + #size-cells = <2>; + + memorycontroller: memory-controller@298e000 { + compatible = "ti,j7-ddrss"; + reg = <0x00 0x02980000 0x00 0x184>; + reg-names = "ss_cfg"; + ranges = <0x00 0x00 0x00 0x02990000 0x00 0x00004000>; + interrupts = ; + power-domains = <&k3_pds 8 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 90 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 8 0>, <&k3_clks 30 9>; + bootph-pre-ram; + ti,ddr-freq1 = <0x27b9fba0>; + ti,ddr-freq2 = <0x27b9fba0>; + ti,ddr-fhs-cnt = <0xa>; + #address-cells = <2>; + #size-cells = <2>; + + ddr@0 { + compatible = "cdns,j7-ddr"; + reg = <0x00 0x0000 0x00 0x72c>, + <0x00 0x2000 0x00 0x4b0>, + <0x00 0x4000 0x00 0x163c>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + bootph-pre-ram; + + ti,ctl-data = < + 0xb00 + 0x0 + 0x0 + >; + + ti,pi-data = < + 0xb00 + 0x0 + 0x0 + >; + + ti,phy-data = < + 0x4f0 + 0x0 + 0x30200 + >; + }; + }; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/mfd/syscon.yaml v_kernel/Documentation/devicetree/bindings/mfd/syscon.yaml --- linux-6.12.57/Documentation/devicetree/bindings/mfd/syscon.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/mfd/syscon.yaml 2026-04-21 11:35:25.171906425 +0200 @@ -109,9 +109,12 @@ - st,spear1340-misc - stericsson,nomadik-pmu - starfive,jh7100-sysmain + - ti,am62-canuart-wake + - ti,am62-ddr-pmctrl - ti,am62-opp-efuse-table - ti,am62-usb-phy-ctrl - ti,am625-dss-oldi-io-ctrl + - ti,am625-dss-clk-ctrl - ti,am62p-cpsw-mac-efuse - ti,am654-dss-oldi-io-ctrl - ti,j784s4-acspcie-proxy-ctrl @@ -206,9 +209,12 @@ - st,spear1340-misc - stericsson,nomadik-pmu - starfive,jh7100-sysmain + - ti,am62-canuart-wake + - ti,am62-ddr-pmctrl - ti,am62-opp-efuse-table - ti,am62-usb-phy-ctrl - ti,am625-dss-oldi-io-ctrl + - ti,am625-dss-clk-ctrl - ti,am62p-cpsw-mac-efuse - ti,am654-dss-oldi-io-ctrl - ti,j784s4-pcie-ctrl @@ -236,4 +242,3 @@ compatible = "allwinner,sun8i-h3-system-controller", "syscon"; reg = <0x01c00000 0x1000>; }; -... diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/mux/reg-mux.yaml v_kernel/Documentation/devicetree/bindings/mux/reg-mux.yaml --- linux-6.12.57/Documentation/devicetree/bindings/mux/reg-mux.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/mux/reg-mux.yaml 2026-04-21 11:35:25.207906519 +0200 @@ -32,11 +32,34 @@ - description: pre-shifted bitfield mask description: Each entry pair describes a single mux control. - idle-states: true + idle-states: + description: Each entry describes mux register state. + + mux-reg-masks-state: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: register offset + - description: pre-shifted bitfield mask + - description: register value to be set + description: This property is an extension of mux-reg-masks which + allows specifying register offset, mask and register + value to be set in a single property. + +oneOf: + - required: [ mux-reg-masks ] + - required: [ mux-reg-masks-state ] + +allOf: + - if: + required: + - mux-reg-masks-state + then: + properties: + idle-states: false required: - compatible - - mux-reg-masks - '#mux-control-cells' additionalProperties: false diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml v_kernel/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml --- linux-6.12.57/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml 2026-04-21 11:35:25.217906546 +0200 @@ -106,6 +106,22 @@ maximum: 32 minItems: 1 + pinctrl-0: + description: Default pinctrl state + + pinctrl-1: + description: Wakeup pinctrl state + + pinctrl-names: + description: + When present should contain at least "default" describing the default pin + states. The second state called "wakeup" describes the pins in their + wakeup configuration required to exit sleep states. + minItems: 1 + items: + - const: default + - const: wakeup + power-domains: description: Power domain provider node and an args specifier containing @@ -122,6 +138,17 @@ minItems: 1 maxItems: 2 + wakeup-source: + oneOf: + - description: This device is capable of wakeup. + type: boolean + - description: This device is capable of wakeup from the defined power + states. + $ref: /schemas/types.yaml#/definitions/string-array + enum: + - suspend + - poweroff + required: - compatible - reg diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/net/ti,icss-iep.yaml v_kernel/Documentation/devicetree/bindings/net/ti,icss-iep.yaml --- linux-6.12.57/Documentation/devicetree/bindings/net/ti,icss-iep.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/net/ti,icss-iep.yaml 2026-04-21 11:35:25.256906648 +0200 @@ -8,6 +8,8 @@ maintainers: - Md Danish Anwar + - Parvathi Pudi + - Basharath Hussain Khaja properties: compatible: @@ -17,9 +19,11 @@ - ti,am642-icss-iep - ti,j721e-icss-iep - const: ti,am654-icss-iep - - - const: ti,am654-icss-iep - + - enum: + - ti,am654-icss-iep + - ti,am5728-icss-iep + - ti,am4376-icss-iep + - ti,am3356-icss-iep reg: maxItems: 1 diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml v_kernel/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml --- linux-6.12.57/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml 2026-04-21 11:35:25.257906651 +0200 @@ -0,0 +1,233 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,icssm-prueth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments ICSSM PRUSS Ethernet + +maintainers: + - Roger Quadros + - Andrew F. Davis + - Parvathi Pudi + - Basharath Hussain Khaja + +description: + Ethernet based on the Programmable Real-Time Unit and Industrial + Communication Subsystem. + +properties: + compatible: + enum: + - ti,am57-prueth # for AM57x SoC family + - ti,am4376-prueth # for AM43x SoC family + - ti,am3359-prueth # for AM33x SoC family + + sram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to OCMC SRAM node + + ti,mii-rt: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the MII_RT peripheral for ICSS + + ti,iep: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to IEP (Industrial Ethernet Peripheral) for ICSS + + ti,ecap: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to Enhanced Capture (eCAP) event for ICSS + + interrupts: + items: + - description: High priority Rx Interrupt specifier. + - description: Low priority Rx Interrupt specifier. + + interrupt-names: + items: + - const: rx_hp + - const: rx_lp + + ethernet-ports: + type: object + additionalProperties: false + + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + ^ethernet-port@[0-1]$: + type: object + description: ICSSM PRUETH external ports + $ref: ethernet-controller.yaml# + unevaluatedProperties: false + + properties: + reg: + items: + - enum: [0, 1] + description: ICSSM PRUETH port number + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: rx + - const: emac_ptp_tx + - const: hsr_ptp_tx + + required: + - reg + + anyOf: + - required: + - ethernet-port@0 + - required: + - ethernet-port@1 + +required: + - compatible + - sram + - ti,mii-rt + - ti,iep + - ti,ecap + - ethernet-ports + - interrupts + - interrupt-names + +allOf: + - $ref: /schemas/remoteproc/ti,pru-consumer.yaml# + +unevaluatedProperties: false + +examples: + - | + /* Dual-MAC Ethernet application node on PRU-ICSS2 */ + pruss2_eth: pruss2-eth { + compatible = "ti,am57-prueth"; + ti,prus = <&pru2_0>, <&pru2_1>; + sram = <&ocmcram1>; + ti,mii-rt = <&pruss2_mii_rt>; + ti,iep = <&pruss2_iep>; + ti,ecap = <&pruss2_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss2_intc>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss2_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss2_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss2_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss2_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 7>, <24 9 7>; + interrupt-names = "rx", "emac_ptp_tx", "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + - | + /* Dual-MAC Ethernet application node on PRU-ICSS1 */ + pruss1_eth: pruss1-eth { + compatible = "ti,am4376-prueth"; + ti,prus = <&pru1_0>, <&pru1_1>; + sram = <&ocmcram>; + ti,mii-rt = <&pruss1_mii_rt>; + ti,iep = <&pruss1_iep>; + ti,ecap = <&pruss1_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss1_intc>; + + pinctrl-0 = <&pruss1_eth_default>; + pinctrl-names = "default"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss1_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss1_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss1_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss1_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 7>, <24 9 7>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + - | + /* Dual-MAC Ethernet application node on PRU-ICSS */ + pruss_eth: pruss-eth { + compatible = "ti,am3359-prueth"; + ti,prus = <&pru0>, <&pru1>; + sram = <&ocmcram>; + ti,mii-rt = <&pruss_mii_rt>; + ti,iep = <&pruss_iep>; + ti,ecap = <&pruss_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss_intc>; + + pinctrl-0 = <&pruss_eth_default>; + pinctrl-names = "default"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 7>, <24 9 7>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/net/ti,pruss-ecap.yaml v_kernel/Documentation/devicetree/bindings/net/ti,pruss-ecap.yaml --- linux-6.12.57/Documentation/devicetree/bindings/net/ti,pruss-ecap.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/net/ti,pruss-ecap.yaml 2026-04-21 11:35:25.257906651 +0200 @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,pruss-ecap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments PRU-ICSS Enhanced Capture (eCAP) event module + +maintainers: + - Murali Karicheri + - Parvathi Pudi + - Basharath Hussain Khaja + +properties: + compatible: + const: ti,pruss-ecap + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pruss2_ecap: ecap@30000 { + compatible = "ti,pruss-ecap"; + reg = <0x30000 0x60>; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml v_kernel/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml --- linux-6.12.57/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml 2026-04-21 11:35:25.304906774 +0200 @@ -96,7 +96,7 @@ Specifies the type of PHY for which the group of PHY lanes is used. Refer include/dt-bindings/phy/phy.h. Constants from the header should be used. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [2, 4] + enum: [2, 4, 8, 9] cdns,num-lanes: description: diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml v_kernel/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml --- linux-6.12.57/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml 2026-04-21 11:35:25.344906879 +0200 @@ -24,6 +24,7 @@ - items: - enum: - ti,am437-padconf + - ti,am62l-padconf - ti,am654-padconf - ti,dra7-padconf - ti,omap2420-padconf diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml v_kernel/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml --- linux-6.12.57/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml 2026-04-21 11:35:25.424907089 +0200 @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/regulator/ti,tps65219.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: TI tps65219 Power Management Integrated Circuit regulators +title: TI TPS65214/TPS65215/TPS65219 Power Management Integrated Circuit maintainers: - Jerome Neanne @@ -12,9 +12,20 @@ description: | Regulator nodes should be named to buck and ldo. + TI TPS65219 is a Power Management IC with 3 Buck regulators, 4 Low + Drop-out Regulators (LDOs), 1 GPIO, 2 GPOs, and power-button. + + TI TPS65215 is a derivative of TPS65219 with 3 Buck regulators, 2 Low + Drop-out Regulators (LDOs), 1 GPIO, 1 GPO, and power-button. + + TI TPS65214 is a derivative of TPS65219 with 3 Buck regulators, 2 Low + Drop-out Regulators (LDOs), 1 GPIO, 1 GPO, and power-button. + properties: compatible: enum: + - ti,tps65214 + - ti,tps65215 - ti,tps65219 reg: @@ -90,6 +101,28 @@ additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: ti,tps65214 + then: + properties: + regulators: + patternProperties: + "^ldo[3-4]$": false + - if: + properties: + compatible: + contains: + const: ti,tps65215 + then: + properties: + regulators: + patternProperties: + "^ldo[3-4]$": false + examples: - | #include diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml v_kernel/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml --- linux-6.12.57/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml 2026-04-21 11:35:25.433907112 +0200 @@ -29,11 +29,13 @@ compatible: enum: - ti,am62a-c7xv-dsp + - ti,j722s-c7xv-dsp - ti,j721e-c66-dsp - ti,j721e-c71-dsp - ti,j721s2-c71-dsp description: Use "ti,am62a-c7xv-dsp" for AM62A Deep learning DSPs on K3 AM62A SoCs + Use "ti,j722s-c7xv-dsp" for J722S Deep learning DSPs on K3 J722S SoCs Use "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs Use "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs Use "ti,j721s2-c71-dsp" for C71x DSPs on K3 J721S2 SoCs @@ -127,6 +129,7 @@ compatible: enum: - ti,am62a-c7xv-dsp + - ti,j722s-c7xv-dsp then: properties: reg: diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/rtc/ti,k3-rtc.yaml v_kernel/Documentation/devicetree/bindings/rtc/ti,k3-rtc.yaml --- linux-6.12.57/Documentation/devicetree/bindings/rtc/ti,k3-rtc.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/rtc/ti,k3-rtc.yaml 2026-04-21 11:35:25.460907183 +0200 @@ -19,6 +19,7 @@ compatible: enum: - ti,am62-rtc + - ti,am62l-rtc reg: maxItems: 1 diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/serial/8250_omap.yaml v_kernel/Documentation/devicetree/bindings/serial/8250_omap.yaml --- linux-6.12.57/Documentation/devicetree/bindings/serial/8250_omap.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/serial/8250_omap.yaml 2026-04-21 11:35:25.461907186 +0200 @@ -78,6 +78,22 @@ overrun-throttle-ms: true wakeup-source: true + pinctrl-0: + description: Default pinctrl state + + pinctrl-1: + description: Wakeup pinctrl state + + pinctrl-names: + description: + When present should contain at least "default" describing the default pin + states. The second state called "wakeup" describes the pins in their + wakeup configuration required to exit sleep states. + minItems: 1 + items: + - const: default + - const: wakeup + required: - compatible - reg diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/serial/ti,pruss-uart.yaml v_kernel/Documentation/devicetree/bindings/serial/ti,pruss-uart.yaml --- linux-6.12.57/Documentation/devicetree/bindings/serial/ti,pruss-uart.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/serial/ti,pruss-uart.yaml 2026-04-21 11:35:25.469907207 +0200 @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/ti,pruss-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI PRUSS serial UART + +maintainers: + - Bin Liu + +description: | + The PRU-ICSS module has a serial UART peripheral, which is based on + industry standard TL16C550, with 16-bytes TX/RX FIFOs. + +allOf: + - $ref: /schemas/serial.yaml# + +properties: + compatible: + items: + - const: ti,pruss-uart + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + minItems: 3 + maxItems: 3 + description: | + PRU UART interrupt mappings, containing an entry of 3 cell-values. + The first is the PRU System Event id for PRU UART Interrupt Request. + The second is the PRU interrupt channel id. + The third is the PRU host interrupt id. + +required: + - compatible + - reg + - clocks + - interrupt-parent + - interrupts + +examples: + - | + pruss_uart: serial@28000 { + compatible = "ti,pruss-uart"; + reg = <0x28000 0x38>; + clocks = <&dpll_per_m2_ck>; + interrupt-parent = <&pruss_intc>; + interrupts = <6 2 2>; + }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml v_kernel/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml --- linux-6.12.57/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml 2026-04-21 11:35:25.497907280 +0200 @@ -68,6 +68,11 @@ description: The node corresponding to SoC chip identification. + "^pcie-ctrl@[0-9a-f]+$": + type: object + description: + This is the PCIe control region. + required: - compatible - reg diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml v_kernel/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml --- linux-6.12.57/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml 2026-04-21 11:35:25.498907283 +0200 @@ -92,6 +92,16 @@ description: | This property is as per sci-pm-domain.txt. + clocks: + items: + - description: ICSSG_CORE Clock + - description: ICSSG_IEP Clock + - description: ICSSG_RGMII_MHZ_250 Clock + - description: ICSSG_RGMII_MHZ_50 Clock + - description: ICSSG_RGMII_MHZ_5 Clock + - description: ICSSG_UART Clock + - description: ICSSG_ICLK Clock + patternProperties: memories@[a-f0-9]+$: @@ -241,6 +251,15 @@ type: object + ecap@[a-f0-9]+$: + description: + PRU-ICSS has a Enhanced Capture (eCAP) event module which can generate + and capture periodic timer based events which will be used for features + like RX Pacing to rise interrupt when the timer event has occurred. + Each PRU-ICSS instance has one eCAP module irrespective of SOCs. + $ref: /schemas/net/ti,pruss-ecap.yaml# + type: object + mii-rt@[a-f0-9]+$: description: | Real-Time Ethernet to support multiple industrial communication protocols. diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml v_kernel/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml --- linux-6.12.57/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml 2026-04-21 11:35:25.513907322 +0200 @@ -40,11 +40,33 @@ tdm-slots: $ref: /schemas/types.yaml#/definitions/uint32 description: - number of channels over one serializer - the property is ignored in DIT mode + Number of channels over one serializer. This property + specifies the TX playback TDM slot count, along with default RX slot count + if tdm-slots-rx is not specified. + The property is ignored in DIT mode. minimum: 2 maximum: 32 + tdm-slots-rx: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of RX capture channels over one serializer. If specified, + allows independent RX TDM slot count separate from TX. Requires + ti,async-mode to be enabled for independent TX/RX clock rates. + The property is ignored in DIT mode. + minimum: 2 + maximum: 32 + + ti,async-mode: + description: + Specify to allow independent TX & RX clocking, + to enable audio playback & record with different sampling rate, + and different number of bits per frame. + if property is omitted, TX and RX will share same bit clock and frame clock signals, + thus RX need to use same bits per frame and sampling rate as TX in synchronous mode. + the property is ignored in DIT mode (as DIT is TX-only) + type: boolean + serial-dir: description: A list of serializer configuration @@ -125,7 +147,21 @@ auxclk-fs-ratio: $ref: /schemas/types.yaml#/definitions/uint32 - description: ratio of AUCLK and FS rate if applicable + description: + Ratio of AUCLK and FS rate if applicable. This property specifies + the TX ratio, along with default RX ratio if auxclk-fs-ratio-rx + is not specified. + When not specified, the inputted system clock frequency via set_sysclk + callback by the machine driver is used for divider calculation. + + auxclk-fs-ratio-rx: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Ratio of AUCLK and FS rate for RX. If specified, allows + for a different RX ratio. Requires ti,async-mode to be + enabled when the ratio differs from auxclk-fs-ratio. + When not specified, it defaults to the value of auxclk-fs-ratio. + The property is ignored in DIT mode. gpio-controller: true @@ -170,14 +206,38 @@ - $ref: dai-common.yaml# - if: properties: - opmode: + op-mode: enum: - 0 - then: required: - tdm-slots + - if: + properties: + op-mode: + const: 1 + then: + properties: + tdm-slots: false + tdm-slots-rx: false + ti,async-mode: false + auxclk-fs-ratio-rx: false + + - if: + required: + - tdm-slots-rx + then: + required: + - ti,async-mode + + - if: + required: + - auxclk-fs-ratio-rx + then: + required: + - ti,async-mode + unevaluatedProperties: false examples: @@ -190,6 +250,7 @@ interrupt-names = "tx", "rx"; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; + ti,async-mode; dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; dma-names = "tx", "rx"; serial-dir = < diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/sound/ti,pcm6240.yaml v_kernel/Documentation/devicetree/bindings/sound/ti,pcm6240.yaml --- linux-6.12.57/Documentation/devicetree/bindings/sound/ti,pcm6240.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/sound/ti,pcm6240.yaml 2026-04-21 11:35:25.558907440 +0200 @@ -29,8 +29,6 @@ https://www.ti.com/lit/gpn/pcm9211 https://www.ti.com/lit/gpn/pcmd3140 https://www.ti.com/lit/gpn/pcmd3180 - https://www.ti.com/lit/gpn/taa5212 - https://www.ti.com/lit/gpn/tad5212 properties: compatible: @@ -81,10 +79,6 @@ ti,pcmd3180: Eight-channel pulse-density-modulation input to TDM or I2S output converter. - ti,taa5212: Low-power high-performance stereo audio ADC with 118-dB - dynamic range. - - ti,tad5212: Low-power stereo audio DAC with 120-dB dynamic range. oneOf: - items: - enum: @@ -98,8 +92,6 @@ - enum: - ti,pcmd512x - ti,pcm9211 - - ti,taa5212 - - ti,tad5212 - const: ti,adc6120 - items: - enum: @@ -114,8 +106,6 @@ - ti,pcmd3140 - ti,pcmd3180 - ti,pcm1690 - - ti,taa5412 - - ti,tad5412 - const: ti,pcm6240 - enum: - ti,adc6120 diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/sound/ti,tac5x1x.yaml v_kernel/Documentation/devicetree/bindings/sound/ti,tac5x1x.yaml --- linux-6.12.57/Documentation/devicetree/bindings/sound/ti,tac5x1x.yaml 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/sound/ti,tac5x1x.yaml 2026-04-21 11:35:25.558907440 +0200 @@ -0,0 +1,262 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright (C) 2025 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ti,tac5x1x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TAC5X1X Codec + +description: | + TAC5X1X are series of low-power and high performance mono or stereo + audio codecs, as well as multiple inputs and outputs programmable in + single-ended or fully differential configurations. Device supports both + Microphone and Line In input on ADC Channel. DAC Output can be configured + for either Line Out or Head Phone Load. + + The serial control bus supports SPI or I2C protocols, while the serial audio + data bus is programmable for I2S, left/right-justified, DSP, or TDM modes. + + Specification about the codecs can be found at: + https://www.ti.com/lit/gpn/taa5212 + https://www.ti.com/lit/gpn/taa5412-q1 + https://www.ti.com/lit/gpn/tac5111 + https://www.ti.com/lit/gpn/tac5112 + https://www.ti.com/lit/gpn/tac5211 + https://www.ti.com/lit/gpn/tac5212 + https://www.ti.com/lit/gpn/tac5311-q1 + https://www.ti.com/lit/gpn/tac5312-q1 + https://www.ti.com/lit/gpn/tac5411-q1 + https://www.ti.com/lit/gpn/tac5412-q1 + https://www.ti.com/lit/gpn/tad5112 + https://www.ti.com/lit/gpn/tad5212 + +maintainers: + - Niranjan H Y + - Kevin Lu + +properties: + compatible: + enum: + - ti,taa5212 + - ti,taa5412 + - ti,tac5111 + - ti,tac5112 + - ti,tac5211 + - ti,tac5212 + - ti,tac5311 + - ti,tac5312 + - ti,tac5411 + - ti,tac5412 + - ti,tad5112 + - ti,tad5212 + + reg: + maxItems: 1 + + ti,vref: + description: VREF required voltage. If node is omitted then VREF is powered down. + $ref: /schemas/types.yaml#/definitions/uint32 + oneOf: + - const: 0 + description: VREF output is powered to 2.75V. + - const: 1 + description: VREF output is powered to 2.5V. + - const: 2 + description: VREF output is powered to 1.375V. + + ti,micbias-vg: + description: MicBias required voltage. If node is omitted then MicBias is powered down. + $ref: /schemas/types.yaml#/definitions/uint32 + oneOf: + - const: 0 + description: MICBIAS output is same as the VREF output + - const: 1 + description: MICBIAS output is 0.5 times the VREF output + - const: 3 + description: MICBIAS output is same as the AVDD + + avdd-supply: + description: Analog DAC voltage. + + iovdd-supply: + description: I/O voltage. + + ti,gpios-func: + description: | + Array indicating the GPIO1, GPIO2, GPO1 Functionality in the same order. + Each integer elemnent in the array represent the following + - 0 TAC5X1X_GPIO_DISABLE - GPIO is Disabled + - 1 TAC5X1X_GPIO_GPI - General Purpose Input + - 2 ADC3XXX_GPIO_GPO - General Purpose Output + - 3 TAC5X1X_GPIO_IRQ - Chip Interrupt + - 4 TAC5X1X_GPIO_PDMCLK - PDM CLK Output + - 5 TAC5X1X_GPIO_P_DOUT - Primary ASI DOUT + - 6 TAC5X1X_GPIO_P_DOUT2 - Primary ASI DOUT2 + - 7 TAC5X1X_GPIO_S_DOUT - Secondary ASI DOUT + - 8 TAC5X1X_GPIO_S_DOUT2 - Secondary ASI DOUT2 + - 9 TAC5X1X_GPIO_S_BCLK - Secondary BCLK Output + - 10 TAC5X1X_GPIO_S_FSYNC - Secondary FSYNC Output + - 11 TAC5X1X_GPIO_CLKOUT - General Purpose Output + - 12 TAC5X1X_GPIO_DOUT_MUX + - 13 TAC5X1X_GPIO_DAISY_OUT + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + maxItems: 3 + + ti,gpios-drive: + description: | + Array indicating the GPIO1, GPIO2, GPO1 Driver values + Each number in the array indicate the following driver values. + - 0 # Hi-Z Output + - 1 # Drive active low and active High + - 2 # Drive active low and weak High + - 3 # Drive acive low and Hi-Z + - 4 # Drive weak low and active High + - 5 # Drive Hi-Z and active High + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + maxItems: 3 + + ti,pdm-input-pins: + description: | + Array indicating the PDM Data Input for "Ch1 & Ch2" and "Ch3 & Ch4" + respectively. Each number in the array indicate the following + - 0 # PDM input disabled + - 1 # PDM input GPIO1 + - 2 # PDM input GPIO2 + - 3 # PDM input GPI1 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + + ti,gpi1-func: + description: GPI1 Functionality + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # TAC5X1X_GPIO_DISABLE - I/O buffers powered down and not used + - 1 # TAC5X1X_GPIO_GPI - General purpose input + default: 0 + + '#sound-dai-cells': + const: 0 + + clocks: + maxItems: 1 + + ti,gpa-gpio: + description: GPA using GPIO1 configuration + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # GPA using GPIO1 is disabled + - 1 # GPA using GPIO1 + default: 0 + + ti,in-ch-en: + description: Enable Input channel diagnostics for TAC54XX and TAC53XX device. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # Disable input channel diagnostics + - 1 # Enable input channel diagnostics + + ti,out-ch-en: + description: Enable Output channel diagnostics for TAC54XX and TAC53XX device + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # Disable Output channel diagnostics + - 1 # Enable Output channel Diagnostics + + ti,incl-se-inm: + description: INxM pin Diagnostics Scan Selection for Single Ended Configuration + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # INxM pin Diagnostics Scan Selection for Single Ended excluded for diagnosis + - 1 # INxM pin Diagnostics Scan Selection for Single Ended included for diagnosis + + ti,incl-ac-coup: + description: AC coupled channels pins Scan Selection for Diagnostics + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # AC coupled channels pins Scan Selection for Diagnostics exluded for diagnosis + - 1 # AC coupled channels pins Scan Selection for Diagnostics included for diagnosis + + ti,micbias-threshold: + description: Micbias Low and High threshold values for TAC54XX and TAC53XX series + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 2 + minItems: 2 + items: + minimum: 72 + maximum: 162 + + ti,gpa-threshold: + description: GPA Low and High threshold Values + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 2 + minItems: 2 + items: + minimum: 75 + maximum: 186 + + ti,adc1-impedance: + description: Channel 1 Input Impedance Value + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # 5 kOhm + - 1 # 10 kOhm + - 2 # 40 kOhm + default: 0 + + ti,adc2-impedance: + description: Channel 2 Input Impedance Value + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # 5 kOhm + - 1 # 10 kOhm + - 2 # 40 kOhm + default: 0 + + ti,out2x-vcom-cfg: + description: Channel OUT2x VCOM configuration + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # 0.6 * Vref + - 1 # AVDD by 2 + default: 0 + +required: + - compatible + - reg + - ti,vref + - ti,micbias-vg + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + tac5x1x: tac5x1x@52 { + compatible = "ti,tac5212"; + reg = <0x52>; + #sound-dai-cells = <0>; + avdd-supply = <&vdd_3v3_reg>; + iovdd-supply = <&vdd_3v3_reg>; + ti,vref = <0>; + ti,micbias-vg = <3>; + ti,gpi1-func = <0>; + ti,gpios-func = <4>, <1>, <0>; + ti,gpios-drive = <0>, <0>, <0>; + ti,gpa-gpio = <0>; + ti,in-ch-en = <1>; + ti,out-ch-en = <1>; + ti,incl-ac-coup = <0>; + ti,incl-se-inm = <0>; + ti,gpa-threshold = <75>, <186>; + }; + }; +... diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml v_kernel/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml --- linux-6.12.57/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml 2026-04-21 11:35:25.572907477 +0200 @@ -115,6 +115,14 @@ description: 32-bit indirect AHB trigger address. + cdns,phase-detect-selector: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + DLL Phase Detect Selector for sampling clock generation to handle the + clock domain crossing between the reference clock and sampling clock. + Refer SoC datasheet for the Phase Detect Selector value and assign + (Phase Detect Selector value - 1) to cdns,phase-detect-selector. + cdns,is-decoded-cs: type: boolean description: diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/vendor-prefixes.yaml v_kernel/Documentation/devicetree/bindings/vendor-prefixes.yaml --- linux-6.12.57/Documentation/devicetree/bindings/vendor-prefixes.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/vendor-prefixes.yaml 2026-04-21 11:35:25.630907629 +0200 @@ -585,6 +585,8 @@ description: GOcontroll Modular Embedded Electronics B.V. "^goldelico,.*": description: Golden Delicious Computers GmbH & Co. KG + "^gooddisplay,.*": + description: Good Display Co., Ltd. "^goodix,.*": description: Shenzhen Huiding Technology Co., Ltd. "^google,.*": diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml v_kernel/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml --- linux-6.12.57/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml 2026-04-21 11:35:25.641907658 +0200 @@ -24,6 +24,7 @@ compatible: enum: - ti,j7-rti-wdt + - ti,am62l-rti-wdt reg: maxItems: 1 diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/networking/device_drivers/ethernet/ti/cpsw_proxy_client.rst v_kernel/Documentation/networking/device_drivers/ethernet/ti/cpsw_proxy_client.rst --- linux-6.12.57/Documentation/networking/device_drivers/ethernet/ti/cpsw_proxy_client.rst 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/Documentation/networking/device_drivers/ethernet/ti/cpsw_proxy_client.rst 2026-04-21 11:35:26.538910011 +0200 @@ -0,0 +1,182 @@ +.. SPDX-License-Identifier: GPL-2.0-only or MIT + +========================================== +Texas Instruments CPSW Proxy Client driver +========================================== + +Introduction +============ + +The CPSW (Common Platform Switch) Ethernet Switch on TI's K3 SoCs provides +Ethernet functionality. There may be multiple instances of CPSW on a single +SoC. The term "CPSWnG" is used to indicate the number of MAC Ports supported +by a specific instance of CPSW. CPSWnG indicates that the peripheral has +(n-1) MAC Ports and 1 Host Port. Examples of existing instances are: +CPSW2G => 1 MAC Port and 1 Host Port +CPSW3G => 2 MAC Ports and 1 Host Port +CPSW5G => 4 MAC Ports and 1 Host Port +CPSW9G => 8 MAC Ports and 1 Host Port + +The presence of 2 or more MAC Ports implies that Hardware Switching can +be enabled between the MAC Ports if required. + +The "am65-cpsw-nuss.c" driver in Linux at: +drivers/net/ethernet/ti/am65-cpsw-nuss.c +provides Ethernet functionality for applications on Linux. +It also handles both the control-path and data-path, namely: +Control => Configuration of the CPSW Peripheral +Data => Configuration of the DMA Channels to transmit/receive data + +The aforementioned configuration supports use-cases where all applications +which require Ethernet functionality are only running on Linux. + +However, there are use-cases where applications running on different +Operating Systems across multiple cores on the SoC require Ethernet +functionality. Such use-cases can be supported by implementing a +Client-Server model to share the data-path among Clients while the Server +owns the control-path. + +On TI's K3 SoCs (J721E, J7200 and J784S4 in particular), the Ethernet Switch +Firmware (EthFw) running on the MAIN R5F core acts as the Server and +configures the CPSWnG instance (CPSW5G on J7200 and CPSW9G on J721E, J784S4) +of the CPSW Ethernet Switch on the SoC. The Clients running on various cores +communicate with EthFw via RPMsg (Remote Processor Messaging) to request +resource allocation details during initialization, followed by requesting +EthFw to enable features supported by CPSW based on the features required +by the applications running on the respective cores. + +EthFw handles requests from the Clients and evaluates them before configuring +CPSW based on the request. Since no Client is actually in control of CPSW and +only requests EthFw for configuring CPSW, EthFw acts as the proxy for the +Clients. Thus, the Linux Client which interfaces with EthFw is named: +CPSW Proxy Client + +The data-path for the CPSW Proxy Client driver remains identical to the +"am65-cpsw-nuss.c" driver which happens to be DMA. It is only the control-path +that is different. + +Client-Server discovery occurs over the RPMsg-Bus. EthFw announces its +RPMsg Endpoint name over the RPMsg-Bus. The CPSW Proxy Client driver +registers itself with the Linux RPMsg framework to be probed for the same +Endpoint name. Following probe, the Linux Client driver begins communicating +with EthFw and queries details of the resources available for the Linux Client. + +Terminology +=========== + +Virtual Port + A Virtual Port refers to the Software View of an Ethernet MAC Port. + There are two types of Virtual Ports: + 1. Virtual MAC Only Port + 2. Virtual Switch Port + +Virtual MAC Only Port + A Virtual MAC only Port refers to a dedicated physical MAC Port for + a Client. This corresponds to MAC Mode of operation in Ethernet + Terminology. All traffic sent to or received from the Physical + MAC Port is that of the Client to which the Virtual MAC Only Port + has been allocated. + +Virtual Switch Port + A Virtual Switch Port refers to a group of physical MAC ports with + Switching enabled across them. This implies that any traffic sent + to the Port from a Client could potentially exit a Physical MAC + Port along with the traffic from other Clients. Similarly, the traffic + received on the Port by a Client could have potentially ingressed + on a Physical MAC Port along with the traffic meant for other Clients. + While the ALE (Address Lookup Engine) handles segregating the traffic, + and the CPSW Ethernet Switch places traffic on dedicated RX DMA Flows + meant for a single Client, it is worth noting that the bandwidths + of the Physical MAC Port are shared by Clients when traffic is sent to + or received from a Virtual Switch Port. + +Network Interface + The user-visible interface in Linux userspace exposed to applications + that serves as the entry/exit point for traffic to/from the Virtual + Ports. A single network interface (ethX) maps to either a Virtual + MAC Only Port or a Virtual Switch Port. + +C2S + RPMsg source is Client and destination is Server. + +S2C + RPMsg source is Server and destination is Client. + +Initialization Sequence +======================= + +The sequence of message exchanges between the Client driver and EthFw starting +from the driver probe and ending with the interfaces being brought up is as +follows: +1. C2S ETHFW_VIRT_PORT_INFO requesting details of Virtual Ports available + for the Linux Client. +2. S2C response containing requested details +3. C2S ETHFW_VIRT_PORT_ATTACH request for each Virtual Port allocated during + step 2. +4. S2C response containing details of the MTU Size, number of Tx DMA Channels + and RX DMA Flows for the specified Virtual Port. The *Features* associated + with the Virtual Port are also shared such as Multicast Filtering capability. +5. C2S ETHFW_ALLOC_RX request for each RX DMA Flow for a Virtual Port. +6. S2C response containing details of the RX PSI-L Thread ID, Flow base and + Flow offset. +7. C2S ETHFW_ALLOC_TX request for each TX DMA Channel for a Virtual Port. +8. S2C response containing details of the TX PSI-L Thread ID. +9. C2S ETHFW_ALLOC_MAC request for each Virtual Port. +10. S2C response containing the MAC Address corresponding to the Virtual Port. +11. C2S ETHFW_MAC_REGISTER request for each Virtual Port with the MAC Address + allocated in step 10. This is necessary to steer packets that ingress on + the MAC Ports of CPSW onto the RX DMA Flow for the Virtual Port in order + to allow the Client to receive the packets. +12. S2C response indicating status of request. +13. C2S ETHFW_IPv4_REGISTER request *only* for Virtual Switch Port interface. + The IPv4 address assigned to the "ethX" network interface in Linux + corresponding to the Virtual Switch Port interface has to be registered + with EthFw. This is due to the reason that all Broadcast requests including + ARP requests received by the MAC Ports corresponding to the Virtual Switch + Port are consumed solely be EthFw. Such traffic is sent to Clients by + alternate methods. Therefore EthFw needs to know the IPv4 address for the + "ethX" network interface in Linux in order to automatically respond to + ARP requests, thereby enabling Unicast communication. +14. S2C response indicating status of request. +15. C2S ETHFW_MCAST_FILTER_ADD request to register the Multicast Addresses + associated with the network interface corresponding to the Virtual Port + which has the Multicast Filtering capability. +16. S2C response indicating status of request. +17. C2S ETHFW_MCAST_FILTER_DEL request to deregister the Multicast Addresses + associated with the network interface corresponding to the Virtual Port + which has the Multicast Filtering capability. +18. S2C response indicating status of request. + +Shutdown Sequence +================= + +The sequence of message exchanges between the Client driver and EthFw on module +removal are as follows: +1. C2S ETHFW_MAC_DEREGISTER request to deregister the MAC Address for each + Virtual Port. +2. S2C response indicating status of request. +3. C2S ETHFW_MCAST_FILTER_DEL request to deregister the Multicast Addresses + associated with the network interface corresponding to the Virtual Port + which has the Multicast Filtering capability. +4. S2C response indicating status of request. +5. C2S ETHFW_FREE_MAC request to release the MAC Address allocated to each + Virtual Port. +6. S2C response indicating status of request. +7. C2S ETHFW_FREE_TX request to release the TX DMA Channel for each TX Channel + for every Virtual Port. +8. S2C response indicating status of request. +9. C2S ETHFW_FREE_RX request to release the RX DMA Flow for each RX Channel + for every Virtual Port. +10. S2C response indicating status of request. +11. C2S ETHFW_VIRT_PORT_DETACH request to release each Virtual Port. +12. S2C response indicating status of request. + +Features Supported +================== + +The set of features supported in addition to providing basic Ethernet +Functionality are: +1. Multicast Filtering +2. Determining Link Status of the network interface corresponding to the + Virtual MAC Only port via ethtool. +3. Interrupt Pacing/Coalescing diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/power/pm_qos_interface.rst v_kernel/Documentation/power/pm_qos_interface.rst --- linux-6.12.57/Documentation/power/pm_qos_interface.rst 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/power/pm_qos_interface.rst 2026-04-21 11:35:26.591910150 +0200 @@ -62,7 +62,8 @@ From user space: -The infrastructure exposes one device node, /dev/cpu_dma_latency, for the CPU +The infrastructure exposes two separate device nodes, /dev/cpu_dma_latency for +the CPU latency QoS and /dev/cpu_wakeup_latency for the CPU system-wakeup latency QoS. Only processes can register a PM QoS request. To provide for automatic @@ -70,15 +71,15 @@ parameter requests as follows. To register the default PM QoS target for the CPU latency QoS, the process must -open /dev/cpu_dma_latency. +open /dev/cpu_dma_latency. To register a CPU system-wakeup QoS limit, the +process must open /dev/cpu_wakeup_latency. As long as the device node is held open that process has a registered request on the parameter. To change the requested target value, the process needs to write an s32 value to the open device node. Alternatively, it can write a hex string for the value -using the 10 char long format e.g. "0x12345678". This translates to a -cpu_latency_qos_update_request() call. +using the 10 char long format e.g. "0x12345678". To remove the user mode request for a target value simply close the device node. diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst v_kernel/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst --- linux-6.12.57/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst 2026-04-21 11:35:26.902910966 +0200 @@ -604,6 +604,11 @@ chosen data limit then the frame will be skipped. Possible values are: +``V4L2_CID_MPEG_VIDEO_BACKGROUND_DETECTION (boolean)`` + If enabled then, the encoder detect a background region in frame and + use low bits or skip mode to encode the background region. + If a lot of scenes are stationary or background, It may help to + reduce the video bitrate. Applicable to the encoder. .. tabularcolumns:: |p{8.2cm}|p{9.3cm}| diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/base/power/qos.c v_kernel/drivers/base/power/qos.c --- linux-6.12.57/drivers/base/power/qos.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/base/power/qos.c 2026-04-21 11:35:32.497925640 +0200 @@ -137,6 +137,7 @@ return ret; } +EXPORT_SYMBOL_GPL(dev_pm_qos_read_value); /** * apply_constraint - Add/modify/remove device PM QoS request. diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/bluetooth/btti_debugfs.c v_kernel/drivers/bluetooth/btti_debugfs.c --- linux-6.12.57/drivers/bluetooth/btti_debugfs.c 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/bluetooth/btti_debugfs.c 2026-04-21 11:35:32.573925840 +0200 @@ -0,0 +1,154 @@ +/* + * This file is part of TI BLE over SDIO + * + * Copyright (C) 2022 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + */ + +#include +#include + +#include +#include + +#include "btti_drv.h" + +struct btti_debugfs_dir { + struct dentry *config_dir; + struct dentry *status_dir; +}; + +int btti_debugfs_if_prepare_command(u8 cmd_type,\ + struct btti_private *private_data); + + +#define DEBUGFS_FORMAT_BUFFER_SIZE 256 + +int btti_format_buffer(char __user *userbuf, size_t count, + loff_t *ppos, char *fmt, ...) +{ + va_list args; + char buf[DEBUGFS_FORMAT_BUFFER_SIZE]; + int res; + + va_start(args, fmt); + res = vscnprintf(buf, sizeof(buf), fmt, args); + va_end(args); + + return simple_read_from_buffer(userbuf, count, ppos, buf, res); +} + +//ble_enable +static ssize_t ble_enable_read(struct file *file, char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct btti_private *private_data = file->private_data; + char buf[16]; + int ret; + + BT_INFO("[bt sdio] ble enable read"); + + ret = snprintf(buf, sizeof(buf) - 1, "%d\n", \ + private_data->hci_adapter->ble_enable); + + return btti_format_buffer(userbuf, count, ppos, "%d\n", \ + private_data->hci_adapter->ble_enable); +} + +static ssize_t ble_enable_write(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct btti_private *private_data = file->private_data; + unsigned long value; + int ret; + + ret = kstrtoul_from_user(user_buf, count, 0, &value); + BT_INFO("[bt sdio] ble enable write: %ld", value); + + if (!private_data || !private_data->hci_adapter) + BT_ERR("[bt sdio] driver is not ready"); + + + if (private_data->hci_adapter->ble_enable) { + BT_WARN("[bt sdio] ble_enable is already %d",\ + private_data->hci_adapter->ble_enable); + return -EINVAL; + } + + if (value != 1) { + BT_WARN("illegal value in ble_enable "\ + "(only value allowed is is 1)"); + BT_WARN("ble_enable can't be disabled after being enabled."); + return -EINVAL; + } + + ret = btti_debugfs_if_prepare_command((u8)CMD_TYPE_BLE_ENABLE,\ + private_data); + + return count; +} + + + +//ble_enable + +static const struct file_operations ble_enable_ops = { + .read = ble_enable_read, + .write = ble_enable_write, + .open = simple_open, + .llseek = default_llseek, +}; + + +void btti_debugfs_init(struct hci_dev *hdev) +{ + struct btti_private *private_data = hci_get_drvdata(hdev); + struct btti_debugfs_dir *dbg; + struct dentry *root_cfg_dir; + + if (!hdev->debugfs) + return; + + dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); + private_data->debugfs_dir_vals = dbg; + + if (!dbg) { + BT_ERR("Can not allocate memory for btti_debugfs_dir."); + return; + } + + dbg->config_dir = debugfs_create_dir("config", hdev->debugfs); + root_cfg_dir = dbg->config_dir; + + debugfs_create_file("ble_enable", 0744, root_cfg_dir, private_data,\ + &ble_enable_ops); + + //dbg->status_dir = debugfs_create_dir("cc3xx_status", hdev->debugfs); +} + +void btti_debugfs_remove(struct hci_dev *hdev) +{ + struct btti_private *private_data = hci_get_drvdata(hdev); + struct btti_debugfs_dir *dbgfs = private_data->debugfs_dir_vals; + + if (!dbgfs) + return; + + if (dbgfs->config_dir) + debugfs_remove_recursive(dbgfs->config_dir); + + if (dbgfs->status_dir) + debugfs_remove_recursive(dbgfs->status_dir); + + kfree(dbgfs); +} diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/bluetooth/btti_drv.h v_kernel/drivers/bluetooth/btti_drv.h --- linux-6.12.57/drivers/bluetooth/btti_drv.h 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/bluetooth/btti_drv.h 2026-04-21 11:35:32.573925840 +0200 @@ -0,0 +1,85 @@ +/* + * This file is part of TI BLE over SDIO + * + * Copyright (C) 2022 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define BT_SDIO_HEADER_LEN 4 +#define BT_SDIO_UPLD_SIZE (251+BT_SDIO_HEADER_LEN) + +#define CMD_TYPE_BLE_ENABLE 1 + + + +struct btti_worker_thread { + struct task_struct *task; + wait_queue_head_t wait_queue; + void *private_data; +}; + +struct btti_device { + void *sdiodev; //see btti_sdio_dev + struct hci_dev *hcidev; + u8 dev_type; +}; + +struct btti_hci_adapter { + u32 num_of_interrupt; + struct sk_buff_head tx_queue; + u8 ble_enable; + u8 enable_autosuspend; + bool is_suspended; + bool is_suspending; +}; + +struct btti_private { + struct btti_device btti_dev; + struct btti_hci_adapter *hci_adapter; + struct btti_worker_thread work_thread; + int (*card_tx_packet_funcp)\ + (struct btti_private *private_data, struct sk_buff *skb); + int (*card_power_up_firmware_funcp)(struct btti_private *private_data); + int (*card_power_dn_firmware_funcp)(struct btti_private *private_data); + int (*card_process_rx_funcp)(struct btti_private *private_data); + spinlock_t irq_cnt_lock; /* spinlock used by driver */ +#ifdef CONFIG_DEBUG_FS + void *debugfs_dir_vals; +#endif + bool sdio_dev_removed; +}; + +/* Prototype of global function */ +int btti_hci_register_hdev(struct btti_private *private_data); +struct btti_private *btti_hci_add_sdio_dev(void *sdiodev); +int btti_hci_remove_sdio_dev(struct btti_private *private_data); +void btti_hci_irq_handler(struct btti_private *private_data); + +#ifdef CONFIG_DEBUG_FS +void btti_debugfs_init(struct hci_dev *hdev); +void btti_debugfs_remove(struct hci_dev *hdev); +#endif diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/bluetooth/btti_main.c v_kernel/drivers/bluetooth/btti_main.c --- linux-6.12.57/drivers/bluetooth/btti_main.c 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/bluetooth/btti_main.c 2026-04-21 11:35:32.573925840 +0200 @@ -0,0 +1,475 @@ +/* + * This file is part of TI BLE over SDIO + * + * Copyright (C) 2022 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + */ + + +#include +#include +#include +#include + +#include +#include + +#include "btti_drv.h" +#include "btti_sdio.h" + +#define VERSION "ti_1.0" + +#define BTTI_SDIO_AUTOSUSPEND_DELAY 8000 + +static int btti_hci_is_ble_enabled(struct btti_private *private_data); + + +/* + * This function is called by the interrupt handler. + * It wakes up the worker thread.to make the RX reception. + */ +void btti_hci_irq_handler(struct btti_private *private_data) +{ + ulong flags; + + spin_lock_irqsave(&private_data->irq_cnt_lock, flags); + private_data->hci_adapter->num_of_interrupt++; + spin_unlock_irqrestore(&private_data->irq_cnt_lock, flags); + + // wakeup to btti_service_work_thread + wake_up_interruptible(&private_data->work_thread.wait_queue); +} +EXPORT_SYMBOL_GPL(btti_hci_irq_handler); + + +int btti_debugfs_if_prepare_command(u8 cmd_type,\ + struct btti_private *private_data) +{ + int ret = 0; + + switch (cmd_type) { + case CMD_TYPE_BLE_ENABLE: + BT_INFO("[bt sdio hci] "\ + "btti_debugfs_if_prepare_command "\ + " CMD_TYPE_BLE_ENABLE "); + ret = btti_hci_is_ble_enabled(private_data); + break; + default: + break; + } + return ret; +} + +static int btti_hci_tx_pkt(struct btti_private *private_data,\ + struct sk_buff *skb) +{ + int ret = 0; + + if (!skb || !skb->data) + return -EINVAL; + + if (!skb->len || ((skb->len + BT_SDIO_HEADER_LEN) > BT_SDIO_UPLD_SIZE)) { + BT_ERR("[bt sdio hci] TX Error: Bad skb length %d : %d", + skb->len, BT_SDIO_UPLD_SIZE); + return -EINVAL; + } + + skb_push(skb, BT_SDIO_HEADER_LEN); + + /* header type: byte[3] + * HCI_COMMAND = 1, ACL_DATA = 2, SCO_DATA = 3, 0xFE = Vendor + * header length: byte[2][1][0] + */ + + skb->data[0] = (skb->len & 0x0000ff); + skb->data[1] = (skb->len & 0x00ff00) >> 8; + skb->data[2] = (skb->len & 0xff0000) >> 16; + skb->data[3] = hci_skb_pkt_type(skb); + + + BT_DBG("[bt sdio hci] TX buff 0x: %*ph", skb->len, skb->data); + + + if (private_data->card_tx_packet_funcp) + ret = private_data->card_tx_packet_funcp(private_data,\ + skb);//btti_sdio_tx_packet + + return ret; +} + +static void btti_hci_init_hci_adapter(struct btti_private *private_data) +{ + + skb_queue_head_init(&private_data->hci_adapter->tx_queue); + private_data->hci_adapter->enable_autosuspend = true; +} + +static void btti_hci_free_hci_adapter(struct btti_private *private_data) +{ + skb_queue_purge(&private_data->hci_adapter->tx_queue); + kfree(private_data->hci_adapter); + + private_data->hci_adapter = NULL; +} + + + + +//it is on purpose without lock , +//worse case card_ble_verify_if_ble_enable_funcp will be called more than once +static int btti_hci_is_ble_enabled(struct btti_private *private_data) +{ + //if ble_enabled -- return 0 + return private_data->hci_adapter->ble_enable; +} + + +static int btti_hci_if_open(struct hci_dev *hdev) +{ + BT_DBG("[bt sdio hci] btti_hci_if_open"); + return 0; +} + +static int btti_hci_if_close(struct hci_dev *hdev) +{ + struct btti_private *private_data = hci_get_drvdata(hdev); + struct btti_sdio_dev *sdiodev = private_data->btti_dev.sdiodev; + BT_DBG("[bt sdio hci] btti_hci_if_close"); + + pm_runtime_disable(&sdiodev->func->dev); + skb_queue_purge(&private_data->hci_adapter->tx_queue); + + return 0; +} + +static int btti_hci_if_flush(struct hci_dev *hdev) +{ + struct btti_private *private_data = hci_get_drvdata(hdev); + BT_DBG("[bt sdio hci] btti_hci_if_flush"); + + skb_queue_purge(&private_data->hci_adapter->tx_queue); + + return 0; +} +static int btti_hci_if_tx_frame(struct hci_dev *hdev, struct sk_buff *skb) +{ + struct btti_private *private_data = hci_get_drvdata(hdev); + + BT_INFO("[bt sdio hci] TX from HCI received ,type=%d,"\ + " opcode: 0x%x len=%d ble_enable=%d", + hci_skb_pkt_type(skb), hci_skb_opcode(skb),\ + skb->len, private_data->hci_adapter->ble_enable); + + if (private_data->hci_adapter->is_suspending\ + || private_data->hci_adapter->is_suspended) { + BT_ERR("[bt sdio hci] %s:"\ + " Device is suspending or suspended", __func__); + goto fail; + } + + //check of ble is enabled + if (!btti_hci_is_ble_enabled(private_data)) { + BT_INFO("[bt sdio hci] ble is not enabled"); + goto fail; + } + + + switch (hci_skb_pkt_type(skb)) { + case HCI_COMMAND_PKT: + if (hdev) + hdev->stat.cmd_tx++; + break; + + case HCI_ACLDATA_PKT: + if (hdev) + hdev->stat.acl_tx++; + break; + + case HCI_SCODATA_PKT: + BT_WARN("[bt sdio hci] HCI_SCODATA_PKT not supported"); + if (hdev) + hdev->stat.sco_tx++; + break; + + default: + BT_ERR("[bt sdio hci] unknown packet type :%d",\ + hci_skb_pkt_type(skb)); + return -EILSEQ; + + } + + + skb_queue_tail(&private_data->hci_adapter->tx_queue, skb); + + if (!private_data->hci_adapter->is_suspended) + wake_up_interruptible(&private_data->work_thread.wait_queue); + else { + skb_dequeue_tail(&private_data->hci_adapter->tx_queue); + BT_INFO("[bt sdio hci] Device is suspending"); + goto fail; + } + + return 0; +fail: + //in case of error HCI frees the skb + return -EIO; +} + + + +static int btti_hci_if_setup(struct hci_dev *hdev) +{ + struct btti_private *private_data = hci_get_drvdata(hdev); + struct btti_sdio_dev *sdiodev = private_data->btti_dev.sdiodev; + + BT_INFO("[bt sdio hci] btti_hci_if_setup"); + pm_runtime_set_autosuspend_delay(&sdiodev->func->dev, + BTTI_SDIO_AUTOSUSPEND_DELAY); + pm_runtime_use_autosuspend(&sdiodev->func->dev); + + pm_runtime_set_active(&sdiodev->func->dev); + + /* Default forbid runtime auto suspend + */ + pm_runtime_forbid(&sdiodev->func->dev); + pm_runtime_enable(&sdiodev->func->dev); + + + //auto suspend is allowed + if (private_data->hci_adapter\ + && private_data->hci_adapter->enable_autosuspend){ + BT_DBG("[bt sdio hci] btti_hci_if_setup , enable auto suspend"); + pm_runtime_allow(&sdiodev->func->dev); + } + return 0; +} + +/* + * This function handles the event generated by firmware, rx data + * received from firmware, and tx data sent from kernel. + * work_thread.wait_queue + */ +static int btti_service_work_thread(void *data) +{ + struct btti_worker_thread *thread = data; + struct btti_private *private_data = thread->private_data; + struct btti_hci_adapter *hci_adapter = private_data->hci_adapter; + wait_queue_entry_t wait; + struct sk_buff *skb; + ulong flags; + + BT_INFO("[bt sdio hci] work thread is started"); + + init_waitqueue_entry(&wait, current); + + for (;;) { + add_wait_queue(&thread->wait_queue, &wait); + + if (kthread_should_stop() || private_data->sdio_dev_removed) { + BT_DBG("[bt sdio hci]work_thread: "\ + " thread is need to stopped"); + break; + } + + + set_current_state(TASK_INTERRUPTIBLE); + + //if no RX and queue is empty or ble is not enabled + if ((!private_data->hci_adapter->ble_enable) || + ((!hci_adapter->num_of_interrupt) &&\ + skb_queue_empty\ + (&hci_adapter->tx_queue))) { + BT_INFO("[bt sdio hci] work thread is sleeping..."); + schedule(); + } + + set_current_state(TASK_RUNNING); + + remove_wait_queue(&thread->wait_queue, &wait); + + BT_DBG("[bt sdio hci] work thread woke up"); + + if (kthread_should_stop() || private_data->sdio_dev_removed) { + BT_INFO("[bt sdio hci] work_thread:"\ + " break from main thread"); + break; + } + + //handle the RX, process the interrupt function + spin_lock_irqsave(&private_data->irq_cnt_lock, flags); + if (hci_adapter->num_of_interrupt) { + hci_adapter->num_of_interrupt = 0; + spin_unlock_irqrestore(&private_data->irq_cnt_lock,\ + flags); + if (private_data->card_process_rx_funcp) { + private_data->card_process_rx_funcp\ + (private_data);//call to btti_sdio_process_rx + } + } else { + spin_unlock_irqrestore(&private_data->irq_cnt_lock,\ + flags); + } + + if (private_data->hci_adapter->is_suspended) { + BT_INFO("[bt sdio hci] work thread not available,"\ + " is_suspended:%d", private_data->hci_adapter->is_suspended); + continue; + } + //handle the TX + skb = skb_dequeue(&hci_adapter->tx_queue); + if (skb) { + if (btti_hci_tx_pkt(private_data, skb)) { + //handle tx packet + BT_ERR("[bt sdio hci] TX , error send packet"); + } + } + } + + return 0; +} + +int btti_hci_register_hdev(struct btti_private *private_data) + +{ + struct hci_dev *hdev = NULL; + struct btti_sdio_dev *sdiodev = private_data->btti_dev.sdiodev; + int ret; + + BT_INFO("[bt sdio hci] btti_hci_register_hdev"); + + hdev = hci_alloc_dev(); + if (!hdev) { + BT_ERR("[bt sdio hci] Can not allocate HCI device"); + goto err_hdev; + } + + private_data->btti_dev.hcidev = hdev; + hci_set_drvdata(hdev, private_data); + + hdev->bus = HCI_SDIO; + hdev->open = btti_hci_if_open; + hdev->close = btti_hci_if_close; + hdev->flush = btti_hci_if_flush; + hdev->send = btti_hci_if_tx_frame; + hdev->setup = btti_hci_if_setup; + SET_HCIDEV_DEV(hdev, &sdiodev->func->dev); + + set_bit(HCI_QUIRK_NON_PERSISTENT_SETUP, &hdev->quirks); + + ret = hci_register_dev(hdev); + if (ret < 0) { + BT_ERR("[bt sdio hci] Can not register HCI device"); + goto err_hci_register_dev; + } + +#ifdef CONFIG_DEBUG_FS + btti_debugfs_init(hdev); +#endif + + return 0; + +err_hci_register_dev: + hci_free_dev(hdev); + +err_hdev: + /* Stop the thread servicing the interrupts */ + kthread_stop(private_data->work_thread.task); + + btti_hci_free_hci_adapter(private_data); + kfree(private_data); + + return -ENOMEM; +} +EXPORT_SYMBOL_GPL(btti_hci_register_hdev); + +struct btti_private *btti_hci_add_sdio_dev(void *sdiodev) +{ + struct btti_private *private_data; + + BT_INFO("[bt sdio hci] btti_hci_add_sdio_dev"); + + private_data = kzalloc(sizeof(*private_data), GFP_KERNEL); + if (!private_data) { + BT_ERR("[bt sdio hci] Can not allocate private_data"); + goto err_priv; + } + + private_data->hci_adapter = \ + kzalloc(sizeof(*private_data->hci_adapter), GFP_KERNEL); + if (!private_data->hci_adapter) { + BT_ERR("[bt sdio hci] Allocate buffer"\ + " for btti_hci_adapter failed!"); + goto err_hci_adapter; + } + + btti_hci_init_hci_adapter(private_data); + + BT_INFO("[bt sdio hci] Starting work thread..."); + private_data->work_thread.private_data = private_data; + spin_lock_init(&private_data->irq_cnt_lock); + + init_waitqueue_head(&private_data->work_thread.wait_queue); + private_data->work_thread.task = kthread_run(btti_service_work_thread, + &private_data->work_thread,\ + "btti_main_service"); + if (IS_ERR(private_data->work_thread.task)) + goto err_thread; + + private_data->btti_dev.sdiodev = sdiodev; + return private_data; + +err_thread: + btti_hci_free_hci_adapter(private_data); + +err_hci_adapter: + kfree(private_data); + +err_priv: + return NULL; +} +EXPORT_SYMBOL_GPL(btti_hci_add_sdio_dev); + +int btti_hci_remove_sdio_dev(struct btti_private *private_data) +{ + struct hci_dev *hdev; + + BT_INFO("[bt sdio hci] remove sdio dev"); + + hdev = private_data->btti_dev.hcidev; + + if (private_data->work_thread.task) + kthread_stop(private_data->work_thread.task); + + + if (hdev) { + BT_INFO("[bt sdio hci] unregister hci"); +#ifdef CONFIG_DEBUG_FS + btti_debugfs_remove(hdev); +#endif + hci_unregister_dev(hdev); + hci_free_dev(hdev); + } + + private_data->btti_dev.hcidev = NULL; + + btti_hci_free_hci_adapter(private_data); + + kfree(private_data); + + return 0; +} +EXPORT_SYMBOL_GPL(btti_hci_remove_sdio_dev); + +MODULE_AUTHOR("Texas Instruments."); +MODULE_DESCRIPTION("Texas Instruments Bluetooth driver ver " VERSION); +MODULE_VERSION(VERSION); +MODULE_LICENSE("GPL v2"); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/bluetooth/btti_sdio.c v_kernel/drivers/bluetooth/btti_sdio.c --- linux-6.12.57/drivers/bluetooth/btti_sdio.c 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/bluetooth/btti_sdio.c 2026-04-21 11:35:32.574925842 +0200 @@ -0,0 +1,1008 @@ +/* + * This file is part of TI BLE over SDIO + * + * Copyright (C) 2022 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + */ + + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "btti_drv.h" +#include "btti_sdio.h" + +#define VERSION "ti_1.0" + +#define SDIO_DEVICE_ID_TI_CC33XX 0x4077 + + +static void btti_sdio_if_remove(struct sdio_func *func); +static int __maybe_unused btti_sdio_unregister_dev(struct sdio_func *func); +static int btti_sdio_rx_packet(struct btti_private *private_dataate_data); +static int btti_sdio_tx_packet(struct btti_private *private_data, + struct sk_buff *skb); +static void btti_sdio_irq_handler(struct sdio_func *func); +static int btti_sdio_power_up_fw(struct btti_private *private_data); +static int btti_handle_rx_vendor_event(struct btti_private *private_data, + struct sk_buff *skb); +static void btti_acknldg_packet(struct btti_sdio_dev *sdiodev, u8 Ack); + + + +static const struct of_device_id btti_sdio_of_match_table[] = { + { .compatible = "ti,cc33xxbt" }, + { } +}; + +static int btti_sdio_if_probe_of(struct device *dev) +{ + + if (!dev || !dev->of_node || + !of_match_node(btti_sdio_of_match_table, dev->of_node)) { + BT_ERR("[bt sdio] sdio device tree data "\ + " not available\n"); + return -1; + } + + return 0; +} + +static const struct btti_sdio_dev_reg_map btti_reg_map_cc33xx = { + /* fun0 ,ELP Wakeup Reg address, func0 not used*/ + .sdio_wup_ble = 0x40, + /* fun1, set 0x1, to enable interrupts, 0 to disable */ + .sdio_enable_int = 0x14, + /* fun1,read and write to the card are at 0x0 address */ + .sdio_rt_data = 0x0, + /* fun1,write 1 to clear rx interrupt after reception */ + .sdio_cl_int = 0x13, + /* fun1, bt mode status, bit 1 means ack mode, + * currently the code just read it + */ + .bt_mode_status = 0x20, + /* fun1 read packet control, write 1 is set ack for RX, + * write 0 for nack + */ + .sdio_pc_rrt = 0x10, +}; + +static const struct btti_sdio_device btti_sdio_cc33xx_bt = { + .reg_map = &btti_reg_map_cc33xx, +}; + +static const struct sdio_device_id btti_sdio_ids[] = { + {SDIO_DEVICE(SDIO_VENDOR_ID_TI, SDIO_DEVICE_ID_TI_CC33XX), .driver_data\ + = (unsigned long)&btti_sdio_cc33xx_bt}, + { } /* Terminating entry */ +}; + +MODULE_DEVICE_TABLE(sdio, btti_sdio_ids); + +static int btti_sdio_enable_func_interrupt(struct btti_sdio_dev *sdiodev, + u8 mask) +{ + int ret; + + sdio_writeb(sdiodev->func, mask, sdiodev->reg_map->sdio_enable_int,\ + &ret); + if (ret) { + BT_ERR("[bt sdio] Unable to enable the host interrupt!"); + ret = -EIO; + } + + return ret; +} + +static int btti_sdio_disable_func_interrupt(struct btti_sdio_dev *sdiodev, + u8 mask) +{ + u8 sdio_enable_int_mask; + int ret; + + sdio_enable_int_mask = sdio_readb(sdiodev->func,\ + sdiodev->reg_map->sdio_enable_int, &ret); + if (ret) + return -EIO; + + sdio_enable_int_mask &= ~mask; + + sdio_writeb(sdiodev->func, sdio_enable_int_mask,\ + sdiodev->reg_map->sdio_enable_int, &ret); + if (ret < 0) { + BT_ERR("[bt sdio] Unable to disable the host interrupt!"); + return -EIO; + } + + return 0; +} + + + +//Read Rx, called from btti_service_work_thread +static int btti_sdio_process_rx(struct btti_private *private_data) +{ + ulong flags; + u8 intrpt_occur; + struct btti_sdio_dev *sdiodev = private_data->btti_dev.sdiodev; + + spin_lock_irqsave(&private_data->irq_cnt_lock, flags); + intrpt_occur = sdiodev->Intrpt_triggered; + sdiodev->Intrpt_triggered = 0; + spin_unlock_irqrestore(&private_data->irq_cnt_lock, flags); + + sdio_claim_host(sdiodev->func); + if (intrpt_occur) + btti_sdio_rx_packet(private_data);//read Rx, + else + btti_acknldg_packet(sdiodev, 1);//nack + + sdio_release_host(sdiodev->func); + + return 0; +} + +static int btti_sdio_clr_irq(struct btti_sdio_dev *sdiodev) +{ + int ret; + + BT_DBG("[bt sdio] clear int_status"); + + sdio_writeb(sdiodev->func, 1, sdiodev->reg_map->sdio_cl_int, &ret); + if (ret) { + BT_ERR("[bt sdio] clear int status failed: %d", ret); + return ret; + } + + return 0; +} + + +static int btti_sdio_register_dev(struct btti_sdio_dev *sdiodev) +{ + struct sdio_func *func; + u8 reg; + int ret; + + if (!sdiodev || !sdiodev->func) { + BT_ERR("[bt sdio] Error: sdiodev or function is NULL!"); + ret = -EINVAL; + goto failed; + } + + func = sdiodev->func; + + sdio_claim_host(func); + + func->enable_timeout = 0; + + ret = sdio_enable_func(func); + if (ret) { + //this is ok, since the ble is not up yet so SDIO_CCCR_IOEx + //is not set on this sage + BT_DBG("[bt sdio] sdio_enable_func: %d failed: ret=%d",\ + func->num, ret); + } else { + BT_INFO("[bt sdio] sdio_enable_func: %d success", func->num); + } + + //set block size + ret = sdio_set_block_size(sdiodev->func, SDIO_BLOCK_SIZE); + if (ret) { + BT_ERR("[bt sdio] cannot set SDIO block size"); + ret = -EIO; + goto unreg_device; + } + + //clear interrupt, write to clear + ret = btti_sdio_clr_irq(sdiodev); + + //read status --not in use + reg = sdio_readb(func, sdiodev->reg_map->bt_mode_status, &ret); + if (ret < 0) { + BT_ERR("[bt sdio] Failed to read bt_mode_status "); + ret = -EIO; + goto unreg_device; + } + sdiodev->bt_mode_status = ret; + + BT_DBG("[bt sdio] SDIO FUNC%d IO port: 0x%x BT MODE: 0x%x",\ + func->num, sdiodev->reg_map->sdio_rt_data,\ + sdiodev->bt_mode_status); + + sdio_set_drvdata(func, sdiodev); + + sdio_release_host(func); + + return 0; + +unreg_device: + sdio_release_host(func); + btti_sdio_unregister_dev(func); + return ret; +failed: + return ret; + +} + +static int btti_sdio_unregister_dev(struct sdio_func *func) +{ + BT_INFO("[bt sdio] btti_sdio_unregister_dev "); + + if (func) { + sdio_claim_host(func); + BT_DBG("[bt sdio] sdio_release_irq"); + sdio_release_irq(func); + sdio_disable_func(func); + sdio_set_drvdata(func, NULL); + sdio_release_host(func); + } + + return 0; +} + +static int btti_sdio_enable_int(struct btti_sdio_dev *sdiodev) +{ + int ret; + + if (!sdiodev || !sdiodev->func) + return -EINVAL; + + sdio_claim_host(sdiodev->func); + + ret = btti_sdio_enable_func_interrupt(sdiodev, INTRPT_ENABLE_MASk); + + sdio_release_host(sdiodev->func); + + return ret; +} + +static int btti_sdio_disable_int(struct btti_sdio_dev *sdiodev) +{ + int ret; + + if (!sdiodev || !sdiodev->func) + return -EINVAL; + + sdio_claim_host(sdiodev->func); + + ret = btti_sdio_disable_func_interrupt(sdiodev, INTRPT_ENABLE_MASk); + + sdio_release_host(sdiodev->func); + + return ret; +} + + + +static void btti_sdio_dump_regs(struct btti_private *private_data) +{ + struct btti_sdio_dev *sdiodev = private_data->btti_dev.sdiodev; + int ret = 0; + unsigned int reg, reg_start, reg_end; + char buf[256], *ptr; + u8 loop, func, data; + int MAX_LOOP = 2; + + btti_sdio_power_up_fw(private_data); + sdio_claim_host(sdiodev->func); + + for (loop = 0; loop < MAX_LOOP; loop++) { + memset(buf, 0, sizeof(buf)); + ptr = buf; + + if (loop == 0) { + /* Read the registers of SDIO function0 */ + func = loop; + reg_start = 0; + reg_end = 9; + } else { + func = 2; + reg_start = 0; + reg_end = 0x09; + } + + ptr += sprintf(ptr, "[bt sdio] SDIO Func%d (%#x-%#x): ", + func, reg_start, reg_end); + for (reg = reg_start; reg <= reg_end; reg++) { + if (func == 0) + data = sdio_f0_readb(sdiodev->func, reg, &ret); + else + data = sdio_readb(sdiodev->func, reg, &ret); + + if (!ret) { + ptr += sprintf(ptr, "%02x ", data); + } else { + ptr += sprintf(ptr, "ERR"); + break; + } + } + + BT_INFO("%s", buf); + } + + sdio_release_host(sdiodev->func); +} + +/* This function dump sdio register and memory data */ +static void btti_sdio_coredump(struct device *dev) +{ + struct sdio_func *func = dev_to_sdio_func(dev); + struct btti_sdio_dev *sdiodev; + struct btti_private *private_data; + + sdiodev = sdio_get_drvdata(func); + if (sdiodev) { + private_data = sdiodev->private_data; + if (!private_data) { + BT_ERR("[bt sdio] private_data is not allocated"); + return; + } + } else { + BT_ERR("[bt sdio] no sdiodev"); + return; + } + + /* dump sdio register first */ + btti_sdio_dump_regs(private_data); +} +static int btti_sdio_power_up_fw(struct btti_private *private_data) +{ + struct btti_sdio_dev *sdiodev = private_data->btti_dev.sdiodev; + int ret = 0; + + BT_DBG("[bt sdio] power up FW"); + + if (!sdiodev || !sdiodev->func) { + BT_ERR("[bt sdio] sdiodev or function is NULL!"); + return -EINVAL; + } + + sdio_claim_host(sdiodev->func); + + // BLE firmware remains awake , force Lx to remain awake; + sdio_f0_writeb(sdiodev->func, HOST_POWER_UP_MASK,\ + sdiodev->reg_map->sdio_wup_ble, &ret); + if (ret) { + BT_ERR("[bt sdio] Unable to power up ble firmware!"); + ret = -EIO; + } + + sdio_release_host(sdiodev->func); + + BT_INFO("[bt sdio] wake up firmware"); + + return ret; +} + +static int btti_sdio_power_dn_fw(struct btti_private *private_data) +{ + struct btti_sdio_dev *sdiodev = private_data->btti_dev.sdiodev; + int ret = 0; + + BT_DBG("[bt sdio] power up FW"); + + if (!sdiodev || !sdiodev->func) { + BT_ERR("[bt sdio] sdiodev or function is NULL!"); + return -EINVAL; + } + + sdio_claim_host(sdiodev->func); + + // Lx Core can go to sleep (from host perspective) + sdio_f0_writeb(sdiodev->func, ~HOST_POWER_UP_MASK,\ + sdiodev->reg_map->sdio_wup_ble, &ret); + if (ret) { + BT_ERR("[bt sdio] Unable to power down ble firmware!"); + ret = -EIO; + } + + sdio_release_host(sdiodev->func); + + BT_INFO("[bt sdio] wake up firmware"); + + return ret; +} +static void btti_sdio_irq_handler(struct sdio_func *func) +{ + struct btti_private *private_data; + struct btti_sdio_dev *sdiodev; + ulong flags; + int ret; + + BT_INFO("[bt sdio] RX btti_sdio_irq_handler received"); + + sdiodev = sdio_get_drvdata(func); + if (!sdiodev || !sdiodev->private_data) { + BT_ERR("[bt sdio] RX btti_hci_irq_handler(%d) "\ + "%p sdiodev or private_data is NULL,"\ + " sdiodev=%p", + func->num, func, sdiodev); + return; + } + + private_data = sdiodev->private_data; + + if (private_data->sdio_dev_removed) { + BT_ERR("[bt sdio] RX sdio_dev_removed"); + return; + } + + sdio_claim_host(func); + + //clear interrupt + ret = btti_sdio_clr_irq(sdiodev); + + sdio_release_host(func); + + if (ret) { + BT_ERR("[bt sdio] RX btti_sdio_irq_handler:failed to clear"); + return; + } + + spin_lock_irqsave(&private_data->irq_cnt_lock, flags); + sdiodev->Intrpt_triggered = 1;// signal that interrupt happened + spin_unlock_irqrestore(&private_data->irq_cnt_lock, flags); + + + btti_hci_irq_handler(private_data); +} + + +//rx +static int btti_sdio_rx_packet(struct btti_private *private_data) +{ + u32 packet_len = 0; + int ret; + u32 data_read_size; + struct sk_buff *skb = NULL; + u32 packet_type; + + struct hci_dev *hdev = private_data->btti_dev.hcidev; + struct btti_sdio_dev *sdiodev = private_data->btti_dev.sdiodev; + u8 *sdio_header = sdiodev->sdio_header; + + if (!sdiodev || !sdiodev->func) { + BT_ERR("[bt sdio] RX sdiodev or function is NULL!"); + ret = -EINVAL; + goto exit; + } + + //Read the length of data to be transferred + ret = sdio_readsb(sdiodev->func, sdio_header, \ + sdiodev->reg_map->sdio_rt_data, SDIO_HEADER_LEN); + if (ret < 0) { + BT_ERR("[bt sdio] RX read rx_len failed"); + ret = -EIO; + goto exit; + } + + packet_len = \ + sdio_header[0] | (sdio_header[1] << 8) | (sdio_header[2] << 16); + packet_type = sdio_header[3]; + + BT_INFO("[bt sdio] RX packet_len:%d packet_type:%d "\ + "packet header hex: %*ph", packet_len, packet_type,\ + SDIO_HEADER_LEN, sdio_header); + + if ((packet_len <= SDIO_HEADER_LEN)\ + || (packet_len > HCI_MAX_FRAME_SIZE)) { + BT_ERR("[bt sdio] RX packet length: %d not HCI"\ + " valid length", packet_len); + ret = -EINVAL; + goto exit; + } + + + if (packet_len > (TIDRV_SIZE_OF_CMD_BUFFER+SDIO_HEADER_LEN)) { + BT_WARN("[bt sdio] RX packet length: %d not supported",\ + packet_len); + } + + data_read_size = roundup((packet_len - SDIO_HEADER_LEN),\ + BTSDIO_RX_ALIGN); + + + skb = bt_skb_alloc(data_read_size, GFP_KERNEL); + if (!skb) { + /* Out of memory. Prepare a read retry and just + * return with the expectation that the next time + * we're called we'll have more memory. + */ + BT_ERR("[bt sdio] No free skb"); + ret = -ENOMEM; + goto exit; + } + + skb_put(skb, packet_len-SDIO_HEADER_LEN); + + ret = sdio_readsb(sdiodev->func, skb->data,\ + sdiodev->reg_map->sdio_rt_data, data_read_size); + if (ret < 0) { + BT_ERR("[bt sdio] RX sdio_readsb failed: %d, size read:%d",\ + ret, data_read_size); + ret = -EIO; + goto exit; + } + BT_INFO("[bt sdio] RX packet , packet data(without header) hex: %*ph",\ + data_read_size, skb->data); + + switch (packet_type) { + case HCI_ACLDATA_PKT: + case HCI_SCODATA_PKT: + case HCI_EVENT_PKT: + if (hdev != NULL) { + btti_acknldg_packet(sdiodev, 0);//ack + hdev->stat.byte_rx += data_read_size; + hci_skb_pkt_type(skb) = packet_type; + + ret = hci_recv_frame(hdev, skb); + if (ret < 0) { + BT_ERR("[bt sdio] RX hci_recv_frame" + " failed :%d ", ret); + } + ret = 0; + } else + ret = -EPERM; + + //no need to free the skb in here, it is freed at hci_recv_frame + break; + + case HCI_VENDOR_PKT: + BT_INFO("[bt sdio] vendor packet received"); + ret = btti_handle_rx_vendor_event(private_data, skb); + if (!ret) { + //if hdev was just created read it + hdev = private_data->btti_dev.hcidev; + if (hdev != NULL) { + btti_acknldg_packet(sdiodev, 0);//ack + BT_INFO("[bt sdio] Hdev was created"); + hdev->stat.byte_rx += data_read_size; + hci_skb_pkt_type(skb) = HCI_EVENT_PKT; + ret = hci_recv_frame(hdev, skb); + if (ret < 0) { + BT_ERR("[bt sdio] vendor RX " + "hci_recv_frame " + "failed :%d ", ret); + } + //no need to free the skb in here, + //it is freed at hci_recv_frame + ret = 0; + } else + ret = -EPERM; + } + break; + + + default: + BT_ERR("[bt sdio] RX Unknown packet packet_type:%d",\ + packet_type); + ret = -ENOENT; + break; + } + +exit: + //send nack + if (ret) { + if (hdev) + hdev->stat.err_rx++; + kfree_skb(skb); + skb = NULL; + btti_acknldg_packet(sdiodev, 1);//nack + } + return ret; +} + +static void btti_acknldg_packet(struct btti_sdio_dev *sdiodev, u8 Ack) +{ + int retACK = 0; + + //ack the packet, HCI will release the skb + BT_DBG("[bt sdio] RX sdio_writesb: send ACK "); + sdio_writeb(sdiodev->func, Ack,\ + sdiodev->reg_map->sdio_pc_rrt, &retACK); + if (retACK && (Ack == 0)) { + BT_ERR("[bt sdio] RX sdio_writesb:"\ + " send ACK failed: %d", retACK); + } + if (retACK && (Ack == 1)) { + BT_ERR("[bt sdio] RX sdio_writesb:"\ + " send NACK failed: %d", retACK); + } +} + + + +static int btti_handle_rx_vendor_event(struct btti_private *private_data, + struct sk_buff *skb) +{ + int ret = 0; + struct btti_vendor_event *vendor_event; + vendor_event = (struct btti_vendor_event *)skb->data; + switch (vendor_event->event_opcode) { + case BTTI_BLE_FIRMWARE_UP: + BT_INFO("[bt sdio] vendor packet- ble is up"); + private_data->hci_adapter->ble_enable = 1; + if (btti_hci_register_hdev(private_data)) { + BT_ERR("[bt sdio] Register hdev failed!"); + ret = -ENODEV; + } + BT_INFO("[bt sdio] registered to HCI"); + + break; + default: + BT_ERR("[bt sdio] unsupported rx vendor event code:"\ + " %d", vendor_event->event_code); + ret = -EINVAL; + break; + } + + return ret; + +} +//tx +//packet_len, the length includes the header. +static int btti_sdio_tx_packet(struct btti_private *private_data, + struct sk_buff *skb) +{ + struct btti_sdio_dev *sdiodev = private_data->btti_dev.sdiodev; + int ret = 0; + int i = 0; + void *tmpbuf = NULL; + u32 data_send_size = 0; + u32 packet_len; + char *payload; + bool alignment_required; + + + BT_DBG("[bt sdio] TX btti_sdio_tx_packet"); + + if (!sdiodev || !sdiodev->func) { + BT_ERR("[bt sdio] sdiodev or function is NULL!"); + return -EINVAL; + } + + packet_len = skb->len; + payload = skb->data; + data_send_size = roundup(packet_len, BTSDIO_TX_ALIGN); + alignment_required = (data_send_size != packet_len); + + if (alignment_required) { + tmpbuf = kzalloc(data_send_size, GFP_KERNEL); + if (!tmpbuf) { + BT_ERR("[bt sdio] TX allocation failed"); + return -ENOMEM; + } + memcpy(tmpbuf, payload, data_send_size); + } else { + tmpbuf = payload; + } + + pm_runtime_get_sync(&sdiodev->func->dev); + + sdio_claim_host(sdiodev->func); + do { + /* Transfer data to device */ + ret = sdio_writesb(sdiodev->func,\ + sdiodev->reg_map->sdio_rt_data, tmpbuf,\ + data_send_size); + if (ret < 0) { + i++; + BT_ERR("[bt sdio] TX i=%d writesb failed: %d", i, ret); + BT_ERR("[bt sdio] TX data_send_size: %d hex: %*ph",\ + data_send_size, data_send_size, tmpbuf); + ret = -EIO; + if (i > MAX_SDIO_TX_RETRY) + goto exit; + } + BT_INFO("[bt sdio] TX to SDIO sdiodev done : %*ph ",\ + data_send_size, tmpbuf); + + } while (ret); + +exit: + sdio_release_host(sdiodev->func); + + if (alignment_required) + kfree(tmpbuf); + + pm_runtime_mark_last_busy(&sdiodev->func->dev); + pm_runtime_put_autosuspend(&sdiodev->func->dev); + + if (ret) { + private_data->btti_dev.hcidev->stat.err_tx++; + } else { + private_data->btti_dev.hcidev->stat.byte_tx\ + += data_send_size; + } + kfree_skb(skb); + return ret; +} + + +static int btti_sdio_if_probe(struct sdio_func *func, + const struct sdio_device_id *id) +{ + int ret = 0; + struct btti_private *private_data = NULL; + struct btti_sdio_dev *sdiodev = NULL; + + BT_INFO("[bt sdio] PROBE vendor=0x%x, device=0x%x,"\ + " class=%d, fn=%d 0x%lx", + id->vendor, id->device, id->class, func->num,\ + (unsigned long)func); + + /* We are only able to handle the wlan function */ + if (func->num != 0x01) { + BT_DBG("[bt sdio] PROBE incorrect function number!"); + ret = -ENODEV; + return ret; + } + + /* Device tree node parsing */ + if (btti_sdio_if_probe_of(&func->dev)) { + ret = -ENODEV; + return ret; + } + + sdiodev = devm_kzalloc(&func->dev, sizeof(*sdiodev), GFP_KERNEL); + if (!sdiodev) { + ret = -ENODEV; + return ret; + } + + sdiodev->func = func; + sdiodev->private_data = NULL; + + if (id->driver_data) { + struct btti_sdio_device *data = (void *) id->driver_data; + sdiodev->reg_map = data->reg_map; + } + + if (btti_sdio_register_dev(sdiodev) < 0) { + BT_ERR("[bt sdio] PROBE Failed to register BT device!"); + ret = -ENODEV; + goto remove_device; + } + //enable interrupts + btti_sdio_enable_int(sdiodev); + + private_data = btti_hci_add_sdio_dev(sdiodev); + if (!private_data) { + BT_ERR("[bt sdio] PROBE Initializing sdiodev failed!"); + ret = -ENODEV; + goto remove_device; + } + + sdiodev->private_data = private_data; + + /* Initialize the interface specific function pointers */ + private_data->card_tx_packet_funcp = btti_sdio_tx_packet; + private_data->card_power_up_firmware_funcp = btti_sdio_power_up_fw; + private_data->card_power_dn_firmware_funcp = btti_sdio_power_dn_fw; + private_data->card_process_rx_funcp = btti_sdio_process_rx; + + + /* pm_runtime_enable would be done after the firmware is being + * downloaded because the core layer probably already enables + * runtime PM for this func such as the case host->caps & + * MMC_CAP_POWER_OFF_CARD. + */ + if (pm_runtime_enabled(&sdiodev->func->dev)) + pm_runtime_disable(&sdiodev->func->dev); + + /* As explaination in drivers/mmc/core/sdio_bus.c tells us: + * Unbound SDIO functions are always suspended. + * During probe, the function is set active and the usage count + * is incremented. If the driver supports runtime PM, + * it should call pm_runtime_put_noidle() in its probe routine and + * pm_runtime_get_noresume() in its remove routine. + * + * So, put a pm_runtime_put_noidle here ! + */ + pm_runtime_put_noidle(&sdiodev->func->dev); + + BT_DBG("[bt sdio] PROBE sdio_claim_irq"); + sdio_claim_host(func); + ret = sdio_claim_irq(func, btti_sdio_irq_handler); + sdio_release_host(func); + + if (ret) { + BT_ERR("[bt sdio] PROBE sdio_claim_irq failed: ret=%d", ret); + ret = -EIO; + goto remove_device; + } + + + BT_INFO("[bt sdio] TI cc33xx BLE-over-SDIO driver is up and running!"); + + return 0; + +/*disable_sdio_dev_int: + btti_sdio_disable_int(sdiodev); + btti_sdio_unregister_dev(func);*/ +remove_device: + btti_sdio_if_remove(func); + return ret; +} + +static void btti_sdio_if_remove(struct sdio_func *func) +{ + struct btti_sdio_dev *sdiodev; + BT_INFO("[bt sdio if] sdio remove"); + + if (func != NULL) { + sdiodev = sdio_get_drvdata(func); + if (sdiodev != NULL) { + BT_INFO("[bt sdio] disable interrupt"); + btti_sdio_disable_int(sdiodev); + if (sdiodev->private_data != NULL) { + sdiodev->private_data->sdio_dev_removed = true; + btti_hci_remove_sdio_dev(sdiodev->private_data); + } else { + BT_ERR("[bt sdio] private_data was "\ + "not allocated"); + } + } + btti_sdio_unregister_dev(func); + } + /* Be consistent the state in btti_sdio_if_probe */ + pm_runtime_get_noresume(&func->dev); + +} + +static int btti_sdio_if_suspend(struct device *dev) +{ + struct sdio_func *func = dev_to_sdio_func(dev); + struct btti_sdio_dev *sdiodev; + struct btti_private *private_data; + mmc_pm_flag_t pm_flags; + struct hci_dev *hcidev; + + BT_INFO("[bt sdio] suspend"); + if (func) { + pm_flags = sdio_get_host_pm_caps(func); + BT_INFO("[bt sdio] %s: suspend: PM flags = 0x%x",\ + sdio_func_id(func), + pm_flags); + if (!(pm_flags & MMC_PM_KEEP_POWER)) { + BT_ERR("[bt sdio] %s: cannot remain"\ + " alive while suspended", + sdio_func_id(func)); + return -ENOSYS; + } + //sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER); + + sdiodev = sdio_get_drvdata(func); + if (!sdiodev || !sdiodev->private_data) { + BT_ERR("[bt sdio] sdiodev or private_data"\ + " structure is not valid"); + return 0; + } + } else { + BT_ERR("[bt sdio] sdio_func is not specified"); + return 0; + } + + private_data = sdiodev->private_data; + private_data->hci_adapter->is_suspending = true; + hcidev = private_data->btti_dev.hcidev; + BT_DBG("[bt sdio] %s: SDIO suspend", hcidev->name); + hci_suspend_dev(hcidev); + private_data->hci_adapter->is_suspending = false; + private_data->hci_adapter->is_suspended = true; + + //if(private_data->card_power_dn_firmware_funcp){ + // private_data->card_power_dn_firmware_funcp(private_data); + //} + + BT_DBG("[bt sdio] suspend end"); + return 0; +} + +static int btti_sdio_if_resume(struct device *dev) +{ + struct sdio_func *func = dev_to_sdio_func(dev); + struct btti_sdio_dev *sdiodev; + struct btti_private *private_data; + mmc_pm_flag_t pm_flags; + struct hci_dev *hcidev; + + BT_INFO("[bt sdio] resume"); + + if (func) { + pm_flags = sdio_get_host_pm_caps(func); + BT_INFO("[bt sdio] %s: resume: PM flags = 0x%x",\ + sdio_func_id(func), + pm_flags); + sdiodev = sdio_get_drvdata(func); + if (!sdiodev || !sdiodev->private_data) { + BT_ERR("[bt sdio] sdiodev or private_data"\ + " structure is not valid"); + return 0; + } + } else { + BT_ERR("[bt sdio] sdio_func is not specified"); + return 0; + } + private_data = sdiodev->private_data; + if (!private_data) { + BT_ERR("[bt sdio] private_data is not allocated"); + return 0; + } + + if (!private_data->hci_adapter->is_suspended) { + BT_WARN("[bt sdio] device already resumed"); + return 0; + } + + //if(private_data->card_power_up_firmware_funcp){ + // private_data->card_power_up_firmware_funcp(private_data); + //} + hcidev = private_data->btti_dev.hcidev; + private_data->hci_adapter->is_suspended = false; + BT_INFO("[bt sdio] %s: SDIO resume", hcidev->name); + hci_resume_dev(hcidev); + + return 0; +} + +static const struct dev_pm_ops btti_sdio_pm_ops = { + .suspend = btti_sdio_if_suspend, + .resume = btti_sdio_if_resume, +}; + +static struct sdio_driver bt_ti_sdio = { + .name = "btti_cc33xx_bt_sdio", + .id_table = btti_sdio_ids, + .probe = btti_sdio_if_probe, + .remove = btti_sdio_if_remove, + .drv = { + .owner = THIS_MODULE, + .coredump = btti_sdio_coredump, + .pm = &btti_sdio_pm_ops, + } +}; + +static int __init btti_sdio_init_module(void) +{ + BT_INFO("[bt sdio] BLE SDIO init module"); + if (sdio_register_driver(&bt_ti_sdio) != 0) { + BT_ERR("[bt sdio] SDIO Driver Registration Failed"); + return -ENODEV; + } + return 0; +} + +static void __exit btti_sdio_exit_module(void) +{ + BT_INFO("[bt sdio] BLE SDIO exit module"); + sdio_unregister_driver(&bt_ti_sdio); +} + +module_init(btti_sdio_init_module); +module_exit(btti_sdio_exit_module); + +MODULE_AUTHOR("Texas Instruments."); +MODULE_DESCRIPTION("Texas Instruments BT-over-SDIO driver ver " VERSION); +MODULE_VERSION(VERSION); +MODULE_LICENSE("GPL v2"); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/bluetooth/btti_sdio.h v_kernel/drivers/bluetooth/btti_sdio.h --- linux-6.12.57/drivers/bluetooth/btti_sdio.h 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/bluetooth/btti_sdio.h 2026-04-21 11:35:32.574925842 +0200 @@ -0,0 +1,80 @@ +/* + * This file is part of TI BLE over SDIO + * + * Copyright (C) 2022 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + */ + + +#define SDIO_HEADER_LEN 4 + +/* SD block size can not bigger than 64 due to buf size limit in firmware */ +/* define SD block size for data Tx/Rx */ +#define SDIO_BLOCK_SIZE 128 + +#define TIDRV_BT_RX_PACKET_BUFFER_SIZE (HCI_MAX_FRAME_SIZE) +#define TIDRV_SIZE_OF_CMD_BUFFER (251) + +#define MAX_RX_PACKET_SIZE (((min_t (int, TIDRV_BT_RX_PACKET_BUFFER_SIZE, \ + TIDRV_SIZE_OF_CMD_BUFFER) + SDIO_HEADER_LEN \ + + SDIO_BLOCK_SIZE - 1) / SDIO_BLOCK_SIZE) \ + * SDIO_BLOCK_SIZE) + + +/* Max retry number of CMD53 write */ +#define MAX_SDIO_TX_RETRY 2 + +/* register bitmasks */ +#define HOST_POWER_UP_MASK 1 // 1 to power up BLE SDIO firmware wake up bit */ + +#define INTRPT_ENABLE_MASk 1 //interrupt set + +struct btti_sdio_dev_reg_map { + u8 sdio_wup_ble; + u8 sdio_enable_int; + u8 sdio_rt_data; + u8 sdio_cl_int; + u8 bt_mode_status; + u8 sdio_pc_rrt;//ack interrupt +}; + +struct btti_sdio_dev { + struct sdio_func *func; + const struct btti_sdio_dev_reg_map *reg_map; + u8 bt_mode_status;/* the status read from 0x20 address */ + struct btti_private *private_data; + u8 sdio_header[SDIO_HEADER_LEN]; + bool Intrpt_triggered; +}; + +struct btti_sdio_device { + const struct btti_sdio_dev_reg_map *reg_map; +}; + +struct btti_vendor_event { + u8 event_code;//0xFF + u8 total_length;//0x2 + u16 event_opcode;// EOGF = 1 ; ESG = 0 ; CMD + u8 param_00[2];//Data +} __packed; + +//BTTI_BLE_FIRMWARE_UP: EOGF = 1 ; ESG = 0 ; CMD= 42 => opcode = 0x042A +#define BTTI_BLE_FIRMWARE_UP 0x2A04 //on the packet it is 0x042A + +// CC33xx HW FIFOs must be accessed with 32 bit alignment +#define BTSDIO_RX_ALIGN 4 +#define BTSDIO_TX_ALIGN 4 + + +/* Macros for Data Alignment : size */ +#define ALIGN_SZ(p, a) \ + (((p) + ((a) - 1)) & ~((a) - 1)) diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/bluetooth/btti_uart.c v_kernel/drivers/bluetooth/btti_uart.c --- linux-6.12.57/drivers/bluetooth/btti_uart.c 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/bluetooth/btti_uart.c 2026-04-21 11:35:32.575925845 +0200 @@ -0,0 +1,742 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * TI Bluetooth HCI UART driver + * Copyright (C) 2023 Texas Instruments + * + * Acknowledgements: + * This file is based on btuart.c, which was written by Marcel Holtmann. + */ + +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "h4_recv.h" + +#define VERSION "0.84" + +struct btti_uart_vnd { + const struct h4_recv_pkt *recv_pkts; + int recv_pkts_cnt; + unsigned int manufacturer; +}; + +enum state{ + STATE_PROBING = 0, + STATE_HW_OFF, + STATE_HW_ON, + STATE_HW_READY, + STATE_REMOVED +}; + +static const char *sm_state_to_string(enum state state) +{ + switch (state) { + case STATE_PROBING: + return "STATE_PROBING"; + case STATE_HW_OFF: + return "STATE_HW_OFF"; + case STATE_HW_ON: + return "STATE_HW_ON"; + case STATE_HW_READY: + return "STATE_HW_READY"; + case STATE_REMOVED: + return "STATE_REMOVED"; + } + + return "Illegal state value"; +}; + +enum sm_event { + EVENT_PROBE_DONE, + EVENT_REMOVE, + EVENT_REGULATOR_ENABLE, + EVENT_REGULATOR_DISABLE, + EVENT_HCI_WAKEUP_FRAME_RECEIVED, +}; + +static const char *event_to_string(enum sm_event event) +{ + switch (event) { + case EVENT_PROBE_DONE: + return "EVENT_PROBE_DONE"; + case EVENT_REMOVE: + return "EVENT_REMOVE"; + case EVENT_REGULATOR_ENABLE: + return "EVENT_REGULATOR_ENABLE"; + case EVENT_REGULATOR_DISABLE: + return "EVENT_REGULATOR_DISABLE"; + case EVENT_HCI_WAKEUP_FRAME_RECEIVED: + return "EVENT_HCI_WAKEUP_FRAME_RECEIVED"; + } + + return "Illegal event value"; +}; + +struct btti_uart_dev { + struct hci_dev *hdev; + struct serdev_device *serdev; + struct regulator *reg; + struct notifier_block nb; + + struct work_struct tx_work; + struct sk_buff_head txq; + + struct work_struct btti_uart_sm_work; + struct llist_head sm_event_list; + enum state sm_state; + + struct sk_buff *rx_skb; + + const struct btti_uart_vnd *vnd; + + struct gpio_desc *host_wakeup; + + struct pinctrl *pinctrl; + struct pinctrl_state *pins_runtime; + struct pinctrl_state *pins_sleep; +}; + +struct event_node { + struct llist_node node; + enum sm_event event; +}; + +static int serial_open(struct btti_uart_dev *bdev) +{ + struct serdev_device *serdev = bdev->serdev; + bool disable_flow_control = false; + u32 max_speed = 3000000; + int ret = 0; + + ret = serdev_device_open(serdev); + if (ret) { + dev_err(&serdev->dev, "Cannot open serial port (%d)", ret); + return ret; + } + + of_property_read_u32(serdev->dev.of_node, "max-speed", &max_speed); + disable_flow_control = of_property_read_bool(serdev->dev.of_node, "disable-flow-control"); + + serdev_device_set_baudrate(serdev, max_speed); + if (disable_flow_control) + serdev_device_set_flow_control(serdev, false); + + if (bdev->host_wakeup) + pm_runtime_enable(&serdev->dev); + + return ret; +} + +static void serial_close(struct btti_uart_dev *bdev) +{ + struct serdev_device *serdev = bdev->serdev; + + if (bdev->host_wakeup) + pm_runtime_disable(&serdev->dev); + + serdev_device_close(serdev); +} + +static int btti_uart_open(struct hci_dev *hdev) +{ + return 0; +} + +static int btti_uart_close(struct hci_dev *hdev) +{ + return 0; +} + +static int btti_uart_flush(struct hci_dev *hdev) +{ + struct btti_uart_dev *bdev = hci_get_drvdata(hdev); + + /* Flush any pending characters */ + serdev_device_write_flush(bdev->serdev); + skb_queue_purge(&bdev->txq); + + cancel_work_sync(&bdev->tx_work); + + kfree_skb(bdev->rx_skb); + bdev->rx_skb = NULL; + + return 0; +} + +static int btti_uart_setup(struct hci_dev *hdev) +{ + return 0; +} + +static int btti_uart_tx_wakeup(struct btti_uart_dev *bdev) +{ + schedule_work(&bdev->tx_work); + return 0; +} + +static int btti_uart_send_frame(struct hci_dev *hdev, struct sk_buff *skb) +{ + struct btti_uart_dev *bdev = hci_get_drvdata(hdev); + + /* Prepend skb with frame type */ + memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); + skb_queue_tail(&bdev->txq, skb); + + btti_uart_tx_wakeup(bdev); + return 0; +} + +static int btti_uart_register_hci_device(struct btti_uart_dev *bdev) +{ + struct serdev_device *serdev = bdev->serdev; + struct hci_dev *hdev; + int ret; + + hdev = hci_alloc_dev(); + if (!hdev) { + dev_err(&serdev->dev, "Can't allocate HCI device"); + return -ENOMEM; + } + + hci_set_drvdata(hdev, bdev); + hdev->bus = HCI_UART; + hdev->open = btti_uart_open; + hdev->close = btti_uart_close; + hdev->flush = btti_uart_flush; + hdev->setup = btti_uart_setup; + hdev->send = btti_uart_send_frame; + SET_HCIDEV_DEV(hdev, &serdev->dev); + + ret = hci_register_dev(hdev); + if (ret) { + dev_err(&serdev->dev, "Can't register HCI device (%d)", ret); + hci_free_dev(hdev); + hdev = NULL; + } + + bdev->hdev = hdev; + return ret; +} + +static void btti_uart_unregister_device(struct btti_uart_dev *bdev) +{ + struct hci_dev *hdev = bdev->hdev; + + hci_unregister_dev(hdev); + hci_free_dev(hdev); + + bdev->hdev = NULL; +} + +static void btti_uart_tx_work(struct work_struct *work) +{ + struct btti_uart_dev *bdev = container_of(work, struct btti_uart_dev, + tx_work); + struct serdev_device *serdev = bdev->serdev; + struct hci_dev *hdev = bdev->hdev; + + while (1) { + struct sk_buff *skb = skb_dequeue(&bdev->txq); + int len; + + if (!skb) + break; + + len = serdev_device_write_buf(serdev, skb->data, + skb->len); + hdev->stat.byte_tx += len; + + skb_pull(skb, len); + if (skb->len > 0) { + skb_queue_head(&bdev->txq, skb); + break; + } + + switch (hci_skb_pkt_type(skb)) { + case HCI_COMMAND_PKT: + hdev->stat.cmd_tx++; + break; + case HCI_ACLDATA_PKT: + hdev->stat.acl_tx++; + break; + case HCI_SCODATA_PKT: + hdev->stat.sco_tx++; + break; + } + + kfree_skb(skb); + } +} + +static void unexpected_event(struct serdev_device *serdev, + enum state state, enum sm_event event) +{ + dev_err(&serdev->dev, "Unexpected event %s at state %s", + event_to_string(event), sm_state_to_string(state)); + WARN_ON(1); +} + +static void btti_uart_sm_post_event(struct btti_uart_dev *bdev, enum sm_event event) +{ + struct event_node *event_node; + + event_node = kzalloc(sizeof(*event_node), GFP_KERNEL); + if (unlikely(!event_node)) { + dev_err(&bdev->serdev->dev, "Event allocation failure"); + return; + } + + event_node->event = event; + + llist_add(&event_node->node, &bdev->sm_event_list); + schedule_work(&bdev->btti_uart_sm_work); +} + +static void sm_process(struct btti_uart_dev *bdev, enum sm_event event) +{ + struct serdev_device *serdev = bdev->serdev; + enum state next_state = bdev->sm_state; + + switch (bdev->sm_state) { + case STATE_PROBING: + switch (event) { + case EVENT_PROBE_DONE: + if (regulator_is_enabled(bdev->reg)) + btti_uart_sm_post_event(bdev, EVENT_REGULATOR_ENABLE); + + next_state = STATE_HW_OFF; + break; + + default: + unexpected_event(serdev, bdev->sm_state, event); + } + break; + + case STATE_HW_OFF: + switch (event) { + case EVENT_REGULATOR_ENABLE: + if (0 == serial_open(bdev)) + next_state = STATE_HW_ON; + else + dev_err(&serdev->dev, "Could not open serial port"); + break; + + case EVENT_REMOVE: + next_state = STATE_REMOVED; + break; + + case EVENT_REGULATOR_DISABLE: + break; + + default: + unexpected_event(serdev, bdev->sm_state, event); + } + break; + + case STATE_HW_ON: + switch (event) { + case EVENT_REMOVE: + case EVENT_REGULATOR_DISABLE: + serial_close(bdev); + next_state = (event == EVENT_REMOVE) ? + STATE_REMOVED : STATE_HW_OFF; + break; + + case EVENT_HCI_WAKEUP_FRAME_RECEIVED: + if (0 == btti_uart_register_hci_device(bdev)) + next_state = STATE_HW_READY; + break; + + case EVENT_REGULATOR_ENABLE: + break; + + default: + unexpected_event(serdev, bdev->sm_state, event); + } + break; + + case STATE_HW_READY: + switch (event) { + case EVENT_REMOVE: + case EVENT_REGULATOR_DISABLE: + btti_uart_unregister_device(bdev); + serial_close(bdev); + next_state = (event == EVENT_REMOVE) ? + STATE_REMOVED : STATE_HW_OFF; + break; + + case EVENT_REGULATOR_ENABLE: + break; + + default: + unexpected_event(serdev, bdev->sm_state, event); + } + break; + + case STATE_REMOVED: + switch (event) { + case EVENT_REGULATOR_DISABLE: + case EVENT_REGULATOR_ENABLE: + case EVENT_HCI_WAKEUP_FRAME_RECEIVED: + break; + + default: + unexpected_event(serdev, bdev->sm_state, event); + } + break; + } + + dev_dbg(&serdev->dev, + "SM: Got %s, moving from %s to %s", + event_to_string(event), sm_state_to_string(bdev->sm_state), + sm_state_to_string(next_state)); + + bdev->sm_state = next_state; +} + +static inline struct llist_node *get_event_list(struct btti_uart_dev *bdev) +{ + struct llist_node *node; + + node = llist_del_all(&bdev->sm_event_list); + if (!node) + return NULL; + + return llist_reverse_order(node); +} + +static void btti_uart_sm_work(struct work_struct *work) +{ + struct btti_uart_dev *bdev; + struct event_node *event_node, *tmp; + struct llist_node *event_list; + + bdev = container_of(work, struct btti_uart_dev, btti_uart_sm_work); + event_list = get_event_list(bdev); + + llist_for_each_entry_safe(event_node, tmp, event_list, node) { + sm_process(bdev, event_node->event); + kfree(event_node); + } +} + +static int btti_uart_wakeup_event_match(struct serdev_device *serdev, + const u8 *data, size_t count) +{ + struct btti_uart_dev *bdev = serdev_device_get_drvdata(serdev); + const u8 hw_wakeup_evt[] = {HCI_VENDOR_PKT, 0xff, 0x02, 0x04, 0x2a, 0x00, 0x00}; + + if (count < sizeof hw_wakeup_evt) + return 0; // Reject data until all bytes have been received + + if (count > sizeof hw_wakeup_evt) + goto error; + + if (0 != memcmp(&hw_wakeup_evt, data, sizeof hw_wakeup_evt)) + goto error; + + btti_uart_sm_post_event(bdev, EVENT_HCI_WAKEUP_FRAME_RECEIVED); + return count; + +error: + dev_err(&serdev->dev, "Unexpected wakeup pattern"); + print_hex_dump(KERN_DEBUG, "Pattern:", + DUMP_PREFIX_NONE, 16, 1, data, count, true); + return count; +} + +static size_t btti_uart_receive_buf(struct serdev_device *serdev, const u8 *data, + size_t count) +{ + struct btti_uart_dev *bdev = serdev_device_get_drvdata(serdev); + const struct btti_uart_vnd *vnd = bdev->vnd; + + if (unlikely(!bdev->hdev)) { + // Accept only wakeup event until driver is registered with HCI + return btti_uart_wakeup_event_match(serdev, data, count); + } + + bdev->rx_skb = h4_recv_buf(bdev->hdev, bdev->rx_skb, data, count, + vnd->recv_pkts, vnd->recv_pkts_cnt); + if (IS_ERR(bdev->rx_skb)) { + int err = PTR_ERR(bdev->rx_skb); + dev_err(&serdev->dev, "Frame reassembly failed (%d)", err); + bdev->rx_skb = NULL; + print_hex_dump(KERN_DEBUG, "Frame:", DUMP_PREFIX_NONE, + 16, 1, data, count, true); + return 0; + } + + bdev->hdev->stat.byte_rx += count; + + return count; +} + +static void btti_uart_write_wakeup(struct serdev_device *serdev) +{ + struct btti_uart_dev *bdev = serdev_device_get_drvdata(serdev); + + btti_uart_tx_wakeup(bdev); +} + +static const struct serdev_device_ops btti_uart_client_ops = { + .receive_buf = btti_uart_receive_buf, + .write_wakeup = btti_uart_write_wakeup, +}; + +static const struct h4_recv_pkt default_recv_pkts[] = { + { H4_RECV_ACL, .recv = hci_recv_frame }, + { H4_RECV_SCO, .recv = hci_recv_frame }, + { H4_RECV_EVENT, .recv = hci_recv_frame }, +}; + +static const struct btti_uart_vnd default_vnd = { + .recv_pkts = default_recv_pkts, + .recv_pkts_cnt = ARRAY_SIZE(default_recv_pkts), +}; + +static const struct btti_uart_vnd ti_vnd = { + .recv_pkts = default_recv_pkts, + .recv_pkts_cnt = ARRAY_SIZE(default_recv_pkts), + .manufacturer = 13, +}; + +static int btti_uart_regulator_event(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct btti_uart_dev *bdev = container_of(nb, struct btti_uart_dev, nb); + + if (event & REGULATOR_EVENT_DISABLE) { + btti_uart_sm_post_event(bdev, EVENT_REGULATOR_DISABLE); + } + + if (event & REGULATOR_EVENT_ENABLE) { + btti_uart_sm_post_event(bdev, EVENT_REGULATOR_ENABLE); + } + + return NOTIFY_OK; +} + +static irqreturn_t host_wake_irq(int irq, void *data) +{ + struct btti_uart_dev *bdev = data; + struct serdev_device *serdev = bdev->serdev; + + dev_info(&serdev->dev, "CC33xx wake IRQ"); + + pm_wakeup_event(&serdev->dev, 0); + pm_system_wakeup(); + + return IRQ_HANDLED; +} + +static void btti_uart_host_wake_init(struct serdev_device *serdev) +{ + struct btti_uart_dev *bdev = serdev_device_get_drvdata(serdev); + int ret; + + if (!bdev->pinctrl) + goto out_err; + + bdev->pins_sleep = pinctrl_lookup_state(bdev->pinctrl, "sleep"); + if (IS_ERR(bdev->pins_sleep)) + bdev->pins_sleep = NULL; + + bdev->host_wakeup = devm_gpiod_get_optional(&serdev->dev, "host-wakeup", GPIOD_IN); + if (IS_ERR(bdev->host_wakeup)) + goto out_err; + + if (device_init_wakeup(&serdev->dev, true) != 0) + goto out_err; + + ret = devm_request_irq(&serdev->dev, gpiod_to_irq(bdev->host_wakeup), + host_wake_irq, IRQF_TRIGGER_RISING, "btti_host_wake", bdev); + if (ret) + goto out_err; + + ret = enable_irq_wake(gpiod_to_irq(bdev->host_wakeup)); + if (ret < 0) + goto out_err_disable_wake; + + disable_irq(gpiod_to_irq(bdev->host_wakeup)); + + dev_info(&serdev->dev, "Host wakeup enabled"); + return; + + +out_err_disable_wake: + device_init_wakeup(&serdev->dev, false); +out_err: + bdev->host_wakeup = NULL; + bdev->pins_sleep = NULL; + dev_info(&serdev->dev, "Host wakeup NOT enabled"); + return; +} + +static int btti_uart_probe(struct serdev_device *serdev) +{ + struct btti_uart_dev *bdev; + int ret; + + bdev = devm_kzalloc(&serdev->dev, sizeof(*bdev), GFP_KERNEL); + if (!bdev) + return -ENOMEM; + + /* Request the vendor specific data and callbacks */ + bdev->vnd = device_get_match_data(&serdev->dev); + if (!bdev->vnd) + bdev->vnd = &default_vnd; + + bdev->serdev = serdev; + serdev_device_set_drvdata(serdev, bdev); + + /* Using the optional get regulator API as normal get returns a dummy + if the regulator is not found. */ + bdev->reg = devm_regulator_get_optional(&serdev->dev, "cc33xx"); + if (PTR_ERR(bdev->reg) == -EPROBE_DEFER) + return -EPROBE_DEFER; + if (IS_ERR(bdev->reg)) { + dev_err(&serdev->dev, "can't get regulator"); + return PTR_ERR(bdev->reg); + } + + bdev->pinctrl = devm_pinctrl_get(&serdev->dev); + if (!IS_ERR(bdev->pinctrl)) { + bdev->pins_runtime = pinctrl_lookup_state(bdev->pinctrl, "default"); + if (IS_ERR(bdev->pins_runtime)) { + dev_err(&serdev->dev, "can't lookup default pin state"); + return PTR_ERR(bdev->pins_runtime); + } + } else { + bdev->pinctrl = NULL; + bdev->pins_runtime = NULL; + } + + btti_uart_host_wake_init(serdev); + + if (bdev->pins_runtime) + pinctrl_select_state(bdev->pinctrl, bdev->pins_runtime); + + bdev->nb.notifier_call = btti_uart_regulator_event; + + ret = regulator_register_notifier(bdev->reg, &bdev->nb); + if (ret != 0) { + dev_err(&serdev->dev, + "Failed to register regulator notifier (%d)", ret); + return ret; + } + + serdev_device_set_client_ops(serdev, &btti_uart_client_ops); + + INIT_WORK(&bdev->tx_work, btti_uart_tx_work); + skb_queue_head_init(&bdev->txq); + + INIT_WORK(&bdev->btti_uart_sm_work, btti_uart_sm_work); + init_llist_head(&bdev->sm_event_list); + + btti_uart_sm_post_event(bdev, EVENT_PROBE_DONE); + + return 0; +} + +static void btti_uart_remove(struct serdev_device *serdev) +{ + struct btti_uart_dev *bdev = serdev_device_get_drvdata(serdev); + + if (bdev->host_wakeup) { + device_init_wakeup(&serdev->dev, false); + disable_irq_wake(gpiod_to_irq(bdev->host_wakeup)); + } + + regulator_unregister_notifier(bdev->reg, &bdev->nb); + btti_uart_sm_post_event(bdev, EVENT_REMOVE); + flush_work(&bdev->btti_uart_sm_work); +} + +static int btti_suspend_device(struct device *dev) +{ + struct btti_uart_dev *bdev = dev_get_drvdata(dev); + struct serdev_device *serdev = bdev->serdev; + int ret; + + if (bdev->pins_sleep) { + ret = pinctrl_select_state(bdev->pinctrl, bdev->pins_sleep); + if (ret < 0) + goto out_err; + } + + enable_irq(gpiod_to_irq(bdev->host_wakeup)); + + ret = serdev_device_set_rts(serdev, false); + if (ret < 0) + goto out_err; + + return 0; + +out_err: + if (bdev->pins_runtime) + pinctrl_select_state(bdev->pinctrl, bdev->pins_runtime); + + serdev_device_set_rts(serdev, true); + + return ret; +} + +static int btti_resume_device(struct device *dev) +{ + struct btti_uart_dev *bdev = dev_get_drvdata(dev); + struct serdev_device *serdev = bdev->serdev; + int ret; + + disable_irq_nosync(gpiod_to_irq(bdev->host_wakeup)); + + if (bdev->pins_runtime) { + ret = pinctrl_select_state(bdev->pinctrl, bdev->pins_runtime); + if (ret < 0) + return ret; + } + + return serdev_device_set_rts(serdev, true); +} + +#ifdef CONFIG_OF +static const struct of_device_id btti_uart_of_match_table[] = { + { .compatible = "ti,cc33xx-bt", .data = &ti_vnd }, + { } +}; +MODULE_DEVICE_TABLE(of, btti_uart_of_match_table); +#endif + +static const struct dev_pm_ops btti_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(btti_suspend_device, btti_resume_device) +}; + +static struct serdev_device_driver btti_uart_driver = { + .probe = btti_uart_probe, + .remove = btti_uart_remove, + .driver = { + .name = "btti", + .of_match_table = of_match_ptr(btti_uart_of_match_table), + .pm = &btti_pm_ops + }, +}; + +module_serdev_device_driver(btti_uart_driver); + +MODULE_DESCRIPTION("TI Bluetooth UART driver ver " VERSION); +MODULE_VERSION(VERSION); +MODULE_LICENSE("GPL"); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/bluetooth/Kconfig v_kernel/drivers/bluetooth/Kconfig --- linux-6.12.57/drivers/bluetooth/Kconfig 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/bluetooth/Kconfig 2026-04-21 11:35:32.562925811 +0200 @@ -384,6 +384,41 @@ Say Y here to compile support for virtual HCI devices into the kernel or say M to compile it as module (hci_vhci). +config BT_TI + tristate "TI Bluetooth driver support" + help + The core driver to support TI Bluetooth devices. + + Say Y here to compile TI Bluetooth driver + into the kernel or say M to compile it as module. + +config BT_TI_SDIO + tristate "TI BT-over-SDIO driver" + depends on BT_TI && MMC + select FW_LOADER + select WANT_DEV_COREDUMP + help + The driver for TI Bluetooth chipsets with SDIO interface. + + This driver is required if you want to use TI Bluetooth + devices with SDIO interface. + chipsets are supported. + + Say Y here to compile support for TI BT-over-SDIO driver + into the kernel or say M to compile it as module. + +config BT_TI_UART + tristate "TI BT-over-UART driver" + depends on SERIAL_DEV_BUS + help + Bluetooth HCI UART driver for CC33XX TI devices. + This driver is required if you want to use CC33XX device with + UART interface. + Currently does not require BT_TI core. + + Say Y here to compile support for CC33XX UART devices into the + kernel or say M to compile it as module (btuart). + config BT_MRVL tristate "Marvell Bluetooth driver support" help diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/bluetooth/Makefile v_kernel/drivers/bluetooth/Makefile --- linux-6.12.57/drivers/bluetooth/Makefile 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/bluetooth/Makefile 2026-04-21 11:35:32.562925811 +0200 @@ -19,6 +19,9 @@ obj-$(CONFIG_BT_INTEL) += btintel.o obj-$(CONFIG_BT_INTEL_PCIE) += btintel_pcie.o btintel.o obj-$(CONFIG_BT_ATH3K) += ath3k.o +obj-$(CONFIG_BT_TI) += btti.o +obj-$(CONFIG_BT_TI_SDIO) += btti_sdio.o +obj-$(CONFIG_BT_TI_UART) += btti_uart.o obj-$(CONFIG_BT_MRVL) += btmrvl.o obj-$(CONFIG_BT_MRVL_SDIO) += btmrvl_sdio.o obj-$(CONFIG_BT_MTKSDIO) += btmtksdio.o @@ -36,6 +39,9 @@ obj-$(CONFIG_BT_HCIRSI) += btrsi.o +btti-y := btti_main.o +btti-$(CONFIG_DEBUG_FS) += btti_debugfs.o + btmrvl-y := btmrvl_main.o btmrvl-$(CONFIG_DEBUG_FS) += btmrvl_debugfs.o diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/bus/ti-sysc.c v_kernel/drivers/bus/ti-sysc.c --- linux-6.12.57/drivers/bus/ti-sysc.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/bus/ti-sysc.c 2026-04-21 11:35:32.602925916 +0200 @@ -1987,6 +1987,19 @@ sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); } +static void sysc_module_enable_quirk_pruss(struct sysc *ddata) +{ + u32 reg; + + reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); + /* Clearing the SYSC_PRUSS_STANDBY_INIT bit - Updates OCP master + * port configuration to enable memory access outside of the + * PRU-ICSS subsystem. + */ + reg &= (~SYSC_PRUSS_STANDBY_INIT); + sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); +} + static void sysc_init_module_quirks(struct sysc *ddata) { if (ddata->legacy_mode || !ddata->name) @@ -2039,8 +2052,10 @@ ddata->module_disable_quirk = sysc_reset_done_quirk_wdt; } - if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS) + if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS) { + ddata->module_enable_quirk = sysc_module_enable_quirk_pruss; ddata->module_disable_quirk = sysc_module_disable_quirk_pruss; + } } static int sysc_clockdomain_init(struct sysc *ddata) diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/clk/clk.c v_kernel/drivers/clk/clk.c --- linux-6.12.57/drivers/clk/clk.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/clk/clk.c 2026-04-21 11:35:32.718926220 +0200 @@ -2796,6 +2796,33 @@ } EXPORT_SYMBOL_GPL(clk_set_max_rate); +int clk_hw_set_spread_spectrum(struct clk_hw *hw, const struct clk_spread_spectrum *ss_conf) +{ + struct clk_core *core; + int ret; + + if (!hw) + return 0; + + core = hw->core; + + clk_prepare_lock(); + + ret = clk_pm_runtime_get(core); + if (ret) + goto fail; + + if (core->ops->set_spread_spectrum) + ret = core->ops->set_spread_spectrum(hw, ss_conf); + + clk_pm_runtime_put(core); + +fail: + clk_prepare_unlock(); + return ret; +} +EXPORT_SYMBOL_GPL(clk_hw_set_spread_spectrum); + /** * clk_get_parent - return the parent of a clk * @clk: the clk whose parent gets returned diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/clk/clk-conf.c v_kernel/drivers/clk/clk-conf.c --- linux-6.12.57/drivers/clk/clk-conf.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/clk/clk-conf.c 2026-04-21 11:35:32.698926167 +0200 @@ -155,6 +155,71 @@ return 0; } +static int __set_clk_spread_spectrum(struct device_node *node, bool clk_supplier) +{ + struct clk_spread_spectrum *sscs __free(kfree) = NULL; + u32 elem_size = sizeof(struct clk_spread_spectrum); + struct of_phandle_args clkspec; + int rc, count, index; + struct clk *clk; + + /* modfreq, spreadPercent, modmethod */ + count = of_property_count_elems_of_size(node, "assigned-clock-sscs", elem_size); + if (count <= 0) + return 0; + + sscs = kcalloc(count, elem_size, GFP_KERNEL); + if (!sscs) + return -ENOMEM; + + rc = of_property_read_u32_array(node, "assigned-clock-sscs", (u32 *)sscs, + count * 3); + if (rc) + return rc; + + for (index = 0; index < count; index++) { + struct clk_spread_spectrum *conf = &sscs[index]; + struct clk_hw *hw; + + if (!conf->modfreq_hz && !conf->spread_bp && !conf->method) + continue; + + rc = of_parse_phandle_with_args(node, "assigned-clocks", "#clock-cells", + index, &clkspec); + if (rc < 0) { + /* skip empty (null) phandles */ + if (rc == -ENOENT) + continue; + else + return rc; + } + + if (clkspec.np == node && !clk_supplier) { + of_node_put(clkspec.np); + return 0; + } + + clk = of_clk_get_from_provider(&clkspec); + of_node_put(clkspec.np); + if (IS_ERR(clk)) { + if (PTR_ERR(clk) != -EPROBE_DEFER) + pr_warn("clk: couldn't get clock %d for %pOF\n", + index, node); + return PTR_ERR(clk); + } + + hw = __clk_get_hw(clk); + rc = clk_hw_set_spread_spectrum(hw, conf); + if (rc < 0) + pr_err("clk: couldn't set %s clk spread spectrum %u %u %u: %d\n", + __clk_get_name(clk), conf->modfreq_hz, conf->spread_bp, + conf->method, rc); + clk_put(clk); + } + + return 0; +} + /** * of_clk_set_defaults() - parse and set assigned clocks configuration * @node: device node to apply clock settings for @@ -174,6 +239,10 @@ if (!node) return 0; + rc = __set_clk_spread_spectrum(node, clk_supplier); + if (rc < 0) + return rc; + rc = __set_clk_parents(node, clk_supplier); if (rc < 0) return rc; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/clk/keystone/sci-clk.c v_kernel/drivers/clk/keystone/sci-clk.c --- linux-6.12.57/drivers/clk/keystone/sci-clk.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/clk/keystone/sci-clk.c 2026-04-21 11:35:32.750926304 +0200 @@ -42,6 +42,8 @@ * @dev_id: Device index * @clk_id: Clock index * @num_parents: Number of parents for this clock + * @actual_parent: Actual parent + * @rate: Clock rate * @provider: Master clock provider * @flags: Flags for the clock * @node: Link for handling clocks probed via DT @@ -53,6 +55,8 @@ u16 dev_id; u32 clk_id; u32 num_parents; + int actual_parent; + unsigned long rate; struct sci_clk_provider *provider; u8 flags; struct list_head node; @@ -210,7 +214,7 @@ unsigned long parent_rate) { struct sci_clk *clk = to_sci_clk(hw); - + clk->rate = rate; return clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id, clk->clk_id, rate / 10 * 9, rate, rate / 10 * 11); @@ -252,12 +256,38 @@ static int sci_clk_set_parent(struct clk_hw *hw, u8 index) { struct sci_clk *clk = to_sci_clk(hw); + int ret; clk->cached_req = 0; - return clk->provider->ops->set_parent(clk->provider->sci, clk->dev_id, + ret = clk->provider->ops->set_parent(clk->provider->sci, clk->dev_id, clk->clk_id, index + 1 + clk->clk_id); + if (!ret) + clk->actual_parent = index; + + return ret; +} + +/** + * sci_clk_set_spread_spectrum - Set spread spectrum for a TI SCI clock + * @hw: clock to set parent for + * @ss_conf: spread spectrum configuration + * + * Sets the spread spectrum of a TI SCI clock. Return TI SCI protocol status. + */ +static int sci_clk_set_spread_spectrum(struct clk_hw *hw, const struct clk_spread_spectrum *ss_conf) +{ + struct sci_clk *clk = to_sci_clk(hw); + + clk->cached_req = 0; + + if (clk->provider->ops->set_spread_spectrum) + return clk->provider->ops->set_spread_spectrum(clk->provider->sci, clk->dev_id, + clk->clk_id, ss_conf->modfreq_hz, ss_conf->spread_bp, + (u8)ss_conf->method); + + return 0; } static const struct clk_ops sci_clk_ops = { @@ -269,6 +299,7 @@ .set_rate = sci_clk_set_rate, .get_parent = sci_clk_get_parent, .set_parent = sci_clk_set_parent, + .set_spread_spectrum = sci_clk_set_spread_spectrum, }; /** @@ -331,6 +362,8 @@ init.parent_names = (void *)parent_names; } + sci_clk->actual_parent = -1; + init.ops = &sci_clk_ops; init.num_parents = sci_clk->num_parents; sci_clk->hw.init = &init; @@ -639,6 +672,27 @@ } #endif +static int ti_sci_clk_resume_noirq(struct device *dev) +{ + struct sci_clk_provider *provider = dev_get_drvdata(dev); + struct sci_clk **clocks = provider->clocks; + int i; + + if (provider->ops->restore_clk) { + for (i = 0; i < provider->num_clocks; i++) { + if (clocks[i]->actual_parent >= 0) + sci_clk_set_parent(&clocks[i]->hw, clocks[i]->actual_parent); + + if (clocks[i]->rate) + sci_clk_set_rate(&clocks[i]->hw, clocks[i]->rate, 0); + } + } + + return 0; +} + +static DEFINE_NOIRQ_DEV_PM_OPS(sci_clk_pm_ops, NULL, ti_sci_clk_resume_noirq); + /** * ti_sci_clk_probe - Probe function for the TI SCI clock driver * @pdev: platform device pointer to be probed @@ -689,6 +743,8 @@ return ret; } + dev_set_drvdata(dev, provider); + return of_clk_add_hw_provider(np, sci_clk_get, provider); } @@ -711,6 +767,7 @@ .driver = { .name = "ti-sci-clk", .of_match_table = of_match_ptr(ti_sci_clk_of_match), + .pm = pm_sleep_ptr(&sci_clk_pm_ops), }, }; module_platform_driver(ti_sci_clk_driver); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/clocksource/arm_global_timer.c v_kernel/drivers/clocksource/arm_global_timer.c --- linux-6.12.57/drivers/clocksource/arm_global_timer.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/clocksource/arm_global_timer.c 2026-04-21 11:35:35.593933760 +0200 @@ -264,14 +264,13 @@ register_current_timer_delay(>_delay_timer); } -static int __init gt_clocksource_init(void) +static int __init gt_clocksource_init(unsigned int psv) { writel(0, gt_base + GT_CONTROL); writel(0, gt_base + GT_COUNTER0); writel(0, gt_base + GT_COUNTER1); /* set prescaler and enable timer on all the cores */ - writel(FIELD_PREP(GT_CONTROL_PRESCALER_MASK, - CONFIG_ARM_GT_INITIAL_PRESCALER_VAL - 1) | + writel(FIELD_PREP(GT_CONTROL_PRESCALER_MASK, psv - 1) | GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK @@ -339,11 +338,45 @@ return NOTIFY_DONE; } +struct gt_prescaler_config { + const char *compatible; + unsigned long prescaler; +}; + +static const struct gt_prescaler_config gt_prescaler_configs[] = { + /* + * On am43 the global timer clock is a child of the clock used for CPU + * OPPs, so the initial prescaler has to be compatible with all OPPs + * which are 300, 600, 720, 800 and 1000 with a fixed divider of 2, this + * gives us a GCD of 10. Initial frequency is 1000, so the prescaler is + * 50. + */ + { .compatible = "ti,am43", .prescaler = 50 }, + { .compatible = "xlnx,zynq-7000", .prescaler = 2 }, + { .compatible = NULL } +}; + +static unsigned long gt_get_initial_prescaler_value(struct device_node *np) +{ + const struct gt_prescaler_config *config; + + if (CONFIG_ARM_GT_INITIAL_PRESCALER_VAL != 0) + return CONFIG_ARM_GT_INITIAL_PRESCALER_VAL; + + for (config = gt_prescaler_configs; config->compatible; config++) { + if (of_machine_is_compatible(config->compatible)) + return config->prescaler; + } + + return 1; +} + static int __init global_timer_of_register(struct device_node *np) { struct clk *gt_clk; static unsigned long gt_clk_rate; int err; + unsigned long psv; /* * In A9 r2p0 the comparators for each processor with the global timer @@ -379,8 +412,9 @@ goto out_unmap; } + psv = gt_get_initial_prescaler_value(np); gt_clk_rate = clk_get_rate(gt_clk); - gt_target_rate = gt_clk_rate / CONFIG_ARM_GT_INITIAL_PRESCALER_VAL; + gt_target_rate = gt_clk_rate / psv; gt_clk_rate_change_nb.notifier_call = gt_clk_rate_change_cb; err = clk_notifier_register(gt_clk, >_clk_rate_change_nb); @@ -405,7 +439,7 @@ } /* Register and immediately configure the timer on the boot CPU */ - err = gt_clocksource_init(); + err = gt_clocksource_init(psv); if (err) goto out_irq; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/clocksource/Kconfig v_kernel/drivers/clocksource/Kconfig --- linux-6.12.57/drivers/clocksource/Kconfig 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/clocksource/Kconfig 2026-04-21 11:35:35.591933754 +0200 @@ -387,8 +387,7 @@ config ARM_GT_INITIAL_PRESCALER_VAL int "ARM global timer initial prescaler value" - default 2 if ARCH_ZYNQ - default 1 + default 0 depends on ARM_GLOBAL_TIMER help When the ARM global timer initializes, its current rate is declared @@ -398,6 +397,7 @@ bounds about how much the parent clock is allowed to decrease or increase wrt the initial clock value. This affects CPU_FREQ max delta from the initial frequency. + Use 0 to use auto-detection in the driver. config ARM_TIMER_SP804 bool "Support for Dual Timer SP804 module" diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/clocksource/timer-ti-dm.c v_kernel/drivers/clocksource/timer-ti-dm.c --- linux-6.12.57/drivers/clocksource/timer-ti-dm.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/clocksource/timer-ti-dm.c 2026-04-21 11:35:35.613933812 +0200 @@ -20,15 +20,21 @@ #include #include +#include +#include #include #include +#include #include #include #include #include +#include #include +#include #include #include +#include #include @@ -141,12 +147,30 @@ struct notifier_block nb; struct notifier_block fclk_nb; unsigned long fclk_rate; + + struct dmtimer_clocksource *clksrc; }; static u32 omap_reserved_systimers; static LIST_HEAD(omap_timer_list); static DEFINE_SPINLOCK(dm_timer_lock); +struct dmtimer_clocksource { + struct clocksource dev; + struct dmtimer *timer; + unsigned int loadval; +}; + +struct omap_dm_timer_clockevent { + struct clock_event_device dev; + struct dmtimer *timer; + u32 period; +}; + +static resource_size_t omap_dm_timer_clocksource_base; +static resource_size_t omap_dm_timer_clockevent_base; +static void __iomem *omap_dm_timer_sched_clock_counter; + enum { REQUEST_ANY = 0, REQUEST_BY_ID, @@ -1073,6 +1097,209 @@ static const struct of_device_id omap_timer_match[]; +static void omap_dm_timer_find_alwon(void) +{ + struct device_node *np; + + if (omap_dm_timer_clocksource_base && omap_dm_timer_clockevent_base) + return; + + for_each_matching_node(np, omap_timer_match) { + struct resource res; + + if (!of_device_is_available(np)) + continue; + + if (!of_property_read_bool(np, "ti,timer-alwon")) + continue; + + if (of_address_to_resource(np, 0, &res)) + continue; + + if (!omap_dm_timer_clocksource_base) { + omap_dm_timer_clocksource_base = res.start; + continue; + } + + if (res.start != omap_dm_timer_clocksource_base) { + omap_dm_timer_clockevent_base = res.start; + + of_node_put(np); + return; + } + } + + if (!omap_dm_timer_clocksource_base) + omap_dm_timer_clocksource_base = -1; + omap_dm_timer_clockevent_base = -1; +} + +static struct dmtimer_clocksource *omap_dm_timer_to_clocksource(struct clocksource *cs) +{ + return container_of(cs, struct dmtimer_clocksource, dev); +} + +static u64 omap_dm_timer_read_cycles(struct clocksource *cs) +{ + struct dmtimer_clocksource *clksrc = omap_dm_timer_to_clocksource(cs); + struct dmtimer *timer = clksrc->timer; + + return (u64)__omap_dm_timer_read_counter(timer); +} + +static void omap_dm_timer_clocksource_suspend(struct clocksource *cs) +{ + struct dmtimer_clocksource *clksrc = omap_dm_timer_to_clocksource(cs); + struct dmtimer *timer = clksrc->timer; + + clksrc->loadval = __omap_dm_timer_read_counter(timer); + __omap_dm_timer_stop(timer); +} + +static void omap_dm_timer_clocksource_resume(struct clocksource *cs) +{ + struct dmtimer_clocksource *clksrc = omap_dm_timer_to_clocksource(cs); + struct dmtimer *timer = clksrc->timer; + + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, clksrc->loadval); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR); +} + +static int omap_dm_timer_setup_clocksource(struct dmtimer *timer) +{ + struct device *dev = &timer->pdev->dev; + struct dmtimer_clocksource *clksrc; + int err; + + __omap_dm_timer_init_regs(timer); + + timer->reserved = 1; + + clksrc = devm_kzalloc(dev, sizeof(*clksrc), GFP_KERNEL); + if (!clksrc) + return -ENOMEM; + + clksrc->timer = timer; + timer->clksrc = clksrc; + + clksrc->dev.name = "omap_dm_timer"; + clksrc->dev.rating = 300; + clksrc->dev.read = omap_dm_timer_read_cycles; + clksrc->dev.mask = CLOCKSOURCE_MASK(32); + clksrc->dev.flags = CLOCK_SOURCE_IS_CONTINUOUS; + clksrc->dev.suspend = omap_dm_timer_clocksource_suspend; + clksrc->dev.resume = omap_dm_timer_clocksource_resume; + + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, 0); + dmtimer_write(timer, OMAP_TIMER_LOAD_REG, 0); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR); + + err = clocksource_register_hz(&clksrc->dev, timer->fclk_rate); + if (err) + return dev_err_probe(dev, err, "Could not register as clocksource\n"); + + return 0; +} + +static struct omap_dm_timer_clockevent *to_dm_timer_clockevent(struct clock_event_device *evt) +{ + return container_of(evt, struct omap_dm_timer_clockevent, dev); +} + +static int omap_dm_timer_evt_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + struct omap_dm_timer_clockevent *clkevt = to_dm_timer_clockevent(evt); + struct dmtimer *timer = clkevt->timer; + + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, 0xffffffff - cycles); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST); + + return 0; +} + +static int omap_dm_timer_evt_shutdown(struct clock_event_device *evt) +{ + struct omap_dm_timer_clockevent *clkevt = to_dm_timer_clockevent(evt); + struct dmtimer *timer = clkevt->timer; + + __omap_dm_timer_stop(timer); + + return 0; +} + +static int omap_dm_timer_evt_set_periodic(struct clock_event_device *evt) +{ + struct omap_dm_timer_clockevent *clkevt = to_dm_timer_clockevent(evt); + struct dmtimer *timer = clkevt->timer; + + omap_dm_timer_evt_shutdown(evt); + + omap_dm_timer_set_load(&timer->cookie, clkevt->period); + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, clkevt->period); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, + OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST); + + return 0; +} + +static irqreturn_t omap_dm_timer_evt_interrupt(int irq, void *dev_id) +{ + struct omap_dm_timer_clockevent *clkevt = dev_id; + struct dmtimer *timer = clkevt->timer; + + __omap_dm_timer_write_status(timer, OMAP_TIMER_INT_OVERFLOW); + + clkevt->dev.event_handler(&clkevt->dev); + + return IRQ_HANDLED; +} + +static int omap_dm_timer_setup_clockevent(struct dmtimer *timer) +{ + struct device *dev = &timer->pdev->dev; + struct omap_dm_timer_clockevent *clkevt; + int ret; + + clkevt = devm_kzalloc(dev, sizeof(*clkevt), GFP_KERNEL); + if (!clkevt) + return -ENOMEM; + + timer->reserved = 1; + clkevt->timer = timer; + + clkevt->dev.name = "omap_dm_timer"; + clkevt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + clkevt->dev.rating = 300; + clkevt->dev.set_next_event = omap_dm_timer_evt_set_next_event; + clkevt->dev.set_state_shutdown = omap_dm_timer_evt_shutdown; + clkevt->dev.set_state_periodic = omap_dm_timer_evt_set_periodic; + clkevt->dev.set_state_oneshot = omap_dm_timer_evt_shutdown; + clkevt->dev.set_state_oneshot_stopped = omap_dm_timer_evt_shutdown; + clkevt->dev.tick_resume = omap_dm_timer_evt_shutdown; + clkevt->dev.cpumask = cpu_possible_mask; + clkevt->period = 0xffffffff - DIV_ROUND_CLOSEST(timer->fclk_rate, HZ); + + __omap_dm_timer_init_regs(timer); + __omap_dm_timer_stop(timer); + __omap_dm_timer_enable_posted(timer); + + ret = devm_request_irq(dev, timer->irq, omap_dm_timer_evt_interrupt, + IRQF_TIMER, "omap_dm_timer_clockevent", clkevt); + if (ret) { + dev_err(dev, "Failed to request interrupt: %d\n", ret); + return ret; + } + + __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW); + + clockevents_config_and_register(&clkevt->dev, timer->fclk_rate, + 3, + 0xffffffff); + + return 0; +} + /** * omap_dm_timer_probe - probe function called for every registered device * @pdev: pointer to current timer platform device @@ -1086,8 +1313,12 @@ struct dmtimer *timer; struct device *dev = &pdev->dev; const struct dmtimer_platform_data *pdata; + struct resource *res; int ret; + if (!omap_dm_timer_clocksource_base || !omap_dm_timer_clockevent_base) + omap_dm_timer_find_alwon(); + pdata = of_device_get_match_data(dev); if (!pdata) pdata = dev_get_platdata(dev); @@ -1156,6 +1387,34 @@ timer->pdev = pdev; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (omap_dm_timer_clockevent_base && res && + res->start == omap_dm_timer_clockevent_base && + !IS_ERR_OR_NULL(timer->fclk)) { + ret = omap_dm_timer_setup_clockevent(timer); + if (ret) + return ret; + } + + if (omap_dm_timer_clocksource_base && res && + res->start == omap_dm_timer_clocksource_base && + !IS_ERR_OR_NULL(timer->fclk)) { + /* + * This timer should have been initialized early via TIMER_OF_DECLARE + * by timer-ti-dm-systimer.c. If we reach here, it means the early + * init didn't happen (e.g., timer doesn't have ti,timer-alwon property + * or is an older platform). Set it up now for legacy compatibility. + */ + dev_info(dev, "Setting up clocksource via platform driver (legacy path)\n"); + + omap_dm_timer_sched_clock_counter = timer->func_base + _OMAP_TIMER_COUNTER_OFFSET; + + ret = omap_dm_timer_setup_clocksource(timer); + if (ret) + return ret; + } + pm_runtime_enable(dev); if (!timer->reserved) { @@ -1178,11 +1437,16 @@ list_add_tail(&timer->node, &omap_timer_list); spin_unlock_irqrestore(&dm_timer_lock, flags); + dev_pm_qos_expose_latency_limit(dev, PM_QOS_RESUME_LATENCY_NO_CONSTRAINT); + dev_dbg(dev, "Device Probed.\n"); return 0; err_disable: + if (timer->clksrc) + clocksource_unregister(&timer->clksrc->dev); + pm_runtime_disable(dev); return ret; } @@ -1197,10 +1461,13 @@ */ static void omap_dm_timer_remove(struct platform_device *pdev) { - struct dmtimer *timer; + struct dmtimer *timer = dev_get_drvdata(&pdev->dev); unsigned long flags; int ret = -EINVAL; + if (timer->clksrc) + clocksource_unregister(&timer->clksrc->dev); + spin_lock_irqsave(&dm_timer_lock, flags); list_for_each_entry(timer, &omap_timer_list, node) if (!strcmp(dev_name(&timer->pdev->dev), diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/clocksource/timer-ti-dm-systimer.c v_kernel/drivers/clocksource/timer-ti-dm-systimer.c --- linux-6.12.57/drivers/clocksource/timer-ti-dm-systimer.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/clocksource/timer-ti-dm-systimer.c 2026-04-21 11:35:35.613933812 +0200 @@ -226,7 +226,7 @@ * Some omap3 boards with unreliable oscillator must not use the counter_32k * or dmtimer1 with 32 KiHz source. Additionally, the boards with unreliable * oscillator should really set counter_32k as disabled, and delete dmtimer1 - * ti,always-on property, but let's not count on it. For these quirky cases, + * ti,timer-alwon property, but let's not count on it. For these quirky cases, * we prefer using the always-on secure dmtimer12 with the internal 32 KiHz * clock as the clocksource, and any available dmtimer as clockevent. * @@ -848,5 +848,6 @@ TIMER_OF_DECLARE(systimer_omap5, "ti,omap5430-timer", dmtimer_systimer_init); TIMER_OF_DECLARE(systimer_am33x, "ti,am335x-timer", dmtimer_systimer_init); TIMER_OF_DECLARE(systimer_am3ms, "ti,am335x-timer-1ms", dmtimer_systimer_init); +TIMER_OF_DECLARE(systimer_am654, "ti,am654-timer", dmtimer_systimer_init); TIMER_OF_DECLARE(systimer_dm814, "ti,dm814-timer", dmtimer_systimer_init); TIMER_OF_DECLARE(systimer_dm816, "ti,dm816-timer", dmtimer_systimer_init); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/cpufreq/cpufreq-dt-platdev.c v_kernel/drivers/cpufreq/cpufreq-dt-platdev.c --- linux-6.12.57/drivers/cpufreq/cpufreq-dt-platdev.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/cpufreq/cpufreq-dt-platdev.c 2026-04-21 11:35:35.695934027 +0200 @@ -183,8 +183,11 @@ { .compatible = "ti,dra7", }, { .compatible = "ti,omap3", }, { .compatible = "ti,am625", }, + { .compatible = "ti,am6254xxl", }, { .compatible = "ti,am62a7", }, + { .compatible = "ti,am62d2", }, { .compatible = "ti,am62p5", }, + { .compatible = "ti,am62l3", }, { .compatible = "qcom,ipq5332", }, { .compatible = "qcom,ipq6018", }, diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/cpufreq/ti-cpufreq.c v_kernel/drivers/cpufreq/ti-cpufreq.c --- linux-6.12.57/drivers/cpufreq/ti-cpufreq.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/cpufreq/ti-cpufreq.c 2026-04-21 11:35:35.718934087 +0200 @@ -48,6 +48,12 @@ #define AM625_SUPPORT_S_MPU_OPP BIT(1) #define AM625_SUPPORT_T_MPU_OPP BIT(2) +#define AM62L3_EFUSE_E_MPU_OPP 5 +#define AM62L3_EFUSE_O_MPU_OPP 15 + +#define AM62L3_SUPPORT_E_MPU_OPP BIT(0) +#define AM62L3_SUPPORT_O_MPU_OPP BIT(1) + enum { AM62A7_EFUSE_M_MPU_OPP = 13, AM62A7_EFUSE_N_MPU_OPP, @@ -72,7 +78,9 @@ #define AM62P5_EFUSE_O_MPU_OPP 15 #define AM62P5_EFUSE_S_MPU_OPP 19 +#define AM62P5_EFUSE_T_MPU_OPP 20 #define AM62P5_EFUSE_U_MPU_OPP 21 +#define AM62P5_EFUSE_V_MPU_OPP 22 #define AM62P5_SUPPORT_O_MPU_OPP BIT(0) #define AM62P5_SUPPORT_U_MPU_OPP BIT(2) @@ -93,6 +101,8 @@ bool multi_regulator; /* Backward compatibility hack: Might have missing syscon */ #define TI_QUIRK_SYSCON_MAY_BE_MISSING 0x1 +/* Backward compatibility hack: new syscon size is 1 register wide */ +#define TI_QUIRK_SYSCON_IS_SINGLE_REG 0x2 u8 quirks; }; @@ -151,7 +161,9 @@ unsigned long calculated_efuse = AM62P5_SUPPORT_O_MPU_OPP; switch (efuse) { + case AM62P5_EFUSE_V_MPU_OPP: case AM62P5_EFUSE_U_MPU_OPP: + case AM62P5_EFUSE_T_MPU_OPP: case AM62P5_EFUSE_S_MPU_OPP: calculated_efuse |= AM62P5_SUPPORT_U_MPU_OPP; fallthrough; @@ -207,6 +219,22 @@ return calculated_efuse; } +static unsigned long am62l3_efuse_xlate(struct ti_cpufreq_data *opp_data, + unsigned long efuse) +{ + unsigned long calculated_efuse = AM62L3_SUPPORT_E_MPU_OPP; + + switch (efuse) { + case AM62L3_EFUSE_O_MPU_OPP: + calculated_efuse |= AM62L3_SUPPORT_O_MPU_OPP; + fallthrough; + case AM62L3_EFUSE_E_MPU_OPP: + calculated_efuse |= AM62L3_SUPPORT_E_MPU_OPP; + } + + return calculated_efuse; +} + static struct ti_cpufreq_soc_data am3x_soc_data = { .efuse_xlate = amx3_efuse_xlate, .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ, @@ -305,9 +333,11 @@ }; static const struct soc_device_attribute k3_cpufreq_soc[] = { - { .family = "AM62X", .revision = "SR1.0" }, - { .family = "AM62AX", .revision = "SR1.0" }, - { .family = "AM62PX", .revision = "SR1.0" }, + { .family = "AM62X", }, + { .family = "AM62AX", }, + { .family = "AM62PX", }, + { .family = "AM62DX", }, + { .family = "AM62LX", }, { /* sentinel */ } }; @@ -316,7 +346,15 @@ .efuse_offset = 0x0018, .efuse_mask = 0x07c0, .efuse_shift = 0x6, - .rev_offset = 0x0014, + .multi_regulator = false, + .quirks = TI_QUIRK_SYSCON_IS_SINGLE_REG, +}; + +static struct ti_cpufreq_soc_data am62l3_soc_data = { + .efuse_xlate = am62l3_efuse_xlate, + .efuse_offset = 0x0, + .efuse_mask = 0x07c0, + .efuse_shift = 0x6, .multi_regulator = false, }; @@ -325,7 +363,6 @@ .efuse_offset = 0x0, .efuse_mask = 0x07c0, .efuse_shift = 0x6, - .rev_offset = 0x0014, .multi_regulator = false, }; @@ -334,7 +371,6 @@ .efuse_offset = 0x0, .efuse_mask = 0x07c0, .efuse_shift = 0x6, - .rev_offset = 0x0014, .multi_regulator = false, }; @@ -354,6 +390,10 @@ ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, &efuse); + + if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_IS_SINGLE_REG && ret == -EIO) + ret = regmap_read(opp_data->syscon, 0x0, &efuse); + if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_MAY_BE_MISSING && ret == -EIO) { /* not a syscon register! */ void __iomem *regs = ioremap(OMAP3_SYSCON_BASE + @@ -452,7 +492,10 @@ { .compatible = "ti,omap34xx", .data = &omap34xx_soc_data, }, { .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, }, { .compatible = "ti,am625", .data = &am625_soc_data, }, + { .compatible = "ti,am6254xxl", .data = &am625_soc_data, }, + { .compatible = "ti,am62l3", .data = &am62l3_soc_data, }, { .compatible = "ti,am62a7", .data = &am62a7_soc_data, }, + { .compatible = "ti,am62d2", .data = &am62a7_soc_data, }, { .compatible = "ti,am62p5", .data = &am62p5_soc_data, }, /* legacy */ { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, }, diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/cpuidle/cpuidle.c v_kernel/drivers/cpuidle/cpuidle.c --- linux-6.12.57/drivers/cpuidle/cpuidle.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/cpuidle/cpuidle.c 2026-04-21 11:35:35.723934101 +0200 @@ -180,20 +180,22 @@ * cpuidle_enter_s2idle - Enter an idle state suitable for suspend-to-idle. * @drv: cpuidle driver for the given CPU. * @dev: cpuidle device for the given CPU. + * @latency_limit_ns: Idle state exit latency limit * * If there are states with the ->enter_s2idle callback, find the deepest of * them and enter it with frozen tick. */ -int cpuidle_enter_s2idle(struct cpuidle_driver *drv, struct cpuidle_device *dev) +int cpuidle_enter_s2idle(struct cpuidle_driver *drv, struct cpuidle_device *dev, + u64 latency_limit_ns) { int index; /* - * Find the deepest state with ->enter_s2idle present, which guarantees - * that interrupts won't be enabled when it exits and allows the tick to - * be frozen safely. + * Find the deepest state with ->enter_s2idle present that meets the + * specified latency limit, which guarantees that interrupts won't be + * enabled when it exits and allows the tick to be frozen safely. */ - index = find_deepest_state(drv, dev, U64_MAX, 0, true); + index = find_deepest_state(drv, dev, latency_limit_ns, 0, true); if (index > 0) { enter_s2idle_proper(drv, dev, index); local_irq_enable(); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/cpuidle/cpuidle-psci.c v_kernel/drivers/cpuidle/cpuidle-psci.c --- linux-6.12.57/drivers/cpuidle/cpuidle-psci.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/cpuidle/cpuidle-psci.c 2026-04-21 11:35:35.721934095 +0200 @@ -25,6 +25,7 @@ #include #include +#include #include "cpuidle-psci.h" #include "dt_idle_states.h" @@ -73,7 +74,9 @@ if (!state) state = states[idx]; + trace_psci_domain_idle_enter(dev->cpu, state, s2idle); ret = psci_cpu_suspend_enter(state) ? -1 : idx; + trace_psci_domain_idle_exit(dev->cpu, state, s2idle); if (s2idle) dev_pm_genpd_resume(pd_dev); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/crypto/Kconfig v_kernel/drivers/crypto/Kconfig --- linux-6.12.57/drivers/crypto/Kconfig 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/crypto/Kconfig 2026-04-21 11:35:35.727934111 +0200 @@ -851,5 +851,6 @@ source "drivers/crypto/aspeed/Kconfig" source "drivers/crypto/starfive/Kconfig" +source "drivers/crypto/ti/Kconfig" endif # CRYPTO_HW diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/crypto/Makefile v_kernel/drivers/crypto/Makefile --- linux-6.12.57/drivers/crypto/Makefile 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/crypto/Makefile 2026-04-21 11:35:35.727934111 +0200 @@ -42,6 +42,7 @@ obj-y += stm32/ obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o obj-$(CONFIG_CRYPTO_DEV_TEGRA) += tegra/ +obj-$(CONFIG_CRYPTO_DEV_TI_MCRC64) += ti/ obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/ #obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/ obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/ @@ -52,3 +53,4 @@ obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/ obj-y += intel/ obj-y += starfive/ +obj-$(CONFIG_ARCH_K3) += ti/ diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/crypto/sa2ul.c v_kernel/drivers/crypto/sa2ul.c --- linux-6.12.57/drivers/crypto/sa2ul.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/crypto/sa2ul.c 2026-04-21 11:35:35.884934523 +0200 @@ -8,46 +8,67 @@ * Vitaly Andrianov * Tero Kristo */ +#include #include #include #include #include #include +#include #include +#include #include #include #include #include #include +#include #include #include #include +#include #include #include #include #include #include #include +#include #include "sa2ul.h" -/* Byte offset for key in encryption security context */ -#define SC_ENC_KEY_OFFSET (1 + 27 + 4) -/* Byte offset for Aux-1 in encryption security context */ -#define SC_ENC_AUX1_OFFSET (1 + 27 + 4 + 32) - -#define SA_CMDL_UPD_ENC 0x0001 -#define SA_CMDL_UPD_AUTH 0x0002 -#define SA_CMDL_UPD_ENC_IV 0x0004 -#define SA_CMDL_UPD_AUTH_IV 0x0008 -#define SA_CMDL_UPD_AUX_KEY 0x0010 +#define SC_ENC_MODESEL_OFFSET (0) +#define SC_ENC_MODESEL_SIZE (1) -#define SA_AUTH_SUBKEY_LEN 16 -#define SA_CMDL_PAYLOAD_LENGTH_MASK 0xFFFF +#define SC_ENC_MCI_OFFSET (SC_ENC_MODESEL_SIZE) +#define SC_ENC_MCI_SIZE (27) + +#define SC_ENC_KEY_OFFSET (SC_ENC_MCI_OFFSET + SC_ENC_MCI_SIZE + 4) +#define SC_ENC_KEY_SIZE 32 + +#define SC_ENC_AUX1_OFFSET (SC_ENC_KEY_OFFSET + SC_ENC_KEY_SIZE) +#define SC_ENC_AUX1_SIZE 32 + +#define SC_ENC_AUX2_OFFSET (SC_ENC_AUX1_OFFSET + SC_ENC_AUX1_SIZE) +#define SC_ENC_AUX2_SIZE 16 + +#define SC_ENC_AUX3_OFFSET (SC_ENC_AUX2_OFFSET + SC_ENC_AUX2_SIZE) +#define SC_ENC_AUX3_SIZE 16 + +#define SA_CMDL_UPD_ENC BIT(1) +#define SA_CMDL_UPD_AUTH BIT(2) +#define SA_CMDL_UPD_ENC_IV BIT(3) +#define SA_CMDL_UPD_IS_GCM BIT(4) +#define SA_CMDL_UPD_IS_CMAC BIT(5) + +#define SA_CMDL_PAYLOAD_LENGTH_MASK 0x0000FFFF +#define SA_CMDL_LENGTH_MASK 0x00FF0000 #define SA_CMDL_SOP_BYPASS_LEN_MASK 0xFF000000 +#define SA_CMDL_OPTION_CTRL1_MASK 0x00FF0000 +#define SA_CMDL_OPTION_CTRL2_MASK 0x0000FF00 +#define SA_CMDL_OPTION_CTRL3_MASK 0x000000FF -#define MODE_CONTROL_BYTES 27 #define SA_HASH_PROCESSING 0 #define SA_CRYPTO_PROCESSING 0 #define SA_UPLOAD_HASH_TO_TLR BIT(6) @@ -68,12 +89,19 @@ /* size of SCCTL structure in bytes */ #define SA_SCCTL_SZ 16 +#define SA_GCM_IV_SIZE 16 + /* Max Authentication tag size */ #define SA_MAX_AUTH_TAG_SZ 64 +/* CMAC definitions */ +#define SA_CMAC_DIGEST_SIZE 16 +#define SA_CMAC_BLOCK_SIZE 16 + enum sa_algo_id { SA_ALG_CBC_AES = 0, SA_ALG_EBC_AES, + SA_ALG_GCM_AES, SA_ALG_CBC_DES3, SA_ALG_ECB_DES3, SA_ALG_SHA1, @@ -81,6 +109,10 @@ SA_ALG_SHA512, SA_ALG_AUTHENC_SHA1_AES, SA_ALG_AUTHENC_SHA256_AES, + SA_ALG_HMAC_SHA1, + SA_ALG_HMAC_SHA256, + SA_ALG_HMAC_SHA512, + SA_ALG_CMAC_AES, }; struct sa_match_data { @@ -93,22 +125,20 @@ /** * struct sa_cmdl_cfg - Command label configuration descriptor - * @aalg: authentication algorithm ID * @enc_eng_id: Encryption Engine ID supported by the SA hardware * @auth_eng_id: Authentication Engine ID * @iv_size: Initialization Vector size - * @akey: Authentication key - * @akey_len: Authentication key length * @enc: True, if this is an encode request + * @is_gcm: True, if this is GCM mode + * @is_cmac: True, if this is CMAC mode */ struct sa_cmdl_cfg { - int aalg; u8 enc_eng_id; u8 auth_eng_id; u8 iv_size; - const u8 *akey; - u16 akey_len; bool enc; + bool is_gcm; + bool is_cmac; }; /** @@ -142,8 +172,11 @@ bool inv_key; struct sa_tfm_ctx *ctx; bool keyed_mac; - void (*prep_iopad)(struct algo_data *algo, const u8 *key, - u16 key_sz, __be32 *ipad, __be32 *opad); + int (*prep_iopad)(struct algo_data *algo, const u8 *key, + u16 key_sz, __be32 *lower_ipad, __be32 *lower_opad, + __be32 *upper_ipad, __be32 *upper_opad); + int (*prep_cmac)(struct algo_data *algo, const u8 *key, + u16 key_sz, __be32 *subkey1, __be32 *subkey2); }; /** @@ -195,6 +228,9 @@ u8 enc; u8 enc_iv_size; u8 iv_idx; + struct sa_crypto_data *pdata; + struct sa_req_ctx_data req_ctx; + bool hw_locked; }; /** @@ -228,6 +264,8 @@ u8 *auth_iv; u32 type; u32 *cmdl; + u8 aad_length; + u8 aad[SA_MAX_ASSOC_SZ]; struct crypto_async_request *base; struct sa_tfm_ctx *ctx; bool enc; @@ -237,11 +275,38 @@ u16 mdata_size; }; +static void sa_hw_lock(struct sa_crypto_data *pdata, bool may_sleep) +{ + unsigned long flags; + + spin_lock_irqsave(&pdata->hw.lock, flags); + while (pdata->hw.busy) { + spin_unlock_irqrestore(&pdata->hw.lock, flags); + if (may_sleep) + wait_event(pdata->hw.wq, !pdata->hw.busy); + else + cpu_relax(); + spin_lock_irqsave(&pdata->hw.lock, flags); + } + pdata->hw.busy = true; + spin_unlock_irqrestore(&pdata->hw.lock, flags); +} + +static void sa_hw_unlock(struct sa_crypto_data *pdata) +{ + unsigned long flags; + + spin_lock_irqsave(&pdata->hw.lock, flags); + pdata->hw.busy = false; + spin_unlock_irqrestore(&pdata->hw.lock, flags); + wake_up_all(&pdata->hw.wq); +} + /* * Mode Control Instructions for various Key lengths 128, 192, 256 * For CBC (Cipher Block Chaining) mode for encryption */ -static u8 mci_cbc_enc_array[3][MODE_CONTROL_BYTES] = { +static u8 mci_cbc_enc_array[3][SC_ENC_MCI_SIZE] = { { 0x61, 0x00, 0x00, 0x18, 0x88, 0x0a, 0xaa, 0x4b, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, @@ -257,7 +322,7 @@ * Mode Control Instructions for various Key lengths 128, 192, 256 * For CBC (Cipher Block Chaining) mode for decryption */ -static u8 mci_cbc_dec_array[3][MODE_CONTROL_BYTES] = { +static u8 mci_cbc_dec_array[3][SC_ENC_MCI_SIZE] = { { 0x71, 0x00, 0x00, 0x80, 0x8a, 0xca, 0x98, 0xf4, 0x40, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, @@ -273,7 +338,7 @@ * Mode Control Instructions for various Key lengths 128, 192, 256 * For CBC (Cipher Block Chaining) mode for encryption */ -static u8 mci_cbc_enc_no_iv_array[3][MODE_CONTROL_BYTES] = { +static u8 mci_cbc_enc_no_iv_array[3][SC_ENC_MCI_SIZE] = { { 0x21, 0x00, 0x00, 0x18, 0x88, 0x0a, 0xaa, 0x4b, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, @@ -289,7 +354,7 @@ * Mode Control Instructions for various Key lengths 128, 192, 256 * For CBC (Cipher Block Chaining) mode for decryption */ -static u8 mci_cbc_dec_no_iv_array[3][MODE_CONTROL_BYTES] = { +static u8 mci_cbc_dec_no_iv_array[3][SC_ENC_MCI_SIZE] = { { 0x31, 0x00, 0x00, 0x80, 0x8a, 0xca, 0x98, 0xf4, 0x40, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, @@ -333,36 +398,87 @@ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, }; +/** + * Mode control engine instructions for AES-GCM encryption + */ +static u8 mci_gcm_aes_enc_array[3][SC_ENC_MCI_SIZE] = { + { 0x61, 0x00, 0x44, 0x80, 0xa9, 0xfe, 0x83, 0x99, 0x7e, 0x58, + 0x2e, 0x0a, 0x90, 0x71, 0x41, 0x83, 0x9d, 0x63, 0xaa, 0x0b, + 0x7e, 0x9a, 0x78, 0x3a, 0xa3, 0x8b, 0x1e }, + { 0x61, 0x00, 0x44, 0x84, 0xa9, 0xfe, 0x83, 0x99, 0x7e, 0x58, + 0x2e, 0x4a, 0x90, 0x71, 0x41, 0x83, 0x9d, 0x63, 0xaa, 0x0b, + 0x7e, 0x9a, 0x78, 0x3a, 0xa3, 0x8b, 0x1e }, + { 0x61, 0x00, 0x44, 0x88, 0xa9, 0xfe, 0x83, 0x99, 0x7e, 0x58, + 0x2e, 0x8a, 0x90, 0x71, 0x41, 0x83, 0x9d, 0x63, 0xaa, 0x0b, + 0x7e, 0x9a, 0x78, 0x3a, 0xa3, 0x8b, 0x1e }, +}; + +/** + * Mode control engine instructions for AES-GCM decryption + */ +static u8 mci_gcm_aes_dec_array[3][SC_ENC_MCI_SIZE] = { + { 0x61, 0x00, 0x44, 0x80, 0xa9, 0xfe, 0x83, 0x99, 0x7e, 0x58, + 0x2e, 0x0a, 0x14, 0x19, 0x07, 0x83, 0x9d, 0x63, 0xaa, 0x0b, + 0x7e, 0x9a, 0x78, 0x3a, 0xa3, 0x8b, 0x1e }, + { 0x61, 0x00, 0x44, 0x84, 0xa9, 0xfe, 0x83, 0x99, 0x7e, 0x58, + 0x2e, 0x4a, 0x14, 0x19, 0x07, 0x83, 0x9d, 0x63, 0xaa, 0x0b, + 0x7e, 0x9a, 0x78, 0x3a, 0xa3, 0x8b, 0x1e }, + { 0x61, 0x00, 0x44, 0x88, 0xa9, 0xfe, 0x83, 0x99, 0x7e, 0x58, + 0x2e, 0x8a, 0x14, 0x19, 0x07, 0x83, 0x9d, 0x63, 0xaa, 0x0b, + 0x7e, 0x9a, 0x78, 0x3a, 0xa3, 0x8b, 0x1e } +}; + /* * Mode Control Instructions for DES algorithm * For CBC (Cipher Block Chaining) mode and ECB mode * encryption and for decryption respectively */ -static u8 mci_cbc_3des_enc_array[MODE_CONTROL_BYTES] = { +static u8 mci_cbc_3des_enc_array[SC_ENC_MCI_SIZE] = { 0x60, 0x00, 0x00, 0x18, 0x88, 0x52, 0xaa, 0x4b, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; -static u8 mci_cbc_3des_dec_array[MODE_CONTROL_BYTES] = { +static u8 mci_cbc_3des_dec_array[SC_ENC_MCI_SIZE] = { 0x70, 0x00, 0x00, 0x85, 0x0a, 0xca, 0x98, 0xf4, 0x40, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; -static u8 mci_ecb_3des_enc_array[MODE_CONTROL_BYTES] = { +static u8 mci_ecb_3des_enc_array[SC_ENC_MCI_SIZE] = { 0x20, 0x00, 0x00, 0x85, 0x0a, 0x04, 0xb7, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; -static u8 mci_ecb_3des_dec_array[MODE_CONTROL_BYTES] = { +static u8 mci_ecb_3des_dec_array[SC_ENC_MCI_SIZE] = { 0x30, 0x00, 0x00, 0x85, 0x0a, 0x04, 0xb7, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; /* + * Mode Control Instructions for CMAC (Cipher-based Message Authentication Code) + * For various Key lengths: 128, 192, 256 bits + * Based on SA2UL/SA3UL specification + * Note: Subkey must be derived by software and supplied via command label + */ +static u8 mci_cmac_aes_array[3][SC_ENC_MCI_SIZE] = { + /* AES-128 CMAC */ + { 0x41, 0x00, 0x00, 0xf1, 0x0d, 0x19, 0x10, 0x8d, 0x2c, 0x12, + 0x88, 0x08, 0xa6, 0x4b, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + /* AES-192 CMAC */ + { 0x41, 0x00, 0x00, 0xf1, 0x0d, 0x19, 0x10, 0x8d, 0x2c, 0x12, + 0x88, 0x48, 0xa6, 0x4b, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + /* AES-256 CMAC */ + { 0x41, 0x00, 0x00, 0xf1, 0x0d, 0x19, 0x10, 0x8d, 0x2c, 0x12, + 0x88, 0x88, 0xa6, 0x4b, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, +}; + +/* * Perform 16 byte or 128 bit swizzling * The SA2UL Expects the security context to * be in little Endian and the bus width is 128 bits or 16 bytes @@ -380,86 +496,134 @@ } } -/* Prepare the ipad and opad from key as per SHA algorithm step 1*/ -static void prepare_kipad(u8 *k_ipad, const u8 *key, u16 key_sz) -{ - int i; - - for (i = 0; i < key_sz; i++) - k_ipad[i] = key[i] ^ 0x36; - - /* Instead of XOR with 0 */ - for (; i < SHA1_BLOCK_SIZE; i++) - k_ipad[i] = 0x36; -} - -static void prepare_kopad(u8 *k_opad, const u8 *key, u16 key_sz) +static int sa_export_shash(struct shash_desc *hash, int digest_size, + void *lower_out, void *upper_out) { - int i; - - for (i = 0; i < key_sz; i++) - k_opad[i] = key[i] ^ 0x5c; + u32 *result; + u64 *result64; + int ret = 0; - /* Instead of XOR with 0 */ - for (; i < SHA1_BLOCK_SIZE; i++) - k_opad[i] = 0x5c; -} + union { + struct sha1_state sha1; + struct sha256_state sha256; + struct sha512_state sha512; + } sha; -static void sa_export_shash(void *state, struct shash_desc *hash, - int digest_size, __be32 *out) -{ - struct sha1_state *sha1; - struct sha256_state *sha256; - u32 *result; + /* Export the intermediate digest to program into SA2UL */ + ret = crypto_shash_export(hash, &sha); + if (ret) { + dev_err(sa_k3_dev, "%s: crypto_shash_export failed\n", + __func__); + return ret; + } switch (digest_size) { case SHA1_DIGEST_SIZE: - sha1 = state; - result = sha1->state; + result = sha.sha1.state; + cpu_to_be32_array(lower_out, result, digest_size / 4); break; case SHA256_DIGEST_SIZE: - sha256 = state; - result = sha256->state; + result = sha.sha256.state; + cpu_to_be32_array(lower_out, result, digest_size / 4); + break; + case SHA512_DIGEST_SIZE: + result64 = sha.sha512.state; + cpu_to_be64_array(upper_out, result64, digest_size / 8 / 2); + cpu_to_be64_array(lower_out, result64 + digest_size / 8 / 2, digest_size / 8 / 2); break; default: dev_err(sa_k3_dev, "%s: bad digest_size=%d\n", __func__, digest_size); - return; + return -EINVAL; } - crypto_shash_export(hash, state); - cpu_to_be32_array(out, result, digest_size / 4); + return ret; } -static void sa_prepare_iopads(struct algo_data *data, const u8 *key, - u16 key_sz, __be32 *ipad, __be32 *opad) +static int sa_prepare_iopads(struct algo_data *data, const u8 *key, + u16 key_sz, __be32 *lower_ipad, __be32 *lower_opad, + __be32 *upper_ipad, __be32 *upper_opad) { SHASH_DESC_ON_STACK(shash, data->ctx->shash); int block_size = crypto_shash_blocksize(data->ctx->shash); int digest_size = crypto_shash_digestsize(data->ctx->shash); - union { - struct sha1_state sha1; - struct sha256_state sha256; - u8 k_pad[SHA1_BLOCK_SIZE]; - } sha; + int ret = 0; + int i = 0; + u8 k_ipad[SHA512_BLOCK_SIZE]; + u8 k_opad[SHA512_BLOCK_SIZE]; + + if (fips_enabled && (key_sz < 112 / 8)) + return -EINVAL; shash->tfm = data->ctx->shash; - prepare_kipad(sha.k_pad, key, key_sz); + if (key_sz > block_size) { + int err; - crypto_shash_init(shash); - crypto_shash_update(shash, sha.k_pad, block_size); - sa_export_shash(&sha, shash, digest_size, ipad); + err = crypto_shash_digest(shash, key, key_sz, k_ipad); + if (err) + return err; - prepare_kopad(sha.k_pad, key, key_sz); + key_sz = digest_size; + } else + memcpy(k_ipad, key, key_sz); - crypto_shash_init(shash); - crypto_shash_update(shash, sha.k_pad, block_size); + memset(k_ipad + key_sz, 0, block_size - key_sz); + memcpy(k_opad, k_ipad, block_size); - sa_export_shash(&sha, shash, digest_size, opad); + for (i = 0; i < block_size; i++) { + k_ipad[i] ^= HMAC_IPAD_VALUE; + k_opad[i] ^= HMAC_OPAD_VALUE; + } + + memset(lower_ipad, 0, digest_size / 2); + memset(lower_opad, 0, digest_size / 2); + memset(upper_ipad, 0, digest_size / 2); + memset(upper_opad, 0, digest_size / 2); + + ret = crypto_shash_init(shash); + if (ret) { + dev_err(sa_k3_dev, "%s: %d: crypto_shash_init for ipad failed, ret=%d\n", + __func__, __LINE__, ret); + return ret; + } + ret = crypto_shash_update(shash, k_ipad, block_size); + if (ret) { + dev_err(sa_k3_dev, "%s: %d: crypto_shash_update for ipad failed, ret=%d\n", + __func__, __LINE__, ret); + return ret; + } + ret = sa_export_shash(shash, digest_size, lower_ipad, upper_ipad); + if (ret) { + dev_err(sa_k3_dev, "%s: %d: sa_export_shash for ipad failed, ret=%d\n", + __func__, __LINE__, ret); + return ret; + } - memzero_explicit(&sha, sizeof(sha)); + ret = crypto_shash_init(shash); + if (ret) { + dev_err(sa_k3_dev, "%s: %d: crypto_shash_init for opad failed, ret=%d\n", + __func__, __LINE__, ret); + return ret; + } + ret = crypto_shash_update(shash, k_opad, block_size); + if (ret) { + dev_err(sa_k3_dev, "%s: %d: crypto_shash_update for opad failed, ret=%d\n", + __func__, __LINE__, ret); + return ret; + } + ret = sa_export_shash(shash, digest_size, lower_opad, upper_opad); + if (ret) { + dev_err(sa_k3_dev, "%s: %d: sa_export_shash for opad failed, ret=%d\n", + __func__, __LINE__, ret); + return ret; + } + + memzero_explicit(k_ipad, sizeof(SHA1_BLOCK_SIZE)); + memzero_explicit(k_opad, sizeof(SHA1_BLOCK_SIZE)); + + return ret; } /* Derive the inverse key used in AES-CBC decryption operation */ @@ -503,10 +667,14 @@ static int sa_set_sc_enc(struct algo_data *ad, const u8 *key, u16 key_sz, u8 enc, u8 *sc_buf) { + WARN_ON(!ad->ctx); + SYNC_SKCIPHER_REQUEST_ON_STACK(req, ad->ctx->skcipher); const u8 *mci = NULL; + int ret = 0; + struct scatterlist sg; /* Set Encryption mode selector to crypto processing */ - sc_buf[0] = SA_CRYPTO_PROCESSING; + sc_buf[SC_ENC_MODESEL_OFFSET] = SA_CRYPTO_PROCESSING; if (enc) mci = ad->mci_enc; @@ -514,7 +682,7 @@ mci = ad->mci_dec; /* Set the mode control instructions in security context */ if (mci) - memcpy(&sc_buf[1], mci, MODE_CONTROL_BYTES); + memcpy(&sc_buf[SC_ENC_MCI_OFFSET], mci, SC_ENC_MCI_SIZE); /* For AES-CBC decryption get the inverse key */ if (ad->inv_key && !enc) { @@ -525,15 +693,45 @@ memcpy(&sc_buf[SC_ENC_KEY_OFFSET], key, key_sz); } + if (ad->ealg_id == SA_EALG_ID_AES_GCM) { + /* + * Program AES_ECB(key, 0) = Hash KEY for GCM + * + * Update the bits 128:255 on sc_buf[SC_ENC_AUX1_OFFSET], + * since the buffer is little endian 255:128 would lie in + * the starting of AUX1 itself + */ + sg_init_one(&sg, &sc_buf[SC_ENC_AUX1_OFFSET], AES_BLOCK_SIZE); + + ret = crypto_sync_skcipher_setkey(ad->ctx->skcipher, key, key_sz); + if (ret) { + dev_err(sa_k3_dev, "%s: %d: crypto_skcipher_setkey failed, ret=%d\n", + __func__, __LINE__, ret); + return ret; + } + skcipher_request_set_sync_tfm(req, ad->ctx->skcipher); + skcipher_request_set_crypt(req, &sg, &sg, AES_BLOCK_SIZE, NULL); + + ret = crypto_skcipher_encrypt(req); + if (ret) { + dev_err(sa_k3_dev, "%s: %d: crypto_skcipher_encrypt failed, ret=%d\n", + __func__, __LINE__, ret); + return ret; + } + } + return 0; } /* Set Security context for the authentication engine */ -static void sa_set_sc_auth(struct algo_data *ad, const u8 *key, u16 key_sz, +static int sa_set_sc_auth(struct algo_data *ad, const u8 *key, u16 key_sz, u8 *sc_buf) { - __be32 *ipad = (void *)(sc_buf + 32); - __be32 *opad = (void *)(sc_buf + 64); + __be32 *lower_ipad = (void *)(sc_buf + 32); + __be32 *lower_opad = (void *)(sc_buf + 64); + __be32 *upper_ipad = (void *)(sc_buf + 96); + __be32 *upper_opad = (void *)(sc_buf + 128); + int ret = 0; /* Set Authentication mode selector to hash processing */ sc_buf[0] = SA_HASH_PROCESSING; @@ -542,21 +740,29 @@ sc_buf[1] |= ad->auth_ctrl; /* Copy the keys or ipad/opad */ - if (ad->keyed_mac) - ad->prep_iopad(ad, key, key_sz, ipad, opad); - else { + if (ad->keyed_mac) { + ret = ad->prep_iopad(ad, key, key_sz, lower_ipad, + lower_opad, upper_ipad, upper_opad); + if (ret) { + dev_err(sa_k3_dev, "%s: %d: sa_prepare_iopads failed, ret=%d\n", + __func__, __LINE__, ret); + return ret; + } + } else { /* basic hash */ sc_buf[1] |= SA_BASIC_HASH; } + + return 0; } -static inline void sa_copy_iv(__be32 *out, const u8 *iv, bool size16) +static inline void sa_copy_to_cmdl(__be32 *out, const u32 *iv, u32 size) { - int j; + int i; - for (j = 0; j < ((size16) ? 4 : 2); j++) { - *out = cpu_to_be32(*((u32 *)iv)); - iv += 4; + for (i = 0; i < size; i += 4) { + *out = cpu_to_be32(*iv); + iv++; out++; } } @@ -597,8 +803,65 @@ /* Encryption command label */ cmdl[enc_offset + SA_CMDL_OFFSET_NESC] = enc_next_eng; - /* Encryption modes requiring IV */ - if (cfg->iv_size) { + if (cfg->is_cmac) { + /* + * CMAC subkey passing via command label option bytes + * + * Subkey (16B) : Goes in AUX1[255:128] + * + * Setup command label to accept 16-byte subkey at runtime. + * The subkey (K1 or K2) selection happens in sa_update_cmdl() + * based on message length. + */ + upd_info->flags |= SA_CMDL_UPD_IS_CMAC; + + upd_info->aux_key_info.index = (SA_CMDL_HEADER_SIZE_BYTES) >> 2; + upd_info->aux_key_info.size = 16; + + /* Set the initial command label length */ + cmdl[enc_offset + SA_CMDL_OFFSET_LABEL_LEN] = + SA_CMDL_HEADER_SIZE_BYTES + upd_info->aux_key_info.size; + + /* The length and offset are specified in unit of 8B + * For AUX1[255:128]: offset=(64+16)=80, length=16 + */ + cmdl[enc_offset + SA_CMDL_OFFSET_OPTION_CTRL1] = + ((SC_ENC_AUX1_OFFSET) | (upd_info->aux_key_info.size >> 3)); + + total = SA_CMDL_HEADER_SIZE_BYTES + upd_info->aux_key_info.size; + } else if (cfg->is_gcm) { + /* + * GCM requires the following things so we need to + * send them through option bytes as they keep + * changing per request. + * + * IV(12B), CTR(4B) : Goes in AUX3 (16B) + * AAD(16B) : Goes in AUX2 (16B) + * AAD Length(8B), Payload Length (8B): Goes in AUX1[0:127] + */ + + /* Program IV in AUX3 */ + upd_info->flags |= SA_CMDL_UPD_ENC_IV; + + /* + * Calculate the 32 bit based index in cmdl where + * IV is supposed t be populated + */ + upd_info->enc_iv.index = (SA_CMDL_HEADER_SIZE_BYTES) >> 2; + upd_info->enc_iv.size = cfg->iv_size; + + /* Set the max length of cmdl */ + cmdl[enc_offset + SA_CMDL_OFFSET_LABEL_LEN] = + SA_CMDL_HEADER_SIZE_BYTES + cfg->iv_size; + + /* The length and offset are specified in unit of 8B*/ + cmdl[enc_offset + SA_CMDL_OFFSET_OPTION_CTRL1] = + (SC_ENC_AUX3_OFFSET | ((cfg->iv_size) >> 3)); + + upd_info->flags |= SA_CMDL_UPD_IS_GCM; + total = SA_CMDL_HEADER_SIZE_BYTES + cfg->iv_size; + + } else if (cfg->iv_size) { upd_info->flags |= SA_CMDL_UPD_ENC_IV; upd_info->enc_iv.index = (enc_offset + SA_CMDL_HEADER_SIZE_BYTES) >> 2; @@ -608,7 +871,7 @@ SA_CMDL_HEADER_SIZE_BYTES + cfg->iv_size; cmdl[enc_offset + SA_CMDL_OFFSET_OPTION_CTRL1] = - (SA_CTX_ENC_AUX2_OFFSET | (cfg->iv_size >> 3)); + (SC_ENC_AUX2_OFFSET | (cfg->iv_size >> 3)); total += SA_CMDL_HEADER_SIZE_BYTES + cfg->iv_size; } else { cmdl[enc_offset + SA_CMDL_OFFSET_LABEL_LEN] = @@ -636,11 +899,9 @@ } /* Update Command label */ -static inline void sa_update_cmdl(struct sa_req *req, u32 *cmdl, - struct sa_cmdl_upd_info *upd_info) +static inline int sa_update_cmdl(struct sa_req *req, u32 *cmdl, + struct sa_cmdl_upd_info *upd_info, u32 total) { - int i = 0, j; - if (likely(upd_info->flags & SA_CMDL_UPD_ENC)) { cmdl[upd_info->enc_size.index] &= ~SA_CMDL_PAYLOAD_LENGTH_MASK; cmdl[upd_info->enc_size.index] |= req->enc_size; @@ -649,16 +910,92 @@ cmdl[upd_info->enc_offset.index] |= FIELD_PREP(SA_CMDL_SOP_BYPASS_LEN_MASK, req->enc_offset); + } - if (likely(upd_info->flags & SA_CMDL_UPD_ENC_IV)) { - __be32 *data = (__be32 *)&cmdl[upd_info->enc_iv.index]; - u32 *enc_iv = (u32 *)req->enc_iv; - - for (j = 0; i < upd_info->enc_iv.size; i += 4, j++) { - data[j] = cpu_to_be32(*enc_iv); - enc_iv++; - } + if (likely(upd_info->flags & SA_CMDL_UPD_ENC_IV)) + sa_copy_to_cmdl((__be32 *)&cmdl[upd_info->enc_iv.index], + (u32 *)req->enc_iv, upd_info->enc_iv.size); + + if (upd_info->flags & SA_CMDL_UPD_IS_GCM) { + WARN_ON(req->aad_length > 16); + + /* We have 4 fields to update (IV, AAD, Payload length, + * AAD Length) + * + * To accommodate it in 3 option bytes, we need to + * update the encryption size and the aad length as part of + * single option byte field only which helps with them + * sharing the same field AUX1. + */ + cmdl[1] &= ~SA_CMDL_OPTION_CTRL2_MASK; + cmdl[1] |= FIELD_PREP(SA_CMDL_OPTION_CTRL2_MASK, + ((SC_ENC_AUX1_OFFSET + 16) | 16 >> 3)); + + /* Update the AAD length (bits) in AUX1[65:127] + * + * The max AAD length can be just 16 bytes = 48 bits as + * AUX2 field has limited capacity + * + * The upper 32 bits are not being written. + */ + cmdl[(roundup(total, 8) >> 2) + 1] = (req->aad_length << 3); + + /* 8B of AAD length */ + total += 8; + + /* Update the encryption size (bits) in AUX1[64:0] + * + * Since the upper 32 bits won't be used as the max payload + * that SA2UL can process without fragmentation is 65536 bytes, + * + * The upper 32 bits are not being written. + */ + cmdl[(roundup(total, 8) >> 2) + 1] = (req->enc_size << 3) & 0xFFFF; + + /* 8B of payload length */ + total += 8; + + if (req->aad_length > 0) { + upd_info->aad.index = roundup(total, 8) >> 2; + upd_info->aad.size = req->aad_length; + + /* Update AAD */ + cmdl[1] &= ~SA_CMDL_OPTION_CTRL3_MASK; + cmdl[1] |= FIELD_PREP(SA_CMDL_OPTION_CTRL3_MASK, + (SC_ENC_AUX2_OFFSET | + roundup(upd_info->aad.size, 8) >> 3)); + + sa_copy_to_cmdl((__be32 *)&cmdl[upd_info->aad.index], + (u32 *)req->aad, upd_info->aad.size); + + /* The option bytes have 8B granularity */ + total += roundup(upd_info->aad.size, 8); } + + cmdl[0] &= ~SA_CMDL_LENGTH_MASK; + cmdl[0] |= FIELD_PREP(SA_CMDL_LENGTH_MASK, total); + } + + /* + * CMAC subkey passing via command label option bytes + * + * Per NIST SP 800-38B and SA2UL hardware requirements: + * - Pass a single 16-byte subkey (K1 or K2) to Aux1[255:128] (bytes 16-31) + * - K1 is used when message is a multiple of block size (16 bytes) + * - K2 is used when message needs padding + * - K1 and K2 are stored in ctx->enc.cmdl_upd_info.aux_key[] + */ + if (upd_info->flags & SA_CMDL_UPD_IS_CMAC) { + struct sa_tfm_ctx *ctx = req->ctx; + u32 *subkey; + + /* Select K1 (complete blocks) or K2 (needs padding) per NIST SP 800-38B */ + subkey = (req->enc_size > 0 && req->enc_size % AES_BLOCK_SIZE == 0) ? + &ctx->enc.cmdl_upd_info.aux_key[0] : /* K1 */ + &ctx->enc.cmdl_upd_info.aux_key[4]; /* K2 */ + + sa_copy_to_cmdl((__be32 *)&cmdl[upd_info->aux_key_info.index], + subkey, upd_info->aux_key_info.size); } if (likely(upd_info->flags & SA_CMDL_UPD_AUTH)) { @@ -669,18 +1006,9 @@ cmdl[upd_info->auth_offset.index] |= FIELD_PREP(SA_CMDL_SOP_BYPASS_LEN_MASK, req->auth_offset); - if (upd_info->flags & SA_CMDL_UPD_AUTH_IV) { - sa_copy_iv((void *)&cmdl[upd_info->auth_iv.index], - req->auth_iv, - (upd_info->auth_iv.size > 8)); - } - if (upd_info->flags & SA_CMDL_UPD_AUX_KEY) { - int offset = (req->auth_size & 0xF) ? 4 : 0; - - memcpy(&cmdl[upd_info->aux_key_info.index], - &upd_info->aux_key[offset], 16); - } } + + return roundup(total, 8); } /* Format SWINFO words to be sent to SA */ @@ -718,31 +1046,47 @@ const u8 *auth_key, u16 auth_key_sz, struct algo_data *ad, u8 enc, u32 *swinfo) { + struct sa_crypto_data *data = dev_get_drvdata(sa_k3_dev); + struct device *dev = &data->pdev->dev; + int enc_sc_offset = 0; int auth_sc_offset = 0; u8 *sc_buf = ctx->sc; u16 sc_id = ctx->sc_id; u8 first_engine = 0; + int ret = 0; memzero_explicit(sc_buf, SA_CTX_MAX_SZ); + /* Set SCCTL fetch/evict control based on engine configuration */ + if (ad->auth_eng.eng_id && ad->enc_eng.eng_id) { + /* Dual-engine (authenc) - fetch both contexts */ + sc_buf[1] = SA_SCCTL_FE_AUTH_ENC; + } else if (ad->enc_eng.eng_id) { + /* Single-engine encryption (CMAC, GCM, CBC, ECB) */ + sc_buf[1] = SA_SCCTL_FE_ENC; + } else if (ad->auth_eng.eng_id) { + /* Single-engine authentication (SHA, HMAC) */ + sc_buf[1] = SA_SCCTL_FE_AUTH; + } else { + /* No engines configured */ + return -EINVAL; + } + enc_sc_offset = SA_CTX_PHP_PE_CTX_SZ; + auth_sc_offset = enc_sc_offset + ad->enc_eng.sc_size; + if (ad->auth_eng.eng_id) { if (enc) first_engine = ad->enc_eng.eng_id; else first_engine = ad->auth_eng.eng_id; - enc_sc_offset = SA_CTX_PHP_PE_CTX_SZ; - auth_sc_offset = enc_sc_offset + ad->enc_eng.sc_size; - sc_buf[1] = SA_SCCTL_FE_AUTH_ENC; if (!ad->hash_size) return -EINVAL; ad->hash_size = roundup(ad->hash_size, 8); - } else if (ad->enc_eng.eng_id && !ad->auth_eng.eng_id) { - enc_sc_offset = SA_CTX_PHP_PE_CTX_SZ; + } else if (ad->enc_eng.eng_id) { first_engine = ad->enc_eng.eng_id; - sc_buf[1] = SA_SCCTL_FE_ENC; ad->hash_size = ad->iv_out_size; } @@ -762,9 +1106,15 @@ } /* Prepare context for authentication engine */ - if (ad->auth_eng.sc_size) - sa_set_sc_auth(ad, auth_key, auth_key_sz, + if (ad->auth_eng.sc_size) { + ret = sa_set_sc_auth(ad, auth_key, auth_key_sz, &sc_buf[auth_sc_offset]); + if (ret) { + dev_err(sa_k3_dev, "%s: Error in setting authentication context\n", + __func__); + return ret; + } + } /* Set the ownership of context to CP_ACE */ sc_buf[SA_CTX_SCCTL_OWNER_OFFSET] = 0x80; @@ -772,6 +1122,12 @@ /* swizzle the security context */ sa_swiz_128(sc_buf, SA_CTX_MAX_SZ); + ctx->sc_phys = dma_map_single(dev, ctx->sc, SA_CTX_MAX_SZ, DMA_BIDIRECTIONAL); + if (dma_mapping_error(dev, ctx->sc_phys)) { + mempool_free(ctx->sc, data->sc_pool); + return -ENOMEM; + } + sa_set_swinfo(first_engine, ctx->sc_id, ctx->sc_phys, 1, 0, SA_SW_INFO_FLAG_EVICT, ad->hash_size, swinfo); @@ -784,6 +1140,7 @@ static void sa_free_ctx_info(struct sa_ctx_info *ctx, struct sa_crypto_data *data) { + struct device *dev = &data->pdev->dev; unsigned long bn; bn = ctx->sc_id - data->sc_id_start; @@ -793,7 +1150,9 @@ spin_unlock(&data->scid_lock); if (ctx->sc) { - dma_pool_free(data->sc_pool, ctx->sc, ctx->sc_phys); + memzero_explicit(ctx->sc, SA_CTX_MAX_SZ); + dma_unmap_single(dev, ctx->sc_phys, SA_CTX_MAX_SZ, DMA_BIDIRECTIONAL); + mempool_free(ctx->sc, data->sc_pool); ctx->sc = NULL; } } @@ -812,7 +1171,7 @@ ctx->sc_id = (u16)(data->sc_id_start + bn); - ctx->sc = dma_pool_alloc(data->sc_pool, GFP_KERNEL, &ctx->sc_phys); + ctx->sc = mempool_alloc(data->sc_pool, GFP_KERNEL); if (!ctx->sc) { dev_err(&data->pdev->dev, "Failed to allocate SC memory\n"); err = -ENOMEM; @@ -860,16 +1219,14 @@ if (ret) return ret; ret = sa_init_ctx_info(&ctx->dec, data); - if (ret) { - sa_free_ctx_info(&ctx->enc, data); - return ret; - } + if (ret) + goto ctx_dec_err; child = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); - if (IS_ERR(child)) { dev_err(sa_k3_dev, "Error allocating fallback algo %s\n", name); - return PTR_ERR(child); + ret = PTR_ERR(child); + goto alloc_err; } ctx->fallback.skcipher = child; @@ -880,6 +1237,11 @@ __func__, tfm, ctx->enc.sc_id, &ctx->enc.sc_phys, ctx->dec.sc_id, &ctx->dec.sc_phys); return 0; +alloc_err: + sa_free_ctx_info(&ctx->dec, data); +ctx_dec_err: + sa_free_ctx_info(&ctx->enc, data); + return ret; } static int sa_cipher_setkey(struct crypto_skcipher *tfm, const u8 *key, @@ -895,8 +1257,9 @@ keylen != AES_KEYSIZE_256) return -EINVAL; + ad->ctx = ctx; ad->enc_eng.eng_id = SA_ENG_ID_EM1; - ad->enc_eng.sc_size = SA_CTX_ENC_TYPE1_SZ; + ad->enc_eng.sc_size = SA_CTX_ENC_TYPE_SZ; memzero_explicit(&cfg, sizeof(cfg)); cfg.enc_eng_id = ad->enc_eng.eng_id; @@ -982,6 +1345,87 @@ return sa_cipher_setkey(tfm, key, keylen, &ad); } +/* AEAD algorithm configuration interface function */ +static int sa_gcm_setkey(struct crypto_aead *authenc, + const u8 *key, unsigned int keylen) +{ + struct sa_tfm_ctx *ctx = crypto_aead_ctx(authenc); + struct algo_data ad; + struct sa_cmdl_cfg cfg; + int cmdl_len; + int ret; + + ret = aes_check_keylen(keylen); + if (ret) + return ret; + + /* Convert the key size (16/24/32) to the key size index (0/1/2) */ + int key_idx = (keylen >> 3) - 2; + + if (key_idx >= 3) { + pr_err("%s: Invalid key length\n", __func__); + return -EINVAL; + } + + ad.ctx = ctx; + ad.enc_eng.eng_id = SA_ENG_ID_EM1; + ad.enc_eng.sc_size = SA_CTX_ENC_TYPE_SZ; + ad.mci_enc = mci_gcm_aes_enc_array[key_idx]; + ad.mci_dec = mci_gcm_aes_dec_array[key_idx]; + ad.ealg_id = SA_EALG_ID_AES_GCM; + ad.iv_out_size = 16; + + memset(&cfg, 0, sizeof(cfg)); + cfg.enc = true; + cfg.enc_eng_id = ad.enc_eng.eng_id; + cfg.iv_size = SA_GCM_IV_SIZE; + cfg.is_gcm = true; + + /* Setup Encryption Security Context & Command label template */ + if (sa_init_sc(&ctx->enc, ctx->dev_data->match_data, key, + keylen, NULL, 0, + &ad, 1, &ctx->enc.epib[1])) { + pr_err("%s: sa_init_sc for enc failed\n", __func__); + return -EINVAL; + } + + cmdl_len = sa_format_cmdl_gen(&cfg, + (u8 *)ctx->enc.cmdl, + &ctx->enc.cmdl_upd_info); + if (cmdl_len <= 0 || (cmdl_len > SA_MAX_CMDL_WORDS * sizeof(u32))) { + pr_err("%s: sa_format_cmdl_gen for enc failed\n", __func__); + return -EINVAL; + } + + ctx->enc.cmdl_size = cmdl_len; + + /* Setup Decryption Security Context & Command label template */ + if (sa_init_sc(&ctx->dec, ctx->dev_data->match_data, key, + keylen, NULL, 0, + &ad, 0, &ctx->dec.epib[1])) { + pr_err("%s: sa_init_sc for dec failed\n", __func__); + return -EINVAL; + } + + cfg.enc = false; + cmdl_len = sa_format_cmdl_gen(&cfg, (u8 *)ctx->dec.cmdl, + &ctx->dec.cmdl_upd_info); + + if (cmdl_len <= 0 || (cmdl_len > SA_MAX_CMDL_WORDS * sizeof(u32))) { + pr_err("%s: sa_format_cmdl_gen for dec failed\n", __func__); + return -EINVAL; + } + + ctx->dec.cmdl_size = cmdl_len; + + crypto_aead_clear_flags(ctx->fallback.aead, CRYPTO_TFM_REQ_MASK); + crypto_aead_set_flags(ctx->fallback.aead, + crypto_aead_get_flags(authenc) & + CRYPTO_TFM_REQ_MASK); + + return crypto_aead_setkey(ctx->fallback.aead, key, keylen); +} + static int sa_3des_cbc_setkey(struct crypto_skcipher *tfm, const u8 *key, unsigned int keylen) { @@ -990,7 +1434,7 @@ ad.mci_enc = mci_cbc_3des_enc_array; ad.mci_dec = mci_cbc_3des_dec_array; ad.ealg_id = SA_EALG_ID_3DES_CBC; - ad.iv_idx = 6; + ad.iv_idx = 4; ad.iv_out_size = 8; return sa_cipher_setkey(tfm, key, keylen, &ad); @@ -1010,13 +1454,17 @@ static void sa_sync_from_device(struct sa_rx_data *rxd) { struct sg_table *sgt; + enum dma_data_direction dir; - if (rxd->mapped_sg[0].dir == DMA_BIDIRECTIONAL) + if (rxd->mapped_sg[0].dir == DMA_BIDIRECTIONAL) { sgt = &rxd->mapped_sg[0].sgt; - else + dir = rxd->mapped_sg[0].dir; + } else { sgt = &rxd->mapped_sg[1].sgt; + dir = rxd->mapped_sg[1].dir; + } - dma_sync_sgtable_for_cpu(rxd->ddev, sgt, DMA_FROM_DEVICE); + dma_sync_sgtable_for_cpu(rxd->ddev, sgt, dir); } static void sa_free_sa_rx_data(struct sa_rx_data *rxd) @@ -1028,7 +1476,7 @@ if (mapped_sg->mapped) { dma_unmap_sgtable(rxd->ddev, &mapped_sg->sgt, - mapped_sg->dir, 0); + mapped_sg->dir, DMA_ATTR_SKIP_CPU_SYNC); kfree(mapped_sg->split_sg); } } @@ -1057,12 +1505,16 @@ result[i] = be32_to_cpu(mdptr[i + rxd->iv_idx]); } + if (rxd->hw_locked) { + sa_hw_unlock(rxd->pdata); + rxd->hw_locked = false; + } sa_free_sa_rx_data(rxd); skcipher_request_complete(req, 0); } -static void +static int sa_prepare_tx_desc(u32 *mdptr, u32 pslen, u32 *psdata, u32 epiblen, u32 *epib) { u32 *out, *in; @@ -1075,13 +1527,15 @@ for (out = &mdptr[5], in = psdata, i = 0; i < pslen / sizeof(u32); i++) *out++ = *in++; + + return epiblen + sizeof(u32) + pslen; } static int sa_run(struct sa_req *req) { struct sa_rx_data *rxd; + struct sa_req_ctx_data *req_ctx; gfp_t gfp_flags; - u32 cmdl[SA_MAX_CMDL_WORDS]; struct sa_crypto_data *pdata = dev_get_drvdata(sa_k3_dev); struct device *ddev; struct dma_chan *dma_rx; @@ -1095,6 +1549,8 @@ bool diff_dst; enum dma_data_direction dir_src; struct sa_mapped_sg *mapped_sg; + bool hw_locked = false; + bool may_sleep = req->base->flags & CRYPTO_TFM_REQ_MAY_SLEEP; gfp_flags = req->base->flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL : GFP_ATOMIC; @@ -1102,6 +1558,7 @@ rxd = kzalloc(sizeof(*rxd), gfp_flags); if (!rxd) return -ENOMEM; + rxd->pdata = pdata; if (req->src != req->dst) { diff_dst = true; @@ -1127,21 +1584,29 @@ ddev = dmaengine_get_dma_device(pdata->dma_tx); rxd->ddev = ddev; - memcpy(cmdl, sa_ctx->cmdl, sa_ctx->cmdl_size); - - sa_update_cmdl(req, cmdl, &sa_ctx->cmdl_upd_info); + req_ctx = &rxd->req_ctx; + memset(req_ctx, 0, sizeof(*req_ctx)); - if (req->type != CRYPTO_ALG_TYPE_AHASH) { - if (req->enc) - req->type |= - (SA_REQ_SUBTYPE_ENC << SA_REQ_SUBTYPE_SHIFT); - else - req->type |= - (SA_REQ_SUBTYPE_DEC << SA_REQ_SUBTYPE_SHIFT); + req_ctx->cmdl_size = sa_ctx->cmdl_size; + memcpy(req_ctx->cmdl, sa_ctx->cmdl, req_ctx->cmdl_size); + req_ctx->cmdl_upd_info = sa_ctx->cmdl_upd_info; + + /* Process the command label for this request. + * IMPORTANT: Use local variable to store the processed size. + * sa_ctx->cmdl_size must remain unchanged as it stores the + * template size for use across multiple requests. + */ + u32 cmdl_len = sa_update_cmdl(req, req_ctx->cmdl, + &req_ctx->cmdl_upd_info, + req_ctx->cmdl_size); + + if (cmdl_len > SA_MAX_CMDL_WORDS * sizeof(u32)) { + dev_err(pdata->dev, "sa_update_cmdl returned %u, exceeds max %lu\n", + cmdl_len, SA_MAX_CMDL_WORDS * sizeof(u32)); + kfree(rxd); + return -EINVAL; } - cmdl[sa_ctx->cmdl_size / sizeof(u32)] = req->type; - /* * Map the packets, first we check if the data fits into a single * sg entry and use that if possible. If it does not fit, we check @@ -1193,7 +1658,7 @@ } } - dma_sync_sgtable_for_device(ddev, &mapped_sg->sgt, DMA_TO_DEVICE); + dma_sync_sgtable_for_device(ddev, &mapped_sg->sgt, mapped_sg->dir); if (!diff_dst) { dst_nents = src_nents; @@ -1241,6 +1706,9 @@ } } + sa_hw_lock(pdata, may_sleep); + hw_locked = true; + rxd->tx_in = dmaengine_prep_slave_sg(dma_rx, dst, dst_nents, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); @@ -1253,7 +1721,7 @@ rxd->req = (void *)req->base; rxd->enc = req->enc; rxd->iv_idx = req->ctx->iv_idx; - rxd->enc_iv_size = sa_ctx->cmdl_upd_info.enc_iv.size; + rxd->enc_iv_size = req_ctx->cmdl_upd_info.enc_iv.size; rxd->tx_in->callback = req->callback; rxd->tx_in->callback_param = rxd; @@ -1273,13 +1741,15 @@ */ mdptr = (u32 *)dmaengine_desc_get_metadata_ptr(tx_out, &pl, &ml); - sa_prepare_tx_desc(mdptr, (sa_ctx->cmdl_size + (SA_PSDATA_CTX_WORDS * - sizeof(u32))), cmdl, sizeof(sa_ctx->epib), - sa_ctx->epib); + req->mdata_size = sa_prepare_tx_desc(mdptr, cmdl_len, + req_ctx->cmdl, sizeof(sa_ctx->epib), + sa_ctx->epib); - ml = sa_ctx->cmdl_size + (SA_PSDATA_CTX_WORDS * sizeof(u32)); dmaengine_desc_set_metadata_len(tx_out, req->mdata_size); + rxd->hw_locked = true; + hw_locked = false; + dmaengine_submit(tx_out); dmaengine_submit(rxd->tx_in); @@ -1289,6 +1759,8 @@ return -EINPROGRESS; err_cleanup: + if (hw_locked) + sa_hw_unlock(pdata); sa_free_sa_rx_data(rxd); return ret; @@ -1333,7 +1805,6 @@ sa_req.type = CRYPTO_ALG_TYPE_SKCIPHER; sa_req.enc = enc; sa_req.callback = sa_aes_dma_in_callback; - sa_req.mdata_size = 44; sa_req.base = &req->base; sa_req.ctx = ctx; @@ -1372,34 +1843,62 @@ for (i = 0; i < (authsize / 4); i++) result[i] = be32_to_cpu(mdptr[i + 4]); + if (rxd->hw_locked) { + sa_hw_unlock(rxd->pdata); + rxd->hw_locked = false; + } sa_free_sa_rx_data(rxd); ahash_request_complete(req, 0); } -static int zero_message_process(struct ahash_request *req) +static int sa_sha_digest(struct ahash_request *req) { - struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - int sa_digest_size = crypto_ahash_digestsize(tfm); + struct sa_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct sa_sha_req_ctx *rctx = ahash_request_ctx(req); + struct sa_req sa_req = { 0 }; + size_t auth_len; - switch (sa_digest_size) { - case SHA1_DIGEST_SIZE: - memcpy(req->result, sha1_zero_message_hash, sa_digest_size); - break; - case SHA256_DIGEST_SIZE: - memcpy(req->result, sha256_zero_message_hash, sa_digest_size); - break; - case SHA512_DIGEST_SIZE: - memcpy(req->result, sha512_zero_message_hash, sa_digest_size); - break; - default: - return -EINVAL; + auth_len = req->nbytes; + + if (!auth_len || auth_len > SA_MAX_DATA_SZ || + (auth_len >= SA_UNSAFE_DATA_SZ_MIN && + auth_len <= SA_UNSAFE_DATA_SZ_MAX)) { + struct ahash_request *subreq = &rctx->fallback_req; + int ret = 0; + + ahash_request_set_tfm(subreq, ctx->fallback.ahash); + subreq->base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP; + + crypto_ahash_init(subreq); + + subreq->nbytes = auth_len; + subreq->src = req->src; + subreq->result = req->result; + + ret |= crypto_ahash_update(subreq); + + subreq->nbytes = 0; + + ret |= crypto_ahash_final(subreq); + + return ret; } - return 0; + sa_req.size = auth_len; + sa_req.auth_size = auth_len; + sa_req.src = req->src; + sa_req.dst = req->src; + sa_req.enc = true; + sa_req.type = CRYPTO_ALG_TYPE_AHASH; + sa_req.callback = sa_sha_dma_in_callback; + sa_req.ctx = ctx; + sa_req.base = &req->base; + + return sa_run(&sa_req); } -static int sa_sha_run(struct ahash_request *req) +static int sa_cmac_digest(struct ahash_request *req) { struct sa_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); struct sa_sha_req_ctx *rctx = ahash_request_ctx(req); @@ -1407,11 +1906,7 @@ size_t auth_len; auth_len = req->nbytes; - - if (!auth_len) - return zero_message_process(req); - - if (auth_len > SA_MAX_DATA_SZ || + if (!auth_len || auth_len > SA_MAX_DATA_SZ || (auth_len >= SA_UNSAFE_DATA_SZ_MIN && auth_len <= SA_UNSAFE_DATA_SZ_MAX)) { struct ahash_request *subreq = &rctx->fallback_req; @@ -1436,42 +1931,63 @@ } sa_req.size = auth_len; - sa_req.auth_size = auth_len; sa_req.src = req->src; sa_req.dst = req->src; sa_req.enc = true; sa_req.type = CRYPTO_ALG_TYPE_AHASH; sa_req.callback = sa_sha_dma_in_callback; - sa_req.mdata_size = 28; sa_req.ctx = ctx; sa_req.base = &req->base; + /* + * CMAC uses the encryption engine, not authentication engine. + * Set enc_size for CMAC (uses encryption path). + * + * The CMAC flag (SA_CMDL_UPD_IS_CMAC) was already set during setup + * in sa_format_cmdl_gen(), which enables sa_update_cmdl() to handle + * K1/K2 subkey selection and insertion automatically. + */ + sa_req.enc_size = auth_len; + sa_req.auth_size = 0; + return sa_run(&sa_req); } -static int sa_sha_setup(struct sa_tfm_ctx *ctx, struct algo_data *ad) +static int sa_sha_setup(struct sa_tfm_ctx *ctx, struct algo_data *ad, + const u8 *key, u8 key_sz) { - int bs = crypto_shash_blocksize(ctx->shash); int cmdl_len; struct sa_cmdl_cfg cfg; + int ret; - ad->enc_eng.sc_size = SA_CTX_ENC_TYPE1_SZ; + ad->ctx = ctx; + ad->enc_eng.sc_size = SA_CTX_ENC_TYPE_SZ; ad->auth_eng.eng_id = SA_ENG_ID_AM1; - ad->auth_eng.sc_size = SA_CTX_AUTH_TYPE2_SZ; + ad->auth_eng.sc_size = SA_CTX_AUTH_TYPE_SZ; + + if (key_sz) { + /* Initialize fallback setkey */ + ret = crypto_ahash_setkey(ad->ctx->fallback.ahash, + key, key_sz); + if (ret) { + dev_err(sa_k3_dev, "%s: Failed to set fallback.ahash setkey=%d", + __func__, ret); + return ret; + } + + ad->keyed_mac = true; + ad->prep_iopad = sa_prepare_iopads; + } - memset(ctx->authkey, 0, bs); memset(&cfg, 0, sizeof(cfg)); - cfg.aalg = ad->aalg_id; cfg.enc_eng_id = ad->enc_eng.eng_id; cfg.auth_eng_id = ad->auth_eng.eng_id; cfg.iv_size = 0; - cfg.akey = NULL; - cfg.akey_len = 0; ctx->dev_data = dev_get_drvdata(sa_k3_dev); /* Setup Encryption Security Context & Command label template */ - if (sa_init_sc(&ctx->enc, ctx->dev_data->match_data, NULL, 0, NULL, 0, - ad, 0, &ctx->enc.epib[1])) + if (sa_init_sc(&ctx->enc, ctx->dev_data->match_data, NULL, 0, key, + key_sz, ad, 0, &ctx->enc.epib[1])) goto badkey; cmdl_len = sa_format_cmdl_gen(&cfg, @@ -1489,7 +2005,7 @@ return -EINVAL; } -static int sa_sha_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base) +static int sa_sha_cra_init_alg(struct crypto_tfm *tfm, const char *hash, const char *alg_base) { struct sa_tfm_ctx *ctx = crypto_tfm_ctx(tfm); struct sa_crypto_data *data = dev_get_drvdata(sa_k3_dev); @@ -1501,23 +2017,31 @@ if (ret) return ret; - if (alg_base) { - ctx->shash = crypto_alloc_shash(alg_base, 0, + if (!alg_base) + dev_err(sa_k3_dev, "alg_base is NULL\n"); + + if (hash) { + /* Allocating fallback for intermediate setkey calculations */ + ctx->shash = crypto_alloc_shash(hash, 0, CRYPTO_ALG_NEED_FALLBACK); if (IS_ERR(ctx->shash)) { dev_err(sa_k3_dev, "base driver %s couldn't be loaded\n", alg_base); return PTR_ERR(ctx->shash); } - /* for fallback */ - ctx->fallback.ahash = - crypto_alloc_ahash(alg_base, 0, - CRYPTO_ALG_NEED_FALLBACK); - if (IS_ERR(ctx->fallback.ahash)) { - dev_err(ctx->dev_data->dev, - "Could not load fallback driver\n"); - return PTR_ERR(ctx->fallback.ahash); - } + } else { + dev_dbg(sa_k3_dev, "%s: hash is NULL so not allocating ctx->shash\n", + __func__); + } + + /* for fallback */ + ctx->fallback.ahash = + crypto_alloc_ahash(alg_base, 0, + CRYPTO_ALG_NEED_FALLBACK); + if (IS_ERR(ctx->fallback.ahash)) { + dev_err(ctx->dev_data->dev, + "Could not load fallback driver\n"); + return PTR_ERR(ctx->fallback.ahash); } dev_dbg(sa_k3_dev, "%s(0x%p) sc-ids(0x%x(0x%pad), 0x%x(0x%pad))\n", @@ -1531,11 +2055,6 @@ return 0; } -static int sa_sha_digest(struct ahash_request *req) -{ - return sa_sha_run(req); -} - static int sa_sha_init(struct ahash_request *req) { struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); @@ -1629,13 +2148,13 @@ struct algo_data ad = { 0 }; struct sa_tfm_ctx *ctx = crypto_tfm_ctx(tfm); - sa_sha_cra_init_alg(tfm, "sha1"); + sa_sha_cra_init_alg(tfm, NULL, "sha1"); ad.aalg_id = SA_AALG_ID_SHA1; ad.hash_size = SHA1_DIGEST_SIZE; ad.auth_ctrl = SA_AUTH_SW_CTRL_SHA1; - sa_sha_setup(ctx, &ad); + sa_sha_setup(ctx, &ad, NULL, 0); return 0; } @@ -1645,13 +2164,13 @@ struct algo_data ad = { 0 }; struct sa_tfm_ctx *ctx = crypto_tfm_ctx(tfm); - sa_sha_cra_init_alg(tfm, "sha256"); + sa_sha_cra_init_alg(tfm, NULL, "sha256"); ad.aalg_id = SA_AALG_ID_SHA2_256; ad.hash_size = SHA256_DIGEST_SIZE; ad.auth_ctrl = SA_AUTH_SW_CTRL_SHA256; - sa_sha_setup(ctx, &ad); + sa_sha_setup(ctx, &ad, NULL, 0); return 0; } @@ -1661,17 +2180,327 @@ struct algo_data ad = { 0 }; struct sa_tfm_ctx *ctx = crypto_tfm_ctx(tfm); - sa_sha_cra_init_alg(tfm, "sha512"); + sa_sha_cra_init_alg(tfm, NULL, "sha512"); ad.aalg_id = SA_AALG_ID_SHA2_512; ad.hash_size = SHA512_DIGEST_SIZE; ad.auth_ctrl = SA_AUTH_SW_CTRL_SHA512; - sa_sha_setup(ctx, &ad); + sa_sha_setup(ctx, &ad, NULL, 0); return 0; } +static int sa_hmac_cra_init(struct crypto_tfm *tfm) +{ + const char *alg_name = crypto_tfm_alg_name(tfm); + int ret = -EINVAL; + + if (!strcmp(alg_name, "hmac(sha1)")) + ret = sa_sha_cra_init_alg(tfm, "sha1", alg_name); + else if (!strcmp(alg_name, "hmac(sha256)")) + ret = sa_sha_cra_init_alg(tfm, "sha256", alg_name); + else if (!strcmp(alg_name, "hmac(sha512)")) + ret = sa_sha_cra_init_alg(tfm, "sha512", alg_name); + else + dev_err(sa_k3_dev, "%s: unsupported algo %s\n", __func__, alg_name); + + return ret; +} + +/** + * cmac_gf_double() - GF(2^128) doubling operation for CMAC subkey derivation + * @in: Input 128-bit value as two u64 words (big-endian) + * @out: Output 128-bit value (can be same as input for in-place operation) + * @gfmask: GF(2^128) reduction polynomial (0x87 for CMAC) + * + * Performs: out = (in << 1) XOR (gfmask if MSB(in) = 1) + * Per NIST SP 800-38B section 6.1 + */ +static inline void cmac_gf_double(const u64 in[2], u64 out[2], u8 gfmask) +{ + u8 msb = (in[1] >> 63); + + out[1] = (in[1] << 1) | (in[0] >> 63); + out[0] = (in[0] << 1) ^ (msb ? gfmask : 0); +} + +/** + * sa_prepare_cmac_subkeys() - Derive CMAC subkeys K1 and K2 + * @data: Algorithm data structure + * @key: AES encryption key + * @key_sz: Key size in bytes (16, 24, or 32) + * @subkey1: Output buffer for K1 (16 bytes) + * @subkey2: Output buffer for K2 (16 bytes) + * + * Derives CMAC subkeys according to NIST SP 800-38B: + * L = AES(key, 0^128) + * K1 = L << 1, XOR 0x87 if MSB(L) = 1 + * K2 = K1 << 1, XOR 0x87 if MSB(K1) = 1 + * + * Return: 0 on success, negative error code on failure + */ +static int sa_prepare_cmac_subkeys(struct algo_data *data, const u8 *key, + u16 key_sz, __be32 *subkey1, __be32 *subkey2) +{ + SYNC_SKCIPHER_REQUEST_ON_STACK(req, data->ctx->skcipher); + struct scatterlist sg; + u8 *L; + u64 k1[2], k2[2]; + const u8 gfmask = 0x87; /* GF(2^128) reduction polynomial */ + int ret; + + /* Allocate buffer from heap to avoid cache flush issues with stack memory */ + L = kmalloc(AES_BLOCK_SIZE, GFP_KERNEL); + if (!L) + return -ENOMEM; + + /* Set key for ECB(AES) cipher */ + ret = crypto_sync_skcipher_setkey(data->ctx->skcipher, key, key_sz); + if (ret) { + dev_err(sa_k3_dev, "%s: crypto_sync_skcipher_setkey failed, ret=%d\n", + __func__, ret); + goto out_free; + } + + /* Step 1: Encrypt zero block to get L = AES(key, 0) */ + memset(L, 0, AES_BLOCK_SIZE); + sg_init_one(&sg, L, AES_BLOCK_SIZE); + skcipher_request_set_sync_tfm(req, data->ctx->skcipher); + skcipher_request_set_crypt(req, &sg, &sg, AES_BLOCK_SIZE, NULL); + + ret = crypto_skcipher_encrypt(req); + if (ret) { + dev_err(sa_k3_dev, "%s: crypto_skcipher_encrypt failed, ret=%d\n", + __func__, ret); + goto out_free; + } + + /* Convert to u64 for easier manipulation (big-endian) */ + k1[1] = get_unaligned_be64(L); /* Upper 64 bits */ + k1[0] = get_unaligned_be64(L + 8); /* Lower 64 bits */ + + /* Step 2: Derive K1 = L << 1, XOR 0x87 if MSB(L) = 1 */ + cmac_gf_double(k1, k1, gfmask); + + /* Store K1 in big-endian format */ + put_unaligned_be64(k1[1], (u8 *)subkey1); + put_unaligned_be64(k1[0], (u8 *)subkey1 + 8); + + /* Step 3: Derive K2 = K1 << 1, XOR 0x87 if MSB(K1) = 1 */ + cmac_gf_double(k1, k2, gfmask); + + /* Store K2 in big-endian format */ + put_unaligned_be64(k2[1], (u8 *)subkey2); + put_unaligned_be64(k2[0], (u8 *)subkey2 + 8); + + ret = 0; + +out_free: + /* Clear sensitive data on all exit paths before freeing */ + memzero_explicit(L, AES_BLOCK_SIZE); + memzero_explicit(k1, sizeof(k1)); + memzero_explicit(k2, sizeof(k2)); + kfree(L); + return ret; +} + +/** + * sa_cmac_setup() - Setup CMAC algorithm context + * @ctx: Transform context + * @ad: Algorithm data + * @key: AES key + * @key_sz: Key size + * + * Initializes CMAC context with: + * - Encryption engine for AES operations + * - Derives K1 and K2 subkeys and stores them in cmdl_upd_info.aux_key[] + * - Sets up command label for runtime subkey passing + */ +static int sa_cmac_setup(struct sa_tfm_ctx *ctx, struct algo_data *ad, + const u8 *key, u8 key_sz) +{ + int cmdl_len; + struct sa_cmdl_cfg cfg; + int ret; + __be32 *k1_storage, *k2_storage; + + ad->ctx = ctx; + ad->enc_eng.eng_id = SA_ENG_ID_EM1; /* Use encryption engine for CMAC */ + ad->enc_eng.sc_size = SA_CTX_ENC_TYPE_SZ; + + if (key_sz) { + /* Initialize fallback setkey */ + ret = crypto_ahash_setkey(ad->ctx->fallback.ahash, + key, key_sz); + if (ret) { + dev_err(sa_k3_dev, "%s: Failed to set fallback.ahash setkey=%d", + __func__, ret); + return ret; + } + + ad->keyed_mac = true; + } + + memset(&cfg, 0, sizeof(cfg)); + cfg.enc_eng_id = ad->enc_eng.eng_id; + cfg.iv_size = 0; + cfg.is_cmac = true; + cfg.enc = true; + + ctx->dev_data = dev_get_drvdata(sa_k3_dev); + + /* Setup Security Context & Command label template + * CMAC uses encryption key for both encryption and authentication + * Use enc=1 to enter the MCI code path (selects mci_enc) + */ + if (sa_init_sc(&ctx->enc, ctx->dev_data->match_data, key, key_sz, + NULL, 0, ad, 1, &ctx->enc.epib[1])) + goto badkey; + + cmdl_len = sa_format_cmdl_gen(&cfg, + (u8 *)ctx->enc.cmdl, + &ctx->enc.cmdl_upd_info); + if (cmdl_len <= 0 || (cmdl_len > SA_MAX_CMDL_WORDS * sizeof(u32))) + goto badkey; + + ctx->enc.cmdl_size = cmdl_len; + + /* + * Derive and store CMAC subkeys K1 and K2 in cmdl_upd_info.aux_key[] + * for runtime access: + * - K1: aux_key[0-3] (words 0-3, bytes 0-15) + * - K2: aux_key[4-7] (words 4-7, bytes 16-31) + * + * The appropriate subkey will be selected at runtime in sa_sha_digest() + * based on message length and passed via command label option bytes. + */ + if (ad->keyed_mac && ad->prep_cmac) { + k1_storage = (__be32 *)&ctx->enc.cmdl_upd_info.aux_key[0]; + k2_storage = (__be32 *)&ctx->enc.cmdl_upd_info.aux_key[4]; + + ret = ad->prep_cmac(ad, key, key_sz, k1_storage, k2_storage); + if (ret) { + dev_err(sa_k3_dev, "%s: prep_cmac failed, ret=%d\n", + __func__, ret); + return ret; + } + } + + return 0; + +badkey: + dev_err(sa_k3_dev, "%s: badkey\n", __func__); + return -EINVAL; +} + +static int sa_cmac_aes_setkey(struct crypto_ahash *ahash, const u8 *key, + unsigned int keylen) +{ + struct crypto_tfm *tfm = crypto_ahash_tfm(ahash); + struct sa_tfm_ctx *ctx = crypto_tfm_ctx(tfm); + struct algo_data ad = { 0 }; + int key_idx; + + /* Validate key length for AES */ + if (aes_check_keylen(keylen)) + return -EINVAL; + + /* Determine key index for MCI selection */ + key_idx = (keylen >> 3) - 2; /* 128->0, 192->1, 256->2 */ + if (key_idx >= 3) + return -EINVAL; + + /* Setup algorithm data for CMAC */ + ad.ctx = ctx; + ad.enc_eng.eng_id = SA_ENG_ID_EM1; /* Encryption engine */ + ad.enc_eng.sc_size = SA_CTX_ENC_TYPE_SZ; + ad.aalg_id = SA_AALG_ID_CMAC; + ad.hash_size = SA_CMAC_DIGEST_SIZE; + ad.iv_out_size = SA_CMAC_DIGEST_SIZE; /* CRITICAL: Output size for egress trailer */ + ad.keyed_mac = true; + ad.prep_cmac = sa_prepare_cmac_subkeys; + + /* Set the appropriate CMAC MCI based on key length */ + /* CMAC needs both mci_enc and mci_dec set to the same MCI */ + ad.mci_enc = mci_cmac_aes_array[key_idx]; + ad.mci_dec = mci_cmac_aes_array[key_idx]; + + /* Use CMAC-specific setup instead of SHA setup */ + return sa_cmac_setup(ctx, &ad, key, keylen); +} + +static int sa_cmac_aes_cra_init(struct crypto_tfm *tfm) +{ + struct sa_tfm_ctx *ctx = crypto_tfm_ctx(tfm); + struct sa_crypto_data *data = dev_get_drvdata(sa_k3_dev); + int ret; + + /* Initialize context */ + memset(ctx, 0, sizeof(*ctx)); + ctx->dev_data = data; + + /* Initialize context info for hardware */ + ret = sa_init_ctx_info(&ctx->enc, data); + if (ret) + return ret; + + /* + * Allocate ECB(AES) cipher for CMAC subkey derivation (AES(key, 0)) + * Request generic software implementation to avoid DMA issues with + * stack-allocated buffers + */ + ctx->skcipher = crypto_alloc_sync_skcipher("ecb(aes)", 0, CRYPTO_ALG_NEED_FALLBACK); + if (IS_ERR(ctx->skcipher)) { + dev_err(sa_k3_dev, "Failed to allocate ecb(aes) for CMAC subkey derivation\n"); + return PTR_ERR(ctx->skcipher); + } + + /* Allocate fallback for CMAC */ + ctx->fallback.ahash = crypto_alloc_ahash("cmac(aes)", 0, + CRYPTO_ALG_NEED_FALLBACK); + if (IS_ERR(ctx->fallback.ahash)) { + dev_err(sa_k3_dev, "Failed to allocate cmac(aes) fallback\n"); + crypto_free_sync_skcipher(ctx->skcipher); + return PTR_ERR(ctx->fallback.ahash); + } + + /* Set request size for ahash requests */ + crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), + sizeof(struct sa_sha_req_ctx) + + crypto_ahash_reqsize(ctx->fallback.ahash)); + + return 0; +} + +static int sa_hmac_sha_setkey(struct crypto_ahash *ahash, const u8 *key, + unsigned int keylen) +{ + struct crypto_tfm *tfm = crypto_ahash_tfm(ahash); + const char *alg_name = crypto_tfm_alg_name(tfm); + struct sa_tfm_ctx *ctx = crypto_tfm_ctx(tfm); + struct algo_data ad = { 0 }; + + if (!strcmp(alg_name, "hmac(sha1)")) { + ad.aalg_id = SA_AALG_ID_SHA1; + ad.hash_size = SHA1_DIGEST_SIZE; + ad.auth_ctrl = SA_AUTH_SW_CTRL_SHA1; + } else if (!strcmp(alg_name, "hmac(sha256)")) { + ad.aalg_id = SA_AALG_ID_SHA2_256; + ad.hash_size = SHA256_DIGEST_SIZE; + ad.auth_ctrl = SA_AUTH_SW_CTRL_SHA256; + } else if (!strcmp(alg_name, "hmac(sha512)")) { + ad.aalg_id = SA_AALG_ID_SHA2_512; + ad.hash_size = SHA512_DIGEST_SIZE; + ad.auth_ctrl = SA_AUTH_SW_CTRL_SHA512; + } else { + dev_err(sa_k3_dev, "%s: unsupported algo %s\n", __func__, alg_name); + return -EINVAL; + } + + return sa_sha_setup(ctx, &ad, key, keylen); +} + static void sa_sha_cra_exit(struct crypto_tfm *tfm) { struct sa_tfm_ctx *ctx = crypto_tfm_ctx(tfm); @@ -1684,6 +2513,7 @@ if (crypto_tfm_alg_type(tfm) == CRYPTO_ALG_TYPE_AHASH) sa_free_ctx_info(&ctx->enc, data); + crypto_free_sync_skcipher(ctx->skcipher); crypto_free_shash(ctx->shash); crypto_free_ahash(ctx->fallback.ahash); } @@ -1708,7 +2538,7 @@ authsize = crypto_aead_authsize(tfm); mdptr = (u32 *)dmaengine_desc_get_metadata_ptr(rxd->tx_in, &pl, &ml); - for (i = 0; i < (authsize / 4); i++) + for (i = 0; i < (crypto_aead_maxauthsize(tfm) / 4); i++) mdptr[i + 4] = swab32(mdptr[i + 4]); if (rxd->enc) { @@ -1722,6 +2552,10 @@ err = memcmp(&mdptr[4], auth_tag, authsize) ? -EBADMSG : 0; } + if (rxd->hw_locked) { + sa_hw_unlock(rxd->pdata); + rxd->hw_locked = false; + } sa_free_sa_rx_data(rxd); aead_request_complete(req, err); @@ -1772,6 +2606,55 @@ return ret; } +static int sa_cra_init_gcm(struct crypto_aead *tfm) +{ + const char *helper_name = "ecb(aes)"; + const char *fallback = crypto_tfm_alg_name(crypto_aead_tfm(tfm)); + struct sa_tfm_ctx *ctx = crypto_aead_ctx(tfm); + struct sa_crypto_data *data = dev_get_drvdata(sa_k3_dev); + int ret; + + memzero_explicit(ctx, sizeof(*ctx)); + ctx->dev_data = data; + + ctx->skcipher = crypto_alloc_sync_skcipher(helper_name, 0, CRYPTO_ALG_NEED_FALLBACK); + if (IS_ERR(ctx->skcipher)) { + dev_err(sa_k3_dev, "base driver %s couldn't be loaded\n", helper_name); + return PTR_ERR(ctx->skcipher); + } + + ctx->fallback.aead = crypto_alloc_aead(fallback, 0, + CRYPTO_ALG_NEED_FALLBACK); + + if (IS_ERR(ctx->fallback.aead)) { + dev_err(sa_k3_dev, "fallback driver %s couldn't be loaded\n", + fallback); + return PTR_ERR(ctx->fallback.aead); + } + + crypto_aead_set_reqsize(tfm, sizeof(struct aead_request) + + crypto_aead_reqsize(ctx->fallback.aead)); + + ret = sa_init_ctx_info(&ctx->enc, data); + if (ret) { + pr_err("%s: %d: sa_init_ctx_info failed with ret = %d\n", __func__, __LINE__, ret); + return ret; + } + + ret = sa_init_ctx_info(&ctx->dec, data); + if (ret) { + pr_err("%s: %d: sa_init_ctx_info failed with ret = %d\n", __func__, __LINE__, ret); + sa_free_ctx_info(&ctx->enc, data); + return ret; + } + + dev_dbg(sa_k3_dev, "%s(0x%p) sc-ids(0x%x(0x%pad), 0x%x(0x%pad))\n", + __func__, tfm, ctx->enc.sc_id, &ctx->enc.sc_phys, + ctx->dec.sc_id, &ctx->dec.sc_phys); + + return ret; +} + static int sa_cra_init_aead_sha1(struct crypto_aead *tfm) { return sa_cra_init_aead(tfm, "sha1", @@ -1817,9 +2700,9 @@ ad->ctx = ctx; ad->enc_eng.eng_id = SA_ENG_ID_EM1; - ad->enc_eng.sc_size = SA_CTX_ENC_TYPE1_SZ; + ad->enc_eng.sc_size = SA_CTX_ENC_TYPE_SZ; ad->auth_eng.eng_id = SA_ENG_ID_AM1; - ad->auth_eng.sc_size = SA_CTX_AUTH_TYPE2_SZ; + ad->auth_eng.sc_size = SA_CTX_AUTH_TYPE_SZ; ad->mci_enc = mci_cbc_enc_no_iv_array[key_idx]; ad->mci_dec = mci_cbc_dec_no_iv_array[key_idx]; ad->inv_key = true; @@ -1829,12 +2712,9 @@ memset(&cfg, 0, sizeof(cfg)); cfg.enc = true; - cfg.aalg = ad->aalg_id; cfg.enc_eng_id = ad->enc_eng.eng_id; cfg.auth_eng_id = ad->auth_eng.eng_id; cfg.iv_size = crypto_aead_ivsize(authenc); - cfg.akey = keys.authkey; - cfg.akey_len = keys.authkeylen; /* Setup Encryption Security Context & Command label template */ if (sa_init_sc(&ctx->enc, ctx->dev_data->match_data, keys.enckey, @@ -1947,7 +2827,6 @@ sa_req.type = CRYPTO_ALG_TYPE_AEAD; sa_req.enc = enc; sa_req.callback = sa_aead_dma_in_callback; - sa_req.mdata_size = 52; sa_req.base = &req->base; sa_req.ctx = ctx; sa_req.src = req->src; @@ -1968,6 +2847,92 @@ return sa_aead_run(req, req->iv, 0); } +static int sa_gcm_run(struct aead_request *req, int enc) +{ + struct crypto_aead *tfm = crypto_aead_reqtfm(req); + struct sa_tfm_ctx *ctx = crypto_aead_ctx(tfm); + struct sa_req sa_req = { 0 }; + size_t auth_size, enc_size; + u8 final_iv[SA_GCM_IV_SIZE]; + + enc_size = req->cryptlen; + auth_size = req->assoclen + req->cryptlen; + + if (!enc) { + enc_size -= crypto_aead_authsize(tfm); + auth_size -= crypto_aead_authsize(tfm); + } + + if (req->assoclen > SA_MAX_ASSOC_SZ || !enc_size || + (auth_size > SA_MAX_DATA_SZ || + (auth_size >= SA_UNSAFE_DATA_SZ_MIN && + auth_size <= SA_UNSAFE_DATA_SZ_MAX))) { + struct aead_request *subreq = aead_request_ctx(req); + int ret; + + aead_request_set_tfm(subreq, ctx->fallback.aead); + aead_request_set_callback(subreq, req->base.flags, + req->base.complete, req->base.data); + aead_request_set_crypt(subreq, req->src, req->dst, + req->cryptlen, req->iv); + aead_request_set_ad(subreq, req->assoclen); + + ret = enc ? crypto_aead_encrypt(subreq) : + crypto_aead_decrypt(subreq); + return ret; + } + + /* + * SA2UL requires the IV field to be 16 bytes long ( IV, Counter ) + * and the last byte of the counter should be initialized to 01 + */ + memset(final_iv, 0, sizeof(final_iv)); + memcpy(final_iv, req->iv, GCM_AES_IV_SIZE); + + /* Set the counter as 0x01 */ + final_iv[15] = 0x01; + + sg_copy_to_buffer(req->src, sg_nents_for_len(req->src, req->assoclen), + sa_req.aad, req->assoclen); + + sa_req.enc_offset = req->assoclen; + sa_req.enc_size = enc_size; + sa_req.size = auth_size; + sa_req.enc_iv = final_iv; + sa_req.type = CRYPTO_ALG_TYPE_AEAD; + sa_req.enc = enc; + sa_req.callback = sa_aead_dma_in_callback; + sa_req.base = &req->base; + sa_req.ctx = ctx; + sa_req.src = req->src; + sa_req.dst = req->dst; + sa_req.aad_length = req->assoclen; + + return sa_run(&sa_req); +} + +static int sa_gcm_encrypt(struct aead_request *req) +{ + return sa_gcm_run(req, 1); +} + +static int sa_gcm_decrypt(struct aead_request *req) +{ + return sa_gcm_run(req, 0); +} + +static void sa_exit_tfm_gcm(struct crypto_aead *tfm) +{ + struct sa_tfm_ctx *ctx = crypto_aead_ctx(tfm); + struct sa_crypto_data *data = dev_get_drvdata(sa_k3_dev); + + crypto_free_sync_skcipher(ctx->skcipher); + crypto_free_aead(ctx->fallback.aead); + + sa_free_ctx_info(&ctx->enc, data); + sa_free_ctx_info(&ctx->dec, data); +} + static struct sa_alg_tmpl sa_algs[] = { [SA_ALG_CBC_AES] = { .type = CRYPTO_ALG_TYPE_SKCIPHER, @@ -2201,6 +3166,150 @@ .decrypt = sa_aead_decrypt, }, }, + [SA_ALG_HMAC_SHA256] = { + .type = CRYPTO_ALG_TYPE_AHASH, + .alg.ahash = { + .halg.base = { + .cra_name = "hmac(sha256)", + .cra_driver_name = "hmac(sha256-sa2ul)", + .cra_priority = 1000, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize = SHA256_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct sa_tfm_ctx), + .cra_module = THIS_MODULE, + .cra_init = sa_hmac_cra_init, + .cra_exit = sa_sha_cra_exit, + }, + .halg.digestsize = SHA256_DIGEST_SIZE, + .halg.statesize = sizeof(struct sa_sha_req_ctx) + + sizeof(struct sha256_state), + .init = sa_sha_init, + .update = sa_sha_update, + .final = sa_sha_final, + .finup = sa_sha_finup, + .setkey = sa_hmac_sha_setkey, + .digest = sa_sha_digest, + .export = sa_sha_export, + .import = sa_sha_import, + }, + }, + [SA_ALG_HMAC_SHA1] = { + .type = CRYPTO_ALG_TYPE_AHASH, + .alg.ahash = { + .halg.base = { + .cra_name = "hmac(sha1)", + .cra_driver_name = "hmac(sha1-sa2ul)", + .cra_priority = 400, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize = SHA1_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct sa_tfm_ctx), + .cra_module = THIS_MODULE, + .cra_init = sa_hmac_cra_init, + .cra_exit = sa_sha_cra_exit, + }, + .halg.digestsize = SHA1_DIGEST_SIZE, + .halg.statesize = sizeof(struct sa_sha_req_ctx) + + sizeof(struct sha1_state), + .init = sa_sha_init, + .update = sa_sha_update, + .final = sa_sha_final, + .finup = sa_sha_finup, + .setkey = sa_hmac_sha_setkey, + .digest = sa_sha_digest, + .export = sa_sha_export, + .import = sa_sha_import, + }, + }, + [SA_ALG_HMAC_SHA512] = { + .type = CRYPTO_ALG_TYPE_AHASH, + .alg.ahash = { + .halg.base = { + .cra_name = "hmac(sha512)", + .cra_driver_name = "hmac(sha512-sa2ul)", + .cra_priority = 400, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize = SHA512_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct sa_tfm_ctx), + .cra_module = THIS_MODULE, + .cra_init = sa_hmac_cra_init, + .cra_exit = sa_sha_cra_exit, + }, + .halg.digestsize = SHA512_DIGEST_SIZE, + .halg.statesize = sizeof(struct sa_sha_req_ctx) + + sizeof(struct sha512_state), + .init = sa_sha_init, + .update = sa_sha_update, + .final = sa_sha_final, + .finup = sa_sha_finup, + .setkey = sa_hmac_sha_setkey, + .digest = sa_sha_digest, + .export = sa_sha_export, + .import = sa_sha_import, + }, + }, + [SA_ALG_CMAC_AES] = { + .type = CRYPTO_ALG_TYPE_AHASH, + .alg.ahash = { + .halg.base = { + .cra_name = "cmac(aes)", + .cra_driver_name = "cmac-aes-sa2ul", + .cra_priority = 400, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize = SA_CMAC_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct sa_tfm_ctx), + .cra_module = THIS_MODULE, + .cra_init = sa_cmac_aes_cra_init, + .cra_exit = sa_sha_cra_exit, + }, + .halg.digestsize = SA_CMAC_DIGEST_SIZE, + .halg.statesize = sizeof(struct sa_sha_req_ctx) + + SA_CMAC_DIGEST_SIZE, + .init = sa_sha_init, + .update = sa_sha_update, + .final = sa_sha_final, + .finup = sa_sha_finup, + .setkey = sa_cmac_aes_setkey, + .digest = sa_cmac_digest, + .export = sa_sha_export, + .import = sa_sha_import, + }, + }, + [SA_ALG_GCM_AES] = { + .type = CRYPTO_ALG_TYPE_AEAD, + .alg.aead = { + .base.cra_name = "gcm(aes)", + .base.cra_driver_name = "gcm-aes-sa2ul", + .base.cra_priority = 30000, + .base.cra_flags = CRYPTO_ALG_TYPE_AEAD | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK, + .base.cra_blocksize = 1, + .base.cra_ctxsize = sizeof(struct sa_tfm_ctx), + .base.cra_module = THIS_MODULE, + .ivsize = GCM_AES_IV_SIZE, + .maxauthsize = AES_BLOCK_SIZE, + .init = sa_cra_init_gcm, + .exit = sa_exit_tfm_gcm, + .setauthsize = sa_aead_setauthsize, + .setkey = sa_gcm_setkey, + .encrypt = sa_gcm_encrypt, + .decrypt = sa_gcm_decrypt, + } + }, + }; /* Register the algorithms in crypto framework */ @@ -2262,48 +3371,42 @@ } } -static int sa_init_mem(struct sa_crypto_data *dev_data) +static int sa_dma_init(struct sa_crypto_data *dev_data) { + int ret; + struct dma_slave_config cfg; struct device *dev = &dev_data->pdev->dev; + /* Setup dma pool for security context buffers */ - dev_data->sc_pool = dma_pool_create("keystone-sc", dev, - SA_CTX_MAX_SZ, 64, 0); + dev_data->sc_pool = mempool_create_kmalloc_pool(64, SA_CTX_MAX_SZ); if (!dev_data->sc_pool) { dev_err(dev, "Failed to create dma pool"); return -ENOMEM; } - return 0; -} - -static int sa_dma_init(struct sa_crypto_data *dd) -{ - int ret; - struct dma_slave_config cfg; - - dd->dma_rx1 = NULL; - dd->dma_tx = NULL; - dd->dma_rx2 = NULL; + dev_data->dma_rx1 = NULL; + dev_data->dma_tx = NULL; + dev_data->dma_rx2 = NULL; - ret = dma_coerce_mask_and_coherent(dd->dev, DMA_BIT_MASK(48)); + ret = dma_coerce_mask_and_coherent(dev_data->dev, DMA_BIT_MASK(48)); if (ret) - return ret; + goto err_dma_coerce; - dd->dma_rx1 = dma_request_chan(dd->dev, "rx1"); - if (IS_ERR(dd->dma_rx1)) - return dev_err_probe(dd->dev, PTR_ERR(dd->dma_rx1), + dev_data->dma_rx1 = dma_request_chan(dev_data->dev, "rx1"); + if (IS_ERR(dev_data->dma_rx1)) + return dev_err_probe(dev_data->dev, PTR_ERR(dev_data->dma_rx1), "Unable to request rx1 DMA channel\n"); - dd->dma_rx2 = dma_request_chan(dd->dev, "rx2"); - if (IS_ERR(dd->dma_rx2)) { - ret = dev_err_probe(dd->dev, PTR_ERR(dd->dma_rx2), + dev_data->dma_rx2 = dma_request_chan(dev_data->dev, "rx2"); + if (IS_ERR(dev_data->dma_rx2)) { + ret = dev_err_probe(dev_data->dev, PTR_ERR(dev_data->dma_rx2), "Unable to request rx2 DMA channel\n"); goto err_dma_rx2; } - dd->dma_tx = dma_request_chan(dd->dev, "tx"); - if (IS_ERR(dd->dma_tx)) { - ret = dev_err_probe(dd->dev, PTR_ERR(dd->dma_tx), + dev_data->dma_tx = dma_request_chan(dev_data->dev, "tx"); + if (IS_ERR(dev_data->dma_tx)) { + ret = dev_err_probe(dev_data->dev, PTR_ERR(dev_data->dma_tx), "Unable to request tx DMA channel\n"); goto err_dma_tx; } @@ -2315,23 +3418,23 @@ cfg.src_maxburst = 4; cfg.dst_maxburst = 4; - ret = dmaengine_slave_config(dd->dma_rx1, &cfg); + ret = dmaengine_slave_config(dev_data->dma_rx1, &cfg); if (ret) { - dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", + dev_err(dev_data->dev, "can't configure IN dmaengine slave: %d\n", ret); goto err_dma_config; } - ret = dmaengine_slave_config(dd->dma_rx2, &cfg); + ret = dmaengine_slave_config(dev_data->dma_rx2, &cfg); if (ret) { - dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", + dev_err(dev_data->dev, "can't configure IN dmaengine slave: %d\n", ret); goto err_dma_config; } - ret = dmaengine_slave_config(dd->dma_tx, &cfg); + ret = dmaengine_slave_config(dev_data->dma_tx, &cfg); if (ret) { - dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", + dev_err(dev_data->dev, "can't configure OUT dmaengine slave: %d\n", ret); goto err_dma_config; } @@ -2339,15 +3442,25 @@ return 0; err_dma_config: - dma_release_channel(dd->dma_tx); + dma_release_channel(dev_data->dma_tx); err_dma_tx: - dma_release_channel(dd->dma_rx2); + dma_release_channel(dev_data->dma_rx2); err_dma_rx2: - dma_release_channel(dd->dma_rx1); + dma_release_channel(dev_data->dma_rx1); +err_dma_coerce: + mempool_destroy(dev_data->sc_pool); return ret; } +static void sa_dma_cleanup(struct sa_crypto_data *dev_data) +{ + dma_release_channel(dev_data->dma_rx2); + dma_release_channel(dev_data->dma_rx1); + dma_release_channel(dev_data->dma_tx); + mempool_destroy(dev_data->sc_pool); +} + static int sa_link_child(struct device *dev, void *data) { struct device *parent = data; @@ -2368,7 +3481,12 @@ BIT(SA_ALG_SHA256) | BIT(SA_ALG_SHA512) | BIT(SA_ALG_AUTHENC_SHA1_AES) | - BIT(SA_ALG_AUTHENC_SHA256_AES), + BIT(SA_ALG_AUTHENC_SHA256_AES) | + BIT(SA_ALG_HMAC_SHA1) | + BIT(SA_ALG_HMAC_SHA256) | + BIT(SA_ALG_HMAC_SHA512) | + BIT(SA_ALG_GCM_AES) | + BIT(SA_ALG_CMAC_AES) }; static struct sa_match_data am64_match_data = { @@ -2378,7 +3496,9 @@ BIT(SA_ALG_EBC_AES) | BIT(SA_ALG_SHA256) | BIT(SA_ALG_SHA512) | - BIT(SA_ALG_AUTHENC_SHA256_AES), + BIT(SA_ALG_AUTHENC_SHA256_AES) | + BIT(SA_ALG_GCM_AES) | + BIT(SA_ALG_CMAC_AES) }; static const struct of_device_id of_match[] = { @@ -2426,12 +3546,14 @@ return ret; } - sa_init_mem(dev_data); ret = sa_dma_init(dev_data); if (ret) - goto destroy_dma_pool; + goto disable_pm_runtime; spin_lock_init(&dev_data->scid_lock); + spin_lock_init(&dev_data->hw.lock); + init_waitqueue_head(&dev_data->hw.wq); + dev_data->hw.busy = false; val = SA_EEC_ENCSS_EN | SA_EEC_AUTHSS_EN | SA_EEC_CTXCACH_EN | SA_EEC_CPPI_PORT_IN_EN | SA_EEC_CPPI_PORT_OUT_EN | @@ -2453,14 +3575,9 @@ release_dma: sa_unregister_algos(dev); + sa_dma_cleanup(dev_data); - dma_release_channel(dev_data->dma_rx2); - dma_release_channel(dev_data->dma_rx1); - dma_release_channel(dev_data->dma_tx); - -destroy_dma_pool: - dma_pool_destroy(dev_data->sc_pool); - +disable_pm_runtime: pm_runtime_put_sync(dev); pm_runtime_disable(dev); @@ -2474,12 +3591,7 @@ of_platform_depopulate(&pdev->dev); sa_unregister_algos(&pdev->dev); - - dma_release_channel(dev_data->dma_rx2); - dma_release_channel(dev_data->dma_rx1); - dma_release_channel(dev_data->dma_tx); - - dma_pool_destroy(dev_data->sc_pool); + sa_dma_cleanup(dev_data); platform_set_drvdata(pdev, NULL); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/crypto/sa2ul.h v_kernel/drivers/crypto/sa2ul.h --- linux-6.12.57/drivers/crypto/sa2ul.h 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/crypto/sa2ul.h 2026-04-21 11:35:35.884934523 +0200 @@ -31,24 +31,9 @@ #define SA_EEC_CPPI_PORT_IN_EN 0x00000200 #define SA_EEC_CPPI_PORT_OUT_EN 0x00000800 -/* - * Encoding used to identify the typo of crypto operation - * performed on the packet when the packet is returned - * by SA - */ -#define SA_REQ_SUBTYPE_ENC 0x0001 -#define SA_REQ_SUBTYPE_DEC 0x0002 -#define SA_REQ_SUBTYPE_SHIFT 16 -#define SA_REQ_SUBTYPE_MASK 0xffff - /* Number of 32 bit words in EPIB */ #define SA_DMA_NUM_EPIB_WORDS 4 -/* Number of 32 bit words in PS data */ -#define SA_DMA_NUM_PS_WORDS 16 -#define NKEY_SZ 3 -#define MCI_SZ 27 - /* * Maximum number of simultaeneous security contexts * supported by the driver @@ -61,12 +46,6 @@ #define SA_CTX_SIZE_TO_DMA_SIZE(ctx_sz) \ ((ctx_sz) ? ((ctx_sz) / 32 - 1) : 0) -#define SA_CTX_ENC_KEY_OFFSET 32 -#define SA_CTX_ENC_AUX1_OFFSET 64 -#define SA_CTX_ENC_AUX2_OFFSET 96 -#define SA_CTX_ENC_AUX3_OFFSET 112 -#define SA_CTX_ENC_AUX4_OFFSET 128 - /* Next Engine Select code in CP_ACE */ #define SA_ENG_ID_EM1 2 /* Enc/Dec engine with AES/DEC core */ #define SA_ENG_ID_EM2 3 /* Encryption/Decryption enginefor pass 2 */ @@ -110,15 +89,12 @@ #define SA_CTX_PE_PKT_TYPE_IPSEC_ESP 3 /* Indicates that it is in data mode, It may not be used by PHP */ #define SA_CTX_PE_PKT_TYPE_NONE 4 -#define SA_CTX_ENC_TYPE1_SZ 64 /* Encryption SC with Key only */ -#define SA_CTX_ENC_TYPE2_SZ 96 /* Encryption SC with Key and Aux1 */ - -#define SA_CTX_AUTH_TYPE1_SZ 64 /* Auth SC with Key only */ -#define SA_CTX_AUTH_TYPE2_SZ 96 /* Auth SC with Key and Aux1 */ +#define SA_CTX_ENC_TYPE_SZ 128 /* Encryption SC with Key and Aux1 */ +#define SA_CTX_AUTH_TYPE_SZ 160 /* Auth SC with Key and Aux1 and Aux2 */ /* Size of security context for PHP engine */ #define SA_CTX_PHP_PE_CTX_SZ 64 -#define SA_CTX_MAX_SZ (64 + SA_CTX_ENC_TYPE2_SZ + SA_CTX_AUTH_TYPE2_SZ) +#define SA_CTX_MAX_SZ (64 + SA_CTX_ENC_TYPE_SZ + SA_CTX_AUTH_TYPE_SZ) /* * Encoding of F/E control in SCCTL @@ -143,14 +119,13 @@ */ #define SA_CTX_SCCTL_OWNER_OFFSET 0 -#define SA_CTX_ENC_KEY_OFFSET 32 -#define SA_CTX_ENC_AUX1_OFFSET 64 -#define SA_CTX_ENC_AUX2_OFFSET 96 -#define SA_CTX_ENC_AUX3_OFFSET 112 -#define SA_CTX_ENC_AUX4_OFFSET 128 - -#define SA_SCCTL_FE_AUTH_ENC 0x65 -#define SA_SCCTL_FE_ENC 0x8D +/* + * SCCTL Fetch/Evict control values + * Based on bit encoding: [7:6]=evict PHP, [5:4]=fetch auth, [3:2]=fetch enc, [1:0]=fetch PHP + */ +#define SA_SCCTL_FE_AUTH_ENC 0x6D /* Dual-engine: PHP + Enc + Auth (authenc) */ +#define SA_SCCTL_FE_ENC 0x8D /* Single-engine Enc: PHP + Enc + evict (CMAC, GCM, CBC) */ +#define SA_SCCTL_FE_AUTH 0x4D /* Single-engine Auth: PHP + Auth (SHA, HMAC) */ #define SA_ALIGN_MASK (sizeof(u32) - 1) #define SA_ALIGNED __aligned(32) @@ -164,6 +139,8 @@ /* SA2UL can only handle maximum data size of 64KB */ #define SA_MAX_DATA_SZ U16_MAX +/* SA2UL can only handle maximum data size of 64KB */ +#define SA_MAX_ASSOC_SZ 16 /* * SA2UL can provide unpredictable results with packet sizes that fall @@ -175,6 +152,18 @@ struct sa_match_data; /** + * struct sa_hw_state - Hardware-level lock state + * @lock: Spinlock to protect busy flag + * @wq: Wait queue for hardware availability + * @busy: Hardware busy flag + */ +struct sa_hw_state { + spinlock_t lock; + wait_queue_head_t wq; + bool busy; +}; + +/** * struct sa_crypto_data - Crypto driver instance data * @base: Base address of the register space * @soc_data: Pointer to SoC specific data @@ -195,7 +184,7 @@ void __iomem *base; const struct sa_match_data *match_data; struct platform_device *pdev; - struct dma_pool *sc_pool; + mempool_t *sc_pool; struct device *dev; spinlock_t scid_lock; /* lock for SC-ID allocation */ /* Security context data */ @@ -208,6 +197,7 @@ struct dma_chan *dma_rx1; struct dma_chan *dma_rx2; struct dma_chan *dma_tx; + struct sa_hw_state hw; }; /** @@ -261,16 +251,8 @@ u32 aux_key[SA_MAX_AUX_DATA_WORDS]; }; -/* - * Number of 32bit words appended after the command label - * in PSDATA to identify the crypto request context. - * word-0: Request type - * word-1: pointer to request - */ -#define SA_PSDATA_CTX_WORDS 4 - /* Maximum size of Command label in 32 words */ -#define SA_MAX_CMDL_WORDS (SA_DMA_NUM_PS_WORDS - SA_PSDATA_CTX_WORDS) +#define SA_MAX_CMDL_WORDS 24 /** * struct sa_ctx_info: SA context information @@ -294,6 +276,18 @@ }; /** + * struct sa_req_ctx_data - Per-request snapshot of command label metadata + * @cmdl_size: template command label size in bytes + * @cmdl: mutable command label buffer for the request + * @cmdl_upd_info: request-local copy of update metadata + */ +struct sa_req_ctx_data { + u16 cmdl_size; + u32 cmdl[SA_MAX_CMDL_WORDS]; + struct sa_cmdl_upd_info cmdl_upd_info; +}; + +/** * struct sa_tfm_ctx: TFM context structure * @dev_data: struct sa_crypto_data pointer * @enc: struct sa_ctx_info for encryption @@ -308,11 +302,9 @@ struct sa_ctx_info enc; struct sa_ctx_info dec; struct sa_ctx_info auth; - int keylen; int iv_idx; - u32 key[AES_KEYSIZE_256 / sizeof(u32)]; - u8 authkey[SHA512_BLOCK_SIZE]; struct crypto_shash *shash; + struct crypto_sync_skcipher *skcipher; /* for fallback */ union { struct crypto_skcipher *skcipher; @@ -329,7 +321,6 @@ */ struct sa_sha_req_ctx { struct sa_crypto_data *dev_data; - u32 cmdl[SA_MAX_CMDL_WORDS + SA_PSDATA_CTX_WORDS]; struct ahash_request fallback_req; }; @@ -350,7 +341,7 @@ SA_EALG_ID_DES_CBC, /* DES CBC mode */ SA_EALG_ID_3DES_CBC, /* 3DES CBC mode */ SA_EALG_ID_CCM, /* Counter with CBC-MAC mode */ - SA_EALG_ID_GCM, /* Galois Counter mode */ + SA_EALG_ID_AES_GCM, /* Galois Counter mode */ SA_EALG_ID_AES_ECB, SA_EALG_ID_LAST }; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/crypto/ti/dthev2-aes.c v_kernel/drivers/crypto/ti/dthev2-aes.c --- linux-6.12.57/drivers/crypto/ti/dthev2-aes.c 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/crypto/ti/dthev2-aes.c 2026-04-21 11:35:35.894934549 +0200 @@ -0,0 +1,1369 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * K3 DTHE V2 crypto accelerator driver + * + * Copyright (C) Texas Instruments 2025 - https://www.ti.com + * Author: T Pratham + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "dthev2-common.h" + +#include +#include +#include +#include +#include +#include +#include + +/* Registers */ + +// AES Engine +#define DTHE_P_AES_BASE 0x7000 + +#define DTHE_P_AES_KEY1_0 0x0038 +#define DTHE_P_AES_KEY1_1 0x003C +#define DTHE_P_AES_KEY1_2 0x0030 +#define DTHE_P_AES_KEY1_3 0x0034 +#define DTHE_P_AES_KEY1_4 0x0028 +#define DTHE_P_AES_KEY1_5 0x002C +#define DTHE_P_AES_KEY1_6 0x0020 +#define DTHE_P_AES_KEY1_7 0x0024 + +#define DTHE_P_AES_KEY2_0 0x0018 +#define DTHE_P_AES_KEY2_1 0x001C +#define DTHE_P_AES_KEY2_2 0x0010 +#define DTHE_P_AES_KEY2_3 0x0014 +#define DTHE_P_AES_KEY2_4 0x0008 +#define DTHE_P_AES_KEY2_5 0x000C +#define DTHE_P_AES_KEY2_6 0x0000 +#define DTHE_P_AES_KEY2_7 0x0004 + +#define DTHE_P_AES_IV_IN_0 0x0040 +#define DTHE_P_AES_IV_IN_1 0x0044 +#define DTHE_P_AES_IV_IN_2 0x0048 +#define DTHE_P_AES_IV_IN_3 0x004C +#define DTHE_P_AES_CTRL 0x0050 +#define DTHE_P_AES_C_LENGTH_0 0x0054 +#define DTHE_P_AES_C_LENGTH_1 0x0058 +#define DTHE_P_AES_AUTH_LENGTH 0x005C +#define DTHE_P_AES_DATA_IN_OUT 0x0060 +#define DTHE_P_AES_TAG_OUT 0x0070 + +#define DTHE_P_AES_SYSCONFIG 0x0084 +#define DTHE_P_AES_IRQSTATUS 0x008C +#define DTHE_P_AES_IRQENABLE 0x0090 + +/* Register write values and macros */ + +enum aes_ctrl_mode_masks { + AES_CTRL_ECB_MASK = 0x00, + AES_CTRL_CBC_MASK = BIT(5), + AES_CTRL_CTR_MASK = BIT(6), + AES_CTRL_XTS_MASK = BIT(12) | BIT(11), + AES_CTRL_GCM_MASK = BIT(17) | BIT(16) | BIT(6), + AES_CTRL_CCM_MASK = BIT(18) | BIT(6), +}; + +#define DTHE_AES_CTRL_MODE_CLEAR_MASK ~GENMASK(28, 5) + +#define DTHE_AES_CTRL_DIR_ENC BIT(2) + +#define DTHE_AES_CTRL_KEYSIZE_16B BIT(3) +#define DTHE_AES_CTRL_KEYSIZE_24B BIT(4) +#define DTHE_AES_CTRL_KEYSIZE_32B (BIT(3) | BIT(4)) + +#define DTHE_AES_CTRL_CTR_WIDTH_128B (BIT(7) | BIT(8)) + +#define DTHE_AES_CCM_L_FROM_IV_MASK GENMASK(2, 0) +#define DTHE_AES_CCM_M_BITS GENMASK(2, 0) +#define DTHE_AES_CTRL_CCM_L_FIELD_MASK GENMASK(21, 19) +#define DTHE_AES_CTRL_CCM_M_FIELD_MASK GENMASK(24, 22) + +#define DTHE_AES_CTRL_SAVE_CTX_SET BIT(29) + +#define DTHE_AES_CTRL_OUTPUT_READY BIT_MASK(0) +#define DTHE_AES_CTRL_INPUT_READY BIT_MASK(1) +#define DTHE_AES_CTRL_SAVED_CTX_READY BIT_MASK(30) +#define DTHE_AES_CTRL_CTX_READY BIT_MASK(31) + +#define DTHE_AES_SYSCONFIG_DMA_DATA_IN_OUT_EN GENMASK(6, 5) +#define DTHE_AES_IRQENABLE_EN_ALL GENMASK(3, 0) + +/* Misc */ +#define AES_IV_SIZE AES_BLOCK_SIZE +#define AES_BLOCK_WORDS (AES_BLOCK_SIZE / sizeof(u32)) +#define AES_IV_WORDS AES_BLOCK_WORDS +#define DTHE_AES_GCM_AAD_MAXLEN (BIT_ULL(32) - 1) +#define DTHE_AES_CCM_AAD_MAXLEN (BIT(16) - BIT(8)) +#define DTHE_AES_CCM_CRYPT_MAXLEN (BIT_ULL(61) - 1) +#define POLL_TIMEOUT_INTERVAL HZ + +static int cnt; + +static int dthe_cipher_init_tfm(struct crypto_skcipher *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm); + struct dthe_data *dev_data = dthe_get_dev(ctx); + + crypto_skcipher_set_reqsize(tfm, sizeof(struct dthe_aes_req_ctx)); + + ctx->dev_data = dev_data; + ctx->keylen = 0; + + return 0; +} + +static int dthe_cipher_xts_init_tfm(struct crypto_skcipher *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm); + struct dthe_data *dev_data = dthe_get_dev(ctx); + + crypto_skcipher_set_reqsize(tfm, sizeof(struct dthe_aes_req_ctx)); + + ctx->dev_data = dev_data; + ctx->keylen = 0; + + ctx->skcipher_fb = crypto_alloc_sync_skcipher("xts(aes)", 0, + CRYPTO_ALG_NEED_FALLBACK); + if (IS_ERR(ctx->skcipher_fb)) { + dev_err(dev_data->dev, "fallback driver xts(aes) couldn't be loaded\n"); + return PTR_ERR(ctx->skcipher_fb); + } + + return 0; +} + +static void dthe_cipher_xts_exit_tfm(struct crypto_skcipher *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm); + + crypto_free_sync_skcipher(ctx->skcipher_fb); +} + +static int dthe_aes_ecb_setkey(struct crypto_skcipher *tfm, const u8 *key, unsigned int keylen) +{ + struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm); + + if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && keylen != AES_KEYSIZE_256) + return -EINVAL; + + ctx->aes_mode = DTHE_AES_ECB; + ctx->keylen = keylen; + memcpy(ctx->key, key, keylen); + + return 0; +} + +static int dthe_aes_cbc_setkey(struct crypto_skcipher *tfm, const u8 *key, unsigned int keylen) +{ + struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm); + + if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && keylen != AES_KEYSIZE_256) + return -EINVAL; + + ctx->aes_mode = DTHE_AES_CBC; + ctx->keylen = keylen; + memcpy(ctx->key, key, keylen); + + return 0; +} + +static int dthe_aes_ctr_setkey(struct crypto_skcipher *tfm, const u8 *key, unsigned int keylen) +{ + struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm); + + if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && keylen != AES_KEYSIZE_256) + return -EINVAL; + + ctx->aes_mode = DTHE_AES_CTR; + ctx->keylen = keylen; + memcpy(ctx->key, key, keylen); + + return 0; +} + +static int dthe_aes_xts_setkey(struct crypto_skcipher *tfm, const u8 *key, unsigned int keylen) +{ + struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm); + + if (keylen != 2 * AES_KEYSIZE_128 && + keylen != 2 * AES_KEYSIZE_192 && + keylen != 2 * AES_KEYSIZE_256) + return -EINVAL; + + ctx->aes_mode = DTHE_AES_XTS; + ctx->keylen = keylen / 2; + memcpy(ctx->key, key, keylen); + + crypto_sync_skcipher_clear_flags(ctx->skcipher_fb, CRYPTO_TFM_REQ_MASK); + crypto_sync_skcipher_set_flags(ctx->skcipher_fb, + crypto_skcipher_get_flags(tfm) & + CRYPTO_TFM_REQ_MASK); + + return crypto_sync_skcipher_setkey(ctx->skcipher_fb, key, keylen); +} + +static void dthe_aes_set_ctrl_key(struct dthe_tfm_ctx *ctx, + struct dthe_aes_req_ctx *rctx, + u32 *iv_in) +{ + struct dthe_data *dev_data = dthe_get_dev(ctx); + void __iomem *aes_base_reg = dev_data->regs + DTHE_P_AES_BASE; + u32 ctrl_val = 0; + + writel_relaxed(ctx->key[0], aes_base_reg + DTHE_P_AES_KEY1_0); + writel_relaxed(ctx->key[1], aes_base_reg + DTHE_P_AES_KEY1_1); + writel_relaxed(ctx->key[2], aes_base_reg + DTHE_P_AES_KEY1_2); + writel_relaxed(ctx->key[3], aes_base_reg + DTHE_P_AES_KEY1_3); + + if (ctx->keylen > AES_KEYSIZE_128) { + writel_relaxed(ctx->key[4], aes_base_reg + DTHE_P_AES_KEY1_4); + writel_relaxed(ctx->key[5], aes_base_reg + DTHE_P_AES_KEY1_5); + } + if (ctx->keylen == AES_KEYSIZE_256) { + writel_relaxed(ctx->key[6], aes_base_reg + DTHE_P_AES_KEY1_6); + writel_relaxed(ctx->key[7], aes_base_reg + DTHE_P_AES_KEY1_7); + } + + if (ctx->aes_mode == DTHE_AES_XTS) { + size_t key2_offset = ctx->keylen / sizeof(u32); + + writel_relaxed(ctx->key[key2_offset + 0], aes_base_reg + DTHE_P_AES_KEY2_0); + writel_relaxed(ctx->key[key2_offset + 1], aes_base_reg + DTHE_P_AES_KEY2_1); + writel_relaxed(ctx->key[key2_offset + 2], aes_base_reg + DTHE_P_AES_KEY2_2); + writel_relaxed(ctx->key[key2_offset + 3], aes_base_reg + DTHE_P_AES_KEY2_3); + + if (ctx->keylen > AES_KEYSIZE_128) { + writel_relaxed(ctx->key[key2_offset + 4], aes_base_reg + DTHE_P_AES_KEY2_4); + writel_relaxed(ctx->key[key2_offset + 5], aes_base_reg + DTHE_P_AES_KEY2_5); + } + if (ctx->keylen == AES_KEYSIZE_256) { + writel_relaxed(ctx->key[key2_offset + 6], aes_base_reg + DTHE_P_AES_KEY2_6); + writel_relaxed(ctx->key[key2_offset + 7], aes_base_reg + DTHE_P_AES_KEY2_7); + } + } + + if (rctx->enc) + ctrl_val |= DTHE_AES_CTRL_DIR_ENC; + + if (ctx->keylen == AES_KEYSIZE_128) + ctrl_val |= DTHE_AES_CTRL_KEYSIZE_16B; + else if (ctx->keylen == AES_KEYSIZE_192) + ctrl_val |= DTHE_AES_CTRL_KEYSIZE_24B; + else + ctrl_val |= DTHE_AES_CTRL_KEYSIZE_32B; + + // Write AES mode + ctrl_val &= DTHE_AES_CTRL_MODE_CLEAR_MASK; + switch (ctx->aes_mode) { + case DTHE_AES_ECB: + ctrl_val |= AES_CTRL_ECB_MASK; + break; + case DTHE_AES_CBC: + ctrl_val |= AES_CTRL_CBC_MASK; + break; + case DTHE_AES_CTR: + ctrl_val |= AES_CTRL_CTR_MASK; + ctrl_val |= DTHE_AES_CTRL_CTR_WIDTH_128B; + break; + case DTHE_AES_XTS: + ctrl_val |= AES_CTRL_XTS_MASK; + break; + case DTHE_AES_GCM: + ctrl_val |= AES_CTRL_GCM_MASK; + break; + case DTHE_AES_CCM: + ctrl_val |= AES_CTRL_CCM_MASK; + ctrl_val |= FIELD_PREP(DTHE_AES_CTRL_CCM_L_FIELD_MASK, + (iv_in[0] & DTHE_AES_CCM_L_FROM_IV_MASK)); + ctrl_val |= FIELD_PREP(DTHE_AES_CTRL_CCM_M_FIELD_MASK, + ((ctx->authsize - 2) >> 1) & DTHE_AES_CCM_M_BITS); + break; + } + + if (iv_in) { + ctrl_val |= DTHE_AES_CTRL_SAVE_CTX_SET; + for (int i = 0; i < AES_IV_WORDS; ++i) + writel_relaxed(iv_in[i], + aes_base_reg + DTHE_P_AES_IV_IN_0 + (DTHE_REG_SIZE * i)); + } + + writel_relaxed(ctrl_val, aes_base_reg + DTHE_P_AES_CTRL); +} + +static void dthe_aes_dma_in_callback(void *data) +{ + struct skcipher_request *req = (struct skcipher_request *)data; + struct dthe_aes_req_ctx *rctx = skcipher_request_ctx(req); + + complete(&rctx->aes_compl); +} + +static int dthe_aes_run(struct crypto_engine *engine, void *areq) +{ + struct skcipher_request *req = container_of(areq, struct skcipher_request, base); + struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req)); + struct dthe_data *dev_data = dthe_get_dev(ctx); + struct dthe_aes_req_ctx *rctx = skcipher_request_ctx(req); + + unsigned int len = req->cryptlen; + struct scatterlist *src = req->src; + struct scatterlist *dst = req->dst; + + struct scatterlist src_padded[2], dst_padded[2]; + + int src_nents = sg_nents_for_len(src, len); + int dst_nents = sg_nents_for_len(dst, len); + + int src_mapped_nents; + int dst_mapped_nents; + + u8 *pad_buf = rctx->padding; + int pad_len = 0; + + bool diff_dst; + enum dma_data_direction src_dir, dst_dir; + + struct device *tx_dev, *rx_dev; + struct dma_async_tx_descriptor *desc_in, *desc_out; + + int ret; + + void __iomem *aes_base_reg = dev_data->regs + DTHE_P_AES_BASE; + + u32 aes_sysconfig_val = readl_relaxed(aes_base_reg + DTHE_P_AES_SYSCONFIG); + + aes_sysconfig_val |= DTHE_AES_SYSCONFIG_DMA_DATA_IN_OUT_EN; + writel_relaxed(aes_sysconfig_val, aes_base_reg + DTHE_P_AES_SYSCONFIG); + + if (ctx->aes_mode == DTHE_AES_CTR) { + /* + * CTR mode can operate on any input length, but the hardware + * requires input length to be a multiple of the block size. + * We need to handle the padding in the driver. + */ + if (req->cryptlen % AES_BLOCK_SIZE) { + /* Need to create a new SG list with padding */ + pad_len = ALIGN(req->cryptlen, AES_BLOCK_SIZE) - req->cryptlen; + struct scatterlist *sg; + + memset(pad_buf, 0, pad_len); + + sg_init_table(src_padded, 2); + sg = sg_last(req->src, src_nents); + sg_set_page(&src_padded[0], sg_page(sg), sg->length, sg->offset); + sg_set_buf(&src_padded[1], pad_buf, pad_len); + + /* First nent can't be an empty chain nent */ + if (src_nents == 1) + src = src_padded; + else + sg_chain(sg, 1, src_padded); + + src_nents++; + + if (req->src == req->dst) { + /* In-place operation, use same SG for dst */ + dst = src; + dst_nents = src_nents; + } else { + sg_init_table(dst_padded, 2); + sg = sg_last(req->dst, dst_nents); + sg_set_page(&dst_padded[0], sg_page(sg), sg->length, sg->offset); + sg_set_buf(&dst_padded[1], pad_buf, pad_len); + + if (dst_nents == 1) + dst = dst_padded; + else + sg_chain(sg, 1, dst_padded); + + dst_nents++; + } + } + } + + if (src == dst) { + diff_dst = false; + src_dir = DMA_BIDIRECTIONAL; + dst_dir = DMA_BIDIRECTIONAL; + } else { + diff_dst = true; + src_dir = DMA_TO_DEVICE; + dst_dir = DMA_FROM_DEVICE; + } + + tx_dev = dmaengine_get_dma_device(dev_data->dma_aes_tx); + rx_dev = dmaengine_get_dma_device(dev_data->dma_aes_rx); + + src_mapped_nents = dma_map_sg(tx_dev, src, src_nents, src_dir); + if (src_mapped_nents == 0) { + ret = -EINVAL; + goto aes_map_src_err; + } + + if (!diff_dst) { + dst_mapped_nents = src_mapped_nents; + } else { + dst_mapped_nents = dma_map_sg(rx_dev, dst, dst_nents, dst_dir); + if (dst_mapped_nents == 0) { + dma_unmap_sg(tx_dev, src, src_nents, src_dir); + ret = -EINVAL; + goto aes_map_dst_err; + } + } + + // HACK: Delay to workaround DMA driver issue + cnt++; + if (cnt % 20 == 0) { + unsigned long delay = jiffies + usecs_to_jiffies(1000); + + while (time_before(jiffies, delay)) + cond_resched(); + cnt = 0; + } + + desc_in = dmaengine_prep_slave_sg(dev_data->dma_aes_rx, dst, dst_mapped_nents, + DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + if (!desc_in) { + dev_err(dev_data->dev, "IN prep_slave_sg() failed\n"); + ret = -EINVAL; + goto aes_prep_err; + } + + desc_out = dmaengine_prep_slave_sg(dev_data->dma_aes_tx, src, src_mapped_nents, + DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + if (!desc_out) { + dev_err(dev_data->dev, "OUT prep_slave_sg() failed\n"); + ret = -EINVAL; + goto aes_prep_err; + } + + desc_in->callback = dthe_aes_dma_in_callback; + desc_in->callback_param = req; + + init_completion(&rctx->aes_compl); + + if (ctx->aes_mode == DTHE_AES_ECB) + dthe_aes_set_ctrl_key(ctx, rctx, NULL); + else + dthe_aes_set_ctrl_key(ctx, rctx, (u32 *)req->iv); + + writel_relaxed(lower_32_bits(req->cryptlen), aes_base_reg + DTHE_P_AES_C_LENGTH_0); + writel_relaxed(upper_32_bits(req->cryptlen), aes_base_reg + DTHE_P_AES_C_LENGTH_1); + + dmaengine_submit(desc_in); + dmaengine_submit(desc_out); + + dma_async_issue_pending(dev_data->dma_aes_rx); + dma_async_issue_pending(dev_data->dma_aes_tx); + + // Need to do a timeout to ensure finalise gets called if DMA callback fails for any reason + ret = wait_for_completion_timeout(&rctx->aes_compl, msecs_to_jiffies(DTHE_DMA_TIMEOUT_MS)); + if (!ret) { + ret = -ETIMEDOUT; + dmaengine_terminate_sync(dev_data->dma_aes_rx); + dmaengine_terminate_sync(dev_data->dma_aes_tx); + + for (int i = 0; i < AES_BLOCK_WORDS; ++i) + readl_relaxed(aes_base_reg + DTHE_P_AES_DATA_IN_OUT + (DTHE_REG_SIZE * i)); + } else { + ret = 0; + } + + // For modes other than ECB, read IV_OUT + if (ctx->aes_mode != DTHE_AES_ECB) { + u32 *iv_out = (u32 *)req->iv; + + for (int i = 0; i < AES_IV_WORDS; ++i) + iv_out[i] = readl_relaxed(aes_base_reg + + DTHE_P_AES_IV_IN_0 + + (DTHE_REG_SIZE * i)); + } + +aes_prep_err: + if (dst_dir != DMA_BIDIRECTIONAL) + dma_unmap_sg(rx_dev, dst, dst_nents, dst_dir); +aes_map_dst_err: + dma_unmap_sg(tx_dev, src, src_nents, src_dir); + +aes_map_src_err: + if (ctx->aes_mode == DTHE_AES_CTR && req->cryptlen % AES_BLOCK_SIZE) { + struct scatterlist *sg; + unsigned int i; + + /* + * Last nent in original sglist is converted to a chain sg. + * Need to revert that to keep the original sglist intact. + */ + if (src_nents > 2) { + /* + * The last 2 nents are from our {src,dst}_padded sg. + * Go to the (n-3)th nent. Then the next in memory is + * the chain sg pointing to our {src,dst}_padded sg. + */ + for (i = 0, sg = req->src; i < src_nents - 3; ++i) + sg = sg_next(sg); + sg++; + sg->page_link &= ~SG_CHAIN; + sg_set_page(sg, sg_page(&src_padded[0]), src_padded[0].length, + src_padded[0].offset); + sg_mark_end(sg); + } + + if (req->src != req->dst && dst_nents > 2) { + for (i = 0, sg = req->dst; i < dst_nents - 3; ++i) + sg = sg_next(sg); + sg++; + sg->page_link &= ~SG_CHAIN; + sg_set_page(sg, sg_page(&dst_padded[0]), dst_padded[0].length, + dst_padded[0].offset); + sg_mark_end(sg); + } + } + + local_bh_disable(); + crypto_finalize_skcipher_request(dev_data->aes_engine, req, ret); + local_bh_enable(); + return 0; +} + +static int dthe_aes_crypt(struct skcipher_request *req) +{ + struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req)); + struct dthe_aes_req_ctx *rctx = skcipher_request_ctx(req); + struct dthe_data *dev_data = dthe_get_dev(ctx); + struct crypto_engine *engine; + + /* + * If data is not a multiple of AES_BLOCK_SIZE: + * - need to return -EINVAL for ECB, CBC as they are block ciphers + * - need to fallback to software as H/W doesn't support Ciphertext Stealing for XTS + * - do nothing for CTR + */ + if (req->cryptlen % AES_BLOCK_SIZE) { + if (ctx->aes_mode == DTHE_AES_XTS) { + SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->skcipher_fb); + + skcipher_request_set_sync_tfm(subreq, ctx->skcipher_fb); + skcipher_request_set_callback(subreq, req->base.flags, + req->base.complete, req->base.data); + skcipher_request_set_crypt(subreq, req->src, req->dst, + req->cryptlen, req->iv); + + return rctx->enc ? crypto_skcipher_encrypt(subreq) : + crypto_skcipher_decrypt(subreq); + } + if (ctx->aes_mode != DTHE_AES_CTR) + return -EINVAL; + } + + /* + * If data length input is zero, no need to do any operation. + * Except for XTS mode, where data should be non-zero. + */ + if (req->cryptlen == 0) { + if (ctx->aes_mode == DTHE_AES_XTS) + return -EINVAL; + return 0; + } + + engine = dev_data->aes_engine; + return crypto_transfer_skcipher_request_to_engine(engine, req); +} + +static int dthe_aes_encrypt(struct skcipher_request *req) +{ + struct dthe_aes_req_ctx *rctx = skcipher_request_ctx(req); + + rctx->enc = 1; + return dthe_aes_crypt(req); +} + +static int dthe_aes_decrypt(struct skcipher_request *req) +{ + struct dthe_aes_req_ctx *rctx = skcipher_request_ctx(req); + + rctx->enc = 0; + return dthe_aes_crypt(req); +} + +static int dthe_aead_init_tfm(struct crypto_aead *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_aead_ctx(tfm); + struct dthe_data *dev_data = dthe_get_dev(ctx); + + memzero_explicit(ctx, sizeof(*ctx)); + ctx->dev_data = dev_data; + + const char *alg_name = crypto_tfm_alg_name(&tfm->base); + + ctx->aead_fb = crypto_alloc_sync_aead(alg_name, 0, + CRYPTO_ALG_NEED_FALLBACK); + if (IS_ERR(ctx->aead_fb)) { + dev_err(dev_data->dev, "fallback driver %s couldn't be loaded\n", + alg_name); + return PTR_ERR(ctx->aead_fb); + } + + crypto_aead_set_reqsize(tfm, sizeof(struct dthe_aes_req_ctx)); + + return 0; +} + +static void dthe_aead_exit_tfm(struct crypto_aead *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_aead_ctx(tfm); + + crypto_free_sync_aead(ctx->aead_fb); +} + +/** + * dthe_aead_prep_src - Prepare source scatterlist for AEAD from input req->src + * @sg: Input req->src scatterlist + * @assoclen: Input req->assoclen + * @cryptlen: Input req->cryptlen (minus size of TAG in decryption) + * @assoc_pad_buf: Buffer to hold AAD padding if needed + * @crypt_pad_buf: Buffer to hold ciphertext/plaintext padding if needed + * + * Description: + * For modes with authentication, DTHEv2 hardware requires the input AAD and + * plaintext/ciphertext to be individually aligned to AES_BLOCK_SIZE. If either is not + * aligned, it needs to be padded with zeros by the software before passing the data to + * the hardware. However, linux crypto's aead_request provides the input with AAD and + * plaintext/ciphertext contiguously appended together in a single scatterlist. + * + * This helper function takes the input scatterlist and splits it into separate + * scatterlists for AAD and plaintext/ciphertext, ensuring each is aligned to + * AES_BLOCK_SIZE by adding necessary padding, and then merges the aligned scatterlists + * back into a single scatterlist for processing. + * + * Return: + * Pointer to the merged scatterlist, or ERR_PTR(error) on failure. + * The calling function needs to free the returned scatterlist when done. + **/ +static struct scatterlist *dthe_aead_prep_src(struct scatterlist *sg, + unsigned int assoclen, + unsigned int cryptlen, + u8 *assoc_pad_buf, + u8 *crypt_pad_buf) +{ + struct scatterlist *in_sg[2]; + struct scatterlist *to_sg; + struct scatterlist *src; + size_t split_sizes[2] = {assoclen, cryptlen}; + int out_mapped_nents[2]; + int crypt_nents = 0, assoc_nents = 0, src_nents = 0; + int err = 0; + + /* sg_split does not work properly if one of the split_sizes is 0 */ + if (cryptlen == 0 || assoclen == 0) { + /* + * Assigning both to sg does not matter as assoclen = 0 or cryptlen = 0 + * being passed to dthe_copy_sg will take care to copy the sg correctly + */ + in_sg[0] = sg; + in_sg[1] = sg; + + src_nents = sg_nents_for_len(sg, assoclen + cryptlen); + } else { + err = sg_split(sg, 0, 0, 2, split_sizes, in_sg, out_mapped_nents, GFP_ATOMIC); + if (err) + goto dthe_aead_prep_src_split_err; + assoc_nents = sg_nents_for_len(in_sg[0], assoclen); + crypt_nents = sg_nents_for_len(in_sg[1], cryptlen); + + src_nents = assoc_nents + crypt_nents; + } + + if (assoclen % AES_BLOCK_SIZE) + src_nents++; + if (cryptlen % AES_BLOCK_SIZE) + src_nents++; + + src = kmalloc_array(src_nents, sizeof(struct scatterlist), GFP_ATOMIC); + if (!src) { + err = -ENOMEM; + goto dthe_aead_prep_src_mem_err; + } + + sg_init_table(src, src_nents); + to_sg = src; + + to_sg = dthe_copy_sg(to_sg, in_sg[0], assoclen); + if (assoclen % AES_BLOCK_SIZE) { + unsigned int pad_len = AES_BLOCK_SIZE - (assoclen % AES_BLOCK_SIZE); + + sg_set_buf(to_sg, assoc_pad_buf, pad_len); + to_sg = sg_next(to_sg); + } + + to_sg = dthe_copy_sg(to_sg, in_sg[1], cryptlen); + if (cryptlen % AES_BLOCK_SIZE) { + unsigned int pad_len = AES_BLOCK_SIZE - (cryptlen % AES_BLOCK_SIZE); + + sg_set_buf(to_sg, crypt_pad_buf, pad_len); + to_sg = sg_next(to_sg); + } + +dthe_aead_prep_src_mem_err: + if (cryptlen != 0 && assoclen != 0) { + kfree(in_sg[0]); + kfree(in_sg[1]); + } + +dthe_aead_prep_src_split_err: + if (err) + return ERR_PTR(err); + return src; +} + +/** + * dthe_aead_prep_dst - Prepare destination scatterlist for AEAD from input req->dst + * @sg: Input req->dst scatterlist + * @assoclen: Input req->assoclen + * @cryptlen: Input req->cryptlen (minus size of TAG in decryption) + * @pad_buf: Buffer to hold ciphertext/plaintext padding if needed + * + * Description: + * For modes with authentication, DTHEv2 hardware returns encrypted ciphertext/decrypted + * plaintext through DMA and TAG through MMRs. However, the dst scatterlist in linux + * crypto's aead_request is allocated same as input req->src scatterlist. That is, it + * contains space for AAD in the beginning and ciphertext/plaintext at the end, with no + * alignment padding. This causes issues with DMA engine and DTHEv2 hardware. + * + * This helper function takes the output scatterlist and maps the part of the buffer + * which holds only the ciphertext/plaintext to a new scatterlist. It also adds a padding + * to align it with AES_BLOCK_SIZE. + * + * Return: + * Pointer to the trimmed scatterlist, or ERR_PTR(error) on failure. + * The calling function needs to free the returned scatterlist when done. + **/ +static struct scatterlist *dthe_aead_prep_dst(struct scatterlist *sg, + unsigned int assoclen, + unsigned int cryptlen, + u8 *pad_buf) +{ + struct scatterlist *out_sg[1]; + struct scatterlist *dst; + struct scatterlist *to_sg; + size_t split_sizes[1] = {cryptlen}; + int out_mapped_nents[1]; + int dst_nents = 0; + int err = 0; + + err = sg_split(sg, 0, assoclen, 1, split_sizes, out_sg, out_mapped_nents, GFP_ATOMIC); + if (err) + goto dthe_aead_prep_dst_split_err; + + dst_nents = sg_nents_for_len(out_sg[0], cryptlen); + if (cryptlen % AES_BLOCK_SIZE) + dst_nents++; + + dst = kmalloc_array(dst_nents, sizeof(struct scatterlist), GFP_ATOMIC); + if (!dst) { + err = -ENOMEM; + goto dthe_aead_prep_dst_mem_err; + } + sg_init_table(dst, dst_nents); + + to_sg = dthe_copy_sg(dst, out_sg[0], cryptlen); + if (cryptlen % AES_BLOCK_SIZE) { + unsigned int pad_len = AES_BLOCK_SIZE - (cryptlen % AES_BLOCK_SIZE); + + sg_set_buf(to_sg, pad_buf, pad_len); + to_sg = sg_next(to_sg); + } + +dthe_aead_prep_dst_mem_err: + kfree(out_sg[0]); + +dthe_aead_prep_dst_split_err: + if (err) + return ERR_PTR(err); + return dst; +} + +static int dthe_aead_read_tag(struct dthe_tfm_ctx *ctx, u32 *tag) +{ + struct dthe_data *dev_data = dthe_get_dev(ctx); + void __iomem *aes_base_reg = dev_data->regs + DTHE_P_AES_BASE; + u32 val; + int ret; + + ret = readl_relaxed_poll_timeout(aes_base_reg + DTHE_P_AES_CTRL, val, + (val & DTHE_AES_CTRL_SAVED_CTX_READY), + 0, POLL_TIMEOUT_INTERVAL); + if (ret) + return ret; + + for (int i = 0; i < AES_BLOCK_WORDS; ++i) + tag[i] = readl_relaxed(aes_base_reg + + DTHE_P_AES_TAG_OUT + + DTHE_REG_SIZE * i); + return 0; +} + +static int dthe_gcm_aes_enc_get_tag(struct aead_request *req) +{ + struct dthe_tfm_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req)); + u32 tag[AES_BLOCK_WORDS]; + int nents; + int ret; + + ret = dthe_aead_read_tag(ctx, tag); + if (ret) + return ret; + + nents = sg_nents_for_len(req->dst, req->cryptlen + req->assoclen + ctx->authsize); + + sg_pcopy_from_buffer(req->dst, nents, tag, ctx->authsize, + req->assoclen + req->cryptlen); + + return 0; +} + +static int dthe_gcm_aes_dec_verify_tag(struct aead_request *req) +{ + struct dthe_tfm_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req)); + u32 tag_out[AES_BLOCK_WORDS]; + u32 tag_in[AES_BLOCK_WORDS]; + int nents; + int ret; + + ret = dthe_aead_read_tag(ctx, tag_out); + if (ret) + return ret; + + nents = sg_nents_for_len(req->src, req->assoclen + req->cryptlen); + + sg_pcopy_to_buffer(req->src, nents, tag_in, ctx->authsize, + req->assoclen + req->cryptlen - ctx->authsize); + + if (memcmp(tag_in, tag_out, ctx->authsize)) + return -EBADMSG; + else + return 0; +} + +static int dthe_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) +{ + struct dthe_tfm_ctx *ctx = crypto_aead_ctx(tfm); + + if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && keylen != AES_KEYSIZE_256) + return -EINVAL; + + crypto_sync_aead_clear_flags(ctx->aead_fb, CRYPTO_TFM_REQ_MASK); + crypto_sync_aead_set_flags(ctx->aead_fb, + crypto_aead_get_flags(tfm) & + CRYPTO_TFM_REQ_MASK); + + return crypto_sync_aead_setkey(ctx->aead_fb, key, keylen); +} + +static int dthe_gcm_aes_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) +{ + struct dthe_tfm_ctx *ctx = crypto_aead_ctx(tfm); + + ctx->aes_mode = DTHE_AES_GCM; + ctx->keylen = keylen; + memcpy(ctx->key, key, keylen); + + return dthe_aead_setkey(tfm, key, keylen); +} + +static int dthe_ccm_aes_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) +{ + struct dthe_tfm_ctx *ctx = crypto_aead_ctx(tfm); + + ctx->aes_mode = DTHE_AES_CCM; + ctx->keylen = keylen; + memcpy(ctx->key, key, keylen); + + return dthe_aead_setkey(tfm, key, keylen); +} + +static int dthe_aead_setauthsize(struct crypto_aead *tfm, unsigned int authsize) +{ + struct dthe_tfm_ctx *ctx = crypto_aead_ctx(tfm); + + /* Invalid auth size will be handled by crypto_aead_setauthsize() */ + ctx->authsize = authsize; + + return crypto_sync_aead_setauthsize(ctx->aead_fb, authsize); +} + +static int dthe_aead_do_fallback(struct aead_request *req) +{ + struct dthe_tfm_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req)); + struct dthe_aes_req_ctx *rctx = aead_request_ctx(req); + + SYNC_AEAD_REQUEST_ON_STACK(subreq, ctx->aead_fb); + + aead_request_set_callback(subreq, req->base.flags, + req->base.complete, req->base.data); + aead_request_set_crypt(subreq, req->src, req->dst, req->cryptlen, req->iv); + aead_request_set_ad(subreq, req->assoclen); + + return rctx->enc ? crypto_aead_encrypt(subreq) : + crypto_aead_decrypt(subreq); +} + +static void dthe_aead_dma_in_callback(void *data) +{ + struct aead_request *req = (struct aead_request *)data; + struct dthe_aes_req_ctx *rctx = aead_request_ctx(req); + + complete(&rctx->aes_compl); +} + +static int dthe_aead_run(struct crypto_engine *engine, void *areq) +{ + struct aead_request *req = container_of(areq, struct aead_request, base); + struct dthe_tfm_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req)); + struct dthe_aes_req_ctx *rctx = aead_request_ctx(req); + struct dthe_data *dev_data = dthe_get_dev(ctx); + + unsigned int cryptlen = req->cryptlen; + unsigned int assoclen = req->assoclen; + unsigned int authsize = ctx->authsize; + unsigned int unpadded_cryptlen; + struct scatterlist *src = req->src; + struct scatterlist *dst = req->dst; + u32 iv_in[AES_BLOCK_SIZE / sizeof(u32)]; + + int src_nents; + int dst_nents; + int src_mapped_nents, dst_mapped_nents; + + u8 *src_assoc_padbuf = rctx->padding; + u8 *src_crypt_padbuf = rctx->padding + AES_BLOCK_SIZE; + u8 *dst_crypt_padbuf = rctx->padding + (2 * AES_BLOCK_SIZE); + + enum dma_data_direction src_dir, dst_dir; + + struct device *tx_dev, *rx_dev; + struct dma_async_tx_descriptor *desc_in, *desc_out; + + int ret; + + void __iomem *aes_base_reg = dev_data->regs + DTHE_P_AES_BASE; + + u32 aes_sysconfig_val = readl_relaxed(aes_base_reg + DTHE_P_AES_SYSCONFIG); + + aes_sysconfig_val |= DTHE_AES_SYSCONFIG_DMA_DATA_IN_OUT_EN; + writel_relaxed(aes_sysconfig_val, aes_base_reg + DTHE_P_AES_SYSCONFIG); + + /* In decryption, the last authsize bytes are the TAG */ + if (!rctx->enc) + cryptlen -= authsize; + unpadded_cryptlen = cryptlen; + + // Prep src and dst scatterlists + memset(src_assoc_padbuf, 0, AES_BLOCK_SIZE); + memset(src_crypt_padbuf, 0, AES_BLOCK_SIZE); + memset(dst_crypt_padbuf, 0, AES_BLOCK_SIZE); + + src = dthe_aead_prep_src(req->src, req->assoclen, cryptlen, + src_assoc_padbuf, src_crypt_padbuf); + if (IS_ERR(src)) { + ret = PTR_ERR(src); + goto aead_err; + } + + if (req->assoclen % AES_BLOCK_SIZE) + assoclen += AES_BLOCK_SIZE - (req->assoclen % AES_BLOCK_SIZE); + if (cryptlen % AES_BLOCK_SIZE) + cryptlen += AES_BLOCK_SIZE - (cryptlen % AES_BLOCK_SIZE); + + src_nents = sg_nents_for_len(src, assoclen + cryptlen); + + if (cryptlen != 0) { + dst = dthe_aead_prep_dst(req->dst, req->assoclen, unpadded_cryptlen, + dst_crypt_padbuf); + if (IS_ERR(dst)) { + ret = PTR_ERR(dst); + goto aead_prep_dst_err; + } + + dst_nents = sg_nents_for_len(dst, cryptlen); + } + // Prep finished + + src_dir = DMA_TO_DEVICE; + dst_dir = DMA_FROM_DEVICE; + + tx_dev = dmaengine_get_dma_device(dev_data->dma_aes_tx); + rx_dev = dmaengine_get_dma_device(dev_data->dma_aes_rx); + + // HACK: Delay to workaround DMA driver issue + cnt++; + if (cnt % 20 == 0) { + unsigned long delay = jiffies + usecs_to_jiffies(1000); + + while (time_before(jiffies, delay)) + cond_resched(); + cnt = 0; + } + + src_mapped_nents = dma_map_sg(tx_dev, src, src_nents, src_dir); + if (src_mapped_nents == 0) { + ret = -EINVAL; + goto aead_dma_map_src_err; + } + + desc_out = dmaengine_prep_slave_sg(dev_data->dma_aes_tx, src, src_mapped_nents, + DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + if (!desc_out) { + ret = -EINVAL; + goto aead_dma_prep_src_err; + } + + desc_out->callback = dthe_aead_dma_in_callback; + desc_out->callback_param = req; + + if (cryptlen != 0) { + dst_mapped_nents = dma_map_sg(rx_dev, dst, dst_nents, dst_dir); + if (dst_mapped_nents == 0) { + ret = -EINVAL; + goto aead_dma_prep_src_err; + } + + desc_in = dmaengine_prep_slave_sg(dev_data->dma_aes_rx, dst, + dst_mapped_nents, DMA_DEV_TO_MEM, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + if (!desc_in) { + ret = -EINVAL; + goto aead_dma_prep_dst_err; + } + } + + init_completion(&rctx->aes_compl); + + /* + * HACK: There is an unknown hw issue where if the previous operation had alen = 0 and + * plen != 0, the current operation's tag calculation is incorrect in the case where + * plen = 0 and alen != 0 currently. This is a workaround for now which somwhow works; + * by resetting the context by writing a 1 to the C_LENGTH_0 and AUTH_LENGTH registers. + */ + if (cryptlen == 0) { + writel_relaxed(1, aes_base_reg + DTHE_P_AES_C_LENGTH_0); + writel_relaxed(1, aes_base_reg + DTHE_P_AES_AUTH_LENGTH); + } + + if (ctx->aes_mode == DTHE_AES_GCM) { + if (req->iv) { + memcpy(iv_in, req->iv, GCM_AES_IV_SIZE); + } else { + iv_in[0] = 0; + iv_in[1] = 0; + iv_in[2] = 0; + } + iv_in[3] = 0x01000000; + } else { + memcpy(iv_in, req->iv, AES_IV_SIZE); + } + + // Clear key2 to reset previous GHASH intermediate data + for (int i = 0; i < AES_KEYSIZE_256 / sizeof(u32); ++i) + writel_relaxed(0, aes_base_reg + DTHE_REG_SIZE * i); + + dthe_aes_set_ctrl_key(ctx, rctx, iv_in); + + writel_relaxed(lower_32_bits(unpadded_cryptlen), aes_base_reg + DTHE_P_AES_C_LENGTH_0); + writel_relaxed(upper_32_bits(unpadded_cryptlen), aes_base_reg + DTHE_P_AES_C_LENGTH_1); + writel_relaxed(req->assoclen, aes_base_reg + DTHE_P_AES_AUTH_LENGTH); + + if (cryptlen != 0) + dmaengine_submit(desc_in); + dmaengine_submit(desc_out); + + if (cryptlen != 0) + dma_async_issue_pending(dev_data->dma_aes_rx); + dma_async_issue_pending(dev_data->dma_aes_tx); + + // Need to do a timeout to ensure mutex gets unlocked if DMA callback fails for any reason + ret = wait_for_completion_timeout(&rctx->aes_compl, msecs_to_jiffies(DTHE_DMA_TIMEOUT_MS)); + if (!ret) { + ret = -ETIMEDOUT; + if (cryptlen != 0) + dmaengine_terminate_sync(dev_data->dma_aes_rx); + dmaengine_terminate_sync(dev_data->dma_aes_tx); + + for (int i = 0; i < AES_BLOCK_SIZE / sizeof(int); ++i) + readl_relaxed(aes_base_reg + DTHE_P_AES_DATA_IN_OUT + DTHE_REG_SIZE * i); + } else { + ret = 0; + } + + if (cryptlen != 0) + dma_sync_sg_for_cpu(rx_dev, dst, dst_nents, dst_dir); + if (rctx->enc) + ret = dthe_gcm_aes_enc_get_tag(req); + else + ret = dthe_gcm_aes_dec_verify_tag(req); + +aead_dma_prep_dst_err: + if (cryptlen != 0) + dma_unmap_sg(rx_dev, dst, dst_nents, dst_dir); +aead_dma_prep_src_err: + dma_unmap_sg(tx_dev, src, src_nents, src_dir); + +aead_dma_map_src_err: + if (cryptlen != 0) + kfree(dst); + +aead_prep_dst_err: + kfree(src); + +aead_err: + if (ret) + ret = dthe_aead_do_fallback(req); + local_bh_disable(); + crypto_finalize_aead_request(dev_data->aes_engine, req, ret); + local_bh_enable(); + return 0; +} + +static int dthe_aead_crypt(struct aead_request *req) +{ + struct dthe_tfm_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req)); + struct dthe_aes_req_ctx *rctx = aead_request_ctx(req); + struct dthe_data *dev_data = dthe_get_dev(ctx); + struct crypto_engine *engine; + unsigned int cryptlen = req->cryptlen; + bool is_zero_ctr = true; + + /* In decryption, last authsize bytes are the TAG */ + if (!rctx->enc) + cryptlen -= ctx->authsize; + + if (ctx->aes_mode == DTHE_AES_CCM) { + /* + * For CCM Mode, the 128-bit IV contains the following: + * | 0 .. 2 | 3 .. 7 | 8 .. (127-8*L) | (128-8*L) .. 127 | + * | L-1 | Zero | Nonce | Counter | + * L needs to be between 2-8 (inclusive), i.e. 1 <= (L-1) <= 7 + * and the next 5 bits need to be zeroes. Else return -EINVAL + */ + u8 *iv = req->iv; + u8 L = iv[0]; + + if (L < 1 || L > 7) + return -EINVAL; + /* + * DTHEv2 HW can only work with zero initial counter in CCM mode. + * Check if the initial counter value is zero or not + */ + for (int i = 0; i < L + 1; ++i) { + if (iv[AES_IV_SIZE - 1 - i] != 0) { + is_zero_ctr = false; + break; + } + } + } + + /* + * Need to fallback to software in the following cases due to HW restrictions: + * - Both AAD and plaintext/ciphertext are zero length + * - For AES-GCM, AAD length is more than 2^32 - 1 bytes + * - For AES-CCM, AAD length is more than 2^16 - 2^8 bytes + * - For AES-CCM, plaintext/ciphertext length is more than 2^61 - 1 bytes + * - For AES-CCM, AAD length is non-zero but plaintext/ciphertext length is zero + * - For AES-CCM, the initial counter (last L+1 bytes of IV) is not all zeroes + * + * PS: req->cryptlen is currently unsigned int type, which causes the second and fourth + * cases above tautologically false. If req->cryptlen is to be changed to a 64-bit + * type, the check for these would also need to be added below. + */ + if ((req->assoclen == 0 && cryptlen == 0) || + (ctx->aes_mode == DTHE_AES_CCM && req->assoclen > DTHE_AES_CCM_AAD_MAXLEN) || + (ctx->aes_mode == DTHE_AES_CCM && cryptlen == 0) || + (ctx->aes_mode == DTHE_AES_CCM && !is_zero_ctr)) + return dthe_aead_do_fallback(req); + + engine = dev_data->aes_engine; + return crypto_transfer_aead_request_to_engine(engine, req); +} + +static int dthe_aead_encrypt(struct aead_request *req) +{ + struct dthe_aes_req_ctx *rctx = aead_request_ctx(req); + + rctx->enc = 1; + return dthe_aead_crypt(req); +} + +static int dthe_aead_decrypt(struct aead_request *req) +{ + struct dthe_aes_req_ctx *rctx = aead_request_ctx(req); + + rctx->enc = 0; + return dthe_aead_crypt(req); +} + +static struct skcipher_engine_alg cipher_algs[] = { + { + .base.init = dthe_cipher_init_tfm, + .base.setkey = dthe_aes_ecb_setkey, + .base.encrypt = dthe_aes_encrypt, + .base.decrypt = dthe_aes_decrypt, + .base.min_keysize = AES_MIN_KEY_SIZE, + .base.max_keysize = AES_MAX_KEY_SIZE, + .base.base = { + .cra_name = "ecb(aes)", + .cra_driver_name = "ecb-aes-dthev2", + .cra_priority = 30000, + .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER | + CRYPTO_ALG_KERN_DRIVER_ONLY, + .cra_alignmask = AES_BLOCK_SIZE - 1, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_module = THIS_MODULE, + }, + .op.do_one_request = dthe_aes_run, + }, /* ECB AES */ + { + .base.init = dthe_cipher_init_tfm, + .base.setkey = dthe_aes_cbc_setkey, + .base.encrypt = dthe_aes_encrypt, + .base.decrypt = dthe_aes_decrypt, + .base.min_keysize = AES_MIN_KEY_SIZE, + .base.max_keysize = AES_MAX_KEY_SIZE, + .base.ivsize = AES_IV_SIZE, + .base.base = { + .cra_name = "cbc(aes)", + .cra_driver_name = "cbc-aes-dthev2", + .cra_priority = 30000, + .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER | + CRYPTO_ALG_KERN_DRIVER_ONLY, + .cra_alignmask = AES_BLOCK_SIZE - 1, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_module = THIS_MODULE, + }, + .op.do_one_request = dthe_aes_run, + }, /* CBC AES */ + { + .base.init = dthe_cipher_init_tfm, + .base.setkey = dthe_aes_ctr_setkey, + .base.encrypt = dthe_aes_encrypt, + .base.decrypt = dthe_aes_decrypt, + .base.min_keysize = AES_MIN_KEY_SIZE, + .base.max_keysize = AES_MAX_KEY_SIZE, + .base.ivsize = AES_IV_SIZE, + .base.base = { + .cra_name = "ctr(aes)", + .cra_driver_name = "ctr-aes-dthev2", + .cra_priority = 30000, + .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY, + .cra_blocksize = 1, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_module = THIS_MODULE, + }, + .op.do_one_request = dthe_aes_run, + }, /* CTR AES */ + { + .base.init = dthe_cipher_xts_init_tfm, + .base.exit = dthe_cipher_xts_exit_tfm, + .base.setkey = dthe_aes_xts_setkey, + .base.encrypt = dthe_aes_encrypt, + .base.decrypt = dthe_aes_decrypt, + .base.min_keysize = AES_MIN_KEY_SIZE * 2, + .base.max_keysize = AES_MAX_KEY_SIZE * 2, + .base.ivsize = AES_IV_SIZE, + .base.base = { + .cra_name = "xts(aes)", + .cra_driver_name = "xts-aes-dthev2", + .cra_priority = 30000, + .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_NEED_FALLBACK, + .cra_alignmask = AES_BLOCK_SIZE - 1, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_module = THIS_MODULE, + }, + .op.do_one_request = dthe_aes_run, + }, /* XTS AES */ +}; + +static struct aead_engine_alg aead_algs[] = { + { + .base.init = dthe_aead_init_tfm, + .base.exit = dthe_aead_exit_tfm, + .base.setkey = dthe_gcm_aes_setkey, + .base.setauthsize = dthe_aead_setauthsize, + .base.maxauthsize = AES_BLOCK_SIZE, + .base.encrypt = dthe_aead_encrypt, + .base.decrypt = dthe_aead_decrypt, + .base.chunksize = AES_BLOCK_SIZE, + .base.ivsize = GCM_AES_IV_SIZE, + .base.base = { + .cra_name = "gcm(aes)", + .cra_driver_name = "gcm-aes-dthev2", + .cra_priority = 3000, + .cra_flags = CRYPTO_ALG_TYPE_AEAD | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize = 1, + .cra_module = THIS_MODULE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + }, + .op.do_one_request = dthe_aead_run, + }, /* GCM AES */ + { + .base.init = dthe_aead_init_tfm, + .base.exit = dthe_aead_exit_tfm, + .base.setkey = dthe_ccm_aes_setkey, + .base.setauthsize = dthe_aead_setauthsize, + .base.maxauthsize = AES_BLOCK_SIZE, + .base.encrypt = dthe_aead_encrypt, + .base.decrypt = dthe_aead_decrypt, + .base.chunksize = AES_BLOCK_SIZE, + .base.ivsize = AES_IV_SIZE, + .base.base = { + .cra_name = "ccm(aes)", + .cra_driver_name = "ccm-aes-dthev2", + .cra_priority = 3000, + .cra_flags = CRYPTO_ALG_TYPE_AEAD | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize = 1, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_module = THIS_MODULE, + }, + .op.do_one_request = dthe_aead_run, + }, /* CCM AES */ +}; + +int dthe_register_aes_algs(void) +{ + int ret = 0; + + ret |= crypto_engine_register_skciphers(cipher_algs, ARRAY_SIZE(cipher_algs)); + ret |= crypto_engine_register_aeads(aead_algs, ARRAY_SIZE(aead_algs)); + + return ret; +} + +void dthe_unregister_aes_algs(void) +{ + crypto_engine_unregister_skciphers(cipher_algs, ARRAY_SIZE(cipher_algs)); + crypto_engine_unregister_aeads(aead_algs, ARRAY_SIZE(aead_algs)); +} diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/crypto/ti/dthev2-common.c v_kernel/drivers/crypto/ti/dthev2-common.c --- linux-6.12.57/drivers/crypto/ti/dthev2-common.c 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/crypto/ti/dthev2-common.c 2026-04-21 11:35:35.894934549 +0200 @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * K3 DTHE V2 crypto accelerator driver + * + * Copyright (C) Texas Instruments 2025 - https://www.ti.com + * Author: T Pratham + */ + +#include +#include +#include +#include +#include + +#include "dthev2-common.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "dthev2" + +static struct dthe_list dthe_dev_list = { + .dev_list = LIST_HEAD_INIT(dthe_dev_list.dev_list), + .lock = __SPIN_LOCK_UNLOCKED(dthe_dev_list.lock), +}; + +struct dthe_data *dthe_get_dev(struct dthe_tfm_ctx *ctx) +{ + struct dthe_data *dev_data; + + if (ctx->dev_data) + return ctx->dev_data; + + spin_lock_bh(&dthe_dev_list.lock); + dev_data = list_first_entry(&dthe_dev_list.dev_list, struct dthe_data, list); + if (dev_data) + list_move_tail(&dev_data->list, &dthe_dev_list.dev_list); + spin_unlock_bh(&dthe_dev_list.lock); + + return dev_data; +} + +struct scatterlist *dthe_copy_sg(struct scatterlist *dst, + struct scatterlist *src, + int buflen) +{ + struct scatterlist *from_sg, *to_sg; + int sglen; + + for (to_sg = dst, from_sg = src; buflen && from_sg; buflen -= sglen) { + sglen = from_sg->length; + if (sglen > buflen) + sglen = buflen; + sg_set_buf(to_sg, sg_virt(from_sg), sglen); + from_sg = sg_next(from_sg); + to_sg = sg_next(to_sg); + } + + return to_sg; +} + +static int dthe_dma_init(struct dthe_data *dev_data) +{ + int ret; + struct dma_slave_config cfg; + + dev_data->dma_aes_rx = NULL; + dev_data->dma_aes_tx = NULL; + dev_data->dma_sha_tx = NULL; + + dev_data->dma_aes_rx = dma_request_chan(dev_data->dev, "rx"); + if (IS_ERR(dev_data->dma_aes_rx)) { + return dev_err_probe(dev_data->dev, PTR_ERR(dev_data->dma_aes_rx), + "Unable to request rx DMA channel\n"); + } + + dev_data->dma_aes_tx = dma_request_chan(dev_data->dev, "tx1"); + if (IS_ERR(dev_data->dma_aes_tx)) { + ret = dev_err_probe(dev_data->dev, PTR_ERR(dev_data->dma_aes_tx), + "Unable to request tx1 DMA channel\n"); + goto err_dma_aes_tx; + } + + dev_data->dma_sha_tx = dma_request_chan(dev_data->dev, "tx2"); + if (IS_ERR(dev_data->dma_sha_tx)) { + ret = dev_err_probe(dev_data->dev, PTR_ERR(dev_data->dma_sha_tx), + "Unable to request tx2 DMA channel\n"); + goto err_dma_sha_tx; + } + + // Do AES Rx and Tx channel config here because it is invariant of AES mode + // SHA Tx channel config is done before DMA transfer depending on hashing algorithm + + memzero_explicit(&cfg, sizeof(cfg)); + + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.src_maxburst = 4; + + ret = dmaengine_slave_config(dev_data->dma_aes_rx, &cfg); + if (ret) { + dev_err(dev_data->dev, "Can't configure IN dmaengine slave: %d\n", ret); + goto err_dma_config; + } + + cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.dst_maxburst = 4; + + ret = dmaengine_slave_config(dev_data->dma_aes_tx, &cfg); + if (ret) { + dev_err(dev_data->dev, "Can't configure OUT dmaengine slave: %d\n", ret); + goto err_dma_config; + } + + return 0; + +err_dma_config: + dma_release_channel(dev_data->dma_sha_tx); +err_dma_sha_tx: + dma_release_channel(dev_data->dma_aes_tx); +err_dma_aes_tx: + dma_release_channel(dev_data->dma_aes_rx); + + return ret; +} + +static int dthe_register_algs(void) +{ + int ret = 0; + + ret |= dthe_register_hash_algs(); + ret |= dthe_register_aes_algs(); + + return ret; +} + +static void dthe_unregister_algs(void) +{ + dthe_unregister_hash_algs(); + dthe_unregister_aes_algs(); +} + +static int dthe_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dthe_data *dev_data; + int ret; + + dev_data = devm_kzalloc(dev, sizeof(*dev_data), GFP_KERNEL); + if (!dev_data) + return -ENOMEM; + + dev_data->dev = dev; + dev_data->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dev_data->regs)) + return PTR_ERR(dev_data->regs); + + platform_set_drvdata(pdev, dev_data); + + spin_lock(&dthe_dev_list.lock); + list_add(&dev_data->list, &dthe_dev_list.dev_list); + spin_unlock(&dthe_dev_list.lock); + mutex_init(&dev_data->hash_mutex); + + ret = dthe_dma_init(dev_data); + if (ret) + goto probe_dma_err; + + dev_data->aes_engine = crypto_engine_alloc_init(dev, 1); + if (!dev_data->aes_engine) { + ret = -ENOMEM; + goto probe_aes_engine_init_err; + } + + ret = crypto_engine_start(dev_data->aes_engine); + if (ret) { + dev_err(dev, "Failed to start aes crypto engine\n"); + goto probe_aes_engine_start_err; + } + + ret = dthe_register_algs(); + if (ret) { + dev_err(dev, "Failed to register algs\n"); + goto probe_aes_engine_start_err; + } + + return 0; + +probe_aes_engine_start_err: + crypto_engine_exit(dev_data->aes_engine); +probe_aes_engine_init_err: + dma_release_channel(dev_data->dma_aes_rx); + dma_release_channel(dev_data->dma_aes_tx); + dma_release_channel(dev_data->dma_sha_tx); +probe_dma_err: + spin_lock(&dthe_dev_list.lock); + list_del(&dev_data->list); + spin_unlock(&dthe_dev_list.lock); + mutex_destroy(&dev_data->hash_mutex); + + return ret; +} + +static void dthe_remove(struct platform_device *pdev) +{ + struct dthe_data *dev_data = platform_get_drvdata(pdev); + + spin_lock(&dthe_dev_list.lock); + list_del(&dev_data->list); + spin_unlock(&dthe_dev_list.lock); + mutex_destroy(&dev_data->hash_mutex); + + dthe_unregister_algs(); + + crypto_engine_exit(dev_data->aes_engine); + + dma_release_channel(dev_data->dma_aes_rx); + dma_release_channel(dev_data->dma_aes_tx); + dma_release_channel(dev_data->dma_sha_tx); +} + +static const struct of_device_id dthe_of_match[] = { + { .compatible = "ti,am62l-dthev2", }, + {}, +}; +MODULE_DEVICE_TABLE(of, dthe_of_match); + +static struct platform_driver dthe_driver = { + .probe = dthe_probe, + .remove = dthe_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = dthe_of_match, + }, +}; + +module_platform_driver(dthe_driver); + +MODULE_AUTHOR("T Pratham "); +MODULE_DESCRIPTION("Texas Instruments DTHE V2 driver"); +MODULE_LICENSE("GPL"); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/crypto/ti/dthev2-common.h v_kernel/drivers/crypto/ti/dthev2-common.h --- linux-6.12.57/drivers/crypto/ti/dthev2-common.h 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/crypto/ti/dthev2-common.h 2026-04-21 11:35:35.895934552 +0200 @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * K3 DTHE V2 crypto accelerator driver + * + * Copyright (C) Texas Instruments 2025 - https://www.ti.com + * Author: T Pratham + */ + +#ifndef __TI_DTHEV2_H__ +#define __TI_DTHEV2_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define DTHE_REG_SIZE 4 +#define DTHE_DMA_TIMEOUT_MS 2000 +/* + * Size of largest possible key (of all algorithms) to be stored in dthe_tfm_ctx + * This is currently the keysize of HMAC-SHA512 + */ +#define DTHE_MAX_KEYSIZE (SHA512_BLOCK_SIZE) +#define DTHE_MAX_PADSIZE (AES_BLOCK_SIZE * 3) + +enum dthe_hash_alg_sel { + DTHE_HASH_MD5 = 0, + DTHE_HASH_SHA1 = BIT(1), + DTHE_HASH_SHA224 = BIT(2), + DTHE_HASH_SHA256 = BIT(1) | BIT(2), + DTHE_HASH_SHA384 = BIT(0), + DTHE_HASH_SHA512 = BIT(0) | BIT(1) +}; + +enum dthe_aes_mode { + DTHE_AES_ECB = 0, + DTHE_AES_CBC, + DTHE_AES_CTR, + DTHE_AES_XTS, + DTHE_AES_GCM, + DTHE_AES_CCM, +}; + +/* Driver specific struct definitions */ + +/** + * struct dthe_data - DTHE_V2 driver instance data + * @dev: Device pointer + * @regs: Base address of the register space + * @list: list node for dev + * @aes_engine: Crypto engine instance for AES Engine + * @dma_aes_rx: AES Rx DMA Channel + * @dma_aes_tx: AES Tx DMA Channel + * @dma_sha_tx: SHA Tx DMA Channel + * @hash_mutex: Mutex protecting access to HASH engine + */ +struct dthe_data { + struct device *dev; + void __iomem *regs; + struct list_head list; + struct crypto_engine *aes_engine; + + struct dma_chan *dma_aes_rx; + struct dma_chan *dma_aes_tx; + + struct dma_chan *dma_sha_tx; + struct mutex hash_mutex; +}; + +/** + * struct dthe_list - device data list head + * @dev_list: linked list head + * @lock: Spinlock protecting accesses to the list + */ +struct dthe_list { + struct list_head dev_list; + spinlock_t lock; +}; + +/** + * struct dthe_tfm_ctx - Transform ctx struct containing ctx for all sub-components of DTHE V2 + * @dev_data: Device data struct pointer + * @keylen: Key length for algorithms that require a key + * @authsize: Authentication size for modes with authentication + * @key: Key + * @aes_mode: AES mode + * @hash_mode: Hashing Engine mode + * @block_size: block size of hash algorithm selected + * @digest_size: digest size of hash algorithm selected + * @phash_size: partial hash size of the hash algorithm selected + * @fallback: Fallback crypto aead handle + * @ahash_fb: Fallback crypto ahash instance for hashing algorithms + * @skcipher_fb: Fallback crypto skcipher handle for AES-XTS mode + */ +struct dthe_tfm_ctx { + struct dthe_data *dev_data; + unsigned int keylen; + unsigned int authsize; + u32 key[DTHE_MAX_KEYSIZE / sizeof(u32)]; + union { + enum dthe_aes_mode aes_mode; + enum dthe_hash_alg_sel hash_mode; + }; + u32 block_size; + u32 digest_size; + u32 phash_size; + union { + struct crypto_sync_aead *aead_fb; + struct crypto_ahash *ahash_fb; + struct crypto_sync_skcipher *skcipher_fb; + }; +}; + +/** + * struct dthe_aes_req_ctx - AES engine req ctx struct + * @enc: flag indicating encryption or decryption operation + * @padding: padding buffer for handling unaligned data + * @aes_compl: Completion variable for use in manual completion in case of DMA callback failure + */ +struct dthe_aes_req_ctx { + int enc; + u8 padding[DTHE_MAX_PADSIZE]; + struct completion aes_compl; +}; + +/** + * struct dthe_hash_req_ctx - Hashing engine req ctx struct + * @phash: buffer to store a partial hash/inner digest from a previous operation + * @odigest: buffer to store the outer digest from a previous operation + * @data_buf: buffer to store part of input data to be carried over to next operation + * @padding: padding buffer for handling unaligned data + * @digestcnt: stores the digest count from a previous operation + * @phash_available: flag indicating if a partial hash from a previous operation is available + * @buflen: length of input data stored in data_buf + * @flags: flags for internal use + * @hash_compl: Completion variable for use in manual completion in case of DMA callback failure + */ +struct dthe_hash_req_ctx { + u32 phash[SHA512_DIGEST_SIZE / sizeof(u32)]; + u32 odigest[SHA512_DIGEST_SIZE / sizeof(u32)]; + u8 data_buf[SHA512_BLOCK_SIZE]; + u8 padding[SHA512_BLOCK_SIZE]; + u32 digestcnt; + u8 phash_available; + u8 buflen; + u8 flags; + struct completion hash_compl; +}; + +/* Struct definitions end */ + +struct dthe_data *dthe_get_dev(struct dthe_tfm_ctx *ctx); + +/** + * dthe_copy_sg - Copy sg entries from src to dst + * @dst: Destination sg to be filled + * @src: Source sg to be copied from + * @buflen: Number of bytes to be copied + * + * Description: + * Copy buflen bytes of data from src to dst. + * + **/ +struct scatterlist *dthe_copy_sg(struct scatterlist *dst, + struct scatterlist *src, + int buflen); + +int dthe_register_aes_algs(void); +void dthe_unregister_aes_algs(void); + +int dthe_register_hash_algs(void); +void dthe_unregister_hash_algs(void); + +#endif diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/crypto/ti/dthev2-hash.c v_kernel/drivers/crypto/ti/dthev2-hash.c --- linux-6.12.57/drivers/crypto/ti/dthev2-hash.c 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/crypto/ti/dthev2-hash.c 2026-04-21 11:35:35.895934552 +0200 @@ -0,0 +1,1372 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * K3 DTHE V2 crypto accelerator driver + * + * Copyright (C) Texas Instruments 2025 - https://www.ti.com + * Author: T Pratham + */ + +#include +#include +#include +#include +#include + +#include "dthev2-common.h" + +#include +#include +#include +#include +#include + +/* Registers */ + +// Hashing Engine +#define DTHE_P_HASH_BASE 0x5000 +#define DTHE_P_HASH512_ODIGEST_A 0x0200 +#define DTHE_P_HASH512_IDIGEST_A 0x0240 +#define DTHE_P_HASH512_DIGEST_COUNT 0x0280 +#define DTHE_P_HASH512_MODE 0x0284 +#define DTHE_P_HASH512_LENGTH 0x0288 +#define DTHE_P_HASH512_DATA_IN_START 0x0080 +#define DTHE_P_HASH512_DATA_IN_END 0x00FC + +#define DTHE_P_HASH_SYSCONFIG 0x0110 +#define DTHE_P_HASH_IRQSTATUS 0x0118 +#define DTHE_P_HASH_IRQENABLE 0x011C + +/* Register write values and macros */ +#define DTHE_HASH_SYSCONFIG_INT_EN BIT(2) +#define DTHE_HASH_SYSCONFIG_DMA_EN BIT(3) +#define DTHE_HASH_IRQENABLE_EN_ALL GENMASK(3, 0) +#define DTHE_HASH_IRQSTATUS_OP_READY BIT(0) +#define DTHE_HASH_IRQSTATUS_IP_READY BIT(1) +#define DTHE_HASH_IRQSTATUS_PH_READY BIT(2) +#define DTHE_HASH_IRQSTATUS_CTX_READY BIT(3) + +#define DTHE_HASH_MODE_ALG_MASK GENMASK(2, 0) +#define DTHE_HASH_MODE_USE_ALG_CONST BIT(3) +#define DTHE_HASH_MODE_CLOSE_HASH BIT(4) +#define DTHE_HASH_MODE_HMAC_KEY_PROCESSING BIT(5) +#define DTHE_HASH_MODE_HMAC_OUTER_HASH BIT(7) +/* Flag to indicate HMAC mode. This bit is not written in hardware registers */ +#define DTHE_HASH_IS_HMAC BIT(8) + +/* Misc */ +#define MD5_BLOCK_SIZE (MD5_BLOCK_WORDS * 4) +#define HMAC_SHA512_MAX_KEYSIZE (SHA512_BLOCK_SIZE) +#define HMAC_SHA256_MAX_KEYSIZE (SHA256_BLOCK_SIZE) +#define HMAC_MD5_MAX_KEYSIZE (MD5_BLOCK_SIZE) + +enum dthe_hash_dma_callback_src { + DMA_CALLBACK_FROM_UPDATE = 0, + DMA_CALLBACK_FROM_FINAL, + DMA_CALLBACK_FROM_FINUP, +}; + +struct sha512_export_state { + struct sha512_state state; + u32 odigest[SHA512_DIGEST_SIZE / sizeof(u32)]; + u32 key[HMAC_SHA512_MAX_KEYSIZE / sizeof(u32)]; + unsigned int keylen; + u8 buflen; + u8 flags; +}; + +struct sha256_export_state { + struct sha256_state state; + u32 odigest[SHA256_DIGEST_SIZE / sizeof(u32)]; + u32 key[HMAC_SHA256_MAX_KEYSIZE / sizeof(u32)]; + unsigned int keylen; + u8 buflen; + u8 flags; +}; + +struct md5_export_state { + struct md5_state state; + u32 odigest[MD5_DIGEST_SIZE / sizeof(u32)]; + u32 key[HMAC_MD5_MAX_KEYSIZE / sizeof(u32)]; + unsigned int keylen; + u8 buflen; + u8 flags; +}; + +static int cnt; + +static int dthe_ahash_init_fb(struct crypto_ahash *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(tfm); + struct dthe_data *dev_data = dthe_get_dev(ctx); + const char *alg_name = crypto_tfm_alg_name(&tfm->base); + + ctx->ahash_fb = crypto_alloc_ahash(alg_name, 0, CRYPTO_ALG_ASYNC); + if (IS_ERR(ctx->ahash_fb)) { + dev_err(dev_data->dev, "Failed to allocate fallback driver: %s\n", + alg_name); + return PTR_ERR(ctx->ahash_fb); + } + + crypto_ahash_set_reqsize(tfm, sizeof(struct ahash_request) + + crypto_ahash_reqsize(ctx->ahash_fb)); + + return 0; +} + +static void dthe_hash_write_zero_message(enum dthe_hash_alg_sel mode, void *dst) +{ + switch (mode) { + case DTHE_HASH_SHA512: + memcpy(dst, sha512_zero_message_hash, SHA512_DIGEST_SIZE); + break; + case DTHE_HASH_SHA384: + memcpy(dst, sha384_zero_message_hash, SHA384_DIGEST_SIZE); + break; + case DTHE_HASH_SHA256: + memcpy(dst, sha256_zero_message_hash, SHA256_DIGEST_SIZE); + break; + case DTHE_HASH_SHA224: + memcpy(dst, sha224_zero_message_hash, SHA224_DIGEST_SIZE); + break; + case DTHE_HASH_MD5: + memcpy(dst, md5_zero_message_hash, MD5_DIGEST_SIZE); + break; + default: + break; + } +} + +static int dthe_hmac_write_zero_message(struct ahash_request *req, void *dst) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct ahash_request *subreq = ahash_request_ctx(req); + int ret; + + ahash_request_set_tfm(subreq, ctx->ahash_fb); + ahash_request_set_callback(subreq, req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP, + req->base.complete, req->base.data); + ahash_request_set_crypt(subreq, req->src, dst, req->nbytes); + + ret = crypto_ahash_digest(subreq); + + return ret; +} + +static int dthe_sha512_init_tfm(struct crypto_ahash *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(tfm); + struct dthe_data *dev_data = dthe_get_dev(ctx); + + if (!dev_data) + return -ENODEV; + + crypto_ahash_set_reqsize(tfm, sizeof(struct dthe_hash_req_ctx)); + + ctx->hash_mode = DTHE_HASH_SHA512; + ctx->block_size = SHA512_BLOCK_SIZE; + ctx->digest_size = SHA512_DIGEST_SIZE; + ctx->phash_size = SHA512_DIGEST_SIZE; + + return 0; +} + +static int dthe_sha384_init_tfm(struct crypto_ahash *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(tfm); + struct dthe_data *dev_data = dthe_get_dev(ctx); + + if (!dev_data) + return -ENODEV; + + crypto_ahash_set_reqsize(tfm, sizeof(struct dthe_hash_req_ctx)); + + ctx->hash_mode = DTHE_HASH_SHA384; + ctx->block_size = SHA384_BLOCK_SIZE; + ctx->digest_size = SHA384_DIGEST_SIZE; + ctx->phash_size = SHA512_DIGEST_SIZE; + + return 0; +} + +static int dthe_sha256_init_tfm(struct crypto_ahash *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(tfm); + struct dthe_data *dev_data = dthe_get_dev(ctx); + + if (!dev_data) + return -ENODEV; + + crypto_ahash_set_reqsize(tfm, sizeof(struct dthe_hash_req_ctx)); + + ctx->hash_mode = DTHE_HASH_SHA256; + ctx->block_size = SHA256_BLOCK_SIZE; + ctx->digest_size = SHA256_DIGEST_SIZE; + ctx->phash_size = SHA256_DIGEST_SIZE; + + return 0; +} + +static int dthe_sha224_init_tfm(struct crypto_ahash *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(tfm); + struct dthe_data *dev_data = dthe_get_dev(ctx); + + if (!dev_data) + return -ENODEV; + + crypto_ahash_set_reqsize(tfm, sizeof(struct dthe_hash_req_ctx)); + + ctx->hash_mode = DTHE_HASH_SHA224; + ctx->block_size = SHA224_BLOCK_SIZE; + ctx->digest_size = SHA224_DIGEST_SIZE; + ctx->phash_size = SHA256_DIGEST_SIZE; + + return 0; +} + +static int dthe_md5_init_tfm(struct crypto_ahash *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(tfm); + struct dthe_data *dev_data = dthe_get_dev(ctx); + + if (!dev_data) + return -ENODEV; + + crypto_ahash_set_reqsize(tfm, sizeof(struct dthe_hash_req_ctx)); + + ctx->hash_mode = DTHE_HASH_MD5; + ctx->block_size = MD5_BLOCK_SIZE; + ctx->digest_size = MD5_DIGEST_SIZE; + ctx->phash_size = MD5_DIGEST_SIZE; + + return 0; +} + +static int dthe_hmac_sha512_init_tfm(struct crypto_ahash *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(tfm); + struct dthe_data *dev_data = dthe_get_dev(ctx); + int ret; + + if (!dev_data) + return -ENODEV; + + crypto_ahash_set_reqsize(tfm, sizeof(struct dthe_hash_req_ctx)); + + ctx->hash_mode = DTHE_HASH_SHA512 | DTHE_HASH_IS_HMAC; + ctx->block_size = SHA512_BLOCK_SIZE; + ctx->digest_size = SHA512_DIGEST_SIZE; + ctx->phash_size = SHA512_DIGEST_SIZE; + ret = dthe_ahash_init_fb(tfm); + + return ret; +} + +static int dthe_hmac_sha384_init_tfm(struct crypto_ahash *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(tfm); + struct dthe_data *dev_data = dthe_get_dev(ctx); + int ret; + + if (!dev_data) + return -ENODEV; + + crypto_ahash_set_reqsize(tfm, sizeof(struct dthe_hash_req_ctx)); + + ctx->hash_mode = DTHE_HASH_SHA384 | DTHE_HASH_IS_HMAC; + ctx->block_size = SHA384_BLOCK_SIZE; + ctx->digest_size = SHA384_DIGEST_SIZE; + ctx->phash_size = SHA512_DIGEST_SIZE; + ret = dthe_ahash_init_fb(tfm); + + return ret; +} + +static int dthe_hmac_sha256_init_tfm(struct crypto_ahash *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(tfm); + struct dthe_data *dev_data = dthe_get_dev(ctx); + int ret; + + if (!dev_data) + return -ENODEV; + + crypto_ahash_set_reqsize(tfm, sizeof(struct dthe_hash_req_ctx)); + + ctx->hash_mode = DTHE_HASH_SHA256 | DTHE_HASH_IS_HMAC; + ctx->block_size = SHA256_BLOCK_SIZE; + ctx->digest_size = SHA256_DIGEST_SIZE; + ctx->phash_size = SHA256_DIGEST_SIZE; + ret = dthe_ahash_init_fb(tfm); + + return ret; +} + +static int dthe_hmac_sha224_init_tfm(struct crypto_ahash *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(tfm); + struct dthe_data *dev_data = dthe_get_dev(ctx); + int ret; + + if (!dev_data) + return -ENODEV; + + crypto_ahash_set_reqsize(tfm, sizeof(struct dthe_hash_req_ctx)); + + ctx->hash_mode = DTHE_HASH_SHA224 | DTHE_HASH_IS_HMAC; + ctx->block_size = SHA224_BLOCK_SIZE; + ctx->digest_size = SHA224_DIGEST_SIZE; + ctx->phash_size = SHA256_DIGEST_SIZE; + ret = dthe_ahash_init_fb(tfm); + + return ret; +} + +static int dthe_hmac_md5_init_tfm(struct crypto_ahash *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(tfm); + struct dthe_data *dev_data = dthe_get_dev(ctx); + int ret; + + if (!dev_data) + return -ENODEV; + + crypto_ahash_set_reqsize(tfm, sizeof(struct dthe_hash_req_ctx)); + + ctx->hash_mode = DTHE_HASH_MD5 | DTHE_HASH_IS_HMAC; + ctx->block_size = MD5_BLOCK_SIZE; + ctx->digest_size = MD5_DIGEST_SIZE; + ctx->phash_size = MD5_DIGEST_SIZE; + ret = dthe_ahash_init_fb(tfm); + + return ret; +} + +static void dthe_hash_exit_tfm(struct crypto_ahash *tfm) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(tfm); + + if (ctx->hash_mode & DTHE_HASH_IS_HMAC) + crypto_free_ahash(ctx->ahash_fb); +} + +static void dthe_hash_dma_in_callback(void *data) +{ + struct ahash_request *req = (struct ahash_request *)data; + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + + complete(&rctx->hash_compl); +} + +static int dthe_hash_dma_start(struct ahash_request *req, struct scatterlist *src, + int src_nents, size_t len) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + struct dthe_data *dev_data = dthe_get_dev(ctx); + struct dma_slave_config cfg; + struct device *tx_dev; + struct dma_async_tx_descriptor *desc_out; + int mapped_nents; + enum dma_data_direction src_dir = DMA_TO_DEVICE; + u32 hash_mode; + int ret = 0; + u32 *dst; + u32 dst_len; + void __iomem *sha_base_reg = dev_data->regs + DTHE_P_HASH_BASE; + + u32 hash_sysconfig_val = DTHE_HASH_SYSCONFIG_INT_EN | DTHE_HASH_SYSCONFIG_DMA_EN; + u32 hash_irqenable_val = DTHE_HASH_IRQENABLE_EN_ALL; + + // Config SHA DMA channel as per SHA mode + memzero_explicit(&cfg, sizeof(cfg)); + + cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.dst_maxburst = ctx->block_size / 4; + + // HACK: Delay to workaround DMA driver issue + cnt++; + if (cnt % 20 == 0) { + unsigned long delay = jiffies + usecs_to_jiffies(1000); + + while (time_before(jiffies, delay)) + cond_resched(); + cnt = 0; + } + + mutex_lock(&dev_data->hash_mutex); + + ret = dmaengine_slave_config(dev_data->dma_sha_tx, &cfg); + if (ret) { + dev_err(dev_data->dev, "Can't configure OUT2 dmaengine slave: %d\n", ret); + goto hash_err; + } + + tx_dev = dmaengine_get_dma_device(dev_data->dma_sha_tx); + if (!tx_dev) { + ret = -ENODEV; + goto hash_err; + } + + mapped_nents = dma_map_sg(tx_dev, src, src_nents, src_dir); + if (mapped_nents == 0) { + ret = -EINVAL; + goto hash_err; + } + + desc_out = dmaengine_prep_slave_sg(dev_data->dma_sha_tx, src, mapped_nents, + DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + if (!desc_out) { + dev_err(dev_data->dev, "OUT prep_slave_sg() failed\n"); + ret = -EINVAL; + goto hash_prep_err; + } + + desc_out->callback = dthe_hash_dma_in_callback; + desc_out->callback_param = req; + + init_completion(&rctx->hash_compl); + + writel_relaxed(hash_sysconfig_val, sha_base_reg + DTHE_P_HASH_SYSCONFIG); + writel_relaxed(hash_irqenable_val, sha_base_reg + DTHE_P_HASH_IRQENABLE); + + hash_mode = (ctx->hash_mode & DTHE_HASH_MODE_ALG_MASK); + + if (rctx->flags == DMA_CALLBACK_FROM_FINAL || rctx->flags == DMA_CALLBACK_FROM_FINUP) { + hash_mode |= DTHE_HASH_MODE_CLOSE_HASH; + if (ctx->hash_mode & DTHE_HASH_IS_HMAC) + hash_mode |= DTHE_HASH_MODE_HMAC_OUTER_HASH; + } + + if (rctx->phash_available) { + for (int i = 0; i < ctx->phash_size / sizeof(u32); ++i) + writel_relaxed(rctx->phash[i], + sha_base_reg + + DTHE_P_HASH512_IDIGEST_A + + (DTHE_REG_SIZE * i)); + if (ctx->hash_mode & DTHE_HASH_IS_HMAC) { + for (int i = 0; i < ctx->phash_size / sizeof(u32); ++i) + writel_relaxed(rctx->odigest[i], + sha_base_reg + + DTHE_P_HASH512_ODIGEST_A + + (DTHE_REG_SIZE * i)); + } + + writel_relaxed(rctx->digestcnt, + sha_base_reg + DTHE_P_HASH512_DIGEST_COUNT); + } else if (ctx->hash_mode & DTHE_HASH_IS_HMAC) { + hash_mode |= DTHE_HASH_MODE_HMAC_KEY_PROCESSING; + + for (int i = 0; i < (ctx->keylen / 2) / sizeof(u32); ++i) + writel_relaxed(ctx->key[i], + sha_base_reg + + DTHE_P_HASH512_ODIGEST_A + + (DTHE_REG_SIZE * i)); + for (int i = 0; i < (ctx->keylen / 2) / sizeof(u32); ++i) + writel_relaxed(ctx->key[i + (ctx->keylen / 2) / sizeof(u32)], + sha_base_reg + + DTHE_P_HASH512_IDIGEST_A + + (DTHE_REG_SIZE * i)); + } else { + hash_mode |= DTHE_HASH_MODE_USE_ALG_CONST; + } + + writel_relaxed(hash_mode, sha_base_reg + DTHE_P_HASH512_MODE); + writel_relaxed(len, sha_base_reg + DTHE_P_HASH512_LENGTH); + + dmaengine_submit(desc_out); + + dma_async_issue_pending(dev_data->dma_sha_tx); + + ret = wait_for_completion_timeout(&rctx->hash_compl, + msecs_to_jiffies(DTHE_DMA_TIMEOUT_MS)); + if (!ret) { + dmaengine_terminate_sync(dev_data->dma_sha_tx); + ret = -ETIMEDOUT; + } else { + ret = 0; + } + + if (rctx->flags == DMA_CALLBACK_FROM_UPDATE) { + // If coming from update, we need to read the phash and store it for future + dst = rctx->phash; + dst_len = ctx->phash_size / sizeof(u32); + } else { + // If coming from finup or final, we need to read the final digest + dst = (u32 *)req->result; + dst_len = ctx->digest_size / sizeof(u32); + } + + for (int i = 0; i < dst_len; ++i) + dst[i] = readl_relaxed(sha_base_reg + + DTHE_P_HASH512_IDIGEST_A + + (DTHE_REG_SIZE * i)); + + if (ctx->hash_mode & DTHE_HASH_IS_HMAC) { + for (int i = 0; i < dst_len; ++i) + rctx->odigest[i] = readl_relaxed(sha_base_reg + + DTHE_P_HASH512_ODIGEST_A + + (DTHE_REG_SIZE * i)); + } + + rctx->digestcnt = readl_relaxed(sha_base_reg + DTHE_P_HASH512_DIGEST_COUNT); + rctx->phash_available = 1; + +hash_prep_err: + dma_unmap_sg(tx_dev, src, src_nents, src_dir); +hash_err: + mutex_unlock(&dev_data->hash_mutex); + ahash_request_complete(req, ret); + + return ret; +} + +static int dthe_hash_init(struct ahash_request *req) +{ + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + + rctx->phash_available = 0; + rctx->buflen = 0; + rctx->digestcnt = 0; + + return 0; +} + +static int dthe_hash_update(struct ahash_request *req) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + + struct scatterlist *src, *sg; + int src_nents = 0; + int in_nents = sg_nents_for_len(req->src, req->nbytes); + unsigned int tot_len; + unsigned int len_to_process; + unsigned int len_to_buffer; + int ret = 0; + + if (req->nbytes == 0) { + if (!rctx->phash_available && !rctx->buflen) { + if (ctx->hash_mode & DTHE_HASH_IS_HMAC) + ret = dthe_hmac_write_zero_message(req, rctx->phash); + else + dthe_hash_write_zero_message(ctx->hash_mode, rctx->phash); + } + + return ret; + } + + tot_len = rctx->buflen + req->nbytes; + len_to_process = tot_len - (tot_len % ctx->block_size); + len_to_buffer = ((len_to_process == 0) ? req->nbytes : (tot_len % ctx->block_size)); + + if (tot_len % ctx->block_size == 0) { + len_to_process -= ctx->block_size; + if (tot_len == ctx->block_size) + len_to_buffer = req->nbytes; + else + len_to_buffer = ctx->block_size; + } + + if (len_to_process == 0) { + sg_copy_to_buffer(req->src, in_nents, rctx->data_buf + rctx->buflen, len_to_buffer); + rctx->buflen += len_to_buffer; + return 0; + } + + if (len_to_buffer < req->nbytes) + src_nents = sg_nents_for_len(req->src, req->nbytes - len_to_buffer); + if (rctx->buflen > 0) + src_nents++; + + src = kcalloc(src_nents, sizeof(struct scatterlist), GFP_KERNEL); + if (!src) + return -ENOMEM; + + sg_init_table(src, src_nents); + sg = src; + + if (rctx->buflen > 0) { + sg_set_buf(sg, rctx->data_buf, rctx->buflen); + sg = sg_next(sg); + } + if (len_to_process > rctx->buflen) + dthe_copy_sg(sg, req->src, len_to_process - rctx->buflen); + + rctx->flags = DMA_CALLBACK_FROM_UPDATE; + ret = dthe_hash_dma_start(req, src, src_nents, len_to_process); + + sg_pcopy_to_buffer(req->src, in_nents, rctx->data_buf, + len_to_buffer, req->nbytes - len_to_buffer); + rctx->buflen = len_to_buffer; + + kfree(src); + + return ret; +} + +static int dthe_hash_final(struct ahash_request *req) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + struct scatterlist *src; + + int ret = 0; + + if (rctx->buflen > 0) { + src = kzalloc(sizeof(*src), GFP_KERNEL); + if (!src) + return -ENOMEM; + + /* Certain DMA restrictions forced us to send data in multiples of BLOCK_SIZE + * bytes. So, add a padding 0s at the end of src scatterlist if data is not a + * multiple of block_size bytes. The extra data is ignored by the DTHE hardware. + */ + for (int i = rctx->buflen; i < ctx->block_size; ++i) + rctx->data_buf[i] = 0; + + sg_init_one(src, rctx->data_buf, ctx->block_size); + + rctx->flags = DMA_CALLBACK_FROM_FINAL; + ret = dthe_hash_dma_start(req, src, 1, rctx->buflen); + + kfree(src); + + return ret; + } else if (!rctx->phash_available) { + if (ctx->hash_mode & DTHE_HASH_IS_HMAC) + ret = dthe_hmac_write_zero_message(req, req->result); + else + dthe_hash_write_zero_message(ctx->hash_mode, req->result); + + return ret; + } + + memcpy(req->result, rctx->phash, ctx->digest_size); + + return 0; +} + +static int dthe_hash_finup(struct ahash_request *req) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + + unsigned int tot_len = rctx->buflen + req->nbytes; + unsigned int pad_len = 0; + struct scatterlist *src, *sg; + int src_nents = 0; + u8 *pad_buf = rctx->padding; + int ret = 0; + + if (tot_len == 0) { + if (rctx->phash_available) + memcpy(req->result, rctx->phash, ctx->digest_size); + else if (ctx->hash_mode & DTHE_HASH_IS_HMAC) + ret = dthe_hmac_write_zero_message(req, req->result); + else + dthe_hash_write_zero_message(ctx->hash_mode, req->result); + + return ret; + } + + if (tot_len % ctx->block_size) + pad_len = ctx->block_size - (tot_len % ctx->block_size); + + if (req->nbytes > 0) + src_nents = sg_nents_for_len(req->src, req->nbytes); + if (rctx->buflen > 0) + src_nents++; + if (pad_len > 0) + src_nents++; + + src = kcalloc(src_nents, sizeof(struct scatterlist), GFP_KERNEL); + if (!src) + return -ENOMEM; + + sg_init_table(src, src_nents); + sg = src; + + if (rctx->buflen > 0) { + sg_set_buf(sg, rctx->data_buf, rctx->buflen); + sg = sg_next(sg); + } + if (req->nbytes > 0) + sg = dthe_copy_sg(sg, req->src, req->nbytes); + + /* Padding 0s in an additional nent at the end. See comment in dthe_hash_final function */ + if (pad_len > 0) { + memset(pad_buf, 0, pad_len); + sg_set_buf(sg, pad_buf, pad_len); + } + + rctx->flags = DMA_CALLBACK_FROM_FINUP; + ret = dthe_hash_dma_start(req, src, src_nents, tot_len); + + kfree(src); + + return ret; +} + +static int dthe_hash_digest(struct ahash_request *req) +{ + dthe_hash_init(req); + return dthe_hash_finup(req); +} + +static int dthe_hmac_setkey(struct crypto_ahash *tfm, const u8 *key, + unsigned int keylen) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(tfm); + unsigned int max_keysize; + const char *hash_alg_name, *alg_name; + + memzero_explicit(ctx->key, HMAC_SHA512_MAX_KEYSIZE); + alg_name = crypto_ahash_alg_name(tfm); + + if (strcmp(alg_name, "hmac(sha512)") == 0) { + max_keysize = HMAC_SHA512_MAX_KEYSIZE; + hash_alg_name = "sha512"; + } else if (strcmp(alg_name, "hmac(sha384)") == 0) { + max_keysize = HMAC_SHA512_MAX_KEYSIZE; + hash_alg_name = "sha384"; + } else if (strcmp(alg_name, "hmac(sha256)") == 0) { + max_keysize = HMAC_SHA256_MAX_KEYSIZE; + hash_alg_name = "sha256"; + } else if (strcmp(alg_name, "hmac(sha224)") == 0) { + max_keysize = HMAC_SHA256_MAX_KEYSIZE; + hash_alg_name = "sha224"; + } else if (strcmp(alg_name, "hmac(md5)") == 0) { + max_keysize = MD5_BLOCK_SIZE; + hash_alg_name = "md5"; + } else { + return -EINVAL; + } + + if (keylen > max_keysize) { + struct crypto_shash *ktfm = crypto_alloc_shash(hash_alg_name, 0, 0); + SHASH_DESC_ON_STACK(desc, ktfm); + int err; + + desc->tfm = ktfm; + err = crypto_shash_digest(desc, key, keylen, (u8 *)ctx->key); + + crypto_free_shash(ktfm); + + if (err) + return err; + } else { + memcpy(ctx->key, key, keylen); + } + + ctx->keylen = max_keysize; + + return crypto_ahash_setkey(ctx->ahash_fb, key, keylen); +} + +static int dthe_sha512_export(struct ahash_request *req, void *out) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + struct sha512_export_state *state = out; + + state->state.count[0] = rctx->digestcnt; + state->buflen = rctx->buflen; + state->flags = rctx->flags; + memcpy(state->state.state, rctx->phash, ctx->phash_size); + memcpy(state->state.buf, rctx->data_buf, rctx->buflen); + + return 0; +} + +static int dthe_sha512_import(struct ahash_request *req, const void *in) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + const struct sha512_export_state *state = in; + + rctx->buflen = state->buflen; + rctx->digestcnt = state->state.count[0]; + rctx->flags = state->flags; + rctx->phash_available = ((rctx->digestcnt) ? 1 : 0); + ctx->hash_mode = DTHE_HASH_SHA512; + ctx->block_size = SHA512_BLOCK_SIZE; + ctx->digest_size = SHA512_DIGEST_SIZE; + ctx->phash_size = SHA512_DIGEST_SIZE; + memcpy(rctx->phash, state->state.state, ctx->phash_size); + memcpy(rctx->data_buf, state->state.buf, rctx->buflen); + + return 0; +} + +static int dthe_sha384_import(struct ahash_request *req, const void *in) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + const struct sha512_export_state *state = in; + + rctx->buflen = state->buflen; + rctx->digestcnt = state->state.count[0]; + rctx->flags = state->flags; + rctx->phash_available = ((rctx->digestcnt) ? 1 : 0); + ctx->hash_mode = DTHE_HASH_SHA384; + ctx->block_size = SHA384_BLOCK_SIZE; + ctx->digest_size = SHA384_DIGEST_SIZE; + ctx->phash_size = SHA512_DIGEST_SIZE; + memcpy(rctx->phash, state->state.state, ctx->phash_size); + memcpy(rctx->data_buf, state->state.buf, rctx->buflen); + + return 0; +} + +static int dthe_sha256_export(struct ahash_request *req, void *out) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + struct sha256_export_state *state = out; + + state->state.count = rctx->digestcnt; + state->buflen = rctx->buflen; + state->flags = rctx->flags; + memcpy(state->state.state, rctx->phash, ctx->phash_size); + memcpy(state->state.buf, rctx->data_buf, rctx->buflen); + + return 0; +} + +static int dthe_sha256_import(struct ahash_request *req, const void *in) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + const struct sha256_export_state *state = in; + + rctx->buflen = state->buflen; + rctx->digestcnt = state->state.count; + rctx->flags = state->flags; + rctx->phash_available = ((rctx->digestcnt) ? 1 : 0); + ctx->hash_mode = DTHE_HASH_SHA256; + ctx->block_size = SHA256_BLOCK_SIZE; + ctx->digest_size = SHA256_DIGEST_SIZE; + ctx->phash_size = SHA256_DIGEST_SIZE; + memcpy(rctx->phash, state->state.state, ctx->phash_size); + memcpy(rctx->data_buf, state->state.buf, rctx->buflen); + + return 0; +} + +static int dthe_sha224_import(struct ahash_request *req, const void *in) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + const struct sha256_export_state *state = in; + + rctx->buflen = state->buflen; + rctx->digestcnt = state->state.count; + rctx->flags = state->flags; + rctx->phash_available = ((rctx->digestcnt) ? 1 : 0); + ctx->hash_mode = DTHE_HASH_SHA224; + ctx->block_size = SHA224_BLOCK_SIZE; + ctx->digest_size = SHA224_DIGEST_SIZE; + ctx->phash_size = SHA256_DIGEST_SIZE; + memcpy(rctx->phash, state->state.state, ctx->phash_size); + memcpy(rctx->data_buf, state->state.buf, rctx->buflen); + + return 0; +} + +static int dthe_md5_export(struct ahash_request *req, void *out) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + struct md5_export_state *state = out; + + state->state.byte_count = rctx->digestcnt; + state->buflen = rctx->buflen; + state->flags = rctx->flags; + memcpy(state->state.hash, rctx->phash, ctx->phash_size); + memcpy(state->state.block, rctx->data_buf, rctx->buflen); + + return 0; +} + +static int dthe_md5_import(struct ahash_request *req, const void *in) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + const struct md5_export_state *state = in; + + rctx->buflen = state->buflen; + rctx->digestcnt = state->state.byte_count; + rctx->flags = state->flags; + rctx->phash_available = ((rctx->digestcnt) ? 1 : 0); + ctx->hash_mode = DTHE_HASH_MD5; + ctx->block_size = MD5_BLOCK_SIZE; + ctx->digest_size = MD5_DIGEST_SIZE; + ctx->phash_size = MD5_DIGEST_SIZE; + memcpy(rctx->phash, state->state.hash, ctx->phash_size); + memcpy(rctx->data_buf, state->state.block, rctx->buflen); + + return 0; +} + +static int dthe_hmac_sha512_export(struct ahash_request *req, void *out) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + struct sha512_export_state *state = out; + + state->state.count[0] = rctx->digestcnt; + state->buflen = rctx->buflen; + state->flags = rctx->flags; + memcpy(state->state.state, rctx->phash, ctx->phash_size); + memcpy(state->state.buf, rctx->data_buf, rctx->buflen); + memcpy(state->key, ctx->key, HMAC_SHA512_MAX_KEYSIZE); + memcpy(state->odigest, rctx->odigest, SHA512_DIGEST_SIZE); + state->keylen = ctx->keylen; + + return 0; +} + +static int dthe_hmac_sha512_import(struct ahash_request *req, const void *in) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + const struct sha512_export_state *state = in; + + rctx->buflen = state->buflen; + rctx->digestcnt = state->state.count[0]; + rctx->flags = state->flags; + rctx->phash_available = ((rctx->digestcnt) ? 1 : 0); + ctx->hash_mode = DTHE_HASH_SHA512 | DTHE_HASH_IS_HMAC; + ctx->block_size = SHA512_BLOCK_SIZE; + ctx->digest_size = SHA512_DIGEST_SIZE; + ctx->phash_size = SHA512_DIGEST_SIZE; + memcpy(rctx->phash, state->state.state, ctx->phash_size); + memcpy(rctx->data_buf, state->state.buf, rctx->buflen); + memcpy(ctx->key, state->key, HMAC_SHA512_MAX_KEYSIZE); + memcpy(rctx->odigest, state->odigest, SHA512_DIGEST_SIZE); + ctx->keylen = state->keylen; + + return 0; +} + +static int dthe_hmac_sha384_import(struct ahash_request *req, const void *in) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + const struct sha512_export_state *state = in; + + rctx->buflen = state->buflen; + rctx->digestcnt = state->state.count[0]; + rctx->flags = state->flags; + rctx->phash_available = ((rctx->digestcnt) ? 1 : 0); + ctx->hash_mode = DTHE_HASH_SHA384 | DTHE_HASH_IS_HMAC; + ctx->block_size = SHA384_BLOCK_SIZE; + ctx->digest_size = SHA384_DIGEST_SIZE; + ctx->phash_size = SHA512_DIGEST_SIZE; + memcpy(rctx->phash, state->state.state, ctx->phash_size); + memcpy(rctx->data_buf, state->state.buf, rctx->buflen); + memcpy(ctx->key, state->key, HMAC_SHA512_MAX_KEYSIZE); + memcpy(rctx->odigest, state->odigest, SHA512_DIGEST_SIZE); + ctx->keylen = state->keylen; + + return 0; +} + +static int dthe_hmac_sha256_export(struct ahash_request *req, void *out) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + struct sha256_export_state *state = out; + + state->state.count = rctx->digestcnt; + state->buflen = rctx->buflen; + state->flags = rctx->flags; + memcpy(state->state.state, rctx->phash, ctx->phash_size); + memcpy(state->state.buf, rctx->data_buf, rctx->buflen); + memcpy(state->key, ctx->key, HMAC_SHA256_MAX_KEYSIZE); + memcpy(state->odigest, rctx->odigest, SHA256_DIGEST_SIZE); + state->keylen = ctx->keylen; + + return 0; +} + +static int dthe_hmac_sha256_import(struct ahash_request *req, const void *in) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + const struct sha256_export_state *state = in; + + rctx->buflen = state->buflen; + rctx->digestcnt = state->state.count; + rctx->flags = state->flags; + rctx->phash_available = ((rctx->digestcnt) ? 1 : 0); + ctx->hash_mode = DTHE_HASH_SHA256 | DTHE_HASH_IS_HMAC; + ctx->block_size = SHA256_BLOCK_SIZE; + ctx->digest_size = SHA256_DIGEST_SIZE; + ctx->phash_size = SHA256_DIGEST_SIZE; + memcpy(rctx->phash, state->state.state, ctx->phash_size); + memcpy(rctx->data_buf, state->state.buf, rctx->buflen); + memcpy(ctx->key, state->key, HMAC_SHA256_MAX_KEYSIZE); + memcpy(rctx->odigest, state->odigest, SHA256_DIGEST_SIZE); + ctx->keylen = state->keylen; + + return 0; +} + +static int dthe_hmac_sha224_import(struct ahash_request *req, const void *in) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + const struct sha256_export_state *state = in; + + rctx->buflen = state->buflen; + rctx->digestcnt = state->state.count; + rctx->flags = state->flags; + rctx->phash_available = ((rctx->digestcnt) ? 1 : 0); + ctx->hash_mode = DTHE_HASH_SHA224 | DTHE_HASH_IS_HMAC; + ctx->block_size = SHA224_BLOCK_SIZE; + ctx->digest_size = SHA224_DIGEST_SIZE; + ctx->phash_size = SHA256_DIGEST_SIZE; + memcpy(rctx->phash, state->state.state, ctx->phash_size); + memcpy(rctx->data_buf, state->state.buf, rctx->buflen); + memcpy(ctx->key, state->key, HMAC_SHA256_MAX_KEYSIZE); + memcpy(rctx->odigest, state->odigest, SHA256_DIGEST_SIZE); + ctx->keylen = state->keylen; + + return 0; +} + +static int dthe_hmac_md5_export(struct ahash_request *req, void *out) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + struct md5_export_state *state = out; + + state->state.byte_count = rctx->digestcnt; + state->buflen = rctx->buflen; + state->flags = rctx->flags; + memcpy(state->state.hash, rctx->phash, ctx->phash_size); + memcpy(state->state.block, rctx->data_buf, rctx->buflen); + memcpy(state->key, ctx->key, MD5_BLOCK_SIZE); + memcpy(state->odigest, rctx->odigest, MD5_DIGEST_SIZE); + state->keylen = ctx->keylen; + + return 0; +} + +static int dthe_hmac_md5_import(struct ahash_request *req, const void *in) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); + const struct md5_export_state *state = in; + + rctx->buflen = state->buflen; + rctx->digestcnt = state->state.byte_count; + rctx->flags = state->flags; + rctx->phash_available = ((rctx->digestcnt) ? 1 : 0); + ctx->hash_mode = DTHE_HASH_MD5 | DTHE_HASH_IS_HMAC; + ctx->block_size = MD5_BLOCK_SIZE; + ctx->digest_size = MD5_DIGEST_SIZE; + ctx->phash_size = MD5_DIGEST_SIZE; + memcpy(rctx->phash, state->state.hash, ctx->phash_size); + memcpy(rctx->data_buf, state->state.block, rctx->buflen); + memcpy(ctx->key, state->key, MD5_BLOCK_SIZE); + memcpy(rctx->odigest, state->odigest, MD5_DIGEST_SIZE); + ctx->keylen = state->keylen; + + return 0; +} + +static struct ahash_alg hash_algs[] = { + { + .init_tfm = dthe_sha512_init_tfm, + .init = dthe_hash_init, + .update = dthe_hash_update, + .final = dthe_hash_final, + .finup = dthe_hash_finup, + .digest = dthe_hash_digest, + .export = dthe_sha512_export, + .import = dthe_sha512_import, + .halg = { + .digestsize = SHA512_DIGEST_SIZE, + .statesize = sizeof(struct sha512_export_state), + .base = { + .cra_name = "sha512", + .cra_driver_name = "sha512-dthev2", + .cra_priority = 400, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY, + .cra_blocksize = SHA512_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_module = THIS_MODULE, + } + }, + }, + { + .init_tfm = dthe_sha384_init_tfm, + .init = dthe_hash_init, + .update = dthe_hash_update, + .final = dthe_hash_final, + .finup = dthe_hash_finup, + .digest = dthe_hash_digest, + .export = dthe_sha512_export, + .import = dthe_sha384_import, + .halg = { + .digestsize = SHA384_DIGEST_SIZE, + .statesize = sizeof(struct sha512_export_state), + .base = { + .cra_name = "sha384", + .cra_driver_name = "sha384-dthev2", + .cra_priority = 400, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY, + .cra_blocksize = SHA384_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_module = THIS_MODULE, + } + }, + }, + { + .init_tfm = dthe_sha256_init_tfm, + .init = dthe_hash_init, + .update = dthe_hash_update, + .final = dthe_hash_final, + .finup = dthe_hash_finup, + .digest = dthe_hash_digest, + .export = dthe_sha256_export, + .import = dthe_sha256_import, + .halg = { + .digestsize = SHA256_DIGEST_SIZE, + .statesize = sizeof(struct sha256_export_state), + .base = { + .cra_name = "sha256", + .cra_driver_name = "sha256-dthev2", + .cra_priority = 400, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY, + .cra_blocksize = SHA256_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_module = THIS_MODULE, + } + }, + }, + { + .init_tfm = dthe_sha224_init_tfm, + .init = dthe_hash_init, + .update = dthe_hash_update, + .final = dthe_hash_final, + .finup = dthe_hash_finup, + .digest = dthe_hash_digest, + .export = dthe_sha256_export, + .import = dthe_sha224_import, + .halg = { + .digestsize = SHA224_DIGEST_SIZE, + .statesize = sizeof(struct sha256_export_state), + .base = { + .cra_name = "sha224", + .cra_driver_name = "sha224-dthev2", + .cra_priority = 400, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY, + .cra_blocksize = SHA224_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_module = THIS_MODULE, + } + }, + }, + { + .init_tfm = dthe_md5_init_tfm, + .init = dthe_hash_init, + .update = dthe_hash_update, + .final = dthe_hash_final, + .finup = dthe_hash_finup, + .digest = dthe_hash_digest, + .export = dthe_md5_export, + .import = dthe_md5_import, + .halg = { + .digestsize = MD5_DIGEST_SIZE, + .statesize = sizeof(struct md5_export_state), + .base = { + .cra_name = "md5", + .cra_driver_name = "md5-dthev2", + .cra_priority = 400, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY, + .cra_blocksize = MD5_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_module = THIS_MODULE, + } + }, + }, + { + .init_tfm = dthe_hmac_sha512_init_tfm, + .exit_tfm = dthe_hash_exit_tfm, + .init = dthe_hash_init, + .update = dthe_hash_update, + .final = dthe_hash_final, + .finup = dthe_hash_finup, + .digest = dthe_hash_digest, + .export = dthe_hmac_sha512_export, + .import = dthe_hmac_sha512_import, + .setkey = dthe_hmac_setkey, + .halg = { + .digestsize = SHA512_DIGEST_SIZE, + .statesize = sizeof(struct sha512_export_state), + .base = { + .cra_name = "hmac(sha512)", + .cra_driver_name = "hmac-sha512-dthev2", + .cra_priority = 400, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY, + .cra_blocksize = SHA512_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_module = THIS_MODULE, + } + }, + }, + { + .init_tfm = dthe_hmac_sha384_init_tfm, + .exit_tfm = dthe_hash_exit_tfm, + .init = dthe_hash_init, + .update = dthe_hash_update, + .final = dthe_hash_final, + .finup = dthe_hash_finup, + .digest = dthe_hash_digest, + .export = dthe_hmac_sha512_export, + .import = dthe_hmac_sha384_import, + .setkey = dthe_hmac_setkey, + .halg = { + .digestsize = SHA384_DIGEST_SIZE, + .statesize = sizeof(struct sha512_export_state), + .base = { + .cra_name = "hmac(sha384)", + .cra_driver_name = "hmac-sha384-dthev2", + .cra_priority = 400, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY, + .cra_blocksize = SHA384_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_module = THIS_MODULE, + } + }, + }, + { + .init_tfm = dthe_hmac_sha256_init_tfm, + .exit_tfm = dthe_hash_exit_tfm, + .init = dthe_hash_init, + .update = dthe_hash_update, + .final = dthe_hash_final, + .finup = dthe_hash_finup, + .digest = dthe_hash_digest, + .export = dthe_hmac_sha256_export, + .import = dthe_hmac_sha256_import, + .setkey = dthe_hmac_setkey, + .halg = { + .digestsize = SHA256_DIGEST_SIZE, + .statesize = sizeof(struct sha256_export_state), + .base = { + .cra_name = "hmac(sha256)", + .cra_driver_name = "hmac-sha256-dthev2", + .cra_priority = 400, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY, + .cra_blocksize = SHA256_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_module = THIS_MODULE, + } + }, + }, + { + .init_tfm = dthe_hmac_sha224_init_tfm, + .exit_tfm = dthe_hash_exit_tfm, + .init = dthe_hash_init, + .update = dthe_hash_update, + .final = dthe_hash_final, + .finup = dthe_hash_finup, + .digest = dthe_hash_digest, + .export = dthe_hmac_sha256_export, + .import = dthe_hmac_sha224_import, + .setkey = dthe_hmac_setkey, + .halg = { + .digestsize = SHA224_DIGEST_SIZE, + .statesize = sizeof(struct sha256_export_state), + .base = { + .cra_name = "hmac(sha224)", + .cra_driver_name = "hmac-sha224-dthev2", + .cra_priority = 400, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY, + .cra_blocksize = SHA224_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_module = THIS_MODULE, + } + }, + }, + { + .init_tfm = dthe_hmac_md5_init_tfm, + .exit_tfm = dthe_hash_exit_tfm, + .init = dthe_hash_init, + .update = dthe_hash_update, + .final = dthe_hash_final, + .finup = dthe_hash_finup, + .digest = dthe_hash_digest, + .export = dthe_hmac_md5_export, + .import = dthe_hmac_md5_import, + .setkey = dthe_hmac_setkey, + .halg = { + .digestsize = MD5_DIGEST_SIZE, + .statesize = sizeof(struct md5_export_state), + .base = { + .cra_name = "hmac(md5)", + .cra_driver_name = "hmac-md5-dthev2", + .cra_priority = 400, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY, + .cra_blocksize = MD5_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_module = THIS_MODULE, + } + }, + }, +}; + +int dthe_register_hash_algs(void) +{ + return crypto_register_ahashes(hash_algs, ARRAY_SIZE(hash_algs)); +} + +void dthe_unregister_hash_algs(void) +{ + crypto_unregister_ahashes(hash_algs, ARRAY_SIZE(hash_algs)); +} diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/crypto/ti/Kconfig v_kernel/drivers/crypto/ti/Kconfig --- linux-6.12.57/drivers/crypto/ti/Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/crypto/ti/Kconfig 2026-04-21 11:35:35.893934546 +0200 @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-only +config CRYPTO_DEV_TI_MCRC64 + tristate "Texas Instruments MCRC64 engine support" + depends on ARCH_K3 || COMPILE_TEST + select CRYPTO_HASH + select CRYPTO_CRC64_ISO3309 + help + This enables support for the MCRC64 engine + which can be found on all AM62* and J722S devices. + MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC) + according to the ISO 3309 standard. + +config CRYPTO_DEV_TI_DTHEV2 + tristate "Support for TI DTHE V2 crypto accelerators" + depends on CRYPTO && CRYPTO_HW && ARCH_K3 + select CRYPTO_ENGINE + select CRYPTO_SKCIPHER + select CRYPTO_ECB + select CRYPTO_CBC + select CRYPTO_CTR + select CRYPTO_XTS + select CRYPTO_GCM + select CRYPTO_CCM + select CRYPTO_SHA256 + select CRYPTO_SHA512 + select CRYPTO_MD5 + select CRYPTO_HMAC + select SG_SPLIT + help + This enables support for the TI DTHE V2 hw crypto accelerator + which can be found on TI K3 SOCs. Selecting this enables use + of hardware acceleration for cryptographic algorithms on + these devices. diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/crypto/ti/Makefile v_kernel/drivers/crypto/ti/Makefile --- linux-6.12.57/drivers/crypto/ti/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/crypto/ti/Makefile 2026-04-21 11:35:35.894934549 +0200 @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_CRYPTO_DEV_TI_MCRC64) += mcrc64.o +obj-$(CONFIG_CRYPTO_DEV_TI_DTHEV2) += dthev2.o +dthev2-objs := dthev2-common.o dthev2-aes.o dthev2-hash.o diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/crypto/ti/mcrc64.c v_kernel/drivers/crypto/ti/mcrc64.c --- linux-6.12.57/drivers/crypto/ti/mcrc64.c 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/crypto/ti/mcrc64.c 2026-04-21 11:35:35.895934552 +0200 @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) Texas Instruments 2023 - http://www.ti.com + * Author: Kamlesh Gurudasani + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define DRIVER_NAME "mcrc64" +#define CHKSUM_DIGEST_SIZE 8 +#define CHKSUM_BLOCK_SIZE 1 + +/* Registers */ +#define CRC_CTRL0 0x0000 /* CRC Global Control Register 0 */ +#define CH_PSA_SWRE(ch) BIT(((ch) - 1) << 3) /* PSA Software Reset */ + +#define CRC_CTRL1 0x0008 /* CRC Global Control Register 1 */ +#define PWDN BIT(0) /* Power Down */ + +#define CRC_CTRL2 0x0010 /* CRC Global Control Register 2 */ +#define CH_MODE(ch, m) ((m) << (((ch) - 1) << 3)) + +#define PSA_SIGREGL(ch) ((0x6 + (4 * ((ch) - 1))) << 4) /* Signature register */ + +#define MCRC64_ALG_MASK 0x8000000000000000 +#define MCRC64_CRC64_POLY 0x000000000000001b + +#define MCRC64_AUTOSUSPEND_DELAY 50 + +enum mcrc64_mode { + MCRC64_MODE_DATA_CAPTURE = 0, + MCRC64_MODE_AUTO, + MCRC64_MODE_SEMI_CPU, + MCRC64_MODE_FULL_CPU, + MCRC64_MODE_INVALID, +}; + +enum mcrc64_channel { + MCRC64_CHANNEL_1 = 1, + MCRC64_CHANNEL_2, + MCRC64_CHANNEL_3, + MCRC64_CHANNEL_4, + MCRC64_CHANNEL_INVALID, +}; + +struct mcrc64_data { + struct list_head list; + struct device *dev; + void __iomem *regs; +}; + +struct mcrc64_list { + struct list_head dev_list; + spinlock_t lock; /* protect dev_list */ +}; + +static struct mcrc64_list mcrc64_dev_list = { + .dev_list = LIST_HEAD_INIT(mcrc64_dev_list.dev_list), + .lock = __SPIN_LOCK_UNLOCKED(mcrc64_dev_list.lock), +}; + +struct mcrc64_tfm_ctx { + struct mcrc64_data *dev_data; + u64 key; +}; + +struct mcrc64_desc_ctx { + u64 signature; +}; + +static struct mcrc64_data *mcrc64_get_dev(struct mcrc64_tfm_ctx *tctx) +{ + struct mcrc64_data *dev_data; + + if (tctx->dev_data) + return tctx->dev_data; + + spin_lock_bh(&mcrc64_dev_list.lock); + dev_data = list_first_entry(&mcrc64_dev_list.dev_list, struct mcrc64_data, list); + if (dev_data) + list_move_tail(&dev_data->list, &mcrc64_dev_list.dev_list); + spin_unlock_bh(&mcrc64_dev_list.lock); + + return dev_data; +} + +static int mcrc64_set_mode(void __iomem *regs, u32 channel, u32 mode) +{ + u32 mode_set_val; + u32 crc_ctrl2_reg = 0; + + if (mode < 0 || mode >= MCRC64_MODE_INVALID) + return -EINVAL; + + if (channel <= 0 || channel >= MCRC64_CHANNEL_INVALID) + return -EINVAL; + + mode_set_val = crc_ctrl2_reg | CH_MODE(channel, mode); + + /* Write CRC_CTRL2, set mode */ + writel_relaxed(mode_set_val, regs + CRC_CTRL2); + + return 0; +} + +static int mcrc64_reset_signature(void __iomem *regs, u32 channel) +{ + u32 crc_ctrl0_reg, reset_val, reset_undo_val; + + if (channel <= 0 || channel >= MCRC64_CHANNEL_INVALID) + return -EINVAL; + + /* reset PSA */ + crc_ctrl0_reg = readl_relaxed(regs + CRC_CTRL0); + + reset_val = crc_ctrl0_reg | CH_PSA_SWRE(channel); + reset_undo_val = crc_ctrl0_reg & ~CH_PSA_SWRE(channel); + + /* Write CRC_CTRL0 register, reset PSA register */ + writel_relaxed(reset_val, regs + CRC_CTRL0); + writel_relaxed(reset_undo_val, regs + CRC_CTRL0); + + return 0; +} + +/* This helper implements crc64 calculation using CPU */ +static u64 mcrc64_calculate_sw_crc(u64 crc, u8 byte) +{ + u64 bit = 0; + u8 j; + + for (j = 0; j < 8; j++) { + bit = crc & MCRC64_ALG_MASK; + crc <<= 1; + if (byte & (0x80 >> j)) + bit ^= MCRC64_ALG_MASK; + if (bit) + crc ^= MCRC64_CRC64_POLY; + } + + return crc; +} + +static int mcrc64_calculate_crc(void __iomem *regs, u32 channel, + const u8 *d8, size_t length, u64 *crc64) +{ + void __iomem *psa_reg; + u64 signature = 0; + + if (channel <= 0 || channel >= MCRC64_CHANNEL_INVALID) + return -EINVAL; + + psa_reg = regs + PSA_SIGREGL(channel); + + for (; length >= sizeof(u64); d8 += sizeof(u64), length -= sizeof(u64)) + writeq_relaxed(cpu_to_be64p((u64 *)d8), psa_reg); + + signature = readq_relaxed(psa_reg); + + if (length) { + while (length--) + signature = mcrc64_calculate_sw_crc(signature, *d8++); + + /* set capture mode */ + int ret = mcrc64_set_mode(regs, MCRC64_CHANNEL_1, + MCRC64_MODE_DATA_CAPTURE); + if (ret) + return ret; + + ret = mcrc64_reset_signature(regs, MCRC64_CHANNEL_1); + if (ret) + return ret; + + writeq_relaxed(signature, psa_reg); + + ret = mcrc64_set_mode(regs, MCRC64_CHANNEL_1, + MCRC64_MODE_FULL_CPU); + if (ret) + return ret; + } + + *crc64 = signature; + + return 0; +} + +static int mcrc64_cra_init(struct crypto_tfm *tfm) +{ + struct mcrc64_tfm_ctx *tctx = crypto_tfm_ctx(tfm); + struct mcrc64_data *dev_data; + + dev_data = mcrc64_get_dev(tctx); + if (!dev_data) + return -ENODEV; + + pm_runtime_get_sync(dev_data->dev); + + tctx->key = 0; + + return 0; +} + +static void mcrc64_cra_exit(struct crypto_tfm *tfm) +{ + struct mcrc64_tfm_ctx *tctx = crypto_tfm_ctx(tfm); + struct mcrc64_data *dev_data; + + dev_data = mcrc64_get_dev(tctx); + + pm_runtime_mark_last_busy(dev_data->dev); + pm_runtime_put_autosuspend(dev_data->dev); +} + +static int mcrc64_setkey(struct crypto_shash *tfm, const u8 *key, + unsigned int keylen) +{ + struct mcrc64_tfm_ctx *tctx = crypto_shash_ctx(tfm); + + if (keylen != sizeof(u64)) + return -EINVAL; + + tctx->key = get_unaligned_le64(key); + + return 0; +} + +static int mcrc64_init(struct shash_desc *desc) +{ + struct mcrc64_desc_ctx *ctx = shash_desc_ctx(desc); + struct mcrc64_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm); + struct mcrc64_data *dev_data; + void __iomem *psa_reg; + + dev_data = mcrc64_get_dev(tctx); + if (!dev_data) + return -ENODEV; + + pm_runtime_get_sync(dev_data->dev); + + /* set capture mode */ + int ret = mcrc64_set_mode(dev_data->regs, MCRC64_CHANNEL_1, + MCRC64_MODE_DATA_CAPTURE); + if (ret) + return ret; + + /* reset PSA */ + psa_reg = dev_data->regs + PSA_SIGREGL(MCRC64_CHANNEL_1); + ret = mcrc64_reset_signature(dev_data->regs, MCRC64_CHANNEL_1); + if (ret) + return ret; + + /* write key */ + writeq_relaxed(tctx->key, psa_reg); + + /* set full cpu mode */ + ret = mcrc64_set_mode(dev_data->regs, MCRC64_CHANNEL_1, + MCRC64_MODE_FULL_CPU); + if (ret) + return ret; + + ctx->signature = readq_relaxed(psa_reg); + + return 0; +} + +static int mcrc64_update(struct shash_desc *desc, const u8 *d8, + unsigned int length) +{ + struct mcrc64_desc_ctx *ctx = shash_desc_ctx(desc); + struct mcrc64_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm); + struct mcrc64_data *dev_data; + + dev_data = mcrc64_get_dev(tctx); + if (!dev_data) + return -ENODEV; + + return mcrc64_calculate_crc(dev_data->regs, MCRC64_CHANNEL_1, + d8, length, &ctx->signature); +} + +static int mcrc64_final(struct shash_desc *desc, u8 *out) +{ + struct mcrc64_desc_ctx *ctx = shash_desc_ctx(desc); + + /* Send computed CRC */ + put_unaligned_le64(ctx->signature, out); + return 0; +} + +static int mcrc64_finup(struct shash_desc *desc, const u8 *data, + unsigned int length, u8 *out) +{ + return mcrc64_update(desc, data, length) ?: + mcrc64_final(desc, out); +} + +static int mcrc64_digest(struct shash_desc *desc, const u8 *data, + unsigned int length, u8 *out) +{ + return mcrc64_init(desc) ?: mcrc64_finup(desc, data, length, out); +} + +static unsigned int refcnt; +static DEFINE_MUTEX(refcnt_lock); +static struct shash_alg algs[] = { + /* CRC-64 */ + { + .setkey = mcrc64_setkey, + .init = mcrc64_init, + .update = mcrc64_update, + .final = mcrc64_final, + .finup = mcrc64_finup, + .digest = mcrc64_digest, + .descsize = sizeof(struct mcrc64_desc_ctx), + .digestsize = CHKSUM_DIGEST_SIZE, + .base = { + .cra_name = CRC64_ISO3309_STRING, + .cra_driver_name = "mcrc64", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_OPTIONAL_KEY, + .cra_blocksize = CHKSUM_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct mcrc64_tfm_ctx), + .cra_module = THIS_MODULE, + .cra_init = mcrc64_cra_init, + .cra_exit = mcrc64_cra_exit, + } + } +}; + +static int mcrc64_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mcrc64_data *dev_data; + int ret; + + dev_data = devm_kzalloc(dev, sizeof(*dev_data), GFP_KERNEL); + if (!dev_data) + return -ENOMEM; + + dev_data->dev = dev; + dev_data->regs = devm_platform_ioremap_resource(pdev, 0); + + platform_set_drvdata(pdev, dev_data); + + spin_lock(&mcrc64_dev_list.lock); + list_add(&dev_data->list, &mcrc64_dev_list.dev_list); + spin_unlock(&mcrc64_dev_list.lock); + + mutex_lock(&refcnt_lock); + if (!refcnt) { + ret = crypto_register_shashes(algs, ARRAY_SIZE(algs)); + if (ret) { + mutex_unlock(&refcnt_lock); + dev_err(dev, "Failed to register\n"); + return ret; + } + } + refcnt++; + mutex_unlock(&refcnt_lock); + + pm_runtime_set_autosuspend_delay(dev, MCRC64_AUTOSUSPEND_DELAY); + pm_runtime_use_autosuspend(dev); + + pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + pm_runtime_put_sync(dev); + + return 0; +} + +static void mcrc64_remove(struct platform_device *pdev) +{ + struct mcrc64_data *dev_data = platform_get_drvdata(pdev); + + pm_runtime_resume_and_get(dev_data->dev); + + spin_lock(&mcrc64_dev_list.lock); + list_del(&dev_data->list); + spin_unlock(&mcrc64_dev_list.lock); + + mutex_lock(&refcnt_lock); + if (!--refcnt) + crypto_unregister_shashes(algs, ARRAY_SIZE(algs)); + mutex_unlock(&refcnt_lock); + + pm_runtime_disable(dev_data->dev); + pm_runtime_put_noidle(dev_data->dev); +} + +static int __maybe_unused mcrc64_suspend(struct device *dev) +{ + return pm_runtime_force_suspend(dev); +} + +static int __maybe_unused mcrc64_resume(struct device *dev) +{ + return pm_runtime_force_resume(dev); +} + +static const struct dev_pm_ops mcrc64_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(mcrc64_suspend, + mcrc64_resume) +}; + +static const struct of_device_id of_match[] = { + { .compatible = "ti,am62-mcrc64", }, + {}, +}; +MODULE_DEVICE_TABLE(of, of_match); + +static struct platform_driver mcrc64_driver = { + .probe = mcrc64_probe, + .remove = mcrc64_remove, + .driver = { + .name = DRIVER_NAME, + .pm = &mcrc64_pm_ops, + .of_match_table = of_match, + }, +}; + +module_platform_driver(mcrc64_driver); + +MODULE_AUTHOR("Kamlesh Gurudasani "); +MODULE_DESCRIPTION("Texas Instruments MCRC64 driver"); +MODULE_LICENSE("GPL"); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/dma/ti/k3-psil-am62l.c v_kernel/drivers/dma/ti/k3-psil-am62l.c --- linux-6.12.57/drivers/dma/ti/k3-psil-am62l.c 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/dma/ti/k3-psil-am62l.c 2026-04-21 11:35:36.141935197 +0200 @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com + */ + +#include + +#include "k3-psil-priv.h" + +#define PSIL_PDMA_XY_TR(x, ch) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .mapped_channel_id = ch, \ + .default_flow_id = -1, \ + }, \ + } + +#define PSIL_PDMA_XY_PKT(x, ch) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .mapped_channel_id = ch, \ + .pkt_mode = 1, \ + .default_flow_id = -1 \ + }, \ + } + +#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 16, \ + .mapped_channel_id = ch, \ + .flow_start = flow_base, \ + .flow_num = flow_cnt, \ + .default_flow_id = flow_base, \ + }, \ + } + +#define PSIL_PDMA_MCASP(x, ch) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .pdma_acc32 = 1, \ + .pdma_burst = 1, \ + .mapped_channel_id = ch, \ + }, \ + } + +/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ +static struct psil_ep am62l_src_ep_map[] = { + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0x4400, 0), + PSIL_PDMA_XY_PKT(0x4401, 2), + PSIL_PDMA_XY_PKT(0x4402, 4), + PSIL_PDMA_XY_PKT(0x4403, 6), + PSIL_PDMA_XY_PKT(0x4404, 8), + PSIL_PDMA_XY_PKT(0x4405, 10), + PSIL_PDMA_XY_PKT(0x4406, 12), + /* PDMA_MAIN0 - SPI0 - CH0-3 */ + PSIL_PDMA_XY_TR(0x4300, 16), + /* PDMA_MAIN0 - SPI1 - CH0-3 */ + PSIL_PDMA_XY_TR(0x4301, 24), + /* PDMA_MAIN0 - SPI2 - CH0-3 */ + PSIL_PDMA_XY_TR(0x4302, 32), + /* PDMA_MAIN0 - SPI3 - CH0-3 */ + PSIL_PDMA_XY_TR(0x4303, 40), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0x4500, 48), + PSIL_PDMA_MCASP(0x4501, 50), + PSIL_PDMA_MCASP(0x4502, 52), + /* PDMA_MAIN0 - AES */ + PSIL_PDMA_XY_TR(0x4700, 65), + /* PDMA_MAIN0 - ADC */ + PSIL_PDMA_XY_TR(0x4503, 80), + PSIL_PDMA_XY_TR(0x4504, 81), + PSIL_ETHERNET(0x4600, 96, 96, 16), +}; + +/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ +static struct psil_ep am62l_dst_ep_map[] = { + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0xC400, 1), + PSIL_PDMA_XY_PKT(0xC401, 3), + PSIL_PDMA_XY_PKT(0xC402, 5), + PSIL_PDMA_XY_PKT(0xC403, 7), + PSIL_PDMA_XY_PKT(0xC404, 9), + PSIL_PDMA_XY_PKT(0xC405, 11), + PSIL_PDMA_XY_PKT(0xC406, 13), + /* PDMA_MAIN0 - SPI0 - CH0-3 */ + PSIL_PDMA_XY_TR(0xC300, 17), + /* PDMA_MAIN0 - SPI1 - CH0-3 */ + PSIL_PDMA_XY_TR(0xC301, 25), + /* PDMA_MAIN0 - SPI2 - CH0-3 */ + PSIL_PDMA_XY_TR(0xC302, 33), + /* PDMA_MAIN0 - SPI3 - CH0-3 */ + PSIL_PDMA_XY_TR(0xC303, 41), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0xC500, 49), + PSIL_PDMA_MCASP(0xC501, 51), + PSIL_PDMA_MCASP(0xC502, 53), + /* PDMA_MAIN0 - SHA */ + PSIL_PDMA_XY_TR(0xC700, 64), + /* PDMA_MAIN0 - AES */ + PSIL_PDMA_XY_TR(0xC701, 66), + /* PDMA_MAIN0 - CRC32 - CH0-1 */ + PSIL_PDMA_XY_TR(0xC702, 67), + /* CPSW3G */ + PSIL_ETHERNET(0xc600, 64, 64, 2), + PSIL_ETHERNET(0xc601, 66, 66, 2), + PSIL_ETHERNET(0xc602, 68, 68, 2), + PSIL_ETHERNET(0xc603, 70, 70, 2), + PSIL_ETHERNET(0xc604, 72, 72, 2), + PSIL_ETHERNET(0xc605, 74, 74, 2), + PSIL_ETHERNET(0xc606, 76, 76, 2), + PSIL_ETHERNET(0xc607, 78, 78, 2), +}; + +struct psil_ep_map am62l_ep_map = { + .name = "am62l", + .src = am62l_src_ep_map, + .src_count = ARRAY_SIZE(am62l_src_ep_map), + .dst = am62l_dst_ep_map, + .dst_count = ARRAY_SIZE(am62l_dst_ep_map), +}; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/dma/ti/k3-psil.c v_kernel/drivers/dma/ti/k3-psil.c --- linux-6.12.57/drivers/dma/ti/k3-psil.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/dma/ti/k3-psil.c 2026-04-21 11:35:36.142935199 +0200 @@ -25,6 +25,7 @@ { .family = "J721S2", .data = &j721s2_ep_map }, { .family = "AM62X", .data = &am62_ep_map }, { .family = "AM62AX", .data = &am62a_ep_map }, + { .family = "AM62LX", .data = &am62l_ep_map }, { .family = "J784S4", .data = &j784s4_ep_map }, { .family = "AM62PX", .data = &am62p_ep_map }, { .family = "J722S", .data = &am62p_ep_map }, diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/dma/ti/k3-psil-priv.h v_kernel/drivers/dma/ti/k3-psil-priv.h --- linux-6.12.57/drivers/dma/ti/k3-psil-priv.h 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/dma/ti/k3-psil-priv.h 2026-04-21 11:35:36.142935199 +0200 @@ -44,6 +44,7 @@ extern struct psil_ep_map j721s2_ep_map; extern struct psil_ep_map am62_ep_map; extern struct psil_ep_map am62a_ep_map; +extern struct psil_ep_map am62l_ep_map; extern struct psil_ep_map j784s4_ep_map; extern struct psil_ep_map am62p_ep_map; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/dma/ti/k3-udma-am62l.c v_kernel/drivers/dma/ti/k3-udma-am62l.c --- linux-6.12.57/drivers/dma/ti/k3-udma-am62l.c 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/dma/ti/k3-udma-am62l.c 2026-04-21 11:35:36.143935202 +0200 @@ -0,0 +1,1509 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Derived from K3 UDMA driver (k3-udma.c) + * Copyright (C) 2024-2025 Texas Instruments Incorporated - http://www.ti.com + * Author: Peter Ujfalusi + * Author: Sai Sree Kartheek Adivi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../virt-dma.h" +#include "k3-udma.h" +#include "k3-psil-priv.h" + +#define UDMA_CHAN_RT_STATIC_TR_XY_REG 0x800 +#define UDMA_CHAN_RT_STATIC_TR_Z_REG 0x804 +#define UDMA_CHAN_RT_PERIPH_BCNT_REG 0x810 + +static const char * const am62l_mmr_names[] = { + [AM62L_MMR_GCFG] = "gcfg", + [AM62L_MMR_BCHANRT] = "bchanrt", + [AM62L_MMR_CHANRT] = "chanrt", +}; + +static int am62l_udma_check_chan_autopair_completion(struct udma_chan *uc) +{ + u32 val; + + val = udma_chanrt_read(uc, UDMA_CHAN_RT_CTL_REG); + if (val & UDMA_CHAN_RT_CTL_PAIR_TIMEOUT) + return -ETIMEDOUT; + else if (val & UDMA_CHAN_RT_CTL_PAIR_COMPLETE) + return 1; + + /* timeout didn't occur and also pairing didn't happen yet. */ + return 0; +} + +static bool am62l_udma_is_chan_paused(struct udma_chan *uc) +{ + u32 val, pause_mask; + + if (uc->config.dir == DMA_MEM_TO_MEM) { + val = udma_chanrt_read(uc, UDMA_CHAN_RT_CTL_REG); + pause_mask = UDMA_CHAN_RT_CTL_PAUSE; + } else { + val = udma_chanrt_read(uc, UDMA_CHAN_RT_PDMA_STATE_REG); + pause_mask = UDMA_CHAN_RT_PDMA_STATE_PAUSE; + } + + if (val & pause_mask) + return true; + + return false; +} + +static void am62l_udma_decrement_byte_counters(struct udma_chan *uc, u32 val) +{ + udma_chanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val); + udma_chanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val); + if (uc->config.ep_type != PSIL_EP_NATIVE) + udma_chanrt_write(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG, val); +} + +static void am62l_udma_reset_counters(struct udma_chan *uc) +{ + u32 val; + + val = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG); + udma_chanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val); + + val = udma_chanrt_read(uc, UDMA_CHAN_RT_SBCNT_REG); + udma_chanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val); + + val = udma_chanrt_read(uc, UDMA_CHAN_RT_PCNT_REG); + udma_chanrt_write(uc, UDMA_CHAN_RT_PCNT_REG, val); + + if (!uc->bchan) { + val = udma_chanrt_read(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG); + udma_chanrt_write(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG, val); + } +} + +static int am62l_udma_reset_chan(struct udma_chan *uc, bool hard) +{ + udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG, 0); + + /* Reset all counters */ + am62l_udma_reset_counters(uc); + + /* Hard reset: re-initialize the channel to reset */ + if (hard) { + struct udma_chan_config ucc_backup; + int ret; + + memcpy(&ucc_backup, &uc->config, sizeof(uc->config)); + uc->ud->ddev.device_free_chan_resources(&uc->vc.chan); + + /* restore the channel configuration */ + memcpy(&uc->config, &ucc_backup, sizeof(uc->config)); + ret = uc->ud->ddev.device_alloc_chan_resources(&uc->vc.chan); + if (ret) + return ret; + + /* + * Setting forced teardown after forced reset helps recovering + * the rchan. + */ + if (uc->config.dir == DMA_DEV_TO_MEM) + udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN | + UDMA_CHAN_RT_CTL_FTDOWN, + UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN | + UDMA_CHAN_RT_CTL_FTDOWN); + } + uc->state = UDMA_CHAN_IS_IDLE; + + return 0; +} + +static int am62l_udma_start(struct udma_chan *uc) +{ + struct virt_dma_desc *vd = vchan_next_desc(&uc->vc); + struct udma_dev *ud = uc->ud; + int status, ret; + + if (!vd) { + uc->desc = NULL; + return -ENOENT; + } + + list_del(&vd->node); + + uc->desc = to_udma_desc(&vd->tx); + + /* Channel is already running and does not need reconfiguration */ + if (udma_is_chan_running(uc) && !udma_chan_needs_reconfiguration(uc)) { + udma_start_desc(uc); + goto out; + } + + /* Make sure that we clear the teardown bit, if it is set */ + ud->udma_reset_chan(uc, false); + + /* Push descriptors before we start the channel */ + udma_start_desc(uc); + + switch (uc->desc->dir) { + case DMA_DEV_TO_MEM: + /* Config remote TR */ + if (uc->config.ep_type == PSIL_EP_PDMA_XY) { + u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) | + PDMA_STATIC_TR_X(uc->desc->static_tr.elsize); + const struct udma_match_data *match_data = + uc->ud->match_data; + + if (uc->config.enable_acc32) + val |= PDMA_STATIC_TR_XY_ACC32; + if (uc->config.enable_burst) + val |= PDMA_STATIC_TR_XY_BURST; + + udma_chanrt_write(uc, + UDMA_CHAN_RT_STATIC_TR_XY_REG, + val); + + udma_chanrt_write(uc, + UDMA_CHAN_RT_STATIC_TR_Z_REG, + PDMA_STATIC_TR_Z(uc->desc->static_tr.bstcnt, + match_data->statictr_z_mask)); + + /* save the current staticTR configuration */ + memcpy(&uc->static_tr, &uc->desc->static_tr, + sizeof(uc->static_tr)); + } + + udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_AUTOPAIR); + + /* Poll for autopair completion */ + ret = read_poll_timeout_atomic(am62l_udma_check_chan_autopair_completion, + status, status != 0, 100, 500, false, uc); + + if (ret <= 0) + return -ETIMEDOUT; + + break; + case DMA_MEM_TO_DEV: + /* Config remote TR */ + if (uc->config.ep_type == PSIL_EP_PDMA_XY) { + u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) | + PDMA_STATIC_TR_X(uc->desc->static_tr.elsize); + + if (uc->config.enable_acc32) + val |= PDMA_STATIC_TR_XY_ACC32; + if (uc->config.enable_burst) + val |= PDMA_STATIC_TR_XY_BURST; + + udma_chanrt_write(uc, + UDMA_CHAN_RT_STATIC_TR_XY_REG, + val); + + /* save the current staticTR configuration */ + memcpy(&uc->static_tr, &uc->desc->static_tr, + sizeof(uc->static_tr)); + } + + udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_AUTOPAIR); + + /* Poll for autopair completion */ + ret = read_poll_timeout_atomic(am62l_udma_check_chan_autopair_completion, + status, status != 0, 100, 500, false, uc); + + if (status <= 0) + return -ETIMEDOUT; + + break; + case DMA_MEM_TO_MEM: + udma_bchanrt_write(uc, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN); + udma_bchanrt_write(uc, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN); + + break; + default: + return -EINVAL; + } + + uc->state = UDMA_CHAN_IS_ACTIVE; +out: + + return 0; +} + +static int am62l_udma_stop(struct udma_chan *uc) +{ + uc->state = UDMA_CHAN_IS_TERMINATING; + reinit_completion(&uc->teardown_completed); + + if (uc->config.dir == DMA_DEV_TO_MEM) { + if (!uc->cyclic && !uc->desc) + udma_push_to_ring(uc, -1); + } + + udma_chanrt_write(uc, UDMA_CHAN_RT_PEER_REG(8), UDMA_CHAN_RT_PEER_REG8_FLUSH); + udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN, + UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN); + + return 0; +} + +static bool am62l_udma_is_desc_really_done(struct udma_chan *uc, struct udma_desc *d) +{ + u32 peer_bcnt, bcnt; + + /* + * Only TX towards PDMA is affected. + * If DMA_PREP_INTERRUPT is not set by consumer then skip the transfer + * completion calculation, consumer must ensure that there is no stale + * data in DMA fabric in this case. + */ + if (uc->config.ep_type == PSIL_EP_NATIVE || + uc->config.dir != DMA_MEM_TO_DEV || !(uc->config.tx_flags & DMA_PREP_INTERRUPT)) + return true; + + peer_bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG); + bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG); + + /* Transfer is incomplete, store current residue and time stamp */ + if (peer_bcnt < bcnt) { + uc->tx_drain.residue = bcnt - peer_bcnt; + uc->tx_drain.tstamp = ktime_get(); + return false; + } + + return true; +} + +static irqreturn_t am62l_udma_udma_irq_handler(int irq, void *data) +{ + struct udma_chan *uc = data; + struct udma_dev *ud = uc->ud; + struct udma_desc *d; + + switch (uc->config.dir) { + case DMA_DEV_TO_MEM: + k3_ringacc_ring_clear_irq(uc->rflow->r_ring); + break; + case DMA_MEM_TO_DEV: + case DMA_MEM_TO_MEM: + k3_ringacc_ring_clear_irq(uc->tchan->tc_ring); + break; + default: + return -ENOENT; + } + + spin_lock(&uc->vc.lock); + d = uc->desc; + if (d) { + d->tr_idx = (d->tr_idx + 1) % d->sglen; + + if (uc->cyclic) { + vchan_cyclic_callback(&d->vd); + } else { + /* TODO: figure out the real amount of data */ + ud->udma_decrement_byte_counters(uc, d->residue); + ud->udma_start(uc); + vchan_cookie_complete(&d->vd); + } + } + + spin_unlock(&uc->vc.lock); + + return IRQ_HANDLED; +} + +static irqreturn_t am62l_udma_ring_irq_handler(int irq, void *data) +{ + struct udma_chan *uc = data; + struct udma_dev *ud = uc->ud; + struct udma_desc *d; + dma_addr_t paddr = 0; + u32 intr_status, reg; + + switch (uc->config.dir) { + case DMA_DEV_TO_MEM: + intr_status = k3_ringacc_ring_get_irq_status(uc->rflow->r_ring); + break; + case DMA_MEM_TO_DEV: + case DMA_MEM_TO_MEM: + intr_status = k3_ringacc_ring_get_irq_status(uc->tchan->tc_ring); + break; + default: + return -ENOENT; + } + + reg = udma_chanrt_read(uc, UDMA_CHAN_RT_CTL_REG); + + if (intr_status & K3_RINGACC_RT_INT_STATUS_TR) { + /* check teardown status */ + if ((reg & UDMA_CHAN_RT_CTL_TDOWN) && !(reg & UDMA_CHAN_RT_CTL_EN)) + complete_all(&uc->teardown_completed); + return am62l_udma_udma_irq_handler(irq, data); + } + + if (udma_pop_from_ring(uc, &paddr) || !paddr) + return IRQ_HANDLED; + + spin_lock(&uc->vc.lock); + + /* Teardown completion message */ + if (cppi5_desc_is_tdcm(paddr)) { + complete_all(&uc->teardown_completed); + + if (uc->terminated_desc) { + udma_desc_free(&uc->terminated_desc->vd); + uc->terminated_desc = NULL; + } + + if (!uc->desc) + ud->udma_start(uc); + + goto out; + } + + d = udma_udma_desc_from_paddr(uc, paddr); + + if (d) { + dma_addr_t desc_paddr = udma_curr_cppi5_desc_paddr(d, + d->desc_idx); + if (desc_paddr != paddr) { + dev_err(uc->ud->dev, "not matching descriptors!\n"); + goto out; + } + + if (d == uc->desc) { + /* active descriptor */ + if (uc->cyclic) { + udma_cyclic_packet_elapsed(uc); + vchan_cyclic_callback(&d->vd); + } else { + if (ud->udma_is_desc_really_done(uc, d)) { + ud->udma_decrement_byte_counters(uc, d->residue); + ud->udma_start(uc); + vchan_cookie_complete(&d->vd); + } else { + schedule_delayed_work(&uc->tx_drain.work, + 0); + } + } + } else { + /* + * terminated descriptor, mark the descriptor as + * completed to update the channel's cookie marker + */ + dma_cookie_complete(&d->vd.tx); + } + } +out: + spin_unlock(&uc->vc.lock); + + return IRQ_HANDLED; +} + +static int am62l_bcdma_v2_get_bchan(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + enum udma_tp_level tpl; + int ret; + + if (uc->bchan) { + dev_dbg(ud->dev, "chan%d: already have bchan%d allocated\n", + uc->id, uc->bchan->id); + return 0; + } + + /* + * Use normal channels for peripherals, and highest TPL channel for + * mem2mem + */ + if (uc->config.tr_trigger_type) + tpl = 0; + else + tpl = ud->bchan_tpl.levels - 1; + + uc->bchan = __udma_reserve_bchan(ud, tpl, uc->id); + if (IS_ERR(uc->bchan)) { + ret = PTR_ERR(uc->bchan); + uc->bchan = NULL; + return ret; + } + uc->chan = uc->bchan; + uc->tchan = uc->bchan; + + return 0; +} + +static int am62l_bcdma_v2_alloc_bchan_resources(struct udma_chan *uc) +{ + struct k3_ring_cfg ring_cfg; + struct udma_dev *ud = uc->ud; + int ret; + + ret = am62l_bcdma_v2_get_bchan(uc); + if (ret) + return ret; + + ret = k3_ringacc_request_rings_pair(ud->ringacc, ud->match_data->chan_cnt + uc->id, -1, + &uc->bchan->t_ring, + &uc->bchan->tc_ring); + if (ret) { + ret = -EBUSY; + goto err_ring; + } + + memset(&ring_cfg, 0, sizeof(ring_cfg)); + ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE; + ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8; + ring_cfg.mode = K3_RINGACC_RING_MODE_RING; + + k3_configure_chan_coherency(&uc->vc.chan, ud->asel); + ring_cfg.asel = ud->asel; + ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan); + + ret = k3_ringacc_ring_cfg(uc->bchan->t_ring, &ring_cfg); + if (ret) + goto err_ringcfg; + + return 0; + +err_ringcfg: + k3_ringacc_ring_free(uc->bchan->tc_ring); + uc->bchan->tc_ring = NULL; + k3_ringacc_ring_free(uc->bchan->t_ring); + uc->bchan->t_ring = NULL; + k3_configure_chan_coherency(&uc->vc.chan, 0); +err_ring: + bcdma_put_bchan(uc); + + return ret; +} + +static int am62l_udma_alloc_tx_resources(struct udma_chan *uc) +{ + struct k3_ring_cfg ring_cfg; + struct udma_dev *ud = uc->ud; + struct udma_tchan *tchan; + int ring_idx, ret; + + ret = udma_get_tchan(uc); + if (ret) + return ret; + + tchan = uc->tchan; + if (tchan->tflow_id >= 0) + ring_idx = tchan->tflow_id; + else + ring_idx = tchan->id; + + ret = k3_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1, + &tchan->t_ring, + &tchan->tc_ring); + if (ret) { + ret = -EBUSY; + goto err_ring; + } + + memset(&ring_cfg, 0, sizeof(ring_cfg)); + ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE; + ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8; + ring_cfg.mode = K3_RINGACC_RING_MODE_RING; + + k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel); + ring_cfg.asel = uc->config.asel; + ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan); + + ret = k3_ringacc_ring_cfg(tchan->t_ring, &ring_cfg); + ret |= k3_ringacc_ring_cfg(tchan->tc_ring, &ring_cfg); + + if (ret) + goto err_ringcfg; + + return 0; + +err_ringcfg: + k3_ringacc_ring_free(uc->tchan->tc_ring); + uc->tchan->tc_ring = NULL; + k3_ringacc_ring_free(uc->tchan->t_ring); + uc->tchan->t_ring = NULL; +err_ring: + udma_put_tchan(uc); + + return ret; +} + +static int am62l_udma_alloc_rx_resources(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + struct k3_ring_cfg ring_cfg; + struct udma_rflow *rflow; + int fd_ring_id; + int ret; + + ret = udma_get_rchan(uc); + if (ret) + return ret; + + /* For MEM_TO_MEM we don't need rflow or rings */ + if (uc->config.dir == DMA_MEM_TO_MEM) + return 0; + + if (uc->config.default_flow_id >= 0) + ret = udma_get_rflow(uc, uc->config.default_flow_id); + else + ret = udma_get_rflow(uc, uc->rchan->id); + + if (ret) { + ret = -EBUSY; + goto err_rflow; + } + + rflow = uc->rflow; + if (ud->tflow_cnt) + fd_ring_id = ud->tflow_cnt + rflow->id; + else + fd_ring_id = uc->rchan->id; + ret = k3_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1, + &rflow->fd_ring, &rflow->r_ring); + if (ret) { + ret = -EBUSY; + goto err_ring; + } + + memset(&ring_cfg, 0, sizeof(ring_cfg)); + + ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8; + ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE; + ring_cfg.mode = K3_RINGACC_RING_MODE_RING; + + k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel); + ring_cfg.asel = uc->config.asel; + ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan); + + ret = k3_ringacc_ring_cfg(rflow->fd_ring, &ring_cfg); + + ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE; + ret |= k3_ringacc_ring_cfg(rflow->r_ring, &ring_cfg); + + if (ret) + goto err_ringcfg; + + return 0; + +err_ringcfg: + k3_ringacc_ring_free(rflow->r_ring); + rflow->r_ring = NULL; + k3_ringacc_ring_free(rflow->fd_ring); + rflow->fd_ring = NULL; +err_ring: + udma_put_rflow(uc); +err_rflow: + udma_put_rchan(uc); + + return ret; +} + +static int am62l_bcdma_v2_alloc_chan_resources(struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + struct udma_dev *ud = to_udma_dev(chan->device); + u32 irq_ring_idx; + __be32 addr[2] = {0, 0}; + struct of_phandle_args out_irq; + int ret; + + /* Only TR mode is supported */ + uc->config.pkt_mode = false; + + /* + * Make sure that the completion is in a known state: + * No teardown, the channel is idle + */ + reinit_completion(&uc->teardown_completed); + complete_all(&uc->teardown_completed); + uc->state = UDMA_CHAN_IS_IDLE; + + switch (uc->config.dir) { + case DMA_MEM_TO_MEM: + /* Non synchronized - mem to mem type of transfer */ + dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__, + uc->id); + + ret = am62l_bcdma_v2_alloc_bchan_resources(uc); + if (ret) + return ret; + + irq_ring_idx = ud->match_data->chan_cnt + uc->id; + break; + case DMA_MEM_TO_DEV: + /* Slave transfer synchronized - mem to dev (TX) trasnfer */ + dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__, + uc->id); + + ret = am62l_udma_alloc_tx_resources(uc); + if (ret) { + uc->config.remote_thread_id = -1; + return ret; + } + + uc->config.src_thread = ud->psil_base + uc->tchan->id; + uc->config.dst_thread = uc->config.remote_thread_id; + uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET; + + irq_ring_idx = uc->tchan->id; + + break; + case DMA_DEV_TO_MEM: + /* Slave transfer synchronized - dev to mem (RX) trasnfer */ + dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__, + uc->id); + + ret = am62l_udma_alloc_rx_resources(uc); + if (ret) { + uc->config.remote_thread_id = -1; + return ret; + } + + uc->config.src_thread = uc->config.remote_thread_id; + uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | + K3_PSIL_DST_THREAD_ID_OFFSET; + + irq_ring_idx = uc->rchan->id; + + break; + default: + /* Can not happen */ + dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n", + __func__, uc->id, uc->config.dir); + return -EINVAL; + } + + /* check if the channel configuration was successful */ + if (ret) + goto err_res_free; + + if (udma_is_chan_running(uc)) { + dev_warn(ud->dev, "chan%d: is running!\n", uc->id); + ud->udma_reset_chan(uc, false); + if (udma_is_chan_running(uc)) { + dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); + ret = -EBUSY; + goto err_res_free; + } + } + + uc->dma_dev = dmaengine_get_dma_device(chan); + if (uc->config.dir == DMA_MEM_TO_MEM && !uc->config.tr_trigger_type) { + uc->config.hdesc_size = cppi5_trdesc_calc_size( + sizeof(struct cppi5_tr_type15_t), 2); + + uc->hdesc_pool = dma_pool_create(uc->name, ud->ddev.dev, + uc->config.hdesc_size, + ud->desc_align, + 0); + if (!uc->hdesc_pool) { + dev_err(ud->ddev.dev, + "Descriptor pool allocation failed\n"); + uc->use_dma_pool = false; + ret = -ENOMEM; + goto err_res_free; + } + + uc->use_dma_pool = true; + } else if (uc->config.dir != DMA_MEM_TO_MEM) { + uc->psil_paired = true; + } + + out_irq.np = dev_of_node(ud->dev); + out_irq.args_count = 1; + out_irq.args[0] = irq_ring_idx; + ret = of_irq_parse_raw(addr, &out_irq); + if (ret) + return ret; + + uc->irq_num_ring = irq_create_of_mapping(&out_irq); + + ret = devm_request_irq(ud->dev, uc->irq_num_ring, am62l_udma_ring_irq_handler, + IRQF_TRIGGER_HIGH, uc->name, uc); + if (ret) { + dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id); + goto err_irq_free; + } + + udma_reset_rings(uc); + + INIT_DELAYED_WORK_ONSTACK(&uc->tx_drain.work, + udma_check_tx_completion); + return 0; + +err_irq_free: + uc->irq_num_ring = 0; + uc->irq_num_udma = 0; +err_res_free: + bcdma_free_bchan_resources(uc); + udma_free_tx_resources(uc); + udma_free_rx_resources(uc); + + udma_reset_uchan(uc); + + if (uc->use_dma_pool) { + dma_pool_destroy(uc->hdesc_pool); + uc->use_dma_pool = false; + } + + return ret; +} + +static int am62l_pktdma_v2_alloc_chan_resources(struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + struct udma_dev *ud = to_udma_dev(chan->device); + u32 irq_ring_idx; + __be32 addr[2] = {0, 0}; + struct of_phandle_args out_irq; + int ret; + + /* + * Make sure that the completion is in a known state: + * No teardown, the channel is idle + */ + reinit_completion(&uc->teardown_completed); + complete_all(&uc->teardown_completed); + uc->state = UDMA_CHAN_IS_IDLE; + + switch (uc->config.dir) { + case DMA_MEM_TO_DEV: + /* Slave transfer synchronized - mem to dev (TX) trasnfer */ + dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__, + uc->id); + + ret = am62l_udma_alloc_tx_resources(uc); + if (ret) { + uc->config.remote_thread_id = -1; + return ret; + } + + uc->config.src_thread = ud->psil_base + uc->tchan->id; + uc->config.dst_thread = uc->config.remote_thread_id; + uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET; + + + irq_ring_idx = uc->config.mapped_channel_id; + break; + case DMA_DEV_TO_MEM: + /* Slave transfer synchronized - dev to mem (RX) trasnfer */ + dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__, + uc->id); + + ret = am62l_udma_alloc_rx_resources(uc); + if (ret) { + uc->config.remote_thread_id = -1; + return ret; + } + + uc->config.src_thread = uc->config.remote_thread_id; + uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | + K3_PSIL_DST_THREAD_ID_OFFSET; + + irq_ring_idx = uc->config.mapped_channel_id; + udma_write(uc->rflow->reg_rt, UDMA_RX_FLOWRT_RFA, BIT(28)); + break; + default: + /* Can not happen */ + dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n", + __func__, uc->id, uc->config.dir); + return -EINVAL; + } + + /* check if the channel configuration was successful */ + if (ret) + goto err_res_free; + + if (udma_is_chan_running(uc)) { + dev_warn(ud->dev, "chan%d: is running!\n", uc->id); + ud->udma_reset_chan(uc, false); + if (udma_is_chan_running(uc)) { + dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); + ret = -EBUSY; + goto err_res_free; + } + } + + uc->dma_dev = dmaengine_get_dma_device(chan); + uc->hdesc_pool = dma_pool_create(uc->name, uc->dma_dev, + uc->config.hdesc_size, ud->desc_align, + 0); + if (!uc->hdesc_pool) { + dev_err(ud->ddev.dev, + "Descriptor pool allocation failed\n"); + uc->use_dma_pool = false; + ret = -ENOMEM; + goto err_res_free; + } + + uc->use_dma_pool = true; + + uc->psil_paired = true; + + out_irq.np = dev_of_node(ud->dev); + out_irq.args_count = 1; + out_irq.args[0] = irq_ring_idx; + ret = of_irq_parse_raw(addr, &out_irq); + if (ret) + return ret; + + uc->irq_num_ring = irq_create_of_mapping(&out_irq); + + ret = devm_request_irq(ud->dev, uc->irq_num_ring, am62l_udma_ring_irq_handler, + IRQF_TRIGGER_HIGH, uc->name, uc); + + if (ret) { + dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id); + goto err_irq_free; + } + + uc->irq_num_udma = 0; + + udma_reset_rings(uc); + + INIT_DELAYED_WORK_ONSTACK(&uc->tx_drain.work, + udma_check_tx_completion); + + if (uc->tchan) + dev_dbg(ud->dev, + "chan%d: tchan%d, tflow%d, Remote thread: 0x%04x\n", + uc->id, uc->tchan->id, uc->tchan->tflow_id, + uc->config.remote_thread_id); + else if (uc->rchan) + dev_dbg(ud->dev, + "chan%d: rchan%d, rflow%d, Remote thread: 0x%04x\n", + uc->id, uc->rchan->id, uc->rflow->id, + uc->config.remote_thread_id); + return 0; + +err_irq_free: + uc->irq_num_ring = 0; +err_res_free: + udma_free_tx_resources(uc); + udma_free_rx_resources(uc); + + udma_reset_uchan(uc); + + dma_pool_destroy(uc->hdesc_pool); + uc->use_dma_pool = false; + + return ret; +} + +static enum dma_status am62l_udma_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct udma_chan *uc = to_udma_chan(chan); + enum dma_status ret; + unsigned long flags; + + spin_lock_irqsave(&uc->vc.lock, flags); + + ret = dma_cookie_status(chan, cookie, txstate); + + if (!udma_is_chan_running(uc)) + ret = DMA_COMPLETE; + + if (ret == DMA_IN_PROGRESS && am62l_udma_is_chan_paused(uc)) + ret = DMA_PAUSED; + + if (ret == DMA_COMPLETE || !txstate) + goto out; + + if (uc->desc && uc->desc->vd.tx.cookie == cookie) { + u32 peer_bcnt = 0; + u32 bcnt = 0; + u32 residue = uc->desc->residue; + u32 delay = 0; + + if (uc->desc->dir == DMA_MEM_TO_DEV) { + bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_SBCNT_REG); + + if (uc->config.ep_type != PSIL_EP_NATIVE) { + peer_bcnt = udma_chanrt_read(uc, 0x810); + + if (bcnt > peer_bcnt) + delay = bcnt - peer_bcnt; + } + } else if (uc->desc->dir == DMA_DEV_TO_MEM) { + bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG); + + if (uc->config.ep_type != PSIL_EP_NATIVE) { + peer_bcnt = udma_chanrt_read(uc, 0x810); + + if (peer_bcnt > bcnt) + delay = peer_bcnt - bcnt; + } + } else { + bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG); + } + + if (bcnt && !(bcnt % uc->desc->residue)) + residue = 0; + else + residue -= bcnt % uc->desc->residue; + + if (!residue && (uc->config.dir == DMA_DEV_TO_MEM || !delay)) { + ret = DMA_COMPLETE; + delay = 0; + } + + dma_set_residue(txstate, residue); + dma_set_in_flight_bytes(txstate, delay); + + } else { + ret = DMA_COMPLETE; + } + +out: + spin_unlock_irqrestore(&uc->vc.lock, flags); + return ret; +} + +static int am62l_udma_pause(struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + + /* pause the channel */ + udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_PAUSE, UDMA_CHAN_RT_CTL_PAUSE); + + return 0; +} + +static int am62l_udma_resume(struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + + /* resume the channel */ + udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_PAUSE, 0); + + return 0; +} + +static struct platform_driver am62l_bcdma_v2_driver; +static struct platform_driver am62l_pktdma_v2_driver; + +static bool am62l_udma_dma_filter_fn(struct dma_chan *chan, void *param) +{ + struct udma_chan_config *ucc; + struct psil_endpoint_config *ep_config; + struct am62l_udma_filter_param *filter_param; + struct udma_chan *uc; + struct udma_dev *ud; + + if (chan->device->dev->driver != &am62l_bcdma_v2_driver.driver && + chan->device->dev->driver != &am62l_pktdma_v2_driver.driver) + return false; + + uc = to_udma_chan(chan); + ucc = &uc->config; + ud = uc->ud; + filter_param = param; + + if (filter_param->asel > 15) { + dev_err(ud->dev, "Invalid channel asel: %u\n", + filter_param->asel); + return false; + } + + ucc->remote_thread_id = filter_param->remote_thread_id; + ucc->asel = filter_param->asel; + ucc->tr_trigger_type = filter_param->tr_trigger_type; + + if (ucc->tr_trigger_type) { + ucc->dir = DMA_MEM_TO_MEM; + goto triggered_bchan; + } else if (ucc->remote_thread_id & K3_PSIL_DST_THREAD_ID_OFFSET) { + ucc->dir = DMA_MEM_TO_DEV; + } else { + ucc->dir = DMA_DEV_TO_MEM; + } + + ep_config = psil_get_ep_config(ucc->remote_thread_id); + if (IS_ERR(ep_config)) { + dev_err(ud->dev, "No configuration for psi-l thread 0x%04x\n", + ucc->remote_thread_id); + ucc->dir = DMA_MEM_TO_MEM; + ucc->remote_thread_id = -1; + ucc->atype = 0; + ucc->asel = 0; + return false; + } + + ucc->pkt_mode = ep_config->pkt_mode; + ucc->channel_tpl = ep_config->channel_tpl; + ucc->notdpkt = ep_config->notdpkt; + ucc->ep_type = ep_config->ep_type; + + if ((ud->match_data->type >= DMA_TYPE_BCDMA_V2) && + ep_config->mapped_channel_id >= 0) { + ucc->mapped_channel_id = ep_config->mapped_channel_id; + ucc->default_flow_id = ep_config->default_flow_id; + } else { + ucc->mapped_channel_id = -1; + ucc->default_flow_id = -1; + } + + ucc->needs_epib = ep_config->needs_epib; + ucc->psd_size = ep_config->psd_size; + ucc->metadata_size = + (ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) + + ucc->psd_size; + + if (ucc->ep_type != PSIL_EP_NATIVE) { + const struct udma_match_data *match_data = ud->match_data; + + if ((match_data->flags & UDMA_FLAG_PDMA_ACC32) && (ep_config->pdma_acc32)) + ucc->enable_acc32 = true; + else + ucc->enable_acc32 = false; + + if ((match_data->flags & UDMA_FLAG_PDMA_BURST) && (ep_config->pdma_burst)) + ucc->enable_burst = true; + else + ucc->enable_burst = false; + } + if (ucc->pkt_mode) + ucc->hdesc_size = ALIGN(sizeof(struct cppi5_host_desc_t) + + ucc->metadata_size, ud->desc_align); + + dev_dbg(ud->dev, "chan%d: Remote thread: 0x%04x (%s)\n", uc->id, + ucc->remote_thread_id, dmaengine_get_direction_text(ucc->dir)); + + return true; + +triggered_bchan: + dev_dbg(ud->dev, "chan%d: triggered channel (type: %u)\n", uc->id, + ucc->tr_trigger_type); + + return true; +} + +static struct dma_chan *am62l_udma_of_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct udma_dev *ud = ofdma->of_dma_data; + dma_cap_mask_t mask = ud->ddev.cap_mask; + struct am62l_udma_filter_param filter_param; + struct dma_chan *chan; + + if (ud->match_data->type == DMA_TYPE_BCDMA_V2) { + if (dma_spec->args_count != 4) + return NULL; + + filter_param.tr_trigger_type = dma_spec->args[0]; + filter_param.trigger_param = dma_spec->args[1]; + filter_param.remote_thread_id = dma_spec->args[2]; + filter_param.asel = dma_spec->args[3]; + } else { + if (dma_spec->args_count != 1 && dma_spec->args_count != 2) + return NULL; + + filter_param.remote_thread_id = dma_spec->args[0]; + filter_param.tr_trigger_type = 0; + if (dma_spec->args_count == 2) + filter_param.asel = dma_spec->args[1]; + else + filter_param.asel = 0; + } + + chan = __dma_request_channel(&mask, am62l_udma_dma_filter_fn, &filter_param, + ofdma->of_node); + if (!chan) { + dev_err(ud->dev, "get channel fail in %s.\n", __func__); + return ERR_PTR(-EINVAL); + } + + return chan; +} + +static struct udma_match_data am62l_bcdma_v2_data = { + .type = DMA_TYPE_BCDMA_V2, + .psil_base = 0x2000, /* for tchan and rchan, not applicable to bchan */ + .enable_memcpy_support = true, /* Supported via bchan */ + .flags = UDMA_FLAGS_J7_CLASS, + .statictr_z_mask = GENMASK(23, 0), + .burst_size = { + TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */ + 0, /* No H Channels */ + 0, /* No UH Channels */ + }, + .bchan_cnt = 16, + .chan_cnt = 128, + .tchan_cnt = 128, + .rchan_cnt = 128, +}; + +static struct udma_match_data am62l_pktdma_v2_data = { + .type = DMA_TYPE_PKTDMA_V2, + .psil_base = 0x1000, + .enable_memcpy_support = false, /* PKTDMA does not support MEM_TO_MEM */ + .flags = UDMA_FLAGS_J7_CLASS, + .statictr_z_mask = GENMASK(23, 0), + .burst_size = { + TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */ + 0, /* No H Channels */ + 0, /* No UH Channels */ + }, + .tchan_cnt = 97, + .rchan_cnt = 97, + .chan_cnt = 97, + .tflow_cnt = 112, + .rflow_cnt = 112, +}; + +static const struct of_device_id udma_of_match[] = { + { + .compatible = "ti,am62l-dmss-bcdma", + .data = &am62l_bcdma_v2_data, + }, + { + .compatible = "ti,am62l-dmss-pktdma", + .data = &am62l_pktdma_v2_data, + }, + { /* Sentinel */ }, +}; + +static const struct soc_device_attribute k3_soc_devices[] = { + { .family = "AM62LX", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, udma_of_match); + +static int am62l_udma_get_mmrs(struct platform_device *pdev, struct udma_dev *ud) +{ + int i; + + ud->mmrs[AM62L_MMR_GCFG] = devm_platform_ioremap_resource_byname(pdev, + am62l_mmr_names[AM62L_MMR_GCFG]); + if (IS_ERR(ud->mmrs[AM62L_MMR_GCFG])) + return PTR_ERR(ud->mmrs[AM62L_MMR_GCFG]); + + /* There are no tchan and rchan in BCDMA_V2 and PKTDMA_V2. + * Duplicate chan as tchan and rchan to keep the common code + * in k3-udma-common.c functional. + */ + if (ud->match_data->type == DMA_TYPE_BCDMA_V2) { + ud->bchan_cnt = ud->match_data->bchan_cnt; + ud->chan_cnt = ud->match_data->chan_cnt; + ud->tchan_cnt = ud->match_data->chan_cnt; + ud->rchan_cnt = ud->match_data->chan_cnt; + ud->rflow_cnt = ud->chan_cnt; + } else if (ud->match_data->type == DMA_TYPE_PKTDMA_V2) { + ud->chan_cnt = ud->match_data->chan_cnt; + ud->tchan_cnt = ud->match_data->tchan_cnt; + ud->rchan_cnt = ud->match_data->rchan_cnt; + ud->rflow_cnt = ud->match_data->rflow_cnt; + } + + for (i = 1; i < AM62L_MMR_LAST; i++) { + if (i == AM62L_MMR_BCHANRT && ud->bchan_cnt == 0) + continue; + if (i == AM62L_MMR_CHANRT && ud->chan_cnt == 0) + continue; + + ud->mmrs[i] = devm_platform_ioremap_resource_byname(pdev, am62l_mmr_names[i]); + if (IS_ERR(ud->mmrs[i])) + return PTR_ERR(ud->mmrs[i]); + } + + return 0; +} + +static int am62l_udma_probe(struct platform_device *pdev) +{ + const struct soc_device_attribute *soc; + struct device *dev = &pdev->dev; + struct udma_dev *ud; + const struct of_device_id *match; + int i, ret; + int ch_count; + + ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(48)); + if (ret) + dev_err(dev, "failed to set dma mask stuff\n"); + + ud = devm_kzalloc(dev, sizeof(*ud), GFP_KERNEL); + if (!ud) + return -ENOMEM; + + match = of_match_node(udma_of_match, dev->of_node); + if (!match) { + dev_err(dev, "No compatible match found\n"); + return -ENODEV; + } + ud->match_data = match->data; + + ud->soc_data = ud->match_data->soc_data; + if (!ud->soc_data) { + soc = soc_device_match(k3_soc_devices); + if (!soc) { + dev_err(dev, "No compatible SoC found\n"); + return -ENODEV; + } + ud->soc_data = soc->data; + } + // Setup function pointers + ud->udma_start = am62l_udma_start; + ud->udma_stop = am62l_udma_stop; + ud->udma_reset_chan = am62l_udma_reset_chan; + ud->udma_is_desc_really_done = am62l_udma_is_desc_really_done; + ud->udma_decrement_byte_counters = am62l_udma_decrement_byte_counters; + + ret = am62l_udma_get_mmrs(pdev, ud); + if (ret) + return ret; + + struct k3_ringacc_init_data ring_init_data = {0}; + + if (ud->match_data->type == DMA_TYPE_BCDMA_V2) { + ring_init_data.num_rings = ud->bchan_cnt + ud->chan_cnt; + } else if (ud->match_data->type == DMA_TYPE_PKTDMA_V2) { + ring_init_data.num_rings = ud->rflow_cnt; + + ud->rflow_rt = devm_platform_ioremap_resource_byname(pdev, "ringrt"); + ring_init_data.base_rt = ud->rflow_rt; + } + + ud->ringacc = k3_ringacc_dmarings_init(pdev, &ring_init_data); + + if (IS_ERR(ud->ringacc)) + return PTR_ERR(ud->ringacc); + + dma_cap_set(DMA_SLAVE, ud->ddev.cap_mask); + + if (ud->match_data->type != DMA_TYPE_PKTDMA_V2) { + dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask); + ud->ddev.device_prep_dma_cyclic = udma_prep_dma_cyclic; + } + + ud->ddev.device_config = udma_slave_config; + ud->ddev.device_prep_slave_sg = udma_prep_slave_sg; + ud->ddev.device_issue_pending = udma_issue_pending; + ud->ddev.device_tx_status = am62l_udma_tx_status; + ud->ddev.device_pause = am62l_udma_pause; + ud->ddev.device_resume = am62l_udma_resume; + ud->ddev.device_terminate_all = udma_terminate_all; + ud->ddev.device_synchronize = udma_synchronize; +#ifdef CONFIG_DEBUG_FS + ud->ddev.dbg_summary_show = udma_dbg_summary_show; +#endif + + switch (ud->match_data->type) { + case DMA_TYPE_BCDMA_V2: + ud->ddev.device_alloc_chan_resources = + am62l_bcdma_v2_alloc_chan_resources; + break; + case DMA_TYPE_PKTDMA_V2: + ud->ddev.device_alloc_chan_resources = + am62l_pktdma_v2_alloc_chan_resources; + break; + default: + return -EINVAL; + } + + ud->ddev.device_free_chan_resources = udma_free_chan_resources; + + ud->ddev.src_addr_widths = TI_UDMAC_BUSWIDTHS; + ud->ddev.dst_addr_widths = TI_UDMAC_BUSWIDTHS; + ud->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); + ud->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; + ud->ddev.desc_metadata_modes = DESC_METADATA_CLIENT | + DESC_METADATA_ENGINE; + if (ud->match_data->enable_memcpy_support && + !(ud->match_data->type == DMA_TYPE_BCDMA && ud->bchan_cnt == 0)) { + dma_cap_set(DMA_MEMCPY, ud->ddev.cap_mask); + ud->ddev.device_prep_dma_memcpy = udma_prep_dma_memcpy; + ud->ddev.directions |= BIT(DMA_MEM_TO_MEM); + } + + ud->ddev.dev = dev; + ud->dev = dev; + ud->psil_base = ud->match_data->psil_base; + + INIT_LIST_HEAD(&ud->ddev.channels); + INIT_LIST_HEAD(&ud->desc_to_purge); + + ch_count = setup_resources(ud); + if (ch_count <= 0) + return ch_count; + + spin_lock_init(&ud->lock); + INIT_WORK(&ud->purge_work, udma_purge_desc_work); + + ud->desc_align = 64; + if (ud->desc_align < dma_get_cache_alignment()) + ud->desc_align = dma_get_cache_alignment(); + + ret = udma_setup_rx_flush(ud); + if (ret) + return ret; + + for (i = 0; i < ud->bchan_cnt; i++) { + struct udma_bchan *bchan = &ud->bchans[i]; + + bchan->id = i; + bchan->reg_rt = ud->mmrs[AM62L_MMR_BCHANRT] + i * 0x1000; + } + + for (i = 0; i < ud->tchan_cnt; i++) { + struct udma_tchan *tchan = &ud->tchans[i]; + + tchan->id = i; + tchan->reg_rt = ud->mmrs[AM62L_MMR_CHANRT] + i * 0x1000; + } + + for (i = 0; i < ud->rchan_cnt; i++) { + struct udma_rchan *rchan = &ud->rchans[i]; + + rchan->id = i; + rchan->reg_rt = ud->mmrs[AM62L_MMR_CHANRT] + i * 0x1000; + } + + for (i = 0; i < ud->rflow_cnt; i++) { + struct udma_rflow *rflow = &ud->rflows[i]; + + rflow->id = i; + rflow->reg_rt = ud->rflow_rt + i * 0x2000; + } + + for (i = 0; i < ch_count; i++) { + struct udma_chan *uc = &ud->channels[i]; + + uc->ud = ud; + uc->vc.desc_free = udma_desc_free; + uc->id = i; + uc->bchan = NULL; + uc->tchan = NULL; + uc->rchan = NULL; + uc->config.remote_thread_id = -1; + uc->config.mapped_channel_id = -1; + uc->config.default_flow_id = -1; + uc->config.dir = DMA_MEM_TO_MEM; + uc->name = devm_kasprintf(dev, GFP_KERNEL, "%s chan%d", + dev_name(dev), i); + + vchan_init(&uc->vc, &ud->ddev); + /* Use custom vchan completion handling */ + tasklet_setup(&uc->vc.task, udma_vchan_complete); + init_completion(&uc->teardown_completed); + INIT_DELAYED_WORK(&uc->tx_drain.work, udma_check_tx_completion); + } + + /* Configure the copy_align to the maximum burst size the device supports */ + ud->ddev.copy_align = udma_get_copy_align(ud); + + ret = dma_async_device_register(&ud->ddev); + if (ret) { + dev_err(dev, "failed to register slave DMA engine: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, ud); + + ret = of_dma_controller_register(dev->of_node, am62l_udma_of_xlate, ud); + if (ret) { + dev_err(dev, "failed to register of_dma controller\n"); + dma_async_device_unregister(&ud->ddev); + } + + return ret; +} + +static int __maybe_unused am62l_udma_pm_suspend(struct device *dev) +{ + struct udma_dev *ud = dev_get_drvdata(dev); + struct dma_device *dma_dev = &ud->ddev; + struct dma_chan *chan; + struct udma_chan *uc; + + list_for_each_entry(chan, &dma_dev->channels, device_node) { + if (chan->client_count) { + uc = to_udma_chan(chan); + /* backup the channel configuration */ + memcpy(&uc->backup_config, &uc->config, + sizeof(struct udma_chan_config)); + dev_dbg(dev, "Suspending channel %s\n", + dma_chan_name(chan)); + ud->ddev.device_free_chan_resources(chan); + } + } + + return 0; +} + +static int __maybe_unused am62l_udma_pm_resume(struct device *dev) +{ + struct udma_dev *ud = dev_get_drvdata(dev); + struct dma_device *dma_dev = &ud->ddev; + struct dma_chan *chan; + struct udma_chan *uc; + int ret; + + list_for_each_entry(chan, &dma_dev->channels, device_node) { + if (chan->client_count) { + uc = to_udma_chan(chan); + /* restore the channel configuration */ + memcpy(&uc->config, &uc->backup_config, + sizeof(struct udma_chan_config)); + dev_dbg(dev, "Resuming channel %s\n", + dma_chan_name(chan)); + ret = ud->ddev.device_alloc_chan_resources(chan); + if (ret) + return ret; + } + } + + return 0; +} + +static const struct dev_pm_ops udma_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(am62l_udma_pm_suspend, am62l_udma_pm_resume) +}; + +static struct platform_driver am62l_bcdma_v2_driver = { + .driver = { + .name = "ti-udma-am62l", + .of_match_table = udma_of_match, + .suppress_bind_attrs = true, + .pm = &udma_pm_ops, + }, + .probe = am62l_udma_probe, +}; + +module_platform_driver(am62l_bcdma_v2_driver); +MODULE_DESCRIPTION("Texas Instruments K3 AM62L UDMA support"); +MODULE_LICENSE("GPL"); + diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/dma/ti/k3-udma.c v_kernel/drivers/dma/ti/k3-udma.c --- linux-6.12.57/drivers/dma/ti/k3-udma.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/dma/ti/k3-udma.c 2026-04-21 11:35:36.146935210 +0200 @@ -33,43 +33,6 @@ #include "k3-udma.h" #include "k3-psil-priv.h" -struct udma_static_tr { - u8 elsize; /* RPSTR0 */ - u16 elcnt; /* RPSTR0 */ - u16 bstcnt; /* RPSTR1 */ -}; - -#define K3_UDMA_MAX_RFLOWS 1024 -#define K3_UDMA_DEFAULT_RING_SIZE 16 - -/* How SRC/DST tag should be updated by UDMA in the descriptor's Word 3 */ -#define UDMA_RFLOW_SRCTAG_NONE 0 -#define UDMA_RFLOW_SRCTAG_CFG_TAG 1 -#define UDMA_RFLOW_SRCTAG_FLOW_ID 2 -#define UDMA_RFLOW_SRCTAG_SRC_TAG 4 - -#define UDMA_RFLOW_DSTTAG_NONE 0 -#define UDMA_RFLOW_DSTTAG_CFG_TAG 1 -#define UDMA_RFLOW_DSTTAG_FLOW_ID 2 -#define UDMA_RFLOW_DSTTAG_DST_TAG_LO 4 -#define UDMA_RFLOW_DSTTAG_DST_TAG_HI 5 - -struct udma_chan; - -enum k3_dma_type { - DMA_TYPE_UDMA = 0, - DMA_TYPE_BCDMA, - DMA_TYPE_PKTDMA, -}; - -enum udma_mmr { - MMR_GCFG = 0, - MMR_BCHANRT, - MMR_RCHANRT, - MMR_TCHANRT, - MMR_LAST, -}; - static const char * const mmr_names[] = { [MMR_GCFG] = "gcfg", [MMR_BCHANRT] = "bchanrt", @@ -77,329 +40,7 @@ [MMR_TCHANRT] = "tchanrt", }; -struct udma_tchan { - void __iomem *reg_rt; - - int id; - struct k3_ring *t_ring; /* Transmit ring */ - struct k3_ring *tc_ring; /* Transmit Completion ring */ - int tflow_id; /* applicable only for PKTDMA */ - -}; - -#define udma_bchan udma_tchan - -struct udma_rflow { - int id; - struct k3_ring *fd_ring; /* Free Descriptor ring */ - struct k3_ring *r_ring; /* Receive ring */ -}; - -struct udma_rchan { - void __iomem *reg_rt; - - int id; -}; - -struct udma_oes_offsets { - /* K3 UDMA Output Event Offset */ - u32 udma_rchan; - - /* BCDMA Output Event Offsets */ - u32 bcdma_bchan_data; - u32 bcdma_bchan_ring; - u32 bcdma_tchan_data; - u32 bcdma_tchan_ring; - u32 bcdma_rchan_data; - u32 bcdma_rchan_ring; - - /* PKTDMA Output Event Offsets */ - u32 pktdma_tchan_flow; - u32 pktdma_rchan_flow; -}; - -#define UDMA_FLAG_PDMA_ACC32 BIT(0) -#define UDMA_FLAG_PDMA_BURST BIT(1) -#define UDMA_FLAG_TDTYPE BIT(2) -#define UDMA_FLAG_BURST_SIZE BIT(3) -#define UDMA_FLAGS_J7_CLASS (UDMA_FLAG_PDMA_ACC32 | \ - UDMA_FLAG_PDMA_BURST | \ - UDMA_FLAG_TDTYPE | \ - UDMA_FLAG_BURST_SIZE) - -struct udma_match_data { - enum k3_dma_type type; - u32 psil_base; - bool enable_memcpy_support; - u32 flags; - u32 statictr_z_mask; - u8 burst_size[3]; - struct udma_soc_data *soc_data; -}; - -struct udma_soc_data { - struct udma_oes_offsets oes; - u32 bcdma_trigger_event_offset; -}; - -struct udma_hwdesc { - size_t cppi5_desc_size; - void *cppi5_desc_vaddr; - dma_addr_t cppi5_desc_paddr; - - /* TR descriptor internal pointers */ - void *tr_req_base; - struct cppi5_tr_resp_t *tr_resp_base; -}; - -struct udma_rx_flush { - struct udma_hwdesc hwdescs[2]; - - size_t buffer_size; - void *buffer_vaddr; - dma_addr_t buffer_paddr; -}; - -struct udma_tpl { - u8 levels; - u32 start_idx[3]; -}; - -struct udma_dev { - struct dma_device ddev; - struct device *dev; - void __iomem *mmrs[MMR_LAST]; - const struct udma_match_data *match_data; - const struct udma_soc_data *soc_data; - - struct udma_tpl bchan_tpl; - struct udma_tpl tchan_tpl; - struct udma_tpl rchan_tpl; - - size_t desc_align; /* alignment to use for descriptors */ - - struct udma_tisci_rm tisci_rm; - - struct k3_ringacc *ringacc; - - struct work_struct purge_work; - struct list_head desc_to_purge; - spinlock_t lock; - - struct udma_rx_flush rx_flush; - - int bchan_cnt; - int tchan_cnt; - int echan_cnt; - int rchan_cnt; - int rflow_cnt; - int tflow_cnt; - unsigned long *bchan_map; - unsigned long *tchan_map; - unsigned long *rchan_map; - unsigned long *rflow_gp_map; - unsigned long *rflow_gp_map_allocated; - unsigned long *rflow_in_use; - unsigned long *tflow_map; - - struct udma_bchan *bchans; - struct udma_tchan *tchans; - struct udma_rchan *rchans; - struct udma_rflow *rflows; - - struct udma_chan *channels; - u32 psil_base; - u32 atype; - u32 asel; -}; - -struct udma_desc { - struct virt_dma_desc vd; - - bool terminated; - - enum dma_transfer_direction dir; - - struct udma_static_tr static_tr; - u32 residue; - - unsigned int sglen; - unsigned int desc_idx; /* Only used for cyclic in packet mode */ - unsigned int tr_idx; - - u32 metadata_size; - void *metadata; /* pointer to provided metadata buffer (EPIP, PSdata) */ - - unsigned int hwdesc_count; - struct udma_hwdesc hwdesc[]; -}; - -enum udma_chan_state { - UDMA_CHAN_IS_IDLE = 0, /* not active, no teardown is in progress */ - UDMA_CHAN_IS_ACTIVE, /* Normal operation */ - UDMA_CHAN_IS_TERMINATING, /* channel is being terminated */ -}; - -struct udma_tx_drain { - struct delayed_work work; - ktime_t tstamp; - u32 residue; -}; - -struct udma_chan_config { - bool pkt_mode; /* TR or packet */ - bool needs_epib; /* EPIB is needed for the communication or not */ - u32 psd_size; /* size of Protocol Specific Data */ - u32 metadata_size; /* (needs_epib ? 16:0) + psd_size */ - u32 hdesc_size; /* Size of a packet descriptor in packet mode */ - bool notdpkt; /* Suppress sending TDC packet */ - int remote_thread_id; - u32 atype; - u32 asel; - u32 src_thread; - u32 dst_thread; - enum psil_endpoint_type ep_type; - bool enable_acc32; - bool enable_burst; - enum udma_tp_level channel_tpl; /* Channel Throughput Level */ - - u32 tr_trigger_type; - unsigned long tx_flags; - - /* PKDMA mapped channel */ - int mapped_channel_id; - /* PKTDMA default tflow or rflow for mapped channel */ - int default_flow_id; - - enum dma_transfer_direction dir; -}; - -struct udma_chan { - struct virt_dma_chan vc; - struct dma_slave_config cfg; - struct udma_dev *ud; - struct device *dma_dev; - struct udma_desc *desc; - struct udma_desc *terminated_desc; - struct udma_static_tr static_tr; - char *name; - - struct udma_bchan *bchan; - struct udma_tchan *tchan; - struct udma_rchan *rchan; - struct udma_rflow *rflow; - - bool psil_paired; - - int irq_num_ring; - int irq_num_udma; - - bool cyclic; - bool paused; - - enum udma_chan_state state; - struct completion teardown_completed; - - struct udma_tx_drain tx_drain; - - /* Channel configuration parameters */ - struct udma_chan_config config; - /* Channel configuration parameters (backup) */ - struct udma_chan_config backup_config; - - /* dmapool for packet mode descriptors */ - bool use_dma_pool; - struct dma_pool *hdesc_pool; - - u32 id; -}; - -static inline struct udma_dev *to_udma_dev(struct dma_device *d) -{ - return container_of(d, struct udma_dev, ddev); -} - -static inline struct udma_chan *to_udma_chan(struct dma_chan *c) -{ - return container_of(c, struct udma_chan, vc.chan); -} - -static inline struct udma_desc *to_udma_desc(struct dma_async_tx_descriptor *t) -{ - return container_of(t, struct udma_desc, vd.tx); -} - -/* Generic register access functions */ -static inline u32 udma_read(void __iomem *base, int reg) -{ - return readl(base + reg); -} - -static inline void udma_write(void __iomem *base, int reg, u32 val) -{ - writel(val, base + reg); -} - -static inline void udma_update_bits(void __iomem *base, int reg, - u32 mask, u32 val) -{ - u32 tmp, orig; - - orig = readl(base + reg); - tmp = orig & ~mask; - tmp |= (val & mask); - - if (tmp != orig) - writel(tmp, base + reg); -} - -/* TCHANRT */ -static inline u32 udma_tchanrt_read(struct udma_chan *uc, int reg) -{ - if (!uc->tchan) - return 0; - return udma_read(uc->tchan->reg_rt, reg); -} - -static inline void udma_tchanrt_write(struct udma_chan *uc, int reg, u32 val) -{ - if (!uc->tchan) - return; - udma_write(uc->tchan->reg_rt, reg, val); -} - -static inline void udma_tchanrt_update_bits(struct udma_chan *uc, int reg, - u32 mask, u32 val) -{ - if (!uc->tchan) - return; - udma_update_bits(uc->tchan->reg_rt, reg, mask, val); -} - -/* RCHANRT */ -static inline u32 udma_rchanrt_read(struct udma_chan *uc, int reg) -{ - if (!uc->rchan) - return 0; - return udma_read(uc->rchan->reg_rt, reg); -} - -static inline void udma_rchanrt_write(struct udma_chan *uc, int reg, u32 val) -{ - if (!uc->rchan) - return; - udma_write(uc->rchan->reg_rt, reg, val); -} - -static inline void udma_rchanrt_update_bits(struct udma_chan *uc, int reg, - u32 mask, u32 val) -{ - if (!uc->rchan) - return; - udma_update_bits(uc->rchan->reg_rt, reg, mask, val); -} - -static int navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread) +int navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread) { struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; @@ -409,7 +50,7 @@ src_thread, dst_thread); } -static int navss_psil_unpair(struct udma_dev *ud, u32 src_thread, +int navss_psil_unpair(struct udma_dev *ud, u32 src_thread, u32 dst_thread) { struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; @@ -420,202 +61,6 @@ src_thread, dst_thread); } -static void k3_configure_chan_coherency(struct dma_chan *chan, u32 asel) -{ - struct device *chan_dev = &chan->dev->device; - - if (asel == 0) { - /* No special handling for the channel */ - chan->dev->chan_dma_dev = false; - - chan_dev->dma_coherent = false; - chan_dev->dma_parms = NULL; - } else if (asel == 14 || asel == 15) { - chan->dev->chan_dma_dev = true; - - chan_dev->dma_coherent = true; - dma_coerce_mask_and_coherent(chan_dev, DMA_BIT_MASK(48)); - chan_dev->dma_parms = chan_dev->parent->dma_parms; - } else { - dev_warn(chan->device->dev, "Invalid ASEL value: %u\n", asel); - - chan_dev->dma_coherent = false; - chan_dev->dma_parms = NULL; - } -} - -static u8 udma_get_chan_tpl_index(struct udma_tpl *tpl_map, int chan_id) -{ - int i; - - for (i = 0; i < tpl_map->levels; i++) { - if (chan_id >= tpl_map->start_idx[i]) - return i; - } - - return 0; -} - -static void udma_reset_uchan(struct udma_chan *uc) -{ - memset(&uc->config, 0, sizeof(uc->config)); - uc->config.remote_thread_id = -1; - uc->config.mapped_channel_id = -1; - uc->config.default_flow_id = -1; - uc->state = UDMA_CHAN_IS_IDLE; -} - -static void udma_dump_chan_stdata(struct udma_chan *uc) -{ - struct device *dev = uc->ud->dev; - u32 offset; - int i; - - if (uc->config.dir == DMA_MEM_TO_DEV || uc->config.dir == DMA_MEM_TO_MEM) { - dev_dbg(dev, "TCHAN State data:\n"); - for (i = 0; i < 32; i++) { - offset = UDMA_CHAN_RT_STDATA_REG + i * 4; - dev_dbg(dev, "TRT_STDATA[%02d]: 0x%08x\n", i, - udma_tchanrt_read(uc, offset)); - } - } - - if (uc->config.dir == DMA_DEV_TO_MEM || uc->config.dir == DMA_MEM_TO_MEM) { - dev_dbg(dev, "RCHAN State data:\n"); - for (i = 0; i < 32; i++) { - offset = UDMA_CHAN_RT_STDATA_REG + i * 4; - dev_dbg(dev, "RRT_STDATA[%02d]: 0x%08x\n", i, - udma_rchanrt_read(uc, offset)); - } - } -} - -static inline dma_addr_t udma_curr_cppi5_desc_paddr(struct udma_desc *d, - int idx) -{ - return d->hwdesc[idx].cppi5_desc_paddr; -} - -static inline void *udma_curr_cppi5_desc_vaddr(struct udma_desc *d, int idx) -{ - return d->hwdesc[idx].cppi5_desc_vaddr; -} - -static struct udma_desc *udma_udma_desc_from_paddr(struct udma_chan *uc, - dma_addr_t paddr) -{ - struct udma_desc *d = uc->terminated_desc; - - if (d) { - dma_addr_t desc_paddr = udma_curr_cppi5_desc_paddr(d, - d->desc_idx); - - if (desc_paddr != paddr) - d = NULL; - } - - if (!d) { - d = uc->desc; - if (d) { - dma_addr_t desc_paddr = udma_curr_cppi5_desc_paddr(d, - d->desc_idx); - - if (desc_paddr != paddr) - d = NULL; - } - } - - return d; -} - -static void udma_free_hwdesc(struct udma_chan *uc, struct udma_desc *d) -{ - if (uc->use_dma_pool) { - int i; - - for (i = 0; i < d->hwdesc_count; i++) { - if (!d->hwdesc[i].cppi5_desc_vaddr) - continue; - - dma_pool_free(uc->hdesc_pool, - d->hwdesc[i].cppi5_desc_vaddr, - d->hwdesc[i].cppi5_desc_paddr); - - d->hwdesc[i].cppi5_desc_vaddr = NULL; - } - } else if (d->hwdesc[0].cppi5_desc_vaddr) { - dma_free_coherent(uc->dma_dev, d->hwdesc[0].cppi5_desc_size, - d->hwdesc[0].cppi5_desc_vaddr, - d->hwdesc[0].cppi5_desc_paddr); - - d->hwdesc[0].cppi5_desc_vaddr = NULL; - } -} - -static void udma_purge_desc_work(struct work_struct *work) -{ - struct udma_dev *ud = container_of(work, typeof(*ud), purge_work); - struct virt_dma_desc *vd, *_vd; - unsigned long flags; - LIST_HEAD(head); - - spin_lock_irqsave(&ud->lock, flags); - list_splice_tail_init(&ud->desc_to_purge, &head); - spin_unlock_irqrestore(&ud->lock, flags); - - list_for_each_entry_safe(vd, _vd, &head, node) { - struct udma_chan *uc = to_udma_chan(vd->tx.chan); - struct udma_desc *d = to_udma_desc(&vd->tx); - - udma_free_hwdesc(uc, d); - list_del(&vd->node); - kfree(d); - } - - /* If more to purge, schedule the work again */ - if (!list_empty(&ud->desc_to_purge)) - schedule_work(&ud->purge_work); -} - -static void udma_desc_free(struct virt_dma_desc *vd) -{ - struct udma_dev *ud = to_udma_dev(vd->tx.chan->device); - struct udma_chan *uc = to_udma_chan(vd->tx.chan); - struct udma_desc *d = to_udma_desc(&vd->tx); - unsigned long flags; - - if (uc->terminated_desc == d) - uc->terminated_desc = NULL; - - if (uc->use_dma_pool) { - udma_free_hwdesc(uc, d); - kfree(d); - return; - } - - spin_lock_irqsave(&ud->lock, flags); - list_add_tail(&vd->node, &ud->desc_to_purge); - spin_unlock_irqrestore(&ud->lock, flags); - - schedule_work(&ud->purge_work); -} - -static bool udma_is_chan_running(struct udma_chan *uc) -{ - u32 trt_ctl = 0; - u32 rrt_ctl = 0; - - if (uc->tchan) - trt_ctl = udma_tchanrt_read(uc, UDMA_CHAN_RT_CTL_REG); - if (uc->rchan) - rrt_ctl = udma_rchanrt_read(uc, UDMA_CHAN_RT_CTL_REG); - - if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN) - return true; - - return false; -} - static bool udma_is_chan_paused(struct udma_chan *uc) { u32 val, pause_mask; @@ -643,122 +88,6 @@ return false; } -static inline dma_addr_t udma_get_rx_flush_hwdesc_paddr(struct udma_chan *uc) -{ - return uc->ud->rx_flush.hwdescs[uc->config.pkt_mode].cppi5_desc_paddr; -} - -static int udma_push_to_ring(struct udma_chan *uc, int idx) -{ - struct udma_desc *d = uc->desc; - struct k3_ring *ring = NULL; - dma_addr_t paddr; - - switch (uc->config.dir) { - case DMA_DEV_TO_MEM: - ring = uc->rflow->fd_ring; - break; - case DMA_MEM_TO_DEV: - case DMA_MEM_TO_MEM: - ring = uc->tchan->t_ring; - break; - default: - return -EINVAL; - } - - /* RX flush packet: idx == -1 is only passed in case of DEV_TO_MEM */ - if (idx == -1) { - paddr = udma_get_rx_flush_hwdesc_paddr(uc); - } else { - paddr = udma_curr_cppi5_desc_paddr(d, idx); - - wmb(); /* Ensure that writes are not moved over this point */ - } - - return k3_ringacc_ring_push(ring, &paddr); -} - -static bool udma_desc_is_rx_flush(struct udma_chan *uc, dma_addr_t addr) -{ - if (uc->config.dir != DMA_DEV_TO_MEM) - return false; - - if (addr == udma_get_rx_flush_hwdesc_paddr(uc)) - return true; - - return false; -} - -static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr) -{ - struct k3_ring *ring = NULL; - int ret; - - switch (uc->config.dir) { - case DMA_DEV_TO_MEM: - ring = uc->rflow->r_ring; - break; - case DMA_MEM_TO_DEV: - case DMA_MEM_TO_MEM: - ring = uc->tchan->tc_ring; - break; - default: - return -ENOENT; - } - - ret = k3_ringacc_ring_pop(ring, addr); - if (ret) - return ret; - - rmb(); /* Ensure that reads are not moved before this point */ - - /* Teardown completion */ - if (cppi5_desc_is_tdcm(*addr)) - return 0; - - /* Check for flush descriptor */ - if (udma_desc_is_rx_flush(uc, *addr)) - return -ENOENT; - - return 0; -} - -static void udma_reset_rings(struct udma_chan *uc) -{ - struct k3_ring *ring1 = NULL; - struct k3_ring *ring2 = NULL; - - switch (uc->config.dir) { - case DMA_DEV_TO_MEM: - if (uc->rchan) { - ring1 = uc->rflow->fd_ring; - ring2 = uc->rflow->r_ring; - } - break; - case DMA_MEM_TO_DEV: - case DMA_MEM_TO_MEM: - if (uc->tchan) { - ring1 = uc->tchan->t_ring; - ring2 = uc->tchan->tc_ring; - } - break; - default: - break; - } - - if (ring1) - k3_ringacc_ring_reset_dma(ring1, - k3_ringacc_ring_get_occ(ring1)); - if (ring2) - k3_ringacc_ring_reset(ring2); - - /* make sure we are not leaking memory by stalled descriptor */ - if (uc->terminated_desc) { - udma_desc_free(&uc->terminated_desc->vd); - uc->terminated_desc = NULL; - } -} - static void udma_decrement_byte_counters(struct udma_chan *uc, u32 val) { if (uc->desc->dir == DMA_DEV_TO_MEM) { @@ -860,40 +189,6 @@ return 0; } -static void udma_start_desc(struct udma_chan *uc) -{ - struct udma_chan_config *ucc = &uc->config; - - if (uc->ud->match_data->type == DMA_TYPE_UDMA && ucc->pkt_mode && - (uc->cyclic || ucc->dir == DMA_DEV_TO_MEM)) { - int i; - - /* - * UDMA only: Push all descriptors to ring for packet mode - * cyclic or RX - * PKTDMA supports pre-linked descriptor and cyclic is not - * supported - */ - for (i = 0; i < uc->desc->sglen; i++) - udma_push_to_ring(uc, i); - } else { - udma_push_to_ring(uc, 0); - } -} - -static bool udma_chan_needs_reconfiguration(struct udma_chan *uc) -{ - /* Only PDMAs have staticTR */ - if (uc->config.ep_type == PSIL_EP_NATIVE) - return false; - - /* Check if the staticTR configuration has changed for TX */ - if (memcmp(&uc->static_tr, &uc->desc->static_tr, sizeof(uc->static_tr))) - return true; - - return false; -} - static int udma_start(struct udma_chan *uc) { struct virt_dma_desc *vd = vchan_next_desc(&uc->vc); @@ -1038,24 +333,6 @@ return 0; } -static void udma_cyclic_packet_elapsed(struct udma_chan *uc) -{ - struct udma_desc *d = uc->desc; - struct cppi5_host_desc_t *h_desc; - - h_desc = d->hwdesc[d->desc_idx].cppi5_desc_vaddr; - cppi5_hdesc_reset_to_original(h_desc); - udma_push_to_ring(uc, d->desc_idx); - d->desc_idx = (d->desc_idx + 1) % d->sglen; -} - -static inline void udma_fetch_epib(struct udma_chan *uc, struct udma_desc *d) -{ - struct cppi5_host_desc_t *h_desc = d->hwdesc[0].cppi5_desc_vaddr; - - memcpy(d->metadata, h_desc->epib, d->metadata_size); -} - static bool udma_is_desc_really_done(struct udma_chan *uc, struct udma_desc *d) { u32 peer_bcnt, bcnt; @@ -1083,75 +360,6 @@ return true; } -static void udma_check_tx_completion(struct work_struct *work) -{ - struct udma_chan *uc = container_of(work, typeof(*uc), - tx_drain.work.work); - bool desc_done = true; - u32 residue_diff; - ktime_t time_diff; - unsigned long delay; - unsigned long flags; - - while (1) { - spin_lock_irqsave(&uc->vc.lock, flags); - - if (uc->desc) { - /* Get previous residue and time stamp */ - residue_diff = uc->tx_drain.residue; - time_diff = uc->tx_drain.tstamp; - /* - * Get current residue and time stamp or see if - * transfer is complete - */ - desc_done = udma_is_desc_really_done(uc, uc->desc); - } - - if (!desc_done) { - /* - * Find the time delta and residue delta w.r.t - * previous poll - */ - time_diff = ktime_sub(uc->tx_drain.tstamp, - time_diff) + 1; - residue_diff -= uc->tx_drain.residue; - if (residue_diff) { - /* - * Try to guess when we should check - * next time by calculating rate at - * which data is being drained at the - * peer device - */ - delay = (time_diff / residue_diff) * - uc->tx_drain.residue; - } else { - /* No progress, check again in 1 second */ - schedule_delayed_work(&uc->tx_drain.work, HZ); - break; - } - - spin_unlock_irqrestore(&uc->vc.lock, flags); - - usleep_range(ktime_to_us(delay), - ktime_to_us(delay) + 10); - continue; - } - - if (uc->desc) { - struct udma_desc *d = uc->desc; - - udma_decrement_byte_counters(uc, d->residue); - udma_start(uc); - vchan_cookie_complete(&d->vd); - break; - } - - break; - } - - spin_unlock_irqrestore(&uc->vc.lock, flags); -} - static irqreturn_t udma_ring_irq_handler(int irq, void *data) { struct udma_chan *uc = data; @@ -1242,135 +450,6 @@ return IRQ_HANDLED; } -/** - * __udma_alloc_gp_rflow_range - alloc range of GP RX flows - * @ud: UDMA device - * @from: Start the search from this flow id number - * @cnt: Number of consecutive flow ids to allocate - * - * Allocate range of RX flow ids for future use, those flows can be requested - * only using explicit flow id number. if @from is set to -1 it will try to find - * first free range. if @from is positive value it will force allocation only - * of the specified range of flows. - * - * Returns -ENOMEM if can't find free range. - * -EEXIST if requested range is busy. - * -EINVAL if wrong input values passed. - * Returns flow id on success. - */ -static int __udma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt) -{ - int start, tmp_from; - DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS); - - tmp_from = from; - if (tmp_from < 0) - tmp_from = ud->rchan_cnt; - /* default flows can't be allocated and accessible only by id */ - if (tmp_from < ud->rchan_cnt) - return -EINVAL; - - if (tmp_from + cnt > ud->rflow_cnt) - return -EINVAL; - - bitmap_or(tmp, ud->rflow_gp_map, ud->rflow_gp_map_allocated, - ud->rflow_cnt); - - start = bitmap_find_next_zero_area(tmp, - ud->rflow_cnt, - tmp_from, cnt, 0); - if (start >= ud->rflow_cnt) - return -ENOMEM; - - if (from >= 0 && start != from) - return -EEXIST; - - bitmap_set(ud->rflow_gp_map_allocated, start, cnt); - return start; -} - -static int __udma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt) -{ - if (from < ud->rchan_cnt) - return -EINVAL; - if (from + cnt > ud->rflow_cnt) - return -EINVAL; - - bitmap_clear(ud->rflow_gp_map_allocated, from, cnt); - return 0; -} - -static struct udma_rflow *__udma_get_rflow(struct udma_dev *ud, int id) -{ - /* - * Attempt to request rflow by ID can be made for any rflow - * if not in use with assumption that caller knows what's doing. - * TI-SCI FW will perform additional permission check ant way, it's - * safe - */ - - if (id < 0 || id >= ud->rflow_cnt) - return ERR_PTR(-ENOENT); - - if (test_bit(id, ud->rflow_in_use)) - return ERR_PTR(-ENOENT); - - if (ud->rflow_gp_map) { - /* GP rflow has to be allocated first */ - if (!test_bit(id, ud->rflow_gp_map) && - !test_bit(id, ud->rflow_gp_map_allocated)) - return ERR_PTR(-EINVAL); - } - - dev_dbg(ud->dev, "get rflow%d\n", id); - set_bit(id, ud->rflow_in_use); - return &ud->rflows[id]; -} - -static void __udma_put_rflow(struct udma_dev *ud, struct udma_rflow *rflow) -{ - if (!test_bit(rflow->id, ud->rflow_in_use)) { - dev_err(ud->dev, "attempt to put unused rflow%d\n", rflow->id); - return; - } - - dev_dbg(ud->dev, "put rflow%d\n", rflow->id); - clear_bit(rflow->id, ud->rflow_in_use); -} - -#define UDMA_RESERVE_RESOURCE(res) \ -static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \ - enum udma_tp_level tpl, \ - int id) \ -{ \ - if (id >= 0) { \ - if (test_bit(id, ud->res##_map)) { \ - dev_err(ud->dev, "res##%d is in use\n", id); \ - return ERR_PTR(-ENOENT); \ - } \ - } else { \ - int start; \ - \ - if (tpl >= ud->res##_tpl.levels) \ - tpl = ud->res##_tpl.levels - 1; \ - \ - start = ud->res##_tpl.start_idx[tpl]; \ - \ - id = find_next_zero_bit(ud->res##_map, ud->res##_cnt, \ - start); \ - if (id == ud->res##_cnt) { \ - return ERR_PTR(-ENOENT); \ - } \ - } \ - \ - set_bit(id, ud->res##_map); \ - return &ud->res##s[id]; \ -} - -UDMA_RESERVE_RESOURCE(bchan); -UDMA_RESERVE_RESOURCE(tchan); -UDMA_RESERVE_RESOURCE(rchan); - static int bcdma_get_bchan(struct udma_chan *uc) { struct udma_dev *ud = uc->ud; @@ -1404,223 +483,6 @@ return 0; } -static int udma_get_tchan(struct udma_chan *uc) -{ - struct udma_dev *ud = uc->ud; - int ret; - - if (uc->tchan) { - dev_dbg(ud->dev, "chan%d: already have tchan%d allocated\n", - uc->id, uc->tchan->id); - return 0; - } - - /* - * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels. - * For PKTDMA mapped channels it is configured to a channel which must - * be used to service the peripheral. - */ - uc->tchan = __udma_reserve_tchan(ud, uc->config.channel_tpl, - uc->config.mapped_channel_id); - if (IS_ERR(uc->tchan)) { - ret = PTR_ERR(uc->tchan); - uc->tchan = NULL; - return ret; - } - - if (ud->tflow_cnt) { - int tflow_id; - - /* Only PKTDMA have support for tx flows */ - if (uc->config.default_flow_id >= 0) - tflow_id = uc->config.default_flow_id; - else - tflow_id = uc->tchan->id; - - if (test_bit(tflow_id, ud->tflow_map)) { - dev_err(ud->dev, "tflow%d is in use\n", tflow_id); - clear_bit(uc->tchan->id, ud->tchan_map); - uc->tchan = NULL; - return -ENOENT; - } - - uc->tchan->tflow_id = tflow_id; - set_bit(tflow_id, ud->tflow_map); - } else { - uc->tchan->tflow_id = -1; - } - - return 0; -} - -static int udma_get_rchan(struct udma_chan *uc) -{ - struct udma_dev *ud = uc->ud; - int ret; - - if (uc->rchan) { - dev_dbg(ud->dev, "chan%d: already have rchan%d allocated\n", - uc->id, uc->rchan->id); - return 0; - } - - /* - * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels. - * For PKTDMA mapped channels it is configured to a channel which must - * be used to service the peripheral. - */ - uc->rchan = __udma_reserve_rchan(ud, uc->config.channel_tpl, - uc->config.mapped_channel_id); - if (IS_ERR(uc->rchan)) { - ret = PTR_ERR(uc->rchan); - uc->rchan = NULL; - return ret; - } - - return 0; -} - -static int udma_get_chan_pair(struct udma_chan *uc) -{ - struct udma_dev *ud = uc->ud; - int chan_id, end; - - if ((uc->tchan && uc->rchan) && uc->tchan->id == uc->rchan->id) { - dev_info(ud->dev, "chan%d: already have %d pair allocated\n", - uc->id, uc->tchan->id); - return 0; - } - - if (uc->tchan) { - dev_err(ud->dev, "chan%d: already have tchan%d allocated\n", - uc->id, uc->tchan->id); - return -EBUSY; - } else if (uc->rchan) { - dev_err(ud->dev, "chan%d: already have rchan%d allocated\n", - uc->id, uc->rchan->id); - return -EBUSY; - } - - /* Can be optimized, but let's have it like this for now */ - end = min(ud->tchan_cnt, ud->rchan_cnt); - /* - * Try to use the highest TPL channel pair for MEM_TO_MEM channels - * Note: in UDMAP the channel TPL is symmetric between tchan and rchan - */ - chan_id = ud->tchan_tpl.start_idx[ud->tchan_tpl.levels - 1]; - for (; chan_id < end; chan_id++) { - if (!test_bit(chan_id, ud->tchan_map) && - !test_bit(chan_id, ud->rchan_map)) - break; - } - - if (chan_id == end) - return -ENOENT; - - set_bit(chan_id, ud->tchan_map); - set_bit(chan_id, ud->rchan_map); - uc->tchan = &ud->tchans[chan_id]; - uc->rchan = &ud->rchans[chan_id]; - - /* UDMA does not use tx flows */ - uc->tchan->tflow_id = -1; - - return 0; -} - -static int udma_get_rflow(struct udma_chan *uc, int flow_id) -{ - struct udma_dev *ud = uc->ud; - int ret; - - if (!uc->rchan) { - dev_err(ud->dev, "chan%d: does not have rchan??\n", uc->id); - return -EINVAL; - } - - if (uc->rflow) { - dev_dbg(ud->dev, "chan%d: already have rflow%d allocated\n", - uc->id, uc->rflow->id); - return 0; - } - - uc->rflow = __udma_get_rflow(ud, flow_id); - if (IS_ERR(uc->rflow)) { - ret = PTR_ERR(uc->rflow); - uc->rflow = NULL; - return ret; - } - - return 0; -} - -static void bcdma_put_bchan(struct udma_chan *uc) -{ - struct udma_dev *ud = uc->ud; - - if (uc->bchan) { - dev_dbg(ud->dev, "chan%d: put bchan%d\n", uc->id, - uc->bchan->id); - clear_bit(uc->bchan->id, ud->bchan_map); - uc->bchan = NULL; - uc->tchan = NULL; - } -} - -static void udma_put_rchan(struct udma_chan *uc) -{ - struct udma_dev *ud = uc->ud; - - if (uc->rchan) { - dev_dbg(ud->dev, "chan%d: put rchan%d\n", uc->id, - uc->rchan->id); - clear_bit(uc->rchan->id, ud->rchan_map); - uc->rchan = NULL; - } -} - -static void udma_put_tchan(struct udma_chan *uc) -{ - struct udma_dev *ud = uc->ud; - - if (uc->tchan) { - dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id, - uc->tchan->id); - clear_bit(uc->tchan->id, ud->tchan_map); - - if (uc->tchan->tflow_id >= 0) - clear_bit(uc->tchan->tflow_id, ud->tflow_map); - - uc->tchan = NULL; - } -} - -static void udma_put_rflow(struct udma_chan *uc) -{ - struct udma_dev *ud = uc->ud; - - if (uc->rflow) { - dev_dbg(ud->dev, "chan%d: put rflow%d\n", uc->id, - uc->rflow->id); - __udma_put_rflow(ud, uc->rflow); - uc->rflow = NULL; - } -} - -static void bcdma_free_bchan_resources(struct udma_chan *uc) -{ - if (!uc->bchan) - return; - - k3_ringacc_ring_free(uc->bchan->tc_ring); - k3_ringacc_ring_free(uc->bchan->t_ring); - uc->bchan->tc_ring = NULL; - uc->bchan->t_ring = NULL; - k3_configure_chan_coherency(&uc->vc.chan, 0); - - bcdma_put_bchan(uc); -} - static int bcdma_alloc_bchan_resources(struct udma_chan *uc) { struct k3_ring_cfg ring_cfg; @@ -1666,19 +528,6 @@ return ret; } -static void udma_free_tx_resources(struct udma_chan *uc) -{ - if (!uc->tchan) - return; - - k3_ringacc_ring_free(uc->tchan->t_ring); - k3_ringacc_ring_free(uc->tchan->tc_ring); - uc->tchan->t_ring = NULL; - uc->tchan->tc_ring = NULL; - - udma_put_tchan(uc); -} - static int udma_alloc_tx_resources(struct udma_chan *uc) { struct k3_ring_cfg ring_cfg; @@ -1736,25 +585,6 @@ return ret; } -static void udma_free_rx_resources(struct udma_chan *uc) -{ - if (!uc->rchan) - return; - - if (uc->rflow) { - struct udma_rflow *rflow = uc->rflow; - - k3_ringacc_ring_free(rflow->fd_ring); - k3_ringacc_ring_free(rflow->r_ring); - rflow->fd_ring = NULL; - rflow->r_ring = NULL; - - udma_put_rflow(uc); - } - - udma_put_rchan(uc); -} - static int udma_alloc_rx_resources(struct udma_chan *uc) { struct udma_dev *ud = uc->ud; @@ -2748,1079 +1578,6 @@ return ret; } -static int udma_slave_config(struct dma_chan *chan, - struct dma_slave_config *cfg) -{ - struct udma_chan *uc = to_udma_chan(chan); - - memcpy(&uc->cfg, cfg, sizeof(uc->cfg)); - - return 0; -} - -static struct udma_desc *udma_alloc_tr_desc(struct udma_chan *uc, - size_t tr_size, int tr_count, - enum dma_transfer_direction dir) -{ - struct udma_hwdesc *hwdesc; - struct cppi5_desc_hdr_t *tr_desc; - struct udma_desc *d; - u32 reload_count = 0; - u32 ring_id; - - switch (tr_size) { - case 16: - case 32: - case 64: - case 128: - break; - default: - dev_err(uc->ud->dev, "Unsupported TR size of %zu\n", tr_size); - return NULL; - } - - /* We have only one descriptor containing multiple TRs */ - d = kzalloc(sizeof(*d) + sizeof(d->hwdesc[0]), GFP_NOWAIT); - if (!d) - return NULL; - - d->sglen = tr_count; - - d->hwdesc_count = 1; - hwdesc = &d->hwdesc[0]; - - /* Allocate memory for DMA ring descriptor */ - if (uc->use_dma_pool) { - hwdesc->cppi5_desc_size = uc->config.hdesc_size; - hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool, - GFP_NOWAIT, - &hwdesc->cppi5_desc_paddr); - } else { - hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size, - tr_count); - hwdesc->cppi5_desc_size = ALIGN(hwdesc->cppi5_desc_size, - uc->ud->desc_align); - hwdesc->cppi5_desc_vaddr = dma_alloc_coherent(uc->ud->dev, - hwdesc->cppi5_desc_size, - &hwdesc->cppi5_desc_paddr, - GFP_NOWAIT); - } - - if (!hwdesc->cppi5_desc_vaddr) { - kfree(d); - return NULL; - } - - /* Start of the TR req records */ - hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size; - /* Start address of the TR response array */ - hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size * tr_count; - - tr_desc = hwdesc->cppi5_desc_vaddr; - - if (uc->cyclic) - reload_count = CPPI5_INFO0_TRDESC_RLDCNT_INFINITE; - - if (dir == DMA_DEV_TO_MEM) - ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring); - else - ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring); - - cppi5_trdesc_init(tr_desc, tr_count, tr_size, 0, reload_count); - cppi5_desc_set_pktids(tr_desc, uc->id, - CPPI5_INFO1_DESC_FLOWID_DEFAULT); - cppi5_desc_set_retpolicy(tr_desc, 0, ring_id); - - return d; -} - -/** - * udma_get_tr_counters - calculate TR counters for a given length - * @len: Length of the trasnfer - * @align_to: Preferred alignment - * @tr0_cnt0: First TR icnt0 - * @tr0_cnt1: First TR icnt1 - * @tr1_cnt0: Second (if used) TR icnt0 - * - * For len < SZ_64K only one TR is enough, tr1_cnt0 is not updated - * For len >= SZ_64K two TRs are used in a simple way: - * First TR: SZ_64K-alignment blocks (tr0_cnt0, tr0_cnt1) - * Second TR: the remaining length (tr1_cnt0) - * - * Returns the number of TRs the length needs (1 or 2) - * -EINVAL if the length can not be supported - */ -static int udma_get_tr_counters(size_t len, unsigned long align_to, - u16 *tr0_cnt0, u16 *tr0_cnt1, u16 *tr1_cnt0) -{ - if (len < SZ_64K) { - *tr0_cnt0 = len; - *tr0_cnt1 = 1; - - return 1; - } - - if (align_to > 3) - align_to = 3; - -realign: - *tr0_cnt0 = SZ_64K - BIT(align_to); - if (len / *tr0_cnt0 >= SZ_64K) { - if (align_to) { - align_to--; - goto realign; - } - return -EINVAL; - } - - *tr0_cnt1 = len / *tr0_cnt0; - *tr1_cnt0 = len % *tr0_cnt0; - - return 2; -} - -static struct udma_desc * -udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl, - unsigned int sglen, enum dma_transfer_direction dir, - unsigned long tx_flags, void *context) -{ - struct scatterlist *sgent; - struct udma_desc *d; - struct cppi5_tr_type1_t *tr_req = NULL; - u16 tr0_cnt0, tr0_cnt1, tr1_cnt0; - unsigned int i; - size_t tr_size; - int num_tr = 0; - int tr_idx = 0; - u64 asel; - - /* estimate the number of TRs we will need */ - for_each_sg(sgl, sgent, sglen, i) { - if (sg_dma_len(sgent) < SZ_64K) - num_tr++; - else - num_tr += 2; - } - - /* Now allocate and setup the descriptor. */ - tr_size = sizeof(struct cppi5_tr_type1_t); - d = udma_alloc_tr_desc(uc, tr_size, num_tr, dir); - if (!d) - return NULL; - - d->sglen = sglen; - - if (uc->ud->match_data->type == DMA_TYPE_UDMA) - asel = 0; - else - asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; - - tr_req = d->hwdesc[0].tr_req_base; - for_each_sg(sgl, sgent, sglen, i) { - dma_addr_t sg_addr = sg_dma_address(sgent); - - num_tr = udma_get_tr_counters(sg_dma_len(sgent), __ffs(sg_addr), - &tr0_cnt0, &tr0_cnt1, &tr1_cnt0); - if (num_tr < 0) { - dev_err(uc->ud->dev, "size %u is not supported\n", - sg_dma_len(sgent)); - udma_free_hwdesc(uc, d); - kfree(d); - return NULL; - } - - cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false, - false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT); - - sg_addr |= asel; - tr_req[tr_idx].addr = sg_addr; - tr_req[tr_idx].icnt0 = tr0_cnt0; - tr_req[tr_idx].icnt1 = tr0_cnt1; - tr_req[tr_idx].dim1 = tr0_cnt0; - tr_idx++; - - if (num_tr == 2) { - cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, - false, false, - CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[tr_idx].flags, - CPPI5_TR_CSF_SUPR_EVT); - - tr_req[tr_idx].addr = sg_addr + tr0_cnt1 * tr0_cnt0; - tr_req[tr_idx].icnt0 = tr1_cnt0; - tr_req[tr_idx].icnt1 = 1; - tr_req[tr_idx].dim1 = tr1_cnt0; - tr_idx++; - } - - d->residue += sg_dma_len(sgent); - } - - cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, - CPPI5_TR_CSF_SUPR_EVT | CPPI5_TR_CSF_EOP); - - return d; -} - -static struct udma_desc * -udma_prep_slave_sg_triggered_tr(struct udma_chan *uc, struct scatterlist *sgl, - unsigned int sglen, - enum dma_transfer_direction dir, - unsigned long tx_flags, void *context) -{ - struct scatterlist *sgent; - struct cppi5_tr_type15_t *tr_req = NULL; - enum dma_slave_buswidth dev_width; - u32 csf = CPPI5_TR_CSF_SUPR_EVT; - u16 tr_cnt0, tr_cnt1; - dma_addr_t dev_addr; - struct udma_desc *d; - unsigned int i; - size_t tr_size, sg_len; - int num_tr = 0; - int tr_idx = 0; - u32 burst, trigger_size, port_window; - u64 asel; - - if (dir == DMA_DEV_TO_MEM) { - dev_addr = uc->cfg.src_addr; - dev_width = uc->cfg.src_addr_width; - burst = uc->cfg.src_maxburst; - port_window = uc->cfg.src_port_window_size; - } else if (dir == DMA_MEM_TO_DEV) { - dev_addr = uc->cfg.dst_addr; - dev_width = uc->cfg.dst_addr_width; - burst = uc->cfg.dst_maxburst; - port_window = uc->cfg.dst_port_window_size; - } else { - dev_err(uc->ud->dev, "%s: bad direction?\n", __func__); - return NULL; - } - - if (!burst) - burst = 1; - - if (port_window) { - if (port_window != burst) { - dev_err(uc->ud->dev, - "The burst must be equal to port_window\n"); - return NULL; - } - - tr_cnt0 = dev_width * port_window; - tr_cnt1 = 1; - } else { - tr_cnt0 = dev_width; - tr_cnt1 = burst; - } - trigger_size = tr_cnt0 * tr_cnt1; - - /* estimate the number of TRs we will need */ - for_each_sg(sgl, sgent, sglen, i) { - sg_len = sg_dma_len(sgent); - - if (sg_len % trigger_size) { - dev_err(uc->ud->dev, - "Not aligned SG entry (%zu for %u)\n", sg_len, - trigger_size); - return NULL; - } - - if (sg_len / trigger_size < SZ_64K) - num_tr++; - else - num_tr += 2; - } - - /* Now allocate and setup the descriptor. */ - tr_size = sizeof(struct cppi5_tr_type15_t); - d = udma_alloc_tr_desc(uc, tr_size, num_tr, dir); - if (!d) - return NULL; - - d->sglen = sglen; - - if (uc->ud->match_data->type == DMA_TYPE_UDMA) { - asel = 0; - csf |= CPPI5_TR_CSF_EOL_ICNT0; - } else { - asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; - dev_addr |= asel; - } - - tr_req = d->hwdesc[0].tr_req_base; - for_each_sg(sgl, sgent, sglen, i) { - u16 tr0_cnt2, tr0_cnt3, tr1_cnt2; - dma_addr_t sg_addr = sg_dma_address(sgent); - - sg_len = sg_dma_len(sgent); - num_tr = udma_get_tr_counters(sg_len / trigger_size, 0, - &tr0_cnt2, &tr0_cnt3, &tr1_cnt2); - if (num_tr < 0) { - dev_err(uc->ud->dev, "size %zu is not supported\n", - sg_len); - udma_free_hwdesc(uc, d); - kfree(d); - return NULL; - } - - cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, false, - true, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[tr_idx].flags, csf); - cppi5_tr_set_trigger(&tr_req[tr_idx].flags, - uc->config.tr_trigger_type, - CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC, 0, 0); - - sg_addr |= asel; - if (dir == DMA_DEV_TO_MEM) { - tr_req[tr_idx].addr = dev_addr; - tr_req[tr_idx].icnt0 = tr_cnt0; - tr_req[tr_idx].icnt1 = tr_cnt1; - tr_req[tr_idx].icnt2 = tr0_cnt2; - tr_req[tr_idx].icnt3 = tr0_cnt3; - tr_req[tr_idx].dim1 = (-1) * tr_cnt0; - - tr_req[tr_idx].daddr = sg_addr; - tr_req[tr_idx].dicnt0 = tr_cnt0; - tr_req[tr_idx].dicnt1 = tr_cnt1; - tr_req[tr_idx].dicnt2 = tr0_cnt2; - tr_req[tr_idx].dicnt3 = tr0_cnt3; - tr_req[tr_idx].ddim1 = tr_cnt0; - tr_req[tr_idx].ddim2 = trigger_size; - tr_req[tr_idx].ddim3 = trigger_size * tr0_cnt2; - } else { - tr_req[tr_idx].addr = sg_addr; - tr_req[tr_idx].icnt0 = tr_cnt0; - tr_req[tr_idx].icnt1 = tr_cnt1; - tr_req[tr_idx].icnt2 = tr0_cnt2; - tr_req[tr_idx].icnt3 = tr0_cnt3; - tr_req[tr_idx].dim1 = tr_cnt0; - tr_req[tr_idx].dim2 = trigger_size; - tr_req[tr_idx].dim3 = trigger_size * tr0_cnt2; - - tr_req[tr_idx].daddr = dev_addr; - tr_req[tr_idx].dicnt0 = tr_cnt0; - tr_req[tr_idx].dicnt1 = tr_cnt1; - tr_req[tr_idx].dicnt2 = tr0_cnt2; - tr_req[tr_idx].dicnt3 = tr0_cnt3; - tr_req[tr_idx].ddim1 = (-1) * tr_cnt0; - } - - tr_idx++; - - if (num_tr == 2) { - cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, - false, true, - CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[tr_idx].flags, csf); - cppi5_tr_set_trigger(&tr_req[tr_idx].flags, - uc->config.tr_trigger_type, - CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC, - 0, 0); - - sg_addr += trigger_size * tr0_cnt2 * tr0_cnt3; - if (dir == DMA_DEV_TO_MEM) { - tr_req[tr_idx].addr = dev_addr; - tr_req[tr_idx].icnt0 = tr_cnt0; - tr_req[tr_idx].icnt1 = tr_cnt1; - tr_req[tr_idx].icnt2 = tr1_cnt2; - tr_req[tr_idx].icnt3 = 1; - tr_req[tr_idx].dim1 = (-1) * tr_cnt0; - - tr_req[tr_idx].daddr = sg_addr; - tr_req[tr_idx].dicnt0 = tr_cnt0; - tr_req[tr_idx].dicnt1 = tr_cnt1; - tr_req[tr_idx].dicnt2 = tr1_cnt2; - tr_req[tr_idx].dicnt3 = 1; - tr_req[tr_idx].ddim1 = tr_cnt0; - tr_req[tr_idx].ddim2 = trigger_size; - } else { - tr_req[tr_idx].addr = sg_addr; - tr_req[tr_idx].icnt0 = tr_cnt0; - tr_req[tr_idx].icnt1 = tr_cnt1; - tr_req[tr_idx].icnt2 = tr1_cnt2; - tr_req[tr_idx].icnt3 = 1; - tr_req[tr_idx].dim1 = tr_cnt0; - tr_req[tr_idx].dim2 = trigger_size; - - tr_req[tr_idx].daddr = dev_addr; - tr_req[tr_idx].dicnt0 = tr_cnt0; - tr_req[tr_idx].dicnt1 = tr_cnt1; - tr_req[tr_idx].dicnt2 = tr1_cnt2; - tr_req[tr_idx].dicnt3 = 1; - tr_req[tr_idx].ddim1 = (-1) * tr_cnt0; - } - tr_idx++; - } - - d->residue += sg_len; - } - - cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, csf | CPPI5_TR_CSF_EOP); - - return d; -} - -static int udma_configure_statictr(struct udma_chan *uc, struct udma_desc *d, - enum dma_slave_buswidth dev_width, - u16 elcnt) -{ - if (uc->config.ep_type != PSIL_EP_PDMA_XY) - return 0; - - /* Bus width translates to the element size (ES) */ - switch (dev_width) { - case DMA_SLAVE_BUSWIDTH_1_BYTE: - d->static_tr.elsize = 0; - break; - case DMA_SLAVE_BUSWIDTH_2_BYTES: - d->static_tr.elsize = 1; - break; - case DMA_SLAVE_BUSWIDTH_3_BYTES: - d->static_tr.elsize = 2; - break; - case DMA_SLAVE_BUSWIDTH_4_BYTES: - d->static_tr.elsize = 3; - break; - case DMA_SLAVE_BUSWIDTH_8_BYTES: - d->static_tr.elsize = 4; - break; - default: /* not reached */ - return -EINVAL; - } - - d->static_tr.elcnt = elcnt; - - if (uc->config.pkt_mode || !uc->cyclic) { - /* - * PDMA must close the packet when the channel is in packet mode. - * For TR mode when the channel is not cyclic we also need PDMA - * to close the packet otherwise the transfer will stall because - * PDMA holds on the data it has received from the peripheral. - */ - unsigned int div = dev_width * elcnt; - - if (uc->cyclic) - d->static_tr.bstcnt = d->residue / d->sglen / div; - else - d->static_tr.bstcnt = d->residue / div; - } else if (uc->ud->match_data->type == DMA_TYPE_BCDMA && - uc->config.dir == DMA_DEV_TO_MEM && - uc->cyclic) { - /* - * For cyclic mode with BCDMA we have to set EOP in each TR to - * prevent short packet errors seen on channel teardown. So the - * PDMA must close the packet after every TR transfer by setting - * burst count equal to the number of bytes transferred. - */ - struct cppi5_tr_type1_t *tr_req = d->hwdesc[0].tr_req_base; - - d->static_tr.bstcnt = - (tr_req->icnt0 * tr_req->icnt1) / dev_width; - } else { - d->static_tr.bstcnt = 0; - } - - if (uc->config.dir == DMA_DEV_TO_MEM && - d->static_tr.bstcnt > uc->ud->match_data->statictr_z_mask) - return -EINVAL; - - return 0; -} - -static struct udma_desc * -udma_prep_slave_sg_pkt(struct udma_chan *uc, struct scatterlist *sgl, - unsigned int sglen, enum dma_transfer_direction dir, - unsigned long tx_flags, void *context) -{ - struct scatterlist *sgent; - struct cppi5_host_desc_t *h_desc = NULL; - struct udma_desc *d; - u32 ring_id; - unsigned int i; - u64 asel; - - d = kzalloc(struct_size(d, hwdesc, sglen), GFP_NOWAIT); - if (!d) - return NULL; - - d->sglen = sglen; - d->hwdesc_count = sglen; - - if (dir == DMA_DEV_TO_MEM) - ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring); - else - ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring); - - if (uc->ud->match_data->type == DMA_TYPE_UDMA) - asel = 0; - else - asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; - - for_each_sg(sgl, sgent, sglen, i) { - struct udma_hwdesc *hwdesc = &d->hwdesc[i]; - dma_addr_t sg_addr = sg_dma_address(sgent); - struct cppi5_host_desc_t *desc; - size_t sg_len = sg_dma_len(sgent); - - hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool, - GFP_NOWAIT, - &hwdesc->cppi5_desc_paddr); - if (!hwdesc->cppi5_desc_vaddr) { - dev_err(uc->ud->dev, - "descriptor%d allocation failed\n", i); - - udma_free_hwdesc(uc, d); - kfree(d); - return NULL; - } - - d->residue += sg_len; - hwdesc->cppi5_desc_size = uc->config.hdesc_size; - desc = hwdesc->cppi5_desc_vaddr; - - if (i == 0) { - cppi5_hdesc_init(desc, 0, 0); - /* Flow and Packed ID */ - cppi5_desc_set_pktids(&desc->hdr, uc->id, - CPPI5_INFO1_DESC_FLOWID_DEFAULT); - cppi5_desc_set_retpolicy(&desc->hdr, 0, ring_id); - } else { - cppi5_hdesc_reset_hbdesc(desc); - cppi5_desc_set_retpolicy(&desc->hdr, 0, 0xffff); - } - - /* attach the sg buffer to the descriptor */ - sg_addr |= asel; - cppi5_hdesc_attach_buf(desc, sg_addr, sg_len, sg_addr, sg_len); - - /* Attach link as host buffer descriptor */ - if (h_desc) - cppi5_hdesc_link_hbdesc(h_desc, - hwdesc->cppi5_desc_paddr | asel); - - if (uc->ud->match_data->type == DMA_TYPE_PKTDMA || - dir == DMA_MEM_TO_DEV) - h_desc = desc; - } - - if (d->residue >= SZ_4M) { - dev_err(uc->ud->dev, - "%s: Transfer size %u is over the supported 4M range\n", - __func__, d->residue); - udma_free_hwdesc(uc, d); - kfree(d); - return NULL; - } - - h_desc = d->hwdesc[0].cppi5_desc_vaddr; - cppi5_hdesc_set_pktlen(h_desc, d->residue); - - return d; -} - -static int udma_attach_metadata(struct dma_async_tx_descriptor *desc, - void *data, size_t len) -{ - struct udma_desc *d = to_udma_desc(desc); - struct udma_chan *uc = to_udma_chan(desc->chan); - struct cppi5_host_desc_t *h_desc; - u32 psd_size = len; - u32 flags = 0; - - if (!uc->config.pkt_mode || !uc->config.metadata_size) - return -ENOTSUPP; - - if (!data || len > uc->config.metadata_size) - return -EINVAL; - - if (uc->config.needs_epib && len < CPPI5_INFO0_HDESC_EPIB_SIZE) - return -EINVAL; - - h_desc = d->hwdesc[0].cppi5_desc_vaddr; - if (d->dir == DMA_MEM_TO_DEV) - memcpy(h_desc->epib, data, len); - - if (uc->config.needs_epib) - psd_size -= CPPI5_INFO0_HDESC_EPIB_SIZE; - - d->metadata = data; - d->metadata_size = len; - if (uc->config.needs_epib) - flags |= CPPI5_INFO0_HDESC_EPIB_PRESENT; - - cppi5_hdesc_update_flags(h_desc, flags); - cppi5_hdesc_update_psdata_size(h_desc, psd_size); - - return 0; -} - -static void *udma_get_metadata_ptr(struct dma_async_tx_descriptor *desc, - size_t *payload_len, size_t *max_len) -{ - struct udma_desc *d = to_udma_desc(desc); - struct udma_chan *uc = to_udma_chan(desc->chan); - struct cppi5_host_desc_t *h_desc; - - if (!uc->config.pkt_mode || !uc->config.metadata_size) - return ERR_PTR(-ENOTSUPP); - - h_desc = d->hwdesc[0].cppi5_desc_vaddr; - - *max_len = uc->config.metadata_size; - - *payload_len = cppi5_hdesc_epib_present(&h_desc->hdr) ? - CPPI5_INFO0_HDESC_EPIB_SIZE : 0; - *payload_len += cppi5_hdesc_get_psdata_size(h_desc); - - return h_desc->epib; -} - -static int udma_set_metadata_len(struct dma_async_tx_descriptor *desc, - size_t payload_len) -{ - struct udma_desc *d = to_udma_desc(desc); - struct udma_chan *uc = to_udma_chan(desc->chan); - struct cppi5_host_desc_t *h_desc; - u32 psd_size = payload_len; - u32 flags = 0; - - if (!uc->config.pkt_mode || !uc->config.metadata_size) - return -ENOTSUPP; - - if (payload_len > uc->config.metadata_size) - return -EINVAL; - - if (uc->config.needs_epib && payload_len < CPPI5_INFO0_HDESC_EPIB_SIZE) - return -EINVAL; - - h_desc = d->hwdesc[0].cppi5_desc_vaddr; - - if (uc->config.needs_epib) { - psd_size -= CPPI5_INFO0_HDESC_EPIB_SIZE; - flags |= CPPI5_INFO0_HDESC_EPIB_PRESENT; - } - - cppi5_hdesc_update_flags(h_desc, flags); - cppi5_hdesc_update_psdata_size(h_desc, psd_size); - - return 0; -} - -static struct dma_descriptor_metadata_ops metadata_ops = { - .attach = udma_attach_metadata, - .get_ptr = udma_get_metadata_ptr, - .set_len = udma_set_metadata_len, -}; - -static struct dma_async_tx_descriptor * -udma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, - unsigned int sglen, enum dma_transfer_direction dir, - unsigned long tx_flags, void *context) -{ - struct udma_chan *uc = to_udma_chan(chan); - enum dma_slave_buswidth dev_width; - struct udma_desc *d; - u32 burst; - - if (dir != uc->config.dir && - (uc->config.dir == DMA_MEM_TO_MEM && !uc->config.tr_trigger_type)) { - dev_err(chan->device->dev, - "%s: chan%d is for %s, not supporting %s\n", - __func__, uc->id, - dmaengine_get_direction_text(uc->config.dir), - dmaengine_get_direction_text(dir)); - return NULL; - } - - if (dir == DMA_DEV_TO_MEM) { - dev_width = uc->cfg.src_addr_width; - burst = uc->cfg.src_maxburst; - } else if (dir == DMA_MEM_TO_DEV) { - dev_width = uc->cfg.dst_addr_width; - burst = uc->cfg.dst_maxburst; - } else { - dev_err(chan->device->dev, "%s: bad direction?\n", __func__); - return NULL; - } - - if (!burst) - burst = 1; - - uc->config.tx_flags = tx_flags; - - if (uc->config.pkt_mode) - d = udma_prep_slave_sg_pkt(uc, sgl, sglen, dir, tx_flags, - context); - else if (is_slave_direction(uc->config.dir)) - d = udma_prep_slave_sg_tr(uc, sgl, sglen, dir, tx_flags, - context); - else - d = udma_prep_slave_sg_triggered_tr(uc, sgl, sglen, dir, - tx_flags, context); - - if (!d) - return NULL; - - d->dir = dir; - d->desc_idx = 0; - d->tr_idx = 0; - - /* static TR for remote PDMA */ - if (udma_configure_statictr(uc, d, dev_width, burst)) { - dev_err(uc->ud->dev, - "%s: StaticTR Z is limited to maximum %u (%u)\n", - __func__, uc->ud->match_data->statictr_z_mask, - d->static_tr.bstcnt); - - udma_free_hwdesc(uc, d); - kfree(d); - return NULL; - } - - if (uc->config.metadata_size) - d->vd.tx.metadata_ops = &metadata_ops; - - return vchan_tx_prep(&uc->vc, &d->vd, tx_flags); -} - -static struct udma_desc * -udma_prep_dma_cyclic_tr(struct udma_chan *uc, dma_addr_t buf_addr, - size_t buf_len, size_t period_len, - enum dma_transfer_direction dir, unsigned long flags) -{ - struct udma_desc *d; - size_t tr_size, period_addr; - struct cppi5_tr_type1_t *tr_req; - unsigned int periods = buf_len / period_len; - u16 tr0_cnt0, tr0_cnt1, tr1_cnt0; - unsigned int i; - int num_tr; - u32 period_csf = 0; - - num_tr = udma_get_tr_counters(period_len, __ffs(buf_addr), &tr0_cnt0, - &tr0_cnt1, &tr1_cnt0); - if (num_tr < 0) { - dev_err(uc->ud->dev, "size %zu is not supported\n", - period_len); - return NULL; - } - - /* Now allocate and setup the descriptor. */ - tr_size = sizeof(struct cppi5_tr_type1_t); - d = udma_alloc_tr_desc(uc, tr_size, periods * num_tr, dir); - if (!d) - return NULL; - - tr_req = d->hwdesc[0].tr_req_base; - if (uc->ud->match_data->type == DMA_TYPE_UDMA) - period_addr = buf_addr; - else - period_addr = buf_addr | - ((u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT); - - /* - * For BCDMA <-> PDMA transfers, the EOP flag needs to be set on the - * last TR of a descriptor, to mark the packet as complete. - * This is required for getting the teardown completion message in case - * of TX, and to avoid short-packet error in case of RX. - * - * As we are in cyclic mode, we do not know which period might be the - * last one, so set the flag for each period. - */ - if (uc->config.ep_type == PSIL_EP_PDMA_XY && - uc->ud->match_data->type == DMA_TYPE_BCDMA) { - period_csf = CPPI5_TR_CSF_EOP; - } - - for (i = 0; i < periods; i++) { - int tr_idx = i * num_tr; - - cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false, - false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - - tr_req[tr_idx].addr = period_addr; - tr_req[tr_idx].icnt0 = tr0_cnt0; - tr_req[tr_idx].icnt1 = tr0_cnt1; - tr_req[tr_idx].dim1 = tr0_cnt0; - - if (num_tr == 2) { - cppi5_tr_csf_set(&tr_req[tr_idx].flags, - CPPI5_TR_CSF_SUPR_EVT); - tr_idx++; - - cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, - false, false, - CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - - tr_req[tr_idx].addr = period_addr + tr0_cnt1 * tr0_cnt0; - tr_req[tr_idx].icnt0 = tr1_cnt0; - tr_req[tr_idx].icnt1 = 1; - tr_req[tr_idx].dim1 = tr1_cnt0; - } - - if (!(flags & DMA_PREP_INTERRUPT)) - period_csf |= CPPI5_TR_CSF_SUPR_EVT; - - if (period_csf) - cppi5_tr_csf_set(&tr_req[tr_idx].flags, period_csf); - - period_addr += period_len; - } - - return d; -} - -static struct udma_desc * -udma_prep_dma_cyclic_pkt(struct udma_chan *uc, dma_addr_t buf_addr, - size_t buf_len, size_t period_len, - enum dma_transfer_direction dir, unsigned long flags) -{ - struct udma_desc *d; - u32 ring_id; - int i; - int periods = buf_len / period_len; - - if (periods > (K3_UDMA_DEFAULT_RING_SIZE - 1)) - return NULL; - - if (period_len >= SZ_4M) - return NULL; - - d = kzalloc(struct_size(d, hwdesc, periods), GFP_NOWAIT); - if (!d) - return NULL; - - d->hwdesc_count = periods; - - /* TODO: re-check this... */ - if (dir == DMA_DEV_TO_MEM) - ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring); - else - ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring); - - if (uc->ud->match_data->type != DMA_TYPE_UDMA) - buf_addr |= (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; - - for (i = 0; i < periods; i++) { - struct udma_hwdesc *hwdesc = &d->hwdesc[i]; - dma_addr_t period_addr = buf_addr + (period_len * i); - struct cppi5_host_desc_t *h_desc; - - hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool, - GFP_NOWAIT, - &hwdesc->cppi5_desc_paddr); - if (!hwdesc->cppi5_desc_vaddr) { - dev_err(uc->ud->dev, - "descriptor%d allocation failed\n", i); - - udma_free_hwdesc(uc, d); - kfree(d); - return NULL; - } - - hwdesc->cppi5_desc_size = uc->config.hdesc_size; - h_desc = hwdesc->cppi5_desc_vaddr; - - cppi5_hdesc_init(h_desc, 0, 0); - cppi5_hdesc_set_pktlen(h_desc, period_len); - - /* Flow and Packed ID */ - cppi5_desc_set_pktids(&h_desc->hdr, uc->id, - CPPI5_INFO1_DESC_FLOWID_DEFAULT); - cppi5_desc_set_retpolicy(&h_desc->hdr, 0, ring_id); - - /* attach each period to a new descriptor */ - cppi5_hdesc_attach_buf(h_desc, - period_addr, period_len, - period_addr, period_len); - } - - return d; -} - -static struct dma_async_tx_descriptor * -udma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, - size_t period_len, enum dma_transfer_direction dir, - unsigned long flags) -{ - struct udma_chan *uc = to_udma_chan(chan); - enum dma_slave_buswidth dev_width; - struct udma_desc *d; - u32 burst; - - if (dir != uc->config.dir) { - dev_err(chan->device->dev, - "%s: chan%d is for %s, not supporting %s\n", - __func__, uc->id, - dmaengine_get_direction_text(uc->config.dir), - dmaengine_get_direction_text(dir)); - return NULL; - } - - uc->cyclic = true; - - if (dir == DMA_DEV_TO_MEM) { - dev_width = uc->cfg.src_addr_width; - burst = uc->cfg.src_maxburst; - } else if (dir == DMA_MEM_TO_DEV) { - dev_width = uc->cfg.dst_addr_width; - burst = uc->cfg.dst_maxburst; - } else { - dev_err(uc->ud->dev, "%s: bad direction?\n", __func__); - return NULL; - } - - if (!burst) - burst = 1; - - if (uc->config.pkt_mode) - d = udma_prep_dma_cyclic_pkt(uc, buf_addr, buf_len, period_len, - dir, flags); - else - d = udma_prep_dma_cyclic_tr(uc, buf_addr, buf_len, period_len, - dir, flags); - - if (!d) - return NULL; - - d->sglen = buf_len / period_len; - - d->dir = dir; - d->residue = buf_len; - - /* static TR for remote PDMA */ - if (udma_configure_statictr(uc, d, dev_width, burst)) { - dev_err(uc->ud->dev, - "%s: StaticTR Z is limited to maximum %u (%u)\n", - __func__, uc->ud->match_data->statictr_z_mask, - d->static_tr.bstcnt); - - udma_free_hwdesc(uc, d); - kfree(d); - return NULL; - } - - if (uc->config.metadata_size) - d->vd.tx.metadata_ops = &metadata_ops; - - return vchan_tx_prep(&uc->vc, &d->vd, flags); -} - -static struct dma_async_tx_descriptor * -udma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, - size_t len, unsigned long tx_flags) -{ - struct udma_chan *uc = to_udma_chan(chan); - struct udma_desc *d; - struct cppi5_tr_type15_t *tr_req; - int num_tr; - size_t tr_size = sizeof(struct cppi5_tr_type15_t); - u16 tr0_cnt0, tr0_cnt1, tr1_cnt0; - u32 csf = CPPI5_TR_CSF_SUPR_EVT; - - if (uc->config.dir != DMA_MEM_TO_MEM) { - dev_err(chan->device->dev, - "%s: chan%d is for %s, not supporting %s\n", - __func__, uc->id, - dmaengine_get_direction_text(uc->config.dir), - dmaengine_get_direction_text(DMA_MEM_TO_MEM)); - return NULL; - } - - num_tr = udma_get_tr_counters(len, __ffs(src | dest), &tr0_cnt0, - &tr0_cnt1, &tr1_cnt0); - if (num_tr < 0) { - dev_err(uc->ud->dev, "size %zu is not supported\n", - len); - return NULL; - } - - d = udma_alloc_tr_desc(uc, tr_size, num_tr, DMA_MEM_TO_MEM); - if (!d) - return NULL; - - d->dir = DMA_MEM_TO_MEM; - d->desc_idx = 0; - d->tr_idx = 0; - d->residue = len; - - if (uc->ud->match_data->type != DMA_TYPE_UDMA) { - src |= (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT; - dest |= (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT; - } else { - csf |= CPPI5_TR_CSF_EOL_ICNT0; - } - - tr_req = d->hwdesc[0].tr_req_base; - - cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true, - CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[0].flags, csf); - - tr_req[0].addr = src; - tr_req[0].icnt0 = tr0_cnt0; - tr_req[0].icnt1 = tr0_cnt1; - tr_req[0].icnt2 = 1; - tr_req[0].icnt3 = 1; - tr_req[0].dim1 = tr0_cnt0; - - tr_req[0].daddr = dest; - tr_req[0].dicnt0 = tr0_cnt0; - tr_req[0].dicnt1 = tr0_cnt1; - tr_req[0].dicnt2 = 1; - tr_req[0].dicnt3 = 1; - tr_req[0].ddim1 = tr0_cnt0; - - if (num_tr == 2) { - cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true, - CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[1].flags, csf); - - tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0; - tr_req[1].icnt0 = tr1_cnt0; - tr_req[1].icnt1 = 1; - tr_req[1].icnt2 = 1; - tr_req[1].icnt3 = 1; - - tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0; - tr_req[1].dicnt0 = tr1_cnt0; - tr_req[1].dicnt1 = 1; - tr_req[1].dicnt2 = 1; - tr_req[1].dicnt3 = 1; - } - - cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, csf | CPPI5_TR_CSF_EOP); - - if (uc->config.metadata_size) - d->vd.tx.metadata_ops = &metadata_ops; - - return vchan_tx_prep(&uc->vc, &d->vd, tx_flags); -} - -static void udma_issue_pending(struct dma_chan *chan) -{ - struct udma_chan *uc = to_udma_chan(chan); - unsigned long flags; - - spin_lock_irqsave(&uc->vc.lock, flags); - - /* If we have something pending and no active descriptor, then */ - if (vchan_issue_pending(&uc->vc) && !uc->desc) { - /* - * start a descriptor if the channel is NOT [marked as - * terminating _and_ it is still running (teardown has not - * completed yet)]. - */ - if (!(uc->state == UDMA_CHAN_IS_TERMINATING && - udma_is_chan_running(uc))) - udma_start(uc); - } - - spin_unlock_irqrestore(&uc->vc.lock, flags); -} - static enum dma_status udma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) @@ -3948,194 +1705,10 @@ return 0; } -static int udma_terminate_all(struct dma_chan *chan) -{ - struct udma_chan *uc = to_udma_chan(chan); - unsigned long flags; - LIST_HEAD(head); - - spin_lock_irqsave(&uc->vc.lock, flags); - - if (udma_is_chan_running(uc)) - udma_stop(uc); - - if (uc->desc) { - uc->terminated_desc = uc->desc; - uc->desc = NULL; - uc->terminated_desc->terminated = true; - cancel_delayed_work(&uc->tx_drain.work); - } - - uc->paused = false; - - vchan_get_all_descriptors(&uc->vc, &head); - spin_unlock_irqrestore(&uc->vc.lock, flags); - vchan_dma_desc_free_list(&uc->vc, &head); - - return 0; -} - -static void udma_synchronize(struct dma_chan *chan) -{ - struct udma_chan *uc = to_udma_chan(chan); - unsigned long timeout = msecs_to_jiffies(1000); - - vchan_synchronize(&uc->vc); - - if (uc->state == UDMA_CHAN_IS_TERMINATING) { - timeout = wait_for_completion_timeout(&uc->teardown_completed, - timeout); - if (!timeout) { - dev_warn(uc->ud->dev, "chan%d teardown timeout!\n", - uc->id); - udma_dump_chan_stdata(uc); - udma_reset_chan(uc, true); - } - } - - udma_reset_chan(uc, false); - if (udma_is_chan_running(uc)) - dev_warn(uc->ud->dev, "chan%d refused to stop!\n", uc->id); - - cancel_delayed_work_sync(&uc->tx_drain.work); - udma_reset_rings(uc); -} - -static void udma_desc_pre_callback(struct virt_dma_chan *vc, - struct virt_dma_desc *vd, - struct dmaengine_result *result) -{ - struct udma_chan *uc = to_udma_chan(&vc->chan); - struct udma_desc *d; - u8 status; - - if (!vd) - return; - - d = to_udma_desc(&vd->tx); - - if (d->metadata_size) - udma_fetch_epib(uc, d); - - if (result) { - void *desc_vaddr = udma_curr_cppi5_desc_vaddr(d, d->desc_idx); - - if (cppi5_desc_get_type(desc_vaddr) == - CPPI5_INFO0_DESC_TYPE_VAL_HOST) { - /* Provide residue information for the client */ - result->residue = d->residue - - cppi5_hdesc_get_pktlen(desc_vaddr); - if (result->residue) - result->result = DMA_TRANS_ABORTED; - else - result->result = DMA_TRANS_NOERROR; - } else { - result->residue = 0; - /* Propagate TR Response errors to the client */ - status = d->hwdesc[0].tr_resp_base->status; - if (status) - result->result = DMA_TRANS_ABORTED; - else - result->result = DMA_TRANS_NOERROR; - } - } -} - -/* - * This tasklet handles the completion of a DMA descriptor by - * calling its callback and freeing it. - */ -static void udma_vchan_complete(struct tasklet_struct *t) -{ - struct virt_dma_chan *vc = from_tasklet(vc, t, task); - struct virt_dma_desc *vd, *_vd; - struct dmaengine_desc_callback cb; - LIST_HEAD(head); - - spin_lock_irq(&vc->lock); - list_splice_tail_init(&vc->desc_completed, &head); - vd = vc->cyclic; - if (vd) { - vc->cyclic = NULL; - dmaengine_desc_get_callback(&vd->tx, &cb); - } else { - memset(&cb, 0, sizeof(cb)); - } - spin_unlock_irq(&vc->lock); - - udma_desc_pre_callback(vc, vd, NULL); - dmaengine_desc_callback_invoke(&cb, NULL); - - list_for_each_entry_safe(vd, _vd, &head, node) { - struct dmaengine_result result; - - dmaengine_desc_get_callback(&vd->tx, &cb); - - list_del(&vd->node); - - udma_desc_pre_callback(vc, vd, &result); - dmaengine_desc_callback_invoke(&cb, &result); - - vchan_vdesc_fini(vd); - } -} - -static void udma_free_chan_resources(struct dma_chan *chan) -{ - struct udma_chan *uc = to_udma_chan(chan); - struct udma_dev *ud = to_udma_dev(chan->device); - - udma_terminate_all(chan); - if (uc->terminated_desc) { - udma_reset_chan(uc, false); - udma_reset_rings(uc); - } - - cancel_delayed_work_sync(&uc->tx_drain.work); - - if (uc->irq_num_ring > 0) { - free_irq(uc->irq_num_ring, uc); - - uc->irq_num_ring = 0; - } - if (uc->irq_num_udma > 0) { - free_irq(uc->irq_num_udma, uc); - - uc->irq_num_udma = 0; - } - - /* Release PSI-L pairing */ - if (uc->psil_paired) { - navss_psil_unpair(ud, uc->config.src_thread, - uc->config.dst_thread); - uc->psil_paired = false; - } - - vchan_free_chan_resources(&uc->vc); - tasklet_kill(&uc->vc.task); - - bcdma_free_bchan_resources(uc); - udma_free_tx_resources(uc); - udma_free_rx_resources(uc); - udma_reset_uchan(uc); - - if (uc->use_dma_pool) { - dma_pool_destroy(uc->hdesc_pool); - uc->use_dma_pool = false; - } -} - static struct platform_driver udma_driver; static struct platform_driver bcdma_driver; static struct platform_driver pktdma_driver; -struct udma_filter_param { - int remote_thread_id; - u32 atype; - u32 asel; - u32 tr_trigger_type; -}; - static bool udma_dma_filter_fn(struct dma_chan *chan, void *param) { struct udma_chan_config *ucc; @@ -4410,6 +1983,18 @@ .soc_data = &j721s2_bcdma_csi_soc_data, }; +static struct udma_match_data j722s_bcdma_csi_data = { + .type = DMA_TYPE_BCDMA, + .psil_base = 0x3100, + .enable_memcpy_support = false, + .burst_size = { + TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */ + 0, /* No H Channels */ + 0, /* No UH Channels */ + }, + .soc_data = &j721s2_bcdma_csi_soc_data, +}; + static const struct of_device_id udma_of_match[] = { { .compatible = "ti,am654-navss-main-udmap", @@ -4441,6 +2026,10 @@ .compatible = "ti,j721s2-dmss-bcdma-csi", .data = &j721s2_bcdma_csi_data, }, + { + .compatible = "ti,j722s-dmss-bcdma-csi", + .data = &j722s_bcdma_csi_data, + }, { /* Sentinel */ }, }; MODULE_DEVICE_TABLE(of, udma_of_match); @@ -4545,813 +2134,6 @@ return 0; } -static void udma_mark_resource_ranges(struct udma_dev *ud, unsigned long *map, - struct ti_sci_resource_desc *rm_desc, - char *name) -{ - bitmap_clear(map, rm_desc->start, rm_desc->num); - bitmap_clear(map, rm_desc->start_sec, rm_desc->num_sec); - dev_dbg(ud->dev, "ti_sci resource range for %s: %d:%d | %d:%d\n", name, - rm_desc->start, rm_desc->num, rm_desc->start_sec, - rm_desc->num_sec); -} - -static const char * const range_names[] = { - [RM_RANGE_BCHAN] = "ti,sci-rm-range-bchan", - [RM_RANGE_TCHAN] = "ti,sci-rm-range-tchan", - [RM_RANGE_RCHAN] = "ti,sci-rm-range-rchan", - [RM_RANGE_RFLOW] = "ti,sci-rm-range-rflow", - [RM_RANGE_TFLOW] = "ti,sci-rm-range-tflow", -}; - -static int udma_setup_resources(struct udma_dev *ud) -{ - int ret, i, j; - struct device *dev = ud->dev; - struct ti_sci_resource *rm_res, irq_res; - struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; - u32 cap3; - - /* Set up the throughput level start indexes */ - cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c); - if (of_device_is_compatible(dev->of_node, - "ti,am654-navss-main-udmap")) { - ud->tchan_tpl.levels = 2; - ud->tchan_tpl.start_idx[0] = 8; - } else if (of_device_is_compatible(dev->of_node, - "ti,am654-navss-mcu-udmap")) { - ud->tchan_tpl.levels = 2; - ud->tchan_tpl.start_idx[0] = 2; - } else if (UDMA_CAP3_UCHAN_CNT(cap3)) { - ud->tchan_tpl.levels = 3; - ud->tchan_tpl.start_idx[1] = UDMA_CAP3_UCHAN_CNT(cap3); - ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); - } else if (UDMA_CAP3_HCHAN_CNT(cap3)) { - ud->tchan_tpl.levels = 2; - ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); - } else { - ud->tchan_tpl.levels = 1; - } - - ud->rchan_tpl.levels = ud->tchan_tpl.levels; - ud->rchan_tpl.start_idx[0] = ud->tchan_tpl.start_idx[0]; - ud->rchan_tpl.start_idx[1] = ud->tchan_tpl.start_idx[1]; - - ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), - GFP_KERNEL); - ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), - GFP_KERNEL); - ud->rflow_gp_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rflow_cnt), - sizeof(unsigned long), - GFP_KERNEL); - ud->rflow_gp_map_allocated = devm_kcalloc(dev, - BITS_TO_LONGS(ud->rflow_cnt), - sizeof(unsigned long), - GFP_KERNEL); - ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), - sizeof(unsigned long), - GFP_KERNEL); - ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows), - GFP_KERNEL); - - if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_gp_map || - !ud->rflow_gp_map_allocated || !ud->tchans || !ud->rchans || - !ud->rflows || !ud->rflow_in_use) - return -ENOMEM; - - /* - * RX flows with the same Ids as RX channels are reserved to be used - * as default flows if remote HW can't generate flow_ids. Those - * RX flows can be requested only explicitly by id. - */ - bitmap_set(ud->rflow_gp_map_allocated, 0, ud->rchan_cnt); - - /* by default no GP rflows are assigned to Linux */ - bitmap_set(ud->rflow_gp_map, 0, ud->rflow_cnt); - - /* Get resource ranges from tisci */ - for (i = 0; i < RM_RANGE_LAST; i++) { - if (i == RM_RANGE_BCHAN || i == RM_RANGE_TFLOW) - continue; - - tisci_rm->rm_ranges[i] = - devm_ti_sci_get_of_resource(tisci_rm->tisci, dev, - tisci_rm->tisci_dev_id, - (char *)range_names[i]); - } - - /* tchan ranges */ - rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; - if (IS_ERR(rm_res)) { - bitmap_zero(ud->tchan_map, ud->tchan_cnt); - irq_res.sets = 1; - } else { - bitmap_fill(ud->tchan_map, ud->tchan_cnt); - for (i = 0; i < rm_res->sets; i++) - udma_mark_resource_ranges(ud, ud->tchan_map, - &rm_res->desc[i], "tchan"); - irq_res.sets = rm_res->sets; - } - - /* rchan and matching default flow ranges */ - rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; - if (IS_ERR(rm_res)) { - bitmap_zero(ud->rchan_map, ud->rchan_cnt); - irq_res.sets++; - } else { - bitmap_fill(ud->rchan_map, ud->rchan_cnt); - for (i = 0; i < rm_res->sets; i++) - udma_mark_resource_ranges(ud, ud->rchan_map, - &rm_res->desc[i], "rchan"); - irq_res.sets += rm_res->sets; - } - - irq_res.desc = kcalloc(irq_res.sets, sizeof(*irq_res.desc), GFP_KERNEL); - if (!irq_res.desc) - return -ENOMEM; - rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; - if (IS_ERR(rm_res)) { - irq_res.desc[0].start = 0; - irq_res.desc[0].num = ud->tchan_cnt; - i = 1; - } else { - for (i = 0; i < rm_res->sets; i++) { - irq_res.desc[i].start = rm_res->desc[i].start; - irq_res.desc[i].num = rm_res->desc[i].num; - irq_res.desc[i].start_sec = rm_res->desc[i].start_sec; - irq_res.desc[i].num_sec = rm_res->desc[i].num_sec; - } - } - rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; - if (IS_ERR(rm_res)) { - irq_res.desc[i].start = 0; - irq_res.desc[i].num = ud->rchan_cnt; - } else { - for (j = 0; j < rm_res->sets; j++, i++) { - if (rm_res->desc[j].num) { - irq_res.desc[i].start = rm_res->desc[j].start + - ud->soc_data->oes.udma_rchan; - irq_res.desc[i].num = rm_res->desc[j].num; - } - if (rm_res->desc[j].num_sec) { - irq_res.desc[i].start_sec = rm_res->desc[j].start_sec + - ud->soc_data->oes.udma_rchan; - irq_res.desc[i].num_sec = rm_res->desc[j].num_sec; - } - } - } - ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res); - kfree(irq_res.desc); - if (ret) { - dev_err(ud->dev, "Failed to allocate MSI interrupts\n"); - return ret; - } - - /* GP rflow ranges */ - rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW]; - if (IS_ERR(rm_res)) { - /* all gp flows are assigned exclusively to Linux */ - bitmap_clear(ud->rflow_gp_map, ud->rchan_cnt, - ud->rflow_cnt - ud->rchan_cnt); - } else { - for (i = 0; i < rm_res->sets; i++) - udma_mark_resource_ranges(ud, ud->rflow_gp_map, - &rm_res->desc[i], "gp-rflow"); - } - - return 0; -} - -static int bcdma_setup_resources(struct udma_dev *ud) -{ - int ret, i, j; - struct device *dev = ud->dev; - struct ti_sci_resource *rm_res, irq_res; - struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; - const struct udma_oes_offsets *oes = &ud->soc_data->oes; - u32 cap; - - /* Set up the throughput level start indexes */ - cap = udma_read(ud->mmrs[MMR_GCFG], 0x2c); - if (BCDMA_CAP3_UBCHAN_CNT(cap)) { - ud->bchan_tpl.levels = 3; - ud->bchan_tpl.start_idx[1] = BCDMA_CAP3_UBCHAN_CNT(cap); - ud->bchan_tpl.start_idx[0] = BCDMA_CAP3_HBCHAN_CNT(cap); - } else if (BCDMA_CAP3_HBCHAN_CNT(cap)) { - ud->bchan_tpl.levels = 2; - ud->bchan_tpl.start_idx[0] = BCDMA_CAP3_HBCHAN_CNT(cap); - } else { - ud->bchan_tpl.levels = 1; - } - - cap = udma_read(ud->mmrs[MMR_GCFG], 0x30); - if (BCDMA_CAP4_URCHAN_CNT(cap)) { - ud->rchan_tpl.levels = 3; - ud->rchan_tpl.start_idx[1] = BCDMA_CAP4_URCHAN_CNT(cap); - ud->rchan_tpl.start_idx[0] = BCDMA_CAP4_HRCHAN_CNT(cap); - } else if (BCDMA_CAP4_HRCHAN_CNT(cap)) { - ud->rchan_tpl.levels = 2; - ud->rchan_tpl.start_idx[0] = BCDMA_CAP4_HRCHAN_CNT(cap); - } else { - ud->rchan_tpl.levels = 1; - } - - if (BCDMA_CAP4_UTCHAN_CNT(cap)) { - ud->tchan_tpl.levels = 3; - ud->tchan_tpl.start_idx[1] = BCDMA_CAP4_UTCHAN_CNT(cap); - ud->tchan_tpl.start_idx[0] = BCDMA_CAP4_HTCHAN_CNT(cap); - } else if (BCDMA_CAP4_HTCHAN_CNT(cap)) { - ud->tchan_tpl.levels = 2; - ud->tchan_tpl.start_idx[0] = BCDMA_CAP4_HTCHAN_CNT(cap); - } else { - ud->tchan_tpl.levels = 1; - } - - ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->bchans = devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans), - GFP_KERNEL); - ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), - GFP_KERNEL); - ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), - GFP_KERNEL); - /* BCDMA do not really have flows, but the driver expect it */ - ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt), - sizeof(unsigned long), - GFP_KERNEL); - ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows), - GFP_KERNEL); - - if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map || - !ud->rflow_in_use || !ud->bchans || !ud->tchans || !ud->rchans || - !ud->rflows) - return -ENOMEM; - - /* Get resource ranges from tisci */ - for (i = 0; i < RM_RANGE_LAST; i++) { - if (i == RM_RANGE_RFLOW || i == RM_RANGE_TFLOW) - continue; - if (i == RM_RANGE_BCHAN && ud->bchan_cnt == 0) - continue; - if (i == RM_RANGE_TCHAN && ud->tchan_cnt == 0) - continue; - if (i == RM_RANGE_RCHAN && ud->rchan_cnt == 0) - continue; - - tisci_rm->rm_ranges[i] = - devm_ti_sci_get_of_resource(tisci_rm->tisci, dev, - tisci_rm->tisci_dev_id, - (char *)range_names[i]); - } - - irq_res.sets = 0; - - /* bchan ranges */ - if (ud->bchan_cnt) { - rm_res = tisci_rm->rm_ranges[RM_RANGE_BCHAN]; - if (IS_ERR(rm_res)) { - bitmap_zero(ud->bchan_map, ud->bchan_cnt); - irq_res.sets++; - } else { - bitmap_fill(ud->bchan_map, ud->bchan_cnt); - for (i = 0; i < rm_res->sets; i++) - udma_mark_resource_ranges(ud, ud->bchan_map, - &rm_res->desc[i], - "bchan"); - irq_res.sets += rm_res->sets; - } - } - - /* tchan ranges */ - if (ud->tchan_cnt) { - rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; - if (IS_ERR(rm_res)) { - bitmap_zero(ud->tchan_map, ud->tchan_cnt); - irq_res.sets += 2; - } else { - bitmap_fill(ud->tchan_map, ud->tchan_cnt); - for (i = 0; i < rm_res->sets; i++) - udma_mark_resource_ranges(ud, ud->tchan_map, - &rm_res->desc[i], - "tchan"); - irq_res.sets += rm_res->sets * 2; - } - } - - /* rchan ranges */ - if (ud->rchan_cnt) { - rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; - if (IS_ERR(rm_res)) { - bitmap_zero(ud->rchan_map, ud->rchan_cnt); - irq_res.sets += 2; - } else { - bitmap_fill(ud->rchan_map, ud->rchan_cnt); - for (i = 0; i < rm_res->sets; i++) - udma_mark_resource_ranges(ud, ud->rchan_map, - &rm_res->desc[i], - "rchan"); - irq_res.sets += rm_res->sets * 2; - } - } - - irq_res.desc = kcalloc(irq_res.sets, sizeof(*irq_res.desc), GFP_KERNEL); - if (!irq_res.desc) - return -ENOMEM; - if (ud->bchan_cnt) { - rm_res = tisci_rm->rm_ranges[RM_RANGE_BCHAN]; - if (IS_ERR(rm_res)) { - irq_res.desc[0].start = oes->bcdma_bchan_ring; - irq_res.desc[0].num = ud->bchan_cnt; - i = 1; - } else { - for (i = 0; i < rm_res->sets; i++) { - irq_res.desc[i].start = rm_res->desc[i].start + - oes->bcdma_bchan_ring; - irq_res.desc[i].num = rm_res->desc[i].num; - } - } - } else { - i = 0; - } - - if (ud->tchan_cnt) { - rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; - if (IS_ERR(rm_res)) { - irq_res.desc[i].start = oes->bcdma_tchan_data; - irq_res.desc[i].num = ud->tchan_cnt; - irq_res.desc[i + 1].start = oes->bcdma_tchan_ring; - irq_res.desc[i + 1].num = ud->tchan_cnt; - i += 2; - } else { - for (j = 0; j < rm_res->sets; j++, i += 2) { - irq_res.desc[i].start = rm_res->desc[j].start + - oes->bcdma_tchan_data; - irq_res.desc[i].num = rm_res->desc[j].num; - - irq_res.desc[i + 1].start = rm_res->desc[j].start + - oes->bcdma_tchan_ring; - irq_res.desc[i + 1].num = rm_res->desc[j].num; - } - } - } - if (ud->rchan_cnt) { - rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; - if (IS_ERR(rm_res)) { - irq_res.desc[i].start = oes->bcdma_rchan_data; - irq_res.desc[i].num = ud->rchan_cnt; - irq_res.desc[i + 1].start = oes->bcdma_rchan_ring; - irq_res.desc[i + 1].num = ud->rchan_cnt; - i += 2; - } else { - for (j = 0; j < rm_res->sets; j++, i += 2) { - irq_res.desc[i].start = rm_res->desc[j].start + - oes->bcdma_rchan_data; - irq_res.desc[i].num = rm_res->desc[j].num; - - irq_res.desc[i + 1].start = rm_res->desc[j].start + - oes->bcdma_rchan_ring; - irq_res.desc[i + 1].num = rm_res->desc[j].num; - } - } - } - - ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res); - kfree(irq_res.desc); - if (ret) { - dev_err(ud->dev, "Failed to allocate MSI interrupts\n"); - return ret; - } - - return 0; -} - -static int pktdma_setup_resources(struct udma_dev *ud) -{ - int ret, i, j; - struct device *dev = ud->dev; - struct ti_sci_resource *rm_res, irq_res; - struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; - const struct udma_oes_offsets *oes = &ud->soc_data->oes; - u32 cap3; - - /* Set up the throughput level start indexes */ - cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c); - if (UDMA_CAP3_UCHAN_CNT(cap3)) { - ud->tchan_tpl.levels = 3; - ud->tchan_tpl.start_idx[1] = UDMA_CAP3_UCHAN_CNT(cap3); - ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); - } else if (UDMA_CAP3_HCHAN_CNT(cap3)) { - ud->tchan_tpl.levels = 2; - ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); - } else { - ud->tchan_tpl.levels = 1; - } - - ud->rchan_tpl.levels = ud->tchan_tpl.levels; - ud->rchan_tpl.start_idx[0] = ud->tchan_tpl.start_idx[0]; - ud->rchan_tpl.start_idx[1] = ud->tchan_tpl.start_idx[1]; - - ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), - GFP_KERNEL); - ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), - GFP_KERNEL); - ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), - sizeof(unsigned long), - GFP_KERNEL); - ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows), - GFP_KERNEL); - ud->tflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt), - sizeof(unsigned long), GFP_KERNEL); - - if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans || - !ud->rchans || !ud->rflows || !ud->rflow_in_use) - return -ENOMEM; - - /* Get resource ranges from tisci */ - for (i = 0; i < RM_RANGE_LAST; i++) { - if (i == RM_RANGE_BCHAN) - continue; - - tisci_rm->rm_ranges[i] = - devm_ti_sci_get_of_resource(tisci_rm->tisci, dev, - tisci_rm->tisci_dev_id, - (char *)range_names[i]); - } - - /* tchan ranges */ - rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; - if (IS_ERR(rm_res)) { - bitmap_zero(ud->tchan_map, ud->tchan_cnt); - } else { - bitmap_fill(ud->tchan_map, ud->tchan_cnt); - for (i = 0; i < rm_res->sets; i++) - udma_mark_resource_ranges(ud, ud->tchan_map, - &rm_res->desc[i], "tchan"); - } - - /* rchan ranges */ - rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; - if (IS_ERR(rm_res)) { - bitmap_zero(ud->rchan_map, ud->rchan_cnt); - } else { - bitmap_fill(ud->rchan_map, ud->rchan_cnt); - for (i = 0; i < rm_res->sets; i++) - udma_mark_resource_ranges(ud, ud->rchan_map, - &rm_res->desc[i], "rchan"); - } - - /* rflow ranges */ - rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW]; - if (IS_ERR(rm_res)) { - /* all rflows are assigned exclusively to Linux */ - bitmap_zero(ud->rflow_in_use, ud->rflow_cnt); - irq_res.sets = 1; - } else { - bitmap_fill(ud->rflow_in_use, ud->rflow_cnt); - for (i = 0; i < rm_res->sets; i++) - udma_mark_resource_ranges(ud, ud->rflow_in_use, - &rm_res->desc[i], "rflow"); - irq_res.sets = rm_res->sets; - } - - /* tflow ranges */ - rm_res = tisci_rm->rm_ranges[RM_RANGE_TFLOW]; - if (IS_ERR(rm_res)) { - /* all tflows are assigned exclusively to Linux */ - bitmap_zero(ud->tflow_map, ud->tflow_cnt); - irq_res.sets++; - } else { - bitmap_fill(ud->tflow_map, ud->tflow_cnt); - for (i = 0; i < rm_res->sets; i++) - udma_mark_resource_ranges(ud, ud->tflow_map, - &rm_res->desc[i], "tflow"); - irq_res.sets += rm_res->sets; - } - - irq_res.desc = kcalloc(irq_res.sets, sizeof(*irq_res.desc), GFP_KERNEL); - if (!irq_res.desc) - return -ENOMEM; - rm_res = tisci_rm->rm_ranges[RM_RANGE_TFLOW]; - if (IS_ERR(rm_res)) { - irq_res.desc[0].start = oes->pktdma_tchan_flow; - irq_res.desc[0].num = ud->tflow_cnt; - i = 1; - } else { - for (i = 0; i < rm_res->sets; i++) { - irq_res.desc[i].start = rm_res->desc[i].start + - oes->pktdma_tchan_flow; - irq_res.desc[i].num = rm_res->desc[i].num; - } - } - rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW]; - if (IS_ERR(rm_res)) { - irq_res.desc[i].start = oes->pktdma_rchan_flow; - irq_res.desc[i].num = ud->rflow_cnt; - } else { - for (j = 0; j < rm_res->sets; j++, i++) { - irq_res.desc[i].start = rm_res->desc[j].start + - oes->pktdma_rchan_flow; - irq_res.desc[i].num = rm_res->desc[j].num; - } - } - ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res); - kfree(irq_res.desc); - if (ret) { - dev_err(ud->dev, "Failed to allocate MSI interrupts\n"); - return ret; - } - - return 0; -} - -static int setup_resources(struct udma_dev *ud) -{ - struct device *dev = ud->dev; - int ch_count, ret; - - switch (ud->match_data->type) { - case DMA_TYPE_UDMA: - ret = udma_setup_resources(ud); - break; - case DMA_TYPE_BCDMA: - ret = bcdma_setup_resources(ud); - break; - case DMA_TYPE_PKTDMA: - ret = pktdma_setup_resources(ud); - break; - default: - return -EINVAL; - } - - if (ret) - return ret; - - ch_count = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt; - if (ud->bchan_cnt) - ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt); - ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt); - ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt); - if (!ch_count) - return -ENODEV; - - ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels), - GFP_KERNEL); - if (!ud->channels) - return -ENOMEM; - - switch (ud->match_data->type) { - case DMA_TYPE_UDMA: - dev_info(dev, - "Channels: %d (tchan: %u, rchan: %u, gp-rflow: %u)\n", - ch_count, - ud->tchan_cnt - bitmap_weight(ud->tchan_map, - ud->tchan_cnt), - ud->rchan_cnt - bitmap_weight(ud->rchan_map, - ud->rchan_cnt), - ud->rflow_cnt - bitmap_weight(ud->rflow_gp_map, - ud->rflow_cnt)); - break; - case DMA_TYPE_BCDMA: - dev_info(dev, - "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n", - ch_count, - ud->bchan_cnt - bitmap_weight(ud->bchan_map, - ud->bchan_cnt), - ud->tchan_cnt - bitmap_weight(ud->tchan_map, - ud->tchan_cnt), - ud->rchan_cnt - bitmap_weight(ud->rchan_map, - ud->rchan_cnt)); - break; - case DMA_TYPE_PKTDMA: - dev_info(dev, - "Channels: %d (tchan: %u, rchan: %u)\n", - ch_count, - ud->tchan_cnt - bitmap_weight(ud->tchan_map, - ud->tchan_cnt), - ud->rchan_cnt - bitmap_weight(ud->rchan_map, - ud->rchan_cnt)); - break; - default: - break; - } - - return ch_count; -} - -static int udma_setup_rx_flush(struct udma_dev *ud) -{ - struct udma_rx_flush *rx_flush = &ud->rx_flush; - struct cppi5_desc_hdr_t *tr_desc; - struct cppi5_tr_type1_t *tr_req; - struct cppi5_host_desc_t *desc; - struct device *dev = ud->dev; - struct udma_hwdesc *hwdesc; - size_t tr_size; - - /* Allocate 1K buffer for discarded data on RX channel teardown */ - rx_flush->buffer_size = SZ_1K; - rx_flush->buffer_vaddr = devm_kzalloc(dev, rx_flush->buffer_size, - GFP_KERNEL); - if (!rx_flush->buffer_vaddr) - return -ENOMEM; - - rx_flush->buffer_paddr = dma_map_single(dev, rx_flush->buffer_vaddr, - rx_flush->buffer_size, - DMA_TO_DEVICE); - if (dma_mapping_error(dev, rx_flush->buffer_paddr)) - return -ENOMEM; - - /* Set up descriptor to be used for TR mode */ - hwdesc = &rx_flush->hwdescs[0]; - tr_size = sizeof(struct cppi5_tr_type1_t); - hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size, 1); - hwdesc->cppi5_desc_size = ALIGN(hwdesc->cppi5_desc_size, - ud->desc_align); - - hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size, - GFP_KERNEL); - if (!hwdesc->cppi5_desc_vaddr) - return -ENOMEM; - - hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr, - hwdesc->cppi5_desc_size, - DMA_TO_DEVICE); - if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr)) - return -ENOMEM; - - /* Start of the TR req records */ - hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size; - /* Start address of the TR response array */ - hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size; - - tr_desc = hwdesc->cppi5_desc_vaddr; - cppi5_trdesc_init(tr_desc, 1, tr_size, 0, 0); - cppi5_desc_set_pktids(tr_desc, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT); - cppi5_desc_set_retpolicy(tr_desc, 0, 0); - - tr_req = hwdesc->tr_req_base; - cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false, - CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT); - - tr_req->addr = rx_flush->buffer_paddr; - tr_req->icnt0 = rx_flush->buffer_size; - tr_req->icnt1 = 1; - - dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr, - hwdesc->cppi5_desc_size, DMA_TO_DEVICE); - - /* Set up descriptor to be used for packet mode */ - hwdesc = &rx_flush->hwdescs[1]; - hwdesc->cppi5_desc_size = ALIGN(sizeof(struct cppi5_host_desc_t) + - CPPI5_INFO0_HDESC_EPIB_SIZE + - CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE, - ud->desc_align); - - hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size, - GFP_KERNEL); - if (!hwdesc->cppi5_desc_vaddr) - return -ENOMEM; - - hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr, - hwdesc->cppi5_desc_size, - DMA_TO_DEVICE); - if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr)) - return -ENOMEM; - - desc = hwdesc->cppi5_desc_vaddr; - cppi5_hdesc_init(desc, 0, 0); - cppi5_desc_set_pktids(&desc->hdr, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT); - cppi5_desc_set_retpolicy(&desc->hdr, 0, 0); - - cppi5_hdesc_attach_buf(desc, - rx_flush->buffer_paddr, rx_flush->buffer_size, - rx_flush->buffer_paddr, rx_flush->buffer_size); - - dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr, - hwdesc->cppi5_desc_size, DMA_TO_DEVICE); - return 0; -} - -#ifdef CONFIG_DEBUG_FS -static void udma_dbg_summary_show_chan(struct seq_file *s, - struct dma_chan *chan) -{ - struct udma_chan *uc = to_udma_chan(chan); - struct udma_chan_config *ucc = &uc->config; - - seq_printf(s, " %-13s| %s", dma_chan_name(chan), - chan->dbg_client_name ?: "in-use"); - if (ucc->tr_trigger_type) - seq_puts(s, " (triggered, "); - else - seq_printf(s, " (%s, ", - dmaengine_get_direction_text(uc->config.dir)); - - switch (uc->config.dir) { - case DMA_MEM_TO_MEM: - if (uc->ud->match_data->type == DMA_TYPE_BCDMA) { - seq_printf(s, "bchan%d)\n", uc->bchan->id); - return; - } - - seq_printf(s, "chan%d pair [0x%04x -> 0x%04x], ", uc->tchan->id, - ucc->src_thread, ucc->dst_thread); - break; - case DMA_DEV_TO_MEM: - seq_printf(s, "rchan%d [0x%04x -> 0x%04x], ", uc->rchan->id, - ucc->src_thread, ucc->dst_thread); - if (uc->ud->match_data->type == DMA_TYPE_PKTDMA) - seq_printf(s, "rflow%d, ", uc->rflow->id); - break; - case DMA_MEM_TO_DEV: - seq_printf(s, "tchan%d [0x%04x -> 0x%04x], ", uc->tchan->id, - ucc->src_thread, ucc->dst_thread); - if (uc->ud->match_data->type == DMA_TYPE_PKTDMA) - seq_printf(s, "tflow%d, ", uc->tchan->tflow_id); - break; - default: - seq_printf(s, ")\n"); - return; - } - - if (ucc->ep_type == PSIL_EP_NATIVE) { - seq_printf(s, "PSI-L Native"); - if (ucc->metadata_size) { - seq_printf(s, "[%s", ucc->needs_epib ? " EPIB" : ""); - if (ucc->psd_size) - seq_printf(s, " PSDsize:%u", ucc->psd_size); - seq_printf(s, " ]"); - } - } else { - seq_printf(s, "PDMA"); - if (ucc->enable_acc32 || ucc->enable_burst) - seq_printf(s, "[%s%s ]", - ucc->enable_acc32 ? " ACC32" : "", - ucc->enable_burst ? " BURST" : ""); - } - - seq_printf(s, ", %s)\n", ucc->pkt_mode ? "Packet mode" : "TR mode"); -} - -static void udma_dbg_summary_show(struct seq_file *s, - struct dma_device *dma_dev) -{ - struct dma_chan *chan; - - list_for_each_entry(chan, &dma_dev->channels, device_node) { - if (chan->client_count) - udma_dbg_summary_show_chan(s, chan); - } -} -#endif /* CONFIG_DEBUG_FS */ - -static enum dmaengine_alignment udma_get_copy_align(struct udma_dev *ud) -{ - const struct udma_match_data *match_data = ud->match_data; - u8 tpl; - - if (!match_data->enable_memcpy_support) - return DMAENGINE_ALIGN_8_BYTES; - - /* Get the highest TPL level the device supports for memcpy */ - if (ud->bchan_cnt) - tpl = udma_get_chan_tpl_index(&ud->bchan_tpl, 0); - else if (ud->tchan_cnt) - tpl = udma_get_chan_tpl_index(&ud->tchan_tpl, 0); - else - return DMAENGINE_ALIGN_8_BYTES; - - switch (match_data->burst_size[tpl]) { - case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES: - return DMAENGINE_ALIGN_256_BYTES; - case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES: - return DMAENGINE_ALIGN_128_BYTES; - case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES: - fallthrough; - default: - return DMAENGINE_ALIGN_64_BYTES; - } -} - -#define TI_UDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ - BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) - static int udma_probe(struct platform_device *pdev) { struct device_node *navss_node = pdev->dev.parent->of_node; @@ -5387,6 +2169,13 @@ ud->soc_data = soc->data; } + // Setup function pointers + ud->udma_start = udma_start; + ud->udma_stop = udma_stop; + ud->udma_reset_chan = udma_reset_chan; + ud->udma_is_desc_really_done = udma_is_desc_really_done; + ud->udma_decrement_byte_counters = udma_decrement_byte_counters; + ret = udma_get_mmrs(pdev, ud); if (ret) return ret; @@ -5432,7 +2221,7 @@ if (ud->match_data->type == DMA_TYPE_UDMA) { ud->ringacc = of_k3_ringacc_get_by_phandle(dev->of_node, "ti,ringacc"); } else { - struct k3_ringacc_init_data ring_init_data; + struct k3_ringacc_init_data ring_init_data = { 0 }; ring_init_data.tisci = ud->tisci_rm.tisci; ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id; @@ -5665,6 +2454,3 @@ module_platform_driver(udma_driver); MODULE_DESCRIPTION("Texas Instruments UDMA support"); MODULE_LICENSE("GPL v2"); - -/* Private interfaces to UDMA */ -#include "k3-udma-private.c" diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/dma/ti/k3-udma-common.c v_kernel/drivers/dma/ti/k3-udma-common.c --- linux-6.12.57/drivers/dma/ti/k3-udma-common.c 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/dma/ti/k3-udma-common.c 2026-04-21 11:35:36.144935205 +0200 @@ -0,0 +1,3024 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com + * Author: Peter Ujfalusi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../virt-dma.h" +#include "k3-udma.h" +#include "k3-psil-priv.h" + +static const char * const range_names[] = { + [RM_RANGE_BCHAN] = "ti,sci-rm-range-bchan", + [RM_RANGE_TCHAN] = "ti,sci-rm-range-tchan", + [RM_RANGE_RCHAN] = "ti,sci-rm-range-rchan", + [RM_RANGE_RFLOW] = "ti,sci-rm-range-rflow", + [RM_RANGE_TFLOW] = "ti,sci-rm-range-tflow", +}; + +void k3_configure_chan_coherency(struct dma_chan *chan, u32 asel) +{ + struct device *chan_dev = &chan->dev->device; + + if (asel == 0) { + /* No special handling for the channel */ + chan->dev->chan_dma_dev = false; + + chan_dev->dma_coherent = false; + chan_dev->dma_parms = NULL; + } else if (asel == 14 || asel == 15) { + chan->dev->chan_dma_dev = true; + + chan_dev->dma_coherent = true; + dma_coerce_mask_and_coherent(chan_dev, DMA_BIT_MASK(48)); + chan_dev->dma_parms = chan_dev->parent->dma_parms; + } else { + dev_warn(chan->device->dev, "Invalid ASEL value: %u\n", asel); + + chan_dev->dma_coherent = false; + chan_dev->dma_parms = NULL; + } +} + +u8 udma_get_chan_tpl_index(struct udma_tpl *tpl_map, int chan_id) +{ + int i; + + for (i = 0; i < tpl_map->levels; i++) { + if (chan_id >= tpl_map->start_idx[i]) + return i; + } + + return 0; +} + +void udma_reset_uchan(struct udma_chan *uc) +{ + memset(&uc->config, 0, sizeof(uc->config)); + uc->config.remote_thread_id = -1; + uc->config.mapped_channel_id = -1; + uc->config.default_flow_id = -1; + uc->state = UDMA_CHAN_IS_IDLE; +} + +void udma_dump_chan_stdata(struct udma_chan *uc) +{ + struct device *dev = uc->ud->dev; + u32 offset; + int i; + + if (uc->config.dir == DMA_MEM_TO_DEV || uc->config.dir == DMA_MEM_TO_MEM) { + dev_dbg(dev, "TCHAN State data:\n"); + for (i = 0; i < 32; i++) { + offset = UDMA_CHAN_RT_STDATA_REG + i * 4; + dev_dbg(dev, "TRT_STDATA[%02d]: 0x%08x\n", i, + udma_tchanrt_read(uc, offset)); + } + } + + if (uc->config.dir == DMA_DEV_TO_MEM || uc->config.dir == DMA_MEM_TO_MEM) { + dev_dbg(dev, "RCHAN State data:\n"); + for (i = 0; i < 32; i++) { + offset = UDMA_CHAN_RT_STDATA_REG + i * 4; + dev_dbg(dev, "RRT_STDATA[%02d]: 0x%08x\n", i, + udma_rchanrt_read(uc, offset)); + } + } +} + +struct udma_desc *udma_udma_desc_from_paddr(struct udma_chan *uc, + dma_addr_t paddr) +{ + struct udma_desc *d = uc->terminated_desc; + + if (d) { + dma_addr_t desc_paddr = udma_curr_cppi5_desc_paddr(d, + d->desc_idx); + + if (desc_paddr != paddr) + d = NULL; + } + + if (!d) { + d = uc->desc; + if (d) { + dma_addr_t desc_paddr = udma_curr_cppi5_desc_paddr(d, + d->desc_idx); + + if (desc_paddr != paddr) + d = NULL; + } + } + + return d; +} + +void udma_free_hwdesc(struct udma_chan *uc, struct udma_desc *d) +{ + if (uc->use_dma_pool) { + int i; + + for (i = 0; i < d->hwdesc_count; i++) { + if (!d->hwdesc[i].cppi5_desc_vaddr) + continue; + + dma_pool_free(uc->hdesc_pool, + d->hwdesc[i].cppi5_desc_vaddr, + d->hwdesc[i].cppi5_desc_paddr); + + d->hwdesc[i].cppi5_desc_vaddr = NULL; + } + } else if (d->hwdesc[0].cppi5_desc_vaddr) { + dma_free_coherent(uc->dma_dev, d->hwdesc[0].cppi5_desc_size, + d->hwdesc[0].cppi5_desc_vaddr, + d->hwdesc[0].cppi5_desc_paddr); + + d->hwdesc[0].cppi5_desc_vaddr = NULL; + } +} + +void udma_purge_desc_work(struct work_struct *work) +{ + struct udma_dev *ud = container_of(work, typeof(*ud), purge_work); + struct virt_dma_desc *vd, *_vd; + unsigned long flags; + LIST_HEAD(head); + + spin_lock_irqsave(&ud->lock, flags); + list_splice_tail_init(&ud->desc_to_purge, &head); + spin_unlock_irqrestore(&ud->lock, flags); + + list_for_each_entry_safe(vd, _vd, &head, node) { + struct udma_chan *uc = to_udma_chan(vd->tx.chan); + struct udma_desc *d = to_udma_desc(&vd->tx); + + udma_free_hwdesc(uc, d); + list_del(&vd->node); + kfree(d); + } + + /* If more to purge, schedule the work again */ + if (!list_empty(&ud->desc_to_purge)) + schedule_work(&ud->purge_work); +} + +void udma_desc_free(struct virt_dma_desc *vd) +{ + struct udma_dev *ud = to_udma_dev(vd->tx.chan->device); + struct udma_chan *uc = to_udma_chan(vd->tx.chan); + struct udma_desc *d = to_udma_desc(&vd->tx); + unsigned long flags; + + if (uc->terminated_desc == d) + uc->terminated_desc = NULL; + + if (uc->use_dma_pool) { + udma_free_hwdesc(uc, d); + kfree(d); + return; + } + + spin_lock_irqsave(&ud->lock, flags); + list_add_tail(&vd->node, &ud->desc_to_purge); + spin_unlock_irqrestore(&ud->lock, flags); + + schedule_work(&ud->purge_work); +} + +bool udma_is_chan_running(struct udma_chan *uc) +{ + u32 trt_ctl = 0; + u32 rrt_ctl = 0; + + if (uc->tchan) + trt_ctl = udma_tchanrt_read(uc, UDMA_CHAN_RT_CTL_REG); + if (uc->rchan) + rrt_ctl = udma_rchanrt_read(uc, UDMA_CHAN_RT_CTL_REG); + + if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN) + return true; + + return false; +} + +void udma_reset_rings(struct udma_chan *uc) +{ + struct k3_ring *ring1 = NULL; + struct k3_ring *ring2 = NULL; + + switch (uc->config.dir) { + case DMA_DEV_TO_MEM: + if (uc->rchan) { + ring1 = uc->rflow->fd_ring; + ring2 = uc->rflow->r_ring; + } + break; + case DMA_MEM_TO_DEV: + case DMA_MEM_TO_MEM: + if (uc->tchan) { + ring1 = uc->tchan->t_ring; + ring2 = uc->tchan->tc_ring; + } + break; + default: + break; + } + + if (ring1) + k3_ringacc_ring_reset_dma(ring1, + k3_ringacc_ring_get_occ(ring1)); + if (ring2) + k3_ringacc_ring_reset(ring2); + + /* make sure we are not leaking memory by stalled descriptor */ + if (uc->terminated_desc) { + udma_desc_free(&uc->terminated_desc->vd); + uc->terminated_desc = NULL; + } +} + +int udma_push_to_ring(struct udma_chan *uc, int idx) +{ + struct udma_desc *d = uc->desc; + struct k3_ring *ring = NULL; + dma_addr_t paddr; + + switch (uc->config.dir) { + case DMA_DEV_TO_MEM: + ring = uc->rflow->fd_ring; + break; + case DMA_MEM_TO_DEV: + case DMA_MEM_TO_MEM: + ring = uc->tchan->t_ring; + break; + default: + return -EINVAL; + } + + /* RX flush packet: idx == -1 is only passed in case of DEV_TO_MEM */ + if (idx == -1) { + paddr = udma_get_rx_flush_hwdesc_paddr(uc); + } else { + paddr = udma_curr_cppi5_desc_paddr(d, idx); + + wmb(); /* Ensure that writes are not moved over this point */ + } + + return k3_ringacc_ring_push(ring, &paddr); +} + +bool udma_desc_is_rx_flush(struct udma_chan *uc, dma_addr_t addr) +{ + if (uc->config.dir != DMA_DEV_TO_MEM) + return false; + + if (addr == udma_get_rx_flush_hwdesc_paddr(uc)) + return true; + + return false; +} + +int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr) +{ + struct k3_ring *ring = NULL; + int ret; + + switch (uc->config.dir) { + case DMA_DEV_TO_MEM: + ring = uc->rflow->r_ring; + break; + case DMA_MEM_TO_DEV: + case DMA_MEM_TO_MEM: + ring = uc->tchan->tc_ring; + break; + default: + return -ENOENT; + } + + ret = k3_ringacc_ring_pop(ring, addr); + if (ret) + return ret; + + rmb(); /* Ensure that reads are not moved before this point */ + + /* Teardown completion */ + if (cppi5_desc_is_tdcm(*addr)) + return 0; + + /* Check for flush descriptor */ + if (udma_desc_is_rx_flush(uc, *addr)) + return -ENOENT; + + return 0; +} + +void udma_start_desc(struct udma_chan *uc) +{ + struct udma_chan_config *ucc = &uc->config; + + if (uc->ud->match_data->type == DMA_TYPE_UDMA && ucc->pkt_mode && + (uc->cyclic || ucc->dir == DMA_DEV_TO_MEM)) { + int i; + + /* + * UDMA only: Push all descriptors to ring for packet mode + * cyclic or RX + * PKTDMA supports pre-linked descriptor and cyclic is not + * supported + */ + for (i = 0; i < uc->desc->sglen; i++) + udma_push_to_ring(uc, i); + } else { + udma_push_to_ring(uc, 0); + } +} + +bool udma_chan_needs_reconfiguration(struct udma_chan *uc) +{ + /* Only PDMAs have staticTR */ + if (uc->config.ep_type == PSIL_EP_NATIVE) + return false; + + /* Check if the staticTR configuration has changed for TX */ + if (memcmp(&uc->static_tr, &uc->desc->static_tr, sizeof(uc->static_tr))) + return true; + + return false; +} + +void udma_cyclic_packet_elapsed(struct udma_chan *uc) +{ + struct udma_desc *d = uc->desc; + struct cppi5_host_desc_t *h_desc; + + h_desc = d->hwdesc[d->desc_idx].cppi5_desc_vaddr; + cppi5_hdesc_reset_to_original(h_desc); + udma_push_to_ring(uc, d->desc_idx); + d->desc_idx = (d->desc_idx + 1) % d->sglen; +} + +void udma_check_tx_completion(struct work_struct *work) +{ + struct udma_chan *uc = container_of(work, typeof(*uc), + tx_drain.work.work); + struct udma_dev *ud = uc->ud; + bool desc_done = true; + u32 residue_diff; + ktime_t time_diff; + unsigned long delay; + unsigned long flags; + + while (1) { + spin_lock_irqsave(&uc->vc.lock, flags); + + if (uc->desc) { + /* Get previous residue and time stamp */ + residue_diff = uc->tx_drain.residue; + time_diff = uc->tx_drain.tstamp; + /* + * Get current residue and time stamp or see if + * transfer is complete + */ + desc_done = ud->udma_is_desc_really_done(uc, uc->desc); + } + + if (!desc_done) { + /* + * Find the time delta and residue delta w.r.t + * previous poll + */ + time_diff = ktime_sub(uc->tx_drain.tstamp, + time_diff) + 1; + residue_diff -= uc->tx_drain.residue; + if (residue_diff) { + /* + * Try to guess when we should check + * next time by calculating rate at + * which data is being drained at the + * peer device + */ + delay = (time_diff / residue_diff) * + uc->tx_drain.residue; + } else { + /* No progress, check again in 1 second */ + schedule_delayed_work(&uc->tx_drain.work, HZ); + break; + } + + spin_unlock_irqrestore(&uc->vc.lock, flags); + + usleep_range(ktime_to_us(delay), + ktime_to_us(delay) + 10); + continue; + } + + if (uc->desc) { + struct udma_desc *d = uc->desc; + + ud->udma_decrement_byte_counters(uc, d->residue); + ud->udma_start(uc); + vchan_cookie_complete(&d->vd); + break; + } + + break; + } + + spin_unlock_irqrestore(&uc->vc.lock, flags); +} + +/** + * __udma_alloc_gp_rflow_range - alloc range of GP RX flows + * @ud: UDMA device + * @from: Start the search from this flow id number + * @cnt: Number of consecutive flow ids to allocate + * + * Allocate range of RX flow ids for future use, those flows can be requested + * only using explicit flow id number. if @from is set to -1 it will try to find + * first free range. if @from is positive value it will force allocation only + * of the specified range of flows. + * + * Returns -ENOMEM if can't find free range. + * -EEXIST if requested range is busy. + * -EINVAL if wrong input values passed. + * Returns flow id on success. + */ +int __udma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt) +{ + int start, tmp_from; + DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS); + + tmp_from = from; + if (tmp_from < 0) + tmp_from = ud->rchan_cnt; + /* default flows can't be allocated and accessible only by id */ + if (tmp_from < ud->rchan_cnt) + return -EINVAL; + + if (tmp_from + cnt > ud->rflow_cnt) + return -EINVAL; + + bitmap_or(tmp, ud->rflow_gp_map, ud->rflow_gp_map_allocated, + ud->rflow_cnt); + + start = bitmap_find_next_zero_area(tmp, + ud->rflow_cnt, + tmp_from, cnt, 0); + if (start >= ud->rflow_cnt) + return -ENOMEM; + + if (from >= 0 && start != from) + return -EEXIST; + + bitmap_set(ud->rflow_gp_map_allocated, start, cnt); + return start; +} + +int __udma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt) +{ + if (from < ud->rchan_cnt) + return -EINVAL; + if (from + cnt > ud->rflow_cnt) + return -EINVAL; + + bitmap_clear(ud->rflow_gp_map_allocated, from, cnt); + return 0; +} + +struct udma_rflow *__udma_get_rflow(struct udma_dev *ud, int id) +{ + /* + * Attempt to request rflow by ID can be made for any rflow + * if not in use with assumption that caller knows what's doing. + * TI-SCI FW will perform additional permission check ant way, it's + * safe + */ + + if (id < 0 || id >= ud->rflow_cnt) + return ERR_PTR(-ENOENT); + + if (test_bit(id, ud->rflow_in_use)) + return ERR_PTR(-ENOENT); + + if (ud->rflow_gp_map) { + /* GP rflow has to be allocated first */ + if (!test_bit(id, ud->rflow_gp_map) && + !test_bit(id, ud->rflow_gp_map_allocated)) + return ERR_PTR(-EINVAL); + } + + dev_dbg(ud->dev, "get rflow%d\n", id); + set_bit(id, ud->rflow_in_use); + return &ud->rflows[id]; +} + +void __udma_put_rflow(struct udma_dev *ud, struct udma_rflow *rflow) +{ + if (!test_bit(rflow->id, ud->rflow_in_use)) { + dev_err(ud->dev, "attempt to put unused rflow%d\n", rflow->id); + return; + } + + dev_dbg(ud->dev, "put rflow%d\n", rflow->id); + clear_bit(rflow->id, ud->rflow_in_use); +} + +#define UDMA_RESERVE_RESOURCE(res) \ +struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \ + enum udma_tp_level tpl, \ + int id) \ +{ \ + if (id >= 0) { \ + if (test_bit(id, ud->res##_map)) { \ + dev_err(ud->dev, "res##%d is in use\n", id); \ + return ERR_PTR(-ENOENT); \ + } \ + } else { \ + int start; \ + \ + if (tpl >= ud->res##_tpl.levels) \ + tpl = ud->res##_tpl.levels - 1; \ + \ + start = ud->res##_tpl.start_idx[tpl]; \ + \ + id = find_next_zero_bit(ud->res##_map, ud->res##_cnt, \ + start); \ + if (id == ud->res##_cnt) { \ + return ERR_PTR(-ENOENT); \ + } \ + } \ + \ + set_bit(id, ud->res##_map); \ + return &ud->res##s[id]; \ +} + +UDMA_RESERVE_RESOURCE(bchan); +UDMA_RESERVE_RESOURCE(tchan); +UDMA_RESERVE_RESOURCE(rchan); + +int udma_get_tchan(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + int ret; + + if (uc->tchan) { + dev_dbg(ud->dev, "chan%d: already have tchan%d allocated\n", + uc->id, uc->tchan->id); + return 0; + } + + /* + * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels. + * For PKTDMA mapped channels it is configured to a channel which must + * be used to service the peripheral. + */ + uc->tchan = __udma_reserve_tchan(ud, uc->config.channel_tpl, + uc->config.mapped_channel_id); + if (IS_ERR(uc->tchan)) { + ret = PTR_ERR(uc->tchan); + uc->tchan = NULL; + return ret; + } + if (ud->match_data->type == DMA_TYPE_BCDMA_V2) + uc->chan = uc->tchan; + + if (ud->tflow_cnt) { + int tflow_id; + + /* Only PKTDMA have support for tx flows */ + if (uc->config.default_flow_id >= 0) + tflow_id = uc->config.default_flow_id; + else + tflow_id = uc->tchan->id; + + if (test_bit(tflow_id, ud->tflow_map)) { + dev_err(ud->dev, "tflow%d is in use\n", tflow_id); + clear_bit(uc->tchan->id, ud->tchan_map); + uc->tchan = NULL; + return -ENOENT; + } + + uc->tchan->tflow_id = tflow_id; + set_bit(tflow_id, ud->tflow_map); + } else { + uc->tchan->tflow_id = -1; + } + + return 0; +} + +int udma_get_rchan(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + int ret; + + if (uc->rchan) { + dev_dbg(ud->dev, "chan%d: already have rchan%d allocated\n", + uc->id, uc->rchan->id); + return 0; + } + + /* + * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels. + * For PKTDMA mapped channels it is configured to a channel which must + * be used to service the peripheral. + */ + uc->rchan = __udma_reserve_rchan(ud, uc->config.channel_tpl, + uc->config.mapped_channel_id); + if (IS_ERR(uc->rchan)) { + ret = PTR_ERR(uc->rchan); + uc->rchan = NULL; + return ret; + } + if (ud->match_data->type == DMA_TYPE_BCDMA_V2) + uc->chan = uc->rchan; + + return 0; +} + +int udma_get_chan_pair(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + int chan_id, end; + + if ((uc->tchan && uc->rchan) && uc->tchan->id == uc->rchan->id) { + dev_info(ud->dev, "chan%d: already have %d pair allocated\n", + uc->id, uc->tchan->id); + return 0; + } + + if (uc->tchan) { + dev_err(ud->dev, "chan%d: already have tchan%d allocated\n", + uc->id, uc->tchan->id); + return -EBUSY; + } else if (uc->rchan) { + dev_err(ud->dev, "chan%d: already have rchan%d allocated\n", + uc->id, uc->rchan->id); + return -EBUSY; + } + + /* Can be optimized, but let's have it like this for now */ + end = min(ud->tchan_cnt, ud->rchan_cnt); + /* + * Try to use the highest TPL channel pair for MEM_TO_MEM channels + * Note: in UDMAP the channel TPL is symmetric between tchan and rchan + */ + chan_id = ud->tchan_tpl.start_idx[ud->tchan_tpl.levels - 1]; + for (; chan_id < end; chan_id++) { + if (!test_bit(chan_id, ud->tchan_map) && + !test_bit(chan_id, ud->rchan_map)) + break; + } + + if (chan_id == end) + return -ENOENT; + + set_bit(chan_id, ud->tchan_map); + set_bit(chan_id, ud->rchan_map); + uc->tchan = &ud->tchans[chan_id]; + uc->rchan = &ud->rchans[chan_id]; + + /* UDMA does not use tx flows */ + uc->tchan->tflow_id = -1; + + return 0; +} + +int udma_get_rflow(struct udma_chan *uc, int flow_id) +{ + struct udma_dev *ud = uc->ud; + int ret; + + if (!uc->rchan) { + dev_err(ud->dev, "chan%d: does not have rchan??\n", uc->id); + return -EINVAL; + } + + if (uc->rflow) { + dev_dbg(ud->dev, "chan%d: already have rflow%d allocated\n", + uc->id, uc->rflow->id); + return 0; + } + + uc->rflow = __udma_get_rflow(ud, flow_id); + if (IS_ERR(uc->rflow)) { + ret = PTR_ERR(uc->rflow); + uc->rflow = NULL; + return ret; + } + + return 0; +} + +void bcdma_put_bchan(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + + if (uc->bchan) { + dev_dbg(ud->dev, "chan%d: put bchan%d\n", uc->id, + uc->bchan->id); + clear_bit(uc->bchan->id, ud->bchan_map); + uc->bchan = NULL; + uc->tchan = NULL; + } +} + +void udma_put_rchan(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + + if (uc->rchan) { + dev_dbg(ud->dev, "chan%d: put rchan%d\n", uc->id, + uc->rchan->id); + clear_bit(uc->rchan->id, ud->rchan_map); + uc->rchan = NULL; + } +} + +void udma_put_tchan(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + + if (uc->tchan) { + dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id, + uc->tchan->id); + clear_bit(uc->tchan->id, ud->tchan_map); + + if (uc->tchan->tflow_id >= 0) + clear_bit(uc->tchan->tflow_id, ud->tflow_map); + + uc->tchan = NULL; + } +} + +void udma_put_rflow(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + + if (uc->rflow) { + dev_dbg(ud->dev, "chan%d: put rflow%d\n", uc->id, + uc->rflow->id); + __udma_put_rflow(ud, uc->rflow); + uc->rflow = NULL; + } +} + +void bcdma_free_bchan_resources(struct udma_chan *uc) +{ + if (!uc->bchan) + return; + + k3_ringacc_ring_free(uc->bchan->tc_ring); + k3_ringacc_ring_free(uc->bchan->t_ring); + uc->bchan->tc_ring = NULL; + uc->bchan->t_ring = NULL; + k3_configure_chan_coherency(&uc->vc.chan, 0); + + bcdma_put_bchan(uc); +} + +void udma_free_tx_resources(struct udma_chan *uc) +{ + if (!uc->tchan) + return; + + k3_ringacc_ring_free(uc->tchan->t_ring); + k3_ringacc_ring_free(uc->tchan->tc_ring); + uc->tchan->t_ring = NULL; + uc->tchan->tc_ring = NULL; + + udma_put_tchan(uc); +} + +void udma_free_rx_resources(struct udma_chan *uc) +{ + if (!uc->rchan) + return; + + if (uc->rflow) { + struct udma_rflow *rflow = uc->rflow; + + k3_ringacc_ring_free(rflow->fd_ring); + k3_ringacc_ring_free(rflow->r_ring); + rflow->fd_ring = NULL; + rflow->r_ring = NULL; + + udma_put_rflow(uc); + } + + udma_put_rchan(uc); +} + +int udma_slave_config(struct dma_chan *chan, + struct dma_slave_config *cfg) +{ + struct udma_chan *uc = to_udma_chan(chan); + + memcpy(&uc->cfg, cfg, sizeof(uc->cfg)); + + return 0; +} + +struct udma_desc *udma_alloc_tr_desc(struct udma_chan *uc, + size_t tr_size, int tr_count, + enum dma_transfer_direction dir) +{ + struct udma_hwdesc *hwdesc; + struct cppi5_desc_hdr_t *tr_desc; + struct udma_desc *d; + u32 reload_count = 0; + u32 ring_id; + + switch (tr_size) { + case 16: + case 32: + case 64: + case 128: + break; + default: + dev_err(uc->ud->dev, "Unsupported TR size of %zu\n", tr_size); + return NULL; + } + + /* We have only one descriptor containing multiple TRs */ + d = kzalloc(sizeof(*d) + sizeof(d->hwdesc[0]), GFP_NOWAIT); + if (!d) + return NULL; + + d->sglen = tr_count; + + d->hwdesc_count = 1; + hwdesc = &d->hwdesc[0]; + + /* Allocate memory for DMA ring descriptor */ + if (uc->use_dma_pool) { + hwdesc->cppi5_desc_size = uc->config.hdesc_size; + hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool, + GFP_NOWAIT, + &hwdesc->cppi5_desc_paddr); + } else { + hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size, + tr_count); + hwdesc->cppi5_desc_size = ALIGN(hwdesc->cppi5_desc_size, + uc->ud->desc_align); + hwdesc->cppi5_desc_vaddr = dma_alloc_coherent(uc->ud->dev, + hwdesc->cppi5_desc_size, + &hwdesc->cppi5_desc_paddr, + GFP_NOWAIT); + } + + if (!hwdesc->cppi5_desc_vaddr) { + kfree(d); + return NULL; + } + + /* Start of the TR req records */ + hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size; + /* Start address of the TR response array */ + hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size * tr_count; + + tr_desc = hwdesc->cppi5_desc_vaddr; + + if (uc->cyclic) + reload_count = CPPI5_INFO0_TRDESC_RLDCNT_INFINITE; + + if (dir == DMA_DEV_TO_MEM) + ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring); + else + ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring); + + cppi5_trdesc_init(tr_desc, tr_count, tr_size, 0, reload_count); + cppi5_desc_set_pktids(tr_desc, uc->id, + CPPI5_INFO1_DESC_FLOWID_DEFAULT); + cppi5_desc_set_retpolicy(tr_desc, 0, ring_id); + + return d; +} + +/** + * udma_get_tr_counters - calculate TR counters for a given length + * @uc: udma chan + * @len: Length of the trasnfer + * @align_to: Preferred alignment + * @tr0_cnt0: First TR icnt0 + * @tr0_cnt1: First TR icnt1 + * @tr1_cnt0: Second (if used) TR icnt0 + * + * For len < SZ_64K only one TR is enough, tr1_cnt0 is not updated + * + * For len >= SZ_64K && cyclic == false: + * First TR: SZ_64K-alignment blocks (tr0_cnt0, tr0_cnt1) + * Second TR: the remaining length (tr1_cnt0) + * + * For len >= SZ_64K && cyclic == true: + * Transfer is split into 2 equal sized TRs. + * + * Limits: In case of cyclic mode, the maximum supported length is + * (SZ_128K - 2) = 131070 bytes, because the split logic relies on fitting + * half the length into a 16-bit counter. + * + * Returns the number of TRs the length needs (1 or 2) + * -EINVAL if the length can not be supported + */ +int udma_get_tr_counters(struct udma_chan *uc, size_t len, + unsigned long align_to, u16 *tr0_cnt0, u16 *tr0_cnt1, + u16 *tr1_cnt0) +{ + if (len < SZ_64K) { + *tr0_cnt0 = len; + *tr0_cnt1 = 1; + + return 1; + } + + if (uc->config.ep_type != PSIL_EP_NATIVE && uc->cyclic) { + u32 dev_width, elcnt; + + if (uc->config.dir == DMA_DEV_TO_MEM) { + dev_width = uc->cfg.src_addr_width; + elcnt = uc->cfg.src_maxburst ? uc->cfg.src_maxburst : 1; + } else if (uc->config.dir == DMA_MEM_TO_DEV) { + dev_width = uc->cfg.dst_addr_width; + elcnt = uc->cfg.dst_maxburst ? uc->cfg.dst_maxburst : 1; + } else { + return -EINVAL; + } + + /* + * In case of cyclic mode: + * For transfers >= 64K, we must use equal-sized TRs and + * the icnt0 should be divisible by dev_width and the maxburst. + * This is required for the static x, y and `bstcnt` logic in + * `udma_configure_statictr` to be valid. + * And transfers >= 131070 bytes (128K - 2) requires more than 2 + * TRs in case of cyclic mode. and the current logic doesn't + * support it. + */ + if ((len % (2 * dev_width * elcnt) != 0) || + (len > SZ_128K - 2)) + return -EINVAL; + + *tr0_cnt0 = len / 2; + *tr0_cnt1 = 1; + *tr1_cnt0 = len - *tr0_cnt0; + + return 2; + } + + /* Non cyclic mode or PSIL_EP_NATIVE*/ + if (align_to > 3) + align_to = 3; + +realign: + *tr0_cnt0 = SZ_64K - BIT(align_to); + if (len / *tr0_cnt0 >= SZ_64K) { + if (align_to) { + align_to--; + goto realign; + } + return -EINVAL; + } + + *tr0_cnt1 = len / *tr0_cnt0; + *tr1_cnt0 = len % *tr0_cnt0; + + return 2; +} + +struct udma_desc * +udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl, + unsigned int sglen, enum dma_transfer_direction dir, + unsigned long tx_flags, void *context) +{ + struct scatterlist *sgent; + struct udma_desc *d; + struct cppi5_tr_type1_t *tr_req = NULL; + u16 tr0_cnt0, tr0_cnt1, tr1_cnt0; + unsigned int i; + size_t tr_size; + int num_tr = 0; + int tr_idx = 0; + u32 extra_flags = 0; + u64 asel; + + /* estimate the number of TRs we will need */ + for_each_sg(sgl, sgent, sglen, i) { + if (sg_dma_len(sgent) < SZ_64K) + num_tr++; + else + num_tr += 2; + } + + /* Now allocate and setup the descriptor. */ + tr_size = sizeof(struct cppi5_tr_type1_t); + d = udma_alloc_tr_desc(uc, tr_size, num_tr, dir); + if (!d) + return NULL; + + d->sglen = sglen; + + if (uc->ud->match_data->type == DMA_TYPE_UDMA) + asel = 0; + else + asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; + + if (dir == DMA_MEM_TO_DEV && uc->ud->match_data->type == DMA_TYPE_BCDMA_V2) + extra_flags = CPPI5_TR_CSF_EOP; + + tr_req = d->hwdesc[0].tr_req_base; + for_each_sg(sgl, sgent, sglen, i) { + dma_addr_t sg_addr = sg_dma_address(sgent); + + num_tr = udma_get_tr_counters(uc, sg_dma_len(sgent), __ffs(sg_addr), + &tr0_cnt0, &tr0_cnt1, &tr1_cnt0); + if (num_tr < 0) { + dev_err(uc->ud->dev, "size %u is not supported\n", + sg_dma_len(sgent)); + udma_free_hwdesc(uc, d); + kfree(d); + return NULL; + } + + cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false, + false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT | extra_flags); + + sg_addr |= asel; + tr_req[tr_idx].addr = sg_addr; + tr_req[tr_idx].icnt0 = tr0_cnt0; + tr_req[tr_idx].icnt1 = tr0_cnt1; + tr_req[tr_idx].dim1 = tr0_cnt0; + tr_idx++; + + if (num_tr == 2) { + cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, + false, false, + CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + cppi5_tr_csf_set(&tr_req[tr_idx].flags, + CPPI5_TR_CSF_SUPR_EVT | extra_flags); + + tr_req[tr_idx].addr = sg_addr + tr0_cnt1 * tr0_cnt0; + tr_req[tr_idx].icnt0 = tr1_cnt0; + tr_req[tr_idx].icnt1 = 1; + tr_req[tr_idx].dim1 = tr1_cnt0; + tr_idx++; + } + + d->residue += sg_dma_len(sgent); + } + + cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, + CPPI5_TR_CSF_SUPR_EVT | CPPI5_TR_CSF_EOP); + + return d; +} + +struct udma_desc * +udma_prep_slave_sg_triggered_tr(struct udma_chan *uc, struct scatterlist *sgl, + unsigned int sglen, + enum dma_transfer_direction dir, + unsigned long tx_flags, void *context) +{ + struct scatterlist *sgent; + struct cppi5_tr_type15_t *tr_req = NULL; + enum dma_slave_buswidth dev_width; + u32 csf = CPPI5_TR_CSF_SUPR_EVT; + u16 tr_cnt0, tr_cnt1; + dma_addr_t dev_addr; + struct udma_desc *d; + unsigned int i; + size_t tr_size, sg_len; + int num_tr = 0; + int tr_idx = 0; + u32 burst, trigger_size, port_window; + u64 asel; + + if (dir == DMA_DEV_TO_MEM) { + dev_addr = uc->cfg.src_addr; + dev_width = uc->cfg.src_addr_width; + burst = uc->cfg.src_maxburst; + port_window = uc->cfg.src_port_window_size; + } else if (dir == DMA_MEM_TO_DEV) { + dev_addr = uc->cfg.dst_addr; + dev_width = uc->cfg.dst_addr_width; + burst = uc->cfg.dst_maxburst; + port_window = uc->cfg.dst_port_window_size; + } else { + dev_err(uc->ud->dev, "%s: bad direction?\n", __func__); + return NULL; + } + + if (!burst) + burst = 1; + + if (port_window) { + if (port_window != burst) { + dev_err(uc->ud->dev, + "The burst must be equal to port_window\n"); + return NULL; + } + + tr_cnt0 = dev_width * port_window; + tr_cnt1 = 1; + } else { + tr_cnt0 = dev_width; + tr_cnt1 = burst; + } + trigger_size = tr_cnt0 * tr_cnt1; + + /* estimate the number of TRs we will need */ + for_each_sg(sgl, sgent, sglen, i) { + sg_len = sg_dma_len(sgent); + + if (sg_len % trigger_size) { + dev_err(uc->ud->dev, + "Not aligned SG entry (%zu for %u)\n", sg_len, + trigger_size); + return NULL; + } + + if (sg_len / trigger_size < SZ_64K) + num_tr++; + else + num_tr += 2; + } + + /* Now allocate and setup the descriptor. */ + tr_size = sizeof(struct cppi5_tr_type15_t); + d = udma_alloc_tr_desc(uc, tr_size, num_tr, dir); + if (!d) + return NULL; + + d->sglen = sglen; + + if (uc->ud->match_data->type == DMA_TYPE_UDMA) { + asel = 0; + csf |= CPPI5_TR_CSF_EOL_ICNT0; + } else { + asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; + dev_addr |= asel; + } + + tr_req = d->hwdesc[0].tr_req_base; + for_each_sg(sgl, sgent, sglen, i) { + u16 tr0_cnt2, tr0_cnt3, tr1_cnt2; + dma_addr_t sg_addr = sg_dma_address(sgent); + + sg_len = sg_dma_len(sgent); + num_tr = udma_get_tr_counters(uc, sg_len / trigger_size, 0, + &tr0_cnt2, &tr0_cnt3, &tr1_cnt2); + if (num_tr < 0) { + dev_err(uc->ud->dev, "size %zu is not supported\n", + sg_len); + udma_free_hwdesc(uc, d); + kfree(d); + return NULL; + } + + cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, false, + true, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + cppi5_tr_csf_set(&tr_req[tr_idx].flags, csf); + cppi5_tr_set_trigger(&tr_req[tr_idx].flags, + uc->config.tr_trigger_type, + CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC, 0, 0); + + sg_addr |= asel; + if (dir == DMA_DEV_TO_MEM) { + tr_req[tr_idx].addr = dev_addr; + tr_req[tr_idx].icnt0 = tr_cnt0; + tr_req[tr_idx].icnt1 = tr_cnt1; + tr_req[tr_idx].icnt2 = tr0_cnt2; + tr_req[tr_idx].icnt3 = tr0_cnt3; + tr_req[tr_idx].dim1 = (-1) * tr_cnt0; + + tr_req[tr_idx].daddr = sg_addr; + tr_req[tr_idx].dicnt0 = tr_cnt0; + tr_req[tr_idx].dicnt1 = tr_cnt1; + tr_req[tr_idx].dicnt2 = tr0_cnt2; + tr_req[tr_idx].dicnt3 = tr0_cnt3; + tr_req[tr_idx].ddim1 = tr_cnt0; + tr_req[tr_idx].ddim2 = trigger_size; + tr_req[tr_idx].ddim3 = trigger_size * tr0_cnt2; + } else { + tr_req[tr_idx].addr = sg_addr; + tr_req[tr_idx].icnt0 = tr_cnt0; + tr_req[tr_idx].icnt1 = tr_cnt1; + tr_req[tr_idx].icnt2 = tr0_cnt2; + tr_req[tr_idx].icnt3 = tr0_cnt3; + tr_req[tr_idx].dim1 = tr_cnt0; + tr_req[tr_idx].dim2 = trigger_size; + tr_req[tr_idx].dim3 = trigger_size * tr0_cnt2; + + tr_req[tr_idx].daddr = dev_addr; + tr_req[tr_idx].dicnt0 = tr_cnt0; + tr_req[tr_idx].dicnt1 = tr_cnt1; + tr_req[tr_idx].dicnt2 = tr0_cnt2; + tr_req[tr_idx].dicnt3 = tr0_cnt3; + tr_req[tr_idx].ddim1 = (-1) * tr_cnt0; + } + + tr_idx++; + + if (num_tr == 2) { + cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, + false, true, + CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + cppi5_tr_csf_set(&tr_req[tr_idx].flags, csf); + cppi5_tr_set_trigger(&tr_req[tr_idx].flags, + uc->config.tr_trigger_type, + CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC, + 0, 0); + + sg_addr += trigger_size * tr0_cnt2 * tr0_cnt3; + if (dir == DMA_DEV_TO_MEM) { + tr_req[tr_idx].addr = dev_addr; + tr_req[tr_idx].icnt0 = tr_cnt0; + tr_req[tr_idx].icnt1 = tr_cnt1; + tr_req[tr_idx].icnt2 = tr1_cnt2; + tr_req[tr_idx].icnt3 = 1; + tr_req[tr_idx].dim1 = (-1) * tr_cnt0; + + tr_req[tr_idx].daddr = sg_addr; + tr_req[tr_idx].dicnt0 = tr_cnt0; + tr_req[tr_idx].dicnt1 = tr_cnt1; + tr_req[tr_idx].dicnt2 = tr1_cnt2; + tr_req[tr_idx].dicnt3 = 1; + tr_req[tr_idx].ddim1 = tr_cnt0; + tr_req[tr_idx].ddim2 = trigger_size; + } else { + tr_req[tr_idx].addr = sg_addr; + tr_req[tr_idx].icnt0 = tr_cnt0; + tr_req[tr_idx].icnt1 = tr_cnt1; + tr_req[tr_idx].icnt2 = tr1_cnt2; + tr_req[tr_idx].icnt3 = 1; + tr_req[tr_idx].dim1 = tr_cnt0; + tr_req[tr_idx].dim2 = trigger_size; + + tr_req[tr_idx].daddr = dev_addr; + tr_req[tr_idx].dicnt0 = tr_cnt0; + tr_req[tr_idx].dicnt1 = tr_cnt1; + tr_req[tr_idx].dicnt2 = tr1_cnt2; + tr_req[tr_idx].dicnt3 = 1; + tr_req[tr_idx].ddim1 = (-1) * tr_cnt0; + } + tr_idx++; + } + + d->residue += sg_len; + } + + cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, csf | CPPI5_TR_CSF_EOP); + + return d; +} + +int udma_configure_statictr(struct udma_chan *uc, struct udma_desc *d, + enum dma_slave_buswidth dev_width, + u16 elcnt) +{ + if (uc->config.ep_type != PSIL_EP_PDMA_XY) + return 0; + + /* Bus width translates to the element size (ES) */ + switch (dev_width) { + case DMA_SLAVE_BUSWIDTH_1_BYTE: + d->static_tr.elsize = 0; + break; + case DMA_SLAVE_BUSWIDTH_2_BYTES: + d->static_tr.elsize = 1; + break; + case DMA_SLAVE_BUSWIDTH_3_BYTES: + d->static_tr.elsize = 2; + break; + case DMA_SLAVE_BUSWIDTH_4_BYTES: + d->static_tr.elsize = 3; + break; + case DMA_SLAVE_BUSWIDTH_8_BYTES: + d->static_tr.elsize = 4; + break; + default: /* not reached */ + return -EINVAL; + } + + d->static_tr.elcnt = elcnt; + + if (uc->config.pkt_mode || !uc->cyclic) { + /* + * PDMA must close the packet when the channel is in packet mode. + * For TR mode when the channel is not cyclic we also need PDMA + * to close the packet otherwise the transfer will stall because + * PDMA holds on the data it has received from the peripheral. + */ + unsigned int div = dev_width * elcnt; + + if (uc->cyclic) + d->static_tr.bstcnt = d->residue / d->sglen / div; + else + d->static_tr.bstcnt = d->residue / div; + } else if ((uc->ud->match_data->type == DMA_TYPE_BCDMA || + uc->ud->match_data->type == DMA_TYPE_BCDMA_V2) && + uc->config.dir == DMA_DEV_TO_MEM && + uc->cyclic) { + /* + * For cyclic mode with BCDMA we have to set EOP in each TR to + * prevent short packet errors seen on channel teardown. So the + * PDMA must close the packet after every TR transfer by setting + * burst count equal to the number of bytes transferred. + */ + struct cppi5_tr_type1_t *tr_req = d->hwdesc[0].tr_req_base; + + d->static_tr.bstcnt = + (tr_req->icnt0 * tr_req->icnt1) / dev_width; + } else { + d->static_tr.bstcnt = 0; + } + + if (uc->config.dir == DMA_DEV_TO_MEM && + d->static_tr.bstcnt > uc->ud->match_data->statictr_z_mask) + return -EINVAL; + + return 0; +} + +struct udma_desc * +udma_prep_slave_sg_pkt(struct udma_chan *uc, struct scatterlist *sgl, + unsigned int sglen, enum dma_transfer_direction dir, + unsigned long tx_flags, void *context) +{ + struct scatterlist *sgent; + struct cppi5_host_desc_t *h_desc = NULL; + struct udma_desc *d; + u32 ring_id; + unsigned int i; + u64 asel; + + d = kzalloc(struct_size(d, hwdesc, sglen), GFP_NOWAIT); + if (!d) + return NULL; + + d->sglen = sglen; + d->hwdesc_count = sglen; + + if (dir == DMA_DEV_TO_MEM) + ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring); + else + ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring); + + if (uc->ud->match_data->type == DMA_TYPE_UDMA) + asel = 0; + else + asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; + + for_each_sg(sgl, sgent, sglen, i) { + struct udma_hwdesc *hwdesc = &d->hwdesc[i]; + dma_addr_t sg_addr = sg_dma_address(sgent); + struct cppi5_host_desc_t *desc; + size_t sg_len = sg_dma_len(sgent); + + hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool, + GFP_NOWAIT, + &hwdesc->cppi5_desc_paddr); + if (!hwdesc->cppi5_desc_vaddr) { + dev_err(uc->ud->dev, + "descriptor%d allocation failed\n", i); + + udma_free_hwdesc(uc, d); + kfree(d); + return NULL; + } + + d->residue += sg_len; + hwdesc->cppi5_desc_size = uc->config.hdesc_size; + desc = hwdesc->cppi5_desc_vaddr; + + if (i == 0) { + cppi5_hdesc_init(desc, 0, 0); + /* Flow and Packed ID */ + cppi5_desc_set_pktids(&desc->hdr, uc->id, + CPPI5_INFO1_DESC_FLOWID_DEFAULT); + cppi5_desc_set_retpolicy(&desc->hdr, 0, ring_id); + } else { + cppi5_hdesc_reset_hbdesc(desc); + cppi5_desc_set_retpolicy(&desc->hdr, 0, 0xffff); + } + + /* attach the sg buffer to the descriptor */ + sg_addr |= asel; + cppi5_hdesc_attach_buf(desc, sg_addr, sg_len, sg_addr, sg_len); + + /* Attach link as host buffer descriptor */ + if (h_desc) + cppi5_hdesc_link_hbdesc(h_desc, + hwdesc->cppi5_desc_paddr | asel); + + if (uc->ud->match_data->type == DMA_TYPE_PKTDMA || + dir == DMA_MEM_TO_DEV) + h_desc = desc; + } + + if (d->residue >= SZ_4M) { + dev_err(uc->ud->dev, + "%s: Transfer size %u is over the supported 4M range\n", + __func__, d->residue); + udma_free_hwdesc(uc, d); + kfree(d); + return NULL; + } + + h_desc = d->hwdesc[0].cppi5_desc_vaddr; + cppi5_hdesc_set_pktlen(h_desc, d->residue); + + return d; +} + +int udma_attach_metadata(struct dma_async_tx_descriptor *desc, + void *data, size_t len) +{ + struct udma_desc *d = to_udma_desc(desc); + struct udma_chan *uc = to_udma_chan(desc->chan); + struct cppi5_host_desc_t *h_desc; + u32 psd_size = len; + u32 flags = 0; + + if (!uc->config.pkt_mode || !uc->config.metadata_size) + return -EOPNOTSUPP; + + if (!data || len > uc->config.metadata_size) + return -EINVAL; + + if (uc->config.needs_epib && len < CPPI5_INFO0_HDESC_EPIB_SIZE) + return -EINVAL; + + h_desc = d->hwdesc[0].cppi5_desc_vaddr; + if (d->dir == DMA_MEM_TO_DEV) + memcpy(h_desc->epib, data, len); + + if (uc->config.needs_epib) + psd_size -= CPPI5_INFO0_HDESC_EPIB_SIZE; + + d->metadata = data; + d->metadata_size = len; + if (uc->config.needs_epib) + flags |= CPPI5_INFO0_HDESC_EPIB_PRESENT; + + cppi5_hdesc_update_flags(h_desc, flags); + cppi5_hdesc_update_psdata_size(h_desc, psd_size); + + return 0; +} + +void *udma_get_metadata_ptr(struct dma_async_tx_descriptor *desc, + size_t *payload_len, size_t *max_len) +{ + struct udma_desc *d = to_udma_desc(desc); + struct udma_chan *uc = to_udma_chan(desc->chan); + struct cppi5_host_desc_t *h_desc; + + if (!uc->config.pkt_mode || !uc->config.metadata_size) + return ERR_PTR(-EOPNOTSUPP); + + h_desc = d->hwdesc[0].cppi5_desc_vaddr; + + *max_len = uc->config.metadata_size; + + *payload_len = cppi5_hdesc_epib_present(&h_desc->hdr) ? + CPPI5_INFO0_HDESC_EPIB_SIZE : 0; + *payload_len += cppi5_hdesc_get_psdata_size(h_desc); + + return h_desc->epib; +} + +int udma_set_metadata_len(struct dma_async_tx_descriptor *desc, + size_t payload_len) +{ + struct udma_desc *d = to_udma_desc(desc); + struct udma_chan *uc = to_udma_chan(desc->chan); + struct cppi5_host_desc_t *h_desc; + u32 psd_size = payload_len; + u32 flags = 0; + + if (!uc->config.pkt_mode || !uc->config.metadata_size) + return -EOPNOTSUPP; + + if (payload_len > uc->config.metadata_size) + return -EINVAL; + + if (uc->config.needs_epib && payload_len < CPPI5_INFO0_HDESC_EPIB_SIZE) + return -EINVAL; + + h_desc = d->hwdesc[0].cppi5_desc_vaddr; + + if (uc->config.needs_epib) { + psd_size -= CPPI5_INFO0_HDESC_EPIB_SIZE; + flags |= CPPI5_INFO0_HDESC_EPIB_PRESENT; + } + + cppi5_hdesc_update_flags(h_desc, flags); + cppi5_hdesc_update_psdata_size(h_desc, psd_size); + + return 0; +} + +struct dma_descriptor_metadata_ops metadata_ops = { + .attach = udma_attach_metadata, + .get_ptr = udma_get_metadata_ptr, + .set_len = udma_set_metadata_len, +}; + +struct dma_async_tx_descriptor * +udma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sglen, enum dma_transfer_direction dir, + unsigned long tx_flags, void *context) +{ + struct udma_chan *uc = to_udma_chan(chan); + enum dma_slave_buswidth dev_width; + struct udma_desc *d; + u32 burst; + + if (dir != uc->config.dir && + (uc->config.dir == DMA_MEM_TO_MEM && !uc->config.tr_trigger_type)) { + dev_err(chan->device->dev, + "%s: chan%d is for %s, not supporting %s\n", + __func__, uc->id, + dmaengine_get_direction_text(uc->config.dir), + dmaengine_get_direction_text(dir)); + return NULL; + } + + if (dir == DMA_DEV_TO_MEM) { + dev_width = uc->cfg.src_addr_width; + burst = uc->cfg.src_maxburst; + } else if (dir == DMA_MEM_TO_DEV) { + dev_width = uc->cfg.dst_addr_width; + burst = uc->cfg.dst_maxburst; + } else { + dev_err(chan->device->dev, "%s: bad direction?\n", __func__); + return NULL; + } + + if (!burst) + burst = 1; + + uc->config.tx_flags = tx_flags; + + if (uc->config.pkt_mode) + d = udma_prep_slave_sg_pkt(uc, sgl, sglen, dir, tx_flags, + context); + else if (is_slave_direction(uc->config.dir)) + d = udma_prep_slave_sg_tr(uc, sgl, sglen, dir, tx_flags, + context); + else + d = udma_prep_slave_sg_triggered_tr(uc, sgl, sglen, dir, + tx_flags, context); + + if (!d) + return NULL; + + d->dir = dir; + d->desc_idx = 0; + d->tr_idx = 0; + + /* static TR for remote PDMA */ + if (udma_configure_statictr(uc, d, dev_width, burst)) { + dev_err(uc->ud->dev, + "%s: StaticTR Z is limited to maximum %u (%u)\n", + __func__, uc->ud->match_data->statictr_z_mask, + d->static_tr.bstcnt); + + udma_free_hwdesc(uc, d); + kfree(d); + return NULL; + } + + if (uc->config.metadata_size) + d->vd.tx.metadata_ops = &metadata_ops; + + return vchan_tx_prep(&uc->vc, &d->vd, tx_flags); +} + +struct udma_desc * +udma_prep_dma_cyclic_tr(struct udma_chan *uc, dma_addr_t buf_addr, + size_t buf_len, size_t period_len, + enum dma_transfer_direction dir, unsigned long flags) +{ + struct udma_desc *d; + size_t tr_size, period_addr; + struct cppi5_tr_type1_t *tr_req; + unsigned int periods = buf_len / period_len; + u16 tr0_cnt0, tr0_cnt1, tr1_cnt0; + unsigned int i; + int num_tr; + u32 period_csf = 0; + + num_tr = udma_get_tr_counters(uc, period_len, __ffs(buf_addr), &tr0_cnt0, + &tr0_cnt1, &tr1_cnt0); + if (num_tr < 0) { + dev_err(uc->ud->dev, "size %zu is not supported\n", period_len); + return NULL; + } + + /* Now allocate and setup the descriptor. */ + tr_size = sizeof(struct cppi5_tr_type1_t); + d = udma_alloc_tr_desc(uc, tr_size, periods * num_tr, dir); + if (!d) + return NULL; + + tr_req = d->hwdesc[0].tr_req_base; + if (uc->ud->match_data->type == DMA_TYPE_UDMA) + period_addr = buf_addr; + else + period_addr = buf_addr | + ((u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT); + + /* + * For BCDMA <-> PDMA transfers, the EOP flag needs to be set on the + * last TR of a descriptor, to mark the packet as complete. + * This is required for getting the teardown completion message in case + * of TX, and to avoid short-packet error in case of RX. + * + * As we are in cyclic mode, we do not know which period might be the + * last one, so set the flag for each period. + */ + if (uc->config.ep_type == PSIL_EP_PDMA_XY && + (uc->ud->match_data->type == DMA_TYPE_BCDMA || + uc->ud->match_data->type == DMA_TYPE_BCDMA_V2)) { + period_csf = CPPI5_TR_CSF_EOP; + } + + if (!(flags & DMA_PREP_INTERRUPT)) + period_csf |= CPPI5_TR_CSF_SUPR_EVT; + + for (i = 0; i < periods; i++) { + int tr_idx = i * num_tr; + + cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false, + false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + + tr_req[tr_idx].addr = period_addr; + tr_req[tr_idx].icnt0 = tr0_cnt0; + tr_req[tr_idx].icnt1 = tr0_cnt1; + tr_req[tr_idx].dim1 = tr0_cnt0; + + if (period_csf) + cppi5_tr_csf_set(&tr_req[tr_idx].flags, period_csf); + + if (num_tr == 2) { + tr_idx++; + + cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, + false, false, + CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + + tr_req[tr_idx].addr = period_addr + tr0_cnt1 * tr0_cnt0; + tr_req[tr_idx].icnt0 = tr1_cnt0; + tr_req[tr_idx].icnt1 = 1; + tr_req[tr_idx].dim1 = tr1_cnt0; + + if (period_csf) + cppi5_tr_csf_set(&tr_req[tr_idx].flags, period_csf); + } + + period_addr += period_len; + } + + return d; +} + +struct udma_desc * +udma_prep_dma_cyclic_pkt(struct udma_chan *uc, dma_addr_t buf_addr, + size_t buf_len, size_t period_len, + enum dma_transfer_direction dir, unsigned long flags) +{ + struct udma_desc *d; + u32 ring_id; + int i; + int periods = buf_len / period_len; + + if (periods > (K3_UDMA_DEFAULT_RING_SIZE - 1)) + return NULL; + + if (period_len >= SZ_4M) + return NULL; + + d = kzalloc(struct_size(d, hwdesc, periods), GFP_NOWAIT); + if (!d) + return NULL; + + d->hwdesc_count = periods; + + /* TODO: re-check this... */ + if (dir == DMA_DEV_TO_MEM) + ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring); + else + ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring); + + if (uc->ud->match_data->type != DMA_TYPE_UDMA) + buf_addr |= (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; + + for (i = 0; i < periods; i++) { + struct udma_hwdesc *hwdesc = &d->hwdesc[i]; + dma_addr_t period_addr = buf_addr + (period_len * i); + struct cppi5_host_desc_t *h_desc; + + hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool, + GFP_NOWAIT, + &hwdesc->cppi5_desc_paddr); + if (!hwdesc->cppi5_desc_vaddr) { + dev_err(uc->ud->dev, + "descriptor%d allocation failed\n", i); + + udma_free_hwdesc(uc, d); + kfree(d); + return NULL; + } + + hwdesc->cppi5_desc_size = uc->config.hdesc_size; + h_desc = hwdesc->cppi5_desc_vaddr; + + cppi5_hdesc_init(h_desc, 0, 0); + cppi5_hdesc_set_pktlen(h_desc, period_len); + + /* Flow and Packed ID */ + cppi5_desc_set_pktids(&h_desc->hdr, uc->id, + CPPI5_INFO1_DESC_FLOWID_DEFAULT); + cppi5_desc_set_retpolicy(&h_desc->hdr, 0, ring_id); + + /* attach each period to a new descriptor */ + cppi5_hdesc_attach_buf(h_desc, + period_addr, period_len, + period_addr, period_len); + } + + return d; +} + +struct dma_async_tx_descriptor * +udma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, + size_t period_len, enum dma_transfer_direction dir, + unsigned long flags) +{ + struct udma_chan *uc = to_udma_chan(chan); + enum dma_slave_buswidth dev_width; + struct udma_desc *d; + u32 burst; + + if (dir != uc->config.dir) { + dev_err(chan->device->dev, + "%s: chan%d is for %s, not supporting %s\n", + __func__, uc->id, + dmaengine_get_direction_text(uc->config.dir), + dmaengine_get_direction_text(dir)); + return NULL; + } + + uc->cyclic = true; + + if (dir == DMA_DEV_TO_MEM) { + dev_width = uc->cfg.src_addr_width; + burst = uc->cfg.src_maxburst; + } else if (dir == DMA_MEM_TO_DEV) { + dev_width = uc->cfg.dst_addr_width; + burst = uc->cfg.dst_maxburst; + } else { + dev_err(uc->ud->dev, "%s: bad direction?\n", __func__); + return NULL; + } + + if (!burst) + burst = 1; + + if (uc->config.pkt_mode) + d = udma_prep_dma_cyclic_pkt(uc, buf_addr, buf_len, period_len, + dir, flags); + else + d = udma_prep_dma_cyclic_tr(uc, buf_addr, buf_len, period_len, + dir, flags); + + if (!d) + return NULL; + + d->sglen = buf_len / period_len; + + d->dir = dir; + d->residue = buf_len; + + /* static TR for remote PDMA */ + if (udma_configure_statictr(uc, d, dev_width, burst)) { + dev_err(uc->ud->dev, + "%s: StaticTR Z is limited to maximum %u (%u)\n", + __func__, uc->ud->match_data->statictr_z_mask, + d->static_tr.bstcnt); + + udma_free_hwdesc(uc, d); + kfree(d); + return NULL; + } + + if (uc->config.metadata_size) + d->vd.tx.metadata_ops = &metadata_ops; + + return vchan_tx_prep(&uc->vc, &d->vd, flags); +} + +struct dma_async_tx_descriptor * +udma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, + size_t len, unsigned long tx_flags) +{ + struct udma_chan *uc = to_udma_chan(chan); + struct udma_desc *d; + struct cppi5_tr_type15_t *tr_req; + int num_tr; + size_t tr_size = sizeof(struct cppi5_tr_type15_t); + u16 tr0_cnt0, tr0_cnt1, tr1_cnt0; + u32 csf = CPPI5_TR_CSF_SUPR_EVT; + + if (uc->config.dir != DMA_MEM_TO_MEM) { + dev_err(chan->device->dev, + "%s: chan%d is for %s, not supporting %s\n", + __func__, uc->id, + dmaengine_get_direction_text(uc->config.dir), + dmaengine_get_direction_text(DMA_MEM_TO_MEM)); + return NULL; + } + + num_tr = udma_get_tr_counters(uc, len, __ffs(src | dest), &tr0_cnt0, + &tr0_cnt1, &tr1_cnt0); + if (num_tr < 0) { + dev_err(uc->ud->dev, "size %zu is not supported\n", + len); + return NULL; + } + + d = udma_alloc_tr_desc(uc, tr_size, num_tr, DMA_MEM_TO_MEM); + if (!d) + return NULL; + + d->dir = DMA_MEM_TO_MEM; + d->desc_idx = 0; + d->tr_idx = 0; + d->residue = len; + + if (uc->ud->match_data->type != DMA_TYPE_UDMA) { + src |= (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT; + dest |= (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT; + } else { + csf |= CPPI5_TR_CSF_EOL_ICNT0; + } + + tr_req = d->hwdesc[0].tr_req_base; + + cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true, + CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + cppi5_tr_csf_set(&tr_req[0].flags, csf); + + tr_req[0].addr = src; + tr_req[0].icnt0 = tr0_cnt0; + tr_req[0].icnt1 = tr0_cnt1; + tr_req[0].icnt2 = 1; + tr_req[0].icnt3 = 1; + tr_req[0].dim1 = tr0_cnt0; + + tr_req[0].daddr = dest; + tr_req[0].dicnt0 = tr0_cnt0; + tr_req[0].dicnt1 = tr0_cnt1; + tr_req[0].dicnt2 = 1; + tr_req[0].dicnt3 = 1; + tr_req[0].ddim1 = tr0_cnt0; + + if (num_tr == 2) { + cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true, + CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + cppi5_tr_csf_set(&tr_req[1].flags, csf); + + tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0; + tr_req[1].icnt0 = tr1_cnt0; + tr_req[1].icnt1 = 1; + tr_req[1].icnt2 = 1; + tr_req[1].icnt3 = 1; + + tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0; + tr_req[1].dicnt0 = tr1_cnt0; + tr_req[1].dicnt1 = 1; + tr_req[1].dicnt2 = 1; + tr_req[1].dicnt3 = 1; + } + + cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, csf | CPPI5_TR_CSF_EOP); + + if (uc->config.metadata_size) + d->vd.tx.metadata_ops = &metadata_ops; + + return vchan_tx_prep(&uc->vc, &d->vd, tx_flags); +} + +void udma_issue_pending(struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + struct udma_dev *ud = to_udma_dev(chan->device); + unsigned long flags; + + spin_lock_irqsave(&uc->vc.lock, flags); + + /* If we have something pending and no active descriptor, then */ + if (vchan_issue_pending(&uc->vc) && !uc->desc) { + /* + * start a descriptor if the channel is NOT [marked as + * terminating _and_ it is still running (teardown has not + * completed yet)]. + */ + if (!(uc->state == UDMA_CHAN_IS_TERMINATING && + udma_is_chan_running(uc))) + ud->udma_start(uc); + } + + spin_unlock_irqrestore(&uc->vc.lock, flags); +} + +int udma_terminate_all(struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + struct udma_dev *ud = to_udma_dev(chan->device); + unsigned long flags; + LIST_HEAD(head); + + spin_lock_irqsave(&uc->vc.lock, flags); + + if (udma_is_chan_running(uc)) + ud->udma_stop(uc); + + if (uc->desc) { + uc->terminated_desc = uc->desc; + uc->desc = NULL; + uc->terminated_desc->terminated = true; + cancel_delayed_work(&uc->tx_drain.work); + } + + uc->paused = false; + + vchan_get_all_descriptors(&uc->vc, &head); + spin_unlock_irqrestore(&uc->vc.lock, flags); + vchan_dma_desc_free_list(&uc->vc, &head); + + return 0; +} + +void udma_synchronize(struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + struct udma_dev *ud = to_udma_dev(chan->device); + unsigned long timeout = msecs_to_jiffies(1000); + + vchan_synchronize(&uc->vc); + + if (uc->state == UDMA_CHAN_IS_TERMINATING) { + timeout = wait_for_completion_timeout(&uc->teardown_completed, + timeout); + if (!timeout) { + dev_warn(uc->ud->dev, "chan%d teardown timeout!\n", + uc->id); + udma_dump_chan_stdata(uc); + ud->udma_reset_chan(uc, true); + } + } + + ud->udma_reset_chan(uc, false); + if (udma_is_chan_running(uc)) + dev_warn(uc->ud->dev, "chan%d refused to stop!\n", uc->id); + + cancel_delayed_work_sync(&uc->tx_drain.work); + udma_reset_rings(uc); +} + +void udma_desc_pre_callback(struct virt_dma_chan *vc, + struct virt_dma_desc *vd, + struct dmaengine_result *result) +{ + struct udma_chan *uc = to_udma_chan(&vc->chan); + struct udma_desc *d; + u8 status; + + if (!vd) + return; + + d = to_udma_desc(&vd->tx); + + if (d->metadata_size) + udma_fetch_epib(uc, d); + + if (result) { + void *desc_vaddr = udma_curr_cppi5_desc_vaddr(d, d->desc_idx); + + if (cppi5_desc_get_type(desc_vaddr) == + CPPI5_INFO0_DESC_TYPE_VAL_HOST) { + /* Provide residue information for the client */ + result->residue = d->residue - + cppi5_hdesc_get_pktlen(desc_vaddr); + if (result->residue) + result->result = DMA_TRANS_ABORTED; + else + result->result = DMA_TRANS_NOERROR; + } else { + result->residue = 0; + /* Propagate TR Response errors to the client */ + status = d->hwdesc[0].tr_resp_base->status; + if (status) + result->result = DMA_TRANS_ABORTED; + else + result->result = DMA_TRANS_NOERROR; + } + } +} + +/* + * This tasklet handles the completion of a DMA descriptor by + * calling its callback and freeing it. + */ +void udma_vchan_complete(struct tasklet_struct *t) +{ + struct virt_dma_chan *vc = from_tasklet(vc, t, task); + struct virt_dma_desc *vd, *_vd; + struct dmaengine_desc_callback cb; + LIST_HEAD(head); + + spin_lock_irq(&vc->lock); + list_splice_tail_init(&vc->desc_completed, &head); + vd = vc->cyclic; + if (vd) { + vc->cyclic = NULL; + dmaengine_desc_get_callback(&vd->tx, &cb); + } else { + memset(&cb, 0, sizeof(cb)); + } + spin_unlock_irq(&vc->lock); + + udma_desc_pre_callback(vc, vd, NULL); + dmaengine_desc_callback_invoke(&cb, NULL); + + list_for_each_entry_safe(vd, _vd, &head, node) { + struct dmaengine_result result; + + dmaengine_desc_get_callback(&vd->tx, &cb); + + list_del(&vd->node); + + udma_desc_pre_callback(vc, vd, &result); + dmaengine_desc_callback_invoke(&cb, &result); + + vchan_vdesc_fini(vd); + } +} + +void udma_free_chan_resources(struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + struct udma_dev *ud = to_udma_dev(chan->device); + + udma_terminate_all(chan); + if (uc->terminated_desc) { + ud->udma_reset_chan(uc, false); + udma_reset_rings(uc); + } + + cancel_delayed_work_sync(&uc->tx_drain.work); + + if (uc->irq_num_ring > 0) { + free_irq(uc->irq_num_ring, uc); + + uc->irq_num_ring = 0; + } + if (uc->irq_num_udma > 0) { + free_irq(uc->irq_num_udma, uc); + + uc->irq_num_udma = 0; + } + + /* Release PSI-L pairing */ + if (uc->psil_paired) { + if (ud->match_data->type < DMA_TYPE_BCDMA_V2 && IS_ENABLED(CONFIG_TI_K3_UDMA)) + navss_psil_unpair(ud, uc->config.src_thread, + uc->config.dst_thread); + uc->psil_paired = false; + } + + vchan_free_chan_resources(&uc->vc); + tasklet_kill(&uc->vc.task); + + bcdma_free_bchan_resources(uc); + udma_free_tx_resources(uc); + udma_free_rx_resources(uc); + udma_reset_uchan(uc); + + if (uc->use_dma_pool) { + dma_pool_destroy(uc->hdesc_pool); + uc->use_dma_pool = false; + } +} + +int setup_resources(struct udma_dev *ud) +{ + struct device *dev = ud->dev; + int ch_count, ret; + + switch (ud->match_data->type) { + case DMA_TYPE_UDMA: + ret = udma_setup_resources(ud); + break; + case DMA_TYPE_BCDMA: + case DMA_TYPE_BCDMA_V2: + ret = bcdma_setup_resources(ud); + break; + case DMA_TYPE_PKTDMA: + case DMA_TYPE_PKTDMA_V2: + ret = pktdma_setup_resources(ud); + break; + default: + return -EINVAL; + } + + if (ret) + return ret; + + if (ud->match_data->type >= DMA_TYPE_BCDMA_V2) { + ch_count = ud->bchan_cnt + ud->tchan_cnt; + if (ud->bchan_cnt) + ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt); + ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt); + } else { + ch_count = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt; + if (ud->bchan_cnt) + ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt); + ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt); + ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt); + } + if (!ch_count) + return -ENODEV; + + ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels), + GFP_KERNEL); + if (!ud->channels) + return -ENOMEM; + + switch (ud->match_data->type) { + case DMA_TYPE_UDMA: + dev_info(dev, + "Channels: %d (tchan: %u, rchan: %u, gp-rflow: %u)\n", + ch_count, + ud->tchan_cnt - bitmap_weight(ud->tchan_map, + ud->tchan_cnt), + ud->rchan_cnt - bitmap_weight(ud->rchan_map, + ud->rchan_cnt), + ud->rflow_cnt - bitmap_weight(ud->rflow_gp_map, + ud->rflow_cnt)); + break; + case DMA_TYPE_BCDMA: + dev_info(dev, + "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n", + ch_count, + ud->bchan_cnt - bitmap_weight(ud->bchan_map, + ud->bchan_cnt), + ud->tchan_cnt - bitmap_weight(ud->tchan_map, + ud->tchan_cnt), + ud->rchan_cnt - bitmap_weight(ud->rchan_map, + ud->rchan_cnt)); + break; + case DMA_TYPE_BCDMA_V2: + dev_info(dev, + "Channels: %d (bchan: %u, tchan + rchan: %u)\n", + ch_count, + ud->bchan_cnt - bitmap_weight(ud->bchan_map, + ud->bchan_cnt), + ud->chan_cnt - bitmap_weight(ud->chan_map, + ud->chan_cnt)); + break; + case DMA_TYPE_PKTDMA: + dev_info(dev, + "Channels: %d (tchan: %u, rchan: %u)\n", + ch_count, + ud->tchan_cnt - bitmap_weight(ud->tchan_map, + ud->tchan_cnt), + ud->rchan_cnt - bitmap_weight(ud->rchan_map, + ud->rchan_cnt)); + break; + case DMA_TYPE_PKTDMA_V2: + dev_info(dev, + "Channels: %d (tchan + rchan: %u)\n", + ch_count, + ud->chan_cnt - bitmap_weight(ud->chan_map, + ud->chan_cnt)); + break; + default: + break; + } + + return ch_count; +} + +void udma_mark_resource_ranges(struct udma_dev *ud, unsigned long *map, + struct ti_sci_resource_desc *rm_desc, + char *name) +{ + bitmap_clear(map, rm_desc->start, rm_desc->num); + bitmap_clear(map, rm_desc->start_sec, rm_desc->num_sec); + dev_dbg(ud->dev, "ti_sci resource range for %s: %d:%d | %d:%d\n", name, + rm_desc->start, rm_desc->num, rm_desc->start_sec, + rm_desc->num_sec); +} + +int udma_setup_resources(struct udma_dev *ud) +{ + int ret, i, j; + struct device *dev = ud->dev; + struct ti_sci_resource *rm_res, irq_res; + struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; + u32 cap3; + + /* Set up the throughput level start indexes */ + cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c); + if (of_device_is_compatible(dev->of_node, + "ti,am654-navss-main-udmap")) { + ud->tchan_tpl.levels = 2; + ud->tchan_tpl.start_idx[0] = 8; + } else if (of_device_is_compatible(dev->of_node, + "ti,am654-navss-mcu-udmap")) { + ud->tchan_tpl.levels = 2; + ud->tchan_tpl.start_idx[0] = 2; + } else if (UDMA_CAP3_UCHAN_CNT(cap3)) { + ud->tchan_tpl.levels = 3; + ud->tchan_tpl.start_idx[1] = UDMA_CAP3_UCHAN_CNT(cap3); + ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); + } else if (UDMA_CAP3_HCHAN_CNT(cap3)) { + ud->tchan_tpl.levels = 2; + ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); + } else { + ud->tchan_tpl.levels = 1; + } + + ud->rchan_tpl.levels = ud->tchan_tpl.levels; + ud->rchan_tpl.start_idx[0] = ud->tchan_tpl.start_idx[0]; + ud->rchan_tpl.start_idx[1] = ud->tchan_tpl.start_idx[1]; + + ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), + sizeof(unsigned long), GFP_KERNEL); + ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), + GFP_KERNEL); + ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), + sizeof(unsigned long), GFP_KERNEL); + ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), + GFP_KERNEL); + ud->rflow_gp_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rflow_cnt), + sizeof(unsigned long), + GFP_KERNEL); + ud->rflow_gp_map_allocated = devm_kcalloc(dev, + BITS_TO_LONGS(ud->rflow_cnt), + sizeof(unsigned long), + GFP_KERNEL); + ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), + sizeof(unsigned long), + GFP_KERNEL); + ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows), + GFP_KERNEL); + + if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_gp_map || + !ud->rflow_gp_map_allocated || !ud->tchans || !ud->rchans || + !ud->rflows || !ud->rflow_in_use) + return -ENOMEM; + + /* + * RX flows with the same Ids as RX channels are reserved to be used + * as default flows if remote HW can't generate flow_ids. Those + * RX flows can be requested only explicitly by id. + */ + bitmap_set(ud->rflow_gp_map_allocated, 0, ud->rchan_cnt); + + /* by default no GP rflows are assigned to Linux */ + bitmap_set(ud->rflow_gp_map, 0, ud->rflow_cnt); + + /* Get resource ranges from tisci */ + for (i = 0; i < RM_RANGE_LAST; i++) { + if (i == RM_RANGE_BCHAN || i == RM_RANGE_TFLOW) + continue; + + tisci_rm->rm_ranges[i] = + devm_ti_sci_get_of_resource(tisci_rm->tisci, dev, + tisci_rm->tisci_dev_id, + (char *)range_names[i]); + } + + /* tchan ranges */ + rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; + if (IS_ERR(rm_res)) { + bitmap_zero(ud->tchan_map, ud->tchan_cnt); + irq_res.sets = 1; + } else { + bitmap_fill(ud->tchan_map, ud->tchan_cnt); + for (i = 0; i < rm_res->sets; i++) + udma_mark_resource_ranges(ud, ud->tchan_map, + &rm_res->desc[i], "tchan"); + irq_res.sets = rm_res->sets; + } + + /* rchan and matching default flow ranges */ + rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; + if (IS_ERR(rm_res)) { + bitmap_zero(ud->rchan_map, ud->rchan_cnt); + irq_res.sets++; + } else { + bitmap_fill(ud->rchan_map, ud->rchan_cnt); + for (i = 0; i < rm_res->sets; i++) + udma_mark_resource_ranges(ud, ud->rchan_map, + &rm_res->desc[i], "rchan"); + irq_res.sets += rm_res->sets; + } + + irq_res.desc = kcalloc(irq_res.sets, sizeof(*irq_res.desc), GFP_KERNEL); + if (!irq_res.desc) + return -ENOMEM; + rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; + if (IS_ERR(rm_res)) { + irq_res.desc[0].start = 0; + irq_res.desc[0].num = ud->tchan_cnt; + i = 1; + } else { + for (i = 0; i < rm_res->sets; i++) { + irq_res.desc[i].start = rm_res->desc[i].start; + irq_res.desc[i].num = rm_res->desc[i].num; + irq_res.desc[i].start_sec = rm_res->desc[i].start_sec; + irq_res.desc[i].num_sec = rm_res->desc[i].num_sec; + } + } + rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; + if (IS_ERR(rm_res)) { + irq_res.desc[i].start = 0; + irq_res.desc[i].num = ud->rchan_cnt; + } else { + for (j = 0; j < rm_res->sets; j++, i++) { + if (rm_res->desc[j].num) { + irq_res.desc[i].start = rm_res->desc[j].start + + ud->soc_data->oes.udma_rchan; + irq_res.desc[i].num = rm_res->desc[j].num; + } + if (rm_res->desc[j].num_sec) { + irq_res.desc[i].start_sec = rm_res->desc[j].start_sec + + ud->soc_data->oes.udma_rchan; + irq_res.desc[i].num_sec = rm_res->desc[j].num_sec; + } + } + } + ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res); + kfree(irq_res.desc); + if (ret) { + dev_err(ud->dev, "Failed to allocate MSI interrupts\n"); + return ret; + } + + /* GP rflow ranges */ + rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW]; + if (IS_ERR(rm_res)) { + /* all gp flows are assigned exclusively to Linux */ + bitmap_clear(ud->rflow_gp_map, ud->rchan_cnt, + ud->rflow_cnt - ud->rchan_cnt); + } else { + for (i = 0; i < rm_res->sets; i++) + udma_mark_resource_ranges(ud, ud->rflow_gp_map, + &rm_res->desc[i], "gp-rflow"); + } + + return 0; +} + +int bcdma_setup_resources(struct udma_dev *ud) +{ + int ret, i, j; + struct device *dev = ud->dev; + struct ti_sci_resource *rm_res, irq_res; + struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; + const struct udma_oes_offsets *oes = &ud->soc_data->oes; + u32 cap; + + /* Set up the throughput level start indexes */ + cap = udma_read(ud->mmrs[MMR_GCFG], 0x2c); + if (BCDMA_CAP3_UBCHAN_CNT(cap)) { + ud->bchan_tpl.levels = 3; + ud->bchan_tpl.start_idx[1] = BCDMA_CAP3_UBCHAN_CNT(cap); + ud->bchan_tpl.start_idx[0] = BCDMA_CAP3_HBCHAN_CNT(cap); + } else if (BCDMA_CAP3_HBCHAN_CNT(cap)) { + ud->bchan_tpl.levels = 2; + ud->bchan_tpl.start_idx[0] = BCDMA_CAP3_HBCHAN_CNT(cap); + } else { + ud->bchan_tpl.levels = 1; + } + + cap = udma_read(ud->mmrs[MMR_GCFG], 0x30); + if (BCDMA_CAP4_URCHAN_CNT(cap)) { + ud->rchan_tpl.levels = 3; + ud->rchan_tpl.start_idx[1] = BCDMA_CAP4_URCHAN_CNT(cap); + ud->rchan_tpl.start_idx[0] = BCDMA_CAP4_HRCHAN_CNT(cap); + } else if (BCDMA_CAP4_HRCHAN_CNT(cap)) { + ud->rchan_tpl.levels = 2; + ud->rchan_tpl.start_idx[0] = BCDMA_CAP4_HRCHAN_CNT(cap); + } else { + ud->rchan_tpl.levels = 1; + } + + if (BCDMA_CAP4_UTCHAN_CNT(cap)) { + ud->tchan_tpl.levels = 3; + ud->tchan_tpl.start_idx[1] = BCDMA_CAP4_UTCHAN_CNT(cap); + ud->tchan_tpl.start_idx[0] = BCDMA_CAP4_HTCHAN_CNT(cap); + } else if (BCDMA_CAP4_HTCHAN_CNT(cap)) { + ud->tchan_tpl.levels = 2; + ud->tchan_tpl.start_idx[0] = BCDMA_CAP4_HTCHAN_CNT(cap); + } else { + ud->tchan_tpl.levels = 1; + } + + ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt), + sizeof(unsigned long), GFP_KERNEL); + bitmap_zero(ud->bchan_map, ud->bchan_cnt); + ud->bchans = devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans), + GFP_KERNEL); + ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), + sizeof(unsigned long), GFP_KERNEL); + bitmap_zero(ud->tchan_map, ud->tchan_cnt); + ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), + GFP_KERNEL); + if (ud->match_data->type == DMA_TYPE_BCDMA_V2) { + ud->rchan_map = ud->tchan_map; + ud->rchans = ud->tchans; + ud->chan_map = ud->tchan_map; + ud->chans = ud->tchans; + } else { + ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), + sizeof(unsigned long), GFP_KERNEL); + bitmap_zero(ud->rchan_map, ud->rchan_cnt); + ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), + GFP_KERNEL); + } + /* BCDMA do not really have flows, but the driver expect it */ + ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt), + sizeof(unsigned long), + GFP_KERNEL); + ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows), + GFP_KERNEL); + + if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map || + !ud->rflow_in_use || !ud->bchans || !ud->tchans || !ud->rchans || + !ud->rflows) + return -ENOMEM; + + if (ud->match_data->type == DMA_TYPE_BCDMA_V2) + return 0; + + /* Get resource ranges from tisci */ + for (i = 0; i < RM_RANGE_LAST; i++) { + if (i == RM_RANGE_RFLOW || i == RM_RANGE_TFLOW) + continue; + if (i == RM_RANGE_BCHAN && ud->bchan_cnt == 0) + continue; + if (i == RM_RANGE_TCHAN && ud->tchan_cnt == 0) + continue; + if (i == RM_RANGE_RCHAN && ud->rchan_cnt == 0) + continue; + + tisci_rm->rm_ranges[i] = + devm_ti_sci_get_of_resource(tisci_rm->tisci, dev, + tisci_rm->tisci_dev_id, + (char *)range_names[i]); + } + + irq_res.sets = 0; + + /* bchan ranges */ + if (ud->bchan_cnt) { + rm_res = tisci_rm->rm_ranges[RM_RANGE_BCHAN]; + if (IS_ERR(rm_res)) { + bitmap_zero(ud->bchan_map, ud->bchan_cnt); + irq_res.sets++; + } else { + bitmap_fill(ud->bchan_map, ud->bchan_cnt); + for (i = 0; i < rm_res->sets; i++) + udma_mark_resource_ranges(ud, ud->bchan_map, + &rm_res->desc[i], + "bchan"); + irq_res.sets += rm_res->sets; + } + } + + /* tchan ranges */ + if (ud->tchan_cnt) { + rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; + if (IS_ERR(rm_res)) { + bitmap_zero(ud->tchan_map, ud->tchan_cnt); + irq_res.sets += 2; + } else { + bitmap_fill(ud->tchan_map, ud->tchan_cnt); + for (i = 0; i < rm_res->sets; i++) + udma_mark_resource_ranges(ud, ud->tchan_map, + &rm_res->desc[i], + "tchan"); + irq_res.sets += rm_res->sets * 2; + } + } + + /* rchan ranges */ + if (ud->rchan_cnt) { + rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; + if (IS_ERR(rm_res)) { + bitmap_zero(ud->rchan_map, ud->rchan_cnt); + irq_res.sets += 2; + } else { + bitmap_fill(ud->rchan_map, ud->rchan_cnt); + for (i = 0; i < rm_res->sets; i++) + udma_mark_resource_ranges(ud, ud->rchan_map, + &rm_res->desc[i], + "rchan"); + irq_res.sets += rm_res->sets * 2; + } + } + + irq_res.desc = kcalloc(irq_res.sets, sizeof(*irq_res.desc), GFP_KERNEL); + if (!irq_res.desc) + return -ENOMEM; + if (ud->bchan_cnt) { + rm_res = tisci_rm->rm_ranges[RM_RANGE_BCHAN]; + if (IS_ERR(rm_res)) { + irq_res.desc[0].start = oes->bcdma_bchan_ring; + irq_res.desc[0].num = ud->bchan_cnt; + i = 1; + } else { + for (i = 0; i < rm_res->sets; i++) { + irq_res.desc[i].start = rm_res->desc[i].start + + oes->bcdma_bchan_ring; + irq_res.desc[i].num = rm_res->desc[i].num; + + if (rm_res->desc[i].num_sec) { + irq_res.desc[i].start_sec = rm_res->desc[i].start_sec + + oes->bcdma_bchan_ring; + irq_res.desc[i].num_sec = rm_res->desc[i].num_sec; + } + } + } + } else { + i = 0; + } + + if (ud->tchan_cnt) { + rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; + if (IS_ERR(rm_res)) { + irq_res.desc[i].start = oes->bcdma_tchan_data; + irq_res.desc[i].num = ud->tchan_cnt; + irq_res.desc[i + 1].start = oes->bcdma_tchan_ring; + irq_res.desc[i + 1].num = ud->tchan_cnt; + i += 2; + } else { + for (j = 0; j < rm_res->sets; j++, i += 2) { + irq_res.desc[i].start = rm_res->desc[j].start + + oes->bcdma_tchan_data; + irq_res.desc[i].num = rm_res->desc[j].num; + + irq_res.desc[i + 1].start = rm_res->desc[j].start + + oes->bcdma_tchan_ring; + irq_res.desc[i + 1].num = rm_res->desc[j].num; + + if (rm_res->desc[j].num_sec) { + irq_res.desc[i].start_sec = rm_res->desc[j].start_sec + + oes->bcdma_tchan_data; + irq_res.desc[i].num_sec = rm_res->desc[j].num_sec; + irq_res.desc[i + 1].start_sec = rm_res->desc[j].start_sec + + oes->bcdma_tchan_ring; + irq_res.desc[i + 1].num_sec = rm_res->desc[j].num_sec; + } + } + } + } + if (ud->rchan_cnt) { + rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; + if (IS_ERR(rm_res)) { + irq_res.desc[i].start = oes->bcdma_rchan_data; + irq_res.desc[i].num = ud->rchan_cnt; + irq_res.desc[i + 1].start = oes->bcdma_rchan_ring; + irq_res.desc[i + 1].num = ud->rchan_cnt; + i += 2; + } else { + for (j = 0; j < rm_res->sets; j++, i += 2) { + irq_res.desc[i].start = rm_res->desc[j].start + + oes->bcdma_rchan_data; + irq_res.desc[i].num = rm_res->desc[j].num; + + irq_res.desc[i + 1].start = rm_res->desc[j].start + + oes->bcdma_rchan_ring; + irq_res.desc[i + 1].num = rm_res->desc[j].num; + + if (rm_res->desc[j].num_sec) { + irq_res.desc[i].start_sec = rm_res->desc[j].start_sec + + oes->bcdma_rchan_data; + irq_res.desc[i].num_sec = rm_res->desc[j].num_sec; + irq_res.desc[i + 1].start_sec = rm_res->desc[j].start_sec + + oes->bcdma_rchan_ring; + irq_res.desc[i + 1].num_sec = rm_res->desc[j].num_sec; + } + } + } + } + + ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res); + kfree(irq_res.desc); + if (ret) { + dev_err(ud->dev, "Failed to allocate MSI interrupts\n"); + return ret; + } + + return 0; +} + +int pktdma_setup_resources(struct udma_dev *ud) +{ + int ret, i, j; + struct device *dev = ud->dev; + struct ti_sci_resource *rm_res, irq_res; + struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; + const struct udma_oes_offsets *oes = &ud->soc_data->oes; + u32 cap3; + + /* Set up the throughput level start indexes */ + cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c); + if (UDMA_CAP3_UCHAN_CNT(cap3)) { + ud->tchan_tpl.levels = 3; + ud->tchan_tpl.start_idx[1] = UDMA_CAP3_UCHAN_CNT(cap3); + ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); + } else if (UDMA_CAP3_HCHAN_CNT(cap3)) { + ud->tchan_tpl.levels = 2; + ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); + } else { + ud->tchan_tpl.levels = 1; + } + + ud->rchan_tpl.levels = ud->tchan_tpl.levels; + ud->rchan_tpl.start_idx[0] = ud->tchan_tpl.start_idx[0]; + ud->rchan_tpl.start_idx[1] = ud->tchan_tpl.start_idx[1]; + + ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), + sizeof(unsigned long), GFP_KERNEL); + bitmap_zero(ud->tchan_map, ud->tchan_cnt); + ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), + GFP_KERNEL); + if (ud->match_data->type == DMA_TYPE_PKTDMA_V2) { + ud->rchan_map = ud->tchan_map; + ud->rchans = ud->tchans; + ud->chan_map = ud->tchan_map; + ud->chans = ud->tchans; + } else { + ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), + sizeof(unsigned long), GFP_KERNEL); + bitmap_zero(ud->rchan_map, ud->rchan_cnt); + ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), + GFP_KERNEL); + } + ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), + sizeof(unsigned long), + GFP_KERNEL); + ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows), + GFP_KERNEL); + ud->tflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt), + sizeof(unsigned long), GFP_KERNEL); + bitmap_zero(ud->tflow_map, ud->tflow_cnt); + + if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans || + !ud->rchans || !ud->rflows || !ud->rflow_in_use) + return -ENOMEM; + + if (ud->match_data->type == DMA_TYPE_PKTDMA_V2) + return 0; + + /* Get resource ranges from tisci */ + for (i = 0; i < RM_RANGE_LAST; i++) { + if (i == RM_RANGE_BCHAN) + continue; + + tisci_rm->rm_ranges[i] = + devm_ti_sci_get_of_resource(tisci_rm->tisci, dev, + tisci_rm->tisci_dev_id, + (char *)range_names[i]); + } + + /* tchan ranges */ + rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; + if (IS_ERR(rm_res)) { + bitmap_zero(ud->tchan_map, ud->tchan_cnt); + } else { + bitmap_fill(ud->tchan_map, ud->tchan_cnt); + for (i = 0; i < rm_res->sets; i++) + udma_mark_resource_ranges(ud, ud->tchan_map, + &rm_res->desc[i], "tchan"); + } + + /* rchan ranges */ + rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; + if (IS_ERR(rm_res)) { + bitmap_zero(ud->rchan_map, ud->rchan_cnt); + } else { + bitmap_fill(ud->rchan_map, ud->rchan_cnt); + for (i = 0; i < rm_res->sets; i++) + udma_mark_resource_ranges(ud, ud->rchan_map, + &rm_res->desc[i], "rchan"); + } + + /* rflow ranges */ + rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW]; + if (IS_ERR(rm_res)) { + /* all rflows are assigned exclusively to Linux */ + bitmap_zero(ud->rflow_in_use, ud->rflow_cnt); + irq_res.sets = 1; + } else { + bitmap_fill(ud->rflow_in_use, ud->rflow_cnt); + for (i = 0; i < rm_res->sets; i++) + udma_mark_resource_ranges(ud, ud->rflow_in_use, + &rm_res->desc[i], "rflow"); + irq_res.sets = rm_res->sets; + } + + /* tflow ranges */ + rm_res = tisci_rm->rm_ranges[RM_RANGE_TFLOW]; + if (IS_ERR(rm_res)) { + /* all tflows are assigned exclusively to Linux */ + bitmap_zero(ud->tflow_map, ud->tflow_cnt); + irq_res.sets++; + } else { + bitmap_fill(ud->tflow_map, ud->tflow_cnt); + for (i = 0; i < rm_res->sets; i++) + udma_mark_resource_ranges(ud, ud->tflow_map, + &rm_res->desc[i], "tflow"); + irq_res.sets += rm_res->sets; + } + + irq_res.desc = kcalloc(irq_res.sets, sizeof(*irq_res.desc), GFP_KERNEL); + if (!irq_res.desc) + return -ENOMEM; + rm_res = tisci_rm->rm_ranges[RM_RANGE_TFLOW]; + if (IS_ERR(rm_res)) { + irq_res.desc[0].start = oes->pktdma_tchan_flow; + irq_res.desc[0].num = ud->tflow_cnt; + i = 1; + } else { + for (i = 0; i < rm_res->sets; i++) { + irq_res.desc[i].start = rm_res->desc[i].start + + oes->pktdma_tchan_flow; + irq_res.desc[i].num = rm_res->desc[i].num; + + if (rm_res->desc[i].num_sec) { + irq_res.desc[i].start_sec = rm_res->desc[i].start_sec + + oes->pktdma_tchan_flow; + irq_res.desc[i].num_sec = rm_res->desc[i].num_sec; + } + } + } + rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW]; + if (IS_ERR(rm_res)) { + irq_res.desc[i].start = oes->pktdma_rchan_flow; + irq_res.desc[i].num = ud->rflow_cnt; + } else { + for (j = 0; j < rm_res->sets; j++, i++) { + irq_res.desc[i].start = rm_res->desc[j].start + + oes->pktdma_rchan_flow; + irq_res.desc[i].num = rm_res->desc[j].num; + + if (rm_res->desc[j].num_sec) { + irq_res.desc[i].start_sec = rm_res->desc[j].start_sec + + oes->pktdma_rchan_flow; + irq_res.desc[i].num_sec = rm_res->desc[j].num_sec; + } + } + } + ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res); + kfree(irq_res.desc); + if (ret) { + dev_err(ud->dev, "Failed to allocate MSI interrupts\n"); + return ret; + } + + return 0; +} + +int udma_setup_rx_flush(struct udma_dev *ud) +{ + struct udma_rx_flush *rx_flush = &ud->rx_flush; + struct cppi5_desc_hdr_t *tr_desc; + struct cppi5_tr_type1_t *tr_req; + struct cppi5_host_desc_t *desc; + struct device *dev = ud->dev; + struct udma_hwdesc *hwdesc; + size_t tr_size; + + /* Allocate 1K buffer for discarded data on RX channel teardown */ + rx_flush->buffer_size = SZ_1K; + rx_flush->buffer_vaddr = devm_kzalloc(dev, rx_flush->buffer_size, + GFP_KERNEL); + if (!rx_flush->buffer_vaddr) + return -ENOMEM; + + rx_flush->buffer_paddr = dma_map_single(dev, rx_flush->buffer_vaddr, + rx_flush->buffer_size, + DMA_TO_DEVICE); + if (dma_mapping_error(dev, rx_flush->buffer_paddr)) + return -ENOMEM; + + /* Set up descriptor to be used for TR mode */ + hwdesc = &rx_flush->hwdescs[0]; + tr_size = sizeof(struct cppi5_tr_type1_t); + hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size, 1); + hwdesc->cppi5_desc_size = ALIGN(hwdesc->cppi5_desc_size, + ud->desc_align); + + hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size, + GFP_KERNEL); + if (!hwdesc->cppi5_desc_vaddr) + return -ENOMEM; + + hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr, + hwdesc->cppi5_desc_size, + DMA_TO_DEVICE); + if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr)) + return -ENOMEM; + + /* Start of the TR req records */ + hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size; + /* Start address of the TR response array */ + hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size; + + tr_desc = hwdesc->cppi5_desc_vaddr; + cppi5_trdesc_init(tr_desc, 1, tr_size, 0, 0); + cppi5_desc_set_pktids(tr_desc, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT); + cppi5_desc_set_retpolicy(tr_desc, 0, 0); + + tr_req = hwdesc->tr_req_base; + cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false, + CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT); + + tr_req->addr = rx_flush->buffer_paddr; + tr_req->icnt0 = rx_flush->buffer_size; + tr_req->icnt1 = 1; + + dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr, + hwdesc->cppi5_desc_size, DMA_TO_DEVICE); + + /* Set up descriptor to be used for packet mode */ + hwdesc = &rx_flush->hwdescs[1]; + hwdesc->cppi5_desc_size = ALIGN(sizeof(struct cppi5_host_desc_t) + + CPPI5_INFO0_HDESC_EPIB_SIZE + + CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE, + ud->desc_align); + + hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size, + GFP_KERNEL); + if (!hwdesc->cppi5_desc_vaddr) + return -ENOMEM; + + hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr, + hwdesc->cppi5_desc_size, + DMA_TO_DEVICE); + if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr)) + return -ENOMEM; + + desc = hwdesc->cppi5_desc_vaddr; + cppi5_hdesc_init(desc, 0, 0); + cppi5_desc_set_pktids(&desc->hdr, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT); + cppi5_desc_set_retpolicy(&desc->hdr, 0, 0); + + cppi5_hdesc_attach_buf(desc, + rx_flush->buffer_paddr, rx_flush->buffer_size, + rx_flush->buffer_paddr, rx_flush->buffer_size); + + dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr, + hwdesc->cppi5_desc_size, DMA_TO_DEVICE); + return 0; +} + +#ifdef CONFIG_DEBUG_FS +void udma_dbg_summary_show_chan(struct seq_file *s, + struct dma_chan *chan) +{ + struct udma_chan *uc = to_udma_chan(chan); + struct udma_chan_config *ucc = &uc->config; + + seq_printf(s, " %-13s| %s", dma_chan_name(chan), + chan->dbg_client_name ?: "in-use"); + if (ucc->tr_trigger_type) + seq_puts(s, " (triggered, "); + else + seq_printf(s, " (%s, ", + dmaengine_get_direction_text(uc->config.dir)); + + switch (uc->config.dir) { + case DMA_MEM_TO_MEM: + if (uc->ud->match_data->type == DMA_TYPE_BCDMA || + uc->ud->match_data->type == DMA_TYPE_BCDMA_V2) { + seq_printf(s, "bchan%d)\n", uc->bchan->id); + return; + } + + seq_printf(s, "chan%d pair [0x%04x -> 0x%04x], ", uc->tchan->id, + ucc->src_thread, ucc->dst_thread); + break; + case DMA_DEV_TO_MEM: + seq_printf(s, "rchan%d [0x%04x -> 0x%04x], ", uc->rchan->id, + ucc->src_thread, ucc->dst_thread); + if (uc->ud->match_data->type == DMA_TYPE_PKTDMA) + seq_printf(s, "rflow%d, ", uc->rflow->id); + break; + case DMA_MEM_TO_DEV: + seq_printf(s, "tchan%d [0x%04x -> 0x%04x], ", uc->tchan->id, + ucc->src_thread, ucc->dst_thread); + if (uc->ud->match_data->type == DMA_TYPE_PKTDMA) + seq_printf(s, "tflow%d, ", uc->tchan->tflow_id); + break; + default: + seq_puts(s, ")\n"); + return; + } + + if (ucc->ep_type == PSIL_EP_NATIVE) { + seq_puts(s, "PSI-L Native"); + if (ucc->metadata_size) { + seq_printf(s, "[%s", ucc->needs_epib ? " EPIB" : ""); + if (ucc->psd_size) + seq_printf(s, " PSDsize:%u", ucc->psd_size); + seq_puts(s, " ]"); + } + } else { + seq_puts(s, "PDMA"); + if (ucc->enable_acc32 || ucc->enable_burst) + seq_printf(s, "[%s%s ]", + ucc->enable_acc32 ? " ACC32" : "", + ucc->enable_burst ? " BURST" : ""); + } + + seq_printf(s, ", %s)\n", ucc->pkt_mode ? "Packet mode" : "TR mode"); +} + +void udma_dbg_summary_show(struct seq_file *s, + struct dma_device *dma_dev) +{ + struct dma_chan *chan; + + list_for_each_entry(chan, &dma_dev->channels, device_node) { + if (chan->client_count) + udma_dbg_summary_show_chan(s, chan); + } +} +#endif /* CONFIG_DEBUG_FS */ + +enum dmaengine_alignment udma_get_copy_align(struct udma_dev *ud) +{ + const struct udma_match_data *match_data = ud->match_data; + u8 tpl; + + if (!match_data->enable_memcpy_support) + return DMAENGINE_ALIGN_8_BYTES; + + /* Get the highest TPL level the device supports for memcpy */ + if (ud->bchan_cnt) + tpl = udma_get_chan_tpl_index(&ud->bchan_tpl, 0); + else if (ud->tchan_cnt) + tpl = udma_get_chan_tpl_index(&ud->tchan_tpl, 0); + else + return DMAENGINE_ALIGN_8_BYTES; + + switch (match_data->burst_size[tpl]) { + case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES: + return DMAENGINE_ALIGN_256_BYTES; + case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES: + return DMAENGINE_ALIGN_128_BYTES; + case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES: + fallthrough; + default: + return DMAENGINE_ALIGN_64_BYTES; + } +} + +/* Private interfaces to UDMA */ +#include "k3-udma-private.c" diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/dma/ti/k3-udma-glue.c v_kernel/drivers/dma/ti/k3-udma-glue.c --- linux-6.12.57/drivers/dma/ti/k3-udma-glue.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/dma/ti/k3-udma-glue.c 2026-04-21 11:35:36.145935207 +0200 @@ -243,6 +243,9 @@ const struct udma_tisci_rm *tisci_rm = tx_chn->common.tisci_rm; struct ti_sci_msg_rm_udmap_tx_ch_cfg req; + if (!tisci_rm->tisci) + return 0; + memset(&req, 0, sizeof(req)); req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | @@ -501,21 +504,29 @@ { int ret; - ret = xudma_navss_psil_pair(tx_chn->common.udmax, - tx_chn->common.src_thread, - tx_chn->common.dst_thread); - if (ret) { - dev_err(tx_chn->common.dev, "PSI-L request err %d\n", ret); - return ret; - } + if (tx_chn->common.udmax->match_data->type == DMA_TYPE_PKTDMA_V2) { + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_AUTOPAIR | UDMA_CHAN_RT_CTL_EN); + + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, + UDMA_PEER_RT_EN_ENABLE); + } else { + ret = xudma_navss_psil_pair(tx_chn->common.udmax, + tx_chn->common.src_thread, + tx_chn->common.dst_thread); + if (ret) { + dev_err(tx_chn->common.dev, "PSI-L request err %d\n", ret); + return ret; + } - tx_chn->psil_paired = true; + tx_chn->psil_paired = true; - xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, - UDMA_PEER_RT_EN_ENABLE); + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, + UDMA_PEER_RT_EN_ENABLE); - xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, - UDMA_CHAN_RT_CTL_EN); + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN); + } k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn en"); return 0; @@ -681,7 +692,6 @@ TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID; - req.nav_id = tisci_rm->tisci_dev_id; req.index = rx_chn->udma_rchan_id; req.rx_fetch_size = rx_chn->common.hdesc_size >> 2; /* @@ -701,11 +711,18 @@ req.rx_chan_type = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR; req.rx_atype = rx_chn->common.atype_asel; + if (!tisci_rm->tisci) { + // TODO: look at the chan settings + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CFG_REG, + UDMA_CHAN_RT_CTL_TDOWN | UDMA_CHAN_RT_CTL_PAUSE); + return 0; + } + + req.nav_id = tisci_rm->tisci_dev_id; ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req); if (ret) dev_err(rx_chn->common.dev, "rchan%d cfg failed %d\n", - rx_chn->udma_rchan_id, ret); - + rx_chn->udma_rchan_id, ret); return ret; } @@ -754,8 +771,11 @@ } if (xudma_is_pktdma(rx_chn->common.udmax)) { - rx_ringfdq_id = flow->udma_rflow_id + + if (tisci_rm->tisci) + rx_ringfdq_id = flow->udma_rflow_id + xudma_get_rflow_ring_offset(rx_chn->common.udmax); + else + rx_ringfdq_id = flow->udma_rflow_id; rx_ring_id = 0; } else { rx_ring_id = flow_cfg->ring_rxq_id; @@ -802,6 +822,13 @@ rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq); } + if (!tisci_rm->tisci) { + xudma_rflowrt_write(flow->udma_rflow, UDMA_RX_FLOWRT_RFA, + UDMA_CHAN_RT_CTL_TDOWN | UDMA_CHAN_RT_CTL_PAUSE); + rx_chn->flows_ready++; + return 0; + } + memset(&req, 0, sizeof(req)); req.valid_params = @@ -1300,6 +1327,9 @@ if (!rx_chn->remote) return -EINVAL; + if (!tisci_rm->tisci) + return 0; + rx_ring_id = k3_ringacc_get_ring_id(flow->ringrx); rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq); @@ -1341,6 +1371,9 @@ if (!rx_chn->remote) return -EINVAL; + if (!tisci_rm->tisci) + return 0; + memset(&req, 0, sizeof(req)); req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID | @@ -1376,21 +1409,26 @@ if (rx_chn->flows_ready < rx_chn->flow_num) return -EINVAL; - ret = xudma_navss_psil_pair(rx_chn->common.udmax, - rx_chn->common.src_thread, - rx_chn->common.dst_thread); - if (ret) { - dev_err(rx_chn->common.dev, "PSI-L request err %d\n", ret); - return ret; - } + if (rx_chn->common.udmax->match_data->type == DMA_TYPE_PKTDMA_V2) { + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_AUTOPAIR | UDMA_CHAN_RT_CTL_EN); + } else { + ret = xudma_navss_psil_pair(rx_chn->common.udmax, + rx_chn->common.src_thread, + rx_chn->common.dst_thread); + if (ret) { + dev_err(rx_chn->common.dev, "PSI-L request err %d\n", ret); + return ret; + } - rx_chn->psil_paired = true; + rx_chn->psil_paired = true; - xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, - UDMA_CHAN_RT_CTL_EN); + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN); - xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, - UDMA_PEER_RT_EN_ENABLE); + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, + UDMA_PEER_RT_EN_ENABLE); + } k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt en"); return 0; diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/dma/ti/k3-udma.h v_kernel/drivers/dma/ti/k3-udma.h --- linux-6.12.57/drivers/dma/ti/k3-udma.h 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/dma/ti/k3-udma.h 2026-04-21 11:35:36.146935210 +0200 @@ -6,7 +6,33 @@ #ifndef K3_UDMA_H_ #define K3_UDMA_H_ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include +#include +#include +#include + +#include "../virt-dma.h" +#include "k3-psil-priv.h" /* Global registers */ #define UDMA_REV_REG 0x0 @@ -18,11 +44,16 @@ #define UDMA_RX_FLOW_ID_FW_OES_REG 0x80 #define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88 +#define UDMA_RX_FLOWRT_RFA 0x8 + /* BCHANRT/TCHANRT/RCHANRT registers */ #define UDMA_CHAN_RT_CTL_REG 0x0 +#define UDMA_CHAN_RT_CFG_REG 0x4 #define UDMA_CHAN_RT_SWTRIG_REG 0x8 #define UDMA_CHAN_RT_STDATA_REG 0x80 +#define UDMA_CHAN_RT_PDMA_STATE_REG 0x80c + #define UDMA_CHAN_RT_PEER_REG(i) (0x200 + ((i) * 0x4)) #define UDMA_CHAN_RT_PEER_STATIC_TR_XY_REG \ UDMA_CHAN_RT_PEER_REG(0) /* PSI-L: 0x400 */ @@ -62,8 +93,16 @@ #define UDMA_CHAN_RT_CTL_TDOWN BIT(30) #define UDMA_CHAN_RT_CTL_PAUSE BIT(29) #define UDMA_CHAN_RT_CTL_FTDOWN BIT(28) +#define UDMA_CHAN_RT_CTL_AUTOPAIR BIT(23) +#define UDMA_CHAN_RT_CTL_PAIR_TIMEOUT BIT(17) +#define UDMA_CHAN_RT_CTL_PAIR_COMPLETE BIT(16) #define UDMA_CHAN_RT_CTL_ERROR BIT(0) +/* UDMA_CHAN_RT_PDMA_STATE_REG */ +#define UDMA_CHAN_RT_PDMA_STATE_IN_EVT BIT(31) +#define UDMA_CHAN_RT_PDMA_STATE_TDOWN BIT(30) +#define UDMA_CHAN_RT_PDMA_STATE_PAUSE BIT(29) + /* UDMA_CHAN_RT_PEER_RT_EN_REG */ #define UDMA_PEER_RT_EN_ENABLE BIT(31) #define UDMA_PEER_RT_EN_TEARDOWN BIT(30) @@ -94,13 +133,68 @@ */ #define PDMA_STATIC_TR_Z(x, mask) ((x) & (mask)) +/* UDMA_CHAN_RT_PEER_REG(8) */ +#define UDMA_CHAN_RT_PEER_REG8_FLUSH 0x09000000 + /* Address Space Select */ #define K3_ADDRESS_ASEL_SHIFT 48 +#define K3_UDMA_MAX_RFLOWS 1024 +#define K3_UDMA_DEFAULT_RING_SIZE 16 + +/* How SRC/DST tag should be updated by UDMA in the descriptor's Word 3 */ +#define UDMA_RFLOW_SRCTAG_NONE 0 +#define UDMA_RFLOW_SRCTAG_CFG_TAG 1 +#define UDMA_RFLOW_SRCTAG_FLOW_ID 2 +#define UDMA_RFLOW_SRCTAG_SRC_TAG 4 + +#define UDMA_RFLOW_DSTTAG_NONE 0 +#define UDMA_RFLOW_DSTTAG_CFG_TAG 1 +#define UDMA_RFLOW_DSTTAG_FLOW_ID 2 +#define UDMA_RFLOW_DSTTAG_DST_TAG_LO 4 +#define UDMA_RFLOW_DSTTAG_DST_TAG_HI 5 + +/* Device capability flags */ +#define UDMA_FLAG_PDMA_ACC32 BIT(0) +#define UDMA_FLAG_PDMA_BURST BIT(1) +#define UDMA_FLAG_TDTYPE BIT(2) +#define UDMA_FLAG_BURST_SIZE BIT(3) +#define UDMA_FLAGS_J7_CLASS (UDMA_FLAG_PDMA_ACC32 | \ + UDMA_FLAG_PDMA_BURST | \ + UDMA_FLAG_TDTYPE | \ + UDMA_FLAG_BURST_SIZE) + +#define TI_UDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) + +struct udma_chan; struct udma_dev; -struct udma_tchan; -struct udma_rchan; -struct udma_rflow; + +enum k3_dma_type { + DMA_TYPE_UDMA = 0, + DMA_TYPE_BCDMA, + DMA_TYPE_PKTDMA, + DMA_TYPE_BCDMA_V2, + DMA_TYPE_PKTDMA_V2, +}; + +enum udma_mmr { + MMR_GCFG = 0, + MMR_BCHANRT, + MMR_RCHANRT, + MMR_TCHANRT, + MMR_LAST, +}; + +enum am62l_udma_mmr { + AM62L_MMR_GCFG = 0, + AM62L_MMR_BCHANRT, + AM62L_MMR_CHANRT, + AM62L_MMR_LAST, +}; enum udma_rm_range { RM_RANGE_BCHAN = 0, @@ -111,6 +205,69 @@ RM_RANGE_LAST, }; +enum udma_chan_state { + UDMA_CHAN_IS_IDLE = 0, /* not active, no teardown is in progress */ + UDMA_CHAN_IS_ACTIVE, /* Normal operation */ + UDMA_CHAN_IS_TERMINATING, /* channel is being terminated */ +}; + +struct udma_filter_param { + int remote_thread_id; + u32 atype; + u32 asel; + u32 tr_trigger_type; +}; + +struct am62l_udma_filter_param { + u32 tr_trigger_type; + u32 trigger_param; + int remote_thread_id; + u32 asel; +}; + +struct udma_static_tr { + u8 elsize; /* RPSTR0 */ + u16 elcnt; /* RPSTR0 */ + u16 bstcnt; /* RPSTR1 */ +}; + +struct udma_tchan { + void __iomem *reg_rt; + + int id; + struct k3_ring *t_ring; /* Transmit ring */ + struct k3_ring *tc_ring; /* Transmit Completion ring */ + int tflow_id; /* applicable only for PKTDMA */ +}; + +#define udma_bchan udma_tchan +#define udma_rchan udma_tchan + +struct udma_rflow { + int id; + struct k3_ring *fd_ring; /* Free Descriptor ring */ + struct k3_ring *r_ring; /* Receive ring */ + void __iomem *reg_rt; +}; + +struct udma_oes_offsets { + /* K3 UDMA Output Event Offset */ + u32 udma_rchan; + + /* BCDMA Output Event Offsets */ + u32 bcdma_bchan_data; + u32 bcdma_bchan_ring; + u32 bcdma_tchan_data; + u32 bcdma_tchan_ring; + u32 bcdma_rchan_data; + u32 bcdma_rchan_ring; + + /* PKTDMA Output Event Offsets */ + u32 pktdma_tchan_flow; + u32 pktdma_rchan_flow; +}; + + struct udma_tisci_rm { const struct ti_sci_handle *tisci; const struct ti_sci_rm_udmap_ops *tisci_udmap_ops; @@ -123,6 +280,414 @@ struct ti_sci_resource *rm_ranges[RM_RANGE_LAST]; }; + +struct udma_match_data { + enum k3_dma_type type; + u32 psil_base; + bool enable_memcpy_support; + u32 flags; + u32 statictr_z_mask; + u8 burst_size[3]; + struct udma_soc_data *soc_data; + u32 bchan_cnt; + u32 chan_cnt; + u32 tchan_cnt; + u32 rchan_cnt; + u32 tflow_cnt; + u32 rflow_cnt; +}; + +struct udma_soc_data { + struct udma_oes_offsets oes; + u32 bcdma_trigger_event_offset; +}; + +struct udma_hwdesc { + size_t cppi5_desc_size; + void *cppi5_desc_vaddr; + dma_addr_t cppi5_desc_paddr; + + /* TR descriptor internal pointers */ + void *tr_req_base; + struct cppi5_tr_resp_t *tr_resp_base; +}; + +struct udma_rx_flush { + struct udma_hwdesc hwdescs[2]; + + size_t buffer_size; + void *buffer_vaddr; + dma_addr_t buffer_paddr; +}; + +struct udma_tpl { + u8 levels; + u32 start_idx[3]; +}; + +struct udma_desc { + struct virt_dma_desc vd; + + bool terminated; + + enum dma_transfer_direction dir; + + struct udma_static_tr static_tr; + u32 residue; + + unsigned int sglen; + unsigned int desc_idx; /* Only used for cyclic in packet mode */ + unsigned int tr_idx; + + u32 metadata_size; + void *metadata; /* pointer to provided metadata buffer (EPIP, PSdata) */ + + unsigned int hwdesc_count; + struct udma_hwdesc hwdesc[]; +}; + +struct udma_tx_drain { + struct delayed_work work; + ktime_t tstamp; + u32 residue; +}; + +struct udma_chan_config { + bool pkt_mode; /* TR or packet */ + bool needs_epib; /* EPIB is needed for the communication or not */ + u32 psd_size; /* size of Protocol Specific Data */ + u32 metadata_size; /* (needs_epib ? 16:0) + psd_size */ + u32 hdesc_size; /* Size of a packet descriptor in packet mode */ + bool notdpkt; /* Suppress sending TDC packet */ + int remote_thread_id; + u32 atype; + u32 asel; + u32 src_thread; + u32 dst_thread; + enum psil_endpoint_type ep_type; + bool enable_acc32; + bool enable_burst; + enum udma_tp_level channel_tpl; /* Channel Throughput Level */ + + u32 tr_trigger_type; + unsigned long tx_flags; + + /* PKDMA mapped channel */ + int mapped_channel_id; + /* PKTDMA default tflow or rflow for mapped channel */ + int default_flow_id; + + enum dma_transfer_direction dir; +}; + +struct udma_dev { + struct dma_device ddev; + struct device *dev; + void __iomem *mmrs[MMR_LAST]; + void __iomem *rflow_rt; + const struct udma_match_data *match_data; + const struct udma_soc_data *soc_data; + + struct udma_tpl bchan_tpl; + struct udma_tpl tchan_tpl; + struct udma_tpl rchan_tpl; + + size_t desc_align; /* alignment to use for descriptors */ + + struct udma_tisci_rm tisci_rm; + + struct k3_ringacc *ringacc; + + struct work_struct purge_work; + struct list_head desc_to_purge; + spinlock_t lock; + + struct udma_rx_flush rx_flush; + + int bchan_cnt; + int chan_cnt; + int tchan_cnt; + int echan_cnt; + int rchan_cnt; + int rflow_cnt; + int tflow_cnt; + unsigned long *bchan_map; + unsigned long *chan_map; + unsigned long *tchan_map; + unsigned long *rchan_map; + unsigned long *rflow_gp_map; + unsigned long *rflow_gp_map_allocated; + unsigned long *rflow_in_use; + unsigned long *tflow_map; + + struct udma_bchan *bchans; + struct udma_tchan *chans; + struct udma_tchan *tchans; + struct udma_rchan *rchans; + struct udma_rflow *rflows; + + struct udma_chan *channels; + u32 psil_base; + u32 atype; + u32 asel; + + int (*udma_start)(struct udma_chan *uc); + int (*udma_stop)(struct udma_chan *uc); + int (*udma_reset_chan)(struct udma_chan *uc, bool hard); + bool (*udma_is_desc_really_done)(struct udma_chan *uc, struct udma_desc *d); + void (*udma_decrement_byte_counters)(struct udma_chan *uc, u32 val); +}; + +struct udma_chan { + struct virt_dma_chan vc; + struct dma_slave_config cfg; + struct udma_dev *ud; + struct device *dma_dev; + struct udma_desc *desc; + struct udma_desc *terminated_desc; + struct udma_static_tr static_tr; + char *name; + + struct udma_bchan *bchan; + struct udma_tchan *chan; + struct udma_tchan *tchan; + struct udma_rchan *rchan; + struct udma_rflow *rflow; + + bool psil_paired; + + int irq_num_ring; + int irq_num_udma; + + bool cyclic; + bool paused; + + enum udma_chan_state state; + struct completion teardown_completed; + + struct udma_tx_drain tx_drain; + + /* Channel configuration parameters */ + struct udma_chan_config config; + /* Channel configuration parameters (backup) */ + struct udma_chan_config backup_config; + + /* dmapool for packet mode descriptors */ + bool use_dma_pool; + struct dma_pool *hdesc_pool; + + u32 id; +}; + +/* K3 UDMA helper functions */ +static inline struct udma_dev *to_udma_dev(struct dma_device *d) +{ + return container_of(d, struct udma_dev, ddev); +} + +static inline struct udma_chan *to_udma_chan(struct dma_chan *c) +{ + return container_of(c, struct udma_chan, vc.chan); +} + +static inline struct udma_desc *to_udma_desc(struct dma_async_tx_descriptor *t) +{ + return container_of(t, struct udma_desc, vd.tx); +} + +/* Generic register access functions */ +static inline u32 udma_read(void __iomem *base, int reg) +{ + return readl(base + reg); +} + +static inline void udma_write(void __iomem *base, int reg, u32 val) +{ + writel(val, base + reg); +} + +static inline void udma_update_bits(void __iomem *base, int reg, + u32 mask, u32 val) +{ + u32 tmp, orig; + + orig = readl(base + reg); + tmp = orig & ~mask; + tmp |= (val & mask); + + if (tmp != orig) + writel(tmp, base + reg); +} + +#define _UDMA_REG_ACCESS(channel) \ +static inline u32 udma_##channel##rt_read(struct udma_chan *uc, int reg) \ +{ \ + if (!uc->channel) \ + return 0; \ + return udma_read(uc->channel->reg_rt, reg); \ +} \ +\ +static inline void udma_##channel##rt_write(struct udma_chan *uc, int reg, u32 val) \ +{ \ + if (!uc->channel) \ + return; \ + udma_write(uc->channel->reg_rt, reg, val); \ +} \ +\ +static inline void udma_##channel##rt_update_bits(struct udma_chan *uc, int reg, \ + u32 mask, u32 val) \ +{ \ + if (!uc->channel) \ + return; \ + udma_update_bits(uc->channel->reg_rt, reg, mask, val); \ +} + +_UDMA_REG_ACCESS(chan); +_UDMA_REG_ACCESS(bchan); +_UDMA_REG_ACCESS(tchan); +_UDMA_REG_ACCESS(rchan); + +static inline dma_addr_t udma_curr_cppi5_desc_paddr(struct udma_desc *d, + int idx) +{ + return d->hwdesc[idx].cppi5_desc_paddr; +} + +static inline void *udma_curr_cppi5_desc_vaddr(struct udma_desc *d, int idx) +{ + return d->hwdesc[idx].cppi5_desc_vaddr; +} + +static inline dma_addr_t udma_get_rx_flush_hwdesc_paddr(struct udma_chan *uc) +{ + return uc->ud->rx_flush.hwdescs[uc->config.pkt_mode].cppi5_desc_paddr; +} + +static inline void udma_fetch_epib(struct udma_chan *uc, struct udma_desc *d) +{ + struct cppi5_host_desc_t *h_desc = d->hwdesc[0].cppi5_desc_vaddr; + + memcpy(d->metadata, h_desc->epib, d->metadata_size); +} + +void udma_start_desc(struct udma_chan *uc); +bool udma_chan_needs_reconfiguration(struct udma_chan *uc); +void udma_cyclic_packet_elapsed(struct udma_chan *uc); +void udma_check_tx_completion(struct work_struct *work); +void udma_issue_pending(struct dma_chan *chan); +void udma_free_chan_resources(struct dma_chan *chan); +int setup_resources(struct udma_dev *ud); +void udma_mark_resource_ranges(struct udma_dev *ud, unsigned long *map, + struct ti_sci_resource_desc *rm_desc, + char *name); +int udma_setup_resources(struct udma_dev *ud); +int bcdma_setup_resources(struct udma_dev *ud); +int pktdma_setup_resources(struct udma_dev *ud); + +void k3_configure_chan_coherency(struct dma_chan *chan, u32 asel); +u8 udma_get_chan_tpl_index(struct udma_tpl *tpl_map, int chan_id); +void udma_reset_uchan(struct udma_chan *uc); +void udma_dump_chan_stdata(struct udma_chan *uc); +struct udma_desc *udma_udma_desc_from_paddr(struct udma_chan *uc, + dma_addr_t paddr); +void udma_free_hwdesc(struct udma_chan *uc, struct udma_desc *d); +void udma_purge_desc_work(struct work_struct *work); +void udma_desc_free(struct virt_dma_desc *vd); +bool udma_is_chan_running(struct udma_chan *uc); +void udma_reset_rings(struct udma_chan *uc); +int udma_push_to_ring(struct udma_chan *uc, int idx); +bool udma_desc_is_rx_flush(struct udma_chan *uc, dma_addr_t addr); +int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr); + +int __udma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt); +int __udma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt); +struct udma_rflow *__udma_get_rflow(struct udma_dev *ud, int id); +void __udma_put_rflow(struct udma_dev *ud, struct udma_rflow *rflow); + +struct udma_bchan *__udma_reserve_bchan(struct udma_dev *ud, enum udma_tp_level tpl, int id); +struct udma_tchan *__udma_reserve_tchan(struct udma_dev *ud, enum udma_tp_level tpl, int id); +struct udma_rchan *__udma_reserve_rchan(struct udma_dev *ud, enum udma_tp_level tpl, int id); + +int udma_get_tchan(struct udma_chan *uc); +int udma_get_rchan(struct udma_chan *uc); +int udma_get_chan_pair(struct udma_chan *uc); +int udma_get_rflow(struct udma_chan *uc, int flow_id); +void bcdma_put_bchan(struct udma_chan *uc); +void udma_put_rchan(struct udma_chan *uc); +void udma_put_tchan(struct udma_chan *uc); +void udma_put_rflow(struct udma_chan *uc); +void bcdma_free_bchan_resources(struct udma_chan *uc); +void udma_free_tx_resources(struct udma_chan *uc); +void udma_free_rx_resources(struct udma_chan *uc); +int udma_slave_config(struct dma_chan *chan, + struct dma_slave_config *cfg); +struct udma_desc *udma_alloc_tr_desc(struct udma_chan *uc, + size_t tr_size, int tr_count, + enum dma_transfer_direction dir); +int udma_get_tr_counters(struct udma_chan *uc, size_t len, unsigned long align_to, u16 *tr0_cnt0, + u16 *tr0_cnt1, u16 *tr1_cnt0); +struct udma_desc * +udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl, + unsigned int sglen, enum dma_transfer_direction dir, + unsigned long tx_flags, void *context); +struct udma_desc * +udma_prep_slave_sg_triggered_tr(struct udma_chan *uc, struct scatterlist *sgl, + unsigned int sglen, + enum dma_transfer_direction dir, + unsigned long tx_flags, void *context); +int udma_configure_statictr(struct udma_chan *uc, struct udma_desc *d, + enum dma_slave_buswidth dev_width, + u16 elcnt); +struct udma_desc * +udma_prep_slave_sg_pkt(struct udma_chan *uc, struct scatterlist *sgl, + unsigned int sglen, enum dma_transfer_direction dir, + unsigned long tx_flags, void *context); +int udma_attach_metadata(struct dma_async_tx_descriptor *desc, + void *data, size_t len); +void *udma_get_metadata_ptr(struct dma_async_tx_descriptor *desc, + size_t *payload_len, size_t *max_len); +int udma_set_metadata_len(struct dma_async_tx_descriptor *desc, + size_t payload_len); +struct dma_async_tx_descriptor * +udma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sglen, enum dma_transfer_direction dir, + unsigned long tx_flags, void *context); +struct udma_desc * +udma_prep_dma_cyclic_tr(struct udma_chan *uc, dma_addr_t buf_addr, + size_t buf_len, size_t period_len, + enum dma_transfer_direction dir, unsigned long flags); +struct udma_desc * +udma_prep_dma_cyclic_pkt(struct udma_chan *uc, dma_addr_t buf_addr, + size_t buf_len, size_t period_len, + enum dma_transfer_direction dir, unsigned long flags); +struct dma_async_tx_descriptor * +udma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, + size_t period_len, enum dma_transfer_direction dir, + unsigned long flags); +struct dma_async_tx_descriptor * +udma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, + size_t len, unsigned long tx_flags); +int udma_terminate_all(struct dma_chan *chan); +void udma_synchronize(struct dma_chan *chan); +void udma_desc_pre_callback(struct virt_dma_chan *vc, + struct virt_dma_desc *vd, + struct dmaengine_result *result); + +void udma_vchan_complete(struct tasklet_struct *t); +int udma_setup_rx_flush(struct udma_dev *ud); + +#ifdef CONFIG_DEBUG_FS +void udma_dbg_summary_show_chan(struct seq_file *s, + struct dma_chan *chan); +void udma_dbg_summary_show(struct seq_file *s, + struct dma_device *dma_dev); +#endif /* CONFIG_DEBUG_FS */ + +enum dmaengine_alignment udma_get_copy_align(struct udma_dev *ud); +int navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread); +int navss_psil_unpair(struct udma_dev *ud, u32 src_thread, + u32 dst_thread); + /* Direct access to UDMA low lever resources for the glue layer */ int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread); int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, @@ -155,6 +720,8 @@ void xudma_rchanrt_write(struct udma_rchan *rchan, int reg, u32 val); bool xudma_rflow_is_gp(struct udma_dev *ud, int id); int xudma_get_rflow_ring_offset(struct udma_dev *ud); +u32 xudma_rflowrt_read(struct udma_rflow *rflow, int reg); +void xudma_rflowrt_write(struct udma_rflow *rflow, int reg, u32 val); int xudma_is_pktdma(struct udma_dev *ud); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/dma/ti/k3-udma-private.c v_kernel/drivers/dma/ti/k3-udma-private.c --- linux-6.12.57/drivers/dma/ti/k3-udma-private.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/dma/ti/k3-udma-private.c 2026-04-21 11:35:36.145935207 +0200 @@ -3,18 +3,28 @@ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com * Author: Peter Ujfalusi */ +#include +#include +#include +#include #include #include int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread) { - return navss_psil_pair(ud, src_thread, dst_thread); + if (IS_ENABLED(CONFIG_TI_K3_UDMA)) + return navss_psil_pair(ud, src_thread, dst_thread); + + return 0; } EXPORT_SYMBOL(xudma_navss_psil_pair); int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, u32 dst_thread) { - return navss_psil_unpair(ud, src_thread, dst_thread); + if (IS_ENABLED(CONFIG_TI_K3_UDMA)) + return navss_psil_unpair(ud, src_thread, dst_thread); + + return 0; } EXPORT_SYMBOL(xudma_navss_psil_unpair); @@ -159,15 +169,32 @@ EXPORT_SYMBOL(xudma_##res##rt_write) XUDMA_RT_IO_FUNCTIONS(tchan); XUDMA_RT_IO_FUNCTIONS(rchan); +XUDMA_RT_IO_FUNCTIONS(rflow); int xudma_is_pktdma(struct udma_dev *ud) { - return ud->match_data->type == DMA_TYPE_PKTDMA; + return (ud->match_data->type == DMA_TYPE_PKTDMA || + ud->match_data->type == DMA_TYPE_PKTDMA_V2); } EXPORT_SYMBOL(xudma_is_pktdma); int xudma_pktdma_tflow_get_irq(struct udma_dev *ud, int udma_tflow_id) { + if (ud->match_data->type == DMA_TYPE_PKTDMA_V2) { + __be32 addr[2] = {0, 0}; + struct of_phandle_args out_irq; + int ret; + + out_irq.np = dev_of_node(ud->dev); + out_irq.args_count = 1; + out_irq.args[0] = udma_tflow_id; + ret = of_irq_parse_raw(addr, &out_irq); + if (ret) + return ret; + + return irq_create_of_mapping(&out_irq); + } + const struct udma_oes_offsets *oes = &ud->soc_data->oes; return msi_get_virq(ud->dev, udma_tflow_id + oes->pktdma_tchan_flow); @@ -176,6 +203,21 @@ int xudma_pktdma_rflow_get_irq(struct udma_dev *ud, int udma_rflow_id) { + if (ud->match_data->type == DMA_TYPE_PKTDMA_V2) { + __be32 addr[2] = {0, 0}; + struct of_phandle_args out_irq; + int ret; + + out_irq.np = dev_of_node(ud->dev); + out_irq.args_count = 1; + out_irq.args[0] = udma_rflow_id; + ret = of_irq_parse_raw(addr, &out_irq); + if (ret) + return ret; + + return irq_create_of_mapping(&out_irq); + } + const struct udma_oes_offsets *oes = &ud->soc_data->oes; return msi_get_virq(ud->dev, udma_rflow_id + oes->pktdma_rchan_flow); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/dma/ti/Kconfig v_kernel/drivers/dma/ti/Kconfig --- linux-6.12.57/drivers/dma/ti/Kconfig 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/dma/ti/Kconfig 2026-04-21 11:35:36.138935189 +0200 @@ -47,17 +47,27 @@ Enable support for the TI UDMA (Unified DMA) controller. This DMA engine is used in AM65x and j721e. +config TI_K3_UDMA_AM62L + tristate "Texas Instruments AM62L UDMA support" + depends on ARCH_K3 + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + select TI_K3_RINGACC + select TI_K3_PSIL + help + Enable support for the TI AM62L UDMA (Unified DMA) controller. + config TI_K3_UDMA_GLUE_LAYER tristate "Texas Instruments UDMA Glue layer for non DMAengine users" depends on ARCH_K3 - depends on TI_K3_UDMA + depends on TI_K3_UDMA || TI_K3_UDMA_AM62L help Say y here to support the K3 NAVSS DMA glue interface If unsure, say N. config TI_K3_PSIL tristate - default TI_K3_UDMA + default TI_K3_UDMA || TI_K3_UDMA_AM62L config TI_DMA_CROSSBAR bool diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/dma/ti/Makefile v_kernel/drivers/dma/ti/Makefile --- linux-6.12.57/drivers/dma/ti/Makefile 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/dma/ti/Makefile 2026-04-21 11:35:36.138935189 +0200 @@ -2,7 +2,8 @@ obj-$(CONFIG_TI_CPPI41) += cppi41.o obj-$(CONFIG_TI_EDMA) += edma.o obj-$(CONFIG_DMA_OMAP) += omap-dma.o -obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o +obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o k3-udma-common.o +obj-$(CONFIG_TI_K3_UDMA_AM62L) += k3-udma-am62l.o k3-udma-common.o obj-$(CONFIG_TI_K3_UDMA_GLUE_LAYER) += k3-udma-glue.o k3-psil-lib-objs := k3-psil.o \ k3-psil-am654.o \ @@ -12,6 +13,7 @@ k3-psil-j721s2.o \ k3-psil-am62.o \ k3-psil-am62a.o \ + k3-psil-am62l.o \ k3-psil-j784s4.o \ k3-psil-am62p.o obj-$(CONFIG_TI_K3_PSIL) += k3-psil-lib.o diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/dma-buf/dma-heap.c v_kernel/drivers/dma-buf/dma-heap.c --- linux-6.12.57/drivers/dma-buf/dma-heap.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/dma-buf/dma-heap.c 2026-04-21 11:35:35.923934625 +0200 @@ -326,4 +326,4 @@ return 0; } -subsys_initcall(dma_heap_init); +core_initcall(dma_heap_init); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/dma-buf/heaps/carveout-heap.c v_kernel/drivers/dma-buf/heaps/carveout-heap.c --- linux-6.12.57/drivers/dma-buf/heaps/carveout-heap.c 1970-01-01 01:00:00.000000000 +0100 +++ v_kernel/drivers/dma-buf/heaps/carveout-heap.c 2026-04-21 11:35:35.924934628 +0200 @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Carveout DMA-Heap userspace exporter + * + * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Andrew Davis + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct carveout_dma_heap { + struct dma_heap *heap; + struct gen_pool *pool; + bool cached; +}; + +struct carveout_dma_heap_buffer { + struct gen_pool *pool; + struct list_head attachments; + struct mutex attachments_lock; + struct mutex vmap_lock; + int vmap_cnt; + unsigned long len; + void *vaddr; + phys_addr_t paddr; + bool cached; +}; + +struct dma_heap_attachment { + struct device *dev; + struct sg_table *table; + struct list_head list; +}; + +static int dma_heap_attach(struct dma_buf *dmabuf, + struct dma_buf_attachment *attachment) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + struct dma_heap_attachment *a; + struct sg_table *table; + + a = kzalloc(sizeof(*a), GFP_KERNEL); + if (!a) + return -ENOMEM; + + table = kmalloc(sizeof(*table), GFP_KERNEL); + if (!table) { + kfree(a); + return -ENOMEM; + } + if (sg_alloc_table(table, 1, GFP_KERNEL)) { + kfree(a); + return -ENOMEM; + } + sg_set_page(table->sgl, pfn_to_page(PFN_DOWN(buffer->paddr)), buffer->len, 0); + + a->table = table; + a->dev = attachment->dev; + INIT_LIST_HEAD(&a->list); + + attachment->priv = a; + + mutex_lock(&buffer->attachments_lock); + list_add(&a->list, &buffer->attachments); + mutex_unlock(&buffer->attachments_lock); + + return 0; +} + +static void dma_heap_detatch(struct dma_buf *dmabuf, + struct dma_buf_attachment *attachment) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + struct dma_heap_attachment *a = attachment->priv; + + mutex_lock(&buffer->attachments_lock); + list_del(&a->list); + mutex_unlock(&buffer->attachments_lock); + + sg_free_table(a->table); + kfree(a->table); + kfree(a); +} + +static struct sg_table *dma_heap_map_dma_buf(struct dma_buf_attachment *attachment, + enum dma_data_direction direction) +{ + struct carveout_dma_heap_buffer *buffer = attachment->dmabuf->priv; + struct dma_heap_attachment *a = attachment->priv; + struct sg_table *table = a->table; + + unsigned long attrs = buffer->cached ? 0 : DMA_ATTR_SKIP_CPU_SYNC; + + if (!dma_map_sg_attrs(attachment->dev, table->sgl, table->nents, + direction, attrs)) + return ERR_PTR(-ENOMEM); + + return table; +} + +static void dma_heap_unmap_dma_buf(struct dma_buf_attachment *attachment, + struct sg_table *table, + enum dma_data_direction direction) +{ + struct carveout_dma_heap_buffer *buffer = attachment->dmabuf->priv; + unsigned long attrs = buffer->cached ? 0 : DMA_ATTR_SKIP_CPU_SYNC; + + dma_unmap_sg_attrs(attachment->dev, table->sgl, table->nents, + direction, attrs); +} + +static void dma_heap_dma_buf_release(struct dma_buf *dmabuf) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + + if (buffer->vmap_cnt > 0) { + WARN(1, "%s: buffer still mapped in the kernel\n", __func__); + memunmap(buffer->vaddr); + } + + gen_pool_free(buffer->pool, buffer->paddr, buffer->len); + kfree(buffer); +} + +static int dma_heap_dma_buf_begin_cpu_access(struct dma_buf *dmabuf, + enum dma_data_direction direction) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + struct dma_heap_attachment *a; + + if (!buffer->cached) + return 0; + + mutex_lock(&buffer->vmap_lock); + if (buffer->vmap_cnt) + invalidate_kernel_vmap_range(buffer->vaddr, buffer->len); + mutex_unlock(&buffer->vmap_lock); + + mutex_lock(&buffer->attachments_lock); + list_for_each_entry(a, &buffer->attachments, list) { + dma_sync_sg_for_cpu(a->dev, a->table->sgl, a->table->nents, + direction); + } + mutex_unlock(&buffer->attachments_lock); + + return 0; +} + +static int dma_heap_dma_buf_end_cpu_access(struct dma_buf *dmabuf, + enum dma_data_direction direction) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + struct dma_heap_attachment *a; + + if (!buffer->cached) + return 0; + + mutex_lock(&buffer->vmap_lock); + if (buffer->vmap_cnt) + flush_kernel_vmap_range(buffer->vaddr, buffer->len); + mutex_unlock(&buffer->vmap_lock); + + mutex_lock(&buffer->attachments_lock); + list_for_each_entry(a, &buffer->attachments, list) { + dma_sync_sg_for_device(a->dev, a->table->sgl, a->table->nents, + direction); + } + mutex_unlock(&buffer->attachments_lock); + + return 0; +} + +static int dma_heap_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + int ret; + + if (!buffer->cached) + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + + ret = vm_iomap_memory(vma, buffer->paddr, buffer->len); + if (ret) + pr_err("Could not map buffer to userspace\n"); + + return ret; +} + +static int dma_heap_vmap(struct dma_buf *dmabuf, struct iosys_map *map) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + void *vaddr; + int ret = 0; + + mutex_lock(&buffer->vmap_lock); + + if (buffer->vmap_cnt) { + buffer->vmap_cnt++; + iosys_map_set_vaddr(map, buffer->vaddr); + goto exit; + } + if (buffer->cached) + vaddr = memremap(buffer->paddr, buffer->len, MEMREMAP_WB); + else + vaddr = memremap(buffer->paddr, buffer->len, MEMREMAP_WC); + if (!vaddr) { + pr_err("Could not memremap buffer\n"); + ret = -ENOMEM; + goto exit; + } + if (IS_ERR(vaddr)) { + ret = PTR_ERR(vaddr); + goto exit; + } + + buffer->vaddr = vaddr; + buffer->vmap_cnt++; + iosys_map_set_vaddr(map, buffer->vaddr); +exit: + mutex_unlock(&buffer->vmap_lock); + + return ret; +} + +static void dma_heap_vunmap(struct dma_buf *dmabuf, struct iosys_map *map) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + + mutex_lock(&buffer->vmap_lock); + if (!--buffer->vmap_cnt) { + memunmap(buffer->vaddr); + buffer->vaddr = NULL; + } + mutex_unlock(&buffer->vmap_lock); +} + +static const struct dma_buf_ops carveout_dma_heap_buf_ops = { + .attach = dma_heap_attach, + .detach = dma_heap_detatch, + .map_dma_buf = dma_heap_map_dma_buf, + .unmap_dma_buf = dma_heap_unmap_dma_buf, + .release = dma_heap_dma_buf_release, + .begin_cpu_access = dma_heap_dma_buf_begin_cpu_access, + .end_cpu_access = dma_heap_dma_buf_end_cpu_access, + .mmap = dma_heap_mmap, + .vmap = dma_heap_vmap, + .vunmap = dma_heap_vunmap, +}; + +static struct dma_buf *carveout_dma_heap_allocate(struct dma_heap *heap, + unsigned long len, + u32 fd_flags, + u64 heap_flags) +{ + struct carveout_dma_heap *carveout_dma_heap = dma_heap_get_drvdata(heap); + struct carveout_dma_heap_buffer *buffer; + + DEFINE_DMA_BUF_EXPORT_INFO(exp_info); + struct dma_buf *dmabuf; + int ret = 0; + + buffer = kzalloc(sizeof(*buffer), GFP_KERNEL); + if (!buffer) + return ERR_PTR(-ENOMEM); + buffer->pool = carveout_dma_heap->pool; + buffer->cached = carveout_dma_heap->cached; + INIT_LIST_HEAD(&buffer->attachments); + mutex_init(&buffer->attachments_lock); + mutex_init(&buffer->vmap_lock); + buffer->len = len; + + buffer->paddr = gen_pool_alloc(buffer->pool, buffer->len); + if (!buffer->paddr) { + ret = -ENOMEM; + goto free_buffer; + } + + /* create the dmabuf */ + exp_info.exp_name = dma_heap_get_name(heap); + exp_info.ops = &carveout_dma_heap_buf_ops; + exp_info.size = buffer->len; + exp_info.flags = fd_flags; + exp_info.priv = buffer; + dmabuf = dma_buf_export(&exp_info); + if (IS_ERR(dmabuf)) { + ret = PTR_ERR(dmabuf); + goto free_pool; + } + + return dmabuf; + +free_pool: + gen_pool_free(buffer->pool, buffer->paddr, buffer->len); +free_buffer: + kfree(buffer); + + return ERR_PTR(ret); +} + +static struct dma_heap_ops carveout_dma_heap_ops = { + .allocate = carveout_dma_heap_allocate, +}; + +static int carveout_dma_heap_export(phys_addr_t base, size_t size, const char *name, bool cached) +{ + struct carveout_dma_heap *carveout_dma_heap; + struct dma_heap_export_info exp_info; + int ret; + + carveout_dma_heap = kzalloc(sizeof(*carveout_dma_heap), GFP_KERNEL); + if (!carveout_dma_heap) + return -ENOMEM; + + carveout_dma_heap->pool = gen_pool_create(PAGE_SHIFT, NUMA_NO_NODE); + if (IS_ERR(carveout_dma_heap->pool)) { + pr_err("Carveout Heap: Could not create memory pool\n"); + ret = PTR_ERR(carveout_dma_heap->pool); + goto free_carveout_dma_heap; + } + ret = gen_pool_add(carveout_dma_heap->pool, base, size, NUMA_NO_NODE); + if (ret) { + pr_err("Carveout Heap: Could not add memory to pool\n"); + goto free_pool; + } + + carveout_dma_heap->cached = cached; + + exp_info.name = kasprintf(GFP_KERNEL, "carveout_%s", name); + exp_info.ops = &carveout_dma_heap_ops; + exp_info.priv = carveout_dma_heap; + carveout_dma_heap->heap = dma_heap_add(&exp_info); + if (IS_ERR(carveout_dma_heap->heap)) { + pr_err("Carveout Heap: Could not add DMA-Heap\n"); + ret = PTR_ERR(carveout_dma_heap->heap); + goto free_pool; + } + + pr_info("Carveout Heap: Exported %zu MiB at %pa\n", size / SZ_1M, &base); + + return 0; + +free_pool: + gen_pool_destroy(carveout_dma_heap->pool); +free_carveout_dma_heap: + kfree(carveout_dma_heap); + return ret; +} + +#ifdef CONFIG_OF_RESERVED_MEM +#include +#include +#include + +#define MAX_HEAP_AREAS 7 +static struct reserved_mem heap_areas[MAX_HEAP_AREAS]; +static size_t heap_area_count; + +static int __init carveout_dma_heap_init_areas(void) +{ + int i; + + for (i = 0; i < heap_area_count; i++) { + struct reserved_mem *rmem = &heap_areas[i]; + bool cached = !of_get_flat_dt_prop(rmem->fdt_node, "no-map", NULL); + int ret = carveout_dma_heap_export(rmem->base, rmem->size, rmem->name, cached); + if (ret) { + pr_err("Carveout Heap: could not export as DMA-Heap\n"); + return ret; + } + } + + return 0; +} +fs_initcall(carveout_dma_heap_init_areas); + +static int __init rmem_dma_heap_carveout_setup(struct reserved_mem *rmem) +{ + phys_addr_t align = PAGE_SIZE; + phys_addr_t mask = align - 1; + + if ((rmem->base & mask) || (rmem->size & mask)) { + pr_err("Carveout Heap: incorrect alignment of region\n"); + return -EINVAL; + } + + /* Sanity check */ + if (heap_area_count == ARRAY_SIZE(heap_areas)) { + pr_err("Not enough slots for DMA-Heap reserved regions!\n"); + return -ENOSPC; + } + + /* + * Each reserved area must be initialized later, when more kernel + * subsystems (like slab allocator) are available. + */ + heap_areas[heap_area_count] = *rmem; + heap_area_count++; + + return 0; +} +RESERVEDMEM_OF_DECLARE(dma_heap_carveout, "dma-heap-carveout", rmem_dma_heap_carveout_setup); + +#endif diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/dma-buf/heaps/Kconfig v_kernel/drivers/dma-buf/heaps/Kconfig --- linux-6.12.57/drivers/dma-buf/heaps/Kconfig 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/dma-buf/heaps/Kconfig 2026-04-21 11:35:35.924934628 +0200 @@ -12,3 +12,13 @@ Choose this option to enable dma-buf CMA heap. This heap is backed by the Contiguous Memory Allocator (CMA). If your system has these regions, you should say Y here. + +config DMABUF_HEAPS_CARVEOUT + bool "DMA-BUF Carveout Heap" + depends on DMABUF_HEAPS && HAS_IOMEM + depends on OF_RESERVED_MEM + select GENERIC_ALLOCATOR + help + Choose this option to enable dma-buf Carveout heap. This heap is + backed by the a carved-out of memory. If your system has these + regions, you should say Y here. diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/dma-buf/heaps/Makefile v_kernel/drivers/dma-buf/heaps/Makefile --- linux-6.12.57/drivers/dma-buf/heaps/Makefile 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/dma-buf/heaps/Makefile 2026-04-21 11:35:35.924934628 +0200 @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_DMABUF_HEAPS_SYSTEM) += system_heap.o obj-$(CONFIG_DMABUF_HEAPS_CMA) += cma_heap.o +obj-$(CONFIG_DMABUF_HEAPS_CARVEOUT) += carveout-heap.o diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/firmware/ti_sci.c v_kernel/drivers/firmware/ti_sci.c --- linux-6.12.57/drivers/firmware/ti_sci.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/firmware/ti_sci.c 2026-04-21 11:35:36.998937444 +0200 @@ -2,13 +2,15 @@ /* * Texas Instruments System Control Interface Protocol Driver * - * Copyright (C) 2015-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2015-2025 Texas Instruments Incorporated - https://www.ti.com/ * Nishanth Menon */ #define pr_fmt(fmt) "%s: " fmt, __func__ #include +#include +#include #include #include #include @@ -19,11 +21,14 @@ #include #include #include +#include #include #include #include #include #include +#include +#include #include #include "ti_sci.h" @@ -84,6 +89,16 @@ }; /** + * struct ti_sci_irq - Description of allocated irqs + * @list: List head + * @desc: Description of the irq + */ +struct ti_sci_irq { + struct list_head list; + struct ti_sci_msg_req_manage_irq desc; +}; + +/** * struct ti_sci_info - Structure representing a TI SCI instance * @dev: Device pointer * @desc: SoC description for this instance @@ -97,7 +112,9 @@ * @chan_rx: Receive mailbox channel * @minfo: Message info * @node: list head + * @irqs: List of allocated irqs * @host_id: Host ID + * @fw_caps: FW/SoC low power capabilities * @users: Number of users of this instance */ struct ti_sci_info { @@ -112,8 +129,10 @@ struct mbox_chan *chan_tx; struct mbox_chan *chan_rx; struct ti_sci_xfers_info minfo; + struct ti_sci_irq irqs; struct list_head node; u8 host_id; + u64 fw_caps; /* protected by ti_sci_list_mutex */ int users; }; @@ -392,10 +411,13 @@ static inline int ti_sci_do_xfer(struct ti_sci_info *info, struct ti_sci_xfer *xfer) { + struct ti_sci_msg_hdr *hdr = (struct ti_sci_msg_hdr *)xfer->tx_message.buf; int ret; int timeout; struct device *dev = info->dev; bool done_state = true; + bool response_expected = !!(hdr->flags & (TI_SCI_FLAG_REQ_ACK_ON_PROCESSED | + TI_SCI_FLAG_REQ_ACK_ON_RECEIVED)); ret = mbox_send_message(info->chan_tx, &xfer->tx_message); if (ret < 0) @@ -403,6 +425,9 @@ ret = 0; + if (!response_expected) + goto no_response; + if (system_state <= SYSTEM_RUNNING) { /* And we wait for the response. */ timeout = msecs_to_jiffies(info->desc->max_rx_timeout_ms); @@ -423,6 +448,7 @@ dev_err(dev, "Mbox timedout in resp(caller: %pS)\n", (void *)_RET_IP_); +no_response: /* * NOTE: we might prefer not to need the mailbox ticker to manage the * transfer queueing since the protocol layer queues things by itself. @@ -1436,6 +1462,14 @@ } /** + * ti_sci_restore_clk_upon_resume() - Check if clock parents and rate are to be restored + */ +static bool ti_sci_restore_clk_upon_resume(void) +{ + return true; +} + +/** * ti_sci_cmd_clk_get_match_freq() - Find a good match for frequency * @handle: pointer to TI SCI handle * @dev_id: Device identifier this request is for @@ -1651,6 +1685,489 @@ return ret; } +/** + * ti_sci_cmd_clk_set_ssc() - Set SSC configurations + * @handle: pointer to TI SCI handle + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * @modfreq_hz: The modulation frequency in Hz + * @mod_depth: The modulation depth in "permyriad". + * @spread_type: Type of spread sprectum modulation. + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_clk_set_ssc(const struct ti_sci_handle *handle, + u32 dev_id, u32 clk_id, u32 modfreq_hz, + u32 mod_depth, u8 spread_type) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_set_clock_ssc *req; + struct ti_sci_msg_hdr *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + /* mod_depth must be between 10 and 310 */ + if (mod_depth > 310 || mod_depth < 10) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_SET_CLOCK_SSC, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + + req = (struct ti_sci_msg_req_set_clock_ssc *)xfer->xfer_buf; + req->dev_id = dev_id; + req->clk_id = clk_id; + req->modfreq_hz = modfreq_hz; + req->mod_depth = mod_depth; + req->spread_type = spread_type; + + if (spread_type == CLK_SPREAD_NO) + req->enable = false; + else + req->enable = true; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf; + + ret = ti_sci_is_response_ack(resp) ? 0 : -ENODEV; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_cmd_prepare_sleep() - Prepare system for system suspend + * @handle: pointer to TI SCI handle + * @mode: Device identifier + * @ctx_lo: Low part of address for context save + * @ctx_hi: High part of address for context save + * @debug_flags: Debug flags to pass to firmware + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_prepare_sleep(const struct ti_sci_handle *handle, u8 mode, + u32 ctx_lo, u32 ctx_hi, u32 debug_flags) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_prepare_sleep *req; + struct ti_sci_msg_hdr *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_PREPARE_SLEEP, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + + req = (struct ti_sci_msg_req_prepare_sleep *)xfer->xfer_buf; + req->mode = mode; + req->ctx_lo = ctx_lo; + req->ctx_hi = ctx_hi; + req->debug_flags = debug_flags; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf; + + if (!ti_sci_is_response_ack(resp)) { + dev_err(dev, "Failed to prepare sleep\n"); + ret = -ENODEV; + } + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_msg_cmd_query_fw_caps() - Get the FW/SoC capabilities + * @handle: Pointer to TI SCI handle + * @fw_caps: Each bit in fw_caps indicating one FW/SOC capability + * + * Check if the firmware supports any optional low power modes. + * Old revisions of TIFS (< 08.04) will NACK the request which results in + * -ENODEV being returned. + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_msg_cmd_query_fw_caps(const struct ti_sci_handle *handle, + u64 *fw_caps) +{ + struct ti_sci_info *info; + struct ti_sci_xfer *xfer; + struct ti_sci_msg_resp_query_fw_caps *resp; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_QUERY_FW_CAPS, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(struct ti_sci_msg_hdr), + sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_resp_query_fw_caps *)xfer->xfer_buf; + + if (!ti_sci_is_response_ack(resp)) { + dev_err(dev, "Failed to get capabilities\n"); + ret = -ENODEV; + goto fail; + } + + if (fw_caps) + *fw_caps = resp->fw_caps; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_cmd_set_io_isolation() - Enable IO isolation in LPM + * @handle: Pointer to TI SCI handle + * @state: The desired state of the IO isolation + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_set_io_isolation(const struct ti_sci_handle *handle, + u8 state) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_set_io_isolation *req; + struct ti_sci_msg_hdr *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_SET_IO_ISOLATION, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_req_set_io_isolation *)xfer->xfer_buf; + req->state = state; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf; + + if (!ti_sci_is_response_ack(resp)) { + dev_err(dev, "Failed to set IO isolation\n"); + ret = -ENODEV; + } + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_msg_cmd_lpm_wake_reason() - Get the wakeup source from LPM + * @handle: Pointer to TI SCI handle + * @source: The wakeup source that woke the SoC from LPM + * @timestamp: Timestamp of the wakeup event + * @pin: The pin that has triggered wake up + * @mode: The last entered low power mode + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_msg_cmd_lpm_wake_reason(const struct ti_sci_handle *handle, + u32 *source, u64 *timestamp, u8 *pin, u8 *mode) +{ + struct ti_sci_info *info; + struct ti_sci_xfer *xfer; + struct ti_sci_msg_resp_lpm_wake_reason *resp; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_LPM_WAKE_REASON, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(struct ti_sci_msg_hdr), + sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_resp_lpm_wake_reason *)xfer->xfer_buf; + + if (!ti_sci_is_response_ack(resp)) { + dev_err(dev, "Failed to get wake reason\n"); + ret = -ENODEV; + goto fail; + } + + if (source) + *source = resp->wake_source; + if (timestamp) + *timestamp = resp->wake_timestamp; + if (pin) + *pin = resp->wake_pin; + if (mode) + *mode = resp->mode; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_cmd_set_device_constraint() - Set LPM constraint on behalf of a device + * @handle: pointer to TI SCI handle + * @id: Device identifier + * @state: The desired state of device constraint: set or clear + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_set_device_constraint(const struct ti_sci_handle *handle, + u32 id, u8 state) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_lpm_set_device_constraint *req; + struct ti_sci_msg_hdr *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_LPM_SET_DEVICE_CONSTRAINT, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_req_lpm_set_device_constraint *)xfer->xfer_buf; + req->id = id; + req->state = state; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf; + + if (!ti_sci_is_response_ack(resp)) { + dev_err(dev, "Failed to set device constraint\n"); + ret = -ENODEV; + } + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_cmd_set_latency_constraint() - Set LPM resume latency constraint + * @handle: pointer to TI SCI handle + * @latency: maximum acceptable latency (in ms) to wake up from LPM + * @state: The desired state of latency constraint: set or clear + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_set_latency_constraint(const struct ti_sci_handle *handle, + u16 latency, u8 state) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_lpm_set_latency_constraint *req; + struct ti_sci_msg_hdr *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_LPM_SET_LATENCY_CONSTRAINT, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_req_lpm_set_latency_constraint *)xfer->xfer_buf; + req->latency = latency; + req->state = state; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf; + + if (!ti_sci_is_response_ack(resp)) { + dev_err(dev, "Failed to set device constraint\n"); + ret = -ENODEV; + } + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_cmd_lpm_abort() - Abort entry to LPM + * @handle: pointer to TI SCI handle + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_lpm_abort(const struct ti_sci_handle *handle) +{ + struct ti_sci_info *info; + struct ti_sci_msg_hdr *req; + struct ti_sci_msg_hdr *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_LPM_ABORT, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_hdr *)xfer->xfer_buf; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf; + + if (!ti_sci_is_response_ack(resp)) + ret = -ENODEV; + else + ret = 0; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + static int ti_sci_cmd_core_reboot(const struct ti_sci_handle *handle) { struct ti_sci_info *info; @@ -1888,6 +2405,29 @@ } /** + * ti_sci_irq_equal() - Helper API to compare two irqs (generic headers are not + * compared) + * @irq_a: irq_a to compare + * @irq_b: irq_b to compare + * + * Return: true if the two irqs are equal, else false. + */ +static bool ti_sci_irq_equal(struct ti_sci_msg_req_manage_irq irq_a, + struct ti_sci_msg_req_manage_irq irq_b) +{ + return irq_a.valid_params == irq_b.valid_params && + irq_a.src_id == irq_b.src_id && + irq_a.src_index == irq_b.src_index && + irq_a.dst_id == irq_b.dst_id && + irq_a.dst_host_irq == irq_b.dst_host_irq && + irq_a.ia_id == irq_b.ia_id && + irq_a.vint == irq_b.vint && + irq_a.global_event == irq_b.global_event && + irq_a.vint_status_bit == irq_b.vint_status_bit && + irq_a.secondary_host == irq_b.secondary_host; +} + +/** * ti_sci_set_irq() - Helper api to configure the irq route between the * requested source and destination * @handle: Pointer to TISCI handle. @@ -1910,15 +2450,44 @@ u16 dst_host_irq, u16 ia_id, u16 vint, u16 global_event, u8 vint_status_bit, u8 s_host) { + struct ti_sci_info *info = handle_to_ti_sci_info(handle); + struct ti_sci_msg_req_manage_irq *desc; + struct ti_sci_irq *irq; + int ret; pr_debug("%s: IRQ set with valid_params = 0x%x from src = %d, index = %d, to dst = %d, irq = %d,via ia_id = %d, vint = %d, global event = %d,status_bit = %d\n", - __func__, valid_params, src_id, src_index, + __func__, valid_params, src_id, src_index, dst_id, dst_host_irq, ia_id, vint, global_event, vint_status_bit); - return ti_sci_manage_irq(handle, valid_params, src_id, src_index, - dst_id, dst_host_irq, ia_id, vint, - global_event, vint_status_bit, s_host, - TI_SCI_MSG_SET_IRQ); + ret = ti_sci_manage_irq(handle, valid_params, src_id, src_index, + dst_id, dst_host_irq, ia_id, vint, + global_event, vint_status_bit, s_host, + TI_SCI_MSG_SET_IRQ); + + if (ret) + return ret; + + if (info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED) { + irq = kzalloc(sizeof(*irq), GFP_KERNEL); + if (!irq) + return -ENOMEM; + + desc = &irq->desc; + desc->valid_params = valid_params; + desc->src_id = src_id; + desc->src_index = src_index; + desc->dst_id = dst_id; + desc->dst_host_irq = dst_host_irq; + desc->ia_id = ia_id; + desc->vint = vint; + desc->global_event = global_event; + desc->vint_status_bit = vint_status_bit; + desc->secondary_host = s_host; + + list_add(&irq->list, &info->irqs.list); + } + + return 0; } /** @@ -1944,15 +2513,48 @@ u16 dst_host_irq, u16 ia_id, u16 vint, u16 global_event, u8 vint_status_bit, u8 s_host) { + struct ti_sci_info *info = handle_to_ti_sci_info(handle); + struct ti_sci_msg_req_manage_irq irq_desc; + struct ti_sci_irq *this_irq; + struct list_head *this; + int ret; + pr_debug("%s: IRQ release with valid_params = 0x%x from src = %d, index = %d, to dst = %d, irq = %d,via ia_id = %d, vint = %d, global event = %d,status_bit = %d\n", - __func__, valid_params, src_id, src_index, - dst_id, dst_host_irq, ia_id, vint, global_event, - vint_status_bit); + __func__, valid_params, src_id, src_index, + dst_id, dst_host_irq, ia_id, vint, global_event, + vint_status_bit); + + ret = ti_sci_manage_irq(handle, valid_params, src_id, src_index, + dst_id, dst_host_irq, ia_id, vint, + global_event, vint_status_bit, s_host, + TI_SCI_MSG_FREE_IRQ); - return ti_sci_manage_irq(handle, valid_params, src_id, src_index, - dst_id, dst_host_irq, ia_id, vint, - global_event, vint_status_bit, s_host, - TI_SCI_MSG_FREE_IRQ); + if (ret) + return ret; + + if (info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED) { + irq_desc.valid_params = valid_params; + irq_desc.src_id = src_id; + irq_desc.src_index = src_index; + irq_desc.dst_id = dst_id; + irq_desc.dst_host_irq = dst_host_irq; + irq_desc.ia_id = ia_id; + irq_desc.vint = vint; + irq_desc.global_event = global_event; + irq_desc.vint_status_bit = vint_status_bit; + irq_desc.secondary_host = s_host; + + list_for_each(this, &info->irqs.list) { + this_irq = list_entry(this, struct ti_sci_irq, list); + if (ti_sci_irq_equal(irq_desc, this_irq->desc)) { + list_del(&this_irq->list); + kfree(this_irq); + break; + } + } + } + + return 0; } /** @@ -2793,6 +3395,7 @@ struct ti_sci_core_ops *core_ops = &ops->core_ops; struct ti_sci_dev_ops *dops = &ops->dev_ops; struct ti_sci_clk_ops *cops = &ops->clk_ops; + struct ti_sci_pm_ops *pmops = &ops->pm_ops; struct ti_sci_rm_core_ops *rm_core_ops = &ops->rm_core_ops; struct ti_sci_rm_irq_ops *iops = &ops->rm_irq_ops; struct ti_sci_rm_ringacc_ops *rops = &ops->rm_ring_ops; @@ -2827,10 +3430,22 @@ cops->set_parent = ti_sci_cmd_clk_set_parent; cops->get_parent = ti_sci_cmd_clk_get_parent; cops->get_num_parents = ti_sci_cmd_clk_get_num_parents; + if (info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED) + cops->restore_clk = ti_sci_restore_clk_upon_resume; cops->get_best_match_freq = ti_sci_cmd_clk_get_match_freq; cops->set_freq = ti_sci_cmd_clk_set_freq; cops->get_freq = ti_sci_cmd_clk_get_freq; + if (info->fw_caps & MSG_FLAG_CAPS_CLOCK_SSC) + cops->set_spread_spectrum = ti_sci_cmd_clk_set_ssc; + + if (info->fw_caps & MSG_FLAG_CAPS_LPM_DM_MANAGED) { + pr_debug("detected DM managed LPM in fw_caps\n"); + pmops->lpm_wake_reason = ti_sci_msg_cmd_lpm_wake_reason; + pmops->set_device_constraint = ti_sci_cmd_set_device_constraint; + pmops->set_latency_constraint = ti_sci_cmd_set_latency_constraint; + pmops->lpm_abort = ti_sci_cmd_lpm_abort; + } rm_core_ops->get_range = ti_sci_cmd_get_resource_range; rm_core_ops->get_range_from_shost = @@ -3262,6 +3877,261 @@ return NOTIFY_BAD; } +static int ti_sci_prepare_system_suspend(struct ti_sci_info *info) +{ + /* + * Map and validate the target Linux suspend state to TISCI LPM. + * Default is to let Device Manager select the low power mode. + */ + switch (pm_suspend_target_state) { + case PM_SUSPEND_MEM: + if (info->fw_caps & MSG_FLAG_CAPS_LPM_DM_MANAGED) { + /* + * For the DM_MANAGED mode the context is reserved for + * internal use and can be 0 + */ + return ti_sci_cmd_prepare_sleep(&info->handle, + TISCI_MSG_VALUE_SLEEP_MODE_DM_MANAGED, + 0, 0, 0); + } else if (info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED) { + /* Nothing to do in the BOARDCFG_MANAGED mode */ + return 0; + } else { + /* DM Managed and BoardCfg Managed are not supported by the firmware. */ + dev_err(info->dev, "Suspend to memory is not supported by the firmware\n"); + return -EOPNOTSUPP; + } + break; + default: + /* + * Do not fail if we don't have action to take for a + * specific suspend mode. + */ + return 0; + } +} + +static int ti_sci_suspend(struct device *dev) +{ + struct ti_sci_info *info = dev_get_drvdata(dev); + struct device *cpu_dev, *cpu_dev_max = NULL; + s32 val, cpu_lat = 0; + u16 cpu_lat_ms; + int i, ret; + + if (info->fw_caps & MSG_FLAG_CAPS_LPM_DM_MANAGED) { + for_each_possible_cpu(i) { + cpu_dev = get_cpu_device(i); + val = dev_pm_qos_read_value(cpu_dev, DEV_PM_QOS_RESUME_LATENCY); + if (val != PM_QOS_RESUME_LATENCY_NO_CONSTRAINT) { + cpu_lat = max(cpu_lat, val); + cpu_dev_max = cpu_dev; + } + } + if (cpu_dev_max) { + /* PM QoS latency unit is usecs, TI SCI uses msecs */ + cpu_lat_ms = cpu_lat / USEC_PER_MSEC; + dev_dbg(cpu_dev_max, "%s: sending max CPU latency=%u ms\n", __func__, + cpu_lat_ms); + ret = ti_sci_cmd_set_latency_constraint(&info->handle, + cpu_lat_ms, + TISCI_MSG_CONSTRAINT_SET); + if (ret) + return ret; + } + } + + ret = ti_sci_prepare_system_suspend(info); + if (ret) { + dev_err(dev, "%s: Failed to prepare sleep. Abort entering low power mode.\n", + __func__); + if (ti_sci_cmd_lpm_abort(&info->handle)) + dev_err(dev, "%s: Failed to abort.\n", __func__); + return ret; + } + return 0; +} + +static int ti_sci_suspend_noirq(struct device *dev) +{ + struct ti_sci_info *info = dev_get_drvdata(dev); + int ret = 0; + + if (info->fw_caps & MSG_FLAG_CAPS_IO_ISOLATION) { + ret = ti_sci_cmd_set_io_isolation(&info->handle, TISCI_MSG_VALUE_IO_ENABLE); + if (ret) { + dev_err(dev, "%s: Failed to suspend. Abort entering low power mode.\n", __func__); + if (ti_sci_cmd_lpm_abort(&info->handle)) + dev_err(dev, "%s: Failed to abort.\n", __func__); + return ret; + } + } + + return 0; +} + +extern int davinci_gpio_resume_all_devices(void); + +static int ti_sci_resume_noirq(struct device *dev) +{ + struct ti_sci_info *info = dev_get_drvdata(dev); + struct ti_sci_msg_req_manage_irq *irq_desc; + struct ti_sci_irq *irq; + struct list_head *this; + int ret = 0; + int err; + u32 source; + u64 time; + u8 pin; + u8 mode; + + switch (pm_suspend_target_state) { + case PM_SUSPEND_MEM: + if (info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED) { + list_for_each(this, &info->irqs.list) { + irq = list_entry(this, struct ti_sci_irq, list); + irq_desc = &irq->desc; + ret = ti_sci_manage_irq(&info->handle, + irq_desc->valid_params, + irq_desc->src_id, + irq_desc->src_index, + irq_desc->dst_id, + irq_desc->dst_host_irq, + irq_desc->ia_id, + irq_desc->vint, + irq_desc->global_event, + irq_desc->vint_status_bit, + irq_desc->secondary_host, + TI_SCI_MSG_SET_IRQ); + if (ret) + return ret; + } + } + break; + default: + break; + } + + if (info->fw_caps & MSG_FLAG_CAPS_IO_ISOLATION) { + /* Resume GPIO before disabling isolation to maintain GPIO state */ + err = davinci_gpio_resume_all_devices(); + if (err) + return err; + + ret = ti_sci_cmd_set_io_isolation(&info->handle, TISCI_MSG_VALUE_IO_DISABLE); + if (ret) + return ret; + } + + ret = ti_sci_msg_cmd_lpm_wake_reason(&info->handle, &source, &time, &pin, &mode); + /* Do not fail to resume on error as the wake reason is not critical */ + if (!ret) + dev_info(dev, "ti_sci: wakeup source:0x%x, pin:0x%x, mode:0x%x\n", + source, pin, mode); + + return 0; +} + +static const struct dev_pm_ops ti_sci_pm_ops = { + .suspend = pm_sleep_ptr(ti_sci_suspend), + .suspend_noirq = pm_sleep_ptr(ti_sci_suspend_noirq), + .resume_noirq = pm_sleep_ptr(ti_sci_resume_noirq), +}; + +/* + * Enter Partial-IO, which disables everything including DDR with only a small + * logic being active for wakeup. + */ +static int tisci_enter_partial_io(struct ti_sci_info *info) +{ + struct ti_sci_msg_req_prepare_sleep *req; + struct ti_sci_xfer *xfer; + struct device *dev = info->dev; + int ret = 0; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_PREPARE_SLEEP, + TI_SCI_FLAG_REQ_GENERIC_NORESPONSE, + sizeof(*req), sizeof(struct ti_sci_msg_hdr)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + + req = (struct ti_sci_msg_req_prepare_sleep *)xfer->xfer_buf; + req->mode = TISCI_MSG_VALUE_SLEEP_MODE_PARTIAL_IO; + req->ctx_lo = 0; + req->ctx_hi = 0; + req->debug_flags = 0; + + dev_info(dev, "Entering Partial-IO because a powered wakeup-enabled device was found.\n"); + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +static bool tisci_canuart_wakeup_enabled(struct ti_sci_info *info) +{ + struct device_node *wakeup_node = NULL; + + for (wakeup_node = of_find_node_with_property(NULL, "wakeup-source"); + wakeup_node; + wakeup_node = of_find_node_with_property(wakeup_node, "wakeup-source")) { + struct platform_device *pdev; + int index; + + index = of_property_match_string(wakeup_node, "wakeup-source", "poweroff"); + if (index < 0) + continue; + + pdev = of_find_device_by_node(wakeup_node); + if (!pdev) + break; + + if (device_may_wakeup(&pdev->dev)) { + dev_dbg(info->dev, "%pOF identified as wakeup source for Partial-IO\n", + wakeup_node); + put_device(&pdev->dev); + of_node_put(wakeup_node); + return true; + } + } + + return false; +} + +static int tisci_sys_off_handler(struct sys_off_data *data) +{ + struct ti_sci_info *info = data->cb_data; + bool enter_partial_io = tisci_canuart_wakeup_enabled(info); + int ret; + + if (!enter_partial_io) + return NOTIFY_DONE; + + ret = tisci_enter_partial_io(info); + + if (ret) { + dev_err(info->dev, + "Failed to enter Partial-IO %pe, trying to do an emergency restart\n", + ERR_PTR(ret)); + emergency_restart(); + } + + mdelay(5000); + emergency_restart(); + + return NOTIFY_DONE; +} + /* Description for K2G */ static const struct ti_sci_desc ti_sci_pmmc_k2g_desc = { .default_host_id = 2, @@ -3390,6 +4260,16 @@ goto out; } + ti_sci_msg_cmd_query_fw_caps(&info->handle, &info->fw_caps); + dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s\n", + info->fw_caps & MSG_FLAG_CAPS_GENERIC ? "Generic" : "", + info->fw_caps & MSG_FLAG_CAPS_LPM_PARTIAL_IO ? " Partial-IO" : "", + info->fw_caps & MSG_FLAG_CAPS_LPM_DM_MANAGED ? " DM-Managed" : "", + info->fw_caps & MSG_FLAG_CAPS_LPM_ABORT ? " LPM-Abort" : "", + info->fw_caps & MSG_FLAG_CAPS_IO_ISOLATION ? " IO-Isolation" : "", + info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED ? " BoardConfig-Managed" : "" + ); + ti_sci_setup_ops(info); ret = devm_register_restart_handler(dev, tisci_reboot_handler, info); @@ -3398,6 +4278,19 @@ goto out; } + if (info->fw_caps & MSG_FLAG_CAPS_LPM_PARTIAL_IO) { + ret = devm_register_sys_off_handler(dev, + SYS_OFF_MODE_POWER_OFF, + SYS_OFF_PRIO_FIRMWARE, + tisci_sys_off_handler, + info); + if (ret) { + dev_err(dev, "Failed to register sys_off_handler %pe\n", + ERR_PTR(ret)); + goto out; + } + } + dev_info(dev, "ABI: %d.%d (firmware rev 0x%04x '%s')\n", info->handle.version.abi_major, info->handle.version.abi_minor, info->handle.version.firmware_revision, @@ -3407,7 +4300,16 @@ list_add_tail(&info->node, &ti_sci_list); mutex_unlock(&ti_sci_list_mutex); - return of_platform_populate(dev->of_node, NULL, NULL, dev); + if (info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED) + INIT_LIST_HEAD(&info->irqs.list); + + ret = of_platform_populate(dev->of_node, NULL, NULL, dev); + if (ret) { + dev_err(dev, "platform_populate failed %pe\n", ERR_PTR(ret)); + goto out; + } + return 0; + out: if (!IS_ERR(info->chan_tx)) mbox_free_channel(info->chan_tx); @@ -3423,6 +4325,7 @@ .name = "ti-sci", .of_match_table = of_match_ptr(ti_sci_of_match), .suppress_bind_attrs = true, + .pm = &ti_sci_pm_ops, }, }; module_platform_driver(ti_sci_driver); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/firmware/ti_sci.h v_kernel/drivers/firmware/ti_sci.h --- linux-6.12.57/drivers/firmware/ti_sci.h 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/firmware/ti_sci.h 2026-04-21 11:35:36.999937446 +0200 @@ -6,7 +6,7 @@ * The system works in a message response protocol * See: https://software-dl.ti.com/tisci/esd/latest/index.html for details * - * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2015-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __TI_SCI_H @@ -19,6 +19,7 @@ #define TI_SCI_MSG_WAKE_REASON 0x0003 #define TI_SCI_MSG_GOODBYE 0x0004 #define TI_SCI_MSG_SYS_RESET 0x0005 +#define TI_SCI_MSG_QUERY_FW_CAPS 0x0022 /* Device requests */ #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200 @@ -31,10 +32,19 @@ #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102 #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103 #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104 +#define TI_SCI_MSG_SET_CLOCK_SSC 0x010a #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e +/* Low Power Mode Requests */ +#define TI_SCI_MSG_PREPARE_SLEEP 0x0300 +#define TI_SCI_MSG_LPM_WAKE_REASON 0x0306 +#define TI_SCI_MSG_SET_IO_ISOLATION 0x0307 +#define TI_SCI_MSG_LPM_SET_DEVICE_CONSTRAINT 0x0309 +#define TI_SCI_MSG_LPM_SET_LATENCY_CONSTRAINT 0x030A +#define TI_SCI_MSG_LPM_ABORT 0x0311 + /* Resource Management Requests */ #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500 @@ -133,6 +143,34 @@ } __packed; /** + * struct ti_sci_msg_resp_query_fw_caps - Response for query firmware caps + * @hdr: Generic header + * @fw_caps: Each bit in fw_caps indicating one FW/SOC capability + * MSG_FLAG_CAPS_GENERIC: Generic capability (LPM not supported) + * MSG_FLAG_CAPS_LPM_PARTIAL_IO: Partial IO in LPM + * MSG_FLAG_CAPS_LPM_DM_MANAGED: LPM can be managed by DM + * MSG_FLAG_CAPS_LPM_ABORT: Abort entry to LPM + * MSG_FLAG_CAPS_IO_ISOLATION: IO Isolation support + * MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED: LPM config done statically for the DM via boardcfg + * + * Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS + * providing currently available SOC/firmware capabilities. SoC that don't + * support low power modes return only MSG_FLAG_CAPS_GENERIC capability. + */ +struct ti_sci_msg_resp_query_fw_caps { + struct ti_sci_msg_hdr hdr; +#define MSG_FLAG_CAPS_GENERIC TI_SCI_MSG_FLAG(0) +#define MSG_FLAG_CAPS_LPM_PARTIAL_IO TI_SCI_MSG_FLAG(4) +#define MSG_FLAG_CAPS_LPM_DM_MANAGED TI_SCI_MSG_FLAG(5) +#define MSG_FLAG_CAPS_IO_ISOLATION TI_SCI_MSG_FLAG(7) +#define MSG_FLAG_CAPS_LPM_ABORT TI_SCI_MSG_FLAG(9) +#define MSG_FLAG_CAPS_CLOCK_SSC TI_SCI_MSG_FLAG(10) +#define MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED TI_SCI_MSG_FLAG(12) +#define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1) + u64 fw_caps; +} __packed; + +/** * struct ti_sci_msg_req_set_device_state - Set the desired state of the device * @hdr: Generic header * @id: Indicates which device to modify @@ -545,6 +583,149 @@ u64 freq_hz; } __packed; +/** + * struct ti_sci_msg_req_set_clock_ssc - Request to setup a clock spread spectrum + * @hdr: Generic Header + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * @modfreq_hz: The desired modulation frequency in Hz. + * @mod_depth: The target modulation depth in "permyriad". The modulation depth + * refers to the maximum variation in frequency as a percentage of + * the clock center frequency. The minimum modulation depth is 0.1% + * and the maximum is 3.1%. Modulation depth can be adjusted in 0.1% + * increments. + * @spread_type: The target spread type. + * @enable: Enable or disable SSC. + * + * This message is used to enable/disable a clock's spread spectrum configurations + */ +struct ti_sci_msg_req_set_clock_ssc { + struct ti_sci_msg_hdr hdr; + u32 dev_id; + u32 clk_id; + u32 modfreq_hz; + u32 mod_depth; + u8 spread_type; + u8 enable; +} __packed; + +/** + * struct tisci_msg_req_prepare_sleep - Request for TISCI_MSG_PREPARE_SLEEP. + * + * @hdr TISCI header to provide ACK/NAK flags to the host. + * @mode Low power mode to enter. + * @ctx_lo Low 32-bits of physical pointer to address to use for context save. + * @ctx_hi High 32-bits of physical pointer to address to use for context save. + * @debug_flags Flags that can be set to halt the sequence during suspend or + * resume to allow JTAG connection and debug. + * + * This message is used as the first step of entering a low power mode. It + * allows configurable information, including which state to enter to be + * easily shared from the application, as this is a non-secure message and + * therefore can be sent by anyone. + */ +struct ti_sci_msg_req_prepare_sleep { + struct ti_sci_msg_hdr hdr; + +/* + * When sending perpare_sleep with MODE_PARTIAL_IO no response will be sent, + * no further steps are required. + */ +#define TISCI_MSG_VALUE_SLEEP_MODE_PARTIAL_IO 0x03 +#define TISCI_MSG_VALUE_SLEEP_MODE_DM_MANAGED 0xfd + u8 mode; + u32 ctx_lo; + u32 ctx_hi; + u32 debug_flags; +} __packed; + +/** + * struct tisci_msg_set_io_isolation_req - Request for TI_SCI_MSG_SET_IO_ISOLATION. + * + * @hdr: Generic header + * @state: The deseared state of the IO isolation. + * + * This message is used to enable/disable IO isolation for low power modes. + * Response is generic ACK / NACK message. + */ +struct ti_sci_msg_req_set_io_isolation { + struct ti_sci_msg_hdr hdr; + u8 state; +} __packed; + +/** + * struct ti_sci_msg_resp_lpm_wake_reason - Response for TI_SCI_MSG_LPM_WAKE_REASON. + * + * @hdr: Generic header. + * @wake_source: The wake up source that woke soc from LPM. + * @wake_timestamp: Timestamp at which soc woke. + * @wake_pin: The pin that has triggered wake up. + * @mode: The last entered low power mode. + * @rsvd: Reserved for future use. + * + * Response to a generic message with message type TI_SCI_MSG_LPM_WAKE_REASON, + * used to query the wake up source, pin and entered low power mode. + */ +struct ti_sci_msg_resp_lpm_wake_reason { + struct ti_sci_msg_hdr hdr; + u32 wake_source; + u64 wake_timestamp; + u8 wake_pin; + u8 mode; + u32 rsvd[2]; +} __packed; + +/** + * struct ti_sci_msg_req_lpm_set_device_constraint - Request for + * TISCI_MSG_LPM_SET_DEVICE_CONSTRAINT. + * + * @hdr: TISCI header to provide ACK/NAK flags to the host. + * @id: Device ID of device whose constraint has to be modified. + * @state: The desired state of device constraint: set or clear. + * @rsvd: Reserved for future use. + * + * This message is used by host to set constraint on the device. This can be + * sent anytime after boot before prepare sleep message. Any device can set a + * constraint on the low power mode that the SoC can enter. It allows + * configurable information to be easily shared from the application, as this + * is a non-secure message and therefore can be sent by anyone. By setting a + * constraint, the device ensures that it will not be powered off or reset in + * the selected mode. Note: Access Restriction: Exclusivity flag of Device will + * be honored. If some other host already has constraint on this device ID, + * NACK will be returned. + */ +struct ti_sci_msg_req_lpm_set_device_constraint { + struct ti_sci_msg_hdr hdr; + u32 id; + u8 state; + u32 rsvd[2]; +} __packed; + +/** + * struct ti_sci_msg_req_lpm_set_latency_constraint - Request for + * TISCI_MSG_LPM_SET_LATENCY_CONSTRAINT. + * + * @hdr: TISCI header to provide ACK/NAK flags to the host. + * @wkup_latency: The maximum acceptable latency to wake up from low power mode + * in milliseconds. The deeper the state, the higher the latency. + * @state: The desired state of wakeup latency constraint: set or clear. + * @rsvd: Reserved for future use. + * + * This message is used by host to set wakeup latency from low power mode. This can + * be sent anytime after boot before prepare sleep message, and can be sent after + * current low power mode is exited. Any device can set a constraint on the low power + * mode that the SoC can enter. It allows configurable information to be easily shared + * from the application, as this is a non-secure message and therefore can be sent by + * anyone. By setting a wakeup latency constraint, the host ensures that the resume time + * from selected low power mode will be less than the constraint value. + */ +struct ti_sci_msg_req_lpm_set_latency_constraint { + struct ti_sci_msg_hdr hdr; + u16 latency; + u8 state; + u32 rsvd; +} __packed; + #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff /** diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/gpio/gpio-davinci.c v_kernel/drivers/gpio/gpio-davinci.c --- linux-6.12.57/drivers/gpio/gpio-davinci.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/gpio/gpio-davinci.c 2026-04-21 11:35:37.331938317 +0200 @@ -62,6 +62,7 @@ int irqs[MAX_INT_PER_BANK]; struct davinci_gpio_regs context[MAX_REGS_BANKS]; u32 binten_context; + bool needs_context_restore; }; static inline u32 __gpio_mask(unsigned gpio) @@ -79,6 +80,7 @@ } static int davinci_gpio_irq_setup(struct platform_device *pdev); +int davinci_gpio_resume_all_devices(void); /*--------------------------------------------------------------------------*/ @@ -221,6 +223,7 @@ chips->chip.request = gpiochip_generic_request; chips->chip.free = gpiochip_generic_free; #endif + chips->needs_context_restore = false; spin_lock_init(&chips->lock); chips->gpio_unbanked = gpio_unbanked; @@ -632,6 +635,7 @@ u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32); davinci_gpio_save_context(chips, nbank); + chips->needs_context_restore = true; return 0; } @@ -641,7 +645,10 @@ struct davinci_gpio_controller *chips = dev_get_drvdata(dev); u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32); - davinci_gpio_restore_context(chips, nbank); + if (chips->needs_context_restore) { + davinci_gpio_restore_context(chips, nbank); + chips->needs_context_restore = false; + } return 0; } @@ -666,6 +673,18 @@ }, }; +static int davinci_gpio_resume_wrapper(struct device *dev, void *unused) +{ + return davinci_gpio_resume(dev); +} + +int davinci_gpio_resume_all_devices(void) +{ + return driver_for_each_device(&davinci_gpio_driver.driver, NULL, + NULL, davinci_gpio_resume_wrapper); +} +EXPORT_SYMBOL(davinci_gpio_resume_all_devices); + /* * GPIO driver registration needs to be done before machine_init functions * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/gpio/gpio-pca953x.c v_kernel/drivers/gpio/gpio-pca953x.c --- linux-6.12.57/drivers/gpio/gpio-pca953x.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/gpio/gpio-pca953x.c 2026-04-21 11:35:37.371938422 +0200 @@ -1224,7 +1224,7 @@ regcache_cache_only(chip->regmap, true); } -static int pca953x_suspend(struct device *dev) +static int pca953x_suspend_noirq(struct device *dev) { struct pca953x_chip *chip = dev_get_drvdata(dev); @@ -1238,7 +1238,7 @@ return 0; } -static int pca953x_resume(struct device *dev) +static int pca953x_resume_noirq(struct device *dev) { struct pca953x_chip *chip = dev_get_drvdata(dev); int ret; @@ -1258,7 +1258,8 @@ return ret; } -static DEFINE_SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); +static DEFINE_NOIRQ_DEV_PM_OPS(pca953x_pm_ops, + pca953x_suspend_noirq, pca953x_resume_noirq); /* convenience to stop overlong match-table lines */ #define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int)) diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/gpio/gpio-tps65219.c v_kernel/drivers/gpio/gpio-tps65219.c --- linux-6.12.57/drivers/gpio/gpio-tps65219.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/gpio/gpio-tps65219.c 2026-04-21 11:35:37.387938464 +0200 @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* - * GPIO driver for TI TPS65219 PMICs + * GPIO driver for TI TPS65215/TPS65219 PMICs * - * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ */ #include @@ -13,22 +13,24 @@ #include #define TPS65219_GPIO0_DIR_MASK BIT(3) -#define TPS65219_GPIO0_OFFSET 2 -#define TPS65219_GPIO0_IDX 0 -#define TPS65219_GPIO_DIR_IN 1 -#define TPS65219_GPIO_DIR_OUT 0 +#define TPS6521X_GPIO0_IDX 0 struct tps65219_gpio { struct gpio_chip gpio_chip; struct tps65219 *tps; }; +struct tps65219_chip_data { + int ngpio; + int offset; +}; + static int tps65219_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) { struct tps65219_gpio *gpio = gpiochip_get_data(gc); int ret, val; - if (offset != TPS65219_GPIO0_IDX) + if (offset != TPS6521X_GPIO0_IDX) return GPIO_LINE_DIRECTION_OUT; ret = regmap_read(gpio->tps->regmap, TPS65219_REG_MFP_1_CONFIG, &val); @@ -44,7 +46,7 @@ struct device *dev = gpio->tps->dev; int ret, val; - if (offset != TPS65219_GPIO0_IDX) { + if (offset != TPS6521X_GPIO0_IDX) { dev_err(dev, "GPIO%d is output only, cannot get\n", offset); return -ENOTSUPP; } @@ -61,7 +63,7 @@ * status bit. */ - if (tps65219_gpio_get_direction(gc, offset) == TPS65219_GPIO_DIR_OUT) + if (tps65219_gpio_get_direction(gc, offset) == GPIO_LINE_DIRECTION_OUT) return -ENOTSUPP; return ret; @@ -73,7 +75,7 @@ struct device *dev = gpio->tps->dev; int v, mask, bit; - bit = (offset == TPS65219_GPIO0_IDX) ? TPS65219_GPIO0_OFFSET : offset - 1; + bit = (offset == TPS6521X_GPIO0_IDX) ? (gpio->gpio_chip.offset - 1) : offset - 1; mask = BIT(bit); v = value ? mask : 0; @@ -119,31 +121,30 @@ struct tps65219_gpio *gpio = gpiochip_get_data(gc); struct device *dev = gpio->tps->dev; - if (offset != TPS65219_GPIO0_IDX) { + if (offset != TPS6521X_GPIO0_IDX) { dev_err(dev, "GPIO%d is output only, cannot change to input\n", offset); return -ENOTSUPP; } - if (tps65219_gpio_get_direction(gc, offset) == TPS65219_GPIO_DIR_IN) + if (tps65219_gpio_get_direction(gc, offset) == GPIO_LINE_DIRECTION_IN) return 0; - return tps65219_gpio_change_direction(gc, offset, TPS65219_GPIO_DIR_IN); + return tps65219_gpio_change_direction(gc, offset, GPIO_LINE_DIRECTION_IN); } static int tps65219_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) { tps65219_gpio_set(gc, offset, value); - if (offset != TPS65219_GPIO0_IDX) + if (offset != TPS6521X_GPIO0_IDX) return 0; - if (tps65219_gpio_get_direction(gc, offset) == TPS65219_GPIO_DIR_OUT) + if (tps65219_gpio_get_direction(gc, offset) == GPIO_LINE_DIRECTION_OUT) return 0; - return tps65219_gpio_change_direction(gc, offset, TPS65219_GPIO_DIR_OUT); + return tps65219_gpio_change_direction(gc, offset, GPIO_LINE_DIRECTION_OUT); } static const struct gpio_chip tps65219_template_chip = { - .label = "tps65219-gpio", .owner = THIS_MODULE, .get_direction = tps65219_gpio_get_direction, .direction_input = tps65219_gpio_direction_input, @@ -151,14 +152,29 @@ .get = tps65219_gpio_get, .set = tps65219_gpio_set, .base = -1, - .ngpio = 3, .can_sleep = true, }; +static const struct tps65219_chip_data chip_info_table[] = { + [TPS65215] = { + .ngpio = 2, + .offset = 1, + }, + [TPS65219] = { + .ngpio = 3, + .offset = 2, + }, +}; + static int tps65219_gpio_probe(struct platform_device *pdev) { - struct tps65219 *tps = dev_get_drvdata(pdev->dev.parent); struct tps65219_gpio *gpio; + const struct tps65219_chip_data *pmic; + + struct tps65219 *tps = dev_get_drvdata(pdev->dev.parent); + enum pmic_id chip = platform_get_device_id(pdev)->driver_data; + + pmic = &chip_info_table[chip]; gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); if (!gpio) @@ -166,20 +182,30 @@ gpio->tps = tps; gpio->gpio_chip = tps65219_template_chip; + gpio->gpio_chip.label = dev_name(&pdev->dev); + gpio->gpio_chip.ngpio = pmic->ngpio; + gpio->gpio_chip.offset = pmic->offset; gpio->gpio_chip.parent = tps->dev; return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio_chip, gpio); } +static const struct platform_device_id tps6521x_gpio_id_table[] = { + { "tps65215-gpio", TPS65215 }, + { "tps65219-gpio", TPS65219 }, + { } +}; +MODULE_DEVICE_TABLE(platform, tps6521x_gpio_id_table); + static struct platform_driver tps65219_gpio_driver = { .driver = { .name = "tps65219-gpio", }, .probe = tps65219_gpio_probe, + .id_table = tps6521x_gpio_id_table, }; module_platform_driver(tps65219_gpio_driver); -MODULE_ALIAS("platform:tps65219-gpio"); MODULE_AUTHOR("Jonathan Cormier "); -MODULE_DESCRIPTION("TPS65219 GPIO driver"); +MODULE_DESCRIPTION("TPS65215/TPS65219 GPIO driver"); MODULE_LICENSE("GPL"); diff -Nur '--exclude=.git*' --no-dereference linux-6.12.57/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c v_kernel/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c --- linux-6.12.57/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c 2025-11-02 14:15:23.000000000 +0100 +++ v_kernel/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c 2026-04-21 11:35:50.208972079 +0200 @@ -9,6 +9,7 @@ #include #include #include