diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.80/arch/arm/boot/dts/am335x-boneblack-pps.dts ti-linux-kernel/arch/arm/boot/dts/am335x-boneblack-pps.dts --- .clang-format | 1 Documentation/ABI/testing/sysfs-bus-counter | 108 Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml | 18 Documentation/devicetree/bindings/arm/ti/k3.yaml | 22 Documentation/devicetree/bindings/clock/ti,am62-audio-refclk.yaml | 43 Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml | 5 Documentation/devicetree/bindings/counter/ti-eqep.yaml | 9 Documentation/devicetree/bindings/crypto/ti,mcrc.yaml | 45 Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml | 14 Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt | 112 Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml | 180 Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml | 6 Documentation/devicetree/bindings/display/panel/panel-edp.yaml | 6 Documentation/devicetree/bindings/display/panel/panel-simple.yaml | 6 Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml | 136 Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml | 109 Documentation/devicetree/bindings/gpu/img,sgx530.yaml | 53 Documentation/devicetree/bindings/gpu/img,sgx540.yaml | 51 Documentation/devicetree/bindings/gpu/img,sgx544.yaml | 74 Documentation/devicetree/bindings/gpu/ti,rogue.yaml | 209 Documentation/devicetree/bindings/i2c/i2c-atr.yaml | 34 Documentation/devicetree/bindings/input/gpio-keys.yaml | 41 Documentation/devicetree/bindings/media/cdns,csi2rx.txt | 100 Documentation/devicetree/bindings/media/cdns,csi2rx.yaml | 176 Documentation/devicetree/bindings/media/cnm,wave5.yml | 77 Documentation/devicetree/bindings/media/i2c/ovti,ov1063x.yaml | 103 Documentation/devicetree/bindings/media/i2c/ovti,ox05b.yaml | 87 Documentation/devicetree/bindings/media/i2c/sony,imx390.yaml | 78 Documentation/devicetree/bindings/media/i2c/ti,ds90ub913.yaml | 133 Documentation/devicetree/bindings/media/i2c/ti,ds90ub953.yaml | 134 Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml | 428 Documentation/devicetree/bindings/media/img,d5500-vxd.yaml | 52 Documentation/devicetree/bindings/media/img,e5010-jpeg-enc.yaml | 75 Documentation/devicetree/bindings/media/img,vxe384.yaml | 48 Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml | 100 Documentation/devicetree/bindings/media/ti,vip.yaml | 312 Documentation/devicetree/bindings/media/video-interfaces.yaml | 1 Documentation/devicetree/bindings/mfd/ti,tps6594.yaml | 193 Documentation/devicetree/bindings/misc/ti,dma-buf-phys.yaml | 39 Documentation/devicetree/bindings/net/can/bosch,m_can.yaml | 24 Documentation/devicetree/bindings/net/ti,cpsw-virt-mac.yaml | 104 Documentation/devicetree/bindings/net/ti,icss-iep.yaml | 37 Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml | 198 Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml | 54 Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml | 8 Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml | 38 Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml | 69 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 46 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml | 152 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 1 Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml | 52 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 2 Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml | 208 Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt | 1 Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml | 3 Documentation/devicetree/bindings/remoteproc/ti,k3-m4f-rproc.yaml | 158 Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml | 76 Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml | 60 Documentation/devicetree/bindings/serial/ti,pruss-uart.yaml | 54 Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml | 17 Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml | 35 Documentation/devicetree/bindings/usb/ti,am62-usb.yaml | 4 Documentation/devicetree/bindings/usb/ti,tps6598x.yaml | 5 Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 Documentation/driver-api/media/v4l2-subdev.rst | 8 Documentation/driver-api/phy/phy.rst | 24 Documentation/i2c/i2c-address-translators.rst | 96 Documentation/i2c/index.rst | 1 Documentation/misc-devices/index.rst | 1 Documentation/misc-devices/tps6594-pfsm.rst | 87 Documentation/userspace-api/ioctl/ioctl-number.rst | 1 Documentation/userspace-api/media/v4l/dev-subdev.rst | 166 Documentation/userspace-api/media/v4l/user-func.rst | 1 Documentation/userspace-api/media/v4l/vidioc-subdev-enum-frame-interval.rst | 5 Documentation/userspace-api/media/v4l/vidioc-subdev-enum-frame-size.rst | 5 Documentation/userspace-api/media/v4l/vidioc-subdev-enum-mbus-code.rst | 5 Documentation/userspace-api/media/v4l/vidioc-subdev-g-crop.rst | 5 Documentation/userspace-api/media/v4l/vidioc-subdev-g-fmt.rst | 5 Documentation/userspace-api/media/v4l/vidioc-subdev-g-frame-interval.rst | 5 Documentation/userspace-api/media/v4l/vidioc-subdev-g-routing.rst | 147 Documentation/userspace-api/media/v4l/vidioc-subdev-g-selection.rst | 5 MAINTAINERS | 55 Makefile | 4 arch/arm/Makefile | 6 arch/arm/boot/dts/Makefile | 10 arch/arm/boot/dts/am335x-boneblack-pps.dts | 25 arch/arm/boot/dts/am335x-evmsk.dts | 21 arch/arm/boot/dts/am33xx-l4.dtsi | 8 arch/arm/boot/dts/am33xx.dtsi | 9 arch/arm/boot/dts/am4372.dtsi | 6 arch/arm/boot/dts/am571x-idk-touchscreen.dtso | 32 arch/arm/boot/dts/am572x-idk-touchscreen.dtso | 32 arch/arm/boot/dts/am57xx-beagle-x15.dts | 2 arch/arm/boot/dts/am57xx-evm.dtso | 127 arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso | 63 arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso | 66 arch/arm/boot/dts/dra7.dtsi | 9 arch/arm/boot/dts/dra74x.dtsi | 122 arch/arm/boot/dts/omap34xx.dtsi | 11 arch/arm/boot/dts/omap4.dtsi | 9 arch/arm/boot/dts/ov10635.dtso | 74 arch/arm/configs/lpae.config | 2 arch/arm/configs/multi_v7_defconfig | 78 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts | 91 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso | 91 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts | 85 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso | 85 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts | 69 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso | 69 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts | 85 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso | 85 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts | 61 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso | 61 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts | 68 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso | 68 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts | 93 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso | 93 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts | 52 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso | 52 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts | 61 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso | 61 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts | 61 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso | 61 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts | 93 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso | 93 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts | 52 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso | 52 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts | 61 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso | 61 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts | 61 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso | 61 arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dts | 36 arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso | 36 arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dts | 36 arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso | 36 arch/arm64/boot/dts/ti/Makefile | 202 arch/arm64/boot/dts/ti/k3-am62-lp-sk-lincolntech-lcd185-panel.dtso | 84 arch/arm64/boot/dts/ti/k3-am62-lp-sk-microtips-mf101hie-panel.dtso | 107 arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso | 119 arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 300 arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 657 arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 103 arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi | 33 arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 99 arch/arm64/boot/dts/ti/k3-am62.dtsi | 26 arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-ov5640.dtso | 69 arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso | 69 arch/arm64/boot/dts/ti/k3-am625-beagleplay-lincolntech-lcd185-panel.dtso | 101 arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 998 arch/arm64/boot/dts/ti/k3-am625-sk-dmtimer-pwm.dtso | 41 arch/arm64/boot/dts/ti/k3-am625-sk-ecap-capture.dtso | 29 arch/arm64/boot/dts/ti/k3-am625-sk-lincolntech-lcd185-panel.dtso | 83 arch/arm64/boot/dts/ti/k3-am625-sk-mcspi-loopback.dtso | 55 arch/arm64/boot/dts/ti/k3-am625-sk-microtips-mf101hie-panel.dtso | 106 arch/arm64/boot/dts/ti/k3-am625-sk-microtips-mf103hie-lcd2.dtso | 64 arch/arm64/boot/dts/ti/k3-am625-sk-pwm.dtso | 59 arch/arm64/boot/dts/ti/k3-am625-sk-rpi-hdr-ehrpwm.dtso | 100 arch/arm64/boot/dts/ti/k3-am625-sk.dts | 370 arch/arm64/boot/dts/ti/k3-am625.dtsi | 52 arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 823 arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 159 arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi | 47 arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 78 arch/arm64/boot/dts/ti/k3-am62a.dtsi | 11 arch/arm64/boot/dts/ti/k3-am62a7-sk-csi2-ox05b1s.dtso | 68 arch/arm64/boot/dts/ti/k3-am62a7-sk-e3-max-opp.dtso | 60 arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso | 61 arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion.dtso | 91 arch/arm64/boot/dts/ti/k3-am62a7-sk-rpi-hdr-ehrpwm.dtso | 110 arch/arm64/boot/dts/ti/k3-am62a7-sk-ub954-evm.dtso | 91 arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 694 arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 52 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 1239 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi | 223 arch/arm64/boot/dts/ti/k3-am62p-thermal.dtsi | 47 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 120 arch/arm64/boot/dts/ti/k3-am62p.dtsi | 133 arch/arm64/boot/dts/ti/k3-am62p5-sk-dsi-rpi-7inch-panel.dtso | 122 arch/arm64/boot/dts/ti/k3-am62p5-sk-dss-shared-mode.dtso | 34 arch/arm64/boot/dts/ti/k3-am62p5-sk-eqep.dtso | 41 arch/arm64/boot/dts/ti/k3-am62p5-sk-mcan.dtso | 122 arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf101hie-panel.dtso | 79 arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf103hie-lcd2.dtso | 66 arch/arm64/boot/dts/ti/k3-am62p5-sk-rpi-hdr-ehrpwm.dtso | 112 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 858 arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 154 arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 588 arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso | 68 arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso | 66 arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso | 66 arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-v3link-fusion.dtso | 81 arch/arm64/boot/dts/ti/k3-am62x-sk-eqep.dtso | 41 arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-audio.dtso | 34 arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-disable-fastboot.dtso | 21 arch/arm64/boot/dts/ti/k3-am62x-sk-lpm-wkup-sources.dtso | 150 arch/arm64/boot/dts/ti/k3-am62x-sk-mcan.dtso | 77 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 178 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 18 arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi | 33 arch/arm64/boot/dts/ti/k3-am64.dtsi | 6 arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso | 102 arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso | 78 arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso | 140 arch/arm64/boot/dts/ti/k3-am642-evm.dts | 326 arch/arm64/boot/dts/ti/k3-am642-sk.dts | 230 arch/arm64/boot/dts/ti/k3-am642.dtsi | 1 arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 147 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 182 arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 18 arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 2 arch/arm64/boot/dts/ti/k3-am65.dtsi | 4 arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi | 1 arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 286 arch/arm64/boot/dts/ti/k3-am654-evm-oldi-lcd1evm.dtso | 69 arch/arm64/boot/dts/ti/k3-am654-idk.dtso | 359 arch/arm64/boot/dts/ti/k3-am654-pcie-usb2.dtso | 65 arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso | 67 arch/arm64/boot/dts/ti/k3-am654.dtsi | 2 arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi | 4 arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 724 arch/arm64/boot/dts/ti/k3-am68-sk-bb-csi2-ov5640.dtso | 82 arch/arm64/boot/dts/ti/k3-am68-sk-bb-rpi-cam-imx219.dtso | 118 arch/arm64/boot/dts/ti/k3-am68-sk-fpdlink-fusion.dtso | 119 arch/arm64/boot/dts/ti/k3-am68-sk-rpi-hdr-ehrpwm.dtso | 70 arch/arm64/boot/dts/ti/k3-am68-sk-som-ddr-mem-carveout.dtso | 306 arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 138 arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion.dtso | 161 arch/arm64/boot/dts/ti/k3-am69-sk-csi2-ov5640.dtso | 140 arch/arm64/boot/dts/ti/k3-am69-sk-csi2-rpi-cam-imx219.dtso | 126 arch/arm64/boot/dts/ti/k3-am69-sk-csi2-v3link-fusion.dtso | 156 arch/arm64/boot/dts/ti/k3-am69-sk-ddr-mem-carveout.dtso | 421 arch/arm64/boot/dts/ti/k3-am69-sk-fpdlink-fusion-auxport.dtso | 81 arch/arm64/boot/dts/ti/k3-am69-sk-fpdlink-fusion.dtso | 132 arch/arm64/boot/dts/ti/k3-am69-sk-rpi-hdr-ehrpwm.dtso | 70 arch/arm64/boot/dts/ti/k3-am69-sk.dts | 858 arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-0.dtso | 93 arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-1.dtso | 93 arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-2.dtso | 93 arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-3.dtso | 93 arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-0.dtso | 93 arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-1.dtso | 93 arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-2.dtso | 93 arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-3.dtso | 93 arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-0.dtso | 93 arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-1.dtso | 93 arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-2.dtso | 93 arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-3.dtso | 93 arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-0.dtso | 89 arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-1.dtso | 89 arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-2.dtso | 89 arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-3.dtso | 89 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 197 arch/arm64/boot/dts/ti/k3-j7200-evm-mcspi-loopback.dtso | 49 arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso | 101 arch/arm64/boot/dts/ti/k3-j7200-evm-virt-mac-client.dtso | 92 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 507 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 94 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 324 arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi | 61 arch/arm64/boot/dts/ti/k3-j7200.dtsi | 34 arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-dsi-rpi-7inch-panel.dtso | 144 arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 1025 arch/arm64/boot/dts/ti/k3-j721e-common-proc-board-infotainment.dtso | 164 arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 287 arch/arm64/boot/dts/ti/k3-j721e-evm-csi2-ov5640.dtso | 52 arch/arm64/boot/dts/ti/k3-j721e-evm-fusion.dtso | 107 arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso | 196 arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso | 53 arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso | 133 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drivers/media/platform/img/vxe-vxd/decoder/mmu_defs.h | 42 drivers/media/platform/img/vxe-vxd/decoder/pixel_api.c | 895 drivers/media/platform/img/vxe-vxd/decoder/pixel_api.h | 152 drivers/media/platform/img/vxe-vxd/decoder/pvdec_entropy_regs.h | 33 drivers/media/platform/img/vxe-vxd/decoder/pvdec_int.h | 82 drivers/media/platform/img/vxe-vxd/decoder/pvdec_vec_be_regs.h | 35 drivers/media/platform/img/vxe-vxd/decoder/reg_io2.h | 76 drivers/media/platform/img/vxe-vxd/decoder/scaler_setup.h | 59 drivers/media/platform/img/vxe-vxd/decoder/swsr.c | 1657 drivers/media/platform/img/vxe-vxd/decoder/swsr.h | 278 drivers/media/platform/img/vxe-vxd/decoder/translation_api.c | 1725 drivers/media/platform/img/vxe-vxd/decoder/translation_api.h | 42 drivers/media/platform/img/vxe-vxd/decoder/vdec_defs.h | 555 drivers/media/platform/img/vxe-vxd/decoder/vdec_mmu_wrapper.c | 829 drivers/media/platform/img/vxe-vxd/decoder/vdec_mmu_wrapper.h | 174 drivers/media/platform/img/vxe-vxd/decoder/vdecdd_defs.h | 446 drivers/media/platform/img/vxe-vxd/decoder/vdecdd_utils.c | 95 drivers/media/platform/img/vxe-vxd/decoder/vdecdd_utils.h | 93 drivers/media/platform/img/vxe-vxd/decoder/vdecdd_utils_buf.c | 897 drivers/media/platform/img/vxe-vxd/decoder/vdecfw_share.h | 36 drivers/media/platform/img/vxe-vxd/decoder/vdecfw_shared.h | 893 drivers/media/platform/img/vxe-vxd/decoder/vxd_core.c | 1689 drivers/media/platform/img/vxe-vxd/decoder/vxd_dec.c | 185 drivers/media/platform/img/vxe-vxd/decoder/vxd_dec.h | 512 drivers/media/platform/img/vxe-vxd/decoder/vxd_ext.h | 74 drivers/media/platform/img/vxe-vxd/decoder/vxd_int.c | 1137 drivers/media/platform/img/vxe-vxd/decoder/vxd_int.h | 128 drivers/media/platform/img/vxe-vxd/decoder/vxd_mmu_defs.h | 30 drivers/media/platform/img/vxe-vxd/decoder/vxd_props.h | 80 drivers/media/platform/img/vxe-vxd/decoder/vxd_pvdec.c | 1745 drivers/media/platform/img/vxe-vxd/decoder/vxd_pvdec_priv.h | 126 drivers/media/platform/img/vxe-vxd/decoder/vxd_pvdec_regs.h | 779 drivers/media/platform/img/vxe-vxd/decoder/vxd_v4l2.c | 2428 drivers/media/platform/img/vxe-vxd/encoder/fw_binaries/ALL_CODECS_FW_ALL_pipes_2_contexts_8_hwconfig_1_bin.c |29013 ++++++++++ drivers/media/platform/img/vxe-vxd/encoder/fw_binaries/include_all_fw_variants.h | 47 drivers/media/platform/img/vxe-vxd/encoder/fw_headers/coreflags.h | 41 drivers/media/platform/img/vxe-vxd/encoder/fw_headers/defs.h | 42 drivers/media/platform/img/vxe-vxd/encoder/fw_headers/mtx_fwif.h | 205 drivers/media/platform/img/vxe-vxd/encoder/fw_headers/topazscfwif.h | 1104 drivers/media/platform/img/vxe-vxd/encoder/fw_headers/vxe_common.h | 165 drivers/media/platform/img/vxe-vxd/encoder/header_gen.c | 1751 drivers/media/platform/img/vxe-vxd/encoder/header_gen.h | 111 drivers/media/platform/img/vxe-vxd/encoder/mtx_fwif.c | 990 drivers/media/platform/img/vxe-vxd/encoder/reg_headers/img_soc_dmac_regs.h | 61 drivers/media/platform/img/vxe-vxd/encoder/reg_headers/mtx_regs.h | 72 drivers/media/platform/img/vxe-vxd/encoder/reg_headers/topaz_coreext_regs.h | 183 drivers/media/platform/img/vxe-vxd/encoder/reg_headers/topaz_db_regs.h | 22 drivers/media/platform/img/vxe-vxd/encoder/reg_headers/topaz_vlc_regs.h | 46 drivers/media/platform/img/vxe-vxd/encoder/reg_headers/topazhp_core_regs.h | 232 drivers/media/platform/img/vxe-vxd/encoder/reg_headers/topazhp_multicore_regs_old.h | 22 drivers/media/platform/img/vxe-vxd/encoder/target.h | 68 drivers/media/platform/img/vxe-vxd/encoder/target_config.h | 56 drivers/media/platform/img/vxe-vxd/encoder/topaz_api.c | 3891 + drivers/media/platform/img/vxe-vxd/encoder/topaz_api.h | 1047 drivers/media/platform/img/vxe-vxd/encoder/topaz_api_utils.c | 1487 drivers/media/platform/img/vxe-vxd/encoder/topaz_api_utils.h | 55 drivers/media/platform/img/vxe-vxd/encoder/topaz_color_formats.h | 97 drivers/media/platform/img/vxe-vxd/encoder/topaz_device.c | 1671 drivers/media/platform/img/vxe-vxd/encoder/topaz_device.h | 160 drivers/media/platform/img/vxe-vxd/encoder/topazmmu.c | 741 drivers/media/platform/img/vxe-vxd/encoder/topazmmu.h | 199 drivers/media/platform/img/vxe-vxd/encoder/vxe_enc.c | 473 drivers/media/platform/img/vxe-vxd/encoder/vxe_enc.h | 255 drivers/media/platform/img/vxe-vxd/encoder/vxe_public_regdefs.h | 926 drivers/media/platform/img/vxe-vxd/encoder/vxe_v4l2.c | 1923 drivers/media/platform/img/vxe-vxd/encoder/vxe_v4l2.h | 39 drivers/media/platform/ti/Kconfig | 25 drivers/media/platform/ti/Makefile | 1 drivers/media/platform/ti/j721e-csi2rx/Makefile | 2 drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c | 1744 drivers/media/platform/ti/vpe/Makefile | 2 drivers/media/platform/ti/vpe/vip.c | 3985 + drivers/media/platform/ti/vpe/vip.h | 718 drivers/media/v4l2-core/v4l2-ctrls-defs.c | 3 drivers/media/v4l2-core/v4l2-ioctl.c | 35 drivers/media/v4l2-core/v4l2-mc.c | 18 drivers/media/v4l2-core/v4l2-subdev.c | 1089 drivers/mfd/Kconfig | 46 drivers/mfd/Makefile | 4 drivers/mfd/tps65219.c | 317 drivers/mfd/tps6594-core.c | 462 drivers/mfd/tps6594-i2c.c | 244 drivers/mfd/tps6594-spi.c | 129 drivers/misc/Kconfig | 37 drivers/misc/Makefile | 4 drivers/misc/dma-buf-phys.c | 221 drivers/misc/pci_endpoint_test.c | 19 drivers/misc/sram-dma-heap.c | 245 drivers/misc/sram.c | 6 drivers/misc/sram.h | 16 drivers/misc/tps6594-esm.c | 149 drivers/misc/tps6594-pfsm.c | 306 drivers/mmc/host/sdhci_am654.c | 346 drivers/mtd/nand/spi/core.c | 217 drivers/mtd/nand/spi/winbond.c | 242 drivers/mtd/spi-nor/core.c | 237 drivers/mtd/spi-nor/sfdp.c | 7 drivers/mux/mmio.c | 19 drivers/net/can/m_can/m_can.c | 75 drivers/net/can/m_can/m_can.h | 7 drivers/net/can/m_can/m_can_platform.c | 21 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 9 drivers/net/ethernet/cavium/liquidio/lio_main.c | 11 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c | 13 drivers/net/ethernet/freescale/fec_ptp.c | 13 drivers/net/ethernet/microchip/lan966x/lan966x_main.c | 5 drivers/net/ethernet/qlogic/qede/qede_ptp.c | 13 drivers/net/ethernet/sfc/ptp.c | 7 drivers/net/ethernet/sfc/siena/ptp.c | 7 drivers/net/ethernet/ti/Kconfig | 45 drivers/net/ethernet/ti/Makefile | 12 drivers/net/ethernet/ti/am65-cpsw-ethtool.c | 132 drivers/net/ethernet/ti/am65-cpsw-nuss.c | 561 drivers/net/ethernet/ti/am65-cpsw-nuss.c.orig | 3218 + drivers/net/ethernet/ti/am65-cpsw-nuss.h | 24 drivers/net/ethernet/ti/am65-cpsw-qos.c | 881 drivers/net/ethernet/ti/am65-cpsw-qos.h | 49 drivers/net/ethernet/ti/am65-cpts.c | 341 drivers/net/ethernet/ti/am65-cpts.h | 21 drivers/net/ethernet/ti/am65-debugfs.c | 152 drivers/net/ethernet/ti/cpsw-proxy-client.c | 2445 drivers/net/ethernet/ti/cpsw_ale.c | 10 drivers/net/ethernet/ti/cpsw_ale.h | 1 drivers/net/ethernet/ti/eth_remote_msg.h | 464 drivers/net/ethernet/ti/icss_iep.c | 889 drivers/net/ethernet/ti/icss_iep.h | 110 drivers/net/ethernet/ti/icssg_classifier.c | 362 drivers/net/ethernet/ti/icssg_config.c | 896 drivers/net/ethernet/ti/icssg_config.h | 229 drivers/net/ethernet/ti/icssg_ethtool.c | 565 drivers/net/ethernet/ti/icssg_mii_cfg.c | 120 drivers/net/ethernet/ti/icssg_mii_rt.h | 151 drivers/net/ethernet/ti/icssg_prueth.c | 3558 + drivers/net/ethernet/ti/icssg_prueth.h | 395 drivers/net/ethernet/ti/icssg_qos.c | 469 drivers/net/ethernet/ti/icssg_qos.h | 136 drivers/net/ethernet/ti/icssg_queues.c | 50 drivers/net/ethernet/ti/icssg_switch_map.h | 234 drivers/net/ethernet/ti/icssg_switchdev.c | 477 drivers/net/ethernet/ti/icssg_switchdev.h | 13 drivers/net/ethernet/ti/j721e-cpsw-virt-mac.c | 1622 drivers/net/phy/dp83869.c | 14 drivers/net/phy/mscc/mscc.h | 2 drivers/net/phy/mscc/mscc_main.c | 20 drivers/of/unittest-data/Makefile | 66 drivers/of/unittest-data/overlay.dts | 64 drivers/of/unittest-data/overlay.dtso | 64 drivers/of/unittest-data/overlay_0.dts | 14 drivers/of/unittest-data/overlay_0.dtso | 14 drivers/of/unittest-data/overlay_1.dts | 14 drivers/of/unittest-data/overlay_1.dtso | 14 drivers/of/unittest-data/overlay_10.dts | 27 drivers/of/unittest-data/overlay_10.dtso | 27 drivers/of/unittest-data/overlay_11.dts | 28 drivers/of/unittest-data/overlay_11.dtso | 28 drivers/of/unittest-data/overlay_12.dts | 14 drivers/of/unittest-data/overlay_12.dtso | 14 drivers/of/unittest-data/overlay_13.dts | 14 drivers/of/unittest-data/overlay_13.dtso | 14 drivers/of/unittest-data/overlay_15.dts | 30 drivers/of/unittest-data/overlay_15.dtso | 30 drivers/of/unittest-data/overlay_16.dts | 15 drivers/of/unittest-data/overlay_16.dtso | 15 drivers/of/unittest-data/overlay_17.dts | 15 drivers/of/unittest-data/overlay_17.dtso | 15 drivers/of/unittest-data/overlay_18.dts | 15 drivers/of/unittest-data/overlay_18.dtso | 15 drivers/of/unittest-data/overlay_19.dts | 15 drivers/of/unittest-data/overlay_19.dtso | 15 drivers/of/unittest-data/overlay_2.dts | 9 drivers/of/unittest-data/overlay_2.dtso | 9 drivers/of/unittest-data/overlay_20.dts | 15 drivers/of/unittest-data/overlay_20.dtso | 15 drivers/of/unittest-data/overlay_3.dts | 9 drivers/of/unittest-data/overlay_3.dtso | 9 drivers/of/unittest-data/overlay_4.dts | 18 drivers/of/unittest-data/overlay_4.dtso | 18 drivers/of/unittest-data/overlay_5.dts | 9 drivers/of/unittest-data/overlay_5.dtso | 9 drivers/of/unittest-data/overlay_6.dts | 10 drivers/of/unittest-data/overlay_6.dtso | 10 drivers/of/unittest-data/overlay_7.dts | 10 drivers/of/unittest-data/overlay_7.dtso | 10 drivers/of/unittest-data/overlay_8.dts | 10 drivers/of/unittest-data/overlay_8.dtso | 10 drivers/of/unittest-data/overlay_9.dts | 10 drivers/of/unittest-data/overlay_9.dtso | 10 drivers/of/unittest-data/overlay_bad_add_dup_node.dts | 28 drivers/of/unittest-data/overlay_bad_add_dup_node.dtso | 28 drivers/of/unittest-data/overlay_bad_add_dup_prop.dts | 39 drivers/of/unittest-data/overlay_bad_add_dup_prop.dtso | 39 drivers/of/unittest-data/overlay_bad_phandle.dts | 14 drivers/of/unittest-data/overlay_bad_phandle.dtso | 14 drivers/of/unittest-data/overlay_bad_symbol.dts | 16 drivers/of/unittest-data/overlay_bad_symbol.dtso | 16 drivers/of/unittest-data/overlay_base.dts | 5 drivers/of/unittest-data/overlay_base.dtso | 5 drivers/of/unittest-data/overlay_gpio_01.dts | 23 drivers/of/unittest-data/overlay_gpio_01.dtso | 23 drivers/of/unittest-data/overlay_gpio_02a.dts | 16 drivers/of/unittest-data/overlay_gpio_02a.dtso | 16 drivers/of/unittest-data/overlay_gpio_02b.dts | 16 drivers/of/unittest-data/overlay_gpio_02b.dtso | 16 drivers/of/unittest-data/overlay_gpio_03.dts | 23 drivers/of/unittest-data/overlay_gpio_03.dtso | 23 drivers/of/unittest-data/overlay_gpio_04a.dts | 16 drivers/of/unittest-data/overlay_gpio_04a.dtso | 16 drivers/of/unittest-data/overlay_gpio_04b.dts | 16 drivers/of/unittest-data/overlay_gpio_04b.dtso | 16 drivers/of/unittest-data/testcases.dts | 21 drivers/of/unittest-data/testcases.dtso | 21 drivers/of/unittest.c | 50 drivers/pci/controller/cadence/Kconfig | 12 drivers/pci/controller/cadence/Makefile | 2 drivers/pci/controller/cadence/pci-j721e-ep.c | 144 drivers/pci/controller/cadence/pci-j721e-host.c | 463 drivers/pci/controller/cadence/pci-j721e.c | 385 drivers/pci/controller/cadence/pci-j721e.h | 110 drivers/pci/controller/cadence/pcie-cadence-ep.c | 18 drivers/pci/controller/cadence/pcie-cadence-host.c | 33 drivers/pci/controller/cadence/pcie-cadence.c | 21 drivers/pci/controller/cadence/pcie-cadence.h | 21 drivers/pci/controller/dwc/pci-keystone.c | 356 drivers/pci/controller/pci-tegra.c | 5 drivers/pci/pcie/aspm.c | 3 drivers/phy/cadence/cdns-dphy-rx.c | 39 drivers/phy/cadence/phy-cadence-sierra.c | 136 drivers/phy/cadence/phy-cadence-torrent.c | 3178 - drivers/phy/phy-core-mipi-dphy.c | 31 drivers/phy/phy-core.c | 51 drivers/phy/ti/phy-gmii-sel.c | 114 drivers/phy/ti/phy-j721e-wiz.c | 105 drivers/pinctrl/Kconfig | 10 drivers/pinctrl/Makefile | 1 drivers/pinctrl/pinctrl-single.c | 12 drivers/pinctrl/pinctrl-tps6594.c | 365 drivers/ptp/ptp_dte.c | 5 drivers/regulator/Kconfig | 13 drivers/regulator/Makefile | 1 drivers/regulator/tps6594-regulator.c | 614 drivers/remoteproc/Kconfig | 13 drivers/remoteproc/Makefile | 3 drivers/remoteproc/omap_remoteproc.h | 4 drivers/remoteproc/pru_rproc.c | 366 drivers/remoteproc/ti_k3_common.c | 446 drivers/remoteproc/ti_k3_common.h | 116 drivers/remoteproc/ti_k3_dsp_remoteproc.c | 560 drivers/remoteproc/ti_k3_m4_remoteproc.c | 596 drivers/remoteproc/ti_k3_r5_remoteproc.c | 298 drivers/rpmsg-kdrv/Kconfig | 48 drivers/rpmsg-kdrv/Makefile | 5 drivers/rpmsg-kdrv/rpmsg_kdrv.c | 745 drivers/rpmsg-kdrv/rpmsg_kdrv_demo.c | 214 drivers/rpmsg-kdrv/rpmsg_kdrv_display.c | 488 drivers/rpmsg-kdrv/rpmsg_kdrv_internal.h | 45 drivers/rpmsg-kdrv/rpmsg_kdrv_switch.c | 937 drivers/rpmsg-kdrv/shared/rpmsg-kdrv-transport-common.h | 80 drivers/rpmsg-kdrv/shared/rpmsg-kdrv-transport-demo.h | 78 drivers/rpmsg-kdrv/shared/rpmsg-kdrv-transport-display.h | 223 drivers/rpmsg-kdrv/shared/rpmsg-kdrv-transport-switch.h | 664 drivers/rpmsg-kdrv/shared/rpmsg-kdrv-transport.h | 83 drivers/rpmsg/Kconfig | 13 drivers/rpmsg/Makefile | 1 drivers/rpmsg/rpmsg_char.c | 4 drivers/rpmsg/rpmsg_pru.c | 351 drivers/rtc/Kconfig | 9 drivers/rtc/Makefile | 1 drivers/rtc/rtc-tps6594.c | 473 drivers/soc/ti/k3-ringacc.c | 1 drivers/soc/ti/k3-socinfo.c | 4 drivers/soc/ti/pruss.c | 255 drivers/soc/ti/pruss.h | 88 drivers/spi/spi-cadence-quadspi.c | 972 drivers/spi/spi-mem.c | 12 drivers/spi/spi-omap2-mcspi.c | 189 drivers/staging/pi433/Documentation/devicetree/pi433-overlay.dts | 48 drivers/staging/pi433/Documentation/devicetree/pi433-overlay.dtso | 48 drivers/staging/pi433/Documentation/devicetree/pi433.txt | 6 drivers/thermal/k3_j72xx_bandgap.c | 281 drivers/tty/serial/8250/8250_omap.c | 75 drivers/tty/serial/8250/8250_omap.c.orig | 1786 drivers/tty/serial/8250/8250_pruss.c | 214 drivers/tty/serial/8250/Kconfig | 10 drivers/tty/serial/8250/Makefile | 1 drivers/ufs/host/ti-j721e-ufs.c | 2 drivers/usb/cdns3/cdns3-gadget.c | 4 drivers/usb/cdns3/cdns3-ti.c | 15 drivers/usb/cdns3/core.h | 1 drivers/usb/cdns3/drd.c | 9 drivers/usb/cdns3/drd.h | 3 drivers/usb/dwc3/core.c | 7 drivers/usb/dwc3/dwc3-am62.c | 162 drivers/usb/host/ehci-exynos.c | 23 drivers/usb/host/ohci-exynos.c | 23 drivers/usb/typec/tipd/core.c | 99 drivers/watchdog/rti_wdt.c | 6 include/drm/drm_bridge.h | 73 include/drm/drm_panel.h | 10 include/dt-bindings/mux/ti-serdes.h | 93 include/dt-bindings/pinctrl/k3.h | 50 include/linux/dma/k3-udma-glue.h | 8 include/linux/dma/ti-cppi5.h | 1 include/linux/gpio_keys.h | 2 include/linux/i2c-atr.h | 116 include/linux/iopoll.h | 22 include/linux/mfd/tps65219.h | 345 include/linux/mfd/tps6594.h | 1020 include/linux/mtd/spinand.h | 154 include/linux/phy/phy-mipi-dphy.h | 3 include/linux/phy/phy.h | 16 include/linux/pruss_driver.h | 123 include/linux/reboot.h | 3 include/linux/remoteproc/pruss.h | 83 include/linux/rpmsg-remotedev/rpmsg-remotedev.h | 220 include/linux/soc/ti/ti_sci_protocol.h | 44 include/linux/spi/spi-mem.h | 50 include/media/i2c/ds90ub9xx.h | 22 include/media/v4l2-mc.h | 8 include/media/v4l2-subdev.h | 399 include/sound/dmaengine_pcm.h | 1 include/uapi/linux/counter.h | 4 include/uapi/linux/dma_buf_phys.h | 35 include/uapi/linux/media-bus-format.h | 10 include/uapi/linux/tps6594_pfsm.h | 37 include/uapi/linux/v4l2-controls.h | 6 include/uapi/linux/v4l2-subdev.h | 74 include/uapi/linux/videodev2.h | 11 kernel/configs/debug.config | 10 kernel/configs/no_smp.config | 6 kernel/configs/ti_arm64_prune.config | 485 kernel/configs/ti_early_display.config | 185 kernel/configs/ti_multi_v7_prune.config | 173 kernel/configs/ti_rt.config | 192 kernel/reboot.c | 3 kernel/reboot.c.orig | 1329 net/hsr/hsr_device.c | 72 net/hsr/hsr_main.h | 1 net/hsr/hsr_slave.c | 18 samples/Kconfig | 7 samples/Makefile | 1 samples/pfsm/Makefile | 4 samples/pfsm/pfsm-wakeup.c | 125 samples/rpmsg/rpmsg_client_sample.c | 1 scripts/Makefile.build | 2 scripts/Makefile.defconf | 29 scripts/Makefile.lib | 22 sound/core/pcm_dmaengine.c | 10 sound/soc/soc-generic-dmaengine-pcm.c | 8 889 files changed, 246781 insertions(+), 19272 deletions(-) Index: linux-6.1.80/.clang-format =================================================================== --- linux-6.1.80.orig/.clang-format +++ linux-6.1.80/.clang-format @@ -190,6 +190,7 @@ ForEachMacros: - 'for_each_active_dev_scope' - 'for_each_active_drhd_unit' - 'for_each_active_iommu' + - 'for_each_active_route' - 'for_each_aggr_pgid' - 'for_each_available_child_of_node' - 'for_each_bench' Index: linux-6.1.80/Documentation/ABI/testing/sysfs-bus-counter =================================================================== --- linux-6.1.80.orig/Documentation/ABI/testing/sysfs-bus-counter +++ linux-6.1.80/Documentation/ABI/testing/sysfs-bus-counter @@ -65,10 +65,14 @@ What: /sys/bus/counter/devices/counterX What: /sys/bus/counter/devices/counterX/countY/function_available What: /sys/bus/counter/devices/counterX/countY/prescaler_available What: /sys/bus/counter/devices/counterX/countY/signalZ_action_available +What: /sys/bus/counter/devices/counterX/edge_capture_unit_prescaler_available +What: /sys/bus/counter/devices/counterX/latch_mode_available +What: /sys/bus/counter/devices/counterX/signalY/index_polarity_available +What: /sys/bus/counter/devices/counterX/signalY/synchronous_mode_available KernelVersion: 5.2 Contact: linux-iio@vger.kernel.org Description: - Discrete set of available values for the respective Count Y + Discrete set of available values for the respective component configuration are listed in this file. Values are delimited by newline characters. @@ -153,6 +157,14 @@ Description: updates the respective count. Quadrature encoding determines the direction. +What: /sys/bus/counter/devices/counterX/countY/latched_count +KernelVersion: 5.16 +Contact: linux-iio@vger.kernel.org +Description: + Latched count data of Count Y represented as a string. The value + is latched in based on the trigger selected by the + counterX/latch_mode attribute. + What: /sys/bus/counter/devices/counterX/countY/name KernelVersion: 5.2 Contact: linux-iio@vger.kernel.org @@ -222,6 +234,7 @@ What: /sys/bus/counter/devices/counterX What: /sys/bus/counter/devices/counterX/countY/direction_component_id What: /sys/bus/counter/devices/counterX/countY/enable_component_id What: /sys/bus/counter/devices/counterX/countY/error_noise_component_id +What: /sys/bus/counter/devices/counterX/countY/latched_count_component_id What: /sys/bus/counter/devices/counterX/countY/prescaler_component_id What: /sys/bus/counter/devices/counterX/countY/preset_component_id What: /sys/bus/counter/devices/counterX/countY/preset_enable_component_id @@ -234,6 +247,14 @@ What: /sys/bus/counter/devices/counterX What: /sys/bus/counter/devices/counterX/signalY/polarity_component_id What: /sys/bus/counter/devices/counterX/signalY/synchronous_mode_component_id What: /sys/bus/counter/devices/counterX/signalY/frequency_component_id +What: /sys/bus/counter/devices/edge_capture_unit_enable_component_id +What: /sys/bus/counter/devices/edge_capture_unit_latched_period_component_id +What: /sys/bus/counter/devices/edge_capture_unit_max_period_component_id +What: /sys/bus/counter/devices/edge_capture_unit_prescaler_component_id +What: /sys/bus/counter/devices/latch_mode_component_id +What: /sys/bus/counter/devices/unit_timer_enable_component_id +What: /sys/bus/counter/devices/unit_timer_period_component_id +What: /sys/bus/counter/devices/unit_timer_time_component_id KernelVersion: 5.16 Contact: linux-iio@vger.kernel.org Description: @@ -249,6 +270,38 @@ Description: shorter or equal to configured value are ignored. Value 0 means filter is disabled. +What: /sys/bus/counter/devices/edge_capture_unit_enable +KernelVersion: 5.16 +Contact: linux-iio@vger.kernel.org +Description: + Read/write attribute that starts or stops the Edge Capture Unit. + Valid values are boolean. + +What: /sys/bus/counter/devices/edge_capture_unit_latched_period +KernelVersion: 5.16 +Contact: linux-iio@vger.kernel.org +Description: + Latched period of the Edge Capture Unit represented as a string. + The value is latched in based on the trigger selected by the + counterX/latch_mode attribute. Units are nanoseconds. + +What: /sys/bus/counter/devices/edge_capture_unit_max_period +KernelVersion: 5.16 +Contact: linux-iio@vger.kernel.org +Description: + Read/write attribute that selects the maximum period that can + be measured by the Edge Capture Unit. Units are nanoseconds. + +What: /sys/bus/counter/devices/edge_capture_unit_prescaler +KernelVersion: 5.16 +Contact: linux-iio@vger.kernel.org +Description: + Read/write attribute that selects the how the + counterX/countY/count value is scaled coming in to the Edge + Capture Unit. This acts like a clock divider, e.g. if a value + of 4 is selected, the Edge Capture Unit will measure the period + between every 4 counts. + What: /sys/bus/counter/devices/counterX/events_queue_size KernelVersion: 5.16 Contact: linux-iio@vger.kernel.org @@ -257,6 +310,22 @@ Description: counter_event data structures. The number of elements will be rounded-up to a power of 2. +What: /sys/bus/counter/devices/counterX/latch_mode +KernelVersion: 5.16 +Contact: linux-iio@vger.kernel.org +Description: + Read/write attribute that selects the trigger for latching + values. Valid values are device-specific (given by + latch_mode_available attribute) and may include: + + "Read count": + Reading the countY/count attribute latches values. + + "Unit timeout": + Unit timer timeout event latches values. + + The latched values can be read from latched_* attributes. + What: /sys/bus/counter/devices/counterX/name KernelVersion: 5.2 Contact: linux-iio@vger.kernel.org @@ -311,13 +380,13 @@ Description: Active level of index input Signal Y; irrelevant in non-synchronous load mode. -What: /sys/bus/counter/devices/counterX/signalY/index_polarity_available -What: /sys/bus/counter/devices/counterX/signalY/synchronous_mode_available +What: /sys/bus/counter/devices/counterX/signalY/name KernelVersion: 5.2 Contact: linux-iio@vger.kernel.org Description: - Discrete set of available values for the respective Signal Y - configuration are listed in this file. + Read-only attribute that indicates the device-specific name of + Signal Y. If possible, this should match the name of the + respective signal as it appears in the device datasheet. What: /sys/bus/counter/devices/counterX/signalY/polarity KernelVersion: 6.1 @@ -332,14 +401,6 @@ Description: negative: Signal low state considered active level (falling edge). -What: /sys/bus/counter/devices/counterX/signalY/name -KernelVersion: 5.2 -Contact: linux-iio@vger.kernel.org -Description: - Read-only attribute that indicates the device-specific name of - Signal Y. If possible, this should match the name of the - respective signal as it appears in the device datasheet. - What: /sys/bus/counter/devices/counterX/signalY/signal KernelVersion: 5.2 Contact: linux-iio@vger.kernel.org @@ -380,3 +441,24 @@ KernelVersion: 6.1 Contact: linux-iio@vger.kernel.org Description: Read-only attribute that indicates the signal Y frequency, in Hz. + +What: /sys/bus/counter/devices/unit_timer_enable +KernelVersion: 5.16 +Contact: linux-iio@vger.kernel.org +Description: + Read/write attribute that starts or stops the unit timer. Valid + values are boolean. + +What: /sys/bus/counter/devices/unit_timer_period +KernelVersion: 5.16 +Contact: linux-iio@vger.kernel.org +Description: + Read/write attribute that selects the unit timer timeout in + nanoseconds. + +What: /sys/bus/counter/devices/unit_timer_time +KernelVersion: 5.16 +Contact: linux-iio@vger.kernel.org +Description: + Read/write attribute that indicates the current time of the + unit timer in nanoseconds. Index: linux-6.1.80/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml @@ -42,12 +42,16 @@ properties: - const: ti,am654-sci reg-names: - description: | - Specifies the debug messages memory mapped region that is optionally - made available from TI-SCI controller. - const: debug_messages + items: + - const: debug_messages + - const: lpm + minItems: 1 reg: + items: + - description: | + Specifies the debug messages memory mapped region that is optionally + made available from TI-SCI controller. minItems: 1 mbox-names: @@ -65,6 +69,12 @@ properties: description: Determines If system reboot can be triggered by SoC reboot type: boolean + ti,partial-io-wakeup-sources: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandles to devicetree nodes that can wakeup the SoC from the + Partial IO poweroff mode. + ti,host-id: $ref: /schemas/types.yaml#/definitions/uint32 description: | Index: linux-6.1.80/Documentation/devicetree/bindings/arm/ti/k3.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -25,10 +25,18 @@ properties: - ti,am62a7-sk - const: ti,am62a7 + - description: K3 AM62P5 SoC and Boards + items: + - enum: + - ti,am62p5-sk + - const: ti,am62p5 + - description: K3 AM625 SoC items: - enum: + - beagle,am625-beagleplay - ti,am625-sk + - ti,am62-lp-sk - const: ti,am625 - description: K3 AM642 SoC @@ -68,9 +76,23 @@ properties: - description: K3 J721s2 SoC items: - enum: + - ti,am68-sk - ti,j721s2-evm - const: ti,j721s2 + - description: K3 J722S SoC and Boards + items: + - enum: + - ti,j722s-evm + - const: ti,j722s + + - description: K3 J784s4 SoC + items: + - enum: + - ti,am69-sk + - ti,j784s4-evm + - const: ti,j784s4 + additionalProperties: true ... Index: linux-6.1.80/Documentation/devicetree/bindings/clock/ti,am62-audio-refclk.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/clock/ti,am62-audio-refclk.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,am62-audio-refclk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Audio Reference Clock + +maintainers: + - Jai Luthra + +properties: + compatible: + items: + - const: ti,am62-audio-refclk + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + - clocks + +additionalProperties: false + +examples: + - | + audio_refclk0: clock@82e0 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e0 0x4>; + clocks = <&k3_clks 157 0>; + assigned-clocks = <&k3_clks 157 0>; + assigned-clock-parents = <&k3_clks 157 8>; + #clock-cells = <0>; + }; Index: linux-6.1.80/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml @@ -16,7 +16,6 @@ properties: - ti,am654-ehrpwm-tbclk - ti,am64-epwm-tbclk - ti,am62-epwm-tbclk - - const: syscon "#clock-cells": const: 1 @@ -33,8 +32,8 @@ additionalProperties: false examples: - | - ehrpwm_tbclk: syscon@4140 { - compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + ehrpwm_tbclk: clock@4140 { + compatible = "ti,am654-ehrpwm-tbclk"; reg = <0x4140 0x18>; #clock-cells = <1>; }; Index: linux-6.1.80/Documentation/devicetree/bindings/counter/ti-eqep.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/counter/ti-eqep.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/counter/ti-eqep.yaml @@ -21,7 +21,7 @@ properties: maxItems: 1 clocks: - description: The clock that determines the SYSCLKOUT rate for the eQEP + description: The clock that determines the clock rate for the eQEP peripheral. maxItems: 1 @@ -42,9 +42,10 @@ examples: eqep0: counter@180 { compatible = "ti,am3352-eqep"; reg = <0x180 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "sysclkout"; - interrupts = <79>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 59 0>; + clock-names = "fck"; + interrupts = ; }; ... Index: linux-6.1.80/Documentation/devicetree/bindings/crypto/ti,mcrc.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/crypto/ti,mcrc.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/ti,mcrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments MCRC bindings + +maintainers: + - Kamlesh Gurudasani + +properties: + compatible: + const: ti,mcrc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + mcrc: mcrc@30300000 { + compatible = "ti,mcrc"; + reg = <0x00 0x30300000 0x00 0x1000>; + clocks = <&k3_clks 116 0>; + power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; + }; + +... Index: linux-6.1.80/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml @@ -66,10 +66,22 @@ patternProperties: required: - compatible - reg - - power-domains - dmas - dma-names +allOf: + - if: + properties: + compatible: + contains: + const: ti,am62-sa3ul + then: + properties: + power-domains: false + else: + required: + - power-domains + additionalProperties: false examples: Index: linux-6.1.80/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt +++ /dev/null @@ -1,112 +0,0 @@ -Cadence DSI bridge -================== - -The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes. - -Required properties: -- compatible: should be set to "cdns,dsi". -- reg: physical base address and length of the controller's registers. -- interrupts: interrupt line connected to the DSI bridge. -- clocks: DSI bridge clocks. -- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk". -- phys: phandle link to the MIPI D-PHY controller. -- phy-names: must contain "dphy". -- #address-cells: must be set to 1. -- #size-cells: must be set to 0. - -Optional properties: -- resets: DSI reset lines. -- reset-names: can contain "dsi_p_rst". - -Required subnodes: -- ports: Ports as described in Documentation/devicetree/bindings/graph.txt. - 2 ports are available: - * port 0: this port is only needed if some of your DSI devices are - controlled through an external bus like I2C or SPI. Can have at - most 4 endpoints. The endpoint number is directly encoding the - DSI virtual channel used by this device. - * port 1: represents the DPI input. - Other ports will be added later to support the new kind of inputs. - -- one subnode per DSI device connected on the DSI bus. Each DSI device should - contain a reg property encoding its virtual channel. - -Example: - dsi0: dsi@fd0c0000 { - compatible = "cdns,dsi"; - reg = <0x0 0xfd0c0000 0x0 0x1000>; - clocks = <&pclk>, <&sysclk>; - clock-names = "dsi_p_clk", "dsi_sys_clk"; - interrupts = <1>; - phys = <&dphy0>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi0_dpi_input: endpoint { - remote-endpoint = <&xxx_dpi_output>; - }; - }; - }; - - panel: dsi-dev@0 { - compatible = ""; - reg = <0>; - }; - }; - -or - - dsi0: dsi@fd0c0000 { - compatible = "cdns,dsi"; - reg = <0x0 0xfd0c0000 0x0 0x1000>; - clocks = <&pclk>, <&sysclk>; - clock-names = "dsi_p_clk", "dsi_sys_clk"; - interrupts = <1>; - phys = <&dphy1>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dsi0_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi_panel_input>; - }; - }; - - port@1 { - reg = <1>; - dsi0_dpi_input: endpoint { - remote-endpoint = <&xxx_dpi_output>; - }; - }; - }; - }; - - i2c@xxx { - panel: panel@59 { - compatible = ""; - reg = <0x59>; - - port { - dsi_panel_input: endpoint { - remote-endpoint = <&dsi0_output>; - }; - }; - }; - }; Index: linux-6.1.80/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/cdns,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence DSI bridge + +maintainers: + - Boris Brezillon + +description: | + CDNS DSI is a bridge device which converts DPI to DSI + +properties: + compatible: + enum: + - cdns,dsi + - ti,j721e-dsi + + reg: + minItems: 1 + items: + - description: + Register block for controller's registers. + - description: + Register block for wrapper settings registers in case of TI J7 SoCs. + + clocks: + items: + - description: PSM clock, used by the IP + - description: sys clock, used by the IP + + clock-names: + items: + - const: dsi_p_clk + - const: dsi_sys_clk + + phys: + maxItems: 1 + + phy-names: + const: dphy + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: dsi_p_rst + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port representing the DSI output. It can have + at most 4 endpoints. The endpoint number is directly encoding + the DSI virtual channel used by this device. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Input port representing the DPI input. + + required: + - port@1 + +allOf: + - $ref: ../dsi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: ti,j721e-dsi + then: + properties: + reg: + minItems: 2 + maxItems: 2 + power-domains: + maxItems: 1 + else: + properties: + reg: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + - ports + +unevaluatedProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + dsi@fd0c0000 { + compatible = "cdns,dsi"; + reg = <0x0 0xfd0c0000 0x0 0x1000>; + clocks = <&pclk>, <&sysclk>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + interrupts = <1>; + phys = <&dphy0>; + phy-names = "dphy"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&xxx_dpi_output>; + }; + }; + }; + + panel@0 { + compatible = "panasonic,vvx10f034n00"; + reg = <0>; + power-supply = <&vcc_lcd_reg>; + }; + }; + }; + + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + dsi@fd0c0000 { + compatible = "cdns,dsi"; + reg = <0x0 0xfd0c0000 0x0 0x1000>; + clocks = <&pclk>, <&sysclk>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + interrupts = <1>; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_panel_input>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&xxx_dpi_output>; + }; + }; + }; + }; + }; Index: linux-6.1.80/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml @@ -57,6 +57,12 @@ properties: interrupts: maxItems: 1 + cdns,no-hpd: + type: boolean + description: + Set if the HPD line on the bridge isn't hooked up to anything or is + otherwise unusable. + ports: $ref: /schemas/graph.yaml#/properties/ports Index: linux-6.1.80/Documentation/devicetree/bindings/display/panel/panel-edp.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/display/panel/panel-edp.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/display/panel/panel-edp.yaml @@ -86,7 +86,11 @@ allOf: properties: compatible: - const: edp-panel + enum: + # Generic Panel EDP + - edp-panel + # TI Simple Panel EDP + - ti,panel-edp hpd-reliable-delay-ms: description: Index: linux-6.1.80/Documentation/devicetree/bindings/display/panel/panel-simple.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -220,6 +220,8 @@ properties: - lg,lp120up1 # LG 12.9" (2560x1700 pixels) TFT LCD panel - lg,lp129qe + # Lincoln Technology Solutions, LCD185-101CT 10.1" TFT 1920x1200 + - lincolntech,lcd185-101ct # Logic Technologies LT161010-2NHC 7" WVGA TFT Cap Touch Module - logictechno,lt161010-2nhc # Logic Technologies LT161010-2NHR 7" WVGA TFT Resistive Touch Module @@ -230,6 +232,10 @@ properties: - logictechno,lttd800480070-l2rt # Logic Technologies LTTD800480070-L6WH-RT 7” 800x480 TFT Resistive Touch Module - logictechno,lttd800480070-l6wh-rt + # Microtips Technology MF-101HIEBCAF0 10.1" WUXGA (1920x1200) TFT LCD panel + - microtips,mf-101hiebcaf0 + # Microtips Technology MF-103HIEB0GA0 10.25" 1920x720 TFT LCD panel + - microtips,mf-103hieb0ga0 # Mitsubishi "AA070MC01 7.0" WVGA TFT LCD panel - mitsubishi,aa070mc01-ca1 # Multi-Inno Technology Co.,Ltd MI0700S4T-6 7" 800x480 TFT Resistive Touch Module Index: linux-6.1.80/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -19,7 +19,11 @@ description: | properties: compatible: - const: ti,am65x-dss + enum: + - ti,am625-dss + - ti,am62a7-dss + - ti,am62p51-dss + - ti,am65x-dss reg: description: @@ -32,6 +36,7 @@ properties: - description: OVR2 overlay manager for vp2 - description: VP1 video port 1 - description: VP2 video port 2 + - description: common1 DSS register area reg-names: items: @@ -42,6 +47,7 @@ properties: - const: ovr2 - const: vp1 - const: vp2 + - const: common1 clocks: items: @@ -67,7 +73,8 @@ properties: maxItems: 1 power-domains: - maxItems: 1 + minItems: 1 + maxItems: 3 description: phandle to the associated power domain dma-coherent: @@ -80,12 +87,22 @@ properties: port@0: $ref: /schemas/graph.yaml#/properties/port description: - The DSS OLDI output port node form video port 1 + For AM625, AM62P51 and AM65x, this maps to DSS OLDI output + port node (OLDI TX 0) forwarded from video port 1. + For AM62A7, this maps to DSS DPI output port node forwarded + from video port 2. (video port 1 remains tied off.) port@1: $ref: /schemas/graph.yaml#/properties/port description: - The DSS DPI output port node from video port 2 + This maps to DSS DPI output port node forwarded from + video port 2. + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: + For AM625, AM62P51, this maps to DSS OLDI output port node + (OLDI TX 1) forwarded from video port 1. ti,am65x-oldi-io-ctrl: $ref: "/schemas/types.yaml#/definitions/phandle" @@ -102,6 +119,112 @@ properties: Input memory (from main memory to dispc) bandwidth limit in bytes per second + ti,dss-shared-mode: + type: boolean + description: + TI DSS7 supports sharing of display between multiple hosts + as it provides separate register space for display configuration and + unique interrupt line to each host. + One of the host is provided access to the global display + configuration labelled as "common" region of DSS allows that host + exclusive access to global registers of DSS while other host can + configure the display for it's usage using a separate register + space labelled as "common1". + The DSS resources can be partitioned in such a way that one or more + of the video planes are owned by Linux whereas other video planes + can be owned by a remote core. + The video port controlling these planes acts as a shared video port + and it can be configured with write access either by Linux or the + remote core in which case Linux only has read-only access to that + video port. + + ti,dss-shared-mode-planes: + description: + The video layer that is owned by processing core running Linux. + The display driver running from Linux has exclusive write access to + this video layer. + $ref: /schemas/types.yaml#/definitions/string + enum: [vidl, vid] + + ti,dss-shared-mode-vp: + description: + The video port that is being used in context of processing core + running Linux with display susbsytem being used in shared mode. + This can be owned either by the processing core running Linux in + which case Linux has the write access and the responsibility to + configure this video port and the associated overlay manager or + it can be shared between core running Linux and a remote core + with remote core provided with write access to this video port and + associated overlay managers and remote core configures and drives + this video port also feeding data from one or more of the + video planes owned by Linux, with Linux only having read-only access + to this video port and associated overlay managers. + + $ref: /schemas/types.yaml#/definitions/string + enum: [vp1, vp2] + + ti,dss-shared-mode-common: + description: + The DSS register region owned by processing core running Linux. + $ref: /schemas/types.yaml#/definitions/string + enum: [common, common1] + + ti,dss-shared-mode-vp-owned: + description: + This tells whether processing core running Linux has write access to + the video ports enlisted in ti,dss-shared-mode-vps. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + ti,dss-shared-mode-plane-zorder: + description: + The zorder of the planes owned by Linux. + For the scenario where Linux is not having write access to associated + video port, this field is just for + informational purpose to enumerate the zorder configuration + being used by remote core. + + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + +dependencies: + ti,dss-shared-mode: [ 'ti,dss-shared-mode-planes', 'ti,dss-shared-mode-vp', + 'ti,dss-shared-mode-plane-zorder', 'ti,dss-shared-mode-vp-owned'] + ti,dss-shared-mode-vp: ['ti,dss-shared-mode', 'ti,dss-shared-mode-planes', + 'ti,dss-shared-mode-plane-zorder', 'ti,dss-shared-mode-vp-owned'] + ti,dss-shared-mode-planes: ['ti,dss-shared-mode', 'ti,dss-shared-mode-vp', + 'ti,dss-shared-mode-plane-zorder', 'ti,dss-shared-mode-vp-owned'] + ti,dss-shared-mode-plane-zorder: ['ti,dss-shared-mode-planes', 'ti,dss-shared-mode-vp', + 'ti,dss-shared-mode', 'ti,dss-shared-mode-vp-owned'] + ti,dss-shared-mode-vp-owned: ['ti,dss-shared-mode-planes', 'ti,dss-shared-mode-vp', + 'ti,dss-shared-mode', 'ti,dss-shared-mode-plane-zorder'] + +allOf: + - if: + properties: + compatible: + contains: + const: ti,am65x-dss + then: + properties: + ports: + properties: + port@2: false + + - if: + properties: + compatible: + contains: + const: ti,am62a7-dss + then: + properties: + ports: + properties: + port@1: false + port@2: false + ti,dss-shared-mode-vp: + enum: [vp2] + required: - compatible - reg @@ -127,9 +250,10 @@ examples: <0x04a07000 0x1000>, /* ovr1 */ <0x04a08000 0x1000>, /* ovr2 */ <0x04a0a000 0x1000>, /* vp1 */ - <0x04a0b000 0x1000>; /* vp2 */ + <0x04a0b000 0x1000>, /* vp2 */ + <0x04a01000 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 67 1>, Index: linux-6.1.80/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml @@ -28,13 +28,22 @@ description: | PDMAs can be configured via BCDMA split channel's peer registers to match with the configuration of the legacy peripheral. -allOf: - - $ref: /schemas/dma/dma-controller.yaml# - - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# - properties: compatible: - const: ti,am64-dmss-bcdma + enum: + - ti,am62a-dmss-bcdma-csirx + - ti,am64-dmss-bcdma + - ti,j721s2-dmss-bcdma-csi + - ti,j722s-dmss-bcdma-csi + + + reg: + minItems: 3 + maxItems: 5 + + reg-names: + minItems: 3 + maxItems: 5 "#dma-cells": const: 3 @@ -65,19 +74,13 @@ properties: cell 3: ASEL value for the channel - reg: - maxItems: 5 - - reg-names: - items: - - const: gcfg - - const: bchanrt - - const: rchanrt - - const: tchanrt - - const: ringrt - msi-parent: true + power-domains: + description: + Power domain if available + maxItems: 1 + ti,asel: $ref: /schemas/types.yaml#/definitions/uint32 description: ASEL value for non slave channels @@ -123,10 +126,80 @@ required: - msi-parent - ti,sci - ti,sci-dev-id - - ti,sci-rm-range-bchan - - ti,sci-rm-range-tchan - ti,sci-rm-range-rchan +allOf: + - $ref: /schemas/dma/dma-controller.yaml# + - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# + + - if: + properties: + compatible: + contains: + const: ti,am62a-dmss-bcdma-csirx + then: + properties: + ti,sci-rm-range-bchan: false + ti,sci-rm-range-tchan: false + + reg: + maxItems: 3 + + reg-names: + items: + - const: gcfg + - const: rchanrt + - const: ringrt + + required: + - power-domains + + - if: + properties: + compatible: + contains: + const: ti,am64-dmss-bcdma + then: + properties: + reg: + minItems: 5 + + reg-names: + items: + - const: gcfg + - const: bchanrt + - const: rchanrt + - const: tchanrt + - const: ringrt + + required: + - ti,sci-rm-range-bchan + - ti,sci-rm-range-tchan + + - if: + properties: + compatible: + contains: + enum: + - ti,j721s2-dmss-bcdma-csi + - ti,j722s-dmss-bcdma-csi + then: + properties: + ti,sci-rm-range-bchan: false + + reg: + maxItems: 4 + + reg-names: + items: + - const: gcfg + - const: rchanrt + - const: tchanrt + - const: ringrt + + required: + - ti,sci-rm-range-tchan + unevaluatedProperties: false examples: Index: linux-6.1.80/Documentation/devicetree/bindings/gpu/img,sgx530.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/gpu/img,sgx530.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/img,sgx530.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagination SGX530 3D Graphics Processing Unit + +maintainers: + - Andrew Davis + +description: | + SGX530 is a 3D Graphics Processing Unit from Imagination Technologies. + SGX is codename for 5th generation / Series 5 of PowerVR chipset family. + +properties: + $nodename: + pattern: '^gpu@[a-f0-9]+$' + + compatible: + items: + - enum: + - ti,omap3530-sgx530 # TI OMAP35x + - ti,omap3630-sgx530 # TI OMAP36x + - ti,am3352-sgx530 # TI AM33x + - ti,am4376-sgx530 # TI AM43x + - const: img,sgx530 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + #include + gpu@56000000 { + compatible = "ti,am4376-sgx530", "img,sgx530"; + reg = <0x56000000 0x10000>; + interrupts = ; + }; + +... Index: linux-6.1.80/Documentation/devicetree/bindings/gpu/img,sgx540.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/gpu/img,sgx540.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/img,sgx540.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagination SGX540 3D Graphics Processing Unit + +maintainers: + - Andrew Davis + +description: | + SGX540 is a 3D Graphics Processing Unit from Imagination Technologies. + SGX is codename for 5th generation / Series 5 of PowerVR chipset family. + +properties: + $nodename: + pattern: '^gpu@[a-f0-9]+$' + + compatible: + items: + - enum: + - ti,omap4430-sgx540 # TI OMAP443x + - ti,omap4460-sgx540 # TI OMAP446x + - const: img,sgx540 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + #include + gpu@0 { + compatible = "ti,omap4430-sgx540", "img,sgx540"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = ; + }; + +... Index: linux-6.1.80/Documentation/devicetree/bindings/gpu/img,sgx544.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/gpu/img,sgx544.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/img,sgx544.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagination SGX544 3D Graphics Processing Unit + +maintainers: + - Andrew Davis + +description: | + SGX544 is a 3D Graphics Processing Unit from Imagination Technologies. + SGX is codename for 5th generation / Series 5 of PowerVR chipset family. + +properties: + $nodename: + pattern: '^gpu@[a-f0-9]+$' + + compatible: + items: + - enum: + - ti,omap4470-sgx544 # TI OMAP447x + - ti,omap5432-sgx544 # TI OMAP543x + - ti,dra7-sgx544 # TI DRA7xx / AM57x + - ti,am654-sgx544 # TI AM654 + - const: img,sgx544 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: ti,am654-sgx544 + then: + properties: + power-domains: + minItems: 1 + required: + - power-domains + +examples: + - | + #include + #include + #include + bus { + #address-cells = <2>; + #size-cells = <2>; + gpu: gpu@7000000 { + compatible = "ti,am654-sgx544", "img,sgx544"; + reg = <0x0 0x7000000 0x0 0x10000>; + interrupts = ; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + }; + }; + +... Index: linux-6.1.80/Documentation/devicetree/bindings/gpu/ti,rogue.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/gpu/ti,rogue.yaml @@ -0,0 +1,209 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/ti,rogue.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments PowerVR Rogue GPU + +description: | + PowerVR Rogue is a family of 3D graphics processing units from Imagination + Technologies. Texas Instruments SoCs have integrated different generations of + PowerVR GPUs and this binding describes the GPU's integrated in Texas + Instruments SoCs in the K3 generation. + +maintainers: + - Darren Etheridge + - Randolph Sapp + +properties: + $nodename: + pattern: '^gpu@[a-f0-9]+$' + + compatible: + oneOf: + - items: + - enum: + - ti,j721s2-pvr + - const: img,pvr-bxs64 + - items: + - enum: + - ti,am62-pvr + - const: img,pvr-axe116m + - items: + - enum: + - ti,j721e-pvr + - const: img,pvr-ge8430 + - items: + - enum: + - ti,am62p-pvr + - const: img,pvr-bxs64 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + power-domains: + minItems: 1 + maxItems: 2 + + power-domain-names: + maxItems: 2 + + assigned-clocks: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + description: | + Allows users to override the default clock value used for the GPU. + Currently ignored on devices other than ti,am62p-pvr. This will be ported + to other devices soon. + +required: + - compatible + - reg + - interrupts + - power-domains + - clocks + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - ti,j721s2-pvr + - ti,j721e-pvr + - ti,am62-pvr + then: + properties: + reg: + minItems: 1 + interrupts: + minItems: 1 + clocks: + minItems: 1 + power-domains: + minItems: 1 + maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - ti,am62p-pvr + then: + required: + - power-domain-names + - assigned-clocks + - clock-names + properties: + reg: + minItems: 1 + interrupts: + minItems: 1 + clocks: + minItems: 1 + clock-names: + items: + - const: core + power-domains: + minItems: 2 + power-domain-names: + items: + - const: firmware + - const: dust + assigned-clocks: + minItems: 1 + assigned-clock-rates: + default: 800000000 + else: + properties: + assigned-clocks: false + assigned-clock-rates: false + +examples: + - | + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + gpu@fd00000 { + compatible = "ti,am62-pvr", "img,pvr-axe116m"; + reg = <0x00 0x0fd00000 0x00 0x20000>; + interrupts = ; + power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 187 0>; + }; + }; + + - | + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + gpu@4e20000000 { + compatible = "ti,j721s2-pvr", "img,pvr-bxs64"; + reg = <0x4e 0x20000000 0x00 0x80000>; + interrupts = ; + power-domains = <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 130 1>; + }; + }; + + - | + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + gpu@4e20000000 { + compatible = "ti,j721e-pvr", "img,pvr-ge8430"; + reg = <0x4e 0x20000000 0x00 0x80000>; + interrupts = ; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 125 0>; + }; + }; + + - | + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + gpu@fd80000 { + compatible = "ti,am62p-pvr", "img,pvr-bxs64"; + reg = <0x00 0x0fd80000 0x00 0x80000>; + interrupts = ; + power-domains = <&k3_pds 237 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 237 3>; + assigned-clock-rates = <720000000>; + power-domain-names = "firmware", "dust"; + clocks = <&k3_clks 237 3>; + clock-names = "core"; + }; + }; +... Index: linux-6.1.80/Documentation/devicetree/bindings/i2c/i2c-atr.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/i2c/i2c-atr.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-atr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common i2c address translator properties + +maintainers: + - Tomi Valkeinen + +description: + An I2C Address Translator (ATR) is a device with an I2C slave parent + ("upstream") port and N I2C master child ("downstream") ports, and + forwards transactions from upstream to the appropriate downstream port + with a modified slave address. The address used on the parent bus is + called the "alias" and is (potentially) different from the physical + slave address of the child bus. Address translation is done by the + hardware. + +properties: + i2c-alias-pool: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + I2C alias pool is a pool of I2C addresses on the main I2C bus that can be + used to access the remote peripherals on the serializer's I2C bus. The + addresses must be available, not used by any other peripheral. Each + remote peripheral is assigned an alias from the pool, and transactions to + that address will be forwarded to the remote peripheral, with the address + translated to the remote peripheral's real address. This property is not + needed if there are no I2C addressable remote peripherals. + +additionalProperties: true +... Index: linux-6.1.80/Documentation/devicetree/bindings/input/gpio-keys.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/input/gpio-keys.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/input/gpio-keys.yaml @@ -31,7 +31,23 @@ patternProperties: maxItems: 1 interrupts: - maxItems: 1 + oneOf: + - items: + - description: Optional key interrupt or wakeup interrupt + - items: + - description: Key interrupt + - description: Wakeup interrupt + + interrupt-names: + description: + Optional interrupt names, can be used to specify a separate dedicated + wake-up interrupt in addition to the gpio irq + oneOf: + - items: + - enum: [ irq, wakeup ] + - items: + - const: irq + - const: wakeup label: description: Descriptive name of the key. @@ -97,6 +113,20 @@ patternProperties: - required: - gpios + allOf: + - if: + properties: + interrupts: + minItems: 2 + required: + - interrupts + then: + properties: + interrupt-names: + minItems: 2 + required: + - interrupt-names + dependencies: wakeup-event-action: [ wakeup-source ] linux,input-value: [ gpios ] @@ -137,6 +167,15 @@ examples: linux,code = <108>; interrupts = <1 IRQ_TYPE_EDGE_FALLING>; }; + + key-wakeup { + label = "GPIO Key WAKEUP"; + linux,code = <143>; + interrupts-extended = <&intc 2 IRQ_TYPE_EDGE_FALLING>, + <&intc_wakeup 0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq", "wakeup"; + wakeup-source; + }; }; ... Index: linux-6.1.80/Documentation/devicetree/bindings/media/cdns,csi2rx.txt =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/media/cdns,csi2rx.txt +++ /dev/null @@ -1,100 +0,0 @@ -Cadence MIPI-CSI2 RX controller -=============================== - -The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI -lanes in input, and 4 different pixel streams in output. - -Required properties: - - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible - - reg: base address and size of the memory mapped region - - clocks: phandles to the clocks driving the controller - - clock-names: must contain: - * sys_clk: main clock - * p_clk: register bank clock - * pixel_if[0-3]_clk: pixel stream output clock, one for each stream - implemented in hardware, between 0 and 3 - -Optional properties: - - phys: phandle to the external D-PHY, phy-names must be provided - - phy-names: must contain "dphy", if the implementation uses an - external D-PHY - -Required subnodes: - - ports: A ports node with one port child node per device input and output - port, in accordance with the video interface bindings defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - port nodes are numbered as follows: - - Port Description - ----------------------------- - 0 CSI-2 input - 1 Stream 0 output - 2 Stream 1 output - 3 Stream 2 output - 4 Stream 3 output - - The stream output port nodes are optional if they are not - connected to anything at the hardware level or implemented - in the design.Since there is only one endpoint per port, - the endpoints are not numbered. - - -Example: - -csi2rx: csi-bridge@0d060000 { - compatible = "cdns,csi2rx"; - reg = <0x0d060000 0x1000>; - clocks = <&byteclock>, <&byteclock> - <&coreclock>, <&coreclock>, - <&coreclock>, <&coreclock>; - clock-names = "sys_clk", "p_clk", - "pixel_if0_clk", "pixel_if1_clk", - "pixel_if2_clk", "pixel_if3_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - csi2rx_in_sensor: endpoint { - remote-endpoint = <&sensor_out_csi2rx>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - - csi2rx_out_grabber0: endpoint { - remote-endpoint = <&grabber0_in_csi2rx>; - }; - }; - - port@2 { - reg = <2>; - - csi2rx_out_grabber1: endpoint { - remote-endpoint = <&grabber1_in_csi2rx>; - }; - }; - - port@3 { - reg = <3>; - - csi2rx_out_grabber2: endpoint { - remote-endpoint = <&grabber2_in_csi2rx>; - }; - }; - - port@4 { - reg = <4>; - - csi2rx_out_grabber3: endpoint { - remote-endpoint = <&grabber3_in_csi2rx>; - }; - }; - }; -}; Index: linux-6.1.80/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml @@ -0,0 +1,176 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/cdns,csi2rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence MIPI-CSI2 RX controller + +description: | + The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI + lanes in input, and 4 different pixel streams in output. + +maintainers: + - Pratyush Yadav + +properties: + compatible: + contains: + const: cdns,csi2rx + + reg: + maxItems: 1 + + clocks: + minItems: 3 + items: + - description: Main clock + - description: Register bank clock + - description: Pixel stream 0 output clock + - description: Pixel stream 1 output clock + - description: Pixel stream 2 output clock + - description: Pixel stream 3 output clock + + clock-names: + minItems: 3 + items: + - const: sys_clk + - const: p_clk + - const: pixel_if0_clk + - const: pixel_if1_clk + - const: pixel_if2_clk + - const: pixel_if3_clk + + phys: + maxItems: 1 + description: phandle to the external D-PHY + + phy-names: + items: + - const: dphy + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI-2 input + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + items: + maximum: 4 + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 0 output + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 1 output + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 2 output + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 3 output + + required: + - port@0 + + +dependencies: + phys: [ 'phy-names' ] + phy-names: [ 'phys' ] + +required: + - compatible + - reg + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + csi2rx: csi-bridge@d060000 { + compatible = "cdns,csi2rx"; + reg = <0x0d060000 0x1000>; + clocks = <&byteclock>, <&byteclock>, + <&coreclock>, <&coreclock>, + <&coreclock>, <&coreclock>; + clock-names = "sys_clk", "p_clk", + "pixel_if0_clk", "pixel_if1_clk", + "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi2rx_in_sensor: endpoint { + remote-endpoint = <&sensor_out_csi2rx>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + + csi2rx_out_grabber0: endpoint { + remote-endpoint = <&grabber0_in_csi2rx>; + }; + }; + + port@2 { + reg = <2>; + + csi2rx_out_grabber1: endpoint { + remote-endpoint = <&grabber1_in_csi2rx>; + }; + }; + + port@3 { + reg = <3>; + + csi2rx_out_grabber2: endpoint { + remote-endpoint = <&grabber2_in_csi2rx>; + }; + }; + + port@4 { + reg = <4>; + + csi2rx_out_grabber3: endpoint { + remote-endpoint = <&grabber3_in_csi2rx>; + }; + }; + }; + }; Index: linux-6.1.80/Documentation/devicetree/bindings/media/cnm,wave5.yml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/media/cnm,wave5.yml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/wave5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Chips&Media Wave 5 Series multi-standard codec IP + +maintainers: + - Nas Chung + - Robert Beckett + - Sebastian Fricke + +description: |- + The Chips&Media WAVE codec IP is a multi format video encoder/decoder + +properties: + compatible: + anyOf: + - items: + - enum: + - cnm,cm511-vpu + - cnm,cm517-vpu + - cnm,cm521-vpu + - cnm,cm521c-vpu + - cnm,cm521c-dual-vpu + - cnm,cm521e1-vpu + - cnm,cm537-vpu + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + sram: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle pointing to the SRAM device node + maxItems: 1 + + sram-size: + description: Amount to allocate from SRAM device node + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + vpu: video-codec@12345678 { + compatible = "cnm,cm521-vpu"; + reg = <0x12345678 0x1000>; + interrupts = <42>; + clocks = <&clks 42>; + clock-names = "vcodec"; + sram = <&sram>; + sram-size = <0x12345>; + }; Index: linux-6.1.80/Documentation/devicetree/bindings/media/i2c/ovti,ov1063x.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/media/i2c/ovti,ov1063x.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov1063x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OmniVision OV10633/OV1035 8/10 bit digital Camera Sensor + +maintainers: + - Benoit Parrot + - Sukrut Bellary + + +description: |- + The OmniVision OV1063x is a 720p(HD) camera sensor which supports resolutions + up to 1280x800(WXGA) and 8/10-bit YUV output formats. + + Each camera nodes should contain a 'port' child node with child + 'endpoint' node. Please refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.yaml. + +properties: + compatible: + enum: + - ovti,ov10633 + - ovti,ov10635 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xvclk + + reset-gpios: + maxItems: 1 + description: + phandle to the GPIO connected to the RESETB pin, if any. + + powerdown-gpios: + maxItems: 1 + description: + phandle for the GPIO connected to the PWDN pin, if any. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + hsync-active: true + vsync-active: true + pclk-sample: true + bus-width: + enum: [ 8, 10 ] + +required: + - compatible + - reg + - clocks + - clock-names + - port + +additionalProperties: false + +examples: + - | + #include + + i2c { + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + camera@30 { + compatible = "ovti,ov10635"; + reg = <0x30>; + + clocks = <&fixed_clock>; + clock-names = "xvclk"; + + reset-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; + + port { + camera1: endpoint { + remote-endpoint = <&vin1a_ep>; + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + bus-width = <8>; + }; + }; + }; + }; + +... Index: linux-6.1.80/Documentation/devicetree/bindings/media/i2c/ovti,ox05b.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/media/i2c/ovti,ox05b.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ox05b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OmniVision OX05B1S Camera Sensor + +maintainers: + - Abhishek Sharma + +description: |- + Omnivision OX05B1S is an RGBIR camera sensor with an active array size of + 2592x1944. It is programmable through the I2C interface. The i2c client + address is fixed at 0x36 as per the sensor datasheet. Every alternate frame, + the sensor changes the exposure/gain registers to stream an - + A. IR-dominant frame on CSI-2 virtual channel 0 + B. RGB-dominant frame on CSI-2 virtual channel 1 + + Both streams are captured at a resolution 2592x1944, 30 fps each + (60 fps total). The sensor also supports a few v4l2 controls like + exposure and gain controls. + +properties: + compatible: + enum: + - ovti,ox05b + + reg: + description: I2C address + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: inck + + pwdn-gpios: + maxItems: 1 + description: + Specifier for the GPIO connected to the PWDN pin. + + port: + $ref: /schemas/graph.yaml#/properties/port + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - port + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ox05b1s: camera@36 { + compatible = "ovti,ox05b"; + reg = <0x36>; + + clocks = <&clk_ox05b1s_fixed>; + clock-names = "inck"; + + pwdn-gpios = <&exp1 13 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + }; + }; + }; + }; + +... Index: linux-6.1.80/Documentation/devicetree/bindings/media/i2c/sony,imx390.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/media/i2c/sony,imx390.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/sony,imx390.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony IMX390 Camera Sensor + +maintainers: + - Tomi Valkeinen + +description: |- + Sony IMX390 camera sensor. + +properties: + compatible: + enum: + - sony,imx390 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: inck + + xclr-gpios: + maxItems: 1 + description: + Specifier for the GPIO connected to the XCLR (System Reset) pin. + + port: + $ref: /schemas/graph.yaml#/properties/port + additionalProperties: false + + properties: + endpoint: + $ref: ../video-interfaces.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - port + +additionalProperties: false + +examples: + - | + #include + + i2c { + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + camera@21 { + compatible = "sony,imx390"; + reg = <0x21>; + + clocks = <&fixed_clock>; + clock-names = "inck"; + + xclr-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + + port { + camera1: endpoint { + remote-endpoint = <&vin1a_ep>; + }; + }; + }; + }; + +... Index: linux-6.1.80/Documentation/devicetree/bindings/media/i2c/ti,ds90ub913.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/media/i2c/ti,ds90ub913.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ti,ds90ub913.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DS90UB913 FPD-Link III Serializer + +maintainers: + - Tomi Valkeinen + +description: + The TI DS90UB913 is an FPD-Link III video serializer for parallel video. + +properties: + compatible: + enum: + - ti,ds90ub913a-q1 + + '#gpio-cells': + const: 2 + description: + First cell is the GPO pin number, second cell is the flags. The GPO pin + number must be in range of [0, 3]. Note that GPOs 2 and 3 are not + available in external oscillator mode. + + gpio-controller: true + + clocks: + maxItems: 1 + description: + Reference clock connected to the CLKIN pin. + + clock-names: + items: + - const: clkin + + '#clock-cells': + const: 0 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Parallel input port + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + required: + - pclk-sample + + port@1: + $ref: /schemas/graph.yaml#/properties/port + unevaluatedProperties: false + description: FPD-Link III output port + + required: + - port@0 + - port@1 + + i2c: + $ref: /schemas/i2c/i2c-controller.yaml# + unevaluatedProperties: false + +required: + - compatible + - '#gpio-cells' + - gpio-controller + - '#clock-cells' + - ports + +additionalProperties: false + +examples: + - | + #include + + serializer { + compatible = "ti,ds90ub913a-q1"; + + gpio-controller; + #gpio-cells = <2>; + + clocks = <&clk_cam_48M>; + clock-names = "clkin"; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub913_in: endpoint { + remote-endpoint = <&sensor_out>; + pclk-sample = <1>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&deser_fpd_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@48 { + compatible = "aptina,mt9v111"; + reg = <0x48>; + + clocks = <&fixed_clock>; + + port { + sensor_out: endpoint { + remote-endpoint = <&ub913_in>; + }; + }; + }; + }; + }; +... Index: linux-6.1.80/Documentation/devicetree/bindings/media/i2c/ti,ds90ub953.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/media/i2c/ti,ds90ub953.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ti,ds90ub953.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DS90UB953 FPD-Link III Serializer + +maintainers: + - Tomi Valkeinen + +description: + The TI DS90UB953 is an FPD-Link III video serializer for MIPI CSI-2. + +properties: + compatible: + enum: + - ti,ds90ub953-q1 + - ti,ds90ub971-q1 + + '#gpio-cells': + const: 2 + description: + First cell is the GPIO pin number, second cell is the flags. The GPIO pin + number must be in range of [0, 3]. + + gpio-controller: true + + clocks: + maxItems: 1 + description: + Reference clock connected to the CLKIN pin. + + clock-names: + items: + - const: clkin + + '#clock-cells': + const: 0 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI-2 input port + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + unevaluatedProperties: false + description: FPD-Link III output port + + required: + - port@0 + - port@1 + + i2c: + $ref: /schemas/i2c/i2c-controller.yaml# + unevaluatedProperties: false + +required: + - compatible + - '#gpio-cells' + - gpio-controller + - '#clock-cells' + - ports + +additionalProperties: false + +examples: + - | + #include + + serializer { + compatible = "ti,ds90ub953-q1"; + + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_out>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&deser_fpd_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx274"; + reg = <0x1a>; + + reset-gpios = <&serializer 0 GPIO_ACTIVE_LOW>; + + clocks = <&serializer>; + clock-names = "inck"; + + port { + sensor_out: endpoint { + remote-endpoint = <&ub953_in>; + }; + }; + }; + }; + }; +... Index: linux-6.1.80/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml @@ -0,0 +1,428 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ti,ds90ub960.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DS90UB9XX Family FPD-Link Deserializer Hubs + +maintainers: + - Tomi Valkeinen + +description: + The TI DS90UB9XX devices are FPD-Link video deserializers with I2C and GPIO + forwarding. + +allOf: + - $ref: /schemas/i2c/i2c-atr.yaml# + +properties: + compatible: + enum: + - ti,ds90ub954-q1 + - ti,ds90ub960-q1 + - ti,ds90ub9702-q1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: + Reference clock connected to the REFCLK pin. + + clock-names: + items: + - const: refclk + + powerdown-gpios: + maxItems: 1 + description: + Specifier for the GPIO connected to the PDB pin. + + i2c-alias-pool: + minItems: 1 + maxItems: 32 + + links: + type: object + additionalProperties: false + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + ti,manual-strobe: + type: boolean + description: + Enable manual strobe position and EQ level + + patternProperties: + '^link@[0-3]$': + type: object + additionalProperties: false + properties: + reg: + description: The link number + maxItems: 1 + + i2c-alias: + description: + The I2C address used for the serializer. Transactions to this + address on the I2C bus where the deserializer resides are + forwarded to the serializer. + + ti,rx-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # RAW10 + - 1 # RAW12 HF + - 2 # RAW12 LF + - 3 # CSI2 SYNC + - 4 # CSI2 NON-SYNC + description: + FPD-Link Input Mode. This should reflect the hardware and the + default mode of the connected device. + + ti,cdr-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # FPD-Link III + - 1 # FPD-Link IV + description: + FPD-Link CDR Mode. This should reflect the hardware and the + default mode of the connected device. + + ti,strobe-pos: + $ref: /schemas/types.yaml#/definitions/int32 + minimum: -13 + maximum: 13 + description: Manual strobe position + + ti,eq-level: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 14 + description: Manual EQ level + + serializer: + type: object + description: FPD-Link Serializer node + + required: + - reg + - i2c-alias + - ti,rx-mode + - serializer + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: FPD-Link input 0 + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + description: + Endpoint for FPD-Link port. If the RX mode for this port is RAW, + hsync-active and vsync-active must be defined. + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: FPD-Link input 1 + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + description: + Endpoint for FPD-Link port. If the RX mode for this port is RAW, + hsync-active and vsync-active must be defined. + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: FPD-Link input 2 + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + description: + Endpoint for FPD-Link port. If the RX mode for this port is RAW, + hsync-active and vsync-active must be defined. + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: FPD-Link input 3 + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + description: + Endpoint for FPD-Link port. If the RX mode for this port is RAW, + hsync-active and vsync-active must be defined. + + port@4: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI-2 Output 0 + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + link-frequencies: + maxItems: 1 + + required: + - data-lanes + - link-frequencies + + port@5: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI-2 Output 1 + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + link-frequencies: + maxItems: 1 + + required: + - data-lanes + - link-frequencies + + required: + - port@0 + - port@1 + - port@2 + - port@3 + - port@4 + - port@5 + +required: + - compatible + - reg + - clocks + - clock-names + - ports + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + deser@3d { + compatible = "ti,ds90ub960-q1"; + reg = <0x3d>; + + clock-names = "refclk"; + clocks = <&fixed_clock>; + + powerdown-gpios = <&pca9555 7 GPIO_ACTIVE_LOW>; + + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* Port 0, Camera 0 */ + port@0 { + reg = <0>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; + + /* Port 1, Camera 1 */ + port@1 { + reg = <1>; + + ub960_fpd3_2_in: endpoint { + remote-endpoint = <&ub913_2_out>; + hsync-active = <0>; + vsync-active = <1>; + }; + }; + + /* Port 2, unconnected */ + port@2 { + reg = <2>; + }; + + /* Port 3, unconnected */ + port@3 { + reg = <3>; + }; + + /* Port 4, CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + + /* Port 5, unconnected */ + port@5 { + reg = <5>; + }; + }; + + links { + #address-cells = <1>; + #size-cells = <0>; + + /* Link 0 has DS90UB953 serializer and IMX274 sensor */ + + link@0 { + reg = <0>; + i2c-alias = <0x44>; + + ti,rx-mode = <3>; + + serializer1: serializer { + compatible = "ti,ds90ub953-q1"; + + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx274"; + reg = <0x1a>; + + reset-gpios = <&serializer1 0 GPIO_ACTIVE_LOW>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; /* End of link@0 */ + + /* Link 1 has DS90UB913 serializer and MT9V111 sensor */ + + link@1 { + reg = <1>; + i2c-alias = <0x45>; + + ti,rx-mode = <0>; + + serializer2: serializer { + compatible = "ti,ds90ub913a-q1"; + + gpio-controller; + #gpio-cells = <2>; + + clocks = <&clk_cam_48M>; + clock-names = "clkin"; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub913_2_in: endpoint { + remote-endpoint = <&sensor_2_out>; + pclk-sample = <1>; + }; + }; + + port@1 { + reg = <1>; + + ub913_2_out: endpoint { + remote-endpoint = <&ub960_fpd3_2_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@48 { + compatible = "aptina,mt9v111"; + reg = <0x48>; + + clocks = <&serializer2>; + + port { + sensor_2_out: endpoint { + remote-endpoint = <&ub913_2_in>; + }; + }; + }; + }; + }; + }; /* End of link@1 */ + }; + }; + }; +... Index: linux-6.1.80/Documentation/devicetree/bindings/media/img,d5500-vxd.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/media/img,d5500-vxd.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/img,d5500-vxd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagination D5520-VXD Driver + +maintainers: + - Sidraya Jayagond + - Prashanth Kumar Amai + +description: | + The IMG VXD video decode driver for the D5500-VXD is a video decoder for + multiple video formats including H.264 and HEVC on the TI J721E family + of SoCs. + +properties: + compatible: + const: img,d5500-vxd + + reg: + maxItems: 2 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + d5520: video-decoder@4300000 { + /* IMG D5520 driver configuration */ + compatible = "img,d5500-vxd"; + reg = <0x00 0x04300000>, + <0x00 0x100000>; + power-domains = <&k3_pds 144>; + interrupts = ; + }; + +... Index: linux-6.1.80/Documentation/devicetree/bindings/media/img,e5010-jpeg-enc.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/media/img,e5010-jpeg-enc.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/img,e5010-jpeg-enc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagination E5010 JPEG Encoder + +maintainers: + - Devarsh Thakkar + +description: | + The E5010 is a JPEG encoder from Imagination Technologies implemented on + TI's AM62A SoC. It is capable of real time encoding of YUV420 and YUV422 + inputs to JPEG and M-JPEG. It supports baseline JPEG Encoding up to + 8Kx8K resolution. + +properties: + compatible: + const: img,e5010-jpeg-enc + + reg: + items: + - description: The E5010 main register region + - description: The E5010 mmu register region + + reg-names: + items: + - const: regjasper + - const: regmmu + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + + e5010: e5010@fd20000 { + compatible = "img,e5010-jpeg-enc"; + reg = <0x00 0xfd20000 0x00 0x100>, + <0x00 0xfd20200 0x00 0x200>; + reg-names = "regjasper", "regmmu"; + clocks = <&k3_clks 201 0>; + clock-names = "core_clk"; + power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; + interrupts = ; + }; Index: linux-6.1.80/Documentation/devicetree/bindings/media/img,vxe384.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/media/img,vxe384.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/img,vxe384.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Imagination VXE384 Driver + +maintainers: + - Sidraya Jayagond + +description: | + The IMG VXE384 video encode driver for the VXE384 is a video encoder for + multiple video formats including H.264 on the TI J721E family of SoCs. + +properties: + compatible: + const: img,vxe384 + + reg: + maxItems: 2 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + vxe384: video-encoder@4200000 { + compatible = "img,vxe384"; + reg = <0x00 0x04200000>, + <0x00 0x100000>; + power-domains = <&k3_pds 153>; + interrupts = ; + }; Index: linux-6.1.80/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/ti,j721e-csi2rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI J721E CSI2RX Wrapper + +description: | + The TI J721E CSI2RX Wrapper is a wrapper around Cadence CSI2RX bridge that + enables sending captured frames to memory over PSI-L DMA. In the J721E + Technical Reference Manual (SPRUIL1B) it is referred to as "SHIM" under the + CSI_RX_IF section. + +maintainers: + - Vaishnav Achath + +properties: + compatible: + - const: ti,j721e-csi2rx + + dmas: + maxItems: 1 + + dma-names: + items: + - const: rx0 + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + ranges: true + + "#address-cells": true + + "#size-cells": true + +patternProperties: + "^csi-bridge@": + type: object + description: CSI2 bridge node. + $ref: cdns,csi2rx.yaml# + +required: + - compatible + - reg + - dmas + - dma-names + - power-domains + - ranges + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx"; + dmas = <&main_udmap 0x4940>; + dma-names = "rx0"; + reg = <0x4500000 0x1000>; + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cdns_csi2rx: csi-bridge@4504000 { + compatible = "cdns,csi2rx"; + reg = <0x4504000 0x1000>; + clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + + reg = <0>; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; Index: linux-6.1.80/Documentation/devicetree/bindings/media/ti,vip.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/media/ti,vip.yaml @@ -0,0 +1,312 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/ti,vip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DRA7x VIDEO INPUT PORT (VIP). + +maintainers: + - Benoit Parrot + +description: |- + The Video Input Port (VIP) is a key component for image capture + applications. The capture module provides the system interface and the + processing capability to connect parallel image-sensor as well as + BT.656/1120 capable encoder chip to DRA7x device. + + Each VIP instance supports 2 independently configurable external video + input capture slices (Slice 0 and Slice 1) each providing up to two video + input ports (Port A and Port B) where Port A can be configured as + 24/16/8-bit port and Port B is fixed as 8-bit port. + Here these ports a represented as follows + port@0 -> Slice 0 Port A + port@1 -> Slice 0 Port B + port@2 -> Slice 1 Port A + port@3 -> Slice 1 Port B + + Each camera port nodes should contain a 'port' child node with child + 'endpoint' node. Please refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.yaml. + +properties: + compatible: + enum: + - ti,dra7-vip1 + - ti,dra7-vip2 + - ti,dra7-vip3 + + label: + description: Instance name + + reg: + items: + - description: The VIP main register region + - description: Video Data Parser (PARSER) register region for Slice0 + - description: Color Space Conversion (CSC) register region for Slice0 + - description: Scaler (SC) register region for Slice0 + - description: Video Data Parser (PARSER) register region for Slice1 + - description: Color Space Conversion (CSC) register region for Slice1 + - description: Scaler (SC) register region for Slice1 + - description: Video Port Direct Memory Access (VPDMA) register region + + reg-names: + items: + - const: vip + - const: parser0 + - const: csc0 + - const: sc0 + - const: parser1 + - const: csc1 + - const: sc1 + - const: vpdma + + interrupts: + minItems: 2 + description: + IRQ index 0 is used for Slice0 interrupts + IRQ index 1 is used for Slice1 interrupts + + ti,vip-clk-polarity: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + phandle to the device control module. The 1st argument should + contain the register offset to the CTRL_CORE_SMA_SW_1 register. + 2nd argument contains the bit field to slice 0 port A, + 3rd argument contains the bit field to slice 0 port B, + 4th argument contains the bit field to slice 1 port A, + 5th argument contains the bit field to slice 1 port B. + + ports: + type: object + additionalProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + additionalProperties: false + + properties: + reg: + const: 0 + description: Slice 0 Port A + + label: + description: Port name. Usually the pin group name + + endpoint: + $ref: video-interfaces.yaml# + type: object + unevaluatedProperties: false + + properties: + hsync-active: true + vsync-active: true + pclk-sample: true + bus-width: + enum: [8, 24] + default: 8 + + remote-endpoint: true + + required: + - reg + - label + + port@1: + type: object + additionalProperties: false + + properties: + reg: + const: 1 + description: Slice 0 Port B + + label: + description: Port name. Usually the pin group name + + endpoint: + $ref: /schemas/graph.yaml#/properties/endpoint + type: object + additionalProperties: false + + properties: + hsync-active: true + vsync-active: true + pclk-sample: true + bus-width: + enum: [8, 24] + default: 8 + + remote-endpoint: true + + required: + - reg + - label + + port@2: + type: object + additionalProperties: false + + properties: + reg: + const: 2 + description: Slice 1 Port A + + label: + description: Port name. Usually the pin group name + + endpoint: + $ref: /schemas/graph.yaml#/properties/endpoint + type: object + additionalProperties: false + + properties: + hsync-active: true + vsync-active: true + pclk-sample: true + bus-width: + enum: [8, 24] + default: 8 + + remote-endpoint: true + + required: + - reg + - label + + port@3: + type: object + additionalProperties: false + + properties: + reg: + const: 3 + description: Slice 1 Port B + + label: + description: Port name. Usually the pin group name + + endpoint: + $ref: /schemas/graph.yaml#/properties/endpoint + type: object + additionalProperties: false + + properties: + hsync-active: true + vsync-active: true + pclk-sample: true + bus-width: + enum: [8, 24] + default: 8 + + remote-endpoint: true + + required: + - reg + - label + + required: + - "#address-cells" + - "#size-cells" + - port@0 + +required: + - compatible + - label + - reg + - reg-names + - interrupts + - ti,vip-clk-polarity + +additionalProperties: false + +examples: + - | + #include + + vip1: vip@48970000 { + compatible = "ti,dra7-vip1"; + label = "vip1"; + reg = <0x48970000 0x114>, + <0x48975500 0xD8>, + <0x48975700 0x18>, + <0x48975800 0x80>, + <0x48975a00 0xD8>, + <0x48975c00 0x18>, + <0x48975d00 0x80>, + <0x4897d000 0x400>; + reg-names = "vip", + "parser0", + "csc0", + "sc0", + "parser1", + "csc1", + "sc1", + "vpdma"; + interrupts = , + ; + ti,vip-clk-polarity = <&scm_conf 0x534 0x1 0x4 0x2 0x8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + vin1a: port@0 { + reg = <0>; + label = "vin1a"; + + vin1a_ep: endpoint { + remote-endpoint = <&camera1>; + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + bus-width = <8>; + }; + }; + vin1b: port@1 { + reg = <1>; + label = "vin1b"; + }; + vin2a: port@2 { + reg = <2>; + label = "vin2a"; + }; + vin2b: port@3 { + reg = <3>; + label = "vin2b"; + }; + }; + }; + + i2c { + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + camera@37 { + compatible = "ovti,ov10633"; + reg = <0x37>; + + clocks = <&fixed_clock>; + clocks-names = "xvclk"; + + port { + camera1: endpoint { + remote-endpoint = <&vin1a_ep>; + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + bus-width = <8>; + }; + }; + }; + }; + +... Index: linux-6.1.80/Documentation/devicetree/bindings/media/video-interfaces.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/media/video-interfaces.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/media/video-interfaces.yaml @@ -159,6 +159,7 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 maxItems: 8 + uniqueItems: true items: # Assume up to 9 physical lane indices maximum: 8 Index: linux-6.1.80/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/ti,tps6594.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI TPS6594 Power Management Integrated Circuit + +maintainers: + - Julien Panis + +description: + TPS6594 is a Power Management IC which provides regulators and others + features like GPIOs, RTC, watchdog, ESMs (Error Signal Monitor), and + PFSM (Pre-configurable Finite State Machine) managing the state of the device. + TPS6594 is the super-set device while TPS6593 and LP8764 are derivatives. + +properties: + compatible: + enum: + - ti,lp8764-q1 + - ti,tps6593-q1 + - ti,tps6594-q1 + + reg: + description: I2C slave address or SPI chip select number. + maxItems: 1 + + ti,primary-pmic: + type: boolean + description: | + Identify the primary PMIC on SPMI bus. + A multi-PMIC synchronization scheme is implemented in the PMIC device + to synchronize the power state changes with other PMIC devices. This is + accomplished through a SPMI bus: the primary PMIC is the controller + device on the SPMI bus, and the secondary PMICs are the target devices + on the SPMI bus. + + system-power-controller: true + + gpio-controller: true + + '#gpio-cells': + const: 2 + description: | + The first cell is the pin number, the second cell is used to specify flags. + See ../gpio/gpio.txt for more information. + + interrupts: + maxItems: 1 + + regulators: + type: object + description: List of regulators provided by this controller. + + patternProperties: + "^buck([1-5]|12|34|123|1234)$": + type: object + $ref: /schemas/regulator/regulator.yaml# + + unevaluatedProperties: false + + "^ldo[1-4]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + + unevaluatedProperties: false + + allOf: + - if: + required: + - buck12 + then: + properties: + buck123: false + buck1234: false + - if: + required: + - buck123 + then: + properties: + buck34: false + - if: + required: + - buck1234 + then: + properties: + buck34: false + + additionalProperties: false + +patternProperties: + "^buck([1-5]|12|34|123|1234)-supply$": + description: Input supply phandle for each buck. + + "^ldo[1-4]-supply$": + description: Input supply phandle for each ldo. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + tps6593: pmic@48 { + compatible = "ti,tps6593-q1"; + reg = <0x48>; + ti,primary-pmic; + system-power-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&mcu_gpio0>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + buck123-supply = <&vcc_3v3_sys>; + buck4-supply = <&vcc_3v3_sys>; + buck5-supply = <&vcc_3v3_sys>; + ldo1-supply = <&vcc_3v3_sys>; + ldo2-supply = <&vcc_3v3_sys>; + ldo3-supply = <&buck5>; + ldo4-supply = <&vcc_3v3_sys>; + + regulators { + buck123: buck123 { + regulator-name = "vcc_core"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: buck4 { + regulator-name = "vcc_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: buck5 { + regulator-name = "vcc_1v8_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: ldo1 { + regulator-name = "vddshv5_sdio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: ldo2 { + regulator-name = "vpp_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: ldo3 { + regulator-name = "vcc_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: ldo4 { + regulator-name = "vdda_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + }; Index: linux-6.1.80/Documentation/devicetree/bindings/misc/ti,dma-buf-phys.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/misc/ti,dma-buf-phys.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/ti,dma-buf-phys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DMA-BUF contiguous buffer physical address user-space exporter binding + +description: | + Driver allowing user-space attaching of DMA-BUFs returning CPU physical + addresses. The reasoning for making this act like a regular device + described by DT is so the virtual device that binds the buffer can be + made to act as if it is out on a bus or behind an IOMMU, for example. + +maintainers: + - Andrew Davis + +properties: + compatible: + const: ti,dma-buf-phys + + iommus: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + +additionalProperties: false + +examples: + - | + dma-buf-phys { + compatible = "ti,dma-buf-phys"; + iommus = <&some_iommu>; + dma-coherent; + }; Index: linux-6.1.80/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -118,12 +118,14 @@ properties: phys: maxItems: 1 + wakeup-source: + $ref: /schemas/types.yaml#/definitions/flag + description: This device is capable to wakeup the SoC. + required: - compatible - reg - reg-names - - interrupts - - interrupt-names - clocks - clock-names - bosch,mram-cfg @@ -132,6 +134,7 @@ additionalProperties: false examples: - | + // Example with interrupts #include can@20e8000 { compatible = "bosch,m_can"; @@ -142,6 +145,23 @@ examples: clocks = <&clks IMX6SX_CLK_CANFD>, <&clks IMX6SX_CLK_CANFD>; clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>; + + can-transceiver { + max-bitrate = <5000000>; + }; + }; + + - | + // Example with timer polling + #include + can@20e8000 { + compatible = "bosch,m_can"; + reg = <0x020e8000 0x4000>, <0x02298000 0x4000>; + reg-names = "m_can", "message_ram"; + clocks = <&clks IMX6SX_CLK_CANFD>, + <&clks IMX6SX_CLK_CANFD>; + clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>; can-transceiver { Index: linux-6.1.80/Documentation/devicetree/bindings/net/ti,cpsw-virt-mac.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/net/ti,cpsw-virt-mac.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,cpsw-virt-mac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI J721E VIRT CPSWxg Ethernet mac + +maintainers: + - Siddharth Vadapalli + +description: | + This document defines the bindings for the Virtual Mac thin client Linux + driver that utilizes Remoteproc Framework to communicate and exchange + network data with the EthSwitch Firmware running on the R-Core. + +properties: + compatible: + const: ti,j721e-cpsw-virt-mac + + dma-coherent: true + + dmas: + maxItems: 9 + + dma-names: + items: + - const: tx0 + - const: tx1 + - const: tx2 + - const: tx3 + - const: tx4 + - const: tx5 + - const: tx6 + - const: tx7 + - const: rx + + ti,psil-base: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + CPSWxg NUSS PSI-L endpoint thread ID base of the UDMA-P + channels. The PSI-L endpoint node thread configuration + subnodes must be present with ti,psil-configX naming + convention, where X is the thread ID offset. + + ti,remote-name: + $ref: /schemas/types.yaml#/definitions/string + description: | + Name of the connected rpmsg-kdrv device represented + by Eth switch FW running on one of the R5F cores. + items: + - enum: + - mpu_1_0_ethswitch-device-0 + - mpu_1_0_ethmac-device-1 + + virt-emac-port: + type: object + properties: + + ti,label: + $ref: /schemas/types.yaml#/definitions/string + description: | + Describes the label associated with this port. + items: + - const: virt-port + + local-mac-address: true + +required: + - compatible + - dmas + - dma-names + - ti,psil-base + - ti,remote-name + - virt-emac-port + +additionalProperties: false + +examples: + - | + cpsw9g_virt_mac: main-r5fss-cpsw9g-virt-mac0 { + compatible = "ti,j721e-cpsw-virt-mac"; + dma-coherent; + ti,psil-base = <0x4a00>; + ti,remote-name = "mpu_1_0_ethswitch-device-0"; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + virt-emac-port { + ti,label = "virt-port"; + /* local-mac-address = [0 0 0 0 0 0]; */ + }; + }; Index: linux-6.1.80/Documentation/devicetree/bindings/net/ti,icss-iep.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/net/ti,icss-iep.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,icss-iep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments ICSS Industrial Ethernet Peripheral (IEP) module + +maintainers: + - Lokesh Vutla + +properties: + compatible: + enum: + - ti,am654-icss-iep # for K3 AM65x, J721E and AM64x SoCs + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: phandle to the IEP source clock + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + icssg0_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; Index: linux-6.1.80/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,icssg-prueth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments ICSSG PRUSS Ethernet + +maintainers: + - Md Danish Anwar + +description: + Ethernet based on the Programmable Real-Time Unit and Industrial + Communication Subsystem. + +allOf: + - $ref: /schemas/remoteproc/ti,pru-consumer.yaml# + +properties: + compatible: + enum: + - ti,am654-icssg-prueth # for AM65x SoC family + - ti,am642-icssg-prueth # for AM64x SoC family + + sram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to MSMC SRAM node + + dmas: + maxItems: 10 + + dma-names: + items: + - const: tx0-0 + - const: tx0-1 + - const: tx0-2 + - const: tx0-3 + - const: tx1-0 + - const: tx1-1 + - const: tx1-2 + - const: tx1-3 + - const: rx0 + - const: rx1 + + ti,mii-g-rt: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to MII_G_RT module's syscon regmap. + + ti,mii-rt: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to MII_RT module's syscon regmap + + ti,pa-stats: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to PA_STATS module's syscon regmap + + interrupts: + maxItems: 2 + description: + Interrupt specifiers to TX timestamp IRQ. + + interrupt-names: + items: + - const: tx_ts0 + - const: tx_ts1 + + ethernet-ports: + type: object + additionalProperties: false + + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + ^port@[0-1]$: + type: object + description: ICSSG PRUETH external ports + $ref: ethernet-controller.yaml# + unevaluatedProperties: false + + properties: + reg: + items: + - enum: [0, 1] + description: ICSSG PRUETH port number + + interrupts: + maxItems: 1 + + ti,syscon-rgmii-delay: + items: + - items: + - description: phandle to system controller node + - description: The offset to ICSSG control register + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + phandle to system controller node and register offset + to ICSSG control register for RGMII transmit delay + + ti,half-duplex-capable: + description: + Enable half duplex operation on ICSSG MII port. This requires + PHY output pin (COL) to be routed to ICSSG GPIO pin + (PRGx_PRU0/1_GPIO10) as input. + + required: + - reg + anyOf: + - required: + - port@0 + - required: + - port@1 + +required: + - compatible + - sram + - dmas + - dma-names + - ethernet-ports + - ti,mii-g-rt + - ti,pa-stats + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + /* Example k3-am654 base board SR2.0, dual-emac */ + pruss2_eth: ethernet { + compatible = "ti,am654-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg2_rgmii_pins_default>; + sram = <&msmc_ram>; + + ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>, + <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>; + firmware-name = "ti-pruss/am65x-pru0-prueth-fw.elf", + "ti-pruss/am65x-rtu0-prueth-fw.elf", + "ti-pruss/am65x-txpru0-prueth-fw.elf", + "ti-pruss/am65x-pru1-prueth-fw.elf", + "ti-pruss/am65x-rtu1-prueth-fw.elf", + "ti-pruss/am65x-txpru1-prueth-fw.elf"; + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + dmas = <&main_udmap 0xc300>, /* egress slice 0 */ + <&main_udmap 0xc301>, /* egress slice 0 */ + <&main_udmap 0xc302>, /* egress slice 0 */ + <&main_udmap 0xc303>, /* egress slice 0 */ + <&main_udmap 0xc304>, /* egress slice 1 */ + <&main_udmap 0xc305>, /* egress slice 1 */ + <&main_udmap 0xc306>, /* egress slice 1 */ + <&main_udmap 0xc307>, /* egress slice 1 */ + <&main_udmap 0x4300>, /* ingress slice 0 */ + <&main_udmap 0x4301>; /* ingress slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + ti,mii-g-rt = <&icssg2_mii_g_rt>; + ti,pa-stats = <&icssg2_pa_stats>; + interrupt-parent = <&icssg2_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss2_emac0: port@0 { + reg = <0>; + phy-handle = <&pruss2_eth0_phy>; + phy-mode = "rgmii-id"; + interrupts-extended = <&icssg2_intc 24>; + ti,syscon-rgmii-delay = <&scm_conf 0x4120>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss2_emac1: port@1 { + reg = <1>; + phy-handle = <&pruss2_eth1_phy>; + phy-mode = "rgmii-id"; + interrupts-extended = <&icssg2_intc 25>; + ti,syscon-rgmii-delay = <&scm_conf 0x4124>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; Index: linux-6.1.80/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml @@ -54,10 +54,12 @@ properties: compatible: enum: + - ti,am642-cpsw-nuss - ti,am654-cpsw-nuss - ti,j7200-cpswxg-nuss - ti,j721e-cpsw-nuss - - ti,am642-cpsw-nuss + - ti,j721e-cpswxg-nuss + - ti,j784s4-cpswxg-nuss reg: maxItems: 1 @@ -111,7 +113,7 @@ properties: const: 0 patternProperties: - "^port@[1-4]$": + "^port@[1-8]$": type: object description: CPSWxG NUSS external ports @@ -121,12 +123,22 @@ properties: properties: reg: minimum: 1 - maximum: 4 + maximum: 8 description: CPSW port number phys: - maxItems: 1 - description: phandle on phy-gmii-sel PHY + minItems: 1 + items: + - description: CPSW MAC's PHY. + - description: Serdes PHY. Serdes PHY is required only if + the Serdes has to be configured in the + Single-Link configuration. + + phy-names: + minItems: 1 + items: + - const: mac + - const: serdes label: description: label associated with this port @@ -186,18 +198,44 @@ allOf: properties: compatible: contains: - const: ti,j7200-cpswxg-nuss + enum: + - ti,j721e-cpswxg-nuss + - ti,j784s4-cpswxg-nuss + then: + properties: + ethernet-ports: + patternProperties: + "^port@[5-8]$": false + "^port@[1-4]$": + properties: + reg: + minimum: 1 + maximum: 4 + + - if: + not: + properties: + compatible: + contains: + enum: + - ti,j7200-cpswxg-nuss + - ti,j721e-cpswxg-nuss + - ti,j784s4-cpswxg-nuss then: properties: ethernet-ports: patternProperties: - "^port@[3-4]$": false + "^port@[3-8]$": false + "^port@[1-2]$": + properties: + reg: + minimum: 1 + maximum: 2 additionalProperties: false examples: - | - #include #include #include #include Index: linux-6.1.80/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml @@ -93,6 +93,14 @@ properties: description: Number of timestamp Generator function outputs (TS_GENFx) + ti,pps: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + description: | + The pair of HWx_TS_PUSH input and TS_GENFy output indexes used for + PPS events generation. Platform/board specific. + refclk-mux: type: object additionalProperties: false Index: linux-6.1.80/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml @@ -49,28 +49,40 @@ required: - reg - reg-names - max-link-speed + - num-lanes - power-domains - ti,syscon-pcie-mode + - phys + - phy-names - dma-coherent unevaluatedProperties: false examples: - | + #include + #include #include #include - #include - pcie0_ep: pcie-ep@5500000 { - compatible = "ti,am654-pcie-ep"; - reg = <0x5500000 0x1000>, - <0x5501000 0x1000>, - <0x10000000 0x8000000>, - <0x5506000 0x1000>; - reg-names = "app", "dbics", "addr_space", "atu"; - power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&scm_conf 0x4060>; - max-link-speed = <2>; - dma-coherent; - interrupts = ; + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie0_ep: pcie-ep@5500000 { + compatible = "ti,am654-pcie-ep"; + reg = <0x0 0x5500000 0x0 0x1000>, + <0x0 0x5501000 0x0 0x1000>, + <0x0 0x10000000 0x0 0x8000000>, + <0x0 0x5506000 0x0 0x1000>; + reg-names = "app", "dbics", "addr_space", "atu"; + power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + ti,syscon-pcie-mode = <&pcie0_mode>; + num-ib-windows = <16>; + num-ob-windows = <16>; + max-link-speed = <2>; + dma-coherent; + interrupts = ; + }; }; Index: linux-6.1.80/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml @@ -55,13 +55,25 @@ properties: dma-coherent: true +patternProperties: + "interrupt-controller": + type: object + description: interrupt controller to handle legacy interrupts. + required: - compatible - reg - reg-names - max-link-speed + - num-lanes + - power-domains + - reset-gpios + - phys + - phy-names + - dma-coherent - ti,syscon-pcie-id - ti,syscon-pcie-mode + - msi-map - ranges if: @@ -82,25 +94,44 @@ examples: #include #include #include + #include - pcie0_rc: pcie@5500000 { - compatible = "ti,am654-pcie-rc"; - reg = <0x5500000 0x1000>, - <0x5501000 0x1000>, - <0x10000000 0x2000>, - <0x5506000 0x1000>; - reg-names = "app", "dbics", "config", "atu"; - power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <3>; + bus { + #address-cells = <2>; #size-cells = <2>; - ranges = <0x81000000 0 0 0x10020000 0 0x00010000>, - <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>; - ti,syscon-pcie-id = <&scm_conf 0x0210>; - ti,syscon-pcie-mode = <&scm_conf 0x4060>; - bus-range = <0x0 0xff>; - max-link-speed = <2>; - dma-coherent; - interrupts = ; - msi-map = <0x0 &gic_its 0x0 0x10000>; - device_type = "pci"; + + pcie0_rc: pcie@5500000 { + compatible = "ti,am654-pcie-rc"; + reg = <0x0 0x5500000 0x0 0x1000>, + <0x0 0x5501000 0x0 0x1000>, + <0x0 0x10000000 0x0 0x2000>, + <0x0 0x5506000 0x0 0x1000>; + reg-names = "app", "dbics", "config", "atu"; + power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>, + <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; + ti,syscon-pcie-id = <&pcie_devid>; + ti,syscon-pcie-mode = <&pcie0_mode>; + bus-range = <0x0 0xff>; + num-viewport = <16>; + max-link-speed = <2>; + dma-coherent; + interrupts = ; + msi-map = <0x0 &gic_its 0x0 0x10000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */ + <0 0 0 2 &pcie0_intc 0>, /* INT B */ + <0 0 0 3 &pcie0_intc 0>, /* INT C */ + <0 0 0 4 &pcie0_intc 0>; /* INT D */ + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; + }; }; Index: linux-6.1.80/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -10,13 +10,11 @@ title: TI J721E PCI EP (PCIe Wrapper) maintainers: - Kishon Vijay Abraham I -allOf: - - $ref: "cdns-pcie-ep.yaml#" - properties: compatible: oneOf: - const: ti,j721e-pcie-ep + - const: ti,j784s4-pcie-ep - description: PCIe EP controller in AM64 items: - const: ti,am64-pcie-ep @@ -58,6 +56,48 @@ properties: dma-coherent: description: Indicates that the PCIe IP block can ensure the coherency + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: link_state + +allOf: + - $ref: cdns-pcie-ep.yaml# + - if: + properties: + compatible: + enum: + - ti,am64-pcie-ep + then: + properties: + num-lanes: + const: 1 + + - if: + properties: + compatible: + enum: + - ti,j7200-pcie-ep + - ti,j721e-pcie-ep + then: + properties: + num-lanes: + minimum: 1 + maximum: 2 + + - if: + properties: + compatible: + enum: + - ti,j784s4-pcie-ep + then: + properties: + num-lanes: + minimum: 1 + maximum: 4 + required: - compatible - reg Index: linux-6.1.80/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -10,13 +10,11 @@ title: TI J721E PCI Host (PCIe Wrapper) maintainers: - Kishon Vijay Abraham I -allOf: - - $ref: "cdns-pcie-host.yaml#" - properties: compatible: oneOf: - const: ti,j721e-pcie-host + - const: ti,j784s4-pcie-host - description: PCIe controller in AM64 items: - const: ti,am64-pcie-host @@ -25,6 +23,10 @@ properties: items: - const: ti,j7200-pcie-host - const: ti,j721e-pcie-host + - description: PCIe controller in J722S + items: + - const: ti,j722s-pcie-host + - const: ti,j721e-pcie-host reg: maxItems: 4 @@ -44,6 +46,18 @@ properties: - description: pcie_ctrl register offset within SYSCON description: Specifier for configuring PCIe mode and link speed. + ti,syscon-pcie-refclk-out: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the SYSCON entry + - description: lock2_kick0 register offset within SYSCON + - description: lock2_kick1 register offset within SYSCON + - description: acspcie_ctrl register offset within SYSCON + - description: pcie_refclk_clksel register offset within SYSCON + - description: clock source index to source ref clock + description: Specifier for enabling ACSPCIe clock buffer for reference clock output. + power-domains: maxItems: 1 @@ -73,14 +87,74 @@ properties: - const: 0xb00f - items: - const: 0xb010 + - items: + - const: 0xb012 + - items: + - const: 0xb013 msi-map: true + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: link_state + + interrupt-controller: + type: object + additionalProperties: false + + properties: + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + +allOf: + - $ref: cdns-pcie-host.yaml# + - if: + properties: + compatible: + enum: + - ti,am64-pcie-host + then: + properties: + num-lanes: + const: 1 + + - if: + properties: + compatible: + enum: + - ti,j7200-pcie-host + - ti,j721e-pcie-host + then: + properties: + num-lanes: + minimum: 1 + maximum: 2 + + - if: + properties: + compatible: + enum: + - ti,j784s4-pcie-host + then: + properties: + num-lanes: + minimum: 1 + maximum: 4 + required: - compatible - reg - reg-names - ti,syscon-pcie-ctrl + - ti,syscon-pcie-refclk-out - max-link-speed - num-lanes - power-domains @@ -101,6 +175,8 @@ examples: - | #include #include + #include + #include bus { #address-cells = <2>; @@ -133,5 +209,75 @@ examples: ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>, <0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; + + }; + }; + + - | + #include + #include + #include + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie1_rc: pcie@2910000 { + compatible = "ti,j784s4-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + ti,syscon-pcie-refclk-out = <&scm_conf 0x9008 0x900c 0x18090 0x8074 0x1>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 333 0>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb013>; + msi-map = <0x0 &gic_its 0x10000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 0>, + <0 0 0 3 &pcie0_intc 0>, + <0 0 0 4 &pcie0_intc 0>; + status = "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; }; }; Index: linux-6.1.80/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml @@ -20,6 +20,7 @@ properties: compatible: enum: - cdns,torrent-phy + - ti,j7200-serdes-10g - ti,j721e-serdes-10g '#address-cells': Index: linux-6.1.80/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml @@ -54,6 +54,8 @@ properties: - ti,dm814-phy-gmii-sel - ti,am654-phy-gmii-sel - ti,j7200-cpsw5g-phy-gmii-sel + - ti,j721e-cpsw9g-phy-gmii-sel + - ti,j784s4-cpsw9g-phy-gmii-sel reg: maxItems: 1 @@ -63,14 +65,17 @@ properties: ti,qsgmii-main-ports: $ref: /schemas/types.yaml#/definitions/uint32-array description: | - Required only for QSGMII mode. Array to select the port for - QSGMII main mode. Rest of the ports are selected as QSGMII_SUB - ports automatically. Any one of the 4 CPSW5G ports can act as the - main port with the rest of them being the QSGMII_SUB ports. - maxItems: 1 + Required only for QSGMII mode. Array to select the port/s for QSGMII + main mode. The size of the array corresponds to the number of QSGMII + interfaces and thus, the number of distinct QSGMII main ports, + supported by the device. If the device supports two QSGMII interfaces + but only one QSGMII interface is desired, repeat the QSGMII main port + value corresponding to the QSGMII interface in the array. + minItems: 1 + maxItems: 2 items: minimum: 1 - maximum: 4 + maximum: 8 allOf: - if: @@ -81,6 +86,9 @@ allOf: - ti,dra7xx-phy-gmii-sel - ti,dm814-phy-gmii-sel - ti,am654-phy-gmii-sel + - ti,j7200-cpsw5g-phy-gmii-sel + - ti,j721e-cpsw9g-phy-gmii-sel + - ti,j784s4-cpsw9g-phy-gmii-sel then: properties: '#phy-cells': @@ -88,12 +96,44 @@ allOf: description: CPSW port number (starting from 1) - if: + properties: + compatible: + contains: + enum: + - ti,j7200-cpsw5g-phy-gmii-sel + then: + properties: + ti,qsgmii-main-ports: + maxItems: 1 + items: + minimum: 1 + maximum: 4 + + - if: + properties: + compatible: + contains: + enum: + - ti,j721e-cpsw9g-phy-gmii-sel + - ti,j784s4-cpsw9g-phy-gmii-sel + then: + properties: + ti,qsgmii-main-ports: + minItems: 2 + maxItems: 2 + items: + minimum: 1 + maximum: 8 + + - if: not: properties: compatible: contains: enum: - ti,j7200-cpsw5g-phy-gmii-sel + - ti,j721e-cpsw9g-phy-gmii-sel + - ti,j784s4-cpsw9g-phy-gmii-sel then: properties: ti,qsgmii-main-ports: false Index: linux-6.1.80/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -15,8 +15,10 @@ properties: enum: - ti,j721e-wiz-16g - ti,j721e-wiz-10g + - ti,j721s2-wiz-10g - ti,am64-wiz-10g - ti,j7200-wiz-10g + - ti,j784s4-wiz-10g power-domains: maxItems: 1 Index: linux-6.1.80/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml @@ -0,0 +1,208 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic Pin Controller with a Single Register for One or More Pins + +maintainers: + - Tony Lindgren + +description: + Some pin controller devices use a single register for one or more pins. The + range of pin control registers can vary from one to many for each controller + instance. Some SoCs from Altera, Broadcom, HiSilicon, Ralink, and TI have this + kind of pin controller instances. + +properties: + compatible: + oneOf: + - enum: + - pinctrl-single + - pinconf-single + - items: + - enum: + - ti,am437-padconf + - ti,am654-padconf + - ti,dra7-padconf + - ti,omap2420-padconf + - ti,omap2430-padconf + - ti,omap3-padconf + - ti,omap4-padconf + - ti,omap5-padconf + - ti,j7200-padconf + - const: pinctrl-single + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#pinctrl-cells': + description: + Number of cells. Usually 2, consisting of register offset, pin configuration + value, and pinmux mode. Some controllers may use 1 for just offset and value. + enum: [ 1, 2 ] + + pinctrl-single,bit-per-mux: + description: Optional flag to indicate register controls more than one pin + type: boolean + + pinctrl-single,function-mask: + description: Mask of the allowed register bits + $ref: /schemas/types.yaml#/definitions/uint32 + + pinctrl-single,function-off: + description: Optional function off mode for disabled state + $ref: /schemas/types.yaml#/definitions/uint32 + + pinctrl-single,register-width: + description: Width of pin specific bits in the register + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 8, 16, 32 ] + + pinctrl-single,gpio-range: + description: Optional list of pin base, nr pins & gpio function + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle of a gpio-range node + - description: pin base + - description: number of pins + - description: gpio function + + '#gpio-range-cells': + description: No longer needed, may exist in older files for gpio-ranges + deprecated: true + const: 3 + + gpio-range: + description: Optional node for gpio range cells + type: object + additionalProperties: false + properties: + '#pinctrl-single,gpio-range-cells': + description: Number of gpio range cells + const: 3 + $ref: /schemas/types.yaml#/definitions/uint32 + +patternProperties: + '-pins(-[0-9]+)?$|-pin$': + description: + Pin group node name using naming ending in -pins followed by an optional + instance number + type: object + additionalProperties: false + + properties: + pinctrl-single,pins: + description: + Array of pins as described in pinmux-node.yaml for pinctrl-pin-array + $ref: /schemas/types.yaml#/definitions/uint32-array + + pinctrl-single,bits: + description: Register bit configuration for pinctrl-single,bit-per-mux + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: register offset + - description: value + - description: pin bitmask in the register + + pinctrl-single,bias-pullup: + description: Optional bias pull up configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: input + - description: enabled pull up bits + - description: disabled pull up bits + - description: bias pull up mask + + pinctrl-single,bias-pulldown: + description: Optional bias pull down configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: input + - description: enabled pull down bits + - description: disabled pull down bits + - description: bias pull down mask + + pinctrl-single,drive-strength: + description: Optional drive strength configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: drive strength current + - description: drive strength mask + + pinctrl-single,input-schmitt: + description: Optional input schmitt configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: input + - description: enable bits + - description: disable bits + - description: input schmitt mask + + pinctrl-single,low-power-mode: + description: Optional low power mode configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: low power mode value + - description: low power mode mask + + pinctrl-single,slew-rate: + description: Optional slew rate configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: slew rate + - description: slew rate mask + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - pinctrl-single,register-width + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <1>; + #size-cells = <1>; + + pinmux@4a100040 { + compatible = "pinctrl-single"; + reg = <0x4a100040 0x0196>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xffff>; + pinctrl-single,gpio-range = <&range 0 3 0>; + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + + uart2-pins { + pinctrl-single,pins = + <0xd8 0x118>, + <0xda 0>, + <0xdc 0x118>, + <0xde 0>; + }; + }; + }; Index: linux-6.1.80/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt +++ linux-6.1.80/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt @@ -9,5 +9,6 @@ Required properties: "ti,omap5-padconf" - OMAP5 compatible pinctrl "ti,dra7-padconf" - DRA7 compatible pinctrl "ti,am437-padconf" - AM437x compatible pinctrl + "ti,am6-padconf" - AM62x compatible pinctrl See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further details. Index: linux-6.1.80/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml @@ -31,10 +31,12 @@ allOf: properties: compatible: enum: + - ti,am62a-c7xv-dsp - ti,j721e-c66-dsp - ti,j721e-c71-dsp - ti,j721s2-c71-dsp description: + Use "ti,am62a-c7xv-dsp" for AM62A Deep learning DSPs on K3 AM62A SoCs Use "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs Use "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs Use "ti,j721s2-c71-dsp" for C71x DSPs on K3 J721S2 SoCs @@ -109,6 +111,7 @@ else: properties: compatible: enum: + - ti,am62a-c7xv-dsp - ti,j721e-c71-dsp - ti,j721s2-c71-dsp then: Index: linux-6.1.80/Documentation/devicetree/bindings/remoteproc/ti,k3-m4f-rproc.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/remoteproc/ti,k3-m4f-rproc.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/ti,k3-m4f-rproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI K3 M4F processor subsystems + +maintainers: + - Hari Nagalla + +description: | + Some K3 family SoCs have Arm Cortex M4F cores. AM64x is a SoC in K3 + family with a M4F core. Typically safety oriented applications may use + the M4F core in isolation without an IPC. Where as some industrial and + home automation applications, may use the M4F core as a remote processor + with IPC communications. + +$ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# + +properties: + $nodename: + pattern: "^m4fss(@.*)?" + + compatible: + enum: + - ti,am64-m4fss + + power-domains: + description: | + Should contain a phandle to a PM domain provider node and an args + specifier containing the M4FSS device id value. + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + reg: + items: + - description: Address and Size of the IRAM internal memory region + - description: Address and Size of the DRAM internal memory region + + reg-names: + items: + - const: iram + - const: dram + + resets: + description: | + Should contain the phandle to the reset controller node managing the + local resets for this device, and a reset specifier. + maxItems: 1 + + firmware-name: + description: | + Should contain the name of the default firmware image + file located on the firmware search path + + mboxes: + description: | + OMAP Mailbox specifier denoting the sub-mailbox, to be used for + communication with the remote processor. This property should match + with the sub-mailbox node used in the firmware image. + maxItems: 1 + + memory-region: + description: | + phandle to the reserved memory nodes to be associated with the + remoteproc device. There should be at least two reserved memory nodes + defined. The reserved memory nodes should be carveout nodes, and + should be defined with a "no-map" property as per the bindings in + Documentation/devicetree/bindings/reserved-memory/reserved-memory.yaml + minItems: 2 + maxItems: 8 + items: + - description: region used for dynamic DMA allocations like vrings and + vring buffers + - description: region reserved for firmware image sections + additionalItems: true + +required: + - compatible + - reg + - reg-names + - ti,sci + - ti,sci-dev-id + - ti,sci-proc-ids + - resets + - firmware-name + - mboxes + - memory-region + +unevaluatedProperties: false + +examples: + - | + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@9cc00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + + mailbox0_cluster0: mailbox-0 { + #mbox-cells = <1>; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + }; + + bus@f0000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; + + bus@4000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; + + mcu_m4fss: m4fss@5000000 { + compatible = "ti,am64-m4fss"; + reg = <0x00 0x5000000 0x00 0x30000>, + <0x00 0x5040000 0x00 0x10000>; + reg-names = "iram", "dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <9>; + ti,sci-proc-ids = <0x18 0xff>; + resets = <&k3_reset 9 1>; + firmware-name = "am62-mcu-m4f0_0-fw"; + mboxes = <&mailbox0_cluster0 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + }; + }; + }; + }; Index: linux-6.1.80/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml @@ -21,6 +21,9 @@ description: | called "Single-CPU" mode, where only Core0 is used, but with ability to use Core1's TCMs as well. + AM62 SoC family support a single R5F core only which runs Device Manager + firmware and can also be used as a remote processor with IPC communication. + Each Dual-Core R5F sub-system is represented as a single DTS node representing the cluster, with a pair of child DT nodes representing the individual R5F cores. Each node has a number of required or optional @@ -34,10 +37,11 @@ properties: compatible: enum: + - ti,am62-r5fss + - ti,am64-r5fss - ti,am654-r5fss - - ti,j721e-r5fss - ti,j7200-r5fss - - ti,am64-r5fss + - ti,j721e-r5fss - ti,j721s2-r5fss power-domains: @@ -64,10 +68,17 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: | Configuration Mode for the Dual R5F cores within the R5F cluster. - Should be either a value of 1 (LockStep mode) or 0 (Split mode) on + For most SoCs (AM65x, J721E, J7200, J721s2), + It should be either a value of 1 (LockStep mode) or 0 (Split mode) on most SoCs (AM65x, J721E, J7200, J721s2), default is LockStep mode if - omitted; and should be either a value of 0 (Split mode) or 2 - (Single-CPU mode) on AM64x SoCs, default is Split mode if omitted. + omitted. + For AM64x SoCs, + It should be either a value of 0 (Split mode) or 2 (Single-CPU mode) and + default is Split mode if omitted. + For AM62x SoCs, + It should be set as 3 (Single-Core mode) which is also the default if + omitted. + # R5F Processor Child Nodes: # ========================== @@ -80,7 +91,9 @@ patternProperties: node representing a TI instantiation of the Arm Cortex R5F core. There are some specific integration differences for the IP like the usage of a Region Address Translator (RAT) for translating the larger SoC bus - addresses into a 32-bit address space for the processor. + addresses into a 32-bit address space for the processor. For AM62x, + the R5F Sub-System device node should only define one R5F child node + as it has only one core available. Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM) internal memories split between two banks - TCMA and TCMB (further @@ -100,10 +113,11 @@ patternProperties: properties: compatible: enum: + - ti,am62-r5f + - ti,am64-r5f - ti,am654-r5f - - ti,j721e-r5f - ti,j7200-r5f - - ti,am64-r5f + - ti,j721e-r5f - ti,j721s2-r5f reg: @@ -208,19 +222,39 @@ patternProperties: unevaluatedProperties: false -if: - properties: - compatible: - enum: - - ti,am64-r5fss -then: - properties: - ti,cluster-mode: - enum: [0, 2] -else: - properties: - ti,cluster-mode: - enum: [0, 1] +allOf: + - if: + properties: + compatible: + enum: + - ti,am64-r5fss + then: + properties: + ti,cluster-mode: + enum: [0, 2] + + - if: + properties: + compatible: + enum: + - ti,am654-r5fss + - ti,j7200-r5fss + - ti,j721e-r5fss + - ti,j721s2-r5fss + then: + properties: + ti,cluster-mode: + enum: [0, 1] + + - if: + properties: + compatible: + enum: + - ti,am62-r5fss + then: + properties: + ti,cluster-mode: + enum: [3] required: - compatible Index: linux-6.1.80/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/ti,pru-consumer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common TI PRU Consumer Binding + +maintainers: + - Suman Anna + +description: | + A PRU application/consumer/user node typically uses one or more PRU device + nodes to implement a PRU application/functionality. Each application/client + node would need a reference to at least a PRU node, and optionally define + some properties needed for hardware/firmware configuration. The below + properties are a list of common properties supported by the PRU remoteproc + infrastructure. + + The application nodes shall define their own bindings like regular platform + devices, so below are in addition to each node's bindings. + +properties: + ti,prus: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: phandles to the PRU, RTU or Tx_PRU nodes used + minItems: 1 + maxItems: 6 + items: + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string-array + minItems: 1 + maxItems: 6 + description: | + firmwares for the PRU cores, the default firmware for the core from + the PRU node will be used if not provided. The firmware names should + correspond to the PRU cores listed in the 'ti,prus' property + + ti,pruss-gp-mux-sel: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 6 + items: + enum: [0, 1, 2, 3, 4] + description: | + array of values for the GP_MUX_SEL under PRUSS_GPCFG register for a PRU. + This selects the internal muxing scheme for the PRU instance. Values + should correspond to the PRU cores listed in the 'ti,prus' property. The + GP_MUX_SEL setting is a per-slice setting (one setting for PRU0, RTU0, + and Tx_PRU0 on K3 SoCs). Use the same value for all cores within the + same slice in the associative array. If the array size is smaller than + the size of 'ti,prus' property, the default out-of-reset value (0) for the + PRU core is used. + +required: + - ti,prus + +additionalProperties: true Index: linux-6.1.80/Documentation/devicetree/bindings/serial/ti,pruss-uart.yaml =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/devicetree/bindings/serial/ti,pruss-uart.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/ti,pruss-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI PRUSS serial UART + +maintainers: + - Bin Liu + +description: | + The PRU-ICSS module has a serial UART peripheral, which is based on + industry standard TL16C550, with 16-bytes TX/RX FIFOs. + +allOf: + - $ref: /schemas/serial.yaml# + +properties: + compatible: + items: + - const: ti,pruss-uart + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + minItems: 3 + maxItems: 3 + description: | + PRU UART interrupt mappings, containing an entry of 3 cell-values. + The first is the PRU System Event id for PRU UART Interrupt Request. + The second is the PRU interrupt channel id. + The third is the PRU host interrupt id. + +required: + - compatible + - reg + - clocks + - interrupt-parent + - interrupts + +examples: + - | + pruss_uart: serial@28000 { + compatible = "ti,pruss-uart"; + reg = <0x28000 0x38>; + clocks = <&dpll_per_m2_ck>; + interrupt-parent = <&pruss_intc>; + interrupts = <6 2 2>; + }; Index: linux-6.1.80/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml @@ -277,6 +277,23 @@ patternProperties: additionalProperties: false + pa-stats@[a-f0-9]+$: + description: | + PA-STATS sub-module represented as a SysCon. + + type: object + + properties: + compatible: + items: + - const: ti,pruss-pa-st + - const: syscon + + reg: + maxItems: 1 + + additionalProperties: false + interrupt-controller@[a-f0-9]+$: description: | PRUSS INTC Node. Each PRUSS has a single interrupt controller instance Index: linux-6.1.80/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml @@ -9,6 +9,19 @@ title: Texas Instruments J72XX VTM (DTS) maintainers: - Keerthy +description: | + The TI K3 family of SoCs typically have a Voltage & Thermal + Management (VTM) device to control up to 8 temperature diode + sensors to measure silicon junction temperatures from different + hotspots of the chip as well as provide temperature, interrupt + and alerting information. + + The following polynomial equation can then be used to convert + value returned by this device into a temperature in Celsius + + Temp(C) = (-9.2627e-12) * x^4 + (6.0373e-08) * x^3 + \ + (-1.7058e-04) * x^2 + (3.2512e-01) * x + (-4.9003e+01) + properties: compatible: enum: @@ -19,7 +32,12 @@ properties: items: - description: VTM cfg1 register space - description: VTM cfg2 register space - - description: VTM efuse register space + - description: | + A software trimming method must be applied to some Jacinto + devices to function properly. This eFuse region provides + the information needed for these SoCs to report + temperatures accurately. + minItems: 2 power-domains: maxItems: 1 @@ -27,6 +45,21 @@ properties: "#thermal-sensor-cells": const: 1 +allOf: + - if: + properties: + compatible: + contains: + const: ti,j721e-vtm + then: + properties: + reg: + minItems: 3 + else: + properties: + reg: + maxItems: 2 + required: - compatible - reg Index: linux-6.1.80/Documentation/devicetree/bindings/usb/ti,am62-usb.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/usb/ti,am62-usb.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/usb/ti,am62-usb.yaml @@ -14,7 +14,9 @@ properties: const: ti,am62-usb reg: - maxItems: 1 + items: + - description: USB CFG register space + - description: USB PHY2 register space ranges: true Index: linux-6.1.80/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml @@ -23,6 +23,8 @@ properties: reg: maxItems: 1 + wakeup-source: true + interrupts: maxItems: 1 @@ -33,8 +35,6 @@ properties: required: - compatible - reg - - interrupts - - interrupt-names additionalProperties: true @@ -48,6 +48,7 @@ examples: tps6598x: tps6598x@38 { compatible = "ti,tps6598x"; reg = <0x38>; + wakeup-source; interrupt-parent = <&msmgpio>; interrupts = <107 IRQ_TYPE_LEVEL_LOW>; Index: linux-6.1.80/Documentation/devicetree/bindings/vendor-prefixes.yaml =================================================================== --- linux-6.1.80.orig/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ linux-6.1.80/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -745,6 +745,8 @@ patternProperties: description: LSI Corp. (LSI Logic) "^lwn,.*": description: Liebherr-Werk Nenzing GmbH + "^lincolntech,.*": + description: Lincoln Technology Solutions "^lxa,.*": description: Linux Automation GmbH "^m5stack,.*": @@ -807,6 +809,8 @@ patternProperties: description: Microsoft Corporation "^microsys,.*": description: MicroSys Electronics GmbH + "^microtips,.*": + description: Microtips Technology USA "^mikroe,.*": description: MikroElektronika d.o.o. "^mikrotik,.*": Index: linux-6.1.80/Documentation/driver-api/media/v4l2-subdev.rst =================================================================== --- linux-6.1.80.orig/Documentation/driver-api/media/v4l2-subdev.rst +++ linux-6.1.80/Documentation/driver-api/media/v4l2-subdev.rst @@ -593,6 +593,14 @@ before calling v4l2_subdev_init_finalize This shares the driver's private mutex between the controls and the states. +Streams, multiplexed media pads and internal routing +---------------------------------------------------- + +A subdevice driver can implement support for multiplexed streams by setting +the V4L2_SUBDEV_FL_STREAMS subdev flag and implementing support for +centrally managed subdev active state, routing and stream based +configuration. + V4L2 sub-device functions and data structures --------------------------------------------- Index: linux-6.1.80/Documentation/driver-api/phy/phy.rst =================================================================== --- linux-6.1.80.orig/Documentation/driver-api/phy/phy.rst +++ linux-6.1.80/Documentation/driver-api/phy/phy.rst @@ -102,27 +102,31 @@ it. This framework provides the followin :: struct phy *phy_get(struct device *dev, const char *string); - struct phy *phy_optional_get(struct device *dev, const char *string); struct phy *devm_phy_get(struct device *dev, const char *string); struct phy *devm_phy_optional_get(struct device *dev, const char *string); + struct phy *devm_of_phy_get(struct device *dev, struct device_node *np, + const char *con_id); + struct phy *devm_of_phy_optional_get(struct device *dev, + struct device_node *np, + const char *con_id); struct phy *devm_of_phy_get_by_index(struct device *dev, struct device_node *np, int index); -phy_get, phy_optional_get, devm_phy_get and devm_phy_optional_get can -be used to get the PHY. In the case of dt boot, the string arguments +phy_get, devm_phy_get and devm_phy_optional_get can be used to get the PHY. +In the case of dt boot, the string arguments should contain the phy name as given in the dt data and in the case of non-dt boot, it should contain the label of the PHY. The two devm_phy_get associates the device with the PHY using devres on successful PHY get. On driver detach, release function is invoked on -the devres data and devres data is freed. phy_optional_get and -devm_phy_optional_get should be used when the phy is optional. These -two functions will never return -ENODEV, but instead returns NULL when -the phy cannot be found.Some generic drivers, such as ehci, may use multiple -phys and for such drivers referencing phy(s) by name(s) does not make sense. In -this case, devm_of_phy_get_by_index can be used to get a phy reference based on -the index. +the devres data and devres data is freed. +The _optional_get variants should be used when the phy is optional. These +functions will never return -ENODEV, but instead return NULL when +the phy cannot be found. +Some generic drivers, such as ehci, may use multiple phys. In this case, +devm_of_phy_get or devm_of_phy_get_by_index can be used to get a phy +reference based on name or index. It should be noted that NULL is a valid phy reference. All phy consumer calls on the NULL phy become NOPs. That is the release calls, Index: linux-6.1.80/Documentation/i2c/i2c-address-translators.rst =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/i2c/i2c-address-translators.rst @@ -0,0 +1,96 @@ +.. SPDX-License-Identifier: GPL-2.0 + +======================= +I2C Address Translators +======================= + +Author: Luca Ceresoli +Author: Tomi Valkeinen + +Description +----------- + +An I2C Address Translator (ATR) is a device with an I2C slave parent +("upstream") port and N I2C master child ("downstream") ports, and +forwards transactions from upstream to the appropriate downstream port +with a modified slave address. The address used on the parent bus is +called the "alias" and is (potentially) different from the physical +slave address of the child bus. Address translation is done by the +hardware. + +An ATR looks similar to an i2c-mux except: + - the address on the parent and child busses can be different + - there is normally no need to select the child port; the alias used on the + parent bus implies it + +The ATR functionality can be provided by a chip with many other features. +The kernel i2c-atr provides a helper to implement an ATR within a driver. + +The ATR creates a new I2C "child" adapter on each child bus. Adding +devices on the child bus ends up in invoking the driver code to select +an available alias. Maintaining an appropriate pool of available aliases +and picking one for each new device is up to the driver implementer. The +ATR maintains a table of currently assigned alias and uses it to modify +all I2C transactions directed to devices on the child buses. + +A typical example follows. + +Topology:: + + Slave X @ 0x10 + .-----. | + .-----. | |---+---- B + | CPU |--A--| ATR | + `-----' | |---+---- C + `-----' | + Slave Y @ 0x10 + +Alias table: + +A, B and C are three physical I2C busses, electrically independent from +each other. The ATR receives the transactions initiated on bus A and +propagates them on bus B or bus C or none depending on the device address +in the transaction and based on the alias table. + +Alias table: + +.. table:: + + =============== ===== + Client Alias + =============== ===== + X (bus B, 0x10) 0x20 + Y (bus C, 0x10) 0x30 + =============== ===== + +Transaction: + + - Slave X driver requests a transaction (on adapter B), slave address 0x10 + - ATR driver finds slave X is on bus B and has alias 0x20, rewrites + messages with address 0x20, forwards to adapter A + - Physical I2C transaction on bus A, slave address 0x20 + - ATR chip detects transaction on address 0x20, finds it in table, + propagates transaction on bus B with address translated to 0x10, + keeps clock streched on bus A waiting for reply + - Slave X chip (on bus B) detects transaction at its own physical + address 0x10 and replies normally + - ATR chip stops clock stretching and forwards reply on bus A, + with address translated back to 0x20 + - ATR driver receives the reply, rewrites messages with address 0x10 + as they were initially + - Slave X driver gets back the msgs[], with reply and address 0x10 + +Usage: + + 1. In the driver (typically in the probe function) add an ATR by + calling i2c_atr_new() passing attach/detach callbacks + 2. When the attach callback is called pick an appropriate alias, + configure it in the chip and return the chosen alias in the + alias_id parameter + 3. When the detach callback is called, deconfigure the alias from + the chip and put the alias back in the pool for later usage + +I2C ATR functions and data structures +------------------------------------- + +.. kernel-doc:: include/linux/i2c-atr.h Index: linux-6.1.80/Documentation/i2c/index.rst =================================================================== --- linux-6.1.80.orig/Documentation/i2c/index.rst +++ linux-6.1.80/Documentation/i2c/index.rst @@ -18,6 +18,7 @@ Introduction i2c-topology muxes/i2c-mux-gpio i2c-sysfs + i2c-address-translators Writing device drivers ====================== Index: linux-6.1.80/Documentation/misc-devices/index.rst =================================================================== --- linux-6.1.80.orig/Documentation/misc-devices/index.rst +++ linux-6.1.80/Documentation/misc-devices/index.rst @@ -28,5 +28,6 @@ fit into other categories. oxsemi-tornado pci-endpoint-test spear-pcie-gadget + tps6594-pfsm uacce xilinx_sdfec Index: linux-6.1.80/Documentation/misc-devices/tps6594-pfsm.rst =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/misc-devices/tps6594-pfsm.rst @@ -0,0 +1,87 @@ +.. SPDX-License-Identifier: GPL-2.0 + +===================================== +Texas Instruments TPS6594 PFSM driver +===================================== + +Author: Julien Panis (jpanis@baylibre.com) + +Overview +======== + +Strictly speaking, PFSM (Pre-configurable Finite State Machine) is not +hardware. It is a piece of code. + +The TPS6594 PMIC (Power Management IC) integrates a state machine which +manages operational modes. Depending on the current operational mode, +some voltage domains remain energized while others can be off. + +The PFSM driver can be used to trigger transitions between configured +states. It also provides R/W access to the device registers. + +Supported chips +--------------- + +- tps6594-q1 +- tps6593-q1 +- lp8764-q1 + +Driver location +=============== + +drivers/misc/tps6594-pfsm.c + +Driver type definitions +======================= + +include/uapi/linux/tps6594_pfsm.h + +Driver IOCTLs +============= + +:c:macro::`PMIC_GOTO_STANDBY` +All device resources are powered down. The processor is off, and +no voltage domains are energized. + +:c:macro::`PMIC_GOTO_LP_STANDBY` +The digital and analog functions of the PMIC, which are not +required to be always-on, are turned off (low-power). + +:c:macro::`PMIC_UPDATE_PGM` +Triggers a firmware update. + +:c:macro::`PMIC_SET_ACTIVE_STATE` +One of the operational modes. +The PMICs are fully functional and supply power to all PDN loads. +All voltage domains are energized in both MCU and Main processor +sections. + +:c:macro::`PMIC_SET_MCU_ONLY_STATE` +One of the operational modes. +Only the power resources assigned to the MCU Safety Island are on. + +:c:macro::`PMIC_SET_RETENTION_STATE` +One of the operational modes. +Depending on the triggers set, some DDR/GPIO voltage domains can +remain energized, while all other domains are off to minimize +total system power. + +Driver usage +============ + +See available PFSMs:: + + # ls /dev/pfsm* + +Dump the registers of pages 0 and 1:: + + # hexdump -C /dev/pfsm-0-0x48 + +See PFSM events:: + + # cat /proc/interrupts + +Userspace code example +---------------------- + +samples/pfsm/pfsm-wakeup.c Index: linux-6.1.80/Documentation/userspace-api/ioctl/ioctl-number.rst =================================================================== --- linux-6.1.80.orig/Documentation/userspace-api/ioctl/ioctl-number.rst +++ linux-6.1.80/Documentation/userspace-api/ioctl/ioctl-number.rst @@ -179,6 +179,7 @@ Code Seq# Include File 'P' 00-0F drivers/usb/class/usblp.c conflict! 'P' 01-09 drivers/misc/pci_endpoint_test.c conflict! 'P' 00-0F xen/privcmd.h conflict! +'P' 00-05 linux/tps6594_pfsm.h conflict! 'Q' all linux/soundcard.h 'R' 00-1F linux/random.h conflict! 'R' 01 linux/rfkill.h conflict! Index: linux-6.1.80/Documentation/userspace-api/media/v4l/dev-subdev.rst =================================================================== --- linux-6.1.80.orig/Documentation/userspace-api/media/v4l/dev-subdev.rst +++ linux-6.1.80/Documentation/userspace-api/media/v4l/dev-subdev.rst @@ -29,6 +29,8 @@ will feature a character device node on - negotiate image formats on individual pads +- inspect and modify internal data routing between pads of the same entity + Sub-device character device nodes, conventionally named ``/dev/v4l-subdev*``, use major number 81. @@ -404,6 +406,8 @@ pixel array is not rectangular but cross size may also be smaller than the BOUNDS rectangle. +.. _format-propagation: + Order of configuration and format propagation --------------------------------------------- @@ -501,3 +505,165 @@ source pads. :maxdepth: 1 subdev-formats + +Streams, multiplexed media pads and internal routing +---------------------------------------------------- + +Simple V4L2 sub-devices do not support multiple, unrelated video streams, +and only a single stream can pass through a media link and a media pad. +Thus each pad contains a format and selection configuration for that +single stream. A subdev can do stream processing and split a stream into +two or compose two streams into one, but the inputs and outputs for the +subdev are still a single stream per pad. + +Some hardware, e.g. MIPI CSI-2, support multiplexed streams, that is, multiple +data streams are transmitted on the same bus, which is represented by a media +link connecting a transmitter source pad with a sink pad on the receiver. For +example, a camera sensor can produce two distinct streams, a pixel stream and a +metadata stream, which are transmitted on the multiplexed data bus, represented +by a media link which connects the single sensor's source pad with the receiver +sink pad. The stream-aware receiver will de-multiplex the streams received on +the its sink pad and allows to route them individually to one of its source +pads. + +Subdevice drivers that support multiplexed streams are compatible with +non-multiplexed subdev drivers, but, of course, require a routing configuration +where the link between those two types of drivers contains only a single +stream. + +Understanding streams +^^^^^^^^^^^^^^^^^^^^^ + +A stream is a stream of content (e.g. pixel data or metadata) flowing through +the media pipeline from a source (e.g. a sensor) towards the final sink (e.g. a +receiver and demultiplexer in a SoC). Each media link carries all the enabled +streams from one end of the link to the other, and sub-devices have routing +tables which describe how the incoming streams from sink pads are routed to the +source pads. + +A stream ID is a media pad-local identifier for a stream. Streams IDs of +the same stream must be equal on both ends of a link. In other words, +a particular stream ID must exist on both sides of a media +link, but another stream ID can be used for the same stream at the other side +of the sub-device. + +A stream at a specific point in the media pipeline is identified by the +sub-device and a (pad, stream) pair. For sub-devices that do not support +multiplexed streams the 'stream' field is always 0. + +Interaction between routes, streams, formats and selections +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The addition of streams to the V4L2 sub-device interface moves the sub-device +formats and selections from pads to (pad, stream) pairs. Besides the +usual pad, also the stream ID needs to be provided for setting formats and +selections. The order of configuring formats and selections along a stream is +the same as without streams (see :ref:`format-propagation`). + +Instead of the sub-device wide merging of streams from all sink pads +towards all source pads, data flows for each route are separate from each +other. Any number of routes from streams on sink pads towards streams on +source pads is allowed, to the extent supported by drivers. For every +stream on a source pad, however, only a single route is allowed. + +Any configurations of a stream within a pad, such as format or selections, +are independent of similar configurations on other streams. This is +subject to change in the future. + +Configuring streams +^^^^^^^^^^^^^^^^^^^ + +The configuration of the streams is done individually for each sub-device and +the validity of the streams between sub-devices is validated when the pipeline +is started. + +There are three steps in configuring the streams: + +1) Set up links. Connect the pads between sub-devices using the :ref:`Media +Controller API ` + +2) Streams. Streams are declared and their routing is configured by +setting the routing table for the sub-device using +:ref:`VIDIOC_SUBDEV_S_ROUTING ` ioctl. Note that +setting the routing table will reset formats and selections in the +sub-device to default values. + +3) Configure formats and selections. Formats and selections of each stream +are configured separately as documented for plain sub-devices in +:ref:`format-propagation`. The stream ID is set to the same stream ID +associated with either sink or source pads of routes configured using the +:ref:`VIDIOC_SUBDEV_S_ROUTING ` ioctl. + +Multiplexed streams setup example +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +A simple example of a multiplexed stream setup might be as follows: + +- Two identical sensors (Sensor A and Sensor B). Each sensor has a single source + pad (pad 0) which carries a pixel data stream. + +- Multiplexer bridge (Bridge). The bridge has two sink pads, connected to the + sensors (pads 0, 1), and one source pad (pad 2), which outputs two streams. + +- Receiver in the SoC (Receiver). The receiver has a single sink pad (pad 0), + connected to the bridge, and two source pads (pads 1-2), going to the DMA + engine. The receiver demultiplexes the incoming streams to the source pads. + +- DMA Engines in the SoC (DMA Engine), one for each stream. Each DMA engine is + connected to a single source pad in the receiver. + +The sensors, the bridge and the receiver are modeled as V4L2 sub-devices, +exposed to userspace via /dev/v4l-subdevX device nodes. The DMA engines are +modeled as V4L2 devices, exposed to userspace via /dev/videoX nodes. + +To configure this pipeline, the userspace must take the following steps: + +1) Set up media links between entities: connect the sensors to the bridge, +bridge to the receiver, and the receiver to the DMA engines. This step does +not differ from normal non-multiplexed media controller setup. + +2) Configure routing + +.. flat-table:: Bridge routing table + :header-rows: 1 + + * - Sink Pad/Stream + - Source Pad/Stream + - Routing Flags + - Comments + * - 0/0 + - 2/0 + - V4L2_SUBDEV_ROUTE_FL_ACTIVE + - Pixel data stream from Sensor A + * - 1/0 + - 2/1 + - V4L2_SUBDEV_ROUTE_FL_ACTIVE + - Pixel data stream from Sensor B + +.. flat-table:: Receiver routing table + :header-rows: 1 + + * - Sink Pad/Stream + - Source Pad/Stream + - Routing Flags + - Comments + * - 0/0 + - 1/0 + - V4L2_SUBDEV_ROUTE_FL_ACTIVE + - Pixel data stream from Sensor A + * - 0/1 + - 2/0 + - V4L2_SUBDEV_ROUTE_FL_ACTIVE + - Pixel data stream from Sensor B + +3) Configure formats and selections + +After configuring routing, the next step is configuring the formats and +selections for the streams. This is similar to performing this step without +streams, with just one exception: the ``stream`` field needs to be assigned +to the value of the stream ID. + +A common way to accomplish this is to start from the sensors and propagate the +configurations along the stream towards the receiver, +using :ref:`VIDIOC_SUBDEV_S_FMT ` ioctls to configure each +stream endpoint in each sub-device. Index: linux-6.1.80/Documentation/userspace-api/media/v4l/user-func.rst =================================================================== --- linux-6.1.80.orig/Documentation/userspace-api/media/v4l/user-func.rst +++ linux-6.1.80/Documentation/userspace-api/media/v4l/user-func.rst @@ -70,6 +70,7 @@ Function Reference vidioc-subdev-g-crop vidioc-subdev-g-fmt vidioc-subdev-g-frame-interval + vidioc-subdev-g-routing vidioc-subdev-g-selection vidioc-subdev-querycap vidioc-subscribe-event Index: linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-enum-frame-interval.rst =================================================================== --- linux-6.1.80.orig/Documentation/userspace-api/media/v4l/vidioc-subdev-enum-frame-interval.rst +++ linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-enum-frame-interval.rst @@ -92,7 +92,10 @@ multiple pads of the same sub-device is - Frame intervals to be enumerated, from enum :ref:`v4l2_subdev_format_whence `. * - __u32 - - ``reserved``\ [8] + - ``stream`` + - Stream identifier. + * - __u32 + - ``reserved``\ [7] - Reserved for future extensions. Applications and drivers must set the array to zero. Index: linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-enum-frame-size.rst =================================================================== --- linux-6.1.80.orig/Documentation/userspace-api/media/v4l/vidioc-subdev-enum-frame-size.rst +++ linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-enum-frame-size.rst @@ -97,7 +97,10 @@ information about try formats. - Frame sizes to be enumerated, from enum :ref:`v4l2_subdev_format_whence `. * - __u32 - - ``reserved``\ [8] + - ``stream`` + - Stream identifier. + * - __u32 + - ``reserved``\ [7] - Reserved for future extensions. Applications and drivers must set the array to zero. Index: linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-enum-mbus-code.rst =================================================================== --- linux-6.1.80.orig/Documentation/userspace-api/media/v4l/vidioc-subdev-enum-mbus-code.rst +++ linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-enum-mbus-code.rst @@ -73,7 +73,10 @@ information about the try formats. - ``flags`` - See :ref:`v4l2-subdev-mbus-code-flags` * - __u32 - - ``reserved``\ [7] + - ``stream`` + - Stream identifier. + * - __u32 + - ``reserved``\ [6] - Reserved for future extensions. Applications and drivers must set the array to zero. Index: linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-g-crop.rst =================================================================== --- linux-6.1.80.orig/Documentation/userspace-api/media/v4l/vidioc-subdev-g-crop.rst +++ linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-g-crop.rst @@ -96,7 +96,10 @@ modified format should be as close as po - ``rect`` - Crop rectangle boundaries, in pixels. * - __u32 - - ``reserved``\ [8] + - ``stream`` + - Stream identifier. + * - __u32 + - ``reserved``\ [7] - Reserved for future extensions. Applications and drivers must set the array to zero. Index: linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-g-fmt.rst =================================================================== --- linux-6.1.80.orig/Documentation/userspace-api/media/v4l/vidioc-subdev-g-fmt.rst +++ linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-g-fmt.rst @@ -102,7 +102,10 @@ should be as close as possible to the or - Definition of an image format, see :c:type:`v4l2_mbus_framefmt` for details. * - __u32 - - ``reserved``\ [8] + - ``stream`` + - Stream identifier. + * - __u32 + - ``reserved``\ [7] - Reserved for future extensions. Applications and drivers must set the array to zero. Index: linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-g-frame-interval.rst =================================================================== --- linux-6.1.80.orig/Documentation/userspace-api/media/v4l/vidioc-subdev-g-frame-interval.rst +++ linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-g-frame-interval.rst @@ -90,7 +90,10 @@ the same sub-device is not defined. - ``interval`` - Period, in seconds, between consecutive video frames. * - __u32 - - ``reserved``\ [9] + - ``stream`` + - Stream identifier. + * - __u32 + - ``reserved``\ [8] - Reserved for future extensions. Applications and drivers must set the array to zero. Index: linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-g-routing.rst =================================================================== --- /dev/null +++ linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-g-routing.rst @@ -0,0 +1,147 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: V4L + +.. _VIDIOC_SUBDEV_G_ROUTING: + +****************************************************** +ioctl VIDIOC_SUBDEV_G_ROUTING, VIDIOC_SUBDEV_S_ROUTING +****************************************************** + +Name +==== + +VIDIOC_SUBDEV_G_ROUTING - VIDIOC_SUBDEV_S_ROUTING - Get or set routing between streams of media pads in a media entity. + + +Synopsis +======== + +.. c:macro:: VIDIOC_SUBDEV_G_ROUTING + +``int ioctl(int fd, VIDIOC_SUBDEV_G_ROUTING, struct v4l2_subdev_routing *argp)`` + +.. c:macro:: VIDIOC_SUBDEV_S_ROUTING + +``int ioctl(int fd, VIDIOC_SUBDEV_S_ROUTING, struct v4l2_subdev_routing *argp)`` + +Arguments +========= + +``fd`` + File descriptor returned by :ref:`open() `. + +``argp`` + Pointer to struct :c:type:`v4l2_subdev_routing`. + + +Description +=========== + +These ioctls are used to get and set the routing in a media entity. +The routing configuration determines the flows of data inside an entity. + +Drivers report their current routing tables using the +``VIDIOC_SUBDEV_G_ROUTING`` ioctl and application may enable or disable routes +with the ``VIDIOC_SUBDEV_S_ROUTING`` ioctl, by adding or removing routes and +setting or clearing flags of the ``flags`` field of a +struct :c:type:`v4l2_subdev_route`. + +All stream configurations are reset when ``VIDIOC_SUBDEV_S_ROUTING`` is called. This +means that the userspace must reconfigure all streams after calling the ioctl +with e.g. ``VIDIOC_SUBDEV_S_FMT``. + +Only subdevices which have both sink and source pads can support routing. + +When inspecting routes through ``VIDIOC_SUBDEV_G_ROUTING`` and the application +provided ``num_routes`` is not big enough to contain all the available routes +the subdevice exposes, drivers return the ENOSPC error code and adjust the +value of the ``num_routes`` field. Application should then reserve enough memory +for all the route entries and call ``VIDIOC_SUBDEV_G_ROUTING`` again. + +.. tabularcolumns:: |p{4.4cm}|p{4.4cm}|p{8.7cm}| + +.. c:type:: v4l2_subdev_routing + +.. flat-table:: struct v4l2_subdev_routing + :header-rows: 0 + :stub-columns: 0 + :widths: 1 1 2 + + * - __u32 + - ``which`` + - Format to modified, from enum + :ref:`v4l2_subdev_format_whence `. + * - struct :c:type:`v4l2_subdev_route` + - ``routes[]`` + - Array of struct :c:type:`v4l2_subdev_route` entries + * - __u32 + - ``num_routes`` + - Number of entries of the routes array + * - __u32 + - ``reserved``\ [5] + - Reserved for future extensions. Applications and drivers must set + the array to zero. + +.. tabularcolumns:: |p{4.4cm}|p{4.4cm}|p{8.7cm}| + +.. c:type:: v4l2_subdev_route + +.. flat-table:: struct v4l2_subdev_route + :header-rows: 0 + :stub-columns: 0 + :widths: 1 1 2 + + * - __u32 + - ``sink_pad`` + - Sink pad number. + * - __u32 + - ``sink_stream`` + - Sink pad stream number. + * - __u32 + - ``source_pad`` + - Source pad number. + * - __u32 + - ``source_stream`` + - Source pad stream number. + * - __u32 + - ``flags`` + - Route enable/disable flags + :ref:`v4l2_subdev_routing_flags `. + * - __u32 + - ``reserved``\ [5] + - Reserved for future extensions. Applications and drivers must set + the array to zero. + +.. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.7cm}| + +.. _v4l2-subdev-routing-flags: + +.. flat-table:: enum v4l2_subdev_routing_flags + :header-rows: 0 + :stub-columns: 0 + :widths: 3 1 4 + + * - V4L2_SUBDEV_ROUTE_FL_ACTIVE + - 0 + - The route is enabled. Set by applications. + +Return Value +============ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. + +ENOSPC + The application provided ``num_routes`` is not big enough to contain + all the available routes the subdevice exposes. + +EINVAL + The sink or source pad identifiers reference a non-existing pad, or reference + pads of different types (ie. the sink_pad identifiers refers to a source pad) + or the sink or source stream identifiers reference a non-existing stream on + the sink or source pad. + +E2BIG + The application provided ``num_routes`` for ``VIDIOC_SUBDEV_S_ROUTING`` is + larger than the number of routes the driver can handle. Index: linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-g-selection.rst =================================================================== --- linux-6.1.80.orig/Documentation/userspace-api/media/v4l/vidioc-subdev-g-selection.rst +++ linux-6.1.80/Documentation/userspace-api/media/v4l/vidioc-subdev-g-selection.rst @@ -94,7 +94,10 @@ Selection targets and flags are document - ``r`` - Selection rectangle, in pixels. * - __u32 - - ``reserved``\ [8] + - ``stream`` + - Stream identifier. + * - __u32 + - ``reserved``\ [7] - Reserved for future extensions. Applications and drivers must set the array to zero. Index: linux-6.1.80/MAINTAINERS =================================================================== --- linux-6.1.80.orig/MAINTAINERS +++ linux-6.1.80/MAINTAINERS @@ -2994,7 +2994,6 @@ F: Documentation/devicetree/bindings/arm F: Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml F: arch/arm64/boot/dts/ti/Makefile F: arch/arm64/boot/dts/ti/k3-* -F: include/dt-bindings/pinctrl/k3.h ARM/THECUS N2100 MACHINE SUPPORT M: Lennert Buytenhek @@ -5140,7 +5139,7 @@ M: Philipp Zabel @@ -9563,6 +9562,14 @@ L: linux-acpi@vger.kernel.org S: Maintained F: drivers/i2c/i2c-core-acpi.c +I2C ADDRESS TRANSLATOR (ATR) +M: Tomi Valkeinen +R: Luca Ceresoli +L: linux-i2c@vger.kernel.org +S: Maintained +F: drivers/i2c/i2c-atr.c +F: include/linux/i2c-atr.h + I2C CONTROLLER DRIVER FOR NVIDIA GPU M: Ajay Gupta L: linux-i2c@vger.kernel.org @@ -9990,10 +9997,25 @@ S: Maintained F: Documentation/devicetree/bindings/auxdisplay/img,ascii-lcd.yaml F: drivers/auxdisplay/img-ascii-lcd.c +IMGTEC VIDEO CODEC V4L2 DRIVER +M: Darren Etheridge +M: Brandon Brnich +S: Maintained +F: Documentation/devicetree/bindings/media/img,d5500-vxd.yaml +F: Documentation/devicetree/bindings/media/img,vxe384.yaml +F: drivers/media/platform/img/vxe-vxd + IMGTEC IR DECODER DRIVER S: Orphan F: drivers/media/rc/img-ir/ +IMGTEC JPEG ENCODER DRIVER +M: Devarsh Thakkar +L: linux-media@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/media/img,e5010-jpeg-enc.yaml +F: drivers/media/platform/img/e5010/ + IMON SOUNDGRAPH USB IR RECEIVER M: Sean Young L: linux-media@vger.kernel.org @@ -15131,6 +15153,7 @@ F: drivers/mfd/menelaus.c F: drivers/mfd/palmas.c F: drivers/mfd/tps65217.c F: drivers/mfd/tps65218.c +F: drivers/mfd/tps65219.c F: drivers/mfd/tps65910.c F: drivers/mfd/twl-core.[ch] F: drivers/mfd/twl4030*.c @@ -15187,6 +15210,16 @@ S: Maintained T: git git://linuxtv.org/media_tree.git F: drivers/media/i2c/ov08d10.c +OMNIVISION OV1063x SENSOR DRIVER +M: Benoit Parrot +M: Sukrut Bellary +L: linux-media@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/i2c/ov1063x.yaml +F: drivers/media/i2c/ov1063x.c +F: drivers/media/i2c/ov1063x_regs.h + OMNIVISION OV13858 SENSOR DRIVER M: Sakari Ailus L: linux-media@vger.kernel.org @@ -20622,6 +20655,14 @@ F: drivers/misc/tifm* F: drivers/mmc/host/tifm_sd.c F: include/linux/tifm.h +TI FPD-LINK DRIVERS +M: Tomi Valkeinen +L: linux-media@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/media/i2c/ti,ds90* +F: drivers/media/i2c/ds90* +F: include/media/i2c/ds90* + TI KEYSTONE MULTICORE NAVIGATOR DRIVERS M: Nishanth Menon M: Santosh Shilimkar @@ -20681,6 +20722,7 @@ S: Maintained W: http://linuxtv.org/ Q: http://patchwork.linuxtv.org/project/linux-media/list/ F: Documentation/devicetree/bindings/media/ti,cal.yaml +F: Documentation/devicetree/bindings/media/ti,vip.yaml F: Documentation/devicetree/bindings/media/ti,vpe.yaml F: drivers/media/platform/ti/cal/ F: drivers/media/platform/ti/vpe/ @@ -22146,6 +22188,15 @@ F: include/linux/watchdog.h F: include/uapi/linux/watchdog.h F: include/trace/events/watchdog.h +WAVE5 VPU CODEC DRIVER +M: Nas Chung +M: Robert Beckett +M: Sebastian Fricke +L: linux-media@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/media/cnm,wave5.yaml +F: drivers/media/platform/chips-media/wave5/ + WHISKEYCOVE PMIC GPIO DRIVER M: Kuppuswamy Sathyanarayanan L: linux-gpio@vger.kernel.org Index: linux-6.1.80/Makefile =================================================================== --- linux-6.1.80.orig/Makefile +++ linux-6.1.80/Makefile @@ -2019,7 +2019,9 @@ clean: $(clean-dirs) @find $(or $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \ \( -name '*.[aios]' -o -name '*.rsi' -o -name '*.ko' -o -name '.*.cmd' \ -o -name '*.ko.*' \ - -o -name '*.dtb' -o -name '*.dtbo' -o -name '*.dtb.S' -o -name '*.dt.yaml' \ + -o -name '*.dtb' -o -name '*.dtbo' \ + -o -name '*.dtb.S' -o -name '*.dtbo.S' \ + -o -name '*.dt.yaml' \ -o -name '*.dwo' -o -name '*.lst' \ -o -name '*.su' -o -name '*.mod' -o -name '*.usyms' \ -o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \ Index: linux-6.1.80/arch/arm/Makefile =================================================================== --- linux-6.1.80.orig/arch/arm/Makefile +++ linux-6.1.80/arch/arm/Makefile @@ -310,6 +310,10 @@ endif # My testing targets (bypasses dependencies) bp:; $(Q)$(MAKE) $(build)=$(boot) $(boot)/bootpImage +include $(srctree)/scripts/Makefile.defconf +PHONY += multi_v7_lpae_defconfig +multi_v7_lpae_defconfig: + $(call merge_into_defconfig,multi_v7_defconfig,lpae) define archhelp echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)' @@ -325,4 +329,6 @@ define archhelp echo ' (distribution) /sbin/$(INSTALLKERNEL) or' echo ' install to $$(INSTALL_PATH) and run lilo' echo ' vdso_install - Install unstripped vdso.so to $$(INSTALL_MOD_PATH)/vdso' + echo + echo ' multi_v7_lpae_defconfig - multi_v7_defconfig with CONFIG_ARM_LPAE enabled' endef Index: linux-6.1.80/arch/arm/boot/dts/Makefile =================================================================== --- linux-6.1.80.orig/arch/arm/boot/dts/Makefile +++ linux-6.1.80/arch/arm/boot/dts/Makefile @@ -933,6 +933,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-base0033.dtb \ am335x-bone.dtb \ am335x-boneblack.dtb \ + am335x-boneblack-pps.dtb \ am335x-boneblack-wireless.dtb \ am335x-boneblue.dtb \ am335x-bonegreen.dtb \ @@ -988,20 +989,29 @@ dtb-$(CONFIG_SOC_OMAP5) += \ omap5-igep0050.dtb \ omap5-sbc-t54.dtb \ omap5-uevm.dtb +am57xx-evm-dtbs := am57xx-beagle-x15.dtb am57xx-evm.dtbo +am57xx-evm-reva3-dtbs := am57xx-beagle-x15-revc.dtb am57xx-evm.dtbo dtb-$(CONFIG_SOC_DRA7XX) += \ am57xx-beagle-x15.dtb \ am57xx-beagle-x15-revb1.dtb \ am57xx-beagle-x15-revc.dtb \ + am57xx-evm.dtb \ + am57xx-evm-reva3.dtb \ am5729-beagleboneai.dtb \ am57xx-cl-som-am57x.dtb \ am57xx-sbc-am57x.dtb \ am572x-idk.dtb \ + am572x-idk-touchscreen.dtbo \ am571x-idk.dtb \ + am571x-idk-touchscreen.dtbo \ am574x-idk.dtb \ + am57xx-idk-lcd-osd101t2045.dtbo \ + am57xx-idk-lcd-osd101t2587.dtbo \ dra7-evm.dtb \ dra72-evm.dtb \ dra72-evm-revc.dtb \ dra71-evm.dtb \ + ov10635.dtbo \ dra76-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += \ orion5x-kuroboxpro.dtb \ Index: linux-6.1.80/arch/arm/boot/dts/am335x-boneblack-pps.dts =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm/boot/dts/am335x-boneblack-pps.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include "am335x-boneblack.dts" + +&am33xx_pinmux { + pwm7_pins: pinmux_pwm7_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + >; + }; +}; + +/{ + pwm7: dmtimer-pwm7 { + compatible = "ti,omap-dmtimer-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; + #pwm-cells = <3>; + ti,timers = <&timer7>; + ti,clock-source = <0x00>; /* timer_sys_ck */ + }; +}; Index: linux-6.1.80/arch/arm/boot/dts/am335x-evmsk.dts =================================================================== --- linux-6.1.80.orig/arch/arm/boot/dts/am335x-evmsk.dts +++ linux-6.1.80/arch/arm/boot/dts/am335x-evmsk.dts @@ -29,6 +29,11 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; + aliases { + serial0 = &uart0; + serial1 = &pruss_uart; + }; + chosen { stdout-path = &uart0; }; @@ -441,6 +446,22 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */ >; }; + + pruss_uart_pins: pruss_uart_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* spi0_sclk.pr1_uart0_cts_n */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* spi0_d0.pr1_uart0_rts_n */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE4) /* spi0_d1.pr1_uart0_rxd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT_PULLUP, MUX_MODE4) /* spi0_cs9.pr1_uart0_txd */ + >; + }; +}; + +&pruss_uart { + interrupts = <6 2 2>; + pinctrl-names = "default"; + pinctrl-0 = <&pruss_uart_pins>; + status = "okay"; }; &uart0 { Index: linux-6.1.80/arch/arm/boot/dts/am33xx-l4.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm/boot/dts/am33xx-l4.dtsi +++ linux-6.1.80/arch/arm/boot/dts/am33xx-l4.dtsi @@ -891,6 +891,14 @@ }; }; + pruss_uart: serial@28000 { + compatible = "ti,pruss-uart"; + reg = <0x28000 0x38>; + clocks = <&dpll_per_m2_ck>; + interrupt-parent = <&pruss_intc>; + status = "disabled"; + }; + pruss_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x58>; Index: linux-6.1.80/arch/arm/boot/dts/am33xx.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm/boot/dts/am33xx.dtsi +++ linux-6.1.80/arch/arm/boot/dts/am33xx.dtsi @@ -630,10 +630,11 @@ #size-cells = <1>; ranges = <0 0x56000000 0x1000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu: gpu@0 { + compatible = "ti,am3352-sgx530", "img,sgx530"; + reg = <0x0 0x10000>; + interrupts = <37>; + }; }; }; }; Index: linux-6.1.80/arch/arm/boot/dts/am4372.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm/boot/dts/am4372.dtsi +++ linux-6.1.80/arch/arm/boot/dts/am4372.dtsi @@ -714,6 +714,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x56000000 0x1000000>; + + gpu: gpu@0 { + compatible = "ti,am4376-sgx530", "img,sgx530"; + reg = <0x0 0x10000>; + interrupts = ; + }; }; }; }; Index: linux-6.1.80/arch/arm/boot/dts/am571x-idk-touchscreen.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm/boot/dts/am571x-idk-touchscreen.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen: edt-ft5506@38 { + compatible = "edt,edt-ft5506", "edt,edt-ft5x06"; + + reg = <0x38>; + + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + + /* GPIO line is inverted before going to touch panel */ + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + + touchscreen-size-x = <1920>; + touchscreen-size-y = <1200>; + + wakeup-source; + }; +}; Index: linux-6.1.80/arch/arm/boot/dts/am572x-idk-touchscreen.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm/boot/dts/am572x-idk-touchscreen.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen: edt-ft5506@38 { + compatible = "edt,edt-ft5506", "edt,edt-ft5x06"; + + reg = <0x38>; + + interrupt-parent = <&gpio3>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + + /* GPIO line is inverted before going to touch panel */ + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + + touchscreen-size-x = <1920>; + touchscreen-size-y = <1200>; + + wakeup-source; + }; +}; Index: linux-6.1.80/arch/arm/boot/dts/am57xx-beagle-x15.dts =================================================================== --- linux-6.1.80.orig/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ linux-6.1.80/arch/arm/boot/dts/am57xx-beagle-x15.dts @@ -12,7 +12,7 @@ &tpd12s015 { gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ - <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ + <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ }; Index: linux-6.1.80/arch/arm/boot/dts/am57xx-evm.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm/boot/dts/am57xx-evm.dtso @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT overlay for AM57xx GP EVM boards + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + compatible = "ti,am5728-evm", "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; + model = "TI AM5728 EVM"; + + aliases { + display0 = "/display"; + display1 = "/connector"; // Fixme: &lcd0 and &hdmi0 could be + // resolved here correcly based on + // information in the base dtb symbol + // table with a fix in dtc + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user1 { + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + label = "USER1"; + linux,code = ; + }; + + button-user2 { + gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; + label = "USER2"; + linux,code = ; + }; + + button-user3 { + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + label = "USER3"; + linux,code = ; + }; + + button-user4 { + gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + label = "USER4"; + linux,code = ; + }; + + button-user5 { + gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; + label = "USER5"; + linux,code = ; + }; + }; + + lcd0: display { + compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; + backlight = <&lcd_bl>; + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + label = "lcd"; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 243 245 247 249 251 252 253 255>; + default-brightness-level = <8>; + pwms = <&ehrpwm1 0 50000 0>; + }; +}; + +&ehrpwm1 { + status = "okay"; +}; + +&epwmss1 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@5c { + compatible = "pixcir,pixcir_tangoc"; + attb-gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio2>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + reg = <0x5c>; + reset-gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + }; +}; + +&uart8 { + status = "okay"; +}; + +&dss { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_out: endpoint { + data-lines = <24>; + remote-endpoint = <&lcd_in>; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + aliases { + display0 = "/display"; + display1 = "/connector"; + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 1>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; +}; + +&dsi_bridge { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + lcd: display { + compatible = "osddisplays,osd101t2045-53ts"; + reg = <0>; + + label = "lcd"; + + backlight = <&lcd_bl>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_bridge_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&lcd_in>; + }; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&ecap0 { + status = "okay"; +}; Index: linux-6.1.80/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + aliases { + display0 = "/display"; + display1 = "/connector"; + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 1>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; +}; + +&dsi_bridge { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + lcd: display { + compatible = "osddisplays,osd101t2587-53ts"; + reg = <0>; + + label = "lcd"; + + backlight = <&lcd_bl>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_bridge_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&lcd_in>; + }; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&ecap0 { + status = "okay"; +}; Index: linux-6.1.80/arch/arm/boot/dts/dra7.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm/boot/dts/dra7.dtsi +++ linux-6.1.80/arch/arm/boot/dts/dra7.dtsi @@ -847,12 +847,19 @@ ; ti,sysc-sidle = , , - ; + , + ; clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; + + gpu: gpu@0 { + compatible = "ti,dra7-sgx544", "img,sgx544"; + reg = <0x0 0x10000>; + interrupts = ; + }; }; crossbar_mpu: crossbar@4a002a48 { Index: linux-6.1.80/arch/arm/boot/dts/dra74x.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm/boot/dts/dra74x.dtsi +++ linux-6.1.80/arch/arm/boot/dts/dra74x.dtsi @@ -49,7 +49,6 @@ reg = <0x41500000 0x100>; }; - target-module@41501000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x41501000 0x4>, @@ -228,5 +227,126 @@ }; }; }; + }; + + target-module@190000 { /* 0x48990000, ap 23 2e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x190010 0x4>; + reg-names = "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x190000 0x10000>; + + vip2: vip@0 { + compatible = "ti,dra7-vip2"; + label = "vip2"; + reg = <0x0000 0x114>, + <0x5500 0xd8>, + <0x5700 0x18>, + <0x5800 0x80>, + <0x5a00 0xd8>, + <0x5c00 0x18>, + <0x5d00 0x80>, + <0xd000 0x400>; + reg-names = "vip", + "parser0", + "csc0", + "sc0", + "parser1", + "csc1", + "sc1", + "vpdma"; + interrupts = , + ; + /* CTRL_CORE_SMA_SW_1 */ + ti,vip-clk-polarity = <&scm_conf 0x534>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + vin3a: port@0 { + reg = <0>; + label = "vin3a"; + }; + vin4a: port@1 { + reg = <1>; + label = "vin4a"; + }; + vin3b: port@2 { + reg = <2>; + label = "vin3b"; + }; + vin4b: port@3 { + reg = <3>; + label = "vin4b"; + }; + }; + }; + }; + + target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x1b0000 0x4>, + <0x1b0010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b0000 0x10000>; + + vip3: vip@0 { + compatible = "ti,dra7-vip3"; + label = "vip3"; + reg = <0x0000 0x114>, + <0x5500 0xd8>, + <0x5700 0x18>, + <0x5800 0x80>, + <0x5a00 0xd8>, + <0x5c00 0x18>, + <0x5d00 0x80>, + <0xd000 0x400>; + reg-names = "vip", + "parser0", + "csc0", + "sc0", + "parser1", + "csc1", + "sc1", + "vpdma"; + interrupts = , + ; + /* CTRL_CORE_SMA_SW_1 */ + ti,vip-clk-polarity = <&scm_conf 0x534>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + vin5a: port@0 { + reg = <0>; + label = "vin5a"; + }; + vin6a: port@1 { + reg = <1>; + label = "vin6a"; + }; + }; + }; }; }; Index: linux-6.1.80/arch/arm/boot/dts/omap34xx.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm/boot/dts/omap34xx.dtsi +++ linux-6.1.80/arch/arm/boot/dts/omap34xx.dtsi @@ -164,12 +164,13 @@ clock-names = "fck", "ick"; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x50000000 0x4000>; + ranges = <0 0x50000000 0x10000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + sgx: gpu@0 { + compatible = "ti,omap3530-sgx530", "img,sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <21>; + }; }; }; Index: linux-6.1.80/arch/arm/boot/dts/omap4.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm/boot/dts/omap4.dtsi +++ linux-6.1.80/arch/arm/boot/dts/omap4.dtsi @@ -501,10 +501,11 @@ #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap4430-sgx540", "img,sgx540"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = ; + }; }; /* Index: linux-6.1.80/arch/arm/boot/dts/ov10635.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm/boot/dts/ov10635.dtso @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include + +/ { + fragment@101 { + target-path = "/"; + + __overlay__ { + clk_ov10635: clock-gate { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_ov10635_fixed>; + enable-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + }; + + clk_ov10635_fixed: clock-fixed { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + #address-cells = <1>; + #size-cells = <0>; + + ov10635@30 { + compatible = "ovti,ov10635"; + reg = <0x30>; + clock-names = "xvclk"; + clocks = <&clk_ov10635>; + powerdown-gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + + port { + cam: endpoint { + remote-endpoint = <&vin3a_ep>; + hsync-active = <1>; + pclk-sample = <1>; + vsync-active = <1>; + bus-width = <8>; + }; + }; + }; +}; + +&vin3a { + vin3a_ep: endpoint { + remote-endpoint = <&cam>; + hsync-active = <1>; + pclk-sample = <1>; + vsync-active = <1>; + }; +}; + +&gpio6 { + p11 { + gpio-hog; + gpios = <11 GPIO_ACTIVE_LOW>; + line-name = "cm-camen-gpio"; + output-high; + }; +}; Index: linux-6.1.80/arch/arm/configs/lpae.config =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm/configs/lpae.config @@ -0,0 +1,2 @@ +CONFIG_ARM_LPAE=y +CONFIG_VMSPLIT_2G=y Index: linux-6.1.80/arch/arm/configs/multi_v7_defconfig =================================================================== --- linux-6.1.80.orig/arch/arm/configs/multi_v7_defconfig +++ linux-6.1.80/arch/arm/configs/multi_v7_defconfig @@ -1,10 +1,18 @@ +CONFIG_XFRM_USER=m CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y CONFIG_CGROUPS=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_BSD_PROCESS_ACCT=y CONFIG_BLK_DEV_INITRD=y CONFIG_EMBEDDED=y CONFIG_PERF_EVENTS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y CONFIG_ARCH_VIRT=y CONFIG_ARCH_AIROHA=y CONFIG_ARCH_ACTIONS=y @@ -142,6 +150,7 @@ CONFIG_CRYPTO_AES_ARM_CE=m CONFIG_CRYPTO_GHASH_ARM_CE=m CONFIG_CRYPTO_CRC32_ARM_CE=m CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_XCBC=m CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y @@ -150,6 +159,7 @@ CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y +CONFIG_INET_ESP=m CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y @@ -174,6 +184,7 @@ CONFIG_BT_MRVL_SDIO=m CONFIG_BT_QCOMSMD=m CONFIG_CFG80211=m CONFIG_MAC80211=m +CONFIG_IWLWIFI=m CONFIG_RFKILL=y CONFIG_RFKILL_INPUT=y CONFIG_RFKILL_GPIO=y @@ -236,19 +247,21 @@ CONFIG_QCOM_COINCELL=m CONFIG_QCOM_FASTRPC=m CONFIG_APDS9802ALS=y CONFIG_ISL29003=y +CONFIG_SRAM_DMA_HEAP=y CONFIG_PCI_ENDPOINT_TEST=m CONFIG_EEPROM_AT24=y CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y CONFIG_ATA=y -CONFIG_SATA_AHCI=y -CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_SATA_AHCI=m +CONFIG_SATA_AHCI_PLATFORM=m CONFIG_AHCI_BRCM=y CONFIG_AHCI_DM816=y CONFIG_AHCI_ST=y CONFIG_AHCI_IMX=y CONFIG_AHCI_SUNXI=y CONFIG_AHCI_TEGRA=y +CONFIG_AHCI_DWC=m CONFIG_SATA_HIGHBANK=y CONFIG_SATA_MV=y CONFIG_SATA_RCAR=y @@ -325,10 +338,13 @@ CONFIG_MOUSE_PS2_ELANTECH=y CONFIG_MOUSE_CYAPA=m CONFIG_MOUSE_ELAN_I2C=y CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_EDT_FT5X06=y CONFIG_TOUCHSCREEN_ADC=m CONFIG_TOUCHSCREEN_ATMEL_MXT=m CONFIG_TOUCHSCREEN_ELAN=m CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m +CONFIG_TOUCHSCREEN_PIXCIR=m CONFIG_TOUCHSCREEN_WM97XX=m CONFIG_TOUCHSCREEN_ST1232=m CONFIG_TOUCHSCREEN_STMPE=y @@ -357,6 +373,7 @@ CONFIG_SERIAL_8250_EM=y CONFIG_SERIAL_8250_OMAP=y CONFIG_SERIAL_8250_MT6577=y CONFIG_SERIAL_8250_UNIPHIER=y +CONFIG_SERIAL_8250_PRUSS=m CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y @@ -531,6 +548,9 @@ CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_RASPBERRYPI_HWMON=m CONFIG_SENSORS_INA2XX=m CONFIG_CPU_THERMAL=y +CONFIG_TI_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_DRA752_THERMAL=y CONFIG_DEVFREQ_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_ROCKCHIP_THERMAL=y @@ -552,6 +572,7 @@ CONFIG_AT91SAM9X_WATCHDOG=y CONFIG_SAMA5D4_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=m CONFIG_DW_WATCHDOG=y +CONFIG_OMAP_WATCHDOG=m CONFIG_DAVINCI_WATCHDOG=m CONFIG_ORION_WATCHDOG=y CONFIG_RN5T618_WATCHDOG=y @@ -598,6 +619,7 @@ CONFIG_MFD_RK808=y CONFIG_MFD_RN5T618=y CONFIG_MFD_SEC_CORE=y CONFIG_MFD_STMPE=y +CONFIG_MFD_TI_AM335X_TSCADC=m CONFIG_MFD_PALMAS=y CONFIG_MFD_TPS65090=y CONFIG_MFD_TPS65217=y @@ -660,6 +682,8 @@ CONFIG_CEC_STM32=m CONFIG_MEDIA_SUPPORT=m CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_TI_VIP=m +CONFIG_VIDEO_TI_VPE=m CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_ASPEED=m @@ -688,6 +712,7 @@ CONFIG_VIDEO_STI_HVA=m CONFIG_VIDEO_STM32_DCMI=m CONFIG_V4L_TEST_DRIVERS=y CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_OV1063X=m CONFIG_VIDEO_ADV7180=m CONFIG_VIDEO_ADV7604=m CONFIG_VIDEO_ADV7604_CEC=y @@ -712,6 +737,9 @@ CONFIG_ROCKCHIP_INNO_HDMI=y CONFIG_DRM_ATMEL_HLCDC=m CONFIG_DRM_RCAR_DU=m CONFIG_DRM_SUN4I=m +CONFIG_DRM_OMAP=m +CONFIG_OMAP5_DSS_HDMI=y +CONFIG_DRM_TILCDC=m CONFIG_DRM_MSM=m CONFIG_DRM_FSL_DCU=m CONFIG_DRM_TEGRA=y @@ -720,6 +748,7 @@ CONFIG_DRM_STM_DSI=m CONFIG_DRM_PANEL_LVDS=m CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y +CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=y CONFIG_DRM_PANEL_SAMSUNG_LD9040=m CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m CONFIG_DRM_PANEL_RAYDIUM_RM68200=m @@ -735,6 +764,8 @@ CONFIG_DRM_SII9234=m CONFIG_DRM_SIMPLE_BRIDGE=m CONFIG_DRM_TOSHIBA_TC358764=m CONFIG_DRM_TOSHIBA_TC358768=m +CONFIG_DRM_TI_TFP410=m +CONFIG_DRM_TI_TPD12S015=m CONFIG_DRM_I2C_ADV7511=m CONFIG_DRM_I2C_ADV7511_AUDIO=y CONFIG_DRM_STI=m @@ -763,6 +794,7 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y CONFIG_SOUND=m CONFIG_SND=m +CONFIG_SND_SOC_OMAP_HDMI=m CONFIG_SND_HDA_TEGRA=m CONFIG_SND_HDA_INPUT_BEEP=y CONFIG_SND_HDA_PATCH_LOADER=y @@ -821,6 +853,7 @@ CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m CONFIG_SND_SOC_SGTL5000=m CONFIG_SND_SOC_STI_SAS=m +CONFIG_SND_SOC_TLV320AIC3X_I2C=m CONFIG_SND_SOC_WM8978=m CONFIG_SND_AUDIO_GRAPH_CARD=m CONFIG_USB=y @@ -851,7 +884,8 @@ CONFIG_USB_UX500_DMA=y CONFIG_USB_INVENTRA_DMA=y CONFIG_USB_TI_CPPI41_DMA=y CONFIG_USB_TUSB_OMAP_DMA=y -CONFIG_USB_DWC3=y +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_DUAL_ROLE=y CONFIG_USB_DWC2=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y @@ -868,6 +902,14 @@ CONFIG_USB_GPIO_VBUS=y CONFIG_USB_ISP1301=y CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y +CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_CDC=y +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=32 +CONFIG_USB_ZERO=m CONFIG_USB_RENESAS_USBHS_UDC=m CONFIG_USB_ASPEED_VHUB=m CONFIG_USB_CONFIGFS=m @@ -890,6 +932,7 @@ CONFIG_USB_CONFIGFS_F_HID=y CONFIG_USB_CONFIGFS_F_UVC=y CONFIG_USB_CONFIGFS_F_PRINTER=y CONFIG_USB_ETH=m +CONFIG_USB_CDC_COMPOSITE=m CONFIG_TYPEC=m CONFIG_TYPEC_STUSB160X=m CONFIG_MMC=y @@ -965,7 +1008,7 @@ CONFIG_RTC_DRV_BQ32K=m CONFIG_RTC_DRV_TWL4030=y CONFIG_RTC_DRV_PALMAS=y CONFIG_RTC_DRV_TPS6586X=y -CONFIG_RTC_DRV_TPS65910=y +CONFIG_RTC_DRV_TPS65910=m CONFIG_RTC_DRV_S35390A=m CONFIG_RTC_DRV_RX8581=m CONFIG_RTC_DRV_EM3027=y @@ -973,6 +1016,7 @@ CONFIG_RTC_DRV_S5M=m CONFIG_RTC_DRV_DA9063=m CONFIG_RTC_DRV_EFI=m CONFIG_RTC_DRV_DIGICOLOR=m +CONFIG_RTC_DRV_OMAP=m CONFIG_RTC_DRV_S3C=m CONFIG_RTC_DRV_SA1100=m CONFIG_RTC_DRV_SH=m @@ -1012,6 +1056,10 @@ CONFIG_QCOM_BAM_DMA=y CONFIG_DW_DMAC=y CONFIG_RCAR_DMAC=y CONFIG_RENESAS_USB_DMAC=m +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_DMABUF_HEAPS_CARVEOUT=y CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_MMIO=y CONFIG_STAGING=y @@ -1046,6 +1094,7 @@ CONFIG_HWSPINLOCK_QCOM=y CONFIG_BCM2835_MBOX=y CONFIG_QCOM_APCS_IPC=y CONFIG_QCOM_IPCC=y +CONFIG_OMAP_IOMMU=y CONFIG_ROCKCHIP_IOMMU=y CONFIG_TEGRA_IOMMU_GART=y CONFIG_TEGRA_IOMMU_SMMU=y @@ -1056,6 +1105,9 @@ CONFIG_QCOM_Q6V5_MSS=m CONFIG_QCOM_SYSMON=m CONFIG_QCOM_WCNSS_PIL=m CONFIG_ST_REMOTEPROC=m +CONFIG_OMAP_REMOTEPROC=m +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_CTRL=m CONFIG_RPMSG_QCOM_SMD=y CONFIG_RPMSG_VIRTIO=m CONFIG_ASPEED_LPC_CTRL=m @@ -1102,9 +1154,16 @@ CONFIG_ARCH_TEGRA_2x_SOC=y CONFIG_ARCH_TEGRA_3x_SOC=y CONFIG_ARCH_TEGRA_114_SOC=y CONFIG_ARCH_TEGRA_124_SOC=y +CONFIG_SOC_TI=y +CONFIG_TI_PRUSS=m +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_DPM_WATCHDOG=y CONFIG_ARM_EXYNOS_BUS_DEVFREQ=m CONFIG_ARM_TEGRA_DEVFREQ=m CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=m +CONFIG_EXTCON_PALMAS=m CONFIG_EXTCON_MAX14577=m CONFIG_EXTCON_MAX77693=m CONFIG_EXTCON_MAX8997=m @@ -1127,6 +1186,7 @@ CONFIG_STM32_ADC_CORE=m CONFIG_STM32_ADC=m CONFIG_STM32_DFSDM_ADC=m CONFIG_STMPE_ADC=m +CONFIG_TI_AM335X_ADC=m CONFIG_VF610_ADC=m CONFIG_XILINX_XADC=y CONFIG_IIO_CROS_EC_SENSORS_CORE=m @@ -1147,6 +1207,8 @@ CONFIG_PWM_ATMEL_TCB=m CONFIG_PWM_BCM2835=y CONFIG_PWM_BRCMSTB=m CONFIG_PWM_FSL_FTM=m +CONFIG_PWM_TIECAP=m +CONFIG_PWM_TIEHRPWM=m CONFIG_PWM_MESON=m CONFIG_PWM_RCAR=m CONFIG_PWM_RENESAS_TPU=y @@ -1206,6 +1268,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8916=y CONFIG_COUNTER=m CONFIG_STM32_TIMER_CNT=m CONFIG_STM32_LPTIMER_CNT=m +CONFIG_FANOTIFY=y CONFIG_EXT4_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y @@ -1248,7 +1311,14 @@ CONFIG_CRYPTO_DEV_ROCKCHIP=m CONFIG_CRYPTO_DEV_STM32_CRC=m CONFIG_CRYPTO_DEV_STM32_HASH=m CONFIG_CRYPTO_DEV_STM32_CRYP=m +CONFIG_CRYPTO_DEV_OMAP=m +CONFIG_CRYPTO_DEV_OMAP_SHAM=m +CONFIG_CRYPTO_DEV_OMAP_AES=m +CONFIG_CRYPTO_DEV_OMAP_DES=m CONFIG_CMA_SIZE_MBYTES=64 CONFIG_PRINTK_TIME=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y +CONFIG_SPI_TI_QSPI=y +CONFIG_CAN_C_CAN=m +CONFIG_CAN_C_CAN_PLATFORM=m Index: linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree fragment for LS1028A QDS board, serdes 13bb - * - * Copyright 2019-2021 NXP - * - * Requires a LS1028A QDS board with lane B rework. - * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C. - * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2. - */ - -/dts-v1/; -/plugin/; - -&mdio_slot1 { - #address-cells = <1>; - #size-cells = <0>; - - slot1_sgmii: ethernet-phy@2 { - /* AQR112 */ - reg = <0x2>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; -}; - -&enetc_port0 { - phy-handle = <&slot1_sgmii>; - phy-mode = "usxgmii"; - managed = "in-band-status"; - status = "okay"; -}; - -&mdio_slot2 { - #address-cells = <1>; - #size-cells = <0>; - - /* 4 ports on AQR412 */ - slot2_qxgmii0: ethernet-phy@0 { - reg = <0x0>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - slot2_qxgmii1: ethernet-phy@1 { - reg = <0x1>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - slot2_qxgmii2: ethernet-phy@2 { - reg = <0x2>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - slot2_qxgmii3: ethernet-phy@3 { - reg = <0x3>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; -}; - -&mscc_felix_ports { - port@0 { - status = "okay"; - phy-handle = <&slot2_qxgmii0>; - phy-mode = "usxgmii"; - managed = "in-band-status"; - }; - - port@1 { - status = "okay"; - phy-handle = <&slot2_qxgmii1>; - phy-mode = "usxgmii"; - managed = "in-band-status"; - }; - - port@2 { - status = "okay"; - phy-handle = <&slot2_qxgmii2>; - phy-mode = "usxgmii"; - managed = "in-band-status"; - }; - - port@3 { - status = "okay"; - phy-handle = <&slot2_qxgmii3>; - phy-mode = "usxgmii"; - managed = "in-band-status"; - }; -}; - -&mscc_felix { - status = "okay"; -}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 13bb + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C. + * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2. + */ + +/dts-v1/; +/plugin/; + +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; +}; + +&enetc_port0 { + phy-handle = <&slot1_sgmii>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + status = "okay"; +}; + +&mdio_slot2 { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on AQR412 */ + slot2_qxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; +}; + +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&slot2_qxgmii0>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qxgmii1>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qxgmii2>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qxgmii3>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; +}; + +&mscc_felix { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree fragment for LS1028A QDS board, serdes 69xx - * - * Copyright 2019-2021 NXP - * - * Requires a LS1028A QDS board with lane B rework. - * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2. - */ - -/dts-v1/; -/plugin/; - -&mdio_slot1 { - #address-cells = <1>; - #size-cells = <0>; - - slot1_sgmii: ethernet-phy@2 { - /* AQR112 */ - reg = <0x2>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; -}; - -&enetc_port0 { - phy-handle = <&slot1_sgmii>; - phy-mode = "2500base-x"; - status = "okay"; -}; - -&mdio_slot2 { - #address-cells = <1>; - #size-cells = <0>; - - /* 4 ports on VSC8514 */ - slot2_qsgmii0: ethernet-phy@8 { - reg = <0x8>; - }; - - slot2_qsgmii1: ethernet-phy@9 { - reg = <0x9>; - }; - - slot2_qsgmii2: ethernet-phy@a { - reg = <0xa>; - }; - - slot2_qsgmii3: ethernet-phy@b { - reg = <0xb>; - }; -}; - -&mscc_felix_ports { - port@0 { - status = "okay"; - phy-handle = <&slot2_qsgmii0>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - - port@1 { - status = "okay"; - phy-handle = <&slot2_qsgmii1>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - - port@2 { - status = "okay"; - phy-handle = <&slot2_qsgmii2>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - - port@3 { - status = "okay"; - phy-handle = <&slot2_qsgmii3>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; -}; - -&mscc_felix { - status = "okay"; -}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 69xx + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2. + */ + +/dts-v1/; +/plugin/; + +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; +}; + +&enetc_port0 { + phy-handle = <&slot1_sgmii>; + phy-mode = "2500base-x"; + status = "okay"; +}; + +&mdio_slot2 { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; + }; + + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; + + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; + + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; +}; + +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; +}; + +&mscc_felix { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree fragment for LS1028A QDS board, serdes 7777 - * - * Copyright 2019-2021 NXP - * - * Requires a LS1028A QDS board without lane B rework. - * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing - * disabled, plugged in slot 1. - */ - -/dts-v1/; -/plugin/; - -&mdio_slot1 { - #address-cells = <1>; - #size-cells = <0>; - - /* 4 ports on AQR412 */ - slot1_sxgmii0: ethernet-phy@0 { - reg = <0x0>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - slot1_sxgmii1: ethernet-phy@1 { - reg = <0x1>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - slot1_sxgmii2: ethernet-phy@2 { - reg = <0x2>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - slot1_sxgmii3: ethernet-phy@3 { - reg = <0x3>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; -}; - -&mscc_felix_ports { - port@0 { - status = "okay"; - phy-handle = <&slot1_sxgmii0>; - phy-mode = "2500base-x"; - }; - - port@1 { - status = "okay"; - phy-handle = <&slot1_sxgmii1>; - phy-mode = "2500base-x"; - }; - - port@2 { - status = "okay"; - phy-handle = <&slot1_sxgmii2>; - phy-mode = "2500base-x"; - }; - - port@3 { - status = "okay"; - phy-handle = <&slot1_sxgmii3>; - phy-mode = "2500base-x"; - }; -}; - -&mscc_felix { - status = "okay"; -}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 7777 + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing + * disabled, plugged in slot 1. + */ + +/dts-v1/; +/plugin/; + +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on AQR412 */ + slot1_sxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; +}; + +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&slot1_sxgmii0>; + phy-mode = "2500base-x"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot1_sxgmii1>; + phy-mode = "2500base-x"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sxgmii2>; + phy-mode = "2500base-x"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot1_sxgmii3>; + phy-mode = "2500base-x"; + }; +}; + +&mscc_felix { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree fragment for LS1028A QDS board, serdes 85bb - * - * Copyright 2019-2021 NXP - * - * Requires a LS1028A QDS board with lane B rework. - * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2. - */ - -/dts-v1/; -/plugin/; - -&mdio_slot1 { - #address-cells = <1>; - #size-cells = <0>; - - slot1_sgmii: ethernet-phy@1c { - /* 1st port on VSC8234 */ - reg = <0x1c>; - }; -}; - -&enetc_port0 { - phy-handle = <&slot1_sgmii>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "okay"; -}; - -&mdio_slot2 { - #address-cells = <1>; - #size-cells = <0>; - - /* 4 ports on VSC8514 */ - slot2_qsgmii0: ethernet-phy@8 { - reg = <0x8>; - }; - - slot2_qsgmii1: ethernet-phy@9 { - reg = <0x9>; - }; - - slot2_qsgmii2: ethernet-phy@a { - reg = <0xa>; - }; - - slot2_qsgmii3: ethernet-phy@b { - reg = <0xb>; - }; -}; - -&mscc_felix_ports { - port@0 { - status = "okay"; - phy-handle = <&slot2_qsgmii0>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - - port@1 { - status = "okay"; - phy-handle = <&slot2_qsgmii1>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - - port@2 { - status = "okay"; - phy-handle = <&slot2_qsgmii2>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - - port@3 { - status = "okay"; - phy-handle = <&slot2_qsgmii3>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; -}; - -&mscc_felix { - status = "okay"; -}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85bb + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2. + */ + +/dts-v1/; +/plugin/; + +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@1c { + /* 1st port on VSC8234 */ + reg = <0x1c>; + }; +}; + +&enetc_port0 { + phy-handle = <&slot1_sgmii>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; + +&mdio_slot2 { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; + }; + + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; + + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; + + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; +}; + +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; +}; + +&mscc_felix { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree fragment for LS1028A QDS board, serdes 85xx - * - * Copyright 2019-2021 NXP - * - * Requires a LS1028A QDS board without lane B rework. - * Requires a SCH-24801 card in slot 1. - */ - -/dts-v1/; -/plugin/; - -&mdio_slot1 { - #address-cells = <1>; - #size-cells = <0>; - - /* VSC8234 */ - slot1_sgmii0: ethernet-phy@1c { - reg = <0x1c>; - }; - - slot1_sgmii1: ethernet-phy@1d { - reg = <0x1d>; - }; - - slot1_sgmii2: ethernet-phy@1e { - reg = <0x1e>; - }; - - slot1_sgmii3: ethernet-phy@1f { - reg = <0x1f>; - }; -}; - -&enetc_port0 { - phy-handle = <&slot1_sgmii0>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "okay"; -}; - -&mscc_felix_ports { - port@1 { - status = "okay"; - phy-handle = <&slot1_sgmii1>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; - - port@2 { - status = "okay"; - phy-handle = <&slot1_sgmii2>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; -}; - -&mscc_felix { - status = "okay"; -}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85xx + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-24801 card in slot 1. + */ + +/dts-v1/; +/plugin/; + +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; + + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; + }; + + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; + }; + + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; + }; + + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; + }; +}; + +&enetc_port0 { + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; + +&mscc_felix_ports { + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; +}; + +&mscc_felix { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree fragment for LS1028A QDS board, serdes 85xx - * - * Copyright 2019-2021 NXP - * - * Requires a LS1028A QDS board without lane B rework. - * Requires a SCH-24801 card in slot 1. - */ - -/dts-v1/; -/plugin/; - -&mdio_slot1 { - #address-cells = <1>; - #size-cells = <0>; - - /* VSC8234 */ - slot1_sgmii0: ethernet-phy@1c { - reg = <0x1c>; - }; - - slot1_sgmii1: ethernet-phy@1d { - reg = <0x1d>; - }; - - slot1_sgmii2: ethernet-phy@1e { - reg = <0x1e>; - }; - - slot1_sgmii3: ethernet-phy@1f { - reg = <0x1f>; - }; -}; - -&mscc_felix_ports { - port@0 { - status = "okay"; - phy-handle = <&slot1_sgmii0>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; - - port@1 { - status = "okay"; - phy-handle = <&slot1_sgmii1>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; - - port@2 { - status = "okay"; - phy-handle = <&slot1_sgmii2>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; - - port@3 { - status = "okay"; - phy-handle = <&slot1_sgmii3>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; -}; - -&mscc_felix { - status = "okay"; -}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85xx + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-24801 card in slot 1. + */ + +/dts-v1/; +/plugin/; + +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; + + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; + }; + + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; + }; + + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; + }; + + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; + }; +}; + +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot1_sgmii3>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; +}; + +&mscc_felix { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Gateworks Corporation - */ - -#include - -#include "imx8mm-pinfunc.h" - -/dts-v1/; -/plugin/; - -&{/} { - compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm"; - - reg_cam: regulator-cam { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_cam>; - compatible = "regulator-fixed"; - regulator-name = "reg_cam"; - gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - cam24m: cam24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "cam24m"; - }; -}; - -&csi { - status = "okay"; -}; - -&i2c3 { - #address-cells = <1>; - #size-cells = <0>; - - imx219: sensor@10 { - compatible = "sony,imx219"; - reg = <0x10>; - clocks = <&cam24m>; - VDIG-supply = <®_cam>; - - port { - /* MIPI CSI-2 bus endpoint */ - imx219_to_mipi_csi2: endpoint { - remote-endpoint = <&imx8mm_mipi_csi_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - link-frequencies = /bits/ 64 <456000000>; - }; - }; - }; -}; - -&mipi_csi { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - imx8mm_mipi_csi_in: endpoint { - remote-endpoint = <&imx219_to_mipi_csi2>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - - imx8mm_mipi_csi_out: endpoint { - remote-endpoint = <&csi_in>; - }; - }; - }; -}; - -&iomuxc { - pinctrl_reg_cam: regcamgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41 - >; - }; -}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm"; + + reg_cam: regulator-cam { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_cam>; + compatible = "regulator-fixed"; + regulator-name = "reg_cam"; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + cam24m: cam24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "cam24m"; + }; +}; + +&csi { + status = "okay"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + imx219: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&cam24m>; + VDIG-supply = <®_cam>; + + port { + /* MIPI CSI-2 bus endpoint */ + imx219_to_mipi_csi2: endpoint { + remote-endpoint = <&imx8mm_mipi_csi_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; +}; + +&mipi_csi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + imx8mm_mipi_csi_in: endpoint { + remote-endpoint = <&imx219_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + + imx8mm_mipi_csi_out: endpoint { + remote-endpoint = <&csi_in>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_reg_cam: regcamgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41 + >; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Gateworks Corporation - * - * GW72xx RS232 with RTS/CTS hardware flow control: - * - GPIO4_0 rs485_en needs to be driven low (in-active) - * - UART4_TX becomes RTS - * - UART4_RX becomes CTS - */ - -#include - -#include "imx8mm-pinfunc.h" - -/dts-v1/; -/plugin/; - -&{/} { - compatible = "gw,imx8mm-gw72xx-0x"; -}; - -&gpio4 { - rs485_en { - gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "rs485_en"; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uart4 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 - MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140 - >; - }; -}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + * + * GW72xx RS232 with RTS/CTS hardware flow control: + * - GPIO4_0 rs485_en needs to be driven low (in-active) + * - UART4_TX becomes RTS + * - UART4_RX becomes CTS + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw72xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rs485_en"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140 + >; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Gateworks Corporation - * - * GW72xx RS422 (RS485 full duplex): - * - GPIO1_0 rs485_term selects on-chip termination - * - GPIO4_0 rs485_en needs to be driven high (active) - * - GPIO4_2 rs485_hd needs to be driven low (in-active) - * - UART4_TX is DE for RS485 transmitter - * - RS485_EN needs to be pulled high - * - RS485_HALF needs to be low - */ - -#include - -#include "imx8mm-pinfunc.h" - -/dts-v1/; -/plugin/; - -&{/} { - compatible = "gw,imx8mm-gw72xx-0x"; -}; - -&gpio4 { - rs485_en { - gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "rs485_en"; - }; - - rs485_hd { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "rs485_hd"; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - linux,rs485-enabled-at-boot-time; - status = "okay"; -}; - -&uart4 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 - >; - }; -}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + * + * GW72xx RS422 (RS485 full duplex): + * - GPIO1_0 rs485_term selects on-chip termination + * - GPIO4_0 rs485_en needs to be driven high (active) + * - GPIO4_2 rs485_hd needs to be driven low (in-active) + * - UART4_TX is DE for RS485 transmitter + * - RS485_EN needs to be pulled high + * - RS485_HALF needs to be low + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw72xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_en"; + }; + + rs485_hd { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rs485_hd"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + >; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Gateworks Corporation - * - * GW72xx RS485 HD: - * - GPIO1_0 rs485_term selects on-chip termination - * - GPIO4_0 rs485_en needs to be driven high (active) - * - GPIO4_2 rs485_hd needs to be driven high (active) - * - UART4_TX is DE for RS485 transmitter - * - RS485_EN needs to be pulled high - * - RS485_HALF needs to be pulled high - */ - -#include - -#include "imx8mm-pinfunc.h" - -/dts-v1/; -/plugin/; - -&{/} { - compatible = "gw,imx8mm-gw72xx-0x"; -}; - -&gpio4 { - rs485_en { - gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "rs485_en"; - }; - - rs485_hd { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "rs485_hd"; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - linux,rs485-enabled-at-boot-time; - status = "okay"; -}; - -&uart4 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 - >; - }; -}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + * + * GW72xx RS485 HD: + * - GPIO1_0 rs485_term selects on-chip termination + * - GPIO4_0 rs485_en needs to be driven high (active) + * - GPIO4_2 rs485_hd needs to be driven high (active) + * - UART4_TX is DE for RS485 transmitter + * - RS485_EN needs to be pulled high + * - RS485_HALF needs to be pulled high + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw72xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_en"; + }; + + rs485_hd { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_hd"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + >; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Gateworks Corporation - */ - -#include - -#include "imx8mm-pinfunc.h" - -/dts-v1/; -/plugin/; - -&{/} { - compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm"; - - reg_cam: regulator-cam { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_cam>; - compatible = "regulator-fixed"; - regulator-name = "reg_cam"; - gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - cam24m: cam24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "cam24m"; - }; -}; - -&csi { - status = "okay"; -}; - -&i2c3 { - #address-cells = <1>; - #size-cells = <0>; - - imx219: sensor@10 { - compatible = "sony,imx219"; - reg = <0x10>; - clocks = <&cam24m>; - VDIG-supply = <®_cam>; - - port { - /* MIPI CSI-2 bus endpoint */ - imx219_to_mipi_csi2: endpoint { - remote-endpoint = <&imx8mm_mipi_csi_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - link-frequencies = /bits/ 64 <456000000>; - }; - }; - }; -}; - -&mipi_csi { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - imx8mm_mipi_csi_in: endpoint { - remote-endpoint = <&imx219_to_mipi_csi2>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - - imx8mm_mipi_csi_out: endpoint { - remote-endpoint = <&csi_in>; - }; - }; - }; -}; - -&iomuxc { - pinctrl_reg_cam: regcamgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41 - >; - }; -}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm"; + + reg_cam: regulator-cam { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_cam>; + compatible = "regulator-fixed"; + regulator-name = "reg_cam"; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + cam24m: cam24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "cam24m"; + }; +}; + +&csi { + status = "okay"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + imx219: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&cam24m>; + VDIG-supply = <®_cam>; + + port { + /* MIPI CSI-2 bus endpoint */ + imx219_to_mipi_csi2: endpoint { + remote-endpoint = <&imx8mm_mipi_csi_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; +}; + +&mipi_csi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + imx8mm_mipi_csi_in: endpoint { + remote-endpoint = <&imx219_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + + imx8mm_mipi_csi_out: endpoint { + remote-endpoint = <&csi_in>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_reg_cam: regcamgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41 + >; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Gateworks Corporation - * - * GW73xx RS232 with RTS/CTS hardware flow control: - * - GPIO4_0 rs485_en needs to be driven low (in-active) - * - UART4_TX becomes RTS - * - UART4_RX becomes CTS - */ - -#include - -#include "imx8mm-pinfunc.h" - -/dts-v1/; -/plugin/; - -&{/} { - compatible = "gw,imx8mm-gw73xx-0x"; -}; - -&gpio4 { - rs485_en { - gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "rs485_en"; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uart4 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 - MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140 - >; - }; -}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + * + * GW73xx RS232 with RTS/CTS hardware flow control: + * - GPIO4_0 rs485_en needs to be driven low (in-active) + * - UART4_TX becomes RTS + * - UART4_RX becomes CTS + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw73xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rs485_en"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140 + >; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2021 Gateworks Corporation - * - * GW73xx RS422 (RS485 full duplex): - * - GPIO1_0 rs485_term selects on-chip termination - * - GPIO4_0 rs485_en needs to be driven high (active) - * - GPIO4_2 rs485_hd needs to be driven low (in-active) - * - UART4_TX is DE for RS485 transmitter - * - RS485_EN needs to be pulled high - * - RS485_HALF needs to be low - */ - -#include - -#include "imx8mm-pinfunc.h" - -/dts-v1/; -/plugin/; - -&{/} { - compatible = "gw,imx8mm-gw73xx-0x"; -}; - -&gpio4 { - rs485_en { - gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "rs485_en"; - }; - - rs485_hd { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "rs485_hd"; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - linux,rs485-enabled-at-boot-time; - status = "okay"; -}; - -&uart4 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 - >; - }; -}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Gateworks Corporation + * + * GW73xx RS422 (RS485 full duplex): + * - GPIO1_0 rs485_term selects on-chip termination + * - GPIO4_0 rs485_en needs to be driven high (active) + * - GPIO4_2 rs485_hd needs to be driven low (in-active) + * - UART4_TX is DE for RS485 transmitter + * - RS485_EN needs to be pulled high + * - RS485_HALF needs to be low + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw73xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_en"; + }; + + rs485_hd { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rs485_hd"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + >; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2021 Gateworks Corporation - * - * GW73xx RS485 HD: - * - GPIO1_0 rs485_term selects on-chip termination - * - GPIO4_0 rs485_en needs to be driven high (active) - * - GPIO4_2 rs485_hd needs to be driven high (active) - * - UART4_TX is DE for RS485 transmitter - * - RS485_EN needs to be pulled high - * - RS485_HALF needs to be pulled high - */ - -#include - -#include "imx8mm-pinfunc.h" - -/dts-v1/; -/plugin/; - -&{/} { - compatible = "gw,imx8mm-gw73xx-0x"; -}; - -&gpio4 { - rs485_en { - gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "rs485_en"; - }; - - rs485_hd { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "rs485_hd"; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - linux,rs485-enabled-at-boot-time; - status = "okay"; -}; - -&uart4 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 - >; - }; -}; Index: linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Gateworks Corporation + * + * GW73xx RS485 HD: + * - GPIO1_0 rs485_term selects on-chip termination + * - GPIO4_0 rs485_en needs to be driven high (active) + * - GPIO4_2 rs485_hd needs to be driven high (active) + * - UART4_TX is DE for RS485 transmitter + * - RS485_EN needs to be pulled high + * - RS485_HALF needs to be pulled high + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw73xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_en"; + }; + + rs485_hd { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_hd"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + >; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree overlay for the AA104XD12 panel connected to LVDS1 on a Draak or - * Ebisu board - * - * Copyright 2021 Ideas on Board Oy - */ - -/dts-v1/; -/plugin/; - -&{/} { -#include "panel-aa104xd12.dtsi" -}; - -&{/panel} { - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds1_out>; - }; - }; -}; - -&lvds1 { - status = "okay"; - - ports { - port@1 { - lvds1_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; Index: linux-6.1.80/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree overlay for the AA104XD12 panel connected to LVDS1 on a Draak or + * Ebisu board + * + * Copyright 2021 Ideas on Board Oy + */ + +/dts-v1/; +/plugin/; + +&{/} { +#include "panel-aa104xd12.dtsi" +}; + +&{/panel} { + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; +}; + +&lvds1 { + status = "okay"; + + ports { + port@1 { + lvds1_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree overlay for the AA104XD12 panel connected to LVDS0 on a - * Salvator-X or Salvator-XS board - * - * Copyright 2021 Ideas on Board Oy - */ - -/dts-v1/; -/plugin/; - -&{/} { -#include "panel-aa104xd12.dtsi" -}; - -&{/panel} { - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; Index: linux-6.1.80/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree overlay for the AA104XD12 panel connected to LVDS0 on a + * Salvator-X or Salvator-XS board + * + * Copyright 2021 Ideas on Board Oy + */ + +/dts-v1/; +/plugin/; + +&{/} { +#include "panel-aa104xd12.dtsi" +}; + +&{/panel} { + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/Makefile =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/Makefile +++ linux-6.1.80/arch/arm64/boot/dts/ti/Makefile @@ -5,23 +5,199 @@ # # Copyright (C) 2016-2021 Texas Instruments Incorporated - https://www.ti.com/ # +# Entries are grouped as per SoC present on the board. Groups are sorted +# alphabetically. -dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb +# Boards with AM62x SoC +dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-tevi-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-lincolntech-lcd185-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-lincolntech-lcd185-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-microtips-mf101hie-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-microtips-mf103hie-lcd2.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-dmtimer-pwm.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-ecap-capture.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-lincolntech-lcd185-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-microtips-mf101hie-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-pwm.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-rpi-hdr-ehrpwm.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-mcspi-loopback.dtbo + +# Boards with AM62Ax SoC +k3-am62a7-sk-csi2-imx219-dtbs := k3-am62a7-sk.dtb k3-am62x-sk-csi2-imx219.dtbo +k3-am62a7-sk-fusion-imx390-dtbs := k3-am62a7-sk.dtb \ + k3-am62a7-sk-fusion.dtbo \ + k3-fpdlink-imx390-rcm-0-0.dtbo +k3-am62a7-sk-fusion-ov2312-dtbs := k3-am62a7-sk.dtb \ + k3-am62a7-sk-fusion.dtbo \ + k3-fpdlink-ov2312-0-0.dtbo +k3-am62a7-sk-ub954-evm-ov2312-dtbs := k3-am62a7-sk.dtb \ + k3-am62a7-sk-ub954-evm.dtbo \ + k3-fpdlink-ov2312-0-0.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-csi2-imx219.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-csi2-ox05b1s.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-e3-max-opp.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-ethernet-dc01.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-fusion-imx390.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-fusion-ov2312.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-rpi-hdr-ehrpwm.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-ub954-evm-ov2312.dtb + +# Boards with AM62Px SoC +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-dsi-rpi-7inch-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-eqep.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-mcan.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-microtips-mf101hie-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-microtips-mf103hie-lcd2.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-dss-shared-mode.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk-rpi-hdr-ehrpwm.dtbo + +# Boards with AM64x SoC +dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac-mii.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-nand.dtbo + +# Boards with AM65x SoC dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb - -dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am654-evm-oldi-lcd1evm.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am654-pcie-usb3.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am654-pcie-usb2.dtbo + +# Boards with J7200 SoC +k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm-mcspi-loopback.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm-virt-mac-client.dtbo + +# Boards with J721e SoC +k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64-dsi-rpi-7inch-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-csi2-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-virt-mac-client.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb - -dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb - +dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-rpi-imx219.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-rpi-hdr-ehrpwm.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board-infotainment.dtbo + +# Boards with J721s2 SoC +dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-bb-csi2-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-bb-rpi-cam-imx219.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-fpdlink-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-rpi-hdr-ehrpwm.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-som-ddr-mem-carveout.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-v3link-fusion.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb - -dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb -dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb - -dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb - -dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-csi2-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo + +# Boards with J722s SoC +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-rpi-cam-imx219.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-tevi-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-dsi-rpi-7inch-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-fpdlink-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-microtips-mf101hie-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-v3link-fusion.dtbo + +# Boards with J784s4 SoC +dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-csi2-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-ddr-mem-carveout.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-csi2-rpi-cam-imx219.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-csi2-v3link-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-fpdlink-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-fpdlink-fusion-auxport.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-rpi-hdr-ehrpwm.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-csi2-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-virt-mac-client.dtbo + +# Common overlays across AM62 family of boards +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-eqep.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-imx219.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-tevi-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-v3link-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-disable-fastboot.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-lpm-wkup-sources.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-mcan.dtbo + +# FPDLink Sensors +dtb-$(CONFIG_ARCH_K3) += k3-fpdlink-imx390-rcm-0-0.dtbo \ + k3-fpdlink-imx390-rcm-0-1.dtbo \ + k3-fpdlink-imx390-rcm-0-2.dtbo \ + k3-fpdlink-imx390-rcm-0-3.dtbo \ + k3-fpdlink-imx390-rcm-1-0.dtbo \ + k3-fpdlink-imx390-rcm-1-1.dtbo \ + k3-fpdlink-imx390-rcm-1-2.dtbo \ + k3-fpdlink-imx390-rcm-1-3.dtbo \ + k3-fpdlink-imx390-rcm-2-0.dtbo \ + k3-fpdlink-imx390-rcm-2-1.dtbo \ + k3-fpdlink-imx390-rcm-2-2.dtbo \ + k3-fpdlink-imx390-rcm-2-3.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-fpdlink-ov2312-0-0.dtbo \ + k3-fpdlink-ov2312-0-1.dtbo \ + k3-fpdlink-ov2312-0-2.dtbo \ + k3-fpdlink-ov2312-0-3.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-v3link-imx219-0-0.dtbo \ + k3-v3link-imx219-0-1.dtbo \ + k3-v3link-imx219-0-2.dtbo \ + k3-v3link-imx219-0-3.dtbo + +#Enable support for device-tree overlays +DTC_FLAGS_k3-am62-lp-sk += -@ +DTC_FLAGS_k3-am625-beagleplay += -@ +DTC_FLAGS_k3-am625-sk += -@ +DTC_FLAGS_k3-am625-sk-lpmdemo += -@ +DTC_FLAGS_k3-am62a7-sk += -@ +DTC_FLAGS_k3-am62a7-sk-fusion += -@ +DTC_FLAGS_k3-am62a7-sk-ub954-evm += -@ +DTC_FLAGS_k3-am62p5-sk += -@ +DTC_FLAGS_k3-am62x-sk-csi2-v3link-fusion += -@ +DTC_FLAGS_k3-am654-base-board += -@ +DTC_FLAGS_k3-am68-sk-base-board += -@ +DTC_FLAGS_k3-am68-sk-fpdlink-fusion += -@ +DTC_FLAGS_k3-am68-sk-v3link-fusion += -@ +DTC_FLAGS_k3-am69-sk += -@ +DTC_FLAGS_k3-am69-sk-csi2-v3link-fusion += -@ +DTC_FLAGS_k3-am69-sk-fpdlink-fusion += -@ +DTC_FLAGS_k3-am69-sk-fpdlink-fusion-auxport += -@ +DTC_FLAGS_k3-j7200-common-proc-board += -@ +DTC_FLAGS_k3-j721e-beagleboneai64 += -@ +DTC_FLAGS_k3-j721e-common-proc-board += -@ +DTC_FLAGS_k3-j721e-evm-fusion += -@ +DTC_FLAGS_k3-j721e-sk += -@ +DTC_FLAGS_k3-j721e-sk-fusion += -@ +DTC_FLAGS_k3-j721s2-common-proc-board += -@ +DTC_FLAGS_k3-j721s2-evm-fusion += -@ +DTC_FLAGS_k3-j722s-evm += -@ +DTC_FLAGS_k3-j722s-evm-fpdlink-fusion += -@ +DTC_FLAGS_k3-j722s-evm-v3link-fusion += -@ +DTC_FLAGS_k3-j784s4-evm += -@ +DTC_FLAGS_k3-am642-evm += -@ Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-lp-sk-lincolntech-lcd185-panel.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-lp-sk-lincolntech-lcd185-panel.dtso @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Lincoln tech Solutions OLDI panel (LCD185-101CT) and touch DT overlay for AM62-LP-SK + * + * AM62-LP SKEVM: https://www.ti.com/tool/SK-AM62-LP + * Panel datasheet: https://lincolntechsolutions.com/wp-content/uploads/2023/04/LCD185-101CTL1ARNTT_DS_R1.3.pdf + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + display { + compatible = "lincolntech,lcd185-101ct"; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * But swapping them will cause an error in the dss driver. + */ + port@0 { + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + port@1 { + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_out1>; + }; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: LVDS Output (OLDI TX 0) */ + port@0 { + reg = <0>; + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; + + /* VP1: LVDS Output (OLDI TX 1) */ + port@2 { + reg = <2>; + oldi_out1: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@57 { + compatible = "atmel,24c256"; + reg = <0x57>; + }; + + touchscreen@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + interrupt-parent = <&exp1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&exp1 15 GPIO_ACTIVE_LOW>; + reset-gpios = <&exp2 18 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1920>; + touchscreen-size-y = <1200>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-lp-sk-microtips-mf101hie-panel.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-lp-sk-microtips-mf101hie-panel.dtso @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Microtips integrated OLDI panel (MF-101HIEBCAF0) and touch DT overlay for AM62 LP-SK + * + * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + display { + compatible = "microtips,mf-101hiebcaf0"; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * Swapping them will not make any difference. + */ + port@0 { + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + port@1 { + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_out1>; + }; + }; + }; +}; + +&main_pmx0 { + main_oldi0_pins_default: main-oldi0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0260, PIN_OUTPUT, 0) /* (AA5) OLDI0_A0N */ + AM62X_IOPAD(0x025c, PIN_OUTPUT, 0) /* (Y6) OLDI0_A0P */ + AM62X_IOPAD(0x0268, PIN_OUTPUT, 0) /* (AD3) OLDI0_A1N */ + AM62X_IOPAD(0x0264, PIN_OUTPUT, 0) /* (AB4) OLDI0_A1P */ + AM62X_IOPAD(0x0270, PIN_OUTPUT, 0) /* (Y8) OLDI0_A2N */ + AM62X_IOPAD(0x026c, PIN_OUTPUT, 0) /* (AA8) OLDI0_A2P */ + AM62X_IOPAD(0x0278, PIN_OUTPUT, 0) /* (AB6) OLDI0_A3N */ + AM62X_IOPAD(0x0274, PIN_OUTPUT, 0) /* (AA7) OLDI0_A3P */ + AM62X_IOPAD(0x0280, PIN_OUTPUT, 0) /* (AC6) OLDI0_A4N */ + AM62X_IOPAD(0x027c, PIN_OUTPUT, 0) /* (AC5) OLDI0_A4P */ + AM62X_IOPAD(0x0288, PIN_OUTPUT, 0) /* (AE5) OLDI0_A5N */ + AM62X_IOPAD(0x0284, PIN_OUTPUT, 0) /* (AD6) OLDI0_A5P */ + AM62X_IOPAD(0x0290, PIN_OUTPUT, 0) /* (AE6) OLDI0_A6N */ + AM62X_IOPAD(0x028c, PIN_OUTPUT, 0) /* (AD7) OLDI0_A6P */ + AM62X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AD8) OLDI0_A7N */ + AM62X_IOPAD(0x0294, PIN_OUTPUT, 0) /* (AE7) OLDI0_A7P */ + AM62X_IOPAD(0x02a0, PIN_OUTPUT, 0) /* (AD4) OLDI0_CLK0N */ + AM62X_IOPAD(0x029c, PIN_OUTPUT, 0) /* (AE3) OLDI0_CLK0P */ + AM62X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (AE4) OLDI0_CLK1N */ + AM62X_IOPAD(0x02a4, PIN_OUTPUT, 0) /* (AD5) OLDI0_CLK1P */ + >; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&main_oldi0_pins_default &main_dss0_pins_default>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: LVDS Output (OLDI TX 0) */ + port@0 { + reg = <0>; + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; + + /* VP1: LVDS Output (OLDI TX 1) */ + port@2 { + reg = <2>; + oldi_out1: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&exp1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&exp2 18 GPIO_ACTIVE_LOW>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + + +#include +#include + +#include "k3-pinctrl.h" + +&mcasp1 { + status = "disabled"; +}; + +&main_pmx0 { + gpmc0_pins_default: gpmc0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (M25) GPMC0_AD0 */ + AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (N23) GPMC0_AD1 */ + AM62X_IOPAD(0x0044, PIN_INPUT, 0) /* (N24) GPMC0_AD2 */ + AM62X_IOPAD(0x0048, PIN_INPUT, 0) /* (N25) GPMC0_AD3 */ + AM62X_IOPAD(0x004c, PIN_INPUT, 0) /* (P24) GPMC0_AD4 */ + AM62X_IOPAD(0x0050, PIN_INPUT, 0) /* (P22) GPMC0_AD5 */ + AM62X_IOPAD(0x0054, PIN_INPUT, 0) /* (P21) GPMC0_AD6 */ + AM62X_IOPAD(0x0058, PIN_INPUT, 0) /* (R23) GPMC0_AD7 */ + AM62X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (L23) GPMC0_ADVn_ALE */ + AM62X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (L24) GPMC0_OEn_REn */ + AM62X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L25) GPMC0_WEn */ + AM62X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (M24) GPMC0_BE0n_CLE */ + AM62X_IOPAD(0x00a8, PIN_OUTPUT, 0) /* (M21) GPMC0_CSn0 */ + AM62X_IOPAD(0x0098, PIN_INPUT, 0) /* (U23) GPMC0_WAIT0 */ + >; + }; +}; + +&gpmc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&gpmc0_pins_default>; + ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */ + #address-cells = <2>; + #size-cells = <1>; + + nand0_0: nand@0,0 { + compatible = "ti,am64-nand"; + reg = <0 0 64>; /* device IO registers */ + interrupt-parent = <&gpmc0>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-xfer-type = "prefetch-polled"; + ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */ + ti,elm-id = <&elm0>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <25>; + gpmc,adv-wr-off-ns = <25>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <3>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "NAND.tiboot3"; + reg = <0x00000000 0x00200000>; /* 2M */ + }; + partition@200000 { + label = "NAND.tispl"; + reg = <0x00200000 0x00200000>; /* 2M */ + }; + partition@400000 { + label = "NAND.tiboot3.backup"; /* 2M */ + reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */ + }; + partition@600000 { + label = "NAND.u-boot"; + reg = <0x00600000 0x00400000>; /* 4M */ + }; + partition@a00000 { + label = "NAND.u-boot-env"; + reg = <0x00a00000 0x00040000>; /* 256K */ + }; + partition@a40000 { + label = "NAND.u-boot-env.backup"; + reg = <0x00a40000 0x00040000>; /* 256K */ + }; + partition@a80000 { + label = "NAND.file-system"; + reg = <0x00a80000 0x3f580000>; + }; + }; + }; +}; + +&elm0{ + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62x LP SK: https://www.ti.com/tool/SK-AM62-LP + * + * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am62x-sk-common.dtsi" + +/ { + compatible = "ti,am62-lp-sk", "ti,am625"; + model = "Texas Instruments AM62x LP SK"; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_5v0: regulator-1 { + /* Output of TPS630702RNMR */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: regulator-2 { + /* output of LM61460-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-3 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_sys>; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + }; + + vddshv_sdio: regulator-4 { + compatible = "regulator-gpio"; + regulator-name = "vddshv_sdio"; + pinctrl-names = "default"; + pinctrl-0 = <&vddshv_sdio_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&ldo1_reg>; + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; +}; + +&main_pmx0 { + vddshv_sdio_pins_default: vddshv-sdio-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ + >; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (C13) UART0_RTSn.GPIO1_23 */ + >; + }; + + pmic_irq_pins_default: pmic-irq-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (B16) EXTINTn */ + >; + }; +}; + +&main_i2c1 { + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "PRU_DETECT", "MMC1_SD_EN", + "VPP_LDO_EN", "EXP_PS_3V3_En", + "EXP_PS_5V0_En", "EXP_HAT_DETECT", + "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", + "UART1_FET_BUF_EN", "BT_UART_WAKE_SOC", + "GPIO_HDMI_RSTn", "CSI_GPIO0", + "CSI_GPIO1", "GPIO_OLDI_INT", + "HDMI_INTn", "TEST_GPIO2", + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", + "MCASP1_FET_SEL", "UART1_FET_SEL", + "", "IO_EXP_TEST_LED"; + + interrupt-parent = <&main_gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + }; + + exp2: gpio@23 { + compatible = "ti,tca6424"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "", "", + "", "", + "", "", + "", "", + "WL_LT_EN", "CSI_RSTz", + "", "", + "", "", + "", "", + "SPI0_FET_SEL", "SPI0_FET_OE", + "GPIO_OLDI_RSTn", "PRU_3V3_EN", + "", "", + "CSI_VLDO_SEL", "SOC_WLAN_SDIO_RST"; + }; +}; + +&sdhci1 { + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vddshv_sdio>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&main_i2c0 { + tps65219: pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + buck1-supply = <&vcc_3v3_sys>; + buck2-supply = <&vcc_3v3_sys>; + buck3-supply = <&vcc_3v3_sys>; + ldo1-supply = <&vcc_3v3_sys>; + ldo2-supply = <&buck2_reg>; + ldo3-supply = <&vcc_3v3_sys>; + ldo4-supply = <&vcc_3v3_sys>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + + interrupt-parent = <&gic500>; + interrupts = ; + + regulators { + buck1_reg: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-boot-on; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "VCC1V8_SYS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "VDD_LPDDR4"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "VDDSHV_SDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo2_reg: ldo2 { + regulator-name = "VDDAR_CORE"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "VDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&tlv320aic3106 { + DVDD-supply = <&buck2_reg>; +}; + +&ospi0 { + flash@0 { + compatible = "spi-nand"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + cdns,phy-mode; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi_nand.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi_nand.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi_nand.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi_nand.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi_nand.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@2000000 { + label = "ospi_nand.rootfs"; + reg = <0x2000000 0x5fc0000>; + }; + + partition@7fc0000 { + label = "ospi_nand.phypattern"; + reg = <0x7fc0000 0x40000>; + }; + }; + }; +}; + +/* + * All SoC variants with the AMC package have no PRU. + * Attempting to access the PRU on these devices will + * result in a crash at kernel bootup. + * + * For now, we do not have any code that can figure out + * the absence of the PRU by reading any SoC registers, + * so for now disable the PRU here in the board DTS file. + */ +&pruss { + status = "disabled"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-main.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -56,10 +56,33 @@ }; epwm_tbclk: clock@4130 { - compatible = "ti,am62-epwm-tbclk", "syscon"; + compatible = "ti,am62-epwm-tbclk"; reg = <0x4130 0x4>; #clock-cells = <1>; }; + + dss_oldi_io_ctrl: dss-oldi-io-ctrl@8600 { + compatible = "syscon"; + reg = <0x8600 0x200>; + }; + + audio_refclk0: clock@82e0 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e0 0x4>; + clocks = <&k3_clks 157 0>; + assigned-clocks = <&k3_clks 157 0>; + assigned-clock-parents = <&k3_clks 157 8>; + #clock-cells = <0>; + }; + + audio_refclk1: clock@82e4 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e4 0x4>; + clocks = <&k3_clks 157 10>; + assigned-clocks = <&k3_clks 157 10>; + assigned-clock-parents = <&k3_clks 157 18>; + #clock-cells = <0>; + }; }; dmss: bus@48000000 { @@ -174,7 +197,6 @@ crypto: crypto@40900000 { compatible = "ti,am62-sa3ul"; reg = <0x00 0x40900000 0x00 0x1200>; - power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; @@ -184,12 +206,139 @@ dma-names = "tx", "rx1", "rx2"; }; + mcrc: mcrc@30300000 { + compatible = "ti,mcrc"; + reg = <0x00 0x30300000 0x00 0x1000>; + clocks = <&k3_clks 116 0>; + power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; + }; + + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + main_pmx0: pinctrl@f4000 { - compatible = "pinctrl-single"; + compatible = "ti,am6-padconf"; reg = <0x00 0xf4000 0x00 0x2ac>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 36 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 2>; + assigned-clock-parents = <&k3_clks 36 3>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 37 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 37 2>; + assigned-clock-parents = <&k3_clks 37 3>; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 38 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 38 2>; + assigned-clock-parents = <&k3_clks 38 3>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 39 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 39 2>; + assigned-clock-parents = <&k3_clks 39 3>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 40 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 40 2>; + assigned-clock-parents = <&k3_clks 40 3>; + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 41 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 41 2>; + assigned-clock-parents = <&k3_clks 41 3>; + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 42 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 42 2>; + assigned-clock-parents = <&k3_clks 42 3>; + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 43 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 43 2>; + assigned-clock-parents = <&k3_clks 43 3>; + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x420000 0x00 0x1000>; + ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; }; main_uart0: serial@2800000 { @@ -199,6 +348,7 @@ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -208,6 +358,7 @@ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 152 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -217,6 +368,7 @@ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 153 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart3: serial@2830000 { @@ -226,6 +378,7 @@ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 154 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart4: serial@2840000 { @@ -235,6 +388,7 @@ power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 155 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart5: serial@2850000 { @@ -244,6 +398,7 @@ power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 156 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart6: serial@2860000 { @@ -253,6 +408,7 @@ power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 158 0>; clock-names = "fclk"; + status = "disabled"; }; main_i2c0: i2c@20000000 { @@ -264,6 +420,7 @@ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 102 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c1: i2c@20010000 { @@ -275,6 +432,7 @@ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 103 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c2: i2c@20020000 { @@ -286,6 +444,7 @@ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 104 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c3: i2c@20030000 { @@ -297,6 +456,7 @@ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 2>; clock-names = "fck"; + status = "disabled"; }; main_spi0: spi@20100000 { @@ -387,15 +547,17 @@ clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 57 6>; assigned-clock-parents = <&k3_clks 57 8>; + bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; - ti,trm-icp = <0x2>; - bus-width = <8>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x9>; - ti,otap-del-sel-hs200 = <0x6>; + ti,otap-del-sel-ddr52 = <0x5>; + ti,otap-del-sel-hs200 = <0x5>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-mmc-hs = <0x1>; + status = "disabled"; }; sdhci1: mmc@fa00000 { @@ -405,20 +567,20 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x6>; - ti,otap-del-sel-ddr50 = <0x9>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x8>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0x0>; + ti,otap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr50 = <0x8>; + ti,otap-del-sel-sdr104 = <0x7>; + ti,otap-del-sel-ddr50 = <0x4>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-sd-hs = <0x1>; + ti,itap-del-sel-sdr12 = <0xa>; + ti,itap-del-sel-sdr25 = <0x1>; + status = "disabled"; }; sdhci2: mmc@fa20000 { @@ -428,24 +590,82 @@ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x6>; - ti,otap-del-sel-ddr50 = <0x9>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; + bus-width = <4>; ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x8>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0x0>; + ti,otap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr50 = <0x8>; + ti,otap-del-sel-sdr104 = <0x7>; + ti,otap-del-sel-ddr50 = <0x8>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-sd-hs = <0xa>; + ti,itap-del-sel-sdr12 = <0xa>; + ti,itap-del-sel-sdr25 = <0x1>; + status = "disabled"; + }; + + gpu: gpu@fd00000 { + compatible = "ti,am62-pvr", "img,pvr-axe116m"; + reg = <0x00 0x0fd00000 0x00 0x20000>; + interrupts = ; + power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 187 0>; + }; + + usbss0: dwc3-usb@f900000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f900000 0x00 0x800>, + <0x00 0x0f908000 0x00 0x400>; + clocks = <&k3_clks 161 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb0: usb@31000000 { + compatible = "snps,dwc3"; + reg =<0x00 0x31000000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + usbss1: dwc3-usb@f910000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; + clocks = <&k3_clks 162 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb1: usb@31100000 { + compatible = "snps,dwc3"; + reg =<0x00 0x31100000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; }; fss: bus@fc00000 { - compatible = "simple-bus"; + compatible = "simple-pm-bus"; reg = <0x00 0x0fc00000 0x00 0x70000>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -465,6 +685,7 @@ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -523,6 +744,7 @@ clocks = <&k3_clks 13 0>; clock-names = "fck"; bus_freq = <1000000>; + status = "disabled"; }; cpts@3d000 { @@ -537,6 +759,41 @@ }; }; + dss: dss@30200000 { + compatible = "ti,am625-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2", "common1"; + ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&k3_clks 186 0>, + <&k3_clks 186 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = ; + + dss_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + timesync_router: pinctrl@a40000 { + compatible = "pinctrl-single"; + reg = <0x0 0xa40000 0x0 0x800>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000107ff>; + status = "disabled"; + }; + hwspinlock: spinlock@2a000000 { compatible = "ti,am64-hwspinlock"; reg = <0x00 0x2a000000 0x00 0x1000>; @@ -560,6 +817,7 @@ power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 51 0>; clock-names = "fck"; + status = "disabled"; }; ecap1: pwm@23110000 { @@ -569,6 +827,7 @@ power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 52 0>; clock-names = "fck"; + status = "disabled"; }; ecap2: pwm@23120000 { @@ -578,6 +837,37 @@ power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 53 0>; clock-names = "fck"; + status = "disabled"; + }; + + eqep0: counter@23200000 { + compatible = "ti,am3352-eqep"; + reg = <0x00 0x23200000 0x00 0x100>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 59 0>; + clock-names = "fck"; + interrupts = ; + status = "disabled"; + }; + + eqep1: counter@23210000 { + compatible = "ti,am3352-eqep"; + reg = <0x00 0x23210000 0x00 0x100>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 60 0>; + clock-names = "fck"; + interrupts = ; + status = "disabled"; + }; + + eqep2: counter@23220000 { + compatible = "ti,am3352-eqep"; + reg = <0x00 0x23220000 0x00 0x100>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 62 0>; + clock-names = "fck"; + interrupts = ; + status = "disabled"; }; main_mcan0: can@20701000 { @@ -592,6 +882,52 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_rti0: watchdog@e000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e000000 0x00 0x100>; + clocks = <&k3_clks 125 0>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-parents = <&k3_clks 125 2>; + }; + + main_rti1: watchdog@e010000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e010000 0x00 0x100>; + clocks = <&k3_clks 126 0>; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 126 0>; + assigned-clock-parents = <&k3_clks 126 2>; + }; + + main_rti2: watchdog@e020000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e020000 0x00 0x100>; + clocks = <&k3_clks 127 0>; + power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 127 0>; + assigned-clock-parents = <&k3_clks 127 2>; + }; + + main_rti3: watchdog@e030000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e030000 0x00 0x100>; + clocks = <&k3_clks 128 0>; + power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 128 0>; + assigned-clock-parents = <&k3_clks 128 2>; + }; + + main_rti15: watchdog@e0f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e0f0000 0x00 0x100>; + clocks = <&k3_clks 130 0>; + power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 130 0>; + assigned-clock-parents = <&k3_clks 130 2>; }; epwm0: pwm@23000000 { @@ -601,6 +937,7 @@ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm1: pwm@23010000 { @@ -610,6 +947,7 @@ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm2: pwm@23020000 { @@ -619,5 +957,258 @@ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + mcasp0: audio-controller@2b00000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b00000 0x00 0x2000>, + <0x00 0x02b08000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 190 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 190 0>; + assigned-clock-parents = <&k3_clks 190 2>; + power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp1: audio-controller@2b10000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b10000 0x00 0x2000>, + <0x00 0x02b18000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 191 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 191 0>; + assigned-clock-parents = <&k3_clks 191 2>; + power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp2: audio-controller@2b20000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b20000 0x00 0x2000>, + <0x00 0x02b28000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 192 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 192 0>; + assigned-clock-parents = <&k3_clks 192 2>; + power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + ti_csi2rx0: ticsi2rx@30102000 { + compatible = "ti,j721e-csi2rx"; + dmas = <&main_bcdma 0 0x4700 0>, <&main_bcdma 0 0x4701 0>, <&main_bcdma 0 0x4702 0>, + <&main_bcdma 0 0x4703 0>; + dma-names = "rx0", "rx1", "rx2", "rx3"; + reg = <0x00 0x30102000 0x00 0x1000>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@30101000 { + compatible = "cdns,csi2rx"; + reg = <0x00 0x30101000 0x00 0x1000>; + clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, + <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@30110000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30110000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + gpmc0: memory-controller@3b000000 { + status = "disabled"; + compatible = "ti,am64-gpmc"; + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 80 0>; + clock-names = "fck"; + reg = <0x00 0x03b000000 0x00 0x400>, + <0x00 0x050000000 0x00 0x8000000>; + reg-names = "cfg", "data"; + interrupts = ; + gpmc,num-cs = <3>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + elm0: ecc@25010000 { + status = "disabled"; + compatible = "ti,am3352-elm"; + reg = <0x00 0x25010000 0x00 0x2000>; + interrupts = ; + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 54 0>; + clock-names = "fck"; + }; + + ecap2: pwm@23120000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23120000 0x00 0x100>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 53 0>; + clock-names = "fck"; + }; + + pruss: pruss@30040000 { + compatible = "ti,am625-pruss"; + reg = <0x00 0x30040000 0x00 0x80000>; + power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x30040000 0x80000>; + + pruss_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x10000>; + reg-names = "dram0", "dram1", "shrdram2"; + }; + + pruss_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + pruss_coreclk_mux: coreclk-mux@3c { + reg = <0x3c>; + #clock-cells = <0>; + clocks = <&k3_clks 81 0>, /* pruss_core_clk */ + <&k3_clks 81 20>; /* pruss_iclk */ + assigned-clocks = <&pruss_coreclk_mux>; + assigned-clock-parents = <&k3_clks 81 20>; + }; + + pruss_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&k3_clks 81 3>, /* pruss_iep_clk */ + <&pruss_coreclk_mux>; /* pruss_coreclk_mux */ + assigned-clocks = <&pruss_iepclk_mux>; + assigned-clock-parents = <&pruss_coreclk_mux>; + }; + }; + }; + + pruss_intc: interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + }; + + pru0: pru@34000 { + compatible = "ti,am625-pru"; + reg = <0x34000 0x3000>, + <0x22000 0x100>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am62x-pru0-fw"; + interrupt-parent = <&pruss_intc>; + interrupts = <16 2 2>; + interrupt-names = "vring"; + }; + + pru1: pru@38000 { + compatible = "ti,am625-pru"; + reg = <0x38000 0x3000>, + <0x24000 0x100>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am62x-pru1-fw"; + interrupt-parent = <&pruss_intc>; + interrupts = <18 3 3>; + interrupt-names = "vring"; + }; }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -14,6 +14,57 @@ pinctrl-single,function-mask = <0xffffffff>; }; + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@4800000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4800000 0x00 0x400>; + clocks = <&k3_clks 35 2>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@4810000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4810000 0x00 0x400>; + clocks = <&k3_clks 48 2>; + clock-names = "fck"; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@4820000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4820000 0x00 0x400>; + clocks = <&k3_clks 49 2>; + clock-names = "fck"; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@4830000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4830000 0x00 0x400>; + clocks = <&k3_clks 50 2>; + clock-names = "fck"; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x4100000 0x00 0x1000>; + ti,esm-pins = <0>, <1>, <2>, <85>; + }; + mcu_uart0: serial@4a00000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; @@ -21,6 +72,7 @@ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; + status = "disabled"; }; mcu_i2c0: i2c@4900000 { @@ -32,6 +84,7 @@ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 106 2>; clock-names = "fck"; + status = "disabled"; }; mcu_spi0: spi@4b00000 { @@ -83,4 +136,54 @@ clocks = <&k3_clks 79 0>; clock-names = "gpio"; }; + + mcu_rti0: watchdog@4880000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x04880000 0x00 0x100>; + clocks = <&k3_clks 131 0>; + power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 131 0>; + assigned-clock-parents = <&k3_clks 131 2>; + /* Tightly coupled to M4F */ + status = "reserved"; + }; + + mcu_m4fss: m4fss@5000000 { + compatible = "ti,am64-m4fss"; + reg = <0x00 0x5000000 0x00 0x30000>, + <0x00 0x5040000 0x00 0x10000>; + reg-names = "iram", "dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <9>; + ti,sci-proc-ids = <0x18 0xff>; + resets = <&k3_reset 9 1>; + firmware-name = "am62-mcu-m4f0_0-fw"; + wakeup-source; + }; + + mcu_mcan0: can@4e08000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e08000 0x00 0x200>, + <0x00 0x4e00000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + wakeup-source; + status = "disabled"; + }; + + mcu_mcan1: can@4e18000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e18000 0x00 0x200>, + <0x00 0x4e10000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + wakeup-source; + status = "disabled"; + }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -5,6 +5,8 @@ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ */ +#include + &cbass_wakeup { wkup_conf: syscon@43000000 { compatible = "syscon", "simple-mfd"; @@ -17,25 +19,110 @@ compatible = "ti,am654-chipid"; reg = <0x14 0x4>; }; + + usb0_phy_ctrl: syscon@4008 { + compatible = "syscon"; + reg = <0x4008 0x4>; + }; + + usb1_phy_ctrl: syscon@4018 { + compatible = "syscon"; + reg = <0x4018 0x4>; + }; }; - wkup_uart0: serial@2b300000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x2b300000 0x00 0x100>; - interrupts = ; + target-module@2b300050 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0 0x2b300050 0 0x4>, + <0 0x2b300054 0 0x4>, + <0 0x2b300058 0 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + ti,no-reset-on-init; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; - clock-names = "fclk"; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2b300000 0x100000>; + + wkup_uart0: serial@0 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0 0x100>; + interrupts = ; + status = "disabled"; + }; }; wkup_i2c0: i2c@2b200000 { compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02b200000 0x00 0x100>; + reg = <0x00 0x2b200000 0x00 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 4>; clock-names = "fck"; + status = "disabled"; + }; + + wkup_rtc0: rtc@2b1f0000 { + compatible = "ti,am62-rtc"; + reg = <0x00 0x2b1f0000 0x00 0x100>; + interrupts = ; + clocks = <&k3_clks 117 6> , <&k3_clks 117 0>; + clock-names = "vbus", "osc32k"; + power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; + wakeup-source; + }; + + wkup_rti0: watchdog@2b000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2b000000 0x00 0x100>; + clocks = <&k3_clks 132 0>; + power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 132 0>; + assigned-clock-parents = <&k3_clks 132 2>; + /* Used by DM firmware */ + status = "reserved"; + }; + + wkup_r5fss0: r5fss@78000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + + wkup_r5fss0_core0: r5f@78000000 { + compatible = "ti,am62-r5f"; + reg = <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <121>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 121 1>; + firmware-name = "ti-sysfw/ti-fs-stub-firmware-am62x-gp-signed.bin"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + wkup_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am62.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -8,9 +8,10 @@ #include #include #include -#include #include +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 AM625 SoC"; compatible = "ti,am625"; @@ -64,6 +65,7 @@ <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30300000 0x00 0x30300000 0x00 0x00001000>, /* MCRC */ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ @@ -75,13 +77,18 @@ <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */ /* MCU Domain Range */ <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, - <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ cbass_mcu: bus@4000000 { compatible = "simple-bus"; @@ -90,17 +97,26 @@ ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ }; - cbass_wakeup: bus@2b000000 { + cbass_wakeup: bus@b00000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; - ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ - <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ }; }; + + #include "k3-am62-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ #include "k3-am62-main.dtsi" #include "k3-am62-mcu.dtsi" #include "k3-am62-wakeup.dtsi" + +&dmsc { + ti,partial-io-wakeup-sources = <&mcu_mcan0>, <&mcu_mcan1>, <&mcu_uart0>, <&wkup_uart0>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-ov5640.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-ov5640.dtso @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ALINX AN5641 & Digilent PCam 5C - OV5640 camera module + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; +}; + +&main_gpio0 { + p11-hog { + /* P11 - CSI2_CAMERA_GPIO1 */ + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI2_CAMERA_GPIO1"; + }; +}; + +&wkup_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx0 { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Technexion TEVI-OV5640-*-RPI - OV5640 camera module + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&main_gpio0 { + p11-hog { + /* P11 - CSI2_CAMERA_GPIO1 */ + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI2_CAMERA_GPIO1"; + }; +}; + +&wkup_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx0 { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-beagleplay-lincolntech-lcd185-panel.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-beagleplay-lincolntech-lcd185-panel.dtso @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Lincoln tech Solutions OLDI panel (LCD185-101CT) and touch DT overlay for AM625-BeaglePlay + * + * AM625-BeaglePlay: https://www.beagleboard.org/boards/beagleplay + * Panel datasheet: https://lincolntechsolutions.com/wp-content/uploads/2023/04/LCD185-101CTL1ARNTT_DS_R1.3.pdf + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins_default>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + enable-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; + pwms = <&epwm0 1 20000 0>; + }; + + lcd { + compatible = "lincolntech,lcd185-101ct"; + backlight = <&backlight>; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * But swapping them will cause an error in the dss driver. + */ + port@0 { + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + port@1 { + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_out1>; + }; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: LVDS Output (OLDI TX 0) */ + port@0 { + reg = <0>; + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; + + /* VP1: LVDS Output (OLDI TX 1) */ + port@2 { + reg = <2>; + oldi_out1: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@57 { + compatible = "atmel,24c256"; + reg = <0x57>; + }; + + touchscreen@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins_default>; + interrupt-parent = <&main_gpio0>; + interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&main_gpio0 39 GPIO_ACTIVE_LOW>; + reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <1920>; + touchscreen-size-y = <1200>; + }; +}; + +&epwm0 { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -0,0 +1,998 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * https://beagleplay.org/ + * + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation + */ + +/dts-v1/; + +#include +#include +#include +#include "k3-am625.dtsi" + +/ { + compatible = "beagle,am625-beagleplay", "ti,am625"; + model = "BeagleBoard.org BeaglePlay"; + + aliases { + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + gpio0 = &main_gpio0; + gpio1 = &main_gpio1; + gpio2 = &mcu_gpio0; + i2c0 = &main_i2c0; + i2c1 = &main_i2c1; + i2c2 = &main_i2c2; + i2c3 = &main_i2c3; + i2c4 = &wkup_i2c0; + i2c5 = &mcu_i2c0; + mdio-gpio0 = &mdio0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + rtc0 = &rtc; + rtc1 = &wkup_rtc0; + serial0 = &main_uart5; + serial1 = &main_uart6; + serial2 = &main_uart0; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops: ramoops@9ca00000 { + compatible = "ramoops"; + reg = <0x00 0x9c700000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x8000000>; + linux,cma-default; + }; + + mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@9cc00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + }; + + vsys_5v0: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3: regulator-2 { + /* output of TLV62595DMQR-U12 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_5v0>; + regulator-always-on; + regulator-boot-on; + }; + + wlan_en: regulator-3 { + /* OUTPUT of SN74AVC2T244DQMR */ + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-always-on; + vin-supply = <&vdd_3v3>; + gpio = <&main_gpio0 38 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_en_pins_default>; + }; + + vdd_3v3_sd: regulator-4 { + /* output of TPS22918DBVR-U21 */ + pinctrl-names = "default"; + pinctrl-0 = <&vdd_3v3_sd_pins_default>; + + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + vin-supply = <&vdd_3v3>; + gpio = <&main_gpio1 19 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: regulator-5 { + compatible = "regulator-gpio"; + regulator-name = "sd_hs200_switch"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&ldo1_reg>; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + + led-1 { + gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + function = LED_FUNCTION_DISK_ACTIVITY; + default-state = "keep"; + }; + + led-2 { + gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_CPU; + }; + + led-3 { + gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_LAN; + }; + + led-4 { + gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_WLAN; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&usr_button_pins_default>; + + usr: button-usr { + label = "User Key"; + linux,code = ; + gpios = <&main_gpio0 18 GPIO_ACTIVE_LOW>; + }; + + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&it66121hdmitx_out>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "it66121 HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&hdmi_dailink_master>; + simple-audio-card,frame-master = <&hdmi_dailink_master>; + + hdmi_dailink_master: simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-direction-out; + }; + + simple-audio-card,codec { + sound-dai = <&it66121hdmitx>; + }; + }; + + /* Workaround for errata i2329 - just use mdio bitbang */ + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default>; + gpios = <&main_gpio0 86 GPIO_ACTIVE_HIGH>, /* MDC */ + <&main_gpio0 85 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <25>; + reset-deassert-us = <60000>; /* T2 */ + }; + }; +}; + +&main_pmx0 { + hdmi_pins_default: hdmi-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ + AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ + AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ + AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ + AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ + AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ + AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ + AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ + AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ + AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ + AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ + AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ + AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ + AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ + AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ + AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ + AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ + AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ + AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ + AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ + AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ + AM62X_IOPAD(0x0064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */ + AM62X_IOPAD(0x0068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */ + AM62X_IOPAD(0x006c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ + AM62X_IOPAD(0x0070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */ + AM62X_IOPAD(0x0074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */ + AM62X_IOPAD(0x0078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ + >; + }; + + hdmi_gpio_pins_default: hdmi-gpio-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0094, PIN_INPUT_PULLUP | PIN_DEBOUNCE_CONF6, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ + AM62X_IOPAD(0x0054, PIN_OUTPUT_PULLUP, 7) /* (P21) GPMC0_AD6.GPIO0_21 */ + >; + }; + + gpio0_pins_default: gpio0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */ + AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */ + AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */ + AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */ + AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */ + AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ + AM62X_IOPAD(0x0024, PIN_INPUT, 7) /* (H25) OSPI0_D6.GPIO0_9 */ + AM62X_IOPAD(0x0028, PIN_INPUT, 7) /* (J22) OSPI0_D7.GPIO0_10 */ + AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ + AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */ + AM62X_IOPAD(0x0034, PIN_INPUT, 7) /* (H21) OSPI0_CSn2.GPIO0_13 */ + AM62X_IOPAD(0x0038, PIN_INPUT, 7) /* (E24) OSPI0_CSn3.GPIO0_14 */ + AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ + AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ + >; + }; + + usr_button_pins_default: usr-button-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0048, PIN_INPUT, 7) /* (N25) GPMC0_AD3.GPIO0_18 */ + >; + }; + + grove_pins_default: grove-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + local_i2c_pins_default: local-i2c-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + i2c2_1v8_pins_default: i2c2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ + AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + mcasp_hdmi_pins_default: mcasp-hdmi-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ + AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ + AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0 */ + AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */ + AM62X_IOPAD(0x0084, PIN_INPUT, 2) /* (L23) GPMC0_ADVn_ALE.MCASP1_AXR2 */ + AM62X_IOPAD(0x007c, PIN_INPUT, 2) /* (P25) GPMC0_CLK.MCASP1_AXR3 */ + >; + }; + + mdio0_pins_default: mdio0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */ + AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */ + >; + }; + + rgmii1_pins_default: rgmii1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x014c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x0150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x0154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x0148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x0144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ + >; + }; + + emmc_pins_default: emmc-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x0214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x0210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x020c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x0208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x0204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x0200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x01fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x01f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + vdd_3v3_sd_pins_default: vdd-3v3-sd-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */ + >; + }; + + sd_pins_default: sd-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ + AM62X_IOPAD(0x0240, PIN_INPUT, 7) /* (D17) MMC1_SDCD.GPIO1_48 */ + >; + }; + + wifi_pins_default: wifi-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ + AM62X_IOPAD(0x0118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ + AM62X_IOPAD(0x0114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */ + AM62X_IOPAD(0x0110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */ + AM62X_IOPAD(0x010c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */ + AM62X_IOPAD(0x0108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */ + AM62X_IOPAD(0x0124, PIN_INPUT, 0) /* (A23) MMC2_SDCD */ + AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ + >; + }; + + wifi_en_pins_default: wifi-en-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x009c, PIN_OUTPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ + >; + }; + + wifi_wlirq_pins_default: wifi-wlirq-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ + >; + }; + + oldi_pins_default: oldi-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0260, PIN_OUTPUT, 0) /* (AA5) OLDI0_A0N */ + AM62X_IOPAD(0x025c, PIN_OUTPUT, 0) /* (Y6) OLDI0_A0P */ + AM62X_IOPAD(0x0268, PIN_OUTPUT, 0) /* (AD3) OLDI0_A1N */ + AM62X_IOPAD(0x0264, PIN_OUTPUT, 0) /* (AB4) OLDI0_A1P */ + AM62X_IOPAD(0x0270, PIN_OUTPUT, 0) /* (Y8) OLDI0_A2N */ + AM62X_IOPAD(0x026c, PIN_OUTPUT, 0) /* (AA8) OLDI0_A2P */ + AM62X_IOPAD(0x0278, PIN_OUTPUT, 0) /* (AB6) OLDI0_A3N */ + AM62X_IOPAD(0x0274, PIN_OUTPUT, 0) /* (AA7) OLDI0_A3P */ + AM62X_IOPAD(0x0280, PIN_OUTPUT, 0) /* (AC6) OLDI0_A4N */ + AM62X_IOPAD(0x027c, PIN_OUTPUT, 0) /* (AC5) OLDI0_A4P */ + AM62X_IOPAD(0x0288, PIN_OUTPUT, 0) /* (AE5) OLDI0_A5N */ + AM62X_IOPAD(0x0284, PIN_OUTPUT, 0) /* (AD6) OLDI0_A5P */ + AM62X_IOPAD(0x0290, PIN_OUTPUT, 0) /* (AE6) OLDI0_A6N */ + AM62X_IOPAD(0x028c, PIN_OUTPUT, 0) /* (AD7) OLDI0_A6P */ + AM62X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AD8) OLDI0_A7N */ + AM62X_IOPAD(0x0294, PIN_OUTPUT, 0) /* (AE7) OLDI0_A7P */ + AM62X_IOPAD(0x02a0, PIN_OUTPUT, 0) /* (AD4) OLDI0_CLK0N */ + AM62X_IOPAD(0x029c, PIN_OUTPUT, 0) /* (AE3) OLDI0_CLK0P */ + AM62X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (AE4) OLDI0_CLK1N */ + AM62X_IOPAD(0x02a4, PIN_OUTPUT, 0) /* (AD5) OLDI0_CLK1P */ + >; + }; + + spe_pins_default: spe-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0168, PIN_INPUT, 1) /* (AE21) RGMII2_TXC.RMII2_CRS_DV */ + AM62X_IOPAD(0x0180, PIN_INPUT, 1) /* (AD23) RGMII2_RXC.RMII2_REF_CLK */ + AM62X_IOPAD(0x0184, PIN_INPUT, 1) /* (AE23) RGMII2_RD0.RMII2_RXD0 */ + AM62X_IOPAD(0x0188, PIN_INPUT, 1) /* (AB20) RGMII2_RD1.RMII2_RXD1 */ + AM62X_IOPAD(0x017c, PIN_INPUT, 1) /* (AD22) RGMII2_RX_CTL.RMII2_RX_ER */ + AM62X_IOPAD(0x016c, PIN_INPUT, 1) /* (Y18) RGMII2_TD0.RMII2_TXD0 */ + AM62X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA18) RGMII2_TD1.RMII2_TXD1 */ + AM62X_IOPAD(0x0164, PIN_INPUT, 1) /* (AA19) RGMII2_TX_CTL.RMII2_TX_EN */ + AM62X_IOPAD(0x018c, PIN_OUTPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */ + AM62X_IOPAD(0x0190, PIN_INPUT, 7) /* (AE22) RGMII2_RD3.GPIO1_6 */ + AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ + >; + }; + + mikrobus_i2c_pins_default: mikrobus-i2c-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A15) UART0_CTSn.I2C3_SCL */ + AM62X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (B15) UART0_RTSn.I2C3_SDA */ + >; + }; + + mikrobus_uart_pins_default: mikrobus-uart-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d8, PIN_INPUT, 1) /* (C15) MCAN0_TX.UART5_RXD */ + AM62X_IOPAD(0x01dc, PIN_OUTPUT, 1) /* (E15) MCAN0_RX.UART5_TXD */ + >; + }; + + mikrobus_spi_pins_default: mikrobus-spi-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */ + AM62X_IOPAD(0x01ac, PIN_INPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */ + AM62X_IOPAD(0x0194, PIN_INPUT, 1) /* (B19) MCASP0_AXR3.SPI2_D0 */ + AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */ + >; + }; + + mikrobus_gpio_pins_default: mikrobus-gpio-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */ + AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */ + AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */ + >; + }; + + touchscreen_pins_default: touchscreen-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b4, PIN_OUTPUT, 7) /* (A13) SPI0_CS0.GPIO1_15 */ + AM62X_IOPAD(0x00a0, PIN_INPUT, 7) /* (K25) GPMC0_WPn.GPIO0_39 */ + >; + }; + + backlight_pins_default: bl-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0000, PIN_OUTPUT, 7) /* (H24) OSPI0_CLK.GPIO0_0 */ + AM62X_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (C13) SPI0_CS1.EHRPWM0_B */ + >; + }; + + console_pins_default: console-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ + AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + wifi_debug_uart_pins_default: wifi-debug-uart-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x001c, PIN_INPUT, 3) /* (J23) OSPI0_D4.UART6_RXD */ + AM62X_IOPAD(0x0020, PIN_OUTPUT, 3) /* (J25) OSPI0_D5.UART6_TXD */ + >; + }; + + usb1_pins_default: usb1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */ + >; + }; + + pmic_irq_pins_default: pmic-irq-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */ + >; + }; +}; + +&mcu_pmx0 { + i2c_qwiic_pins_default: i2c-qwiic-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ + AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ + >; + }; + + gbe_pmx_obsclk: gbe-pmx-clk-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (B8) MCU_SPI0_CS1.MCU_OBSCLK0 */ + >; + }; + + i2c_csi_pins_default: i2c-csi-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x004c, PIN_INPUT_PULLUP, 0) /* (B9) WKUP_I2C0_SCL */ + AM62X_MCU_IOPAD(0x0050, PIN_INPUT_PULLUP, 0) /* (A9) WKUP_I2C0_SDA */ + >; + }; + + wifi_32k_clk: mcu-clk-out-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ + >; + }; +}; + +&a53_opp_table { + /* Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + }; +}; + +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_csi_pins_default>; + clock-frequency = <400000>; + /* Enable with overlay for camera sensor */ +}; + +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_qwiic_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +&mcu_m4fss { + mboxes = <&mailbox0_cluster0 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; +}; + +&wkup_r5fss0 { + /* Runs dedicated Device Management firmware */ + status = "reserved"; +}; + +&mailbox0_cluster0 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; +}; + +&usbss1 { + ti,vbus-divider; + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_default>; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins_default>, <&spe_pins_default>, + <&gbe_pmx_obsclk>; + assigned-clocks = <&k3_clks 157 70>, <&k3_clks 157 20>; + assigned-clock-parents = <&k3_clks 157 72>, <&k3_clks 157 22>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rmii"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + /* Workaround for errata i2329 - Use mdio bitbang */ + status = "disabled"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_pins_default>; + gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */ + "USR0", "USR1", "USR2", "USR3", "", "", "USR4", /* 3-9 */ + "EEPROM_WP", /* 10 */ + "CSI2_CAMERA_GPIO1", "CSI2_CAMERA_GPIO2", /* 11-12 */ + "CC1352P7_BOOT", "CC1352P7_RSTN", "", "", "", /* 13-17 */ + "USR_BUTTON", "", "", "", "", "", "", "", "", /* 18-26 */ + "", "", "", "", "", "", "", "", "", "HDMI_INT", /* 27-36 */ + "", "VDD_WLAN_EN", "", "", "WL_IRQ", "GBE_INTN",/* 37-42 */ + "", "", "", "", "", "", "", "", "", "", "", "", /* 43-54 */ + "", "", "", "", "", "", "", "", "", "", "", "", /* 55-66 */ + "", "", "", "", "", "", "", "", "", "", "", "", /* 67-78 */ + "", "", "", "", "", "", /* 79-84 */ + "BITBANG_MDIO_DATA", "BITBANG_MDIO_CLK", /* 85-86 */ + "", "", "", "", ""; /* 87-91 */ +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&mikrobus_gpio_pins_default>; + gpio-line-names = "", "", "", "", "", /* 0-4 */ + "SPE_RSTN", "SPE_INTN", "MIKROBUS_GPIO1_7", /* 5-7 */ + "MIKROBUS_GPIO1_8", "MIKROBUS_GPIO1_9", /* 8-9 */ + "MIKROBUS_GPIO1_10", "MIKROBUS_GPIO1_11", /* 10-11 */ + "MIKROBUS_GPIO1_12", "MIKROBUS_W1_GPIO0", /* 12-13 */ + "MIKROBUS_GPIO1_14", /* 14 */ + "", "", "", "", "VDD_3V3_SD", "", "", /* 15-21 */ + "MIKROBUS_GPIO1_22", "MIKROBUS_GPIO1_23", /* 22-23 */ + "MIKROBUS_GPIO1_24", "MIKROBUS_GPIO1_25", /* 24-25 */ + "", "", "", "", "", "", "", "", "", "", "", "", /* 26-37 */ + "", "", "", "", "", "", "", "", "", "", /* 38-47 */ + "SD_CD", "SD_VOLT_SEL", "", ""; /* 48-51 */ +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&local_i2c_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + + rtc: rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + interrupt-parent = <&main_gpio0>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + }; + + tps65219: pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + buck1-supply = <&vsys_5v0>; + buck2-supply = <&vsys_5v0>; + buck3-supply = <&vsys_5v0>; + ldo1-supply = <&vdd_3v3>; + ldo2-supply = <&buck2_reg>; + ldo3-supply = <&vdd_3v3>; + ldo4-supply = <&vdd_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + system-power-controller; + ti,power-button; + + regulators { + buck1_reg: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "VDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + /* + * Regulator is left as is unused, vdd_sd + * is controlled via GPIO with bypass config + * as per the NVM configuration + */ + regulator-name = "VDD_SD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allow-bypass; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "VDDA_0V85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "VDD_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&grove_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_1v8_pins_default>; + clock-frequency = <100000>; + status = "okay"; + + it66121hdmitx: hdmitx@4c { + #sound-dai-cells = <0>; + compatible = "ite,it66121"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_gpio_pins_default>; + reg = <0x4c>; + + interrupt-parent = <&main_gpio0>; + interrupts = <36 IRQ_TYPE_EDGE_FALLING>; + + vcn33-supply = <&vdd_3v3>; + vcn18-supply = <&buck2_reg>; + vrf12-supply = <&buck3_reg>; + + reset-gpios = <&main_gpio0 21 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + it66121hdmitx_in: endpoint { + bus-width = <24>; + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + it66121hdmitx_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&mikrobus_i2c_pins_default>; + clock-frequency = <400000>; + status = "okay"; +}; + +&main_spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&mikrobus_spi_pins_default>; + status = "okay"; +}; + +&mcasp0 { + status = "disabled"; +}; + +&mcasp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp_hdmi_pins_default>; + + #sound-dai-cells = <0>; + + auxclk-fs-ratio = <2177>; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <0>; + rx-num-evt = <0>; +}; + +&mcasp2 { + status = "disabled"; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins_default>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP2: DPI Output */ + port@1 { + reg = <1>; + + dpi1_out: endpoint { + remote-endpoint = <&it66121hdmitx_in>; + }; + }; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins_default>; + disable-wp; + status = "okay"; +}; + +&sdhci1 { + /* SD/MMC */ + pinctrl-names = "default"; + pinctrl-0 = <&sd_pins_default>; + + vmmc-supply = <&vdd_3v3_sd>; + vqmmc-supply = <&vdd_sd_dv>; + disable-wp; + cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; + cd-debounce-delay-ms = <100>; + ti,fails-without-test-cd; + status = "okay"; +}; + +&sdhci2 { + vmmc-supply = <&wlan_en>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>; + non-removable; + ti,fails-without-test-cd; + cap-power-off-card; + keep-power-in-suspend; + assigned-clocks = <&k3_clks 157 158>; + assigned-clock-parents = <&k3_clks 157 160>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1807"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wlirq_pins_default>; + interrupt-parent = <&main_gpio0>; + interrupts = <41 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&console_pins_default>; + status = "okay"; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; +}; + +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&mikrobus_uart_pins_default>; + status = "okay"; +}; + +&main_uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_debug_uart_pins_default>; + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-dmtimer-pwm.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-dmtimer-pwm.dtso @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay to enable brightness control for Heartbeat LED + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + leds { + compatible = "pwm-leds"; + pinctrl-names; + pinctrl-0; + + led-0 { + pwms = <&main_pwm7 0 7812500 0>; + max-brightness = <255>; + }; + }; + + main_pwm7: dmtimer-main-pwm-7 { + pinctrl-0 = <&usr_led_pins_default>; + pinctrl-names = "default"; + compatible = "ti,omap-dmtimer-pwm"; + #pwm-cells = <3>; + ti,timers = <&main_timer7>; + }; +}; + +&main_pmx0 { + usr_led_pins_default: usr-led-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x244, PIN_OUTPUT, 2) /* (C17) MMC1_SDWP.TIMER_IO7 */ + >; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-ecap-capture.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-ecap-capture.dtso @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for enabling ECAP capture mode on AM625-SK board. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + main_ecap2_capture_pins_default: main-ecap2-capture-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01a4, PIN_INPUT, 2) /* (B20) MCASP0_ACLKX.ECAP2_IN_APWM_OUT */ + >; + }; +}; + +&ecap2 { + compatible = "ti,am62-ecap-capture"; + interrupt-parent = <&gic500>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap2_capture_pins_default>; + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-lincolntech-lcd185-panel.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-lincolntech-lcd185-panel.dtso @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Lincoln tech Solutions OLDI panel (LCD185-101CT) and touch DT overlay for AM625-SK + * + * AM625-SKEVM: https://www.ti.com/tool/SK-AM62 + * Panel datasheet: https://lincolntechsolutions.com/wp-content/uploads/2023/04/LCD185-101CTL1ARNTT_DS_R1.3.pdf + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + display { + compatible = "lincolntech,lcd185-101ct"; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * But swapping them will cause an error in the dss driver. + */ + port@0 { + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + port@1 { + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_out1>; + }; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: LVDS Output (OLDI TX 0) */ + port@0 { + reg = <0>; + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; + + /* VP1: LVDS Output (OLDI TX 1) */ + port@2 { + reg = <2>; + oldi_out1: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@57 { + compatible = "atmel,24c256"; + reg = <0x57>; + }; + + touchscreen@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + interrupt-parent = <&exp1>; + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&exp1 22 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1920>; + touchscreen-size-y = <1200>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-mcspi-loopback.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-mcspi-loopback.dtso @@ -0,0 +1,55 @@ + + +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for using McSPI on the RPi header on AM625-SK board. + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + main_spi0_pins_default: main-spi0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01bc, PIN_INPUT, 0) /* (A14) SPI0_CLK */ + AM62X_IOPAD(0x01c0, PIN_INPUT, 0) /* (B13) SPI0_D0 */ + AM62X_IOPAD(0x01c4, PIN_INPUT, 0) /* (B14) SPI0_D1 */ + AM62X_IOPAD(0x01b4, PIN_INPUT, 0) /* (A13) SPI0_CS0 */ + >; + }; +}; + +&main_i2c1 { + gpio@22 { + en_rpi_3v3 { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_3V3_EN"; + }; + }; +}; + +&main_spi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&main_spi0_pins_default>; + pinctrl-names = "default"; + spidev@0 { + /* + * Using spidev compatible is warned loudly, + * thus use another equivalent compatible id + * from spidev. + */ + compatible = "rohm,dh2228fv"; + spi-max-frequency = <24000000>; + reg = <0>; + }; +}; + Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-microtips-mf101hie-panel.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-microtips-mf101hie-panel.dtso @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Microtips integrated OLDI panel (MF-101HIEBCAF0) and touch DT overlay for AM625 - SK + * + * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + display { + compatible = "microtips,mf-101hiebcaf0"; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * Swapping them will not make any difference. + */ + port@0 { + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + port@1 { + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_out1>; + }; + }; + }; +}; + +&main_pmx0 { + main_oldi0_pins_default: main-oldi0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0260, PIN_OUTPUT, 0) /* (AA5) OLDI0_A0N */ + AM62X_IOPAD(0x025c, PIN_OUTPUT, 0) /* (Y6) OLDI0_A0P */ + AM62X_IOPAD(0x0268, PIN_OUTPUT, 0) /* (AD3) OLDI0_A1N */ + AM62X_IOPAD(0x0264, PIN_OUTPUT, 0) /* (AB4) OLDI0_A1P */ + AM62X_IOPAD(0x0270, PIN_OUTPUT, 0) /* (Y8) OLDI0_A2N */ + AM62X_IOPAD(0x026c, PIN_OUTPUT, 0) /* (AA8) OLDI0_A2P */ + AM62X_IOPAD(0x0278, PIN_OUTPUT, 0) /* (AB6) OLDI0_A3N */ + AM62X_IOPAD(0x0274, PIN_OUTPUT, 0) /* (AA7) OLDI0_A3P */ + AM62X_IOPAD(0x0280, PIN_OUTPUT, 0) /* (AC6) OLDI0_A4N */ + AM62X_IOPAD(0x027c, PIN_OUTPUT, 0) /* (AC5) OLDI0_A4P */ + AM62X_IOPAD(0x0288, PIN_OUTPUT, 0) /* (AE5) OLDI0_A5N */ + AM62X_IOPAD(0x0284, PIN_OUTPUT, 0) /* (AD6) OLDI0_A5P */ + AM62X_IOPAD(0x0290, PIN_OUTPUT, 0) /* (AE6) OLDI0_A6N */ + AM62X_IOPAD(0x028c, PIN_OUTPUT, 0) /* (AD7) OLDI0_A6P */ + AM62X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AD8) OLDI0_A7N */ + AM62X_IOPAD(0x0294, PIN_OUTPUT, 0) /* (AE7) OLDI0_A7P */ + AM62X_IOPAD(0x02a0, PIN_OUTPUT, 0) /* (AD4) OLDI0_CLK0N */ + AM62X_IOPAD(0x029c, PIN_OUTPUT, 0) /* (AE3) OLDI0_CLK0P */ + AM62X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (AE4) OLDI0_CLK1N */ + AM62X_IOPAD(0x02a4, PIN_OUTPUT, 0) /* (AD5) OLDI0_CLK1P */ + >; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&main_oldi0_pins_default &main_dss0_pins_default>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: LVDS Output (OLDI TX 0) */ + port@0 { + reg = <0>; + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; + + /* VP1: LVDS Output (OLDI TX 1) */ + port@2 { + reg = <2>; + oldi_out1: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&exp1>; + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-microtips-mf103hie-lcd2.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-microtips-mf103hie-lcd2.dtso @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Microtips integrated OLDI panel (MF-103HIEB0GA0) (SK-LCD2) DT overlay for AM625-SK and AM62-LP SK + * + * AM625-SKEVM: https://www.ti.com/tool/SK-AM62 + * AM62-LP SKEVM: https://www.ti.com/tool/SK-AM62-LP + * Panel datasheet: https://simplespec.microtipsusa.com/uploads/spec/datasheetFile/2660/13-103HIEB0GA0-S_V1.0_20211206.pdf + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + display { + compatible = "microtips,mf-103hieb0ga0"; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * But swapping them will cause an error in the dss driver. + */ + port@0 { + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + port@1 { + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_out1>; + }; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: LVDS Output (OLDI TX 0) */ + port@0 { + reg = <0>; + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; + + /* VP1: LVDS Output (OLDI TX 1) */ + port@2 { + reg = <2>; + oldi_out1: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-pwm.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-pwm.dtso @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling PWM output on RPi header on AM625-SK board. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + main_epwm0_pins_default: main-epwm0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01ac, PIN_OUTPUT, 6) /* (E19) MCASP0_AFSR.EHRPWM0_A */ + >; + }; + main_epwm1_pins_default: main-epwm1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01a0, PIN_OUTPUT, 6) /* (E18) MCASP0_AXR0.EHRPWM1_B */ + >; + }; + main_ecap1_pins_default: main-ecap1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01a4, PIN_OUTPUT, 2) /* (B20) MCASP0_ACLKX.ECAP2_IN_APWM_OUT */ + >; + }; +}; + +&main_i2c1 { + gpio@22 { + fet_sel { + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "UART1_FET_SEL"; + }; + }; +}; + +&epwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm0_pins_default>; + status = "okay"; +}; + +&epwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm1_pins_default>; + status = "okay"; +}; + +&ecap2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap1_pins_default>; + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-rpi-hdr-ehrpwm.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk-rpi-hdr-ehrpwm.dtso @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling RPi header with GPIOs and eHRPWMs for AM625-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0038, PIN_INPUT, 7) /* (E24) OSPI0_CSn3.GPIO0_14 */ + AM62X_IOPAD(0x0088, PIN_INPUT, 7) /* (L24) GPMC0_OEn_REn.GPIO0_33 */ + AM62X_IOPAD(0x0094, PIN_INPUT, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ + AM62X_IOPAD(0x009c, PIN_INPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ + AM62X_IOPAD(0x00a0, PIN_INPUT, 7) /* (K25) GPMC0_WPn.GPIO0_39 */ + AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ + AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ + AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ + >; + }; + + rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d0, PIN_INPUT, 7) /* (A15) UART0_CTSn.GPIO1_22 */ + >; + }; + + rpi_header_ehrpwm0_pins_default: rpi-header-ehrpwm0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01ac, PIN_OUTPUT, 6) /* (E19) MCASP0_AFSR.EHRPWM0_A */ + AM62X_IOPAD(0x01b0, PIN_OUTPUT, 6) /* (A20) MCASP0_ACLKR.EHRPWM0_B */ + >; + }; + + rpi_header_ehrpwm1_pins_default: rpi-header-ehrpwm1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x019c, PIN_OUTPUT, 6) /* (B18) MCASP0_AXR1.EHRPWM1_A */ + AM62X_IOPAD(0x01a0, PIN_OUTPUT, 6) /* (E18) MCASP0_AXR0.EHRPWM1_B */ + >; + }; +}; + +&main_i2c1 { + gpio@22 { + p05-hog { + /* P05 - EXP_PS_3V3_EN */ + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_3V3_EN"; + }; + + p06-hog { + /* P06 - EXP_PS_5V0_EN */ + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_5V0_EN"; + }; + + p25-hog { + /* P25 - UART1_FET_SEL */ + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "UART1_FET_SEL"; + }; + }; +}; + +&epwm0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm0_pins_default>; +}; + +&epwm1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm1_pins_default>; +}; + + +&main_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; + +&main_gpio1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio1_pins_default>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -7,28 +7,19 @@ /dts-v1/; -#include -#include -#include -#include "k3-am625.dtsi" +#include "k3-am62x-sk-common.dtsi" / { compatible = "ti,am625-sk", "ti,am625"; model = "Texas Instruments AM625 SK"; - aliases { - serial2 = &main_uart0; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - mmc2 = &sdhci2; - spi0 = &ospi0; - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + opp-table { + /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; }; memory@80000000 { @@ -38,39 +29,6 @@ }; - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ramoops@9ca00000 { - compatible = "ramoops"; - reg = <0x00 0x9ca00000 0x00 0x00100000>; - record-size = <0x8000>; - console-size = <0x8000>; - ftrace-size = <0x00>; - pmsg-size = <0x8000>; - }; - - secure_tfa_ddr: tfa@9e780000 { - reg = <0x00 0x9e780000 0x00 0x80000>; - alignment = <0x1000>; - no-map; - }; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ - alignment = <0x1000>; - no-map; - }; - - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9db00000 0x00 0xc00000>; - no-map; - }; - }; - vmain_pd: regulator-0 { /* TPS65988 PD CONTROLLER OUTPUT */ compatible = "regulator-fixed"; @@ -130,107 +88,51 @@ <3300000 0x1>; }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&usr_led_pins_default>; - - led-0 { - label = "am62-sk:green:heartbeat"; - gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - function = LED_FUNCTION_HEARTBEAT; - default-state = "off"; - }; - }; -}; - -&main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ - AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ - >; - }; - - main_i2c0_pins_default: main-i2c0-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ - AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ - AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ - >; - }; - - main_i2c2_pins_default: main-i2c2-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ - AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ - >; - }; - - main_mmc0_pins_default: main-mmc0-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ - AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ - AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ - AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ - AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ - AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ - AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ - AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ - AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ - AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ - >; - }; - - main_mmc1_pins_default: main-mmc1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ - AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ - AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ - AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ - AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ - AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ - AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ - >; + vcc_1v8: regulator-5 { + /* output of TPS6282518DMQ */ + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + regulator-boot-on; }; - usr_led_pins_default: usr-led-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ - >; + wlan_lten: regulator-6 { + compatible = "regulator-fixed"; + regulator-name = "wlan_lten"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_sys>; + gpios = <&exp1 11 GPIO_ACTIVE_LOW>; }; - main_mdio1_pins_default: main-mdio1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ - AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ - >; + wlan_en: regulator-7 { + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&wlan_lten>; + enable-active-high; + gpios = <&main_gpio0 71 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_pins_default>; }; - main_rgmii1_pins_default: main-rgmii1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ - AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ - AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ - AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ - AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ - AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ - AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ - AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ - AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ - AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ - AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ - AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ - >; + vdd_core: regulator-8 { + /* output of TPS62826DMQ */ + compatible = "regulator-fixed"; + regulator-name = "vdd_core"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + regulator-boot-on; }; +}; +&main_pmx0 { main_rgmii2_pins_default: main-rgmii2-pins-default { pinctrl-single,pins = < AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ @@ -275,66 +177,33 @@ AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ >; }; -}; -&wkup_uart0 { - /* WKUP UART0 is used by DM firmware */ - status = "reserved"; -}; - -&mcu_uart0 { - status = "disabled"; -}; - -&main_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; -}; - -&main_uart1 { - /* Main UART1 is used by TIFS firmware */ - status = "reserved"; -}; - -&main_uart2 { - status = "disabled"; -}; - -&main_uart3 { - status = "disabled"; -}; - -&main_uart4 { - status = "disabled"; -}; - -&main_uart5 { - status = "disabled"; -}; - -&main_uart6 { - status = "disabled"; -}; - -&mcu_i2c0 { - status = "disabled"; -}; + wlan_en_pins_default: wlan-en-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x124, PIN_OUTPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */ + >; + }; -&wkup_i2c0 { - status = "disabled"; -}; + main_mmc2_pins_default: main-mmc2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ + AM62X_IOPAD(0x118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ + AM62X_IOPAD(0x114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */ + AM62X_IOPAD(0x110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */ + AM62X_IOPAD(0x10c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */ + AM62X_IOPAD(0x108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */ + AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ + >; + }; -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; + main_wlirq_pins_default: main-wlirq-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x128, PIN_INPUT, 7) /* (B23) MMC2_SDWP.GPIO0_72 */ + >; + }; }; &main_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - exp1: gpio@22 { compatible = "ti,tca6424"; reg = <0x22>; @@ -348,7 +217,7 @@ "UART1_FET_BUF_EN", "WL_LT_EN", "GPIO_HDMI_RSTn", "CSI_GPIO1", "CSI_GPIO2", "PRU_3V3_EN", - "HDMI_INTn", "TEST_GPIO2", + "HDMI_INTn", "PD_I2C_IRQ", "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", "MCASP1_FET_SEL", "UART1_FET_SEL", "TSINT#", "IO_EXP_TEST_LED"; @@ -363,41 +232,45 @@ }; }; -&main_i2c2 { - status = "disabled"; -}; - -&main_i2c3 { - status = "disabled"; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc0_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - &sdhci1 { - /* SD/MMC */ vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv>; +}; + +&sdhci2 { + status = "okay"; + vmmc-supply = <&wlan_en>; pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; + pinctrl-0 = <&main_mmc2_pins_default>; + bus-width = <4>; + non-removable; + ti,fails-without-test-cd; + cap-power-off-card; + keep-power-in-suspend; + assigned-clocks = <&k3_clks 157 158>; + assigned-clock-parents = <&k3_clks 157 160>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&main_wlirq_pins_default>; + interrupt-parent = <&main_gpio0>; + interrupts = <72 IRQ_TYPE_EDGE_RISING>; + }; }; &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&main_mdio1_pins_default - &main_rgmii1_pins_default + pinctrl-0 = <&main_rgmii1_pins_default &main_rgmii2_pins_default>; -}; -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy0>; + cpts@3d000 { + /* MAP HW3_TS_PUSH to GENF1 */ + ti,pps = <2 1>; + }; }; &cpsw_port2 { @@ -406,13 +279,6 @@ }; &cpsw3g_mdio { - cpsw3g_phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - }; - cpsw3g_phy1: ethernet-phy@1 { reg = <1>; ti,rx-internal-delay = ; @@ -421,14 +287,8 @@ }; }; -&mailbox0_cluster0 { - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; @@ -487,30 +347,22 @@ }; }; -&ecap0 { - status = "disabled"; -}; - -&ecap1 { - status = "disabled"; -}; - -&ecap2 { - status = "disabled"; -}; - -&main_mcan0 { - status = "disabled"; +&tlv320aic3106 { + DVDD-supply = <&vcc_1v8>; }; -&epwm0 { - status = "disabled"; -}; +#define K3_TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val) -&epwm1 { - status = "disabled"; -}; +×ync_router { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_cpts>; -&epwm2 { - status = "disabled"; + /* Use Time Sync Router to map GENF1 input to HW3_TS_PUSH output */ + cpsw_cpts: cpsw-cpts { + pinctrl-single,pins = < + /* pps [cpsw cpts genf1] in17 -> out12 [cpsw cpts hw3_push] */ + K3_TS_OFFSET(12, 17) + >; + }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am625.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -48,6 +48,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 135 0>; }; cpu1: cpu@1 { @@ -62,6 +64,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 136 0>; }; cpu2: cpu@2 { @@ -76,6 +80,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 137 0>; }; cpu3: cpu@3 { @@ -90,11 +96,57 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 138 0>; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&wkup_conf>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; }; }; L2_0: l2-cache0 { compatible = "cache"; + cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -48,6 +48,36 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x20000>; + + phy_gmii_sel: phy@4044 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4044 0x8>; + #phy-cells = <1>; + }; + + epwm_tbclk: clock-controller@4130 { + compatible = "ti,am62-epwm-tbclk"; + reg = <0x4130 0x4>; + #clock-cells = <1>; + }; + + audio_refclk0: clock@82e0 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e0 0x4>; + clocks = <&k3_clks 157 0>; + assigned-clocks = <&k3_clks 157 0>; + assigned-clock-parents = <&k3_clks 157 8>; + #clock-cells = <0>; + }; + + audio_refclk1: clock@82e4 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e4 0x4>; + clocks = <&k3_clks 157 10>; + assigned-clocks = <&k3_clks 157 10>; + assigned-clock-parents = <&k3_clks 157 18>; + #clock-cells = <0>; + }; }; dmss: bus@48000000 { @@ -69,6 +99,105 @@ interrupt-names = "rx_012"; interrupts = ; }; + + inta_main_dmss: interrupt-controller@48000000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x48000000 0x00 0x100000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <28>; + ti,interrupt-ranges = <6 70 34>; + ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; + }; + + main_bcdma: dma-controller@485c0100 { + compatible = "ti,am64-dmss-bcdma"; + reg = <0x00 0x485c0100 0x00 0x100>, + <0x00 0x4c000000 0x00 0x20000>, + <0x00 0x4a820000 0x00 0x20000>, + <0x00 0x4aa40000 0x00 0x20000>, + <0x00 0x4bc00000 0x00 0x100000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <3>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <26>; + ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ + ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ + ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ + }; + + main_pktdma: dma-controller@485c0000 { + compatible = "ti,am64-dmss-pktdma"; + reg = <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x40000>, + <0x00 0x4b800000 0x00 0x400000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <2>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <30>; + ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ + <0x24>, /* CPSW_TX_CHAN */ + <0x25>, /* SAUL_TX_0_CHAN */ + <0x26>; /* SAUL_TX_1_CHAN */ + ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ + <0x11>, /* RING_CPSW_TX_CHAN */ + <0x12>, /* RING_SAUL_TX_0_CHAN */ + <0x13>; /* RING_SAUL_TX_1_CHAN */ + ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ + <0x2b>, /* CPSW_RX_CHAN */ + <0x2d>, /* SAUL_RX_0_CHAN */ + <0x2f>, /* SAUL_RX_1_CHAN */ + <0x31>, /* SAUL_RX_2_CHAN */ + <0x33>; /* SAUL_RX_3_CHAN */ + ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ + <0x2c>, /* FLOW_CPSW_RX_CHAN */ + <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ + <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ + }; + }; + + dmss_csi: bus@4e000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>; + + ti,sci-dev-id = <198>; + + inta_main_dmss_csi: interrupt-controller@4e0a0000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x4e0a0000 0x00 0x8000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <200>; + ti,interrupt-ranges = <0 237 8>; + ti,unmapped-event-sources = <&main_bcdma_csi>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + }; + + main_bcdma_csi: dma-controller@4e230000 { + compatible = "ti,am62a-dmss-bcdma-csirx"; + reg = <0x00 0x4e230000 0x00 0x100>, + <0x00 0x4e180000 0x00 0x8000>, + <0x00 0x4e100000 0x00 0x10000>; + reg-names = "gcfg", "rchanrt", "ringrt"; + msi-parent = <&inta_main_dmss_csi>; + #dma-cells = <3>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <199>; + ti,sci-rm-range-rchan = <0x21>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + }; }; dmsc: system-controller@44043000 { @@ -96,12 +225,123 @@ }; }; + crypto: crypto@40900000 { + compatible = "ti,am62-sa3ul"; + reg = <0x00 0x40900000 0x00 0x1200>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; + + dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, + <&main_pktdma 0x7507 0>; + dma-names = "tx", "rx1", "rx2"; + }; + main_pmx0: pinctrl@f4000 { - compatible = "pinctrl-single"; - reg = <0x00 0xf4000 0x00 0x2ac>; + compatible = "ti,am6-padconf"; + reg = <0x00 0xf4000 0x00 0x25c>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 36 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 2>; + assigned-clock-parents = <&k3_clks 36 3>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 37 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 37 2>; + assigned-clock-parents = <&k3_clks 37 3>; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 38 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 38 2>; + assigned-clock-parents = <&k3_clks 38 3>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 39 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 39 2>; + assigned-clock-parents = <&k3_clks 39 3>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 40 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 40 2>; + assigned-clock-parents = <&k3_clks 40 3>; + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 41 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 41 2>; + assigned-clock-parents = <&k3_clks 41 3>; + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 42 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 42 2>; + assigned-clock-parents = <&k3_clks 42 3>; + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 43 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 43 2>; + assigned-clock-parents = <&k3_clks 43 3>; + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; }; main_uart0: serial@2800000 { @@ -222,6 +462,39 @@ status = "disabled"; }; + main_spi0: spi@20100000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x20100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 141 0>; + status = "disabled"; + }; + + main_spi1: spi@20110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 142 0>; + status = "disabled"; + }; + + main_spi2: spi@20120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 143 0>; + status = "disabled"; + }; + main_gpio_intr: interrupt-controller@a00000 { compatible = "ti,sci-intr"; reg = <0x00 0x00a00000 0x00 0x800>; @@ -271,6 +544,24 @@ status = "disabled"; }; + sdhci0: mmc@fa10000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; + interrupts = ; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 57 6>; + assigned-clock-parents = <&k3_clks 57 8>; + mmc-hs200-1_8v; + bus-width = <8>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-hs200 = <0x6>; + status = "disabled"; + }; + sdhci1: mmc@fa00000 { compatible = "ti,am62-sdhci"; reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; @@ -278,8 +569,9 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; - ti,otap-del-sel-legacy = <0x0>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; @@ -290,9 +582,530 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; + status = "disabled"; + }; + + sdhci2: mmc@fa20000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>; + interrupts = ; + power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; + clock-names = "clk_ahb", "clk_xin"; bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; no-1-8-v; status = "disabled"; }; + + usbss0: dwc3-usb@f900000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f900000 0x00 0x800>, + <0x00 0x0f908000 0x00 0x400>; + clocks = <&k3_clks 161 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb0: usb@31000000 { + compatible = "snps,dwc3"; + reg =<0x00 0x31000000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + usbss1: dwc3-usb@f910000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; + clocks = <&k3_clks 162 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb1: usb@31100000 { + compatible = "snps,dwc3"; + reg =<0x00 0x31100000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + fss: bus@fc00000 { + compatible = "simple-bus"; + reg = <0x00 0x0fc00000 0x00 0x70000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + ospi0: spi@fc40000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 75 7>; + assigned-clocks = <&k3_clks 75 7>; + assigned-clock-parents = <&k3_clks 75 8>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cpsw3g: ethernet@8000000 { + compatible = "ti,am642-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x8000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; + clocks = <&k3_clks 13 0>; + assigned-clocks = <&k3_clks 13 3>; + assigned-clock-parents = <&k3_clks 13 11>; + clock-names = "fck"; + power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + dmas = <&main_pktdma 0xc600 15>, + <&main_pktdma 0xc601 15>, + <&main_pktdma 0xc602 15>, + <&main_pktdma 0xc603 15>, + <&main_pktdma 0xc604 15>, + <&main_pktdma 0xc605 15>, + <&main_pktdma 0xc606 15>, + <&main_pktdma 0xc607 15>, + <&main_pktdma 0x4600 15>; + dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", + "tx7", "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + phys = <&phy_gmii_sel 1>; + mac-address = [00 00 00 00 00 00]; + ti,syscon-efuse = <&wkup_conf 0x200>; + }; + + cpsw_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + phys = <&phy_gmii_sel 2>; + mac-address = [00 00 00 00 00 00]; + }; + }; + + cpsw3g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x0 0xf00 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 13 0>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x0 0x3d000 0x0 0x400>; + clocks = <&k3_clks 13 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + + timesync_router: pinctrl@a40000 { + compatible = "pinctrl-single"; + reg = <0x0 0xa40000 0x0 0x800>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000107ff>; + status = "disabled"; + }; + + hwspinlock: spinlock@2a000000 { + compatible = "ti,am64-hwspinlock"; + reg = <0x00 0x2a000000 0x00 0x1000>; + #hwlock-cells = <1>; + }; + + mailbox0_cluster0: mailbox@29000000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29000000 0x00 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster1: mailbox@29010000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29010000 0x00 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster2: mailbox@29020000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29020000 0x00 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster3: mailbox@29030000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29030000 0x00 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + main_mcan0: can@20701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + epwm0: pwm@23000000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23000000 0x00 0x100>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm1: pwm@23010000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23010000 0x00 0x100>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm2: pwm@23020000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23020000 0x00 0x100>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + ecap0: pwm@23100000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23100000 0x00 0x100>; + power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 51 0>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap1: pwm@23110000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23110000 0x00 0x100>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 52 0>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap2: pwm@23120000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23120000 0x00 0x100>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 53 0>; + clock-names = "fck"; + status = "disabled"; + }; + + eqep0: counter@23200000 { + compatible = "ti,am3352-eqep"; + reg = <0x00 0x23200000 0x00 0x100>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 59 0>; + clock-names = "fck"; + interrupts = ; + status = "disabled"; + }; + + eqep1: counter@23210000 { + compatible = "ti,am3352-eqep"; + reg = <0x00 0x23210000 0x00 0x100>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 60 0>; + clock-names = "fck"; + interrupts = ; + status = "disabled"; + }; + + eqep2: counter@23220000 { + compatible = "ti,am3352-eqep"; + reg = <0x00 0x23220000 0x00 0x100>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 62 0>; + clock-names = "fck"; + interrupts = ; + status = "disabled"; + }; + + mcasp0: audio-controller@2b00000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b00000 0x00 0x2000>, + <0x00 0x02b08000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 190 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 190 0>; + assigned-clock-parents = <&k3_clks 190 2>; + power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp1: audio-controller@2b10000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b10000 0x00 0x2000>, + <0x00 0x02b18000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 191 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 191 0>; + assigned-clock-parents = <&k3_clks 191 2>; + power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp2: audio-controller@2b20000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b20000 0x00 0x2000>, + <0x00 0x02b28000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 192 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 192 0>; + assigned-clock-parents = <&k3_clks 192 2>; + power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + ti_csi2rx0: ticsi2rx@30102000 { + compatible = "ti,j721e-csi2rx"; + dmas = <&main_bcdma_csi 0 0x5000 0>, <&main_bcdma_csi 0 0x5001 0>, + <&main_bcdma_csi 0 0x5002 0>, <&main_bcdma_csi 0 0x5003 0>, + <&main_bcdma_csi 0 0x5004 0>, <&main_bcdma_csi 0 0x5005 0>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5"; + reg = <0x00 0x30102000 0x00 0x1000>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@30101000 { + compatible = "cdns,csi2rx"; + reg = <0x00 0x30101000 0x00 0x1000>; + clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, + <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@30110000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30110000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dss: dss@30200000 { + compatible = "ti,am62a7-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: OLDI: Tied OFF */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2", "common1"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&k3_clks 186 0>, + <&k3_clks 186 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = ; + + dss_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + vpu: video-codec@30210000 { + compatible = "cnm,cm521c-vpu"; + reg = <0x00 0x30210000 0x00 0x10000>; + clocks = <&k3_clks 204 2>; + clock-names = "vcodec"; + power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; + sram=<&oc_sram>; + sram-size=<0xf800>; + operating-points-v2 = <&vpu_opp_table>; + vpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-20000000 { + opp-hz = /bits/ 64 <20000000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + }; + }; + + e5010: e5010@fd20000 { + compatible = "img,e5010-jpeg-enc"; + reg = <0x00 0xfd20000 0x00 0x100>, + <0x00 0xfd20200 0x00 0x200>; + reg-names = "regjasper", "regmmu"; + clocks = <&k3_clks 201 0>; + clock-names = "core_clk"; + power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; + interrupts = ; + }; + + c7x_0: dsp@7e000000 { + compatible = "ti,am62a-c7xv-dsp"; + reg = <0x00 0x7e000000 0x00 0x00100000>; + reg-names = "l2sram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <208>; + ti,sci-proc-ids = <0x04 0xff>; + resets = <&k3_reset 208 1>; + firmware-name = "am62a-c71_0-fw"; + }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -6,6 +6,18 @@ */ &cbass_mcu { + mcu_ram: sram@79100000 { + compatible = "mmio-sram"; + reg = <0x00 0x79100000 0x00 0x80000>; + ranges = <0x00 0x00 0x79100000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + + mcu_sram1@0 { + reg = <0x0 0x80000>; + }; + }; + mcu_pmx0: pinctrl@4084000 { compatible = "pinctrl-single"; reg = <0x00 0x04084000 0x00 0x88>; @@ -15,6 +27,51 @@ status = "disabled"; }; + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@4800000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4800000 0x00 0x400>; + clocks = <&k3_clks 35 2>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@4810000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4810000 0x00 0x400>; + clocks = <&k3_clks 48 2>; + clock-names = "fck"; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@4820000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4820000 0x00 0x400>; + clocks = <&k3_clks 49 2>; + clock-names = "fck"; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@4830000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4830000 0x00 0x400>; + clocks = <&k3_clks 50 2>; + clock-names = "fck"; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + mcu_uart0: serial@4a00000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; @@ -36,4 +93,106 @@ clock-names = "fck"; status = "disabled"; }; + + mcu_spi0: spi@4b00000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x04b00000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 147 0>; + status = "disabled"; + }; + + mcu_spi1: spi@4b10000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x04b10000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 148 0>; + status = "disabled"; + }; + + mcu_gpio_intr: interrupt-controller@4210000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x04210000 0x00 0x200>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <5>; + ti,interrupt-ranges = <0 104 4>; + }; + + mcu_gpio0: gpio@4201000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x04201000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&mcu_gpio_intr>; + interrupts = <30>, <31>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <24>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 79 0>; + clock-names = "gpio"; + status = "disabled"; + }; + + mcu_r5fss0: r5fss@79000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x79000000 0x00 0x79000000 0x8000>, + <0x79020000 0x00 0x79020000 0x8000>; + power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + mcu_r5fss0_core0: r5f@79000000 { + compatible = "ti,am62-r5f"; + reg = <0x79000000 0x00008000>, + <0x79020000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <9>; + ti,sci-proc-ids = <0x03 0xff>; + resets = <&k3_reset 9 1>; + firmware-name = "am62a-mcu-r5f0_0-fw"; + ti,atcm-enable = <0>; + ti,btcm-enable = <1>; + ti,loczrama = <0>; + sram = <&mcu_ram>; + wakeup-source; + }; + }; + + mcu_mcan0: can@4e08000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e08000 0x00 0x200>, + <0x00 0x4e00000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + wakeup-source; + status = "disabled"; + }; + + mcu_mcan1: can@4e18000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e18000 0x00 0x200>, + <0x00 0x4e10000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + wakeup-source; + status = "disabled"; + }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -5,6 +5,8 @@ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ +#include + &cbass_wakeup { wkup_conf: syscon@43000000 { compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; @@ -17,21 +19,51 @@ compatible = "ti,am654-chipid"; reg = <0x14 0x4>; }; + + usb0_phy_ctrl: syscon@4008 { + compatible = "syscon"; + reg = <0x4008 0x4>; + }; + + usb1_phy_ctrl: syscon@4018 { + compatible = "syscon"; + reg = <0x4018 0x4>; + }; }; - wkup_uart0: serial@2b300000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x2b300000 0x00 0x100>; - interrupts = ; + target-module@2b300050 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0 0x2b300050 0 0x4>, + <0 0x2b300054 0 0x4>, + <0 0x2b300058 0 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + ti,no-reset-on-init; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; - clock-names = "fclk"; - status = "disabled"; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2b300000 0x100000>; + + wkup_uart0: serial@0 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0 0x100>; + interrupts = ; + status = "disabled"; + }; }; wkup_i2c0: i2c@2b200000 { compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02b200000 0x00 0x100>; + reg = <0x00 0x2b200000 0x00 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -49,6 +81,36 @@ clock-names = "vbus", "osc32k"; power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; wakeup-source; - status = "disabled"; + }; + + wkup_r5fss0: r5fss@78000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + wkup_r5fss0_core0: r5f@78000000 { + compatible = "ti,am62-r5f"; + reg = <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <121>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 121 1>; + firmware-name = "am62-wkup-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + wkup_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am62a.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a.dtsi @@ -8,9 +8,10 @@ #include #include #include -#include #include +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 AM62A SoC"; compatible = "ti,am62a7"; @@ -60,6 +61,8 @@ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ + <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */ + <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */ <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ @@ -114,9 +117,15 @@ <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ }; }; + + #include "k3-am62a-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ #include "k3-am62a-main.dtsi" #include "k3-am62a-mcu.dtsi" #include "k3-am62a-wakeup.dtsi" + +&dmsc { + ti,partial-io-wakeup-sources = <&mcu_mcan0>, <&mcu_mcan1>, <&mcu_uart0>, <&wkup_uart0>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7-sk-csi2-ox05b1s.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7-sk-csi2-ox05b1s.dtso @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OX05B1S Camera Module + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ox05b1s_fixed: ox05b1s-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + /* CAM port */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ox05b1s: camera@36 { + compatible = "ovti,ox05b"; + reg = <0x36>; + + clocks = <&clk_ox05b1s_fixed>; + clock-names = "inck"; + + pwdn-gpios = <&exp1 13 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <480000000>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7-sk-e3-max-opp.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7-sk-e3-max-opp.dtso @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay to run AM62A7-SK Rev E3 board at maximum performance + * Requires VDD_CORE to be at 0.85V + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + opp-table { + /* + * Add 1.4GHz and disable lower OPPs for max A53 performance + * Only for AM62A7-SK Rev E3 board + * Requires VDD_CORE to be at 0.85V + */ + opp-200000000 { + status = "disabled"; + }; + + opp-400000000 { + status = "disabled"; + }; + + opp-600000000 { + status = "disabled"; + }; + + opp-800000000 { + status = "disabled"; + }; + + opp-1000000000 { + status = "disabled"; + }; + + opp-1250000000 { + status = "disabled"; + }; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; +}; + +&c7x_0 { + /* + * Override C7x frequency to 1 GHz for max performance + * Only for AM62A7-SK Rev E3 board + * Requires VDD_CORE to be at 0.85V + */ + clocks = <&k3_clks 208 0>; + assigned-clocks = <&k3_clks 208 0>; + assigned-clock-rates = <1000000000>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for second CPSW3G port in RGMII mode using SK-ETHERNET-DC01 + * Add-On Daughtercard with AM62A7-SK. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@f0000/ethernet@8000000/ethernet-ports/port@2"; + }; +}; + +&cpsw3g { + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; +}; + +&cpsw_port2 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + #address-cells = <1>; + #size-cells = <0>; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&main_pmx0 { + main_rgmii2_pins_default: main-rgmii2-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x0184, PIN_INPUT, 0) /* (AA21) RGMII2_RD0 */ + AM62AX_IOPAD(0x0188, PIN_INPUT, 0) /* (Y20) RGMII2_RD1 */ + AM62AX_IOPAD(0x018c, PIN_INPUT, 0) /* (AB21) RGMII2_RD2 */ + AM62AX_IOPAD(0x0190, PIN_INPUT, 0) /* (AB20) RGMII2_RD3 */ + AM62AX_IOPAD(0x0180, PIN_INPUT, 0) /* (AA20) RGMII2_RXC */ + AM62AX_IOPAD(0x017c, PIN_INPUT, 0) /* (W18) RGMII2_RX_CTL */ + AM62AX_IOPAD(0x016c, PIN_INPUT, 0) /* (AA19) RGMII2_TD0 */ + AM62AX_IOPAD(0x0170, PIN_INPUT, 0) /* (Y18) RGMII2_TD1 */ + AM62AX_IOPAD(0x0174, PIN_INPUT, 0) /* (AA18) RGMII2_TD2 */ + AM62AX_IOPAD(0x0178, PIN_INPUT, 0) /* (W17) RGMII2_TD3 */ + AM62AX_IOPAD(0x0168, PIN_INPUT, 0) /* (AB19) RGMII2_TXC */ + AM62AX_IOPAD(0x0164, PIN_INPUT, 0) /* (Y19) RGMII2_TX_CTL */ + >; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion.dtso @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Fusion (FPD-Link III) board on SK-AM62A + * https://svtronics.com/portfolio/evm577pfusion-v1-0-fusion/ + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&exp2 { + p19-hog { + /* P19 - CSI_SEL2 */ + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "CSI_SEL2"; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deser@3d { + compatible = "ti,ds90ub960-q1"; + reg = <0x3d>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + ds90ub960_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + ds90ub960_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7-sk-rpi-hdr-ehrpwm.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7-sk-rpi-hdr-ehrpwm.dtso @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling RPi header with GPIOs and eHRPWMs on AM62A-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x0038, PIN_INPUT, 7) /* (G20) OSPI0_CSn3.GPIO0_14 */ + AM62AX_IOPAD(0x0088, PIN_INPUT, 7) /* (L17) GPMC0_OEn_REn.GPIO0_33 */ + AM62AX_IOPAD(0x0094, PIN_INPUT, 7) /* (M18) GPMC0_BE1n.GPIO0_36 */ + AM62AX_IOPAD(0x009c, PIN_INPUT, 7) /* (R17) GPMC0_WAIT1.GPIO0_38 */ + AM62AX_IOPAD(0x00a0, PIN_INPUT, 7) /* (K17) GPMC0_WPn.GPIO0_39 */ + AM62AX_IOPAD(0x00a4, PIN_INPUT, 7) /* (K18) GPMC0_DIR.GPIO0_40 */ + AM62AX_IOPAD(0x00a8, PIN_INPUT, 7) /* (M19) GPMC0_CSn0.GPIO0_41 */ + AM62AX_IOPAD(0x00ac, PIN_INPUT, 7) /* (M21) GPMC0_CSn1.GPIO0_42 */ + >; + }; + + rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x0194, PIN_INPUT, 7) /* (C19) MCASP0_AXR3.GPIO1_7 */ + AM62AX_IOPAD(0x0198, PIN_INPUT, 7) /* (B19) MCASP0_AXR2.GPIO1_8 */ + AM62AX_IOPAD(0x01a4, PIN_INPUT, 7) /* (A19) MCASP0_ACLKX.GPIO1_11 */ + AM62AX_IOPAD(0x01b4, PIN_INPUT, 7) /* (D16) SPI0_CS0.GPIO1_15 */ + AM62AX_IOPAD(0x01b8, PIN_INPUT, 7) /* (C16) SPI0_CS1.GPIO1_16 */ + AM62AX_IOPAD(0x01bc, PIN_INPUT, 7) /* (A17) SPI0_CLK.GPIO1_17 */ + AM62AX_IOPAD(0x01c0, PIN_INPUT, 7) /* (B15) SPI0_D0.GPIO1_18 */ + AM62AX_IOPAD(0x01c4, PIN_INPUT, 7) /* (E15) SPI0_D1.GPIO1_19 */ + AM62AX_IOPAD(0x01d0, PIN_INPUT, 7) /* (F14) UART0_CTSn.GPIO1_22 */ + AM62AX_IOPAD(0x01d8, PIN_INPUT, 7) /* (B17) MCAN0_TX.GPIO1_24 */ + AM62AX_IOPAD(0x01dc, PIN_INPUT, 7) /* (C18) MCAN0_RX.GPIO1_25 */ + >; + }; + + rpi_header_ehrpwm0_pins_default: rpi-header-ehrpwm0-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x01ac, PIN_OUTPUT, 6) /* (B21) MCASP0_AFSR.EHRPWM0_A */ + AM62AX_IOPAD(0x01b0, PIN_OUTPUT, 6) /* (A21) MCASP0_ACLKR.EHRPWM0_B */ + >; + }; + + rpi_header_ehrpwm1_pins_default: rpi-header-ehrpwm1-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x019c, PIN_OUTPUT, 6) /* (B18) MCASP0_AXR1.EHRPWM1_A */ + AM62AX_IOPAD(0x01a0, PIN_OUTPUT, 6) /* (B20) MCASP0_AXR0.EHRPWM1_B */ + >; + }; +}; + +&main_i2c1 { + gpio@22 { + p05-hog { + /* P05 - EXP_PS_3V3_EN */ + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_3V3_EN"; + }; + + p06-hog { + /* P06 - EXP_PS_5V0_EN */ + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_5V0_EN"; + }; + + p25-hog { + /* P25 - UART1_FET_SEL */ + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "UART1_FET_SEL"; + }; + }; +}; + +&epwm0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm0_pins_default>; +}; + +&epwm1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm1_pins_default>; +}; + + +&main_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; + +&main_gpio1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio1_pins_default>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7-sk-ub954-evm.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7-sk-ub954-evm.dtso @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for DS90UB954-Q1EVM FPDLink-III deserializer board on SK-AM62A + * https://www.ti.com/tool/DS90UB954-Q1EVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&exp2 { + p19-hog { + /* P19 - CSI_SEL2 */ + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "CSI_SEL2"; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deser@3d { + compatible = "ti,ds90ub954-q1"; + reg = <0x3d>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + ds90ub960_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@2 { + reg = <2>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + ds90ub960_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -9,6 +9,7 @@ #include #include +#include #include "k3-am62a7.dtsi" / { @@ -16,8 +17,13 @@ model = "Texas Instruments AM62A7 SK"; aliases { + serial0 = &mcu_uart0; + serial1 = &wkup_uart0; serial2 = &main_uart0; + mmc0 = &sdhci0; mmc1 = &sdhci1; + ethernet0 = &cpsw_port1; + spi0 = &ospi0; }; chosen { @@ -31,11 +37,24 @@ <0x00000008 0x80000000 0x00000000 0x80000000>; }; + dma_buf_phys { + compatible = "ti,dma-buf-phys"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x24000000>; + alloc-ranges = <0x00 0xc0000000 0x00 0x24000000>; + linux,cma-default; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; @@ -48,11 +67,63 @@ no-map; }; + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c900000 0x00 0x01e00000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0x0f00000>; + no-map; + }; + + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99900000 0x00 0x01efffff>; + no-map; + }; + + edgeai_rtos_ipc_memory_region: edgeai-rtos-ipc-memory-region { + reg = <0x00 0xa0000000 0x00 0x01000000>; + no-map; + }; + + edgeai_memory_region: edgeai-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x02000000>; + no-map; + }; + + edgeai_shared_region: edgeai_shared-memories { + compatible = "dma-heap-carveout"; + reg = <0x00 0xa3000000 0x00 0x0b000000>; + }; + + edgeai_core_heaps: edgeai-core-heap-memory@ae000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xae000000 0x00 0x12000000>; + no-map; + }; }; vmain_pd: regulator-0 { @@ -76,10 +147,10 @@ regulator-boot-on; }; - vcc_3v3_sys: regulator-2 { + vcc_3v3_main: regulator-2 { /* output of LM5141-Q1 */ compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sys"; + regulator-name = "vcc_3v3_main"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&vmain_pd>; @@ -98,6 +169,31 @@ gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; }; + vcc_3v3_sys: regulator-4 { + /* output of TPS222965DSGT */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_main>; + regulator-always-on; + regulator-boot-on; + }; + + vddshv_sdio: regulator-5 { + compatible = "regulator-gpio"; + regulator-name = "vddshv_sdio"; + pinctrl-names = "default"; + pinctrl-0 = <&vddshv_sdio_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&ldo1>; + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -111,6 +207,52 @@ default-state = "off"; }; }; + + tlv320_mclk: clk-0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12288000>; + }; + + codec_audio: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM62Ax-SKEVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&tlv320_mclk>; + }; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; }; &main_pmx0 { @@ -159,6 +301,137 @@ AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */ >; }; + + main_usb1_pins_default: main-usb1-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ + >; + }; + + main_mdio1_pins_default: main-mdio1-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ + AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ + >; + }; + + main_rgmii1_pins_default: main-rgmii1-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */ + AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */ + AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */ + AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */ + AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */ + AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */ + AM62AX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */ + AM62AX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */ + AM62AX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */ + AM62AX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */ + AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */ + AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */ + >; + }; + + main_mcasp1_pins_default: main-mcasp1-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x090, PIN_INPUT, 2) /* (L19) GPMC0_BE0n_CLE.MCASP1_ACLKX */ + AM62AX_IOPAD(0x098, PIN_INPUT, 2) /* (R18) GPMC0_WAIT0.MCASP1_AFSX */ + AM62AX_IOPAD(0x08c, PIN_OUTPUT, 2) /* (K19) GPMC0_WEn.MCASP1_AXR0 */ + AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */ + >; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */ + + >; + }; + + main_dss0_pins_default: main-dss0-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x100, PIN_OUTPUT, 0) /* (V17) VOUT0_VSYNC */ + AM62AX_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (T18) VOUT0_HSYNC */ + AM62AX_IOPAD(0x104, PIN_OUTPUT, 0) /* (AA22) VOUT0_PCLK */ + AM62AX_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (U17) VOUT0_DE */ + AM62AX_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62AX_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (U21) VOUT0_DATA1 */ + AM62AX_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (U20) VOUT0_DATA2 */ + AM62AX_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (U19) VOUT0_DATA3 */ + AM62AX_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (T19) VOUT0_DATA4 */ + AM62AX_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (U18) VOUT0_DATA5 */ + AM62AX_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (V22) VOUT0_DATA6 */ + AM62AX_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA7 */ + AM62AX_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V19) VOUT0_DATA8 */ + AM62AX_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (V18) VOUT0_DATA9 */ + AM62AX_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA10 */ + AM62AX_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA11 */ + AM62AX_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (W20) VOUT0_DATA12 */ + AM62AX_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (W19) VOUT0_DATA13 */ + AM62AX_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y21) VOUT0_DATA14 */ + AM62AX_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA15 */ + AM62AX_IOPAD(0x05c, PIN_OUTPUT, 1) /* (P22) GPMC0_AD8.VOUT0_DATA16 */ + AM62AX_IOPAD(0x060, PIN_OUTPUT, 1) /* (R19) GPMC0_AD9.VOUT0_DATA17 */ + AM62AX_IOPAD(0x064, PIN_OUTPUT, 1) /* (R20) GPMC0_AD10.VOUT0_DATA18 */ + AM62AX_IOPAD(0x068, PIN_OUTPUT, 1) /* (R22) GPMC0_AD11.VOUT0_DATA19 */ + AM62AX_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ + AM62AX_IOPAD(0x070, PIN_OUTPUT, 1) /* (R21) GPMC0_AD13.VOUT0_DATA21 */ + AM62AX_IOPAD(0x074, PIN_OUTPUT, 1) /* (T20) GPMC0_AD14.VOUT0_DATA22 */ + AM62AX_IOPAD(0x078, PIN_OUTPUT, 1) /* (T21) GPMC0_AD15.VOUT0_DATA23 */ + >; + }; + + main_mmc0_pins_default: main-mmc0-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */ + AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + vddshv_sdio_pins_default: vddshv-sdio-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ + >; + }; + + ospi0_pins_default: ospi0-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ + AM62AX_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ + AM62AX_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ + AM62AX_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ + AM62AX_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ + AM62AX_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ + AM62AX_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ + AM62AX_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ + AM62AX_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ + AM62AX_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ + >; + }; +}; + +&mcu_pmx0 { + status = "okay"; + + pmic_irq_pins_default: pmic-irq-pins-default { + pinctrl-single,pins = < + AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */ + >; + }; +}; + +&mcu_gpio0 { + status = "okay"; }; &main_i2c0 { @@ -166,6 +439,105 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + + typec_pd0: usb-power-controller@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + port { + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; + + tps659312: pmic@48 { + compatible = "ti,tps6593-q1"; + reg = <0x48>; + ti,primary-pmic; + system-power-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&mcu_gpio0>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + buck123-supply = <&vcc_3v3_sys>; + buck4-supply = <&vcc_3v3_sys>; + buck5-supply = <&vcc_3v3_sys>; + ldo1-supply = <&vcc_3v3_sys>; + ldo2-supply = <&vcc_3v3_sys>; + ldo3-supply = <&buck5>; + ldo4-supply = <&vcc_3v3_sys>; + + regulators { + buck123: buck123 { + regulator-name = "vcc_core"; + regulator-min-microvolt = <715000>; + regulator-max-microvolt = <895000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: buck4 { + regulator-name = "vcc_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: buck5 { + regulator-name = "vcc_1v8_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: ldo1 { + regulator-name = "vddshv5_sdio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: ldo2 { + regulator-name = "vpp_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: ldo3 { + regulator-name = "vcc_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: ldo4 { + regulator-name = "vdda_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &main_i2c1 { @@ -180,6 +552,11 @@ gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&main_gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", "BT_EN_SOC", "MMC1_SD_EN", "VPP_EN", "EXP_PS_3V3_En", @@ -192,16 +569,92 @@ "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", "MCASP1_FET_SEL", "UART1_FET_SEL", "PD_I2C_IRQ", "IO_EXP_TEST_LED"; + + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + }; + + exp2: gpio@23 { + compatible = "ti,tca6424"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "", "", + "", "", + "", "", + "", "", + "WL_LT_EN", "CSI_RSTz", + "", "", + "", "", + "", "", + "SPI0_FET_SEL", "SPI0_FET_OE", + "RGMII2_BRD_CONN_DET", "CSI_SEL2", + "CSI_EN", "AUTO_100M_1000M_CONFIG", + "CSI_VLDO_SEL", "SoC_WLAN_SDIO_RST"; + }; + + tlv320aic3106: audio-codec@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + ai3x-micbias-vg = <1>; /* 2.0V */ + ai3x-ocmv = <1>; /* 1.5V */ + + /* Regulators */ + AVDD-supply = <&vcc_3v3_sys>; + IOVDD-supply = <&vcc_3v3_sys>; + DRVDD-supply = <&vcc_3v3_sys>; + }; + + sii9022: sii9022@3b { + #sound-dai-cells = <0>; + compatible = "sil,sii9022"; + reg = <0x3b>; + + interrupt-parent = <&exp1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + + sil,i2s-data-lanes = < 0 >; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; }; + +}; + +&main_i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; }; &sdhci1 { /* SD/MMC */ status = "okay"; vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vddshv_sdio>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -221,4 +674,239 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + interrupts-extended = <&gic500 GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <&main_pmx0 0x1c8>; /* (D14) UART0_RXD PADCONFIG114 */ + interrupt-names = "irq", "wakeup"; +}; + +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + usb-role-switch; + + port { + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + +&usbss1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; + +&cpsw3g { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>; + + cpts@3d000 { + /* MAP HW3_TS_PUSH to GENF1 */ + ti,pps = <2 1>; + }; +}; + +&cpsw_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&mcasp1 { + status = "okay"; + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp1_pins_default>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <0>; + rx-num-evt = <0>; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&main_dss0_pins_default>; +}; + +&dss_ports { + /* VP2: DPI Output */ + hdmi0_dss: port@0 { + reg = <0>; + + dpi1_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; + +&fss { + status = "okay"; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + flash@0{ + compatible = "spi-nand"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + cdns,phy-mode; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi_nand.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi_nand.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi_nand.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi_nand.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi_nand.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@2000000 { + label = "ospi_nand.rootfs"; + reg = <0x2000000 0x5fc0000>; + }; + + partition@7fc0000 { + label = "ospi_nand.phypattern"; + reg = <0x7fc0000 0x40000>; + }; + }; + }; +}; + +&mailbox0_cluster0 { + ti,mbox-num-fifos = <2>; + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + ti,mbox-num-fifos = <2>; + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + ti,mbox-num-fifos = <2>; + mbox_mcu_r5_0: mbox-mcu_r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&c7x_0 { + mboxes = <&mailbox0_cluster1 &mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +#define K3_TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val) + +×ync_router { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_cpts>; + + /* Use Time Sync Router to map GENF1 input to HW3_TS_PUSH output */ + cpsw_cpts: cpsw-cpts { + pinctrl-single,pins = < + /* pps [cpsw cpts genf1] in17 -> out12 [cpsw cpts hw3_push] */ + K3_TS_OFFSET(12, 17) + >; + }; +}; + +&sdhci0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + disable-wp; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am62a7.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62a7.dtsi @@ -48,6 +48,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 135 0>; }; cpu1: cpu@1 { @@ -62,6 +64,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 136 0>; }; cpu2: cpu@2 { @@ -76,6 +80,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 137 0>; }; cpu3: cpu@3 { @@ -90,11 +96,57 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 138 0>; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&wkup_conf>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; }; }; L2_0: l2-cache0 { compatible = "cache"; + cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -0,0 +1,1239 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P main domain peripherals + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + oc_sram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x00 0x70000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x70000000 0x10000>; + }; + + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = ; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_conf: bus@100000 { + compatible = "simple-bus"; + reg = <0x00 0x00100000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00100000 0x20000>; + + phy_gmii_sel: phy@4044 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4044 0x8>; + #phy-cells = <1>; + }; + + epwm_tbclk: clock-controller@4130 { + compatible = "ti,am62-epwm-tbclk"; + reg = <0x4130 0x4>; + #clock-cells = <1>; + }; + + dss_oldi_io_ctrl: dss-oldi-io-ctrl@8600 { + compatible = "syscon"; + reg = <0x8600 0x200>; + }; + }; + + dmss: bus@48000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; + bootph-all; + + ti,sci-dev-id = <25>; + + secure_proxy_main: mailbox@4d000000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x4d000000 0x00 0x80000>, + <0x00 0x4a600000 0x00 0x80000>, + <0x00 0x4a400000 0x00 0x80000>; + interrupt-names = "rx_012"; + interrupts = ; + bootph-all; + }; + + inta_main_dmss: interrupt-controller@48000000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x48000000 0x00 0x100000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <28>; + ti,interrupt-ranges = <5 69 35>; + ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; + }; + + main_bcdma: dma-controller@485c0100 { + compatible = "ti,am64-dmss-bcdma"; + reg = <0x00 0x485c0100 0x00 0x100>, + <0x00 0x4c000000 0x00 0x20000>, + <0x00 0x4a820000 0x00 0x20000>, + <0x00 0x4aa40000 0x00 0x20000>, + <0x00 0x4bc00000 0x00 0x100000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <3>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <26>; + ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ + ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ + ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ + bootph-all; + }; + + main_pktdma: dma-controller@485c0000 { + compatible = "ti,am64-dmss-pktdma"; + reg = <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x40000>, + <0x00 0x4b800000 0x00 0x400000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <2>; + bootph-all; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <30>; + ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ + <0x24>, /* CPSW_TX_CHAN */ + <0x25>, /* SAUL_TX_0_CHAN */ + <0x26>; /* SAUL_TX_1_CHAN */ + ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ + <0x11>, /* RING_CPSW_TX_CHAN */ + <0x12>, /* RING_SAUL_TX_0_CHAN */ + <0x13>; /* RING_SAUL_TX_1_CHAN */ + ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ + <0x2b>, /* CPSW_RX_CHAN */ + <0x2d>, /* SAUL_RX_0_CHAN */ + <0x2f>, /* SAUL_RX_1_CHAN */ + <0x31>, /* SAUL_RX_2_CHAN */ + <0x33>; /* SAUL_RX_3_CHAN */ + ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ + <0x2c>, /* FLOW_CPSW_RX_CHAN */ + <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ + <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ + }; + }; + + dmss_csi: bus@4e000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>; + + ti,sci-dev-id = <198>; + + inta_main_dmss_csi: interrupt-controller@4e400000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x4e400000 0x00 0x8000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <200>; + ti,interrupt-ranges = <0 237 8>; + ti,unmapped-event-sources = <&main_bcdma_csi>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + }; + + main_bcdma_csi: dma-controller@4e230000 { + compatible = "ti,am62a-dmss-bcdma-csirx"; + reg = <0x00 0x4e230000 0x00 0x100>, + <0x00 0x4e180000 0x00 0x8000>, + <0x00 0x4e100000 0x00 0x10000>; + reg-names = "gcfg", "rchanrt", "ringrt"; + msi-parent = <&inta_main_dmss_csi>; + #dma-cells = <3>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <199>; + ti,sci-rm-range-rchan = <0x21>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + }; + }; + + dmsc: system-controller@44043000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + mbox-names = "rx", "tx"; + mboxes = <&secure_proxy_main 12>, + <&secure_proxy_main 13>; + reg-names = "debug_messages"; + reg = <0x00 0x44043000 0x00 0xfe0>; + bootph-all; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + bootph-all; + }; + + k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + bootph-all; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + bootph-all; + }; + }; + + crypto: crypto@40900000 { + compatible = "ti,am62-sa3ul"; + reg = <0x00 0x40900000 0x00 0x1200>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; + + dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, + <&main_pktdma 0x7507 0>; + dma-names = "tx", "rx1", "rx2"; + }; + + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + bootph-all; + }; + + main_pmx0: pinctrl@f4000 { + compatible = "ti,am6-padconf"; + reg = <0x00 0xf4000 0x00 0x2ac>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + bootph-all; + }; + + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x420000 0x00 0x1000>; + ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; + bootph-pre-ram; + }; + + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 36 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 2>; + assigned-clock-parents = <&k3_clks 36 3>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + bootph-all; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 37 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 37 2>; + assigned-clock-parents = <&k3_clks 37 3>; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 38 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 38 2>; + assigned-clock-parents = <&k3_clks 38 3>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 39 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 39 2>; + assigned-clock-parents = <&k3_clks 39 3>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 40 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 40 2>; + assigned-clock-parents = <&k3_clks 40 3>; + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 41 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 41 2>; + assigned-clock-parents = <&k3_clks 41 3>; + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 42 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 42 2>; + assigned-clock-parents = <&k3_clks 42 3>; + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 43 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 43 2>; + assigned-clock-parents = <&k3_clks 43 3>; + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 146 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart2: serial@2820000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 153 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart3: serial@2830000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 154 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart4: serial@2840000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 155 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart5: serial@2850000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart6: serial@2860000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_i2c0: i2c@20000000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20000000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c1: i2c@20010000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20010000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 103 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c2: i2c@20020000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20020000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 104 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c3: i2c@20030000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20030000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 105 2>; + clock-names = "fck"; + status = "disabled"; + }; + + vpu: video-codec@30210000 { + compatible = "cnm,cm521c-vpu"; + reg = <0x00 0x30210000 0x00 0x10000>; + interrupts = ; + clocks = <&k3_clks 204 2>; + clock-names = "vcodec"; + power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; + sram = <&oc_sram>; + sram-size = <0xf800>; + operating-points-v2 = <&vpu_opp_table>; + vpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-20000000 { + opp-hz = /bits/ 64 <20000000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + }; + }; + }; + + main_spi0: spi@20100000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x20100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 141 0>; + status = "disabled"; + }; + + main_spi1: spi@20110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 142 0>; + status = "disabled"; + }; + + main_spi2: spi@20120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 143 0>; + status = "disabled"; + }; + + main_gpio_intr: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <3>; + ti,interrupt-ranges = <0 32 16>; + }; + + main_gpio0: gpio@600000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00600000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <190>, <191>, <192>, + <193>, <194>, <195>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <92>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 77 0>; + clock-names = "gpio"; + }; + + main_gpio1: gpio@601000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00601000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <180>, <181>, <182>, + <183>, <184>, <185>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <52>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 78 0>; + clock-names = "gpio"; + }; + + sdhci0: mmc@fa10000 { + compatible = "ti,am64-sdhci-8bit"; + reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 57 1>, <&k3_clks 57 2>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 57 2>; + assigned-clock-parents = <&k3_clks 57 4>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + ti,clkbuf-sel = <0x7>; + ti,strobe-sel = <0x55>; + ti,trm-icp = <0x8>; + ti,otap-del-sel-legacy = <0x1>; + ti,otap-del-sel-mmc-hs = <0x1>; + ti,otap-del-sel-ddr52 = <0x6>; + ti,otap-del-sel-hs200 = <0x8>; + ti,otap-del-sel-hs400 = <0x5>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; + status = "disabled"; + }; + + sdhci1: mmc@fa00000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; + clock-names = "clk_ahb", "clk_xin"; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + status = "disabled"; + }; + + sdhci2: mmc@fa20000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; + clock-names = "clk_ahb", "clk_xin"; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + status = "disabled"; + }; + + usbss0: dwc3-usb@f900000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f900000 0x00 0x800>, + <0x00 0x0f908000 0x00 0x400>; + clocks = <&k3_clks 161 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb0: usb@31000000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31000000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + usbss1: dwc3-usb@f910000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; + clocks = <&k3_clks 162 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb1: usb@31100000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31100000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + fss: bus@fc00000 { + compatible = "simple-bus"; + reg = <0x00 0x0fc00000 0x00 0x70000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ospi0: spi@fc40000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 75 7>; + assigned-clocks = <&k3_clks 75 7>; + assigned-clock-parents = <&k3_clks 75 8>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + cpsw3g: ethernet@8000000 { + compatible = "ti,am642-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0x08000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; + clocks = <&k3_clks 13 0>; + assigned-clocks = <&k3_clks 13 3>; + assigned-clock-parents = <&k3_clks 13 11>; + clock-names = "fck"; + power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_pktdma 0xc600 15>, + <&main_pktdma 0xc601 15>, + <&main_pktdma 0xc602 15>, + <&main_pktdma 0xc603 15>, + <&main_pktdma 0xc604 15>, + <&main_pktdma 0xc605 15>, + <&main_pktdma 0xc606 15>, + <&main_pktdma 0xc607 15>, + <&main_pktdma 0x4600 15>; + dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", + "tx7", "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + phys = <&phy_gmii_sel 1>; + mac-address = [00 00 00 00 00 00]; + }; + + cpsw_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + phys = <&phy_gmii_sel 2>; + mac-address = [00 00 00 00 00 00]; + }; + }; + + cpsw3g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 13 0>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 13 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + + hwspinlock: spinlock@2a000000 { + compatible = "ti,am64-hwspinlock"; + reg = <0x00 0x2a000000 0x00 0x1000>; + #hwlock-cells = <1>; + }; + + mailbox0_cluster0: mailbox@29000000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29000000 0x00 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster1: mailbox@29010000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29010000 0x00 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster2: mailbox@29020000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29020000 0x00 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster3: mailbox@29030000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29030000 0x00 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + ecap0: pwm@23100000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23100000 0x00 0x100>; + power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 51 0>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap1: pwm@23110000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23110000 0x00 0x100>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 52 0>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap2: pwm@23120000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23120000 0x00 0x100>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 53 0>; + clock-names = "fck"; + status = "disabled"; + }; + + eqep0: counter@23200000 { + compatible = "ti,am3352-eqep"; + reg = <0x00 0x23200000 0x00 0x100>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 59 0>; + clock-names = "fck"; + interrupts = ; + status = "disabled"; + }; + + eqep1: counter@23210000 { + compatible = "ti,am3352-eqep"; + reg = <0x00 0x23210000 0x00 0x100>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 60 0>; + clock-names = "fck"; + interrupts = ; + status = "disabled"; + }; + + eqep2: counter@23220000 { + compatible = "ti,am3352-eqep"; + reg = <0x00 0x23220000 0x00 0x100>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 62 0>; + clock-names = "fck"; + interrupts = ; + status = "disabled"; + }; + + main_mcan0: can@20701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan1: can@20711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20711000 0x00 0x200>, + <0x00 0x20718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 99 6>, <&k3_clks 99 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_rti0: watchdog@e000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e000000 0x00 0x100>; + clocks = <&k3_clks 125 0>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-parents = <&k3_clks 125 2>; + }; + + main_rti1: watchdog@e010000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e010000 0x00 0x100>; + clocks = <&k3_clks 126 0>; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 126 0>; + assigned-clock-parents = <&k3_clks 126 2>; + }; + + main_rti2: watchdog@e020000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e020000 0x00 0x100>; + clocks = <&k3_clks 127 0>; + power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 127 0>; + assigned-clock-parents = <&k3_clks 127 2>; + }; + + main_rti3: watchdog@e030000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e030000 0x00 0x100>; + clocks = <&k3_clks 128 0>; + power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 128 0>; + assigned-clock-parents = <&k3_clks 128 2>; + }; + + main_rti15: watchdog@e0f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e0f0000 0x00 0x100>; + clocks = <&k3_clks 130 0>; + power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 130 0>; + assigned-clock-parents = <&k3_clks 130 2>; + }; + + epwm0: pwm@23000000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23000000 0x00 0x100>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm1: pwm@23010000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23010000 0x00 0x100>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm2: pwm@23020000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23020000 0x00 0x100>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + mcasp0: audio-controller@2b00000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b00000 0x00 0x2000>, + <0x00 0x02b08000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 190 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 190 0>; + assigned-clock-parents = <&k3_clks 190 2>; + power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp1: audio-controller@2b10000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b10000 0x00 0x2000>, + <0x00 0x02b18000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 191 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 191 0>; + assigned-clock-parents = <&k3_clks 191 2>; + power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp2: audio-controller@2b20000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b20000 0x00 0x2000>, + <0x00 0x02b28000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 192 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 192 0>; + assigned-clock-parents = <&k3_clks 192 2>; + power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dss0: dss@30200000 { + compatible = "ti,am62p51-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2", "common1"; + ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>, /* DSS0 */ + <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>, /* OLDI0 */ + <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; /* OLDI1 */ + clocks = <&k3_clks 186 6>, + <&k3_clks 186 0>, + <&k3_clks 186 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = ; + status = "disabled"; + + dss0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gpu: gpu@fd80000 { + compatible = "ti,am62p-pvr", "img,pvr-bxs64"; + reg = <0x00 0x0fd80000 0x00 0x80000>; + interrupts = ; + power-domains = <&k3_pds 237 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 237 3>; + assigned-clock-rates = <800000000>; + power-domain-names = "firmware", "dust"; + clocks = <&k3_clks 237 3>; + clock-names = "core"; + }; + + ti_csi2rx0: ticsi2rx@30102000 { + compatible = "ti,j721e-csi2rx"; + dmas = <&main_bcdma_csi 0 0x5000 0>, <&main_bcdma_csi 0 0x5001 0>, + <&main_bcdma_csi 0 0x5002 0>, <&main_bcdma_csi 0 0x5003 0>, + <&main_bcdma_csi 0 0x5004 0>, <&main_bcdma_csi 0 0x5005 0>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5"; + reg = <0x00 0x30102000 0x00 0x1000>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@30101000 { + compatible = "cdns,csi2rx"; + reg = <0x00 0x30101000 0x00 0x1000>; + clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, + <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@30110000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30110000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dss1: dss@30220000 { + compatible = "ti,am62p52-dss"; + reg = <0x00 0x30220000 0x00 0x1000>, /* common */ + <0x00 0x30222000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30226000 0x00 0x1000>, /* vid */ + <0x00 0x30227000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30228000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3022a000 0x00 0x1000>, /* vp1: Used for OLDI */ + <0x00 0x3022b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2"; + ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; + power-domains = <&k3_pds 232 TI_SCI_PD_EXCLUSIVE>, /* DSS0 */ + <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; /* OLDI1 */ + clocks = <&k3_clks 232 8>, + <&k3_clks 232 0>, + <&k3_clks 232 4>; + clock-names = "fck", "vp1", "vp2"; + interrupts = ; + status = "disabled"; + + dss1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + dphy_tx0: phy@301c0000 { + compatible = "ti,j721e-dphy"; + reg = <0x0 0x301c0000 0x0 0x1000>; + clocks = <&k3_clks 238 16>, <&k3_clks 238 1>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 238 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 238 1>; + assigned-clock-parents = <&k3_clks 238 2>; + assigned-clock-rates = <25000000>; + status = "disabled"; + }; + + dsi0: dsi@30500000 { + compatible = "ti,j721e-dsi"; + reg = <0x0 0x30500000 0x0 0x100000>, <0x0 0x30270000 0x0 0x100>; + clocks = <&k3_clks 231 2>, <&k3_clks 231 5>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 231 TI_SCI_PD_EXCLUSIVE>; + interrupt-parent = <&gic500>; + interrupts = ; + phys = <&dphy_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P MCU domain peripherals + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu { + mcu_ram: sram@79100000 { + compatible = "mmio-sram"; + reg = <0x00 0x79100000 0x00 0x80000>; + ranges = <0x00 0x00 0x79100000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + + mcu_sram1@0 { + reg = <0x0 0x80000>; + }; + }; + + mcu_pmx0: pinctrl@4084000 { + compatible = "pinctrl-single"; + reg = <0x00 0x04084000 0x00 0x88>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + bootph-all; + }; + + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x4100000 0x00 0x1000>; + ti,esm-pins = <0>, <1>, <2>, <85>; + status = "reserved"; + bootph-pre-ram; + }; + + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@4800000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4800000 0x00 0x400>; + clocks = <&k3_clks 35 2>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@4810000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4810000 0x00 0x400>; + clocks = <&k3_clks 48 2>; + clock-names = "fck"; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@4820000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4820000 0x00 0x400>; + clocks = <&k3_clks 49 2>; + clock-names = "fck"; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@4830000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4830000 0x00 0x400>; + clocks = <&k3_clks 50 2>; + clock-names = "fck"; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_uart0: serial@4a00000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x04a00000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 149 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + mcu_i2c0: i2c@4900000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x04900000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 106 2>; + clock-names = "fck"; + status = "disabled"; + }; + + mcu_spi0: spi@4b00000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x04b00000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 147 0>; + status = "disabled"; + }; + + mcu_spi1: spi@4b10000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x04b10000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 148 0>; + status = "disabled"; + }; + + mcu_gpio_intr: interrupt-controller@4210000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x04210000 0x00 0x200>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <5>; + ti,interrupt-ranges = <0 104 4>; + }; + + mcu_gpio0: gpio@4201000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x4201000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&mcu_gpio_intr>; + interrupts = <30>, <31>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <24>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 79 0>; + clock-names = "gpio"; + }; + + mcu_rti0: watchdog@4880000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x04880000 0x00 0x100>; + clocks = <&k3_clks 131 0>; + power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 131 0>; + assigned-clock-parents = <&k3_clks 131 2>; + /* Tightly coupled to M4F */ + status = "reserved"; + }; + + mcu_mcan0: can@4e08000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e08000 0x00 0x200>, + <0x00 0x4e00000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + interrupts = , + ; + interrupt-names = "int0", "int1"; + wakeup-source; + status = "disabled"; + }; + + mcu_mcan1: can@4e18000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e18000 0x00 0x200>, + <0x00 0x4e10000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + interrupts = , + ; + interrupt-names = "int0", "int1"; + wakeup-source; + status = "disabled"; + }; + + mcu_r5fss0: r5fss@79000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x79000000 0x00 0x79000000 0x8000>, + <0x79020000 0x00 0x79020000 0x8000>; + power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + mcu_r5fss0_core0: r5f@79000000 { + compatible = "ti,am62-r5f"; + reg = <0x79000000 0x00008000>, + <0x79020000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <9>; + ti,sci-proc-ids = <0x03 0xff>; + resets = <&k3_reset 9 1>; + firmware-name = "am62p-mcu-r5f0_0-fw"; + ti,atcm-enable = <0>; + ti,btcm-enable = <1>; + ti,loczrama = <0>; + sram = <&mcu_ram>; + wakeup-source; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p-thermal.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p-thermal.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P wakeup domain peripherals + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include + +&cbass_wakeup { + wkup_conf: syscon@43000000 { + compatible = "syscon", "simple-mfd"; + reg = <0x00 0x43000000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x43000000 0x20000>; + bootph-all; + + chipid: chipid@14 { + compatible = "ti,am654-chipid"; + reg = <0x14 0x4>; + bootph-all; + }; + }; + + target-module@2b300050 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0 0x2b300050 0 0x4>, + <0 0x2b300054 0 0x4>, + <0 0x2b300058 0 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + ti,no-reset-on-init; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2b300000 0x100000>; + + wkup_uart0: serial@0 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0 0x100>; + interrupts = ; + status = "disabled"; + }; + }; + + wkup_i2c0: i2c@2b200000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x2b200000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 107 4>; + clock-names = "fck"; + status = "disabled"; + }; + + wkup_rtc0: rtc@2b1f0000 { + compatible = "ti,am62-rtc"; + reg = <0x00 0x2b1f0000 0x00 0x100>; + interrupts = ; + clocks = <&k3_clks 117 6> , <&k3_clks 117 0>; + clock-names = "vbus", "osc32k"; + power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; + wakeup-source; + }; + + wkup_rti0: watchdog@2b000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2b000000 0x00 0x100>; + clocks = <&k3_clks 132 0>; + power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 132 0>; + assigned-clock-parents = <&k3_clks 132 2>; + /* Used by DM firmware */ + status = "reserved"; + }; + + wkup_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; + + wkup_r5fss0: r5fss@78000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + wkup_r5fss0_core0: r5f@78000000 { + compatible = "ti,am62-r5f"; + reg = <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <121>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 121 1>; + firmware-name = "am62-wkup-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62P SoC Family + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include + +#include "k3-pinctrl.h" + +/ { + model = "Texas Instruments K3 AM62P5 SoC"; + compatible = "ti,am62p5"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + cbass_main: bus@f0000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + bootph-all; + + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ + <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ + <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */ + <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI Wrapper */ + <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI Config */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, + + /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; + + cbass_mcu: bus@4000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */ + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ + bootph-all; + }; + + cbass_wakeup: bus@b00000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ + bootph-all; + }; + }; + + #include "k3-am62p-thermal.dtsi" +}; + +/* Now include peripherals for each bus segment */ +#include "k3-am62p-main.dtsi" +#include "k3-am62p-mcu.dtsi" +#include "k3-am62p-wakeup.dtsi" + +&dmsc { + ti,partial-io-wakeup-sources = <&mcu_mcan0>, <&mcu_mcan1>, <&mcu_uart0>, <&wkup_uart0>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk-dsi-rpi-7inch-panel.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk-dsi-rpi-7inch-panel.dtso @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for RPi 7inch touchscreen panel interfaced with DSI on + * AM62P5-SK EVM. + * + * RPi DSI Panel: https://www.raspberrypi.com/products/raspberry-pi-touch-display/ + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + panel0 { + compatible = "raspberrypi,7inch-dsi", "simple-panel"; + backlight = <&display_reg>; + power-supply = <&display_reg>; + port { + panel_in: endpoint { + remote-endpoint = <&panel_bridge_out>; + }; + }; + }; + + bridge_reg: bridge-regulator { + compatible = "regulator-fixed"; + regulator-name = "bridge-reg"; + gpio = <&display_reg 0 0>; + vin-supply = <&display_reg>; + enable-active-high; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + display_reg: regulator@45 { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&dss1 { + status = "okay"; +}; + +&dss1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* DSS1-VP1: DSI Output */ + port@1 { + reg = <1>; + + dss1_dpi1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&dsi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_out: endpoint { + remote-endpoint = <&panel_bridge_in>; + }; + }; + + port@1 { + reg = <1>; + dsi0_in: endpoint { + remote-endpoint = <&dss1_dpi1_out>; + }; + }; + }; + + bridge@0 { + status = "okay"; + compatible = "toshiba,tc358762"; + reg = <0>; + vddc-supply = <&bridge_reg>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + panel_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk-dss-shared-mode.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk-dss-shared-mode.dtso @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay to enable display sharing mode for AM62P DSS0 + * This is compatible with AM62P Device Manager firmware labelled as + * "dss_display_share.wkup-r5f0_0.release.strip.out" + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&dss0 { + ti,dss-shared-mode; + ti,dss-shared-mode-vp = "vp1"; + ti,dss-shared-mode-vp-owned = <0>; + ti,dss-shared-mode-common = "common1"; + ti,dss-shared-mode-planes = "vid"; + ti,dss-shared-mode-plane-zorder = <0>; + interrupts = ; +}; + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + rtos_framebuffer_memory_region: rtos-framebuffer-memory@93500000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x93500000 0x00 0x08000000>; + no-map; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk-eqep.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk-eqep.dtso @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for enabling EQEP on AM62P-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + main_eqep0_pins_default: main-eqep0-pins-default { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0194, PIN_INPUT, 8) /* (D25) MCASP0_AXR3.EQEP0_A */ + AM62PX_IOPAD(0x0198, PIN_INPUT, 8) /* (E25) MCASP0_AXR2.EQEP0_B */ + AM62PX_IOPAD(0x01a0, PIN_INPUT, 8) /* (F23) MCASP0_AXR0.EQEP0_I */ + AM62PX_IOPAD(0x019c, PIN_INPUT, 8) /* (E24) MCASP0_AXR1.EQEP0_S */ + >; + }; +}; + +&main_i2c1 { + gpio@22 { + p02-hog { + /* P02 - UART1_FET_SEL */ + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "UART1_FET_SEL"; + }; + }; +}; + +&eqep0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_eqep0_pins_default>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk-mcan.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk-mcan.dtso @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for enabling MCAN for AM62P-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver4: can-phy3 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&main_pmx0 { + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01dc, PIN_INPUT, 0) /* (F20) MCAN0_RX */ + AM62PX_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (B23) MCAN0_TX */ + >; + }; + + main_mcan1_pins_default: main-mcan1-pins-default { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00b4, PIN_INPUT, 5) /* (U25) GPMC0_CSn3.MCAN1_RX */ + AM62PX_IOPAD(0x00b0, PIN_OUTPUT, 5) /* (T22) GPMC0_CSn2.MCAN1_TX */ + >; + }; +}; + +&mcu_pmx0 { + mcu_mcan0_pins_default: mcu-mcan0-pins-default { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (D6) MCU_MCAN0_RX */ + AM62PX_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (E8) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0040, PIN_INPUT, 0) /* (E7) MCU_MCAN1_RX */ + AM62PX_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) /* (F8) MCU_MCAN1_TX */ + >; + }; +}; + +&main_i2c2{ + /* + * main_i2c2 is using (U25) and (T22) + * so disable to use main_mcan1 + */ + status = "disabled"; +}; + +&main_i2c1 { + /* + * Unset GPIO SoC_I2C2_MCAN_SEL to + * route MCAN1 signals to MCAN1 HDR + */ + gpio@23 { + p20-hog { + /* P20 - SoC_I2C2_MCAN_SEL */ + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "SoC_I2C2_MCAN_SEL"; + }; + }; +}; + +&main_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&main_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver3>; +}; + +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver4>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf101hie-panel.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf101hie-panel.dtso @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Microtips integrated OLDI panel (MF-101HIEBCAF0) and touch DT overlay for AM62P5-SK + * + * Panel datasheet: https://simplespec.microtipsusa.com/uploads/spec/datasheetFile/2588/13-101HIEBCAF0-S_V1.1_20221104.pdf + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + display { + compatible = "microtips,mf-101hiebcaf0"; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * Swapping them will not make any difference. + */ + port@0 { + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + port@1 { + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_out1>; + }; + }; + }; +}; + +&dss0 { + status = "okay"; +}; + +&dss0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: LVDS Output (OLDI TX 0) */ + port@0 { + reg = <0>; + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; + + /* VP1: LVDS Output (OLDI TX 1) */ + port@2 { + reg = <2>; + oldi_out1: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&exp1>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&exp2 20 GPIO_ACTIVE_LOW>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf103hie-lcd2.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk-microtips-mf103hie-lcd2.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Microtips integrated OLDI panel (MF-103HIEB0GA0) (SK-LCD2) DT overlay for AM62PS5-SK + * + * Panel datasheet: https://simplespec.microtipsusa.com/uploads/spec/datasheetFile/2660/13-103HIEB0GA0-S_V1.0_20211206.pdf + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + display { + compatible = "microtips,mf-103hieb0ga0"; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * But swapping them will cause an error in the dss driver. + */ + port@0 { + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + port@1 { + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_out1>; + }; + }; + }; +}; + +&dss0 { + status = "okay"; +}; + +&dss0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: LVDS Output (OLDI TX 0) */ + port@0 { + reg = <0>; + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; + + /* VP1: LVDS Output (OLDI TX 1) */ + port@2 { + reg = <2>; + oldi_out1: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk-rpi-hdr-ehrpwm.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk-rpi-hdr-ehrpwm.dtso @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling RPi header with GPIOs and eHRPWMs on AM62P-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0038, PIN_INPUT, 7) /* (L23) OSPI0_CSn3.GPIO0_14 */ + AM62PX_IOPAD(0x0088, PIN_INPUT, 7) /* (R24) GPMC0_OEn_REn.GPIO0_33 */ + AM62PX_IOPAD(0x0094, PIN_INPUT, 7) /* (T24) GPMC0_BE1n.GPIO0_36 */ + AM62PX_IOPAD(0x009c, PIN_INPUT, 7) /* (AD24) GPMC0_WAIT1.GPIO0_38 */ + AM62PX_IOPAD(0x00a0, PIN_INPUT, 7) /* (P24) GPMC0_WPn.GPIO0_39 */ + AM62PX_IOPAD(0x00a4, PIN_INPUT, 7) /* (P25) GPMC0_DIR.GPIO0_40 */ + AM62PX_IOPAD(0x00a8, PIN_INPUT, 7) /* (T23) GPMC0_CSn0.GPIO0_41 */ + AM62PX_IOPAD(0x00ac, PIN_INPUT, 7) /* (U23) GPMC0_CSn1.GPIO0_42 */ + >; + }; + + rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01a4, PIN_INPUT, 7) /* (F24) MCASP0_ACLKX.GPIO1_11 */ + AM62PX_IOPAD(0x01bc, PIN_INPUT, 7) /* (B21) SPI0_CLK.GPIO1_17 */ + AM62PX_IOPAD(0x01c0, PIN_INPUT, 7) /* (B20) SPI0_D0.GPIO1_18 */ + AM62PX_IOPAD(0x01c4, PIN_INPUT, 7) /* (C21) SPI0_D1.GPIO1_19 */ + AM62PX_IOPAD(0x01d0, PIN_INPUT, 7) /* (A23) UART0_CTSn.GPIO1_22 */ + AM62PX_IOPAD(0x01d8, PIN_INPUT, 7) /* (B23) MCAN0_TX.GPIO1_24 */ + AM62PX_IOPAD(0x01dc, PIN_INPUT, 7) /* (F20) MCAN0_RX.GPIO1_25 */ + >; + }; + + rpi_header_ehrpwm0_pins_default: rpi-header-ehrpwm0-pins-default { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (D20) SPI0_CS0.EHRPWM0_A */ + AM62PX_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (E20) SPI0_CS1.EHRPWM0_B */ + >; + }; + + rpi_header_ehrpwm1_pins_default: rpi-header-ehrpwm1-pins-default { + pinctrl-single,pins = < + AM62PX_IOPAD(0x019c, PIN_OUTPUT, 6) /* (E24) MCASP0_AXR1.EHRPWM1_A */ + AM62PX_IOPAD(0x01a0, PIN_OUTPUT, 6) /* (F23) MCASP0_AXR0.EHRPWM1_B */ + >; + }; +}; + +&main_i2c1 { + gpio@22 { + p02-hog { + /* P02 - UART1_FET_SEL */ + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "UART1_FET_SEL"; + }; + + p05-hog { + /* P05 - EXP_PS_3V3_EN */ + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_3V3_EN"; + }; + }; + + gpio@23 { + p01-hog { + /* P01 - EXP_PS_5V0_EN */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_PS_5V0_EN"; + }; + }; +}; + +&dss0 { + /* Conflict with GPIO0_38 */ + status = "disabled"; +}; + +&epwm0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm0_pins_default>; +}; + +&epwm1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm1_pins_default>; +}; + +&main_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; + +&main_gpio1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio1_pins_default>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -0,0 +1,858 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P5-SK + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://www.ti.com/lit/zip/sprr487 + */ + +/dts-v1/; + +#include +#include +#include +#include "k3-am62p5.dtsi" + +/ { + compatible = "ti,am62p5-sk", "ti,am62p5"; + model = "Texas Instruments AM62P5 SK"; + + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + spi0 = &ospi0; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = &main_uart0; + + framebuffer0: framebuffer@0 { + compatible = "simple-framebuffer"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&k3_clks 186 0>, + <&k3_clks 186 2>; + display = <&dss0>; + status = "disabled"; + }; + }; + + memory@80000000 { + /* 8G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type = "memory"; + bootph-pre-ram; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x24000000>; + linux,cma-default; + }; + + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b500000 0x00 0x00300000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x00100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0x00f00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x00100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + no-map; + }; + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_5v0: regulator-1 { + /* Output of TPS630702RNMR */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vdd_mmc1: regulator-2 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vddshv_sdio: regulator-3 { + compatible = "regulator-gpio"; + regulator-name = "vddshv_sdio"; + pinctrl-names = "default"; + pinctrl-0 = <&vddshv_sdio_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + bootph-all; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pins_default>; + + led-0 { + label = "am62-sk:green:heartbeat"; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + }; + + opp-table { + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + + tlv320_mclk: clk-0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12288000>; + }; + + codec_audio: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM62x-SKEVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&tlv320_mclk>; + }; + }; + + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; +}; + +&main_gpio0 { + bootph-all; +}; + +&main_gpio1 { + bootph-all; +}; + +&main_pmx0 { + bootph-all; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */ + AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */ + AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */ + >; + bootph-all; + }; + + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */ + AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C22) UART0_RTSn.GPIO1_23 */ + >; + }; + + main_mcasp1_pins_default: main-mcasp1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ + AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */ + AM62PX_IOPAD(0x008c, PIN_OUTPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */ + AM62PX_IOPAD(0x0084, PIN_INPUT, 2) /* (R25) GPMC0_ADVn_ALE.MCASP1_AXR2 */ + >; + }; + + main_mdio1_pins_default: main-mdio1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */ + AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */ + >; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */ + AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */ + AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */ + AM62PX_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H23) MMC1_DAT1 */ + AM62PX_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (H22) MMC1_DAT2 */ + AM62PX_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ + AM62PX_IOPAD(0x0240, PIN_INPUT, 0) /* (D23) MMC1_SDCD */ + >; + bootph-all; + }; + + main_mmc2_pins_default: main-mmc2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */ + AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */ + AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */ + AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */ + AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */ + AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */ + AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */ + >; + bootph-all; + }; + + main_rgmii1_pins_default: main-rgmii1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */ + AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */ + AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */ + AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */ + AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */ + AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */ + AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */ + AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */ + AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */ + AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */ + AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */ + AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */ + >; + bootph-all; + }; + + main_rgmii2_pins_default: main-rgmii2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */ + AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */ + AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */ + AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */ + AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */ + AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */ + AM62PX_IOPAD(0x016c, PIN_INPUT, 0) /* (B19) RGMII2_TD0 */ + AM62PX_IOPAD(0x0170, PIN_INPUT, 0) /* (A21) RGMII2_TD1 */ + AM62PX_IOPAD(0x0174, PIN_INPUT, 0) /* (D17) RGMII2_TD2 */ + AM62PX_IOPAD(0x0178, PIN_INPUT, 0) /* (A19) RGMII2_TD3 */ + AM62PX_IOPAD(0x0168, PIN_INPUT, 0) /* (D16) RGMII2_TXC */ + AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX_CTL */ + >; + bootph-all; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ + >; + bootph-all; + }; + + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3.UART1_CTSn */ + AM62PX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2.UART1_RTSn */ + AM62PX_IOPAD(0x01ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR.UART1_RXD */ + AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR.UART1_TXD */ + >; + bootph-all; + }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ + >; + }; + + main_wlirq_pins_default: main-wlirq-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0128, PIN_INPUT, 7) /* (K25) MMC2_SDWP.GPIO0_72 */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (P23) OSPI0_CLK */ + AM62PX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (M25) OSPI0_CSn0 */ + AM62PX_IOPAD(0x000c, PIN_INPUT, 0) /* (L25) OSPI0_D0 */ + AM62PX_IOPAD(0x0010, PIN_INPUT, 0) /* (N24) OSPI0_D1 */ + AM62PX_IOPAD(0x0014, PIN_INPUT, 0) /* (N25) OSPI0_D2 */ + AM62PX_IOPAD(0x0018, PIN_INPUT, 0) /* (M24) OSPI0_D3 */ + AM62PX_IOPAD(0x001c, PIN_INPUT, 0) /* (N21) OSPI0_D4 */ + AM62PX_IOPAD(0x0020, PIN_INPUT, 0) /* (N22) OSPI0_D5 */ + AM62PX_IOPAD(0x0024, PIN_INPUT, 0) /* (P21) OSPI0_D6 */ + AM62PX_IOPAD(0x0028, PIN_INPUT, 0) /* (N20) OSPI0_D7 */ + AM62PX_IOPAD(0x0008, PIN_INPUT, 0) /* (P22) OSPI0_DQS */ + >; + bootph-all; + }; + + usr_led_pins_default: usr-led-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0244, PIN_INPUT, 7) /* (D24) MMC1_SDWP.GPIO1_49 */ + >; + }; + + vddshv_sdio_pins_default: vddshvr-sdio-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x007c, PIN_INPUT, 7) /* (Y25) GPMC0_CLK.GPIO0_31 */ + >; + bootph-all; + }; + + wlan_en_pins_default: wlan-en-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0124, PIN_INPUT, 7) /* (J25) MMC2_SDCD.GPIO0_71 */ + >; + }; + + main_dpi_pins_default: main-dpi-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0100, PIN_OUTPUT, 0) /* (W20) VOUT0_VSYNC */ + AM62PX_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AC20) VOUT0_HSYNC */ + AM62PX_IOPAD(0x0104, PIN_OUTPUT, 0) /* (Y21) VOUT0_PCLK */ + AM62PX_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (W21) VOUT0_DE */ + AM62PX_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (AE24) VOUT0_DATA0 */ + AM62PX_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (W23) VOUT0_DATA1 */ + AM62PX_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA2 */ + AM62PX_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA3 */ + AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (AB23) VOUT0_DATA4 */ + AM62PX_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (AD23) VOUT0_DATA5 */ + AM62PX_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (AC23) VOUT0_DATA6 */ + AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AE23) VOUT0_DATA7 */ + AM62PX_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (AE22) VOUT0_DATA8 */ + AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (AC22) VOUT0_DATA9 */ + AM62PX_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA10 */ + AM62PX_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AE21) VOUT0_DATA11 */ + AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AD21) VOUT0_DATA12 */ + AM62PX_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AC21) VOUT0_DATA13 */ + AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AA20) VOUT0_DATA14 */ + AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (Y20) VOUT0_DATA15 */ + AM62PX_IOPAD(0x005c, PIN_OUTPUT, 1) /* (AC25) GPMC0_AD8.VOUT0_DATA16 */ + AM62PX_IOPAD(0x0060, PIN_OUTPUT, 1) /* (AB25) GPMC0_AD9.VOUT0_DATA17 */ + AM62PX_IOPAD(0x0064, PIN_OUTPUT, 1) /* (AA25) GPMC0_AD10.VOUT0_DATA18 */ + AM62PX_IOPAD(0x0068, PIN_OUTPUT, 1) /* (W24) GPMC0_AD11.VOUT0_DATA19 */ + AM62PX_IOPAD(0x006c, PIN_OUTPUT, 1) /* (Y24) GPMC0_AD12.VOUT0_DATA20 */ + AM62PX_IOPAD(0x0070, PIN_OUTPUT, 1) /* (AD25) GPMC0_AD13.VOUT0_DATA21 */ + AM62PX_IOPAD(0x0074, PIN_OUTPUT, 1) /* (AB24) GPMC0_AD14.VOUT0_DATA22 */ + AM62PX_IOPAD(0x0078, PIN_OUTPUT, 1) /* (AC24) GPMC0_AD15.VOUT0_DATA23 */ + AM62PX_IOPAD(0x009c, PIN_OUTPUT, 1) /* (AD24) GPMC0_WAIT1.VOUT0_EXTPCLKIN */ + >; + }; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + typec_pd0: tps6598x@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; + }; +}; + +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <100000>; + bootph-all; + + tlv320aic3106: audio-codec@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + ai3x-micbias-vg = <1>; /* 2.0V */ + }; + + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "OLDI_INT#", "x8_NAND_DETECT", + "UART1_FET_SEL", "MMC1_SD_EN", + "VPP_EN", "EXP_PS_3V3_EN", + "UART1_FET_BUF_EN", "EXP_HAT_DETECT", + "DSI_GPIO0", "DSI_GPIO1", + "OLDI_EDID", "BT_UART_WAKE_SOC_3V3", + "USB_TYPEA_OC_INDICATION", "CSI_GPIO0", + "CSI_GPIO1", "WLAN_ALERTn", + "HDMI_INTn", "TEST_GPIO2", + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", + "MCASP1_FET_SEL", "DSI_EDID", + "PD_I2C_IRQ", "IO_EXP_TEST_LED"; + + interrupt-parent = <&main_gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + bootph-all; + }; + + exp2: gpio@23 { + compatible = "ti,tca6424"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "BT_EN_SOC", "EXP_PS_5V0_EN", + "", "", + "", "", + "", "", + "WL_LT_EN", "", + "TP3", "TP6", + "TP4", "TP7", + "TP5", "TP8", + "SoC_I2C2_MCAN_SEL", "GPIO_HDMI_RSTn", + "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "GPIO_OLDI_RSTn", "GPIO_AUD_RSTn", + "GPIO_eMMC_RSTn", "SoC_WLAN_SDIO_RST"; + }; + + sii9022: bridge-hdmi@3b { + compatible = "sil,sii9022"; + reg = <0x3b>; + interrupt-parent = <&exp1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = < 0 >; + + hdmi_tx_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * HDMI can be serviced with 3 potential VPs - + * (DSS0 VP1 / DSS1 VP0 / DSS1 VP1). + * For now, we will service it with DSS0 VP1. + */ + port@0 { + reg = <0>; + sii9022_in: endpoint { + remote-endpoint = <&dss0_dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&main_i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; +}; + +&sdhci0 { + status = "okay"; + ti,driver-strength-ohm = <50>; + disable-wp; + bootph-all; +}; + +&sdhci1 { + /* SD/MMC */ + status = "okay"; + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vddshv_sdio>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + disable-wp; + bootph-all; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>, + <&main_rgmii2_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usbss1 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + usb-role-switch; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; + +&mcasp1 { + status = "okay"; + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp1_pins_default>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <0>; + rx-num-evt = <0>; +}; + +&fss { + bootph-all; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + bootph-all; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x00 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + bootph-all; + }; + }; + }; +}; + +&mailbox0_cluster0 { + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + interrupts-extended = <&gic500 GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <&main_pmx0 0x1c8>; /* (D14) UART0_RXD PADCONFIG114 */ + interrupt-names = "irq", "wakeup"; + status = "okay"; + bootph-all; +}; + +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; + bootph-all; +}; + +&mcu_pmx0 { + bootph-all; + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ + AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ + >; + bootph-all; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "reserved"; + bootph-all; +}; + +&dss0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_dpi_pins_default>; +}; + +&dss0_ports { + /* DSS0-VP2: DPI/HDMI Output */ + hdmi0_dss: port@1 { + reg = <1>; + dss0_dpi1_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ +&mcu_gpio0 { + status = "reserved"; +}; + +&mcu_gpio_intr { + status = "reserved"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62p5.dtsi @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P5 SoC family (quad core) + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * TRM: https://www.ti.com/lit/pdf/spruj83 + */ + +/dts-v1/; + +#include "k3-am62p.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 135 0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 136 0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 137 0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 138 0>; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&wkup_conf>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common dtsi for AM62x SK and derivatives + * + * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include "k3-am625.dtsi" + +/ { + aliases { + serial0 = &mcu_uart0; + serial1 = &wkup_uart0; + serial2 = &main_uart0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + spi0 = &ospi0; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial2:115200n8"; + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + + framebuffer0: framebuffer@0 { + compatible = "simple-framebuffer"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&k3_clks 186 0>, + <&k3_clks 186 2>; + display = <&dss>; + status = "disabled"; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@9c700000 { + compatible = "ramoops"; + reg = <0x00 0x9c700000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x8000000>; + linux,cma-default; + }; + + rtos_ipc_memory_region: ipc-memories@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x00300000>; + no-map; + }; + + mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@9cc00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9da00000 0x00 0x00100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0x00c00000>; + no-map; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pins_default>; + + led-0 { + label = "am62-sk:green:heartbeat"; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + }; + + tlv320_mclk: clk-0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12288000>; + }; + + codec_audio: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM62x-SKEVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&tlv320_mclk>; + }; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; +}; + +&main_pmx0 { + /* First pad number is ALW package and second is AMC package */ + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */ + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16/D14) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */ + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */ + >; + }; + + main_i2c2_pins_default: main-i2c2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22/H18) GPMC0_CSn2.I2C2_SCL */ + AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24/H19) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_mmc0_pins_default: main-mmc0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2/V2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1/V1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3/W2) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4/W1) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2/Y2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1/W3) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2/W4) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2/V4) MMC0_DAT7 */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */ + AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */ + AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22/A19) MMC1_DAT0 */ + AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21/B19) MMC1_DAT1 */ + AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21/B20) MMC1_DAT2 */ + AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22/C19) MMC1_DAT3 */ + AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17/C15) MMC1_SDCD */ + >; + }; + + usr_led_pins_default: usr-led-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17/B15) MMC1_SDWP.GPIO1_49 */ + >; + }; + + main_mdio1_pins_default: main-mdio1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24/V17) MDIO0_MDC */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22/U16) MDIO0_MDIO */ + >; + }; + + main_rgmii1_pins_default: main-rgmii1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16/AA17) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15/Y15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17/AA16) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17/W14) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20/U14) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20/AA19) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18/Y17) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18/AA18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19/W16) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */ + >; + }; + + ospi0_pins_default: ospi0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ + AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ + AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ + AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ + AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ + AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ + AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ + AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ + AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ + AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ + >; + }; + + main_usb1_pins_default: main-usb1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ + >; + }; + + main_mcasp1_pins_default: main-mcasp1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24) GPMC0_BE0N_CLE.MCASP1_ACLKX */ + AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ + AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEN.MCASP1_AXR0 */ + AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23) GPMC0_ADVN_ALE.MCASP1_AXR2 */ + >; + }; + + main_dss0_pins_default: main-dss0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ + AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ + AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ + AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ + AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ + AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ + AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ + AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ + AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ + AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ + AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ + AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ + AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ + AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ + AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ + AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ + AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ + AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ + AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ + AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ + AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ + AM62X_IOPAD(0x0064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */ + AM62X_IOPAD(0x0068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */ + AM62X_IOPAD(0x006c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ + AM62X_IOPAD(0x0070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */ + AM62X_IOPAD(0x0074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */ + AM62X_IOPAD(0x0078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ + >; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; + +&main_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + interrupts-extended = <&gic500 GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <&main_pmx0 0x1c8>; /* (D14) UART0_RXD PADCONFIG114 */ + interrupt-names = "irq", "wakeup"; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + typec_pd0: tps6598x@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; + }; +}; + +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <100000>; + + tlv320aic3106: audio-codec@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + ai3x-micbias-vg = <1>; /* 2.0V */ + + /* Regulators */ + AVDD-supply = <&vcc_3v3_sys>; + IOVDD-supply = <&vcc_3v3_sys>; + DRVDD-supply = <&vcc_3v3_sys>; + }; + + sii9022: sii9022@3b { + #sound-dai-cells = <0>; + compatible = "sil,sii9022"; + reg = <0x3b>; + + interrupt-parent = <&exp1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + + sil,i2s-data-lanes = < 0 >; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&main_i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; +}; + +&sdhci0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + disable-wp; +}; + +&sdhci1 { + /* SD/MMC */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + disable-wp; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&mailbox0_cluster0 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mcu_m4fss { + mboxes = <&mailbox0_cluster0 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usbss1 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + usb-role-switch; + + port@0 { + reg = <0>; + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; + +&mcasp1 { + status = "okay"; + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp1_pins_default>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <0>; + rx-num-evt = <0>; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&main_dss0_pins_default>; +}; + +&dss_ports { + /* VP2: DPI Output */ + hdmi0_dss: port@1 { + reg = <1>; + + dpi1_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; + +/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ +&mcu_gpio0 { + status = "reserved"; +}; + +&mcu_gpio_intr { + status = "reserved"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX219 (RPi v2) Camera Module + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + /* CAM port */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ov5640: camera@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + reset-gpios = <&exp1 13 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ALINX AN5641 & Digilent PCam 5C - OV5640 camera module + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + /* CAM port */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + powerdown-gpios = <&exp1 13 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Technexion TEVI-OV5640-*-RPI - OV5640 camera module + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + /* CAM port */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + powerdown-gpios = <&exp1 13 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-v3link-fusion.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-v3link-fusion.dtso @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Arducam V3Link UC-A09 board + * https://www.arducam.com/fpd-link-3-cameras/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + ds90ub960_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + ds90ub960_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-eqep.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-eqep.dtso @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for enabling EQEP on AM625-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + main_eqep0_pins_default: main-eqep0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0194, PIN_INPUT, 8) /* (B19) MCASP0_AXR3.EQEP0_A */ + AM62X_IOPAD(0x0198, PIN_INPUT, 8) /* (A19) MCASP0_AXR2.EQEP0_B */ + AM62X_IOPAD(0x01a0, PIN_INPUT, 8) /* (E18) MCASP0_AXR0.EQEP0_I */ + AM62X_IOPAD(0x019c, PIN_INPUT, 8) /* (B18) MCASP0_AXR1.EQEP0_S */ + >; + }; +}; + +&main_i2c1 { + gpio@22 { + p25-hog { + /* P25 - UART1_FET_SEL */ + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "UART1_FET_SEL"; + }; + }; +}; + +&eqep0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_eqep0_pins_default>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-audio.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-audio.dtso @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Audio playback via HDMI for AM625-SK and AM62-LP SK. + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + hdmi_audio: sound-sii9022 { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM62x-Sil9022-HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&hdmi_dailink_master>; + simple-audio-card,frame-master = <&hdmi_dailink_master>; + hdmi_dailink_master: simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-direction-out; + }; + simple-audio-card,codec { + sound-dai = <&sii9022>; + }; + }; +}; + +&mcasp1 { + auxclk-fs-ratio = <2177>; +}; + +&codec_audio { + status = "disabled"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-disable-fastboot.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-disable-fastboot.dtso @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Overlay to remove HDMI support for TI K3 AM62* SK + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&hdmi0 { + status = "disabled"; +}; + +&sii9022 { + status = "disabled"; +}; + +&hdmi0_dss { + status = "disabled"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-lpm-wkup-sources.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-lpm-wkup-sources.dtso @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * AM62 family of devices can wakeup from Low Power Modes via + * multiple wakeup sources. This overlay enables MAIN GPIO, MCU GPIO, + * and MCU MCAN pins. + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + gpio_key { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_pins_default>; + switch { + label = "WKGPIO"; + linux,code = ; + interrupts-extended = <&main_gpio1 10 IRQ_TYPE_EDGE_RISING>, + <&main_pmx0 0x1a0>; + interrupt-names = "irq", "wakeup"; + }; + }; + + mcu_gpio_key { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&wake_mcugpio1_pins_default>; + interrupt-parent = <&mcu_gpio0>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + switch { + label = "MCUGPIO"; + linux,code = <143>; + gpios = <&mcu_gpio0 4 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; +}; + +&main_pmx0 { + main_gpio1_pins_default: main-gpio1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1a0, PIN_INPUT_PULLUP, 7) /* (E18) MCASP0_AXR0.EHRPWM1_B */ + >; + }; +}; + +&mcu_pmx0 { + wake_mcugpio1_pins_default: wake-mcugpio1-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0010, PIN_INPUT, 7) /* (D8) MCU_SPI0_D1.MCU_GPIO0_4 */ + >; + }; + + mcu_mcan0_tx_pins_default: mcu-mcan0-tx-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan0_rx_pins_default: mcu-mcan0-rx-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan0_rx_pins_wakeup: mcu-mcan0-rx-pins-wakeup { + pinctrl-single,pins = < + AM62X_IOPAD(0x038, PIN_INPUT | WKUP_EN, 0) /* (B3) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan1_tx_pins_default: mcu-mcan1-tx-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x03c, PIN_OUTPUT, 0) /* (E5) MCU_MCAN1_TX */ + >; + }; + + mcu_mcan1_rx_pins_default: mcu-mcan1-rx-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x040, PIN_INPUT, 0) /* (D4) MCU_MCAN1_RX */ + >; + }; + + mcu_mcan1_rx_pins_wakeup: mcu-mcan1-rx-pins-wakeup { + pinctrl-single,pins = < + AM62X_IOPAD(0x040, PIN_INPUT | WKUP_EN, 0) /* (D4) MCU_MCAN1_RX */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_UART0_CTSn */ + AM62X_MCU_IOPAD(0x0020, PIN_OUTPUT, 0) /* MCU_UART0_RTSn */ + AM62X_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_UART0_TXD */ + >; + }; + + mcu_uart0_rxd_pins_default: mcu-uart0-rxd-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_UART0_RXD */ + >; + }; + + mcu_uart0_rxd_pins_wakeup: mcu-uart0-rxd-pins-wakeup { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0014, PIN_INPUT | WKUP_EN, 0) /* MCU_UART0_RXD */ + >; + }; +}; + +&mcu_gpio0 { + status = "okay"; +}; + +&mcu_gpio_intr { + status = "okay"; +}; + +&mcu_mcan0 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_default>; + pinctrl-1 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_wakeup>; + status = "okay"; +}; + +&mcu_mcan1 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_default>; + pinctrl-1 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_wakeup>; + status = "okay"; +}; + +&mcu_uart0 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_uart0_pins_default>, <&mcu_uart0_rxd_pins_default>; + pinctrl-1 = <&mcu_uart0_pins_default>, <&mcu_uart0_rxd_pins_wakeup>; + status = "ok"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-mcan.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am62x-sk-mcan.dtso @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay to enable MCAN on AM625-SK, AM62A-SK, AM62 LP-SK + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-pinctrl.h" + +&{/} { + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&main_pmx0 { + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ + AM62X_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ + >; + }; +}; + +&mcu_pmx0 { + mcu_mcan0_pins_default: mcu-mcan0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ + AM62X_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0040, PIN_INPUT, 0) /* (D4) MCU_MCAN1_RX */ + AM62X_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) /* (E5) MCU_MCAN1_TX */ + >; + }; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&transceiver1>; + status = "okay"; +}; + +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver2>; + status = "okay"; +}; + +&mcu_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver3>; + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am64-main.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -222,7 +222,7 @@ }; epwm_tbclk: clock@4140 { - compatible = "ti,am64-epwm-tbclk", "syscon"; + compatible = "ti,am64-epwm-tbclk"; reg = <0x4130 0x4>; #clock-cells = <1>; }; @@ -237,6 +237,7 @@ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -248,6 +249,7 @@ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 152 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -259,6 +261,7 @@ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 153 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart3: serial@2830000 { @@ -270,6 +273,7 @@ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 154 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart4: serial@2840000 { @@ -281,6 +285,7 @@ power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 155 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart5: serial@2850000 { @@ -292,6 +297,7 @@ power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 156 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart6: serial@2860000 { @@ -303,6 +309,7 @@ power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 158 0>; clock-names = "fclk"; + status = "disabled"; }; main_i2c0: i2c@20000000 { @@ -314,6 +321,7 @@ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 102 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c1: i2c@20010000 { @@ -325,6 +333,7 @@ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 103 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c2: i2c@20020000 { @@ -336,6 +345,7 @@ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 104 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c3: i2c@20030000 { @@ -347,6 +357,7 @@ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 2>; clock-names = "fck"; + status = "disabled"; }; main_spi0: spi@20100000 { @@ -359,6 +370,7 @@ clocks = <&k3_clks 141 0>; dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; dma-names = "tx0", "rx0"; + status = "disabled"; }; main_spi1: spi@20110000 { @@ -369,6 +381,7 @@ #size-cells = <0>; power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 142 0>; + status = "disabled"; }; main_spi2: spi@20120000 { @@ -379,6 +392,7 @@ #size-cells = <0>; power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 143 0>; + status = "disabled"; }; main_spi3: spi@20130000 { @@ -389,6 +403,7 @@ #size-cells = <0>; power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 144 0>; + status = "disabled"; }; main_spi4: spi@20140000 { @@ -399,6 +414,7 @@ #size-cells = <0>; power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 145 0>; + status = "disabled"; }; main_gpio_intr: interrupt-controller@a00000 { @@ -454,13 +470,19 @@ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; clock-names = "clk_ahb", "clk_xin"; + bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x2>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x6>; ti,otap-del-sel-hs200 = <0x7>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; + status = "disabled"; }; sdhci1: mmc@fa00000 { @@ -470,15 +492,20 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x6>; ti,otap-del-sel-ddr50 = <0x9>; - ti,clkbuf-sel = <0x7>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + status = "disabled"; }; cpsw3g: ethernet@8000000 { @@ -536,6 +563,7 @@ clocks = <&k3_clks 13 0>; clock-names = "fck"; bus_freq = <1000000>; + status = "disabled"; }; cpts@3d000 { @@ -855,6 +883,20 @@ ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; + status = "disabled"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */ + <0 0 0 2 &pcie0_intc 0>, /* INT B */ + <0 0 0 3 &pcie0_intc 0>, /* INT C */ + <0 0 0 4 &pcie0_intc 0>; /* INT D */ + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; }; pcie0_ep: pcie-ep@f102000 { @@ -873,6 +915,7 @@ clocks = <&k3_clks 114 0>; clock-names = "fck"; max-functions = /bits/ 8 <1>; + status = "disabled"; }; epwm0: pwm@23000000 { @@ -882,6 +925,7 @@ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm1: pwm@23010000 { @@ -891,6 +935,7 @@ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm2: pwm@23020000 { @@ -900,6 +945,7 @@ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm3: pwm@23030000 { @@ -909,6 +955,7 @@ power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm4: pwm@23040000 { @@ -918,6 +965,7 @@ power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm5: pwm@23050000 { @@ -927,6 +975,7 @@ power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm6: pwm@23060000 { @@ -936,6 +985,7 @@ power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm7: pwm@23070000 { @@ -945,6 +995,7 @@ power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm8: pwm@23080000 { @@ -954,6 +1005,7 @@ power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ecap0: pwm@23100000 { @@ -963,6 +1015,7 @@ power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 51 0>; clock-names = "fck"; + status = "disabled"; }; ecap1: pwm@23110000 { @@ -972,6 +1025,7 @@ power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 52 0>; clock-names = "fck"; + status = "disabled"; }; ecap2: pwm@23120000 { @@ -981,6 +1035,37 @@ power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 53 0>; clock-names = "fck"; + status = "disabled"; + }; + + eqep0: counter@23200000 { + compatible = "ti,am3352-eqep"; + reg = <0x00 0x23200000 0x00 0x100>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 59 0>; + clock-names = "fck"; + interrupts = ; + status = "disabled"; + }; + + eqep1: counter@23210000 { + compatible = "ti,am3352-eqep"; + reg = <0x00 0x23210000 0x00 0x100>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 60 0>; + clock-names = "fck"; + interrupts = ; + status = "disabled"; + }; + + eqep2: counter@23220000 { + compatible = "ti,am3352-eqep"; + reg = <0x00 0x23220000 0x00 0x100>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 62 0>; + clock-names = "fck"; + interrupts = ; + status = "disabled"; }; main_rti0: watchdog@e000000 { @@ -1008,6 +1093,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x30000000 0x80000>; + assigned-clocks = <&k3_clks 81 0>; + assigned-clock-parents = <&k3_clks 81 2>; icssg0_mem: memories@0 { reg = <0x0 0x2000>, @@ -1033,7 +1120,7 @@ clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ <&k3_clks 81 20>; /* icssg0_iclk */ assigned-clocks = <&icssg0_coreclk_mux>; - assigned-clock-parents = <&k3_clks 81 20>; + assigned-clock-parents = <&k3_clks 81 0>; }; icssg0_iepclk_mux: iepclk-mux@30 { @@ -1047,6 +1134,18 @@ }; }; + icssg0_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + + icssg0_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + icssg0_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; @@ -1057,6 +1156,11 @@ reg = <0x33000 0x1000>; }; + icssg0_pa_stats: pa-stats@2c000 { + compatible = "ti,pruss-pa-st", "syscon"; + reg = <0x2c000 0x1000>; + }; + icssg0_intc: interrupt-controller@20000 { compatible = "ti,icssg-intc"; reg = <0x20000 0x2000>; @@ -1083,6 +1187,9 @@ <0x22400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-pru0_0-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <16 2 2>; + interrupt-names = "vring"; }; rtu0_0: rtu@4000 { @@ -1092,6 +1199,9 @@ <0x23400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-rtu0_0-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <20 4 4>; + interrupt-names = "vring"; }; tx_pru0_0: txpru@a000 { @@ -1110,6 +1220,9 @@ <0x24400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-pru0_1-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <18 3 3>; + interrupt-names = "vring"; }; rtu0_1: rtu@6000 { @@ -1119,6 +1232,9 @@ <0x23c00 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-rtu0_1-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <22 5 5>; + interrupt-names = "vring"; }; tx_pru0_1: txpru@c000 { @@ -1138,6 +1254,7 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -1148,6 +1265,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x30080000 0x80000>; + assigned-clocks = <&k3_clks 82 0>; + assigned-clock-parents = <&k3_clks 82 2>; icssg1_mem: memories@0 { reg = <0x0 0x2000>, @@ -1173,7 +1292,7 @@ clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ <&k3_clks 82 20>; /* icssg1_iclk */ assigned-clocks = <&icssg1_coreclk_mux>; - assigned-clock-parents = <&k3_clks 82 20>; + assigned-clock-parents = <&k3_clks 82 0>; }; icssg1_iepclk_mux: iepclk-mux@30 { @@ -1187,6 +1306,18 @@ }; }; + icssg1_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + + icssg1_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + icssg1_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; @@ -1197,6 +1328,11 @@ reg = <0x33000 0x1000>; }; + icssg1_pa_stats: pa-stats@2c000 { + compatible = "ti,pruss-pa-st", "syscon"; + reg = <0x2c000 0x1000>; + }; + icssg1_intc: interrupt-controller@20000 { compatible = "ti,icssg-intc"; reg = <0x20000 0x2000>; @@ -1223,6 +1359,9 @@ <0x22400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-pru1_0-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <16 2 2>; + interrupt-names = "vring"; }; rtu1_0: rtu@4000 { @@ -1232,6 +1371,9 @@ <0x23400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-rtu1_0-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <20 4 4>; + interrupt-names = "vring"; }; tx_pru1_0: txpru@a000 { @@ -1250,6 +1392,9 @@ <0x24400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-pru1_1-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <18 3 3>; + interrupt-names = "vring"; }; rtu1_1: rtu@6000 { @@ -1259,6 +1404,9 @@ <0x23c00 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-rtu1_1-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <22 5 5>; + interrupt-names = "vring"; }; tx_pru1_1: txpru@c000 { @@ -1278,6 +1426,7 @@ clocks = <&k3_clks 82 0>; clock-names = "fck"; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -1293,6 +1442,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan1: can@20711000 { @@ -1307,6 +1457,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; crypto: crypto@40900000 { @@ -1324,7 +1475,6 @@ compatible = "inside-secure,safexcel-eip76"; reg = <0x00 0x40910000 0x00 0x7d>; interrupts = ; - clocks = <&k3_clks 133 1>; status = "disabled"; /* Used by OP-TEE */ }; }; @@ -1334,8 +1484,8 @@ power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 80 0>; clock-names = "fck"; - reg = <0x00 0x03b000000 0x00 0x400>, - <0x00 0x050000000 0x00 0x8000000>; + reg = <0x00 0x3b000000 0x00 0x400>, + <0x00 0x50000000 0x00 0x8000000>; reg-names = "cfg", "data"; interrupts = ; gpmc,num-cs = <3>; @@ -1346,6 +1496,7 @@ #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + status = "disabled"; }; elm0: ecc@25010000 { @@ -1355,5 +1506,14 @@ power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 54 0>; clock-names = "fck"; + status = "disabled"; + }; + + main_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -14,6 +14,7 @@ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; + status = "disabled"; }; mcu_uart1: serial@4a10000 { @@ -24,6 +25,7 @@ power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 160 0>; clock-names = "fclk"; + status = "disabled"; }; mcu_i2c0: i2c@4900000 { @@ -35,6 +37,7 @@ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 106 2>; clock-names = "fck"; + status = "disabled"; }; mcu_i2c1: i2c@4910000 { @@ -46,6 +49,7 @@ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 2>; clock-names = "fck"; + status = "disabled"; }; mcu_spi0: spi@4b00000 { @@ -56,6 +60,7 @@ #size-cells = <0>; power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 147 0>; + status = "disabled"; }; mcu_spi1: spi@4b10000 { @@ -66,6 +71,7 @@ #size-cells = <0>; power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 148 0>; + status = "disabled"; }; mcu_gpio_intr: interrupt-controller@4210000 { @@ -103,4 +109,16 @@ pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; + + mcu_m4fss: m4fss@5000000 { + compatible = "ti,am64-m4fss"; + reg = <0x00 0x5000000 0x00 0x30000>, + <0x00 0x5040000 0x00 0x10000>; + reg-names = "iram", "dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <9>; + ti,sci-proc-ids = <0x18 0xff>; + resets = <&k3_reset 9 1>; + firmware-name = "am64-mcu-m4f0_0-fw"; + }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&main_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&main_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am64.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am64.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am64.dtsi @@ -8,9 +8,10 @@ #include #include #include -#include #include +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 AM642 SoC"; compatible = "ti,am642"; @@ -69,6 +70,7 @@ <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */ @@ -105,6 +107,8 @@ ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ }; }; + + #include "k3-am64-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for 2nd ICSSG1 port enabling on AM642 EVM + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/icssg1-eth/ethernet-ports/port@0"; + ethernet2 = "/icssg1-eth/ethernet-ports/port@1"; + }; + + mdio-mux-2 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mdio_mux>; + mdio-parent-bus = <&icssg1_mdio>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + icssg1_phy2: ethernet-phy@3 { + reg = <3>; + }; + }; + }; +}; + +&main_pmx0 { + icssg1_mii1_pins_default: icssg1-mii1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x00f8, PIN_INPUT, 1) /* (V9) PRG1_PRU0_GPO16.PR1_MII_MT0_CLK */ + AM64X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (Y9) PRG1_PRU0_GPO15.PR1_MII0_TXEN */ + AM64X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AA9) PRG1_PRU0_GPO14.PR1_MII0_TXD3 */ + AM64X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (W9) PRG1_PRU0_GPO13.PR1_MII0_TXD2 */ + AM64X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (U9) PRG1_PRU0_GPO12.PR1_MII0_TXD1 */ + AM64X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA8) PRG1_PRU0_GPO11.PR1_MII0_TXD0 */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 1) /* (Y8) PRG1_PRU0_GPO4.PR1_MII0_RXDV */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 1) /* (AA7) PRG1_PRU0_GPO6.PR1_MII_MR0_CLK */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 1) /* (V8) PRG1_PRU0_GPO3.PR1_MII0_RXD3 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 1) /* (W8) PRG1_PRU0_GPO2.PR1_MII0_RXD2 */ + AM64X_IOPAD(0x00cc, PIN_INPUT, 1) /* (V13) PRG1_PRU0_GPO5.PR1_MII0_RXER */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 1) /* (U8) PRG1_PRU0_GPO1.PR1_MII0_RXD1 */ + AM64X_IOPAD(0x00b8, PIN_INPUT, 1) /* (Y7) PRG1_PRU0_GPO0.PR1_MII0_RXD0 */ + AM64X_IOPAD(0x00d8, PIN_INPUT, 1) /* (W13) PRG1_PRU0_GPO8.PR1_MII0_RXLINK */ + >; + }; + + icssg1_mii2_pins_default: icssg1-mii-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0148, PIN_INPUT, 1) /* (Y10) PRG1_PRU1_GPO16.PR1_MII_MT1_CLK */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 0) /* (Y11) PRG1_PRU1_GPO15.PR1_MII1_TXEN */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AA11) PRG1_PRU1_GPO14.PR1_MII1_TXD3 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (U10) PRG1_PRU1_GPO13.PR1_MII1_TXD2 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (V10) PRG1_PRU1_GPO12.PR1_MII1_TXD1 */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AA10) PRG1_PRU1_GPO11.PR1_MII1_TXD0 */ + AM64X_IOPAD(0x0118, PIN_INPUT, 1) /* (W12) PRG1_PRU1_GPO4.PR1_MII1_RXDV */ + AM64X_IOPAD(0x0120, PIN_INPUT, 1) /* (U11) PRG1_PRU1_GPO6.PR1_MII_MR1_CLK */ + AM64X_IOPAD(0x0114, PIN_INPUT, 1) /* (Y12) PRG1_PRU1_GPO3.PR1_MII1_RXD3 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 1) /* (AA12) PRG1_PRU1_GPO2.PR1_MII1_RXD2 */ + AM64X_IOPAD(0x011c, PIN_INPUT, 1) /* (AA13) PRG1_PRU1_GPO5.PR1_MII1_RXER */ + AM64X_IOPAD(0x010c, PIN_INPUT, 1) /* (V11) PRG1_PRU1_GPO1.PR1_MII1_RXD1 */ + AM64X_IOPAD(0x0108, PIN_INPUT, 1) /* (W11) PRG1_PRU1_GPO0.PR1_MII1_RXD0 */ + AM64X_IOPAD(0x0128, PIN_INPUT, 1) /* (U12) PRG1_PRU1_GPO8.PR1_MII1_RXLINK */ + >; + }; +}; + +&cpsw3g { + pinctrl-0 = <&rgmii1_pins_default>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&mdio_mux_1 { + status = "disabled"; +}; + +&icssg1_eth { + pinctrl-0 = <&icssg1_mii1_pins_default &icssg1_mii2_pins_default>; +}; + +&icssg1_emac0 { + phy-mode = "mii"; +}; + +&icssg1_emac1 { + status = "okay"; + phy-handle = <&icssg1_phy2>; + phy-mode = "mii"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for 2nd ICSSG1 port enabling on AM642 EVM + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/icssg1-eth/ethernet-ports/port@0"; + ethernet2 = "/icssg1-eth/ethernet-ports/port@1"; + }; + + mdio-mux-2 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mdio_mux>; + mdio-parent-bus = <&icssg1_mdio>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + icssg1_phy2: ethernet-phy@3 { + reg = <3>; + }; + }; + }; +}; + +&main_pmx0 { + icssg1_rgmii2_pins_default: icssg1-rgmii2-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 2) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; +}; + +&cpsw3g { + pinctrl-0 = <&rgmii1_pins_default>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&mdio_mux_1 { + status = "disabled"; +}; + +&icssg1_eth { + pinctrl-0 = <&icssg1_rgmii1_pins_default &icssg1_rgmii2_pins_default>; +}; + +&icssg1_emac1 { + status = "okay"; + phy-handle = <&icssg1_phy2>; + phy-mode = "rgmii-id"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for HSE NAND expansion card on AM642 EVM + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + gpmc0_pins_default: gpmc0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0094, PIN_INPUT, 7) /* (T19) GPMC0_BE1n.GPIO0_36 */ + + AM64X_IOPAD(0x003c, PIN_INPUT, 0) /* (T20) GPMC0_AD0 */ + AM64X_IOPAD(0x0040, PIN_INPUT, 0) /* (U21) GPMC0_AD1 */ + AM64X_IOPAD(0x0064, PIN_INPUT, 0) /* (R16) GPMC0_AD10 */ + AM64X_IOPAD(0x0068, PIN_INPUT, 0) /* (W20) GPMC0_AD11 */ + AM64X_IOPAD(0x006c, PIN_INPUT, 0) /* (W21) GPMC0_AD12 */ + AM64X_IOPAD(0x0070, PIN_INPUT, 0) /* (V18) GPMC0_AD13 */ + AM64X_IOPAD(0x0074, PIN_INPUT, 0) /* (Y21) GPMC0_AD14 */ + AM64X_IOPAD(0x0078, PIN_INPUT, 0) /* (Y20) GPMC0_AD15 */ + AM64X_IOPAD(0x0044, PIN_INPUT, 0) /* (T18) GPMC0_AD2 */ + AM64X_IOPAD(0x0048, PIN_INPUT, 0) /* (U20) GPMC0_AD3 */ + AM64X_IOPAD(0x004c, PIN_INPUT, 0) /* (U18) GPMC0_AD4 */ + AM64X_IOPAD(0x0050, PIN_INPUT, 0) /* (U19) GPMC0_AD5 */ + AM64X_IOPAD(0x0054, PIN_INPUT, 0) /* (V20) GPMC0_AD6 */ + AM64X_IOPAD(0x0058, PIN_INPUT, 0) /* (V21) GPMC0_AD7 */ + AM64X_IOPAD(0x005c, PIN_INPUT, 0) /* (V19) GPMC0_AD8 */ + AM64X_IOPAD(0x0060, PIN_INPUT, 0) /* (T17) GPMC0_AD9 */ + AM64X_IOPAD(0x0098, PIN_INPUT_PULLUP, 0) /* (W19) GPMC0_WAIT0 */ + AM64X_IOPAD(0x009c, PIN_INPUT_PULLUP, 0) /* (Y18) GPMC0_WAIT1 */ + AM64X_IOPAD(0x00a8, PIN_OUTPUT_PULLUP, 0) /* (R19) GPMC0_CSn0 */ + AM64X_IOPAD(0x00ac, PIN_OUTPUT_PULLUP, 0) /* (R20) GPMC0_CSn1 */ + AM64X_IOPAD(0x00b0, PIN_OUTPUT_PULLUP, 0) /* (P19) GPMC0_CSn2 */ + AM64X_IOPAD(0x00b4, PIN_OUTPUT_PULLUP, 0) /* (R21) GPMC0_CSn3 */ + AM64X_IOPAD(0x007c, PIN_OUTPUT, 0) /* (R17) GPMC0_CLK */ + AM64X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (P16) GPMC0_ADVn_ALE */ + AM64X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (R18) GPMC0_OEn_REn */ + AM64X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (T21) GPMC0_WEn */ + AM64X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (P17) GPMC0_BE0n_CLE */ + AM64X_IOPAD(0x00a0, PIN_OUTPUT_PULLUP, 0) /* (N16) GPMC0_WPn */ + AM64X_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (N17) GPMC0_DIR */ + >; + }; +}; + +&main_gpio0 { + gpio0-36 { + gpio-hog; + gpios = <36 0>; + input; + line-name = "GPMC0_MUX_DIR"; + }; +}; + +&elm0 { + status = "okay"; +}; + +&gpmc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&gpmc0_pins_default>; + ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */ + #address-cells = <2>; + #size-cells = <1>; + + nand@0,0 { + compatible = "ti,am64-nand"; + reg = <0 0 64>; /* device IO registers */ + interrupt-parent = <&gpmc0>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-xfer-type = "prefetch-polled"; + ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */ + ti,elm-id = <&elm0>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <25>; + gpmc,adv-wr-off-ns = <25>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <3>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "NAND.tiboot3"; + reg = <0x00000000 0x00200000>; /* 2M */ + }; + partition@200000 { + label = "NAND.tispl"; + reg = <0x00200000 0x00200000>; /* 2M */ + }; + partition@400000 { + label = "NAND.tiboot3.backup"; /* 2M */ + reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */ + }; + partition@600000 { + label = "NAND.u-boot"; + reg = <0x00600000 0x00400000>; /* 4M */ + }; + partition@a00000 { + label = "NAND.u-boot-env"; + reg = <0x00a00000 0x00040000>; /* 256K */ + }; + partition@a40000 { + label = "NAND.u-boot-env.backup"; + reg = <0x00a40000 0x00040000>; /* 256K */ + }; + partition@a80000 { + label = "NAND.file-system"; + reg = <0x00a80000 0x3f580000>; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am642-evm.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -21,6 +21,11 @@ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; + aliases { + ethernet2 = &icssg1_emac0; + ethernet3 = &icssg1_emac1; + }; + memory@80000000 { device_type = "memory"; /* 2G RAM */ @@ -87,6 +92,18 @@ no-map; }; + mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + rtos_ipc_memory_region: ipc-memories@a5000000 { reg = <0x00 0xa5000000 0x00 0x00800000>; alignment = <0x1000>; @@ -167,7 +184,7 @@ mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; }; - mdio-mux-1 { + mdio_mux_1: mdio-mux-1 { compatible = "mdio-mux-multiplexer"; mux-controls = <&mdio_mux>; mdio-parent-bus = <&cpsw3g_mdio>; @@ -181,6 +198,8 @@ cpsw3g_phy3: ethernet-phy@3 { reg = <3>; + tx-internal-delay-ps = <250>; + rx-internal-delay-ps = <2000>; }; }; }; @@ -198,6 +217,73 @@ max-bitrate = <5000000>; standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; }; + + icssg1_eth: icssg1-eth { + compatible = "ti,am642-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_rgmii1_pins_default>; + + sram = <&oc_sram>; + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ti,mii-g-rt = <&icssg1_mii_g_rt>; + ti,mii-rt = <&icssg1_mii_rt>; + ti,pa-stats = <&icssg1_pa_stats>; + iep = <&icssg1_iep0>, <&icssg1_iep1>; + + interrupt-parent = <&icssg1_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>, /* ingress slice 1 */ + <&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */ + <&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + icssg1_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg1_phy1>; + phy-mode = "rgmii-id"; + ti,syscon-rgmii-delay = <&main_conf 0x4110>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + icssg1_emac1: port@1 { + reg = <1>; + ti,syscon-rgmii-delay = <&main_conf 0x4114>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + }; + }; + }; }; &main_pmx0 { @@ -322,9 +408,40 @@ AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ >; }; + + icssg1_mdio1_pins_default: icssg1-mdio1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ + >; + }; + + icssg1_rgmii1_pins_default: icssg1-rgmii1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ + AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ + AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ + AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ + >; + }; + + icssg1_iep0_pins_default: icssg1-iep0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0104, PIN_OUTPUT, 2) /* (W7) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */ + >; + }; }; &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; @@ -334,35 +451,8 @@ status = "reserved"; }; -&main_uart2 { - status = "disabled"; -}; - -&main_uart3 { - status = "disabled"; -}; - -&main_uart4 { - status = "disabled"; -}; - -&main_uart5 { - status = "disabled"; -}; - -&main_uart6 { - status = "disabled"; -}; - -&mcu_uart0 { - status = "disabled"; -}; - -&mcu_uart1 { - status = "disabled"; -}; - &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; @@ -400,28 +490,17 @@ }; }; -/* mcu_gpio0 is reserved for mcu firmware usage */ +/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ &mcu_gpio0 { status = "reserved"; }; -&mcu_i2c0 { - status = "disabled"; -}; - -&mcu_i2c1 { - status = "disabled"; -}; - -&mcu_spi0 { - status = "disabled"; -}; - -&mcu_spi1 { - status = "disabled"; +&mcu_gpio_intr { + status = "reserved"; }; &main_spi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; ti,pindir-d0-out-d1-in; @@ -436,7 +515,7 @@ &sdhci0 { /* emmc */ - bus-width = <8>; + status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; @@ -444,11 +523,10 @@ &sdhci1 { /* SD/MMC */ + status = "okay"; vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; - bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -466,9 +544,13 @@ &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&mdio1_pins_default - &rgmii1_pins_default + pinctrl-0 = <&rgmii1_pins_default &rgmii2_pins_default>; + + /* Map HW8_TS_PUSH to GENF1 */ + cpts@3d000 { + ti,pps = <7 1>; + }; }; &cpsw_port1 { @@ -482,6 +564,10 @@ }; &cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default>; + cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; @@ -509,6 +595,47 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; @@ -579,6 +706,12 @@ <&main_r5fss1_core1_memory_region>; }; +&mcu_m4fss { + mboxes = <&mailbox0_cluster6 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; +}; + &serdes_ln_ctrl { idle-states = ; }; @@ -594,6 +727,7 @@ }; &pcie0_rc { + status = "okay"; reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; @@ -604,83 +738,63 @@ phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; num-lanes = <1>; - status = "disabled"; }; &ecap0 { + status = "okay"; /* PWM is available on Pin 1 of header J12 */ pinctrl-names = "default"; pinctrl-0 = <&main_ecap0_pins_default>; }; -&ecap1 { - status = "disabled"; -}; - -&ecap2 { - status = "disabled"; -}; - -&epwm0 { - status = "disabled"; -}; - -&epwm1 { - status = "disabled"; -}; - -&epwm2 { - status = "disabled"; -}; - -&epwm3 { - status = "disabled"; -}; - -&epwm4 { - status = "disabled"; -}; - -&epwm5 { - status = "disabled"; -}; - -&epwm6 { - status = "disabled"; -}; - -&epwm7 { - status = "disabled"; -}; - -&epwm8 { - status = "disabled"; -}; - -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - &main_mcan0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan0_pins_default>; phys = <&transceiver1>; }; &main_mcan1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan1_pins_default>; phys = <&transceiver2>; }; -&gpmc0 { - status = "disabled"; +&icssg1_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_mdio1_pins_default>; + + icssg1_phy1: ethernet-phy@0 { + reg = <0xf>; + tx-internal-delay-ps = <250>; + rx-internal-delay-ps = <2000>; + }; }; -&elm0 { - status = "disabled"; +#define TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val) + +×ync_router { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_cpts_pps>; + + /* + * Use Time Sync Router to map GENF1 input to HW8_TS_PUSH output as well + * as the PRU ICSSG0 SYNC1 output. + */ + cpsw_cpts_pps: cpsw-cpts-pps { + pinctrl-single,pins = < + /* pps [cpts genf1] in22 -> out37 [cpts hw8_push] */ + TS_OFFSET(37, 22) + /* pps [cpts genf1] in22 -> out26 [SYNC1_OUT pin] */ + TS_OFFSET(26, 22) + >; + }; +}; + +&icssg1_iep0 { + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_iep0_pins_default>; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am642-sk.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -87,6 +87,18 @@ no-map; }; + mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + rtos_ipc_memory_region: ipc-memories@a5000000 { reg = <0x00 0xa5000000 0x00 0x00800000>; alignment = <0x1000>; @@ -336,17 +348,19 @@ AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ >; }; -}; -&mcu_uart0 { - status = "disabled"; -}; - -&mcu_uart1 { - status = "disabled"; + main_eqep0_pins_default: main-eqep0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x00a0, PIN_INPUT, 3) /* (N16) GPMC0_WPn.EQEP0_A */ + AM64X_IOPAD(0x00a4, PIN_INPUT, 3) /* (N17) GPMC0_DIR.EQEP0_B */ + AM64X_IOPAD(0x00ac, PIN_INPUT, 3) /* (R20) GPMC0_CSn1.EQEP0_I */ + AM64X_IOPAD(0x00a8, PIN_INPUT, 3) /* (R19) GPMC0_CSn0.EQEP0_S */ + >; + }; }; &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; @@ -356,35 +370,8 @@ status = "reserved"; }; -&main_uart2 { - status = "disabled"; -}; - -&main_uart3 { - status = "disabled"; -}; - -&main_uart4 { - status = "disabled"; -}; - -&main_uart5 { - status = "disabled"; -}; - -&main_uart6 { - status = "disabled"; -}; - -&mcu_i2c0 { - status = "disabled"; -}; - -&mcu_i2c1 { - status = "disabled"; -}; - &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; @@ -409,24 +396,17 @@ }; }; -&main_i2c3 { - status = "disabled"; -}; - -&mcu_spi0 { - status = "disabled"; -}; - -&mcu_spi1 { - status = "disabled"; +/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ +&mcu_gpio0 { + status = "reserved"; }; -/* mcu_gpio0 is reserved for mcu firmware usage */ -&mcu_gpio0 { +&mcu_gpio_intr { status = "reserved"; }; &sdhci0 { + status = "okay"; vmmc-supply = <&wlan_en>; bus-width = <4>; non-removable; @@ -448,11 +428,10 @@ &sdhci1 { /* SD/MMC */ + status = "okay"; vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; - bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -485,9 +464,13 @@ &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&mdio1_pins_default - &rgmii1_pins_default + pinctrl-0 = <&rgmii1_pins_default &rgmii2_pins_default>; + + /* Map HW8_TS_PUSH to GENF1 */ + cpts@3d000 { + ti,pps = <7 1>; + }; }; &cpsw_port1 { @@ -501,6 +484,10 @@ }; &cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default>; + cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; @@ -533,6 +520,47 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; @@ -603,92 +631,44 @@ <&main_r5fss1_core1_memory_region>; }; -&pcie0_rc { - status = "disabled"; -}; - -&pcie0_ep { - status = "disabled"; +&mcu_m4fss { + mboxes = <&mailbox0_cluster6 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; }; &ecap0 { + status = "okay"; /* PWM is available on Pin 1 of header J3 */ pinctrl-names = "default"; pinctrl-0 = <&main_ecap0_pins_default>; }; -&ecap1 { - status = "disabled"; -}; - -&ecap2 { - status = "disabled"; -}; - -&epwm0 { - status = "disabled"; -}; - -&epwm1 { - status = "disabled"; -}; - -&epwm2 { - status = "disabled"; +&eqep0 { + /* EQEP0_A is available on Pin 18 of header J4 */ + /* EQEP0_B is available on Pin 22 of header J4 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_eqep0_pins_default>; }; -&epwm3 { - status = "disabled"; -}; +#define TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val) -&epwm4 { - /* - * EPWM4_A, EPWM4_B is available on Pin 32 and 33 on J4 (RPi hat) - * But RPi Hat will be used for other use cases, so marking epwm4 as disabled. - */ - status = "disabled"; -}; +×ync_router { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_cpts_pps>; -&epwm5 { /* - * EPWM5_A, EPWM5_B is available on Pin 29 and 31 on J4 (RPi hat) - * But RPi Hat will be used for other use cases, so marking epwm5 as disabled. + * Use Time Sync Router to map GENF1 input to HW8_TS_PUSH output as well + * as the PRU ICSSG0 SYNC1 output. */ - status = "disabled"; -}; - -&epwm6 { - status = "disabled"; -}; - -&epwm7 { - status = "disabled"; -}; - -&epwm8 { - status = "disabled"; -}; - -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - -&main_mcan0 { - status = "disabled"; -}; - -&main_mcan1 { - status = "disabled"; -}; - -&gpmc0 { - status = "disabled"; -}; - -&elm0 { - status = "disabled"; + cpsw_cpts_pps: cpsw-cpts-pps { + pinctrl-single,pins = < + /* pps [cpts genf1] in22 -> out37 [cpts hw8_push] */ + TS_OFFSET(37, 22) + /* pps [cpts genf1] in22 -> out26 [SYNC1_OUT pin] */ + TS_OFFSET(26, 22) + >; + }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am642.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am642.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am642.dtsi @@ -58,6 +58,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x40000>; cache-line-size = <64>; cache-sets = <256>; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -360,15 +360,13 @@ }; &main_uart1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; }; -&main_uart2 { - status = "disabled"; -}; - &mcu_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&arduino_uart_pins_default>; }; @@ -413,12 +411,14 @@ }; &wkup_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; }; &mcu_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_i2c0_pins_default>; clock-frequency = <400000>; @@ -478,6 +478,7 @@ }; &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -495,18 +496,21 @@ }; &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; }; &main_i2c2 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c2_pins_default>; clock-frequency = <400000>; }; &main_i2c3 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c3_pins_default>; clock-frequency = <400000>; @@ -546,6 +550,7 @@ }; &ecap0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins_default>; }; @@ -570,6 +575,7 @@ }; &mcu_spi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_spi0_pins_default>; @@ -603,6 +609,52 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + seboot@0 { + label = "seboot"; + reg = <0x0 0x180000>; /* 1.5M */ + }; + + tispl@180000 { + label = "tispl"; + reg = <0x180000 0x200000>; /* 2M */ + }; + + u-boot@380000 { + label = "u-boot"; + reg = <0x380000 0x300000>; /* 3M */ + }; + + env@680000 { + label = "env"; + reg = <0x680000 0x20000>; /* 128K */ + }; + + env-backup@6a0000 { + label = "env.backup"; + reg = <0x6a0000 0x20000>; /* 128K */ + }; + + otpcmd@6c0000 { + label = "otpcmd"; + reg = <0x6c0000 0x10000>; /* 64K */ + }; + + unused@6d0000 { + label = "unused"; + reg = <0x6d0000 0x7b0000>; /* 7872K */ + }; + + seboot-backup@e80000 { + label = "seboot.backup"; + reg = <0xe80000 0x180000>; /* 1.5M */ + }; + }; }; }; @@ -626,15 +678,8 @@ }; }; -&pcie0_rc { - status = "disabled"; -}; - -&pcie0_ep { - status = "disabled"; -}; - &pcie1_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&minipcie_pins_default>; @@ -644,19 +689,8 @@ reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; }; -&m_can0 { - status = "disabled"; -}; - -&m_can1 { - status = "disabled"; -}; - -&pcie1_ep { - status = "disabled"; -}; - &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -666,6 +700,7 @@ }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { @@ -674,46 +709,6 @@ }; }; -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; @@ -725,27 +720,3 @@ <&mcu_r5fss0_core1_memory_region>; mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; }; - -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - -&icssg2_mdio { - status = "disabled"; -}; - -&mcasp0 { - status = "disabled"; -}; - -&mcasp1 { - status = "disabled"; -}; - -&mcasp2 { - status = "disabled"; -}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am65-main.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -91,6 +91,7 @@ clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -99,6 +100,7 @@ interrupts = ; clock-frequency = <48000000>; power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -107,6 +109,7 @@ interrupts = ; clock-frequency = <48000000>; power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; crypto: crypto@4e00000 { @@ -125,7 +128,6 @@ compatible = "inside-secure,safexcel-eip76"; reg = <0x0 0x4e10000 0x0 0x7d>; interrupts = ; - clocks = <&k3_clks 136 1>; status = "disabled"; /* Used by OP-TEE */ }; }; @@ -155,6 +157,7 @@ clock-names = "fck"; clocks = <&k3_clks 110 1>; power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c1: i2c@2010000 { @@ -166,6 +169,7 @@ clock-names = "fck"; clocks = <&k3_clks 111 1>; power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c2: i2c@2020000 { @@ -177,6 +181,7 @@ clock-names = "fck"; clocks = <&k3_clks 112 1>; power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c3: i2c@2030000 { @@ -188,6 +193,7 @@ clock-names = "fck"; clocks = <&k3_clks 113 1>; power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; ecap0: pwm@3100000 { @@ -197,6 +203,7 @@ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 39 0>; clock-names = "fck"; + status = "disabled"; }; main_spi0: spi@2100000 { @@ -209,6 +216,7 @@ #size-cells = <0>; dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; dma-names = "tx0", "rx0"; + status = "disabled"; }; main_spi1: spi@2110000 { @@ -221,6 +229,7 @@ #size-cells = <0>; assigned-clocks = <&k3_clks 137 1>; assigned-clock-rates = <48000000>; + status = "disabled"; }; main_spi2: spi@2120000 { @@ -231,6 +240,7 @@ power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; main_spi3: spi@2130000 { @@ -241,6 +251,7 @@ power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; main_spi4: spi@2140000 { @@ -251,6 +262,7 @@ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; sdhci0: mmc@4f80000 { @@ -341,11 +353,11 @@ dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { compatible = "syscon"; - reg = <0x0000041e0 0x14>; + reg = <0x000041e0 0x14>; }; ehrpwm_tbclk: clock@4140 { - compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + compatible = "ti,am654-ehrpwm-tbclk"; reg = <0x4140 0x18>; #clock-cells = <1>; }; @@ -500,6 +512,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster1: mailbox@31f81000 { @@ -509,6 +522,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster2: mailbox@31f82000 { @@ -518,6 +532,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster3: mailbox@31f83000 { @@ -527,6 +542,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster4: mailbox@31f84000 { @@ -536,6 +552,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster5: mailbox@31f85000 { @@ -545,6 +562,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster6: mailbox@31f86000 { @@ -554,6 +572,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster7: mailbox@31f87000 { @@ -563,6 +582,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster8: mailbox@31f88000 { @@ -572,6 +592,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster9: mailbox@31f89000 { @@ -581,6 +602,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster10: mailbox@31f8a000 { @@ -590,6 +612,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster11: mailbox@31f8b000 { @@ -599,6 +622,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; ringacc: ringacc@3c000000 { @@ -706,6 +730,20 @@ interrupts = ; msi-map = <0x0 &gic_its 0x0 0x10000>; device_type = "pci"; + status = "disabled"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */ + <0 0 0 2 &pcie0_intc 0>, /* INT B */ + <0 0 0 3 &pcie0_intc 0>, /* INT C */ + <0 0 0 4 &pcie0_intc 0>; /* INT D */ + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; }; pcie0_ep: pcie-ep@5500000 { @@ -719,6 +757,7 @@ max-link-speed = <2>; dma-coherent; interrupts = ; + status = "disabled"; }; pcie1_rc: pcie@5600000 { @@ -739,6 +778,20 @@ interrupts = ; msi-map = <0x0 &gic_its 0x10000 0x10000>; device_type = "pci"; + status = "disabled"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; }; pcie1_ep: pcie-ep@5600000 { @@ -752,6 +805,7 @@ max-link-speed = <2>; dma-coherent; interrupts = ; + status = "disabled"; }; mcasp0: mcasp@2b00000 { @@ -769,6 +823,7 @@ clocks = <&k3_clks 104 0>; clock-names = "fck"; power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp1: mcasp@2b10000 { @@ -786,6 +841,7 @@ clocks = <&k3_clks 105 0>; clock-names = "fck"; power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp2: mcasp@2b20000 { @@ -803,6 +859,7 @@ clocks = <&k3_clks 106 0>; clock-names = "fck"; power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; cal: cal@6f03000 { @@ -835,9 +892,10 @@ <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ + <0x0 0x04a01000 0x0 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; @@ -866,6 +924,13 @@ }; }; + gpu: gpu@7000000 { + compatible = "ti,am654-sgx544", "img,sgx544"; + reg = <0x0 0x7000000 0x0 0x10000>; + interrupts = ; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + }; + ehrpwm0: pwm@3000000 { compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; @@ -873,6 +938,7 @@ power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ehrpwm1: pwm@3010000 { @@ -882,6 +948,7 @@ power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ehrpwm2: pwm@3020000 { @@ -891,6 +958,7 @@ power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ehrpwm3: pwm@3030000 { @@ -900,6 +968,7 @@ power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ehrpwm4: pwm@3040000 { @@ -909,6 +978,7 @@ power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ehrpwm5: pwm@3050000 { @@ -918,6 +988,18 @@ power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + timesync_router: pinctrl@a40000 { + compatible = "pinctrl-single"; + reg = <0x0 0xa40000 0x0 0x800>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x800007ff>; + status = "disabled"; }; icssg0: icssg@b000000 { @@ -967,6 +1049,18 @@ }; }; + icssg0_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + + icssg0_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + icssg0_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; @@ -977,6 +1071,11 @@ reg = <0x33000 0x1000>; }; + icssg0_pa_stats: pa-stats@2c000 { + compatible = "ti,pruss-pa-st", "syscon"; + reg = <0x2c000 0x1000>; + }; + icssg0_intc: interrupt-controller@20000 { compatible = "ti,icssg-intc"; reg = <0x20000 0x2000>; @@ -1003,6 +1102,9 @@ <0x22400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-pru0_0-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <16 2 2>; + interrupt-names = "vring"; }; rtu0_0: rtu@4000 { @@ -1012,6 +1114,9 @@ <0x23400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-rtu0_0-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <20 4 4>; + interrupt-names = "vring"; }; tx_pru0_0: txpru@a000 { @@ -1030,6 +1135,9 @@ <0x24400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-pru0_1-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <18 3 3>; + interrupt-names = "vring"; }; rtu0_1: rtu@6000 { @@ -1039,6 +1147,9 @@ <0x23c00 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-rtu0_1-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <22 5 5>; + interrupt-names = "vring"; }; tx_pru0_1: txpru@c000 { @@ -1058,6 +1169,7 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -1108,6 +1220,18 @@ }; }; + icssg1_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + + icssg1_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + icssg1_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; @@ -1118,6 +1242,11 @@ reg = <0x33000 0x1000>; }; + icssg1_pa_stats: pa-stats@2c000 { + compatible = "ti,pruss-pa-st", "syscon"; + reg = <0x2c000 0x1000>; + }; + icssg1_intc: interrupt-controller@20000 { compatible = "ti,icssg-intc"; reg = <0x20000 0x2000>; @@ -1144,6 +1273,9 @@ <0x22400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-pru1_0-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <16 2 2>; + interrupt-names = "vring"; }; rtu1_0: rtu@4000 { @@ -1153,6 +1285,9 @@ <0x23400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-rtu1_0-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <20 4 4>; + interrupt-names = "vring"; }; tx_pru1_0: txpru@a000 { @@ -1171,6 +1306,9 @@ <0x24400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-pru1_1-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <18 3 3>; + interrupt-names = "vring"; }; rtu1_1: rtu@6000 { @@ -1180,6 +1318,9 @@ <0x23c00 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-rtu1_1-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <22 5 5>; + interrupt-names = "vring"; }; tx_pru1_1: txpru@c000 { @@ -1199,6 +1340,7 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -1249,6 +1391,18 @@ }; }; + icssg2_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg2_iepclk_mux>; + }; + + icssg2_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg2_iepclk_mux>; + }; + icssg2_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; @@ -1259,6 +1413,11 @@ reg = <0x33000 0x1000>; }; + icssg2_pa_stats: pa-stats@2c000 { + compatible = "ti,pruss-pa-st", "syscon"; + reg = <0x2c000 0x1000>; + }; + icssg2_intc: interrupt-controller@20000 { compatible = "ti,icssg-intc"; reg = <0x20000 0x2000>; @@ -1285,6 +1444,9 @@ <0x22400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-pru2_0-fw"; + interrupt-parent = <&icssg2_intc>; + interrupts = <16 2 2>; + interrupt-names = "vring"; }; rtu2_0: rtu@4000 { @@ -1294,6 +1456,9 @@ <0x23400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-rtu2_0-fw"; + interrupt-parent = <&icssg2_intc>; + interrupts = <20 4 4>; + interrupt-names = "vring"; }; tx_pru2_0: txpru@a000 { @@ -1312,6 +1477,9 @@ <0x24400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-pru2_1-fw"; + interrupt-parent = <&icssg2_intc>; + interrupts = <18 3 3>; + interrupt-names = "vring"; }; rtu2_1: rtu@6000 { @@ -1321,6 +1489,9 @@ <0x23c00 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-rtu2_1-fw"; + interrupt-parent = <&icssg2_intc>; + interrupts = <22 5 5>; + interrupt-names = "vring"; }; tx_pru2_1: txpru@c000 { @@ -1340,6 +1511,7 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -22,11 +22,12 @@ mcu_uart0: serial@40a00000 { compatible = "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x100>; - interrupts = ; - clock-frequency = <96000000>; - current-speed = <115200>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + reg = <0x00 0x40a00000 0x00 0x100>; + interrupts = ; + clock-frequency = <96000000>; + current-speed = <115200>; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_ram: sram@41c00000 { @@ -46,6 +47,7 @@ clock-names = "fck"; clocks = <&k3_clks 114 1>; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_spi0: spi@40300000 { @@ -56,6 +58,7 @@ power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; mcu_spi1: spi@40310000 { @@ -66,6 +69,7 @@ power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; mcu_spi2: spi@40320000 { @@ -76,6 +80,7 @@ power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; tscadc0: tscadc@40200000 { @@ -172,6 +177,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; m_can1: mcan@40568000 { @@ -187,6 +193,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; fss: fss@47000000 { @@ -273,6 +280,7 @@ clocks = <&k3_clks 5 10>; clock-names = "fck"; bus_freq = <1000000>; + status = "disabled"; }; cpts@3d000 { Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -54,6 +54,7 @@ clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; wkup_i2c0: i2c@42120000 { @@ -65,6 +66,7 @@ clock-names = "fck"; clocks = <&k3_clks 115 1>; power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; intr_wkup_gpio: interrupt-controller@42200000 { Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am65.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -8,9 +8,10 @@ #include #include #include -#include #include +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 AM654 SoC"; compatible = "ti,am654"; @@ -70,6 +71,7 @@ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */ Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi @@ -50,6 +50,7 @@ }; &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am654-base-board.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -13,6 +13,11 @@ compatible = "ti,am654-evm", "ti,am654"; model = "Texas Instruments AM654 Base Board"; + aliases { + ethernet1 = &icssg2_emac0; + ethernet2 = &icssg2_emac1; + }; + chosen { stdout-path = "serial2:115200n8"; bootargs = "earlycon=ns16550a,mmio32,0x02800000"; @@ -117,6 +122,76 @@ vin-supply = <&vcc3v3_io>; gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; }; + + /* Dual Ethernet application node on PRU-ICSSG2 */ + icssg2_eth: icssg2-eth { + compatible = "ti,am654-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg2_rgmii_pins_default>; + sram = <&msmc_ram>; + ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>, + <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>; + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ti,mii-g-rt = <&icssg2_mii_g_rt>; + ti,mii-rt = <&icssg2_mii_rt>; + ti,pa-stats = <&icssg2_pa_stats>; + iep = <&icssg2_iep0>, <&icssg2_iep1>; + + interrupt-parent = <&icssg2_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + + dmas = <&main_udmap 0xc300>, /* egress slice 0 */ + <&main_udmap 0xc301>, /* egress slice 0 */ + <&main_udmap 0xc302>, /* egress slice 0 */ + <&main_udmap 0xc303>, /* egress slice 0 */ + <&main_udmap 0xc304>, /* egress slice 1 */ + <&main_udmap 0xc305>, /* egress slice 1 */ + <&main_udmap 0xc306>, /* egress slice 1 */ + <&main_udmap 0xc307>, /* egress slice 1 */ + + <&main_udmap 0x4300>, /* ingress slice 0 */ + <&main_udmap 0x4301>, /* ingress slice 1 */ + <&main_udmap 0x4302>, /* mgmnt rsp slice 0 */ + <&main_udmap 0x4303>; /* mgmnt rsp slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + icssg2_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg2_phy0>; + phy-mode = "rgmii-id"; + ti,syscon-rgmii-delay = <&scm_conf 0x4120>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + icssg2_emac1: port@1 { + reg = <1>; + phy-handle = <&icssg2_phy1>; + phy-mode = "rgmii-id"; + ti,syscon-rgmii-delay = <&scm_conf 0x4124>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; }; &wkup_pmx0 { @@ -242,6 +317,43 @@ AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ >; }; + + icssg2_mdio_pins_default: icssg2-mdio-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */ + AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */ + >; + }; + + icssg2_rgmii_pins_default: icssg2-rgmii-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */ + AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */ + AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */ + AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */ + AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */ + AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */ + AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */ + AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */ + AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */ + AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */ + AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */ + AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */ + + AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */ + AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */ + AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */ + AM65X_IOPAD(0x0084, PIN_INPUT, 2) /* (AG18) PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */ + AM65X_IOPAD(0x0098, PIN_OUTPUT, 2) /* (AH16) PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */ + AM65X_IOPAD(0x009c, PIN_OUTPUT, 2) /* (AG16) PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */ + AM65X_IOPAD(0x00a0, PIN_OUTPUT, 2) /* (AF16) PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */ + AM65X_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (AE16) PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */ + AM65X_IOPAD(0x00a8, PIN_INPUT, 2) /* (AD16) PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */ + AM65X_IOPAD(0x0090, PIN_OUTPUT, 2) /* (AE17) PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */ + AM65X_IOPAD(0x008c, PIN_INPUT, 2) /* (AF17) PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */ + AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */ + >; + }; }; &main_pmx1 { @@ -264,6 +376,13 @@ AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ >; }; + + /* Select GPIO1_87 for ICSSG2 PHY interrupt */ + icssg2_phy_irq_pins_default: icssg2-phy-irq-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x0014, PIN_INPUT, 7) /* (A22) EXT_REFCLK1.GPIO1_87 */ + >; + }; }; &wkup_uart0 { @@ -271,13 +390,20 @@ status = "reserved"; }; +&mcu_uart0 { + status = "okay"; + /* Default pinmux */ +}; + &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; &wkup_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; @@ -296,7 +422,13 @@ }; }; +&mcu_i2c0 { + status = "okay"; + /* Default pinmux */ +}; + &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -310,23 +442,27 @@ }; &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; }; &main_i2c2 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c2_pins_default>; clock-frequency = <400000>; }; &ecap0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins_default>; }; &main_spi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; #address-cells = <1>; @@ -398,31 +534,8 @@ status = "disabled"; }; -&pcie0_rc { - status = "disabled"; -}; - -&pcie0_ep { - status = "disabled"; -}; - -&pcie1_rc { - status = "disabled"; -}; - -&pcie1_ep { - status = "disabled"; -}; - -&m_can0 { - status = "disabled"; -}; - -&m_can1 { - status = "disabled"; -}; - &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -432,6 +545,7 @@ }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { @@ -440,46 +554,6 @@ }; }; -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; @@ -507,15 +581,65 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x20000>; + }; + + partition@6a0000 { + label = "ospi.env.backup"; + reg = <0x6a0000 0x20000>; + }; + + partition@6c0000 { + label = "ospi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fe0000 { + label = "ospi.phypattern"; + reg = <0x3fe0000 0x20000>; + }; + }; }; }; &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>; }; &davinci_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mdio_pins_default>; + phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; @@ -528,18 +652,6 @@ phy-handle = <&phy0>; }; -&mcasp0 { - status = "disabled"; -}; - -&mcasp1 { - status = "disabled"; -}; - -&mcasp2 { - status = "disabled"; -}; - &dss { status = "disabled"; }; @@ -553,5 +665,23 @@ }; &icssg2_mdio { - status = "disabled"; + status = "okay"; + pinctrl-names = "default", "icssg2-phy-irq"; + pinctrl-0 = <&icssg2_mdio_pins_default>, <&icssg2_phy_irq_pins_default>; + + icssg2_phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&main_gpio1>; + interrupts = <87 0x2>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; + + icssg2_phy1: ethernet-phy@3 { + reg = <3>; + interrupt-parent = <&main_gpio1>; + interrupts = <87 0x2>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am654-evm-oldi-lcd1evm.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am654-evm-oldi-lcd1evm.dtso @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * OLDI-LCD1EVM Rocktech integrated panel and touch DT overlay for AM654-EVM. + * + * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + display0 { + compatible = "rocktech,rk101ii01d-ct"; + backlight = <&lcd_bl>; + enable-gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>; + port { + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + }; + lcd_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = + <0 32 64 96 128 160 192 224 255>; + default-brightness-level = <8>; + }; +}; + +&dss { + status = "okay"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; +}; + +&main_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + gt928: touchscreen@14 { + status = "okay"; + compatible = "goodix,gt928"; + reg = <0x14>; + + interrupt-parent = <&pca9554>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + + reset-gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>; + irq-gpios = <&pca9554 3 GPIO_ACTIVE_HIGH>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am654-idk.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am654-idk.dtso @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for IDK application board on AM654 EVM + * + * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet3 = "/icssg0-eth/ethernet-ports/port@0"; + ethernet4 = "/icssg0-eth/ethernet-ports/port@1"; + ethernet5 = "/icssg1-eth/ethernet-ports/port@0"; + ethernet6 = "/icssg1-eth/ethernet-ports/port@1"; + }; + + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcan0_gpio_pins_default>; + standby-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcan1_gpio_pins_default>; + standby-gpios = <&main_gpio1 67 GPIO_ACTIVE_LOW>; + }; + + /* Dual Ethernet application node on PRU-ICSSG0 */ + icssg0_eth: icssg0-eth { + compatible = "ti,am654-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg0_rgmii_pins_default>; + sram = <&msmc_ram>; + ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>; + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ti,mii-g-rt = <&icssg0_mii_g_rt>; + ti,mii-rt = <&icssg0_mii_rt>; + ti,pa-stats = <&icssg0_pa_stats>; + iep = <&icssg0_iep0>, <&icssg0_iep1>; + + interrupt-parent = <&icssg0_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + + dmas = <&main_udmap 0xc100>, /* egress slice 0 */ + <&main_udmap 0xc101>, /* egress slice 0 */ + <&main_udmap 0xc102>, /* egress slice 0 */ + <&main_udmap 0xc103>, /* egress slice 0 */ + <&main_udmap 0xc104>, /* egress slice 1 */ + <&main_udmap 0xc105>, /* egress slice 1 */ + <&main_udmap 0xc106>, /* egress slice 1 */ + <&main_udmap 0xc107>, /* egress slice 1 */ + + <&main_udmap 0x4100>, /* ingress slice 0 */ + <&main_udmap 0x4101>, /* ingress slice 1 */ + <&main_udmap 0x4102>, /* mgmnt rsp slice 0 */ + <&main_udmap 0x4103>; /* mgmnt rsp slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + icssg0_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg0_phy0>; + phy-mode = "rgmii-id"; + ti,syscon-rgmii-delay = <&scm_conf 0x4100>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + icssg0_emac1: port@1 { + reg = <1>; + phy-handle = <&icssg0_phy1>; + phy-mode = "rgmii-id"; + ti,syscon-rgmii-delay = <&scm_conf 0x4104>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + + /* Dual Ethernet application node on PRU-ICSSG1 */ + icssg1_eth: icssg1-eth { + compatible = "ti,am654-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_rgmii_pins_default>; + sram = <&msmc_ram>; + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ti,mii-g-rt = <&icssg1_mii_g_rt>; + ti,mii-rt = <&icssg1_mii_rt>; + ti,pa-stats = <&icssg1_pa_stats>; + iep = <&icssg1_iep0>, <&icssg1_iep1>; + + interrupt-parent = <&icssg1_intc>; + interrupts = <24 0 2>, <25 1 3>; + + interrupt-names = "tx_ts0", "tx_ts1"; + + dmas = <&main_udmap 0xc200>, /* egress slice 0 */ + <&main_udmap 0xc201>, /* egress slice 0 */ + <&main_udmap 0xc202>, /* egress slice 0 */ + <&main_udmap 0xc203>, /* egress slice 0 */ + <&main_udmap 0xc204>, /* egress slice 1 */ + <&main_udmap 0xc205>, /* egress slice 1 */ + <&main_udmap 0xc206>, /* egress slice 1 */ + <&main_udmap 0xc207>, /* egress slice 1 */ + + <&main_udmap 0x4200>, /* ingress slice 0 */ + <&main_udmap 0x4201>, /* ingress slice 1 */ + <&main_udmap 0x4202>, /* mgmnt rsp slice 0 */ + <&main_udmap 0x4203>; /* mgmnt rsp slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + icssg1_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg1_phy0>; + phy-mode = "rgmii-id"; + ti,syscon-rgmii-delay = <&scm_conf 0x4110>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + icssg1_emac1: port@1 { + reg = <1>; + phy-handle = <&icssg1_phy1>; + phy-mode = "rgmii-id"; + ti,syscon-rgmii-delay = <&scm_conf 0x4114>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; +}; + +&main_pmx0 { + mcan0_gpio_pins_default: mcan0-gpio-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x023c, PIN_INPUT, 7) /* (V25) PRG0_PRU0_GPIO18:GPIO1_47 */ + >; + }; + + mcan1_gpio_pins_default: mcan1-gpio-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x028c, PIN_INPUT, 7) /* (Y26) PRG0_PRU1_GPIO18.GPIO1_67 */ + >; + }; + + icssg0_mdio_pins_default: icssg0-mdio-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */ + AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */ + >; + }; + + icssg0_rgmii_pins_default: icssg0-rgmii-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */ + AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */ + AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */ + AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */ + AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */ + AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */ + AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */ + AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */ + AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */ + AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */ + AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */ + AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */ + + AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */ + AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */ + AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */ + AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */ + AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */ + AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */ + AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26) PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */ + AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24) PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */ + AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */ + AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25) PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */ + AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */ + AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */ + >; + }; + + icssg0_iep0_pins_default: icssg0-iep0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0240, PIN_INPUT, 2) /* (U24) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */ + >; + }; + + icssg1_mdio_pins_default: icssg1-mdio-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0180, PIN_INPUT, 0) /* (AD18) PRG1_MDIO0_MDIO */ + AM65X_IOPAD(0x0184, PIN_OUTPUT, 0) /* (AH18) PRG1_MDIO0_MDC */ + >; + }; + + icssg1_rgmii_pins_default: icssg1-rgmii-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0130, PIN_INPUT, 2) /* (AH24) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */ + AM65X_IOPAD(0x0134, PIN_INPUT, 2) /* (AH23) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */ + AM65X_IOPAD(0x0138, PIN_INPUT, 2) /* (AG21) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */ + AM65X_IOPAD(0x013c, PIN_INPUT, 2) /* (AH22) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */ + AM65X_IOPAD(0x0160, PIN_OUTPUT, 2) /* (AE20) PRG1_PRU1_GPO12.PRG1_RGMII2_TD0 */ + AM65X_IOPAD(0x0164, PIN_OUTPUT, 2) /* (AF19) PRG1_PRU1_GPO13.PRG1_RGMII2_TD1 */ + AM65X_IOPAD(0x0168, PIN_OUTPUT, 2) /* (AH19) PRG1_PRU1_GPO14.PRG1_RGMII2_TD2 */ + AM65X_IOPAD(0x016c, PIN_OUTPUT, 2) /* (AG19) PRG1_PRU1_GPO15.PRG1_RGMII2_TD3 */ + AM65X_IOPAD(0x0170, PIN_INPUT, 2) /* (AE19) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */ + AM65X_IOPAD(0x015c, PIN_OUTPUT, 2) /* (AC20) PRG1_PRU1_GPO11.PRG1_RGMII2_TX_CTL */ + AM65X_IOPAD(0x0148, PIN_INPUT, 2) /* (AG22) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */ + AM65X_IOPAD(0x0140, PIN_INPUT, 2) /* (AE21) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */ + + AM65X_IOPAD(0x00e0, PIN_INPUT, 2) /* (AE22) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM65X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AG24) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM65X_IOPAD(0x00e8, PIN_INPUT, 2) /* (AF23) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM65X_IOPAD(0x00ec, PIN_INPUT, 2) /* (AD21) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM65X_IOPAD(0x0110, PIN_OUTPUT, 2) /* (AH20) PRG1_PRU0_GPO12.PRG1_RGMII1_TD0 */ + AM65X_IOPAD(0x0114, PIN_OUTPUT, 2) /* (AH21) PRG1_PRU0_GPO13.PRG1_RGMII1_TD1 */ + AM65X_IOPAD(0x0118, PIN_OUTPUT, 2) /* (AG20) PRG1_PRU0_GPO14.PRG1_RGMII1_TD2 */ + AM65X_IOPAD(0x011c, PIN_OUTPUT, 2) /* (AD19) PRG1_PRU0_GPO15.PRG1_RGMII1_TD3 */ + AM65X_IOPAD(0x0120, PIN_INPUT, 2) /* (AD20) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + AM65X_IOPAD(0x010c, PIN_OUTPUT, 2) /* (AF21) PRG1_PRU0_GPO11.PRG1_RGMII1_TX_CTL */ + AM65X_IOPAD(0x00f8, PIN_INPUT, 2) /* (AF22) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM65X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AG23) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + >; + }; + + icssg1_iep0_pins_default: icssg1-iep0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x012c, PIN_INPUT, 2) /* (AG26) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */ + >; + }; +}; + +&wkup_pmx0 { + mcu_mcan0_pins_default: mcu-mcan0-pins-default { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x00ac, PIN_INPUT_PULLUP, 0) /* (W2) MCU_MCAN0_RX */ + AM65X_WKUP_IOPAD(0x00a8, PIN_OUTPUT_PULLUP, 0) /* (W1) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x00c4, PIN_INPUT_PULLUP, 1) /* (AD3) WKUP_GPIO0_5.MCU_MCAN1_RX */ + AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT_PULLUP, 1) /* (AC3) WKUP_GPIO0_4.MCU_MCAN1_TX */ + >; + }; +}; + +&m_can0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&m_can1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&icssg0_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg0_mdio_pins_default>; + #address-cells = <1>; + #size-cells = <0>; + + icssg0_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; + + icssg0_phy1: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&icssg0_iep0 { + pinctrl-names = "default"; + pinctrl-0 = <&icssg0_iep0_pins_default>; +}; + +&icssg1_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_mdio_pins_default>; + #address-cells = <1>; + #size-cells = <0>; + + icssg1_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; + + icssg1_phy1: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&icssg1_iep0 { + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_iep0_pins_default>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am654-pcie-usb2.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am654-pcie-usb2.dtso @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for SERDES personality card: 2lane PCIe + USB2.0 Host on AM654 EVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include +#include +#include +#include "k3-pinctrl.h" + +&serdes0 { + assigned-clocks = <&k3_clks 153 4>, + <&serdes0 AM654_SERDES_CMU_REFCLK>, + <&serdes0 AM654_SERDES_RO_REFCLK>; + assigned-clock-parents = <&k3_clks 153 8>, + <&k3_clks 153 4>, + <&k3_clks 153 4>; + status = "okay"; +}; + +&serdes1 { + assigned-clocks = <&serdes1 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&serdes0 AM654_SERDES_RO_REFCLK>; + status = "okay"; +}; + +&pcie0_rc { + num-lanes = <2>; + phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>; + phy-names = "pcie-phy0", "pcie-phy1"; + reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie0_ep { + num-lanes = <2>; + phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>; + phy-names = "pcie-phy0", "pcie-phy1"; +}; + +&main_pmx0 { + usb0_pins_default: usb0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ + >; + }; +}; + +&dwc3_0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_default>; + dr_mode = "host"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for SERDES personality card: 1lane PCIe + USB3.0 DRD on AM654 EVM + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include +#include +#include + +#include "k3-pinctrl.h" + +&serdes1 { + status = "okay"; +}; + +&pcie1_rc { + num-lanes = <1>; + phys = <&serdes1 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy0"; + reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie1_ep { + num-lanes = <1>; + phys = <&serdes1 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy0"; +}; + +&main_pmx0 { + usb0_pins_default: usb0_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ + >; + }; +}; + +&serdes0 { + status = "okay"; + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; +}; + +&dwc3_0 { + status = "okay"; + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ + phys = <&serdes0 PHY_TYPE_USB3 0>; + phy-names = "usb3-phy"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_default>; + dr_mode = "host"; + maximum-speed = "super-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; +}; + +&usb0_phy { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am654.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am654.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am654.dtsi @@ -93,6 +93,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; @@ -102,6 +103,7 @@ L2_1: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi @@ -50,7 +50,3 @@ ti,driver-strength-ohm = <50>; disable-wp; }; - -&main_uart0 { - status = "disabled"; -}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -0,0 +1,724 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * Base Board: https://www.ti.com/lit/zip/SPRR463 + */ + +/dts-v1/; + +#include "k3-am68-sk-som.dtsi" +#include +#include +#include +#include + +/ { + compatible = "ti,am68-sk", "ti,j721s2"; + model = "Texas Instruments AM68 SK"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + aliases { + serial2 = &main_uart8; + mmc1 = &main_sdhci1; + can0 = &mcu_mcan0; + can1 = &mcu_mcan1; + can2 = &main_mcan6; + can3 = &main_mcan7; + }; + + vusb_main: regulator-vusb-main5v0 { + /* USB MAIN INPUT 5V DC */ + compatible = "regulator-fixed"; + regulator-name = "vusb-main5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: regulator-vsys3v3 { + /* Output of LM5141 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vusb_main>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-sd { + /* Output of TPS22918 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vsys_3v3>; + gpio = <&exp1 8 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: regulator-tlv71033 { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_3v3>; + gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + edp0_refclk: clock-edp0-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver4: can-phy3 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + dp0_pwr_3v3: fixedregulator-dp0-pwr { + compatible = "regulator-fixed"; + regulator-name = "dp0-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; /*P0 - DP0_3V3 _EN */ + enable-active-high; + regulator-always-on; + }; + + + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_pins_default>; + + ddc-i2c-bus = <&mcu_i2c1>; + digital; + + /* HDMI_HPD */ + hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + dvi-bridge { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,tfp410"; + + /* HDMI_PDn */ + powerdown-gpios = <&exp2 0 GPIO_ACTIVE_LOW>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_out0>; + pclk-sample = <1>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&main_pmx0 { + main_uart8_pins_default: main-uart8-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ + J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */ + J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ac, PIN_INPUT, 13) /* (AC25) MCASP0_AXR15.I2C1_SCL */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 13) /* (AD26) MCASP1_AXR3.I2C1_SDA */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ + J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ + J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ + J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ + J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ + J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ + J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */ + >; + }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; + + main_mcan6_pins_default: main-mcan6-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */ + J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */ + >; + }; + + main_mcan7_pins_default: main-mcan7-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */ + J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */ + >; + }; + + dss_vout0_pins_default: dss-vout0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */ + J721S2_IOPAD(0x070, PIN_OUTPUT, 2) /* (R27) MCAN1_RX.VOUT0_DATA1 */ + J721S2_IOPAD(0x04c, PIN_OUTPUT, 2) /* (V27) MCASP1_AXR1.VOUT0_DATA10 */ + J721S2_IOPAD(0x048, PIN_OUTPUT, 2) /* (AB27) MCASP0_AXR2.VOUT0_DATA11 */ + J721S2_IOPAD(0x044, PIN_OUTPUT, 2) /* (Y26) MCASP0_AXR1.VOUT0_DATA12 */ + J721S2_IOPAD(0x040, PIN_OUTPUT, 2) /* (AC28) MCASP0_AXR0.VOUT0_DATA13 */ + J721S2_IOPAD(0x03c, PIN_OUTPUT, 2) /* (U27) MCASP0_AFSX.VOUT0_DATA14 */ + J721S2_IOPAD(0x038, PIN_OUTPUT, 2) /* (AB28) MCASP0_ACLKX.VOUT0_DATA15 */ + J721S2_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AD28) EXT_REFCLK1.VOUT0_DATA16 */ + J721S2_IOPAD(0x030, PIN_OUTPUT, 2) /* (T26) GPIO0_12.VOUT0_DATA17 */ + J721S2_IOPAD(0x02c, PIN_OUTPUT, 2) /* (V23) GPIO0_11.VOUT0_DATA18 */ + J721S2_IOPAD(0x028, PIN_OUTPUT, 2) /* (AB24) MCAN16_RX.VOUT0_DATA19 */ + J721S2_IOPAD(0x07c, PIN_OUTPUT, 2) /* (T27) MCASP0_AXR3.VOUT0_DATA2 */ + J721S2_IOPAD(0x024, PIN_OUTPUT, 2) /* (Y28) MCAN16_TX.VOUT0_DATA20 */ + J721S2_IOPAD(0x020, PIN_OUTPUT, 2) /* (AA23) MCAN15_RX.VOUT0_DATA21 */ + J721S2_IOPAD(0x01c, PIN_OUTPUT, 2) /* (Y24) MCAN15_TX.VOUT0_DATA22 */ + J721S2_IOPAD(0x018, PIN_OUTPUT, 2) /* (W23) MCAN14_RX.VOUT0_DATA23 */ + J721S2_IOPAD(0x068, PIN_OUTPUT, 2) /* (U28) MCAN0_RX.VOUT0_DATA3 */ + J721S2_IOPAD(0x064, PIN_OUTPUT, 2) /* (W28) MCAN0_TX.VOUT0_DATA4 */ + J721S2_IOPAD(0x060, PIN_OUTPUT, 2) /* (AC27) MCASP2_AXR1.VOUT0_DATA5 */ + J721S2_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AA26) MCASP2_AXR0.VOUT0_DATA6 */ + J721S2_IOPAD(0x058, PIN_OUTPUT, 2) /* (AA27) MCASP2_AFSX.VOUT0_DATA7 */ + J721S2_IOPAD(0x054, PIN_OUTPUT, 2) /* (Y27) MCASP2_ACLKX.VOUT0_DATA8 */ + J721S2_IOPAD(0x050, PIN_OUTPUT, 2) /* (W27) MCASP1_AXR2.VOUT0_DATA9 */ + J721S2_IOPAD(0x084, PIN_OUTPUT, 2) /* (AA28) MCASP0_AXR5.VOUT0_DE */ + J721S2_IOPAD(0x080, PIN_OUTPUT, 2) /* (U26) MCASP0_AXR4.VOUT0_HSYNC */ + J721S2_IOPAD(0x078, PIN_OUTPUT, 2) /* (Y25) MCAN2_RX.VOUT0_PCLK */ + J721S2_IOPAD(0x088, PIN_OUTPUT, 2) /* (AD27) MCASP0_AXR6.VOUT0_VP0_VSYNC */ + >; + }; + + hdmi_hpd_pins_default: hdmi-hpd-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x000, PIN_INPUT, 7) /* (AG24) EXTINTN.GPIO0_0 */ + >; + }; + + main_i2c4_pins_default: main-i2c4-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */ + J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */ + >; + }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */ + J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */ + J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */ + J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */ + J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */ + J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */ + J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */ + J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */ + J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */ + J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */ + J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */ + J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */ + J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */ + J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */ + >; + }; +}; + +&wkup_pmx2 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + >; + }; + + mcu_mcan0_pins_default: mcu-mcan0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ + >; + }; + + mcu_i2c1_pins_default: mcu-i2c1-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ + J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ + >; + }; + + mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-pins0-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ + J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ + J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */ + J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/ + J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */ + J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */ + J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */ + J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */ + >; + }; +}; + +&wkup_pmx3 { + mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-pins1-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */ + >; + }; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; + +&main_gpio2 { + status = "disabled"; +}; + +&main_gpio4 { + status = "disabled"; +}; + +&main_gpio6 { + status = "disabled"; +}; + +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>; +}; + +&wkup_gpio1 { + status = "disabled"; +}; + +&wkup_uart0 { + status = "reserved"; +}; + +&main_uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart8_pins_default>; + /* Shared with TFA on this platform */ + power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + exp1: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = " ", " ", " ", " ", " ", + "BOARDID_EEPROM_WP", "CAN_STB", " ", + "GPIO_uSD_PWR_EN", " ", "IO_EXP_PCIe1_M.2_RTSz", + "IO_EXP_MCU_RGMII_RST#", " ", " ", " ", " "; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + + exp3: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", + "IO_EXP_CSI2_EXP_RSTz","CSI0_B_GPIO1", + "CSI1_B_GPIO1"; + }; +}; + +&mcu_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c1_pins_default>; + /* i2c1 is used for DVI DDC, so we need to use 100kHz */ + clock-frequency = <100000>; + + exp2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "HDMI_PDn","HDMI_LS_OE", + "DP0_3V3_EN","eDP_ENABLE"; + }; + + dsi_edp_bridge: dsi-edp-bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clock-names = "refclk"; + clocks = <&edp0_refclk>; + + enable-gpios = <&exp2 3 GPIO_ACTIVE_HIGH>; + + vpll-supply = <&vsys_io_1v8>; + vccio-supply = <&vsys_io_1v8>; + vcca-supply = <&vsys_io_1v2>; + vcc-supply = <&vsys_io_1v2>; + + aux-bus { + panel { + compatible = "ti,panel-edp"; + power-supply = <&dp0_pwr_3v3>; + + port { + dp0_panel_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; + }; + + dsi_edp_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + dp0_out: endpoint { + remote-endpoint = <&dp0_panel_in>; + }; + }; + }; + }; +}; + +&main_i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <400000>; +}; + +&main_sdhci0 { + /* Unused */ + status = "disabled"; +}; + +&main_sdhci1 { + /* SD card */ + pinctrl-0 = <&main_mmc1_pins_default>; + pinctrl-names = "default"; + disable-wp; + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; +}; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +}; + +&serdes_ln_ctrl { + idle-states = , , + , ; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&torrent_phy_dp { + status = "disabled"; +}; + +&serdes0 { + status = "okay"; + + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + + serdes0_usb_link: phy@2 { + status = "okay"; + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 3>; + }; +}; + +&usb_serdes_mux { + idle-states = <0>; /* USB0 to SERDES lane 2 */ +}; + +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "host"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&pcie1_rc { + status = "okay"; + reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&dss { + + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_vout0_pins_default>; + + /* + * These clock assignments are chosen to enable the following outputs: + * + * VP1 - DPI0 + */ + assigned-clocks = <&k3_clks 158 5>; + assigned-clock-parents = <&k3_clks 158 7>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + dpi0_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + /* HDMI */ + port@1 { + reg = <1>; + + dpi_out0: endpoint { + remote-endpoint = <&tfp410_in>; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; + /* MIPI-CSI Connector */ +}; + +&ti_csi2rx1 { + status = "okay"; + /* MIPI-CSI Connector */ +}; + +&dphy_rx0 { + status = "okay"; +}; + +&dphy_rx1 { + status = "okay"; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_ports { + + port@0 { + reg = <0>; + dsi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; + + port@1 { + reg = <1>; + dsi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; +}; + +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan6_pins_default>; + phys = <&transceiver3>; +}; + +&main_mcan7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan7_pins_default>; + phys = <&transceiver4>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-bb-csi2-ov5640.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-bb-csi2-ov5640.dtso @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * LI OV5640 MIPI Camera module. + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&wkup_pmx2 { + csi2_exp_refclk_pins_default: csi2-exp-refclk-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x084, PIN_OUTPUT, 6) /* (F25) WKUP_GPIO0_11.MCU_CLKOUT0 */ + >; + }; +}; + +&k3_clks { + /* Confiure AUDIO_EXT_REFCLK2 pin as output */ + pinctrl-names = "default"; + pinctrl-0 = <&csi2_exp_refclk_pins_default>; +}; + +&main_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + /* CAM0 I2C */ + ti_cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + powerdown-gpios = <&exp3 2 GPIO_ACTIVE_LOW>; + + /* MCU_CLKOUT0 WKUP_GPIO0_11 (F25) */ + clocks = <&k3_clks 157 221>; + clock-names = "xclk"; + + /* HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10 -> REFCLK2 */ + assigned-clocks = <&k3_clks 157 221>; + assigned-clock-parents = <&k3_clks 157 223>; + assigned-clock-rates = <25000000>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-bb-rpi-cam-imx219.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-bb-rpi-cam-imx219.dtso @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for RPi Camera V2.1 (Sony IMX219) interfaced with CSI2 on AM68-SK board. + * https://datasheets.raspberrypi.org/camera/camera-v2-schematic.pdf + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&exp3 { + p01-hog { + /* CSI_MUX_SEL_2 */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI_MUX_SEL_2"; + }; +}; + +&main_i2c1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-switch@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c-alias-pool = /bits/ 16 <0x10 0x11>; + + /* CAM0 I2C */ + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + imx219_0: imx219_0@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + reset-gpios = <&exp3 3 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + cam1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + imx219_1: imx219_1@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + reset-gpios = <&exp3 4 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; + +&csi1_port0 { + status = "okay"; + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-fpdlink-fusion.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-fpdlink-fusion.dtso @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Fusion (FPD-Link III) board on AM68 SK + * https://svtronics.com/portfolio/evm577pfusion-v1-0-fusion/ + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-pinctrl.h" + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&main_i2c1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-switch@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + deser@3d { + compatible = "ti,ds90ub960-q1"; + reg = <0x3d>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + ds90ub960_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX*/ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + ds90ub960_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + deser@36 { + compatible = "ti,ds90ub960-q1"; + reg = <0x36>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + ds90ub960_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX*/ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + ds90ub960_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; +}; + +&csi1_port0 { + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-rpi-hdr-ehrpwm.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-rpi-hdr-ehrpwm.dtso @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling EHRPWMs on RPi expansion header on AM68 SK board. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-pinctrl.h" + +&main_pmx0 { + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */ + J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */ + J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */ + J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */ + J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */ + J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPI0_2 */ + J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */ + J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */ + J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */ + J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */ + J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */ + >; + }; + + rpi_header_ehrpwm0_pins_default: rpi-header-ehrpwm0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0cc, PIN_INPUT, 5) /* (AE27) SPI0_CS0.GPIO0_51.EHRPWM0_A */ + >; + }; + + rpi_header_ehrpwm3_pins_default: rpi-header-ehrpwm3-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x08c, PIN_INPUT, 9) /* (T25) RGMII1_TD0.GPIO0_35.EHRPWM3_A */ + >; + }; + + rpi_header_ehrpwm4_pins_default: rpi-header-ehrpwm4-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0a4, PIN_INPUT, 9) /* (T23) RGMII1_RD2.GPIO0_41.EHRPWM4_A */ + >; + }; +}; + +&main_ehrpwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm0_pins_default>; + status = "okay"; +}; + +&main_ehrpwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm3_pins_default>; + status = "okay"; +}; + +&main_ehrpwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm4_pins_default>; + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-som-ddr-mem-carveout.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-som-ddr-mem-carveout.dtso @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for DDR careveout memory nodes for R5F and C71x DSPs. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + dma_buf_phys { + compatible = "ti,dma-buf-phys"; + }; +}; + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a8000000 { + reg = <0x00 0xa8000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "disabled"; +}; + +&mailbox0_cluster4 { + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + status = "disabled"; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; + +&mailbox0_cluster8 { + status = "disabled"; +}; + +&mailbox0_cluster9 { + status = "disabled"; +}; + +&mailbox0_cluster10 { + status = "disabled"; +}; + +&mailbox0_cluster11 { + status = "disabled"; +}; + +&mailbox1_cluster0 { + status = "disabled"; +}; + +&mailbox1_cluster1 { + status = "disabled"; +}; + +&mailbox1_cluster2 { + status = "disabled"; +}; + +&mailbox1_cluster3 { + status = "disabled"; +}; + +&mailbox1_cluster4 { + status = "disabled"; +}; + +&mailbox1_cluster5 { + status = "disabled"; +}; + +&mailbox1_cluster6 { + status = "disabled"; +}; + +&mailbox1_cluster7 { + status = "disabled"; +}; + +&mailbox1_cluster8 { + status = "disabled"; +}; + +&mailbox1_cluster9 { + status = "disabled"; +}; + +&mailbox1_cluster10 { + status = "disabled"; +}; + +&mailbox1_cluster11 { + status = "disabled"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&c71_0 { + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-j721s2.dtsi" +#include + +/ { + memory@80000000 { + device_type = "memory"; + /* 16 GB RAM */ + reg = <0x00 0x80000000 0x00 0x80000000>, + <0x08 0x80000000 0x03 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x38000000>; + linux,cma-default; + }; + }; +}; + +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ + >; + }; +}; + +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ + >; + }; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + /* AT24C512C-MAHM-T */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am68-sk-v3link-fusion.dtso @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Arducam V3Link UC-A09 board + * https://www.arducam.com/fpd-link-3-cameras/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&exp3 { + p01-hog { + /* CSI_MUX_SEL_2 */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI_MUX_SEL_2"; + }; +}; + +&main_i2c1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-switch@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + /* CAM0 I2C */ + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + ds90ub960_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + ds90ub960_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + /* CAM1 I2C */ + cam1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + ds90ub960_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + ds90ub960_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; \ No newline at end of file Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk-csi2-ov5640.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk-csi2-ov5640.dtso @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for OV5640 Camera module on MIPI CSI connector for AM69 SK board. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&wkup_pmx2 { + csi2_exp_refclk_pins_default: csi2-exp-refclk-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x084, PIN_OUTPUT, 6) /* (M38) WKUP_GPIO0_11.MCU_CLKOUT0 */ + >; + }; +}; + +&k3_clks { + pinctrl-names = "default"; + pinctrl-0 = <&csi2_exp_refclk_pins_default>; +}; + +&exp2 { + p01-hog{ + /* P01 - CSI_MUX_SEL_2 */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + output-high; + line-name = "CSI_MUX_SEL_2"; + }; +}; + +&pca9543 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-alias-pool = /bits/ 16 <0x3c 0x3d>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + /* MCU_CLKOUT0 WKUP_GPIO0_11 (M38) */ + clocks = <&k3_clks 157 174>; + clock-names = "xclk"; + powerdown-gpios = <&exp2 2 GPIO_ACTIVE_LOW>; + + /* HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10 -> REFCLK2 */ + assigned-clocks = <&k3_clks 157 174>; + assigned-clock-parents = <&k3_clks 157 176>; + assigned-clock-rates = <25000000>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + /* MCU_CLKOUT0 WKUP_GPIO0_11 (M38) */ + clocks = <&k3_clks 157 174>; + clock-names = "xclk"; + powerdown-gpios = <&exp2 2 GPIO_ACTIVE_LOW>; + + /* HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10 -> REFCLK2 */ + assigned-clocks = <&k3_clks 157 174>; + assigned-clock-parents = <&k3_clks 157 176>; + assigned-clock-rates = <25000000>; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx2_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; + +&csi2_port0 { + status = "okay"; + + csi2rx2_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&ti_csi2rx2 { + status = "okay"; +}; + +&dphy_rx0 { + status = "okay"; +}; + +&dphy_rx2 { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk-csi2-rpi-cam-imx219.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk-csi2-rpi-cam-imx219.dtso @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for RPi Camera V2.1 (Sony IMX219) interfaced with CSI2 on AM69-SK board. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&exp2 { + p01-hog{ + /* P01 - CSI_MUX_SEL_2 */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI_MUX_SEL_2"; + }; +}; + +&pca9543 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-alias-pool = /bits/ 16 <0x10 0x11>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + imx219_0: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + reset-gpios = <&exp2 3 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + imx219_1: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + reset-gpios = <&exp2 4 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; + +&csi1_port0 { + status = "okay"; + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy_rx0 { + status = "okay"; +}; + +&dphy_rx1 { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk-csi2-v3link-fusion.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk-csi2-v3link-fusion.dtso @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Arducam V3Link UC-A09 board + * https://www.arducam.com/fpd-link-3-cameras/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&exp2 { + p01-hog { + /* P01 - CSI_MUX_SEL_2 */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI_MUX_SEL_2"; + }; +}; + +&pca9543 { + #address-cells = <1>; + #size-cells = <0>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + ds90ub960_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + ds90ub960_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + ds90ub960_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + ds90ub960_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + port@0 { + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; +}; }; + +&cdns_csi2rx1 { + ports { + port@0 { + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy_rx0 { + status = "okay"; +}; + +&dphy_rx1 { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk-ddr-mem-carveout.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk-ddr-mem-carveout.dtso @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for DDR careveout memory nodes for R5F and C71x DSPs. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + dma-buf-phys { + compatible = "ti,dma-buf-phys"; + }; +}; + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core0_memory_region: r5f-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core1_memory_region: r5f-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a9000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a9100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9100000 0x00 0xf00000>; + no-map; + }; + + c71_2_dma_memory_region: c71-dma-memory@aa000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa000000 0x00 0x100000>; + no-map; + }; + + c71_2_memory_region: c71-memory@aa100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa100000 0x00 0xf00000>; + no-map; + }; + + c71_3_dma_memory_region: c71-dma-memory@ab000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab000000 0x00 0x100000>; + no-map; + }; + + c71_3_memory_region: c71-memory@ab100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab100000 0x00 0xf00000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + interrupt-parent = <&main_navss_intr>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + interrupt-parent = <&main_navss_intr>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + interrupt-parent = <&main_navss_intr>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + interrupts = <424>; + interrupt-parent = <&main_navss_intr>; + + mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + interrupt-parent = <&main_navss_intr>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster5 { + status = "okay"; + interrupts = <416>; + interrupt-parent = <&main_navss_intr>; + + mbox_c71_2: mbox-c71-2 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_3: mbox-c71-3 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster6 { + status = "disabled"; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; + +&mailbox0_cluster8 { + status = "disabled"; +}; + +&mailbox0_cluster9 { + status = "disabled"; +}; + +&mailbox0_cluster10 { + status = "disabled"; +}; + +&mailbox0_cluster11 { + status = "disabled"; +}; + +&mailbox1_cluster0 { + status = "disabled"; +}; + +&mailbox1_cluster1 { + status = "disabled"; +}; + +&mailbox1_cluster2 { + status = "disabled"; +}; + +&mailbox1_cluster3 { + status = "disabled"; +}; + +&mailbox1_cluster4 { + status = "disabled"; +}; + +&mailbox1_cluster5 { + status = "disabled"; +}; + +&mailbox1_cluster6 { + status = "disabled"; +}; + +&mailbox1_cluster7 { + status = "disabled"; +}; + +&mailbox1_cluster8 { + status = "disabled"; +}; + +&mailbox1_cluster9 { + status = "disabled"; +}; + +&mailbox1_cluster10 { + status = "disabled"; +}; + +&mailbox1_cluster11 { + status = "disabled"; +}; + +&mcu_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&main_r5fss2_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; + memory-region = <&main_r5fss2_core0_dma_memory_region>, + <&main_r5fss2_core0_memory_region>; +}; + +&main_r5fss2_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; + memory-region = <&main_r5fss2_core1_dma_memory_region>, + <&main_r5fss2_core1_memory_region>; +}; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; + +&c71_2 { + status = "okay"; + mboxes = <&mailbox0_cluster5 &mbox_c71_2>; + memory-region = <&c71_2_dma_memory_region>, + <&c71_2_memory_region>; +}; + +&c71_3 { + status = "okay"; + mboxes = <&mailbox0_cluster5 &mbox_c71_3>; + memory-region = <&c71_3_dma_memory_region>, + <&c71_3_memory_region>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk-fpdlink-fusion-auxport.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk-fpdlink-fusion-auxport.dtso @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Fusion (FPD-Link III) board on AM69 SK CSI2 Aux Port + * https://svtronics.com/portfolio/evm577pfusion-v1-0-fusion/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + clk_fusion1_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&pca9543 { + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deser@3d { + compatible = "ti,ds90ub960-q1"; + reg = <0x3d>; + clocks = <&clk_fusion1_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x6a 0x6b 0x6c 0x6d 0x6e 0x6f>; + + ds90ub960_2_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX*/ + port@4 { + reg = <4>; + ds90ub960_2_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy2>; + }; + }; + }; + + ds90ub960_2_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + port@0 { + status = "okay"; + + csi2_phy2: endpoint { + remote-endpoint = <&ds90ub960_2_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx2 { + status = "okay"; +}; + +&dphy_rx2 { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk-fpdlink-fusion.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk-fpdlink-fusion.dtso @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Fusion (FPD-Link III) board on AM69 SK + * https://svtronics.com/portfolio/evm577pfusion-v1-0-fusion/ + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&pca9543 { + #address-cells = <1>; + #size-cells = <0>; + + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + deser@3d { + compatible = "ti,ds90ub960-q1"; + reg = <0x3d>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + ds90ub960_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX*/ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + ds90ub960_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + deser@36 { + compatible = "ti,ds90ub960-q1"; + reg = <0x36>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + ds90ub960_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX*/ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + ds90ub960_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + port@0 { + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; +}; }; + +&cdns_csi2rx1 { + ports { + port@0 { + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy_rx0 { + status = "okay"; +}; + +&dphy_rx1 { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk-rpi-hdr-ehrpwm.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk-rpi-hdr-ehrpwm.dtso @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling EHRPWMs on RPi expansion header on AM69 SK board. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-pinctrl.h" + +&main_pmx0 { + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0bc, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ + J784S4_IOPAD(0x06c, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ + J784S4_IOPAD(0x0b4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */ + J784S4_IOPAD(0x0c0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ + J784S4_IOPAD(0x00c, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */ + J784S4_IOPAD(0x0b8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */ + J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */ + J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ + J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ + J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ + >; + }; + + rpi_header_ehrpwm0_pins_default: rpi-header-ehrpwm0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0cc, PIN_INPUT, 5) /* (AM37) SPI0_CS0.EHRPWM0_A */ + >; + }; + + rpi_header_ehrpwm3_pins_default: rpi-header-ehrpwm3-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x08c, PIN_INPUT, 9) /* (AE35) MCASP0_AXR7.EHRPWM3_A */ + >; + }; + + rpi_header_ehrpwm4_pins_default: rpi-header-ehrpwm4-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0a4, PIN_INPUT, 9) /* (AJ36) MCASP0_AXR13.EHRPWM4_A */ + >; + }; +}; + +&main_ehrpwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm0_pins_default>; + status = "okay"; +}; + +&main_ehrpwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm3_pins_default>; + status = "okay"; +}; + +&main_ehrpwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm4_pins_default>; + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk.dts =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -0,0 +1,858 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * Design Files: https://www.ti.com/lit/zip/SPRR466 + * TRM: https://www.ti.com/lit/zip/spruj52 + */ + +/dts-v1/; + +#include +#include +#include "k3-j784s4.dtsi" + +/ { + compatible = "ti,am69-sk", "ti,j784s4"; + model = "Texas Instruments AM69 SK"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + aliases { + serial2 = &main_uart8; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + i2c0 = &main_i2c0; + i2c1 = &main_i2c1; + ethernet0 = &mcu_cpsw_port1; + can0 = &mcu_mcan0; + can1 = &mcu_mcan1; + can2 = &main_mcan6; + can3 = &main_mcan7; + }; + + memory@80000000 { + device_type = "memory"; + /* 32G RAM */ + reg = <0x00 0x80000000 0x00 0x80000000>, + <0x08 0x80000000 0x07 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x70000000>; + linux,cma-default; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + }; + + vusb_main: regulator-vusb-main5v0 { + /* USB MAIN INPUT 5V DC */ + compatible = "regulator-fixed"; + regulator-name = "vusb-main5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_5v0: regulator-vsys5v0 { + /* Output of LM61460 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vusb_main>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: regulator-vsys3v3 { + /* Output of LM5143 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vusb_main>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-sd { + /* Output of TPS22918 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vsys_3v3>; + gpio = <&exp1 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: regulator-tlv71033 { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver4: can-phy3 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + dp0_pwr_3v3: regulator { + compatible = "regulator-fixed"; + regulator-name = "dp0-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&dp_pwr_en_pins_default>; + gpio = <&main_gpio0 4 0>; /* DP0_3V3 _EN */ + enable-active-high; + }; + + dp0: connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_pins_default>; + + ddc-i2c-bus = <&mcu_i2c1>; + digital; + + /* HDMI_HPD */ + hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + dvi-bridge { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,tfp410"; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pdn_pins_default>; + + /* HDMI_PDn */ + powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi1_out0>; + pclk-sample = <1>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&main_pmx0 { + main_uart8_pins_default: main-uart8-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ + J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ + J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_SCL */ + J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SDA */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ + J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ + J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ + J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ + J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ + J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ + J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ + J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ + >; + }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ + >; + }; + + main_mcan6_pins_default: main-mcan6-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x098, PIN_INPUT, 0) /* (AH36) MCAN6_RX */ + J784S4_IOPAD(0x094, PIN_OUTPUT, 0) /* (AG35) MCAN6_TX */ + >; + }; + + main_mcan7_pins_default: main-mcan7-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */ + J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ + >; + }; + + dp0_pins_default: dp0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */ + >; + }; + + dp_pwr_en_pins_default: dp-pwr-en-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x010, PIN_INPUT, 7) /* (AH33) MCAN13_RX.GPIO0_4 */ + >; + }; + + dss_vout0_pins_default: dss-vout0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x074, PIN_OUTPUT, 2) /* (AC33) MCAN2_TX.VOUT0_DATA0 */ + J784S4_IOPAD(0x070, PIN_OUTPUT, 2) /* (AH38) MCAN1_RX.VOUT0_DATA1 */ + J784S4_IOPAD(0x07c, PIN_OUTPUT, 2) /* (AJ38) MCASP0_AXR3.VOUT0_DATA2 */ + J784S4_IOPAD(0x068, PIN_OUTPUT, 2) /* (AE38) MCAN0_RX.VOUT0_DATA3 */ + J784S4_IOPAD(0x064, PIN_OUTPUT, 2) /* (AF38) MCAN0_TX.VOUT0_DATA4 */ + J784S4_IOPAD(0x060, PIN_OUTPUT, 2) /* (AE36) MCASP2_AXR1.VOUT0_DATA5 */ + J784S4_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AC36) MCASP2_AXR0.VOUT0_DATA6 */ + J784S4_IOPAD(0x058, PIN_OUTPUT, 2) /* (AE37) MCASP2_AFSX.VOUT0_DATA7 */ + J784S4_IOPAD(0x054, PIN_OUTPUT, 2) /* (AD37) MCASP2_ACLKX.VOUT0_DATA8 */ + J784S4_IOPAD(0x050, PIN_OUTPUT, 2) /* (AC37) MCASP1_AXR2.VOUT0_DATA9 */ + J784S4_IOPAD(0x04c, PIN_OUTPUT, 2) /* (AC32) MCASP1_AXR1.VOUT0_DATA10 */ + J784S4_IOPAD(0x048, PIN_OUTPUT, 2) /* (AK33) MCASP0_AXR2.VOUT0_DATA11 */ + J784S4_IOPAD(0x044, PIN_OUTPUT, 2) /* (AG37) MCASP0_AXR1.VOUT0_DATA12 */ + J784S4_IOPAD(0x040, PIN_OUTPUT, 2) /* (AF37) MCASP0_AXR0.VOUT0_DATA13 */ + J784S4_IOPAD(0x03c, PIN_OUTPUT, 2) /* (AK38) MCASP0_AFSX.VOUT0_DATA14 */ + J784S4_IOPAD(0x038, PIN_OUTPUT, 2) /* (AK35) MCASP0_ACLKX.VOUT0_DATA15 */ + J784S4_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AJ32) EXT_REFCLK1.VOUT0_DATA16 */ + J784S4_IOPAD(0x030, PIN_OUTPUT, 2) /* (AK37) GPIO0_12.VOUT0_DATA17 */ + J784S4_IOPAD(0x02c, PIN_OUTPUT, 2) /* (AL32) GPIO0_11.VOUT0_DATA18 */ + J784S4_IOPAD(0x028, PIN_OUTPUT, 2) /* (AE33) MCAN16_RX.VOUT0_DATA19 */ + J784S4_IOPAD(0x024, PIN_OUTPUT, 2) /* (AH34) MCAN16_TX.VOUT0_DATA20 */ + J784S4_IOPAD(0x020, PIN_OUTPUT, 2) /* (AJ35) MCAN15_RX.VOUT0_DATA21 */ + J784S4_IOPAD(0x01c, PIN_OUTPUT, 2) /* (AG34) MCAN15_TX.VOUT0_DATA22 */ + J784S4_IOPAD(0x018, PIN_OUTPUT, 2) /* (AK36) MCAN14_RX.VOUT0_DATA23 */ + J784S4_IOPAD(0x084, PIN_OUTPUT, 2) /* (AG38) MCASP0_AXR5.VOUT0_DE */ + J784S4_IOPAD(0x080, PIN_OUTPUT, 2) /* (AK34) MCASP0_AXR4.VOUT0_HSYNC */ + J784S4_IOPAD(0x078, PIN_OUTPUT, 2) /* (AH37) MCAN2_RX.VOUT0_PCLK */ + J784S4_IOPAD(0x088, PIN_OUTPUT, 2) /* (AF36) MCASP0_AXR6.VOUT0_VSYNC */ + >; + }; + + hdmi_hpd_pins_default: hdmi-hpd-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */ + >; + }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ + J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ + J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */ + J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ + J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */ + J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */ + J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */ + J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */ + J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ + J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ + J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ + J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */ + J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ + J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ + >; + }; +}; + +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ + J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ + >; + }; +}; + +&wkup_pmx2 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ + J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ + J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ + J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ + J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ + J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ + J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + >; + }; + + mcu_i2c0_pins_default: mcu-i2c0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */ + >; + }; + + mcu_i2c1_pins_default: mcu-i2c1-pins-default { + pinctrl-single,pins = < + /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */ + J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0) + /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */ + J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0) + >; + }; + + hdmi_pdn_pins_default: hdmi-pdn-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */ + >; + }; + + mcu_mcan0_pins_default: mcu-mcan0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ + J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0)/* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ + >; + }; + + mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */ + J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */ + J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ + J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (H38) WKUP_GPIO0_0 */ + J784S4_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (M37) WKUP_GPIO0_56 */ + J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */ + J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (K37) WKUP_GPIO0_15 */ + J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */ + J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */ + >; + }; +}; + +&wkup_pmx3 { + mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */ + >; + }; +}; + +&main_uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart8_pins_default>; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + exp1: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN", + "IO_EXP_MCU_RGMII_RST#", "IO_EXP_PCIe0_4L_PERST#", + "IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_PCIe3_M.2_RTSz", + "PM_INA_BUS_EN", "ENET1_EXP_PWRDN", "EXP1_ENET_RSTz", + "ENET1_I2CMUX_SEL", "PCIe0_CLKREQ#", "PCIe1_M.2_CLKREQ#", + "PCIe3_M2_CLKREQ#", "PCIe0_PRSNT2#_1", "PCIe0_PRSNT2#_2"; + }; +}; + +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + + #address-cells = <1>; + #size-cells = <0>; + + exp2: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz", + "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1"; + }; + + pca9543: i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + }; +}; + +&mcu_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&mcu_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c1_pins_default>; + clock-frequency = <100000>; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; + +&fss { + status = "okay"; +}; + +&main_sdhci0 { + /* eMMC */ + status = "okay"; + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; + no-mmc-hs400; +}; + +&main_sdhci1 { + /* SD card */ + status = "okay"; + pinctrl-0 = <&main_mmc1_pins_default>; + pinctrl-names = "default"; + disable-wp; + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; +}; + +&wkup_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>; +}; + +&wkup_gpio_intr { + status = "okay"; +}; + +&main_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; + +&mcu_cpsw { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; +}; + +&davinci_mdio { + mcu_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&mcu_cpsw_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&mcu_phy0>; +}; + +&serdes_wiz4 { + status = "okay"; +}; + +&serdes4 { + status = "okay"; + serdes4_dp_link: phy@0 { + reg = <0>; + cdns,num-lanes = <4>; + #phy-cells = <0>; + cdns,max-bit-rate = <2700>; + cdns,phy-type = ; + resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, + <&serdes_wiz4 3>, <&serdes_wiz4 4>; + }; +}; + +&dss { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dss_vout0_pins_default>; + assigned-clocks = <&k3_clks 218 2>, + <&k3_clks 218 5>; + assigned-clock-parents = <&k3_clks 218 3>, + <&k3_clks 218 7>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* DP */ + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; + + /* HDMI */ + port@1 { + reg = <1>; + dpi1_out0: endpoint { + remote-endpoint = <&tfp410_in>; + }; + }; +}; + +&mhdp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; + phys = <&serdes4_dp_link>; + phy-names = "dpphy"; +}; + +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , ; +}; + +&serdes_wiz0 { + status = "okay"; +}; + +&serdes0 { + status = "okay"; + serdes0_pcie_link1: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + serdes0_pcie_link2: phy@2 { + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 3>; + }; + serdes0_usb_link: phy@3 { + reg = <3>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 4>; + }; +}; + +&serdes1 { + status = "okay"; + serdes1_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <4>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, <&serdes_wiz1 3>, <&serdes_wiz1 4>; + }; +}; + +&serdes_wiz1 { + status = "okay"; +}; + +&pcie0_rc { + status = "okay"; + reset-gpios = <&exp1 4 GPIO_ACTIVE_HIGH>; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; +}; + +&pcie0_ep { + status = "disabled"; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; +}; + +&pcie1_rc { + status = "okay"; + reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link1>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie1_ep { + status = "disabled"; + phys = <&serdes0_pcie_link1>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie3_rc { + status = "okay"; + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link2>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&pcie3_ep { + status = "disabled"; + phys = <&serdes0_pcie_link2>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&usb_serdes_mux { + idle-states = <0>; /* USB0 to SERDES0 */ +}; + +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan6_pins_default>; + phys = <&transceiver3>; +}; + +&main_mcan7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan7_pins_default>; + phys = <&transceiver4>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-0.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-0.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 0 */ + port@0 { + reg = <0>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@0 { + reg = <0>; + i2c-alias = <0x44>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-1.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-1.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 1 */ + port@1 { + reg = <1>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@1 { + reg = <1>; + i2c-alias = <0x45>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-2.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-2.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 2 */ + port@2 { + reg = <2>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@2 { + reg = <2>; + i2c-alias = <0x46>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-3.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-0-3.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 3 */ + port@3 { + reg = <3>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@3 { + reg = <3>; + i2c-alias = <0x47>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-0.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-0.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 0 */ + port@0 { + reg = <0>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_1_links { + #address-cells = <1>; + #size-cells = <0>; + + link@0 { + reg = <0>; + i2c-alias = <0x54>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-1.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-1.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 1 */ + port@1 { + reg = <1>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_1_links { + #address-cells = <1>; + #size-cells = <0>; + + link@1 { + reg = <1>; + i2c-alias = <0x55>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-2.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-2.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 2 */ + port@2 { + reg = <2>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_1_links { + #address-cells = <1>; + #size-cells = <0>; + + link@2 { + reg = <2>; + i2c-alias = <0x56>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-3.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-1-3.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 3 */ + port@3 { + reg = <3>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_1_links { + #address-cells = <1>; + #size-cells = <0>; + + link@3 { + reg = <3>; + i2c-alias = <0x57>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-0.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-0.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_2_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 0 */ + port@0 { + reg = <0>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_2_links { + #address-cells = <1>; + #size-cells = <0>; + + link@0 { + reg = <0>; + i2c-alias = <0x64>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-1.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-1.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_2_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 1 */ + port@1 { + reg = <1>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_2_links { + #address-cells = <1>; + #size-cells = <0>; + + link@1 { + reg = <1>; + i2c-alias = <0x65>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-2.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-2.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_2_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 2 */ + port@2 { + reg = <2>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_2_links { + #address-cells = <1>; + #size-cells = <0>; + + link@2 { + reg = <2>; + i2c-alias = <0x66>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-3.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-imx390-rcm-2-3.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * https://www.d3engineering.co/product/designcore-d3rcm-imx390-953-rugged-camera-module/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_2_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 3 */ + port@3 { + reg = <3>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_2_links { + #address-cells = <1>; + #size-cells = <0>; + + link@3 { + reg = <3>; + i2c-alias = <0x67>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@1a { + compatible = "sony,imx390"; + reg = <0x1a>; + + clocks = <&serializer>; + clock-names = "inck"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <27000000>; + + xclr-gpios = <&serializer 1 GPIO_ACTIVE_LOW>; + error0-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + error1-gpios = <&serializer 3 GPIO_ACTIVE_HIGH>; + comready-gpios = <&serializer 0 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-0.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-0.dtso @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 0 */ + port@0 { + reg = <0>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@0 { + reg = <0>; + i2c-alias = <0x44>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2>; + /*clock-noncontinuous;*/ + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@60 { + compatible = "ovti,ov2312"; + reg = <0x60>; + + clocks = <&serializer>; + clock-names = "xvclk"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <24000000>; + + reset-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-1.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-1.dtso @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 1 */ + port@1 { + reg = <1>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@1 { + reg = <1>; + i2c-alias = <0x45>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2>; + /*clock-noncontinuous;*/ + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@60 { + compatible = "ovti,ov2312"; + reg = <0x60>; + + clocks = <&serializer>; + clock-names = "xvclk"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <24000000>; + + reset-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-2.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-2.dtso @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 2 */ + port@2 { + reg = <2>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@2 { + reg = <2>; + i2c-alias = <0x46>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2>; + /*clock-noncontinuous;*/ + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@60 { + compatible = "ovti,ov2312"; + reg = <0x60>; + + clocks = <&serializer>; + clock-names = "xvclk"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <24000000>; + + reset-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-3.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-fpdlink-ov2312-0-3.dtso @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX390 FPD-Link 3 Camera Module + * Copyright (c) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&ds90ub960_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 3 */ + port@3 { + reg = <3>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@3 { + reg = <3>; + i2c-alias = <0x47>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + data-lanes = <1 2>; + /*clock-noncontinuous;*/ + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@60 { + compatible = "ovti,ov2312"; + reg = <0x60>; + + clocks = <&serializer>; + clock-names = "xvclk"; + assigned-clocks = <&serializer>; + assigned-clock-rates = <24000000>; + + reset-gpios = <&serializer 2 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -78,9 +78,56 @@ states = <1800000 0x0>, <3300000 0x1>; }; + + transceiver1: can-phy1 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 58 GPIO_ACTIVE_LOW>; + enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver3: can-phy3 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; + enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; + mux-states = <&mux0 1>; + }; +}; + +&wkup_pmx0{ }; &wkup_pmx2 { + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x90, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ @@ -98,15 +145,57 @@ >; }; + wkup_gpio_pins_default: wkup-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ + >; + }; + mcu_mdio_pins_default: mcu-mdio1-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ >; }; + + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x54, PIN_INPUT, 0) /* (A17) MCU_MCAN0_RX */ + J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (A16) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x6c, PIN_INPUT, 0) /* (B16) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (D13) WKUP_GPIO0_4.MCU_MCAN1_TX */ + >; + }; + + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x58, PIN_INPUT, 7) /* (B18) WKUP_GPIO0_0 */ + J721E_WKUP_IOPAD(0x40, PIN_INPUT, 7) /* (B17) MCU_SPI0_D1 */ + >; + }; + + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x60, PIN_INPUT, 7) /* (D14) WKUP_GPIO0_2 */ + >; + }; }; &main_pmx0 { + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ + J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ + J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ + J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ + >; + }; + main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ @@ -139,6 +228,13 @@ J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ >; }; + + main_mcan3_pins_default: main-mcan3-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x3c, PIN_INPUT, 0) /* (W16) MCAN3_RX */ + J721E_IOPAD(0x38, PIN_OUTPUT, 0) /* (Y21) MCAN3_TX */ + >; + }; }; &main_pmx1 { @@ -152,11 +248,28 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&mcu_uart0 { + status = "okay"; + /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart0 { + status = "okay"; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; +}; + +&main_uart1 { + status = "okay"; + /* Default pinmux */ }; &main_uart2 { @@ -164,41 +277,6 @@ status = "reserved"; }; -&main_uart3 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart4 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart5 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart6 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart7 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart8 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart9 { - /* UART not brought out */ - status = "disabled"; -}; - &main_gpio2 { status = "disabled"; }; @@ -211,6 +289,11 @@ status = "disabled"; }; +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; +}; + &wkup_gpio1 { status = "disabled"; }; @@ -218,6 +301,11 @@ &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + + cpts@3d000 { + /* Map HW4_TS_PUSH to GENF1 */ + ti,pps = <3 1>; + }; }; &davinci_mdio { @@ -234,6 +322,7 @@ }; &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -261,6 +350,7 @@ * The i2c1 of the CPB (as it is labeled) is not connected to j7200. */ &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; @@ -355,3 +445,40 @@ num-lanes = <2>; status = "disabled"; }; + +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan3_pins_default>; + phys = <&transceiver3>; +}; + +#define K3_TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val) + +×ync_router { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_cpts>; + + /* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */ + mcu_cpsw_cpts: mcu-cpsw-cpts { + pinctrl-single,pins = < + /* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */ + K3_TS_OFFSET(25, 17) + >; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-evm-mcspi-loopback.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-evm-mcspi-loopback.dtso @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MCSPI internal master-slave loopback example overlay for J7200. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * J7200 has MCSPI4 connected as master to MCU_MCSPI2 by default and not + * pinned out to external pads, This overlay enables spidev on these + * interfaces for userspace testing. + */ + +/dts-v1/; +/plugin/; + +&main_spi4 { + status = "okay"; + #address-cells = <0>; + #size-cells = <0>; + spi-slave; + dmas = <&main_udmap 0xc610>, <&main_udmap 0x4610>; + dma-names = "tx0", "rx0"; + + slave { + /* + * Using spidev compatible is warned loudly, + * thus use another equivalent compatible id + * from spidev. + */ + compatible = "rohm,dh2228fv"; + spi-max-frequency = <24000000>; + }; +}; + +&mcu_spi2 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + spidev@0 { + /* + * Using spidev compatible is warned loudly, + * thus use another equivalent compatible id + * from spidev. + */ + compatible = "rohm,dh2228fv"; + spi-max-frequency = <24000000>; + reg = <0>; + }; +}; \ No newline at end of file Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with + * J7200 board. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; + ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; + ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; + }; +}; + +&cpsw0 { + status = "okay"; +}; + +&cpsw0_port1 { + status = "okay"; + phy-handle = <&cpsw5g_phy0>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 1>; +}; + +&cpsw0_port2 { + status = "okay"; + phy-handle = <&cpsw5g_phy1>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 2>; +}; + +&cpsw0_port3 { + status = "okay"; + phy-handle = <&cpsw5g_phy2>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 3>; +}; + +&cpsw0_port4 { + status = "okay"; + phy-handle = <&cpsw5g_phy3>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 4>; +}; + +&cpsw5g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default>; + reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <120000>; + #address-cells = <1>; + #size-cells = <0>; + + cpsw5g_phy0: ethernet-phy@16 { + reg = <16>; + }; + cpsw5g_phy1: ethernet-phy@17 { + reg = <17>; + }; + cpsw5g_phy2: ethernet-phy@18 { + reg = <18>; + }; + cpsw5g_phy3: ethernet-phy@19 { + reg = <19>; + }; +}; + +&exp2 { + qsgmii-line-hog { + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "qsgmii-pwrdn-line"; + }; +}; + +&main_pmx0 { + mdio0_pins_default: mdio0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */ + J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */ + >; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-evm-virt-mac-client.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-evm-virt-mac-client.dtso @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling CPSW Virt MAC Client driver in linux to interface with EthFw via the + * Linux MAC Only port as well as the Switch Ports of the CPSW5G CPSW instance. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + cpsw5g_virt_mac: main-r5fss-cpsw5g-virt-mac0 { + compatible = "ti,j721e-cpsw-virt-mac"; + dma-coherent; + ti,psil-base = <0x4a00>; + ti,remote-name = "mpu_1_0_ethswitch-device-0"; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + virt-emac-port { + ti,label = "virt-port"; + /* local-mac-address = [0 0 0 0 0 0]; */ + }; + }; + + cpsw5g_virt_maconly: main-r5fss-cpsw5g-virt-mac1 { + compatible = "ti,j721e-cpsw-virt-mac"; + dma-coherent; + ti,psil-base = <0x4a00>; + ti,remote-name = "mpu_1_0_ethmac-device-1"; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + virt-emac-port { + ti,label = "virt-port"; + /* local-mac-address = [0 0 0 0 0 0]; */ + }; + }; +}; + +/* uart2 is assigned to cpsw9g eth-switch fw running on remote CPU core */ +&main_uart2 { + status = "reserved"; +}; + +/* Reserve shared memory for inter-core network communication */ +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + + main_r5fss0_core0_shared_memory_queue_region:r5f-virtual-eth-queues@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x200000>; + no-map; + }; + + main_r5fss0_core0_shared_memory_bufpool_region:r5f-virtual-eth-buffers@a5200000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5200000 0x00 0x1e00000>; + no-map; + }; +}; + +&main_r5fss0_core0 { + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>, + <&main_r5fss0_core0_shared_memory_queue_region>, + <&main_r5fss0_core0_shared_memory_bufpool_region>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -39,6 +39,13 @@ <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ }; + cpsw0_phy_gmii_sel: phy@4044 { + compatible = "ti,j7200-cpsw5g-phy-gmii-sel"; + ti,qsgmii-main-ports = <1>; + reg = <0x4044 0x10>; + #phy-cells = <1>; + }; + usb_serdes_mux: mux-controller@4000 { compatible = "mmio-mux"; #mux-control-cells = <1>; @@ -142,6 +149,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster1: mailbox@31f81000 { @@ -151,6 +159,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster2: mailbox@31f82000 { @@ -160,6 +169,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster3: mailbox@31f83000 { @@ -169,6 +179,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster4: mailbox@31f84000 { @@ -178,6 +189,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster5: mailbox@31f85000 { @@ -187,6 +199,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster6: mailbox@31f86000 { @@ -196,6 +209,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster7: mailbox@31f87000 { @@ -205,6 +219,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster8: mailbox@31f88000 { @@ -214,6 +229,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster9: mailbox@31f89000 { @@ -223,6 +239,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster10: mailbox@31f8a000 { @@ -232,6 +249,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster11: mailbox@31f8b000 { @@ -241,6 +259,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; main_ringacc: ringacc@3c000000 { @@ -292,8 +311,89 @@ }; }; + cpsw0: ethernet@c000000 { + compatible = "ti,j7200-cpswxg-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0xc000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; + clocks = <&k3_clks 19 33>; + clock-names = "fck"; + power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + cpsw0_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + status = "disabled"; + }; + + cpsw0_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + status = "disabled"; + }; + + cpsw0_port3: port@3 { + reg = <3>; + ti,mac-only; + label = "port3"; + status = "disabled"; + }; + + cpsw0_port4: port@4 { + reg = <4>; + ti,mac-only; + label = "port4"; + status = "disabled"; + }; + }; + + cpsw5g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 19 33>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 19 16>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x11c000 0x00 0x10c>; #pinctrl-cells = <1>; @@ -302,7 +402,7 @@ }; main_pmx1: pinctrl@11c11c { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x11c11c 0x00 0xc>; #pinctrl-cells = <1>; @@ -319,6 +419,7 @@ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -330,6 +431,7 @@ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 278 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -341,6 +443,7 @@ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 279 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart3: serial@2830000 { @@ -352,6 +455,7 @@ power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 280 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart4: serial@2840000 { @@ -363,6 +467,7 @@ power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 281 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart5: serial@2850000 { @@ -374,6 +479,7 @@ power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 282 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart6: serial@2860000 { @@ -385,6 +491,7 @@ power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 283 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart7: serial@2870000 { @@ -396,6 +503,7 @@ power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 284 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart8: serial@2880000 { @@ -407,6 +515,7 @@ power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 285 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart9: serial@2890000 { @@ -418,6 +527,7 @@ power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 286 2>; clock-names = "fclk"; + status = "disabled"; }; main_i2c0: i2c@2000000 { @@ -429,6 +539,7 @@ clock-names = "fck"; clocks = <&k3_clks 187 1>; power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; + status = "disabled"; }; main_i2c1: i2c@2010000 { @@ -440,6 +551,7 @@ clock-names = "fck"; clocks = <&k3_clks 188 1>; power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c2: i2c@2020000 { @@ -451,6 +563,7 @@ clock-names = "fck"; clocks = <&k3_clks 189 1>; power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c3: i2c@2030000 { @@ -462,6 +575,7 @@ clock-names = "fck"; clocks = <&k3_clks 190 1>; power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c4: i2c@2040000 { @@ -473,6 +587,7 @@ clock-names = "fck"; clocks = <&k3_clks 191 1>; power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c5: i2c@2050000 { @@ -484,6 +599,7 @@ clock-names = "fck"; clocks = <&k3_clks 192 1>; power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c6: i2c@2060000 { @@ -495,6 +611,7 @@ clock-names = "fck"; clocks = <&k3_clks 193 1>; power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_sdhci0: mmc@4f80000 { @@ -511,6 +628,7 @@ ti,otap-del-sel-hs400 = <0x5>; ti,itap-del-sel-legacy = <0x10>; ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; ti,strobe-sel = <0x77>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; @@ -627,6 +745,20 @@ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <0>; + interrupt-parent = <&gic500>; + interrupts = ; + }; }; pcie1_ep: pcie-ep@2910000 { @@ -748,6 +880,364 @@ clock-names = "gpio"; }; + main_mcan0: can@2701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02701000 0x00 0x200>, + <0x00 0x02708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>, <&k3_clks 156 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan1: can@2711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02711000 0x00 0x200>, + <0x00 0x02718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>, <&k3_clks 158 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan2: can@2721000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02721000 0x00 0x200>, + <0x00 0x02728000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 160 0>, <&k3_clks 160 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan3: can@2731000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02731000 0x00 0x200>, + <0x00 0x02738000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 161 0>, <&k3_clks 161 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan4: can@2741000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02741000 0x00 0x200>, + <0x00 0x02748000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 162 0>, <&k3_clks 162 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan5: can@2751000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02751000 0x00 0x200>, + <0x00 0x02758000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 163 0>, <&k3_clks 163 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan6: can@2761000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02761000 0x00 0x200>, + <0x00 0x02768000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 164 0>, <&k3_clks 164 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan7: can@2771000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02771000 0x00 0x200>, + <0x00 0x02778000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 165 0>, <&k3_clks 165 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan8: can@2781000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02781000 0x00 0x200>, + <0x00 0x02788000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 166 0>, <&k3_clks 166 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan9: can@2791000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02791000 0x00 0x200>, + <0x00 0x02798000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 167 0>, <&k3_clks 167 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan10: can@27a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027a1000 0x00 0x200>, + <0x00 0x027a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 168 0>, <&k3_clks 168 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan11: can@27b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027b1000 0x00 0x200>, + <0x00 0x027b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 169 0>, <&k3_clks 169 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan12: can@27c1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027c1000 0x00 0x200>, + <0x00 0x027c8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 170 0>, <&k3_clks 170 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan13: can@27d1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027d1000 0x00 0x200>, + <0x00 0x027d8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 171 0>, <&k3_clks 171 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan14: can@2681000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02681000 0x00 0x200>, + <0x00 0x02688000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 150 0>, <&k3_clks 150 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan15: can@2691000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02691000 0x00 0x200>, + <0x00 0x02698000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 151 0>, <&k3_clks 151 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan16: can@26a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x026a1000 0x00 0x200>, + <0x00 0x026a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>, <&k3_clks 152 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan17: can@26b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x026b1000 0x00 0x200>, + <0x00 0x026b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 153 0>, <&k3_clks 153 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_spi0: spi@2100000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 266 1>; + status = "disabled"; + }; + + main_spi1: spi@2110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 267 1>; + status = "disabled"; + }; + + main_spi2: spi@2120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 268 1>; + status = "disabled"; + }; + + main_spi3: spi@2130000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02130000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 269 1>; + status = "disabled"; + }; + + main_spi4: spi@2140000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02140000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 270 1>; + status = "disabled"; + }; + + main_spi5: spi@2150000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02150000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 271 1>; + status = "disabled"; + }; + + main_spi6: spi@2160000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02160000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 272 1>; + status = "disabled"; + }; + + main_spi7: spi@2170000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02170000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 273 1>; + status = "disabled"; + }; + watchdog0: watchdog@2200000 { compatible = "ti,j7-rti-wdt"; reg = <0x0 0x2200000 0x0 0x100>; @@ -768,7 +1258,7 @@ main_r5fss0: r5fss@5c00000 { compatible = "ti,j7200-r5fss"; - ti,cluster-mode = <1>; + ti,cluster-mode = <0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x5c00000 0x00 0x5c00000 0x20000>, @@ -805,4 +1295,15 @@ ti,loczrama = <1>; }; }; + + timesync_router: pinctrl@a40000 { + compatible = "ti,j7200-padconf", "pinctrl-single"; + reg = <0x0 0xa40000 0x0 0x800>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000107ff>; + status = "disabled"; + }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -54,7 +54,7 @@ }; wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c000 0x00 0x34>; #pinctrl-cells = <1>; @@ -63,7 +63,7 @@ }; wkup_pmx1: pinctrl@0x4301c038 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c038 0x00 0x8>; #pinctrl-cells = <1>; @@ -72,7 +72,7 @@ }; wkup_pmx2: pinctrl@0x4301c068 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c068 0x00 0xec>; #pinctrl-cells = <1>; @@ -81,7 +81,7 @@ }; wkup_pmx3: pinctrl@0x4301c174 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c174 0x00 0x20>; #pinctrl-cells = <1>; @@ -106,6 +106,7 @@ power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 287 2>; clock-names = "fclk"; + status = "disabled"; }; mcu_uart0: serial@40a00000 { @@ -117,6 +118,7 @@ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 2>; clock-names = "fclk"; + status = "disabled"; }; wkup_gpio_intr: interrupt-controller@42200000 { @@ -276,6 +278,7 @@ clock-names = "fck"; clocks = <&k3_clks 194 1>; power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_i2c1: i2c@40b10000 { @@ -287,6 +290,7 @@ clock-names = "fck"; clocks = <&k3_clks 195 1>; power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; wkup_i2c0: i2c@42120000 { @@ -298,6 +302,40 @@ clock-names = "fck"; clocks = <&k3_clks 197 1>; power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; + status = "disabled"; + }; + + mcu_spi0: spi@40300000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040300000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 274 0>; + status = "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040310000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 275 0>; + status = "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040320000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 0>; + status = "disabled"; }; fss: syscon@47000000 { @@ -365,7 +403,7 @@ mcu_r5fss0: r5fss@41000000 { compatible = "ti,j7200-r5fss"; - ti,cluster-mode = <1>; + ti,cluster-mode = <0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x41000000 0x00 0x41000000 0x20000>, @@ -421,4 +459,50 @@ status = "disabled"; /* Used by OP-TEE */ }; }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0x42040000 0x00 0x350>, + <0x00 0x42050000 0x00 0x350>, + <0x00 0x43000300 0x00 0x10>; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; + + mcu_esm: esm@40800000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x40800000 0x00 0x1000>; + ti,esm-pins = <95>; + bootph-pre-ram; + }; + + mcu_mcan0: can@40528000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40528000 0x00 0x200>, + <0x00 0x40500000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 172 0>, <&k3_clks 172 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcu_mcan1: can@40568000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40568000 0x00 0x200>, + <0x00 0x40540000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 173 0>, <&k3_clks 173 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -5,6 +5,8 @@ /dts-v1/; +#include + #include "k3-j7200.dtsi" / { @@ -80,6 +82,25 @@ no-map; }; }; + + mux0: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; + }; + + mux1: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver0: can-phy0 { + /* standby pin has been grounded by default */ + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; }; &wkup_pmx0 { @@ -118,6 +139,25 @@ }; }; +&wkup_pmx2 { + /* wkup_pmx2 starts at 0x68 */ + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ + J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ + >; + }; +}; + +&wkup_pmx3 { + /* wkup_pmx3 starts at 0x174 */ + pmic_irq_pins_default: pmic-irq-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 7) /* (E18) WKUP_GPIO0_84 */ + >; + }; +}; + &main_pmx0 { main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < @@ -125,6 +165,13 @@ J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ >; }; + + main_mcan0_pins_default: main-mcan0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x24, PIN_INPUT, 0) /* (V20) MCAN0_RX */ + J721E_IOPAD(0x20, PIN_OUTPUT, 0) /* (V18) MCAN0_TX */ + >; + }; }; &hbmc { @@ -140,10 +187,42 @@ flash@0,0 { compatible = "cypress,hyperflash", "cfi-flash"; reg = <0x00 0x00 0x4000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "hbmc.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "hbmc.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "hbmc.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "hbmc.env"; + reg = <0x700000 0x40000>; + }; + + partition@800000 { + label = "hbmc.rootfs"; + reg = <0x800000 0x3800000>; + }; + }; }; }; &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -158,6 +237,7 @@ }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { @@ -171,46 +251,6 @@ }; }; -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, @@ -267,5 +307,209 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + tps659414: pmic@48 { + compatible = "ti,tps6594-q1"; + reg = <0x48>; + ti,primary-pmic; + system-power-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&wkup_gpio0>; + interrupts = <84 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + buck1-supply = <&vsys_3v3>; + buck2-supply = <&vsys_3v3>; + buck3-supply = <&vsys_3v3>; + buck4-supply = <&vsys_3v3>; + buck5-supply = <&vsys_3v3>; + ldo1-supply = <&vsys_3v3>; + ldo2-supply = <&vsys_3v3>; + ldo3-supply = <&vsys_3v3>; + ldo4-supply = <&vsys_3v3>; + + regulators { + bucka1: buck1 { + regulator-name = "vda_mcu_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka2: buck2 { + regulator-name = "vdd_mcuio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka3: buck3 { + regulator-name = "vdd_mcu_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka4: buck4 { + regulator-name = "vdd_ddr_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name = "vdd_phyio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name = "vdd1_lpddr4_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name = "vda_dll_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name = "vdd_wk_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name = "vda_pll_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + lp876441: pmic@4c { + compatible = "ti,lp8764-q1"; + reg = <0x4c>; + system-power-controller; + interrupt-parent = <&wkup_gpio0>; + interrupts = <84 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + buck1-supply = <&vsys_3v3>; + buck2-supply = <&vsys_3v3>; + buck3-supply = <&vsys_3v3>; + buck4-supply = <&vsys_3v3>; + + regulators: regulators { + buckb1: buck1 { + regulator-name = "vdd_cpu_avs"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + }; + + buckb2: buck2 { + regulator-name = "vdd_ram_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb3: buck3 { + regulator-name = "vdd_core_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb4: buck4 { + regulator-name = "vdd_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; }; }; + +&main_mcan0 { + status = "okay"; + pinctrl-0 = <&main_mcan0_pins_default>; + pinctrl-names = "default"; + phys = <&transceiver0>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + mcu_thermal: mcu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup_crit: wkup-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + mpu_thermal: mpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + mpu_crit: mpu-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + + mpu_alert0: mpu_alert { + temperature = <75000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + }; + + cpu_cooling_maps: cooling-maps { + map0 { + trip = <&mpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + main_thermal: main-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + c7x_crit: c7x-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -7,9 +7,10 @@ #include #include -#include #include +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 J7200 SoC"; compatible = "ti,j7200"; @@ -64,6 +65,10 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&L2_0>; + clocks = <&k3_clks 202 2>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ }; cpu1: cpu@1 { @@ -78,12 +83,37 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&L2_0>; + clocks = <&k3_clks 203 0>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp4-2000000000 { + opp-hz = /bits/ 64 <2000000000>; + }; + + opp3-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + }; + + opp2-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + }; + + opp1-750000000 { + opp-hz = /bits/ 64 <750000000>; }; }; L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -168,6 +198,8 @@ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */ }; }; + + #include "k3-j7200-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-dsi-rpi-7inch-panel.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-dsi-rpi-7inch-panel.dtso @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for RPi 7inch touchscreen panel interfaced with DSI on + * J721E based BeagleBone AI-64 (BBAI-64) platform. + * + * BBAI-64: https://www.beagleboard.org/boards/beaglebone-ai-64 + * RPi DSI Panel: https://www.raspberrypi.com/products/raspberry-pi-touch-display/ + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + bridge_reg: bridge-regulator { + compatible = "regulator-fixed"; + regulator-name = "bridge-reg"; + gpio = <&display_reg 0 0>; + vin-supply = <&display_reg>; + enable-active-high; + }; + + panel0 { + compatible = "raspberrypi,7inch-dsi", "simple-panel"; + backlight = <&display_reg>; + power-supply = <&display_reg>; + port { + panel_in: endpoint { + remote-endpoint = <&panel_bridge_out>; + }; + }; + }; +}; + +&main_pmx0 { + dsi_main_i2c4_pins: dsi-main-i2c4-pins { + pinctrl-single,pins = < + J721E_IOPAD(0xa8, PIN_INPUT_PULLUP, 2) /* (AD19) PRG1_MDIO0_MDIO.I2C4_SCL */ + J721E_IOPAD(0xac, PIN_INPUT_PULLUP, 2) /* (AD18) PRG1_MDIO0_MDC.I2C4_SDA */ + >; + }; +}; + +&main_i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi_main_i2c4_pins>; + #address-cells = <1>; + #size-cells = <0>; + + display_reg: regulator@45 { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + }; + + touch-controller@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + + touchscreen-size-x = < 800 >; + touchscreen-size-y = < 480 >; + + vcc-supply = <&display_reg>; + reset-gpio = <&display_reg 1 1>; + + touchscreen-inverted-x; + touchscreen-inverted-y; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&dphy2 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_out: endpoint { + remote-endpoint = <&panel_bridge_in>; + }; + }; + + port@1 { + reg = <1>; + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; + }; + + bridge@0 { + compatible = "toshiba,tc358762"; + reg = <0>; + vddc-supply = <&bridge_reg>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + panel_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -0,0 +1,1025 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * https://beagleboard.org/ai-64 + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation + * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation + */ + +/dts-v1/; + +#include "k3-j721e.dtsi" +#include +#include +#include +#include +#include + +/ { + compatible = "beagle,j721e-beagleboneai64", "ti,j721e"; + model = "BeagleBoard.org BeagleBone AI-64"; + + aliases { + serial2 = &main_uart0; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + i2c0 = &wkup_i2c0; + i2c1 = &main_i2c6; + i2c2 = &main_i2c2; + i2c3 = &main_i2c4; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + /* 4G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + c66_1_dma_memory_region: c66-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c66_0_memory_region: c66-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c66_0_dma_memory_region: c66-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c66_1_memory_region: c66-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@aa000000 { + reg = <0x00 0xaa000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&sw_pwr_pins_default>; + + button-1 { + label = "BOOT"; + linux,code = ; + gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>; + }; + + button-2 { + label = "POWER"; + linux,code = ; + gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_default>; + + led-0 { + gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_DISK_ACTIVITY; + linux,default-trigger = "mmc0"; + }; + + led-2 { + gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_CPU; + linux,default-trigger = "cpu"; + }; + + led-3 { + gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_DISK_ACTIVITY; + linux,default-trigger = "mmc1"; + }; + + led-4 { + gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_WLAN; + default-state = "off"; + }; + }; + + evm_12v0: regulator-0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: regulator-1 { + /* Output of LMS140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_5v0: regulator-2 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pwr_en_pins_default>; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vsys_3v3>; + gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv_alt: regulator-4 { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; + regulator-name = "tlv71033"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + dp_pwr_3v3: regulator-5 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_3v3_en_pins_default>; + regulator-name = "dp-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */ + enable-active-high; + }; + + dp0: connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp_pwr_3v3>; + + port { + dp_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; +}; + +&main_pmx0 { + led_pins_default: led-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */ + J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */ + J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ + J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */ + J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ + J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ + J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ + J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ + J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ + J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ + J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ + J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ + >; + }; + + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ + J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ + >; + }; + + sd_pwr_en_pins_default: sd-pwr-en-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ + >; + }; + + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ + >; + }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */ + >; + }; + + main_usbss1_pins_default: main-usbss1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */ + >; + }; + + dp0_3v3_en_pins_default:dp0-3v3-en-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */ + >; + }; + + dp0_pins_default: dp0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ + J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ + J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ + >; + }; + + main_i2c2_pins_default: main-i2c2-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */ + J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */ + J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */ + J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */ + >; + }; + + main_i2c3_pins_default: main-i2c3-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ + J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ + >; + }; + + main_i2c4_pins_default: main-i2c4-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */ + J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */ + J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */ + J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */ + >; + }; + + main_i2c5_pins_default: main-i2c5-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ + J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ + >; + }; + + main_i2c6_pins_default: main-i2c6-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ + J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ + J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */ + J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */ + >; + }; + + csi0_gpio_pins_default: csi0-gpio-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ + J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ + >; + }; + + csi1_gpio_pins_default: csi1-gpio-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ + J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ + >; + }; + + pcie1_rst_pins_default: pcie1-rst-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */ + >; + }; +}; + +&wkup_pmx0 { + eeprom_wp_pins_default: eeprom-wp-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */ + >; + }; + + mcu_adc0_pins_default: mcu-adc0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */ + J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */ + J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */ + J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */ + J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */ + J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */ + J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */ + >; + }; + + mcu_adc1_pins_default: mcu-adc1-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */ + >; + }; + + mikro_bus_pins_default: mikro-bus-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */ + J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */ + J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */ + J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */ + J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */ + + J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */ + J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */ + J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */ + J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */ + + J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */ + J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */ + + J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */ + J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */ + J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */ + J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */ + >; + }; + + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ + J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio1-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ + >; + }; + + sw_pwr_pins_default: sw-pwr-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */ + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ + J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ + >; + }; + + mcu_usbss1_pins_default: mcu-usbss1-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */ + >; + }; +}; + +&wkup_uart0 { + /* Wakeup UART is used by TIFS firmware. */ + status = "reserved"; +}; + +&main_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + /* Shared with ATF on this platform */ + power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; +}; + +&main_sdhci0 { + /* eMMC */ + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&main_sdhci1 { + /* SD Card */ + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv_alt>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&main_sdhci2 { + /* Unused */ + status = "disabled"; +}; + +&ospi0 { + /* Unused */ + status = "disabled"; +}; + +&ospi1 { + /* Unused */ + status = "disabled"; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c2 { + /* BBB Header: P9.19 and P9.20 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <100000>; +}; + +&main_i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c3_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c4 { + /* BBB Header: P9.24 and P9.26 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <100000>; +}; + +&main_i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c6 { + /* BBB Header: P9.17 and P9.18 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c6_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&eeprom_wp_pins_default>; + }; +}; + +&main_gpio2 { + /* Unused */ + status = "disabled"; +}; + +&main_gpio3 { + /* Unused */ + status = "disabled"; +}; + +&main_gpio4 { + /* Unused */ + status = "disabled"; +}; + +&main_gpio5 { + /* Unused */ + status = "disabled"; +}; + +&main_gpio6 { + /* Unused */ + status = "disabled"; +}; + +&main_gpio7 { + /* Unused */ + status = "disabled"; +}; + +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>, + <&mikro_bus_pins_default>; +}; + +&wkup_gpio1 { + /* Unused */ + status = "disabled"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>; +}; + +&usb_serdes_mux { + idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , + , ; +}; + +&serdes_wiz3 { + typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>; + typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ +}; + +&serdes3 { + serdes3_usb_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; + }; +}; + +&serdes4 { + torrent_phy_dp: phy@0 { + reg = <0>; + resets = <&serdes_wiz4 1>; + cdns,phy-type = ; + cdns,num-lanes = <4>; + cdns,max-bit-rate = <5400>; + #phy-cells = <0>; + }; +}; + +&mhdp { + phys = <&torrent_phy_dp>; + phy-names = "dpphy"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; +}; + +&usbss0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usbss0_pins_default>; + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "peripheral"; + maximum-speed = "super-speed"; + phys = <&serdes3_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&serdes2 { + serdes2_usb_link: phy@1 { + reg = <1>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz2 2>; + }; +}; + +&usbss1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>; + ti,vbus-divider; +}; + +&usb1 { + dr_mode = "host"; + maximum-speed = "super-speed"; + phys = <&serdes2_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&tscadc0 { + /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */ + adc { + ti,adc-channels = <0 1 2 3 4 5 6>; + }; +}; + +&tscadc1 { + /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */ + adc { + ti,adc-channels = <0>; + }; +}; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default>; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mdio_pins_default>; + + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +}; + +&dss { + /* + * These clock assignments are chosen to enable the following outputs: + * + * VP0 - DisplayPort SST + * VP1 - DPI0 + * VP2 - DSI + * VP3 - DPI1 + */ + + assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ + <&k3_clks 152 4>, /* VP 2 pixel clock */ + <&k3_clks 152 9>, /* VP 3 pixel clock */ + <&k3_clks 152 13>; /* VP 4 pixel clock */ + assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ + <&k3_clks 152 6>, /* PLL19_HSDIV0 */ + <&k3_clks 152 11>, /* PLL18_HSDIV0 */ + <&k3_clks 152 18>; /* PLL23_HSDIV0 */ +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; +}; + +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp_connector_in>; + }; + }; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes1 { + serdes1_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; + }; +}; + +&pcie1_rc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_rst_pins_default>; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + max-link-speed = <3>; + reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; +}; + +&ufs_wrapper { + status = "disabled"; +}; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + interrupts = <424>; + + mbox_c66_0: mbox-c66-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c66_1: mbox-c66-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&c66_0 { + mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; + memory-region = <&c66_0_dma_memory_region>, + <&c66_0_memory_region>; +}; + +&c66_1 { + mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; + memory-region = <&c66_1_dma_memory_region>, + <&c66_1_memory_region>; +}; + +&c71_0 { + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board-infotainment.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board-infotainment.dtso @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Infotainment Expansion Board for j721e-evm + * User Guide: + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&main_i2c1>; + digital; + /* P12 - HDMI_HPD */ + hpd-gpios = <&exp6 10 GPIO_ACTIVE_HIGH>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + dvi-bridge { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,tfp410"; + /* P10 - HDMI_PDn */ + powerdown-gpios = <&exp6 8 GPIO_ACTIVE_LOW>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_out0>; + pclk-sample = <1>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = + <&hdmi_connector_in>; + }; + }; + }; +}; + +&main_pmx0 { + main_i2c1_exp6_pins_default: main-i2c1-exp6-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x264, PIN_INPUT, 7) /* (T29) MMC2_DAT2.GPIO1_24 */ + >; + }; + + dss_vout0_pins_default: dss-vout0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ + J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ + J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */ + J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */ + J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */ + J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */ + J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */ + J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */ + J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */ + J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */ + J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */ + J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */ + J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */ + J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */ + J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */ + J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */ + J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */ + J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */ + J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */ + J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */ + J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */ + J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */ + J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */ + J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */ + J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */ + J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */ + J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */ + J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ + >; + }; +}; + +&exp1 { + p14-hog { + /* P14 - VINOUT_MUX_SEL0 */ + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "VINOUT_MUX_SEL0"; + }; + + p15-hog { + /* P15 - VINOUT_MUX_SEL1 */ + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "VINOUT_MUX_SEL1"; + }; +}; + +&main_i2c1 { + /* i2c1 is used for DVI DDC, so we need to use 100kHz */ + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + + exp6: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_exp6_pins_default>; + interrupt-parent = <&main_gpio1>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + p11-hog { + /* P11 - HDMI_DDC_OE */ + gpio-hog; + gpios = <9 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "HDMI_DDC_OE"; + }; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&dss_vout0_pins_default>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dpi_out0: endpoint { + remote-endpoint = <&tfp410_in>; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -96,7 +96,7 @@ <3300000 0x1>; }; - sound0: sound@0 { + sound0: sound-0 { compatible = "ti,j721e-cpb-audio"; model = "j721e-cpb"; @@ -173,6 +173,15 @@ }; &main_pmx0 { + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */ + J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ + J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ + J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ + >; + }; + sw10_button_pins_default: sw10-button-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ @@ -363,45 +372,64 @@ J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ >; }; + + wkup_gpio_pins_default: wkup-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; }; &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; -&main_uart0 { - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; -}; - -&main_uart3 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart5 { - /* UART not brought out */ - status = "disabled"; +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; -&main_uart6 { - /* UART not brought out */ - status = "disabled"; +&main_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + /* Shared with ATF on this platform */ + power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; -&main_uart7 { - /* UART not brought out */ - status = "disabled"; +&main_uart1 { + status = "okay"; + /* Default pinmux */ }; -&main_uart8 { - /* UART not brought out */ - status = "disabled"; +&main_uart2 { + status = "okay"; + /* Default pinmux */ }; -&main_uart9 { - /* UART not brought out */ - status = "disabled"; +&main_uart4 { + status = "okay"; + /* Default pinmux */ }; &main_gpio2 { @@ -428,6 +456,11 @@ status = "disabled"; }; +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; +}; + &wkup_gpio1 { status = "disabled"; }; @@ -521,6 +554,52 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qspi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "qspi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "qspi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "qspi.env"; + reg = <0x680000 0x20000>; + }; + + partition@6a0000 { + label = "qspi.env.backup"; + reg = <0x6a0000 0x20000>; + }; + + partition@6c0000 { + label = "qspi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "qspi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fe0000 { + label = "qspi.phypattern"; + reg = <0x3fe0000 0x20000>; + }; + }; }; }; @@ -537,6 +616,7 @@ }; &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -573,6 +653,7 @@ }; &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; @@ -598,6 +679,7 @@ }; &main_i2c3 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c3_pins_default>; clock-frequency = <400000>; @@ -636,6 +718,7 @@ }; &main_i2c6 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c6_pins_default>; clock-frequency = <400000>; @@ -651,6 +734,11 @@ &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + + cpts@3d000 { + /* Map HW4_TS_PUSH to GENF1 */ + ti,pps = <3 1>; + }; }; &davinci_mdio { @@ -713,47 +801,8 @@ }; }; -&mcasp0 { - status = "disabled"; -}; - -&mcasp1 { - status = "disabled"; -}; - -&mcasp2 { - status = "disabled"; -}; - -&mcasp3 { - status = "disabled"; -}; - -&mcasp4 { - status = "disabled"; -}; - -&mcasp5 { - status = "disabled"; -}; - -&mcasp6 { - status = "disabled"; -}; - -&mcasp7 { - status = "disabled"; -}; - -&mcasp8 { - status = "disabled"; -}; - -&mcasp9 { - status = "disabled"; -}; - &mcasp10 { + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; @@ -771,10 +820,6 @@ rx-num-evt = <0>; }; -&mcasp11 { - status = "disabled"; -}; - &cmn_refclk1 { clock-frequency = <100000000>; }; @@ -854,7 +899,7 @@ resets = <&serdes_wiz4 1>; cdns,phy-type = ; cdns,num-lanes = <4>; - cdns,max-bit-rate = <5400>; + cdns,max-bit-rate = <2700>; #phy-cells = <0>; }; }; @@ -867,6 +912,7 @@ }; &pcie0_rc { + status = "okay"; reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; @@ -874,6 +920,7 @@ }; &pcie1_rc { + status = "okay"; reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; phys = <&serdes1_pcie_link>; phy-names = "pcie-phy"; @@ -881,117 +928,71 @@ }; &pcie2_rc { + status = "okay"; reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; phys = <&serdes2_pcie_link>; phy-names = "pcie-phy"; num-lanes = <2>; }; -&pcie0_ep { - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; - status = "disabled"; -}; - -&pcie1_ep { - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; -}; - -&pcie2_ep { - phys = <&serdes2_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; -}; - -&pcie3_rc { - status = "disabled"; -}; - -&pcie3_ep { - status = "disabled"; -}; - -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - &mcu_mcan0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_mcan0_pins_default>; phys = <&transceiver1>; }; &mcu_mcan1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_mcan1_pins_default>; phys = <&transceiver2>; }; &main_mcan0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan0_pins_default>; phys = <&transceiver3>; }; -&main_mcan1 { - status = "disabled"; -}; - &main_mcan2 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan2_pins_default>; phys = <&transceiver4>; }; -&main_mcan3 { - status = "disabled"; -}; - -&main_mcan4 { - status = "disabled"; -}; - -&main_mcan5 { - status = "disabled"; +&ti_csi2rx0 { + status = "okay"; + /* MIPI-CSI Connector */ }; -&main_mcan6 { - status = "disabled"; -}; - -&main_mcan7 { - status = "disabled"; +&ti_csi2rx1 { + status = "okay"; + /* MIPI-CSI Connector */ }; -&main_mcan8 { - status = "disabled"; -}; - -&main_mcan9 { - status = "disabled"; +&dphy0 { + status = "okay"; }; -&main_mcan10 { - status = "disabled"; +&dphy1 { + status = "okay"; }; -&main_mcan11 { - status = "disabled"; -}; +#define K3_TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val) -&main_mcan12 { - status = "disabled"; -}; +×ync_router { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_cpts>; -&main_mcan13 { - status = "disabled"; + /* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */ + mcu_cpsw_cpts: mcu-cpsw-cpts { + pinctrl-single,pins = < + /* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */ + K3_TS_OFFSET(25, 17) + >; + }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-evm-csi2-ov5640.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-evm-csi2-ov5640.dtso @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LI OV5640 MIPI Camera module on MIPI CSI connector. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&main_i2c6 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + powerdown-gpios = <&exp5 0 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-evm-fusion.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-evm-fusion.dtso @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Fusion (FPD-Link III) board on J721E EVM + * https://svtronics.com/portfolio/evm577pfusion-v1-0-fusion/ + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + + +&main_i2c6 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + deser@3d { + compatible = "ti,ds90ub960-q1"; + reg = <0x3d>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + ds90ub960_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + ds90ub960_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + deser@36 { + compatible = "ti,ds90ub960-q1"; + reg = <0x36>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + ds90ub960_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + ds90ub960_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; +}; + +&csi1_port0 { + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with + * J721E board. + * + * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; + ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; + ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; + }; +}; + +&cpsw0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins_default + &rgmii2_pins_default + &rgmii3_pins_default + &rgmii4_pins_default>; +}; + +&cpsw0_port1 { + status = "okay"; + phy-handle = <&cpsw9g_phy12>; + phy-mode = "rgmii-rxid"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 1>; +}; + +&cpsw0_port2 { + status = "okay"; + phy-handle = <&cpsw9g_phy15>; + phy-mode = "rgmii-rxid"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 2>; +}; + +&cpsw0_port3 { + status = "okay"; + phy-handle = <&cpsw9g_phy0>; + phy-mode = "rgmii-rxid"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 3>; +}; + +&cpsw0_port4 { + status = "okay"; + phy-handle = <&cpsw9g_phy3>; + phy-mode = "rgmii-rxid"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 4>; +}; + +&cpsw9g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default>; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + + cpsw9g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; + cpsw9g_phy3: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; + cpsw9g_phy12: ethernet-phy@12 { + reg = <12>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; + cpsw9g_phy15: ethernet-phy@15 { + reg = <15>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&exp1 { + p15-hog { + /* P15 - EXP_MUX2 */ + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_MUX2"; + }; + + p16-hog { + /* P16 - EXP_MUX3 */ + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_MUX3"; + }; +}; + +&main_pmx0 { + mdio0_pins_default: mdio0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */ + J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */ + >; + }; + + rgmii1_pins_default: rgmii1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x4, PIN_INPUT, 4) /* (AC23) PRG1_PRU0_GPO0.RGMII1_RD0 */ + J721E_IOPAD(0x8, PIN_INPUT, 4) /* (AG22) PRG1_PRU0_GPO1.RGMII1_RD1 */ + J721E_IOPAD(0xc, PIN_INPUT, 4) /* (AF22) PRG1_PRU0_GPO2.RGMII1_RD2 */ + J721E_IOPAD(0x10, PIN_INPUT, 4) /* (AJ23) PRG1_PRU0_GPO3.RGMII1_RD3 */ + J721E_IOPAD(0x1c, PIN_INPUT, 4) /* (AD22) PRG1_PRU0_GPO6.RGMII1_RXC */ + J721E_IOPAD(0x14, PIN_INPUT, 4) /* (AH23) PRG1_PRU0_GPO4.RGMII1_RX_CTL */ + J721E_IOPAD(0x30, PIN_OUTPUT, 4) /* (AF24) PRG1_PRU0_GPO11.RGMII1_TD0 */ + J721E_IOPAD(0x34, PIN_OUTPUT, 4) /* (AJ24) PRG1_PRU0_GPO12.RGMII1_TD1 */ + J721E_IOPAD(0x38, PIN_OUTPUT, 4) /* (AG24) PRG1_PRU0_GPO13.RGMII1_TD2 */ + J721E_IOPAD(0x3c, PIN_OUTPUT, 4) /* (AD24) PRG1_PRU0_GPO14.RGMII1_TD3 */ + J721E_IOPAD(0x44, PIN_OUTPUT, 4) /* (AE24) PRG1_PRU0_GPO16.RGMII1_TXC */ + J721E_IOPAD(0x40, PIN_OUTPUT, 4) /* (AC24) PRG1_PRU0_GPO15.RGMII1_TX_CTL */ + >; + }; + + rgmii2_pins_default: rgmii2-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x58, PIN_INPUT, 4) /* (AE22) PRG1_PRU1_GPO0.RGMII2_RD0 */ + J721E_IOPAD(0x5c, PIN_INPUT, 4) /* (AG23) PRG1_PRU1_GPO1.RGMII2_RD1 */ + J721E_IOPAD(0x60, PIN_INPUT, 4) /* (AF23) PRG1_PRU1_GPO2.RGMII2_RD2 */ + J721E_IOPAD(0x64, PIN_INPUT, 4) /* (AD23) PRG1_PRU1_GPO3.RGMII2_RD3 */ + J721E_IOPAD(0x70, PIN_INPUT, 4) /* (AE23) PRG1_PRU1_GPO6.RGMII2_RXC */ + J721E_IOPAD(0x68, PIN_INPUT, 4) /* (AH24) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + J721E_IOPAD(0x84, PIN_OUTPUT, 4) /* (AJ25) PRG1_PRU1_GPO11.RGMII2_TD0 */ + J721E_IOPAD(0x88, PIN_OUTPUT, 4) /* (AH25) PRG1_PRU1_GPO12.RGMII2_TD1 */ + J721E_IOPAD(0x8c, PIN_OUTPUT, 4) /* (AG25) PRG1_PRU1_GPO13.RGMII2_TD2 */ + J721E_IOPAD(0x90, PIN_OUTPUT, 4) /* (AH26) PRG1_PRU1_GPO14.RGMII2_TD3 */ + J721E_IOPAD(0x98, PIN_OUTPUT, 4) /* (AJ26) PRG1_PRU1_GPO16.RGMII2_TXC */ + J721E_IOPAD(0x94, PIN_OUTPUT, 4) /* (AJ27) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; + + rgmii3_pins_default: rgmii3-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0xb0, PIN_INPUT, 4) /* (AF28) PRG0_PRU0_GPO0.RGMII3_RD0 */ + J721E_IOPAD(0xb4, PIN_INPUT, 4) /* (AE28) PRG0_PRU0_GPO1.RGMII3_RD1 */ + J721E_IOPAD(0xb8, PIN_INPUT, 4) /* (AE27) PRG0_PRU0_GPO2.RGMII3_RD2 */ + J721E_IOPAD(0xbc, PIN_INPUT, 4) /* (AD26) PRG0_PRU0_GPO3.RGMII3_RD3 */ + J721E_IOPAD(0xc8, PIN_INPUT, 4) /* (AE26) PRG0_PRU0_GPO6.RGMII3_RXC */ + J721E_IOPAD(0xc0, PIN_INPUT, 4) /* (AD25) PRG0_PRU0_GPO4.RGMII3_RX_CTL */ + J721E_IOPAD(0xdc, PIN_OUTPUT, 4) /* (AJ28) PRG0_PRU0_GPO11.RGMII3_TD0 */ + J721E_IOPAD(0xe0, PIN_OUTPUT, 4) /* (AH27) PRG0_PRU0_GPO12.RGMII3_TD1 */ + J721E_IOPAD(0xe4, PIN_OUTPUT, 4) /* (AH29) PRG0_PRU0_GPO13.RGMII3_TD2 */ + J721E_IOPAD(0xe8, PIN_OUTPUT, 4) /* (AG28) PRG0_PRU0_GPO14.RGMII3_TD3 */ + J721E_IOPAD(0xf0, PIN_OUTPUT, 4) /* (AH28) PRG0_PRU0_GPO16.RGMII3_TXC */ + J721E_IOPAD(0xec, PIN_OUTPUT, 4) /* (AG27) PRG0_PRU0_GPO15.RGMII3_TX_CTL */ + >; + }; + + rgmii4_pins_default: rgmii4-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x100, PIN_INPUT, 4) /* (AE29) PRG0_PRU1_GPO0.RGMII4_RD0 */ + J721E_IOPAD(0x104, PIN_INPUT, 4) /* (AD28) PRG0_PRU1_GPO1.RGMII4_RD1 */ + J721E_IOPAD(0x108, PIN_INPUT, 4) /* (AD27) PRG0_PRU1_GPO2.RGMII4_RD2 */ + J721E_IOPAD(0x10c, PIN_INPUT, 4) /* (AC25) PRG0_PRU1_GPO3.RGMII4_RD3 */ + J721E_IOPAD(0x118, PIN_INPUT, 4) /* (AC26) PRG0_PRU1_GPO6.RGMII4_RXC */ + J721E_IOPAD(0x110, PIN_INPUT, 4) /* (AD29) PRG0_PRU1_GPO4.RGMII4_RX_CTL */ + J721E_IOPAD(0x12c, PIN_OUTPUT, 4) /* (AG26) PRG0_PRU1_GPO11.RGMII4_TD0 */ + J721E_IOPAD(0x130, PIN_OUTPUT, 4) /* (AF27) PRG0_PRU1_GPO12.RGMII4_TD1 */ + J721E_IOPAD(0x134, PIN_OUTPUT, 4) /* (AF26) PRG0_PRU1_GPO13.RGMII4_TD2 */ + J721E_IOPAD(0x138, PIN_OUTPUT, 4) /* (AE25) PRG0_PRU1_GPO14.RGMII4_TD3 */ + J721E_IOPAD(0x140, PIN_OUTPUT, 4) /* (AG29) PRG0_PRU1_GPO16.RGMII4_TXC */ + J721E_IOPAD(0x13c, PIN_OUTPUT, 4) /* (AF29) PRG0_PRU1_GPO15.RGMII4_TX_CTL */ + >; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the + * J7 common processor board. + * + * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie0_rc { + status = "disabled"; +}; + +&cbass_main { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + + pcie0_ep: pcie-ep@2900000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; + max-link-speed = <3>; + num-lanes = <1>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with + * J721E board. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; + ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; + ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; + }; +}; + +&cpsw0 { + status = "okay"; +}; + +&cpsw0_port1 { + status = "okay"; + phy-handle = <&cpsw9g_phy0>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 1>; +}; + +&cpsw0_port2 { + status = "okay"; + phy-handle = <&cpsw9g_phy1>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 2>; +}; + +&cpsw0_port3 { + status = "okay"; + phy-handle = <&cpsw9g_phy2>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 3>; +}; + +&cpsw0_port4 { + status = "okay"; + phy-handle = <&cpsw9g_phy3>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 4>; +}; + +&cpsw9g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default>; + reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <120000>; + #address-cells = <1>; + #size-cells = <0>; + + cpsw9g_phy0: ethernet-phy@17 { + reg = <17>; + }; + cpsw9g_phy1: ethernet-phy@16 { + reg = <16>; + }; + cpsw9g_phy2: ethernet-phy@18 { + reg = <18>; + }; + cpsw9g_phy3: ethernet-phy@19 { + reg = <19>; + }; +}; + +&exp2 { + qsgmii-line-hog { + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "qsgmii-pwrdn-line"; + }; +}; + +&main_pmx0 { + mdio0_pins_default: mdio0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */ + J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */ + >; + }; +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , + , ; +}; + +&serdes_wiz0 { + status = "okay"; +}; + +&serdes0 { + status = "okay"; + + assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>; + assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>; + #address-cells = <1>; + #size-cells = <0>; + + serdes0_qsgmii_link: phy@1 { + reg = <1>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 2>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-evm-virt-mac-client.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-evm-virt-mac-client.dtso @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling CPSW Virt MAC Client driver in linux to interface with EthFw via the + * Linux MAC Only port as well as the Switch Ports of the CPSW9G CPSW instance. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + cpsw9g_virt_mac: main-r5fss-cpsw9g-virt-mac0 { + compatible = "ti,j721e-cpsw-virt-mac"; + dma-coherent; + ti,psil-base = <0x4a00>; + ti,remote-name = "mpu_1_0_ethswitch-device-0"; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + virt-emac-port { + ti,label = "virt-port"; + /* local-mac-address = [0 0 0 0 0 0]; */ + }; + }; + + cpsw9g_virt_maconly: main-r5fss-cpsw9g-virt-mac1 { + compatible = "ti,j721e-cpsw-virt-mac"; + dma-coherent; + ti,psil-base = <0x4a00>; + ti,remote-name = "mpu_1_0_ethmac-device-1"; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + virt-emac-port { + ti,label = "virt-port"; + /* local-mac-address = [0 0 0 0 0 0]; */ + }; + }; +}; + +/* uart2 is assigned to cpsw9g eth-switch fw running on remote CPU core */ +&main_uart2 { + status = "reserved"; +}; + +/* Reserve shared memory for inter-core network communication */ +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + + main_r5fss0_core0_shared_memory_queue_region:r5f-virtual-eth-queues@ac000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xac000000 0x00 0x200000>; + no-map; + }; + + main_r5fss0_core0_shared_memory_bufpool_region:r5f-virtual-eth-buffers@ac200000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xac200000 0x00 0x1e00000>; + no-map; + }; +}; + +&main_r5fss0_core0 { + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>, + <&main_r5fss0_core0_shared_memory_queue_region>, + <&main_r5fss0_core0_shared_memory_bufpool_region>; +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , + , ; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -61,12 +61,85 @@ , ; }; + cpsw0_phy_gmii_sel: phy@4044 { + compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; + ti,qsgmii-main-ports = <2>, <2>; + reg = <0x4044 0x20>; + #phy-cells = <1>; + }; + usb_serdes_mux: mux-controller@4000 { compatible = "mmio-mux"; #mux-control-cells = <1>; mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ - }; + }; + + ehrpwm_tbclk: clock-controller@4140 { + compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + reg = <0x4140 0x18>; + #clock-cells = <1>; + }; + }; + + main_ehrpwm0: pwm@3000000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3000000 0x00 0x100>; + power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm1: pwm@3010000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3010000 0x00 0x100>; + power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm2: pwm@3020000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3020000 0x00 0x100>; + power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm3: pwm@3030000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3030000 0x00 0x100>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm4: pwm@3040000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3040000 0x00 0x100>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm5: pwm@3050000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3050000 0x00 0x100>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; }; gic500: interrupt-controller@1800000 { @@ -176,6 +249,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster1: mailbox@31f81000 { @@ -185,6 +259,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster2: mailbox@31f82000 { @@ -194,6 +269,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster3: mailbox@31f83000 { @@ -203,6 +279,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster4: mailbox@31f84000 { @@ -212,6 +289,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster5: mailbox@31f85000 { @@ -221,6 +299,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster6: mailbox@31f86000 { @@ -230,6 +309,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster7: mailbox@31f87000 { @@ -239,6 +319,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster8: mailbox@31f88000 { @@ -248,6 +329,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster9: mailbox@31f89000 { @@ -257,6 +339,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster10: mailbox@31f8a000 { @@ -266,6 +349,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster11: mailbox@31f8b000 { @@ -275,6 +359,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; main_ringacc: ringacc@3c000000 { @@ -326,6 +411,115 @@ }; }; + cpsw0: ethernet@c000000 { + compatible = "ti,j721e-cpswxg-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0xc000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; + clocks = <&k3_clks 19 89>; + clock-names = "fck"; + power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + cpsw0_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + status = "disabled"; + }; + + cpsw0_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + status = "disabled"; + }; + + cpsw0_port3: port@3 { + reg = <3>; + ti,mac-only; + label = "port3"; + status = "disabled"; + }; + + cpsw0_port4: port@4 { + reg = <4>; + ti,mac-only; + label = "port4"; + status = "disabled"; + }; + + cpsw0_port5: port@5 { + reg = <5>; + ti,mac-only; + label = "port5"; + status = "disabled"; + }; + + cpsw0_port6: port@6 { + reg = <6>; + ti,mac-only; + label = "port6"; + status = "disabled"; + }; + + cpsw0_port7: port@7 { + reg = <7>; + ti,mac-only; + label = "port7"; + status = "disabled"; + }; + + cpsw0_port8: port@8 { + reg = <8>; + ti,mac-only; + label = "port8"; + status = "disabled"; + }; + }; + + cpsw9g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x0 0xf00 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 19 89>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x0 0x3d000 0x0 0x400>; + clocks = <&k3_clks 19 16>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + main_crypto: crypto@4e00000 { compatible = "ti,j721e-sa2ul"; reg = <0x0 0x4e00000 0x0 0x1200>; @@ -342,7 +536,6 @@ compatible = "inside-secure,safexcel-eip76"; reg = <0x0 0x4e10000 0x0 0x7d>; interrupts = ; - clocks = <&k3_clks 264 2>; }; }; @@ -621,26 +814,20 @@ ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */ + <0 0 0 2 &pcie0_intc 0>, /* INT B */ + <0 0 0 3 &pcie0_intc 0>, /* INT C */ + <0 0 0 4 &pcie0_intc 0>; /* INT D */ + status = "disabled"; - pcie0_ep: pcie-ep@2900000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02900000 0x00 0x1000>, - <0x00 0x02907000 0x00 0x400>, - <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 239 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; }; pcie1_rc: pcie@2910000 { @@ -669,26 +856,20 @@ ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + status = "disabled"; - pcie1_ep: pcie-ep@2910000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = ; + }; }; pcie2_rc: pcie@2920000 { @@ -717,26 +898,20 @@ ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, /* INT A */ + <0 0 0 2 &pcie2_intc 0>, /* INT B */ + <0 0 0 3 &pcie2_intc 0>, /* INT C */ + <0 0 0 4 &pcie2_intc 0>; /* INT D */ + status = "disabled"; - pcie2_ep: pcie-ep@2920000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02920000 0x00 0x1000>, - <0x00 0x02927000 0x00 0x400>, - <0x00 0x0e000000 0x00 0x00800000>, - <0x44 0x00000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 241 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = ; + }; }; pcie3_rc: pcie@2930000 { @@ -765,28 +940,20 @@ ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, /* INT A */ + <0 0 0 2 &pcie3_intc 0>, /* INT B */ + <0 0 0 3 &pcie3_intc 0>, /* INT C */ + <0 0 0 4 &pcie3_intc 0>; /* INT D */ + status = "disabled"; - pcie3_ep: pcie-ep@2930000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02930000 0x00 0x1000>, - <0x00 0x02937000 0x00 0x400>, - <0x00 0x0e800000 0x00 0x00800000>, - <0x44 0x10000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 242 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - #address-cells = <2>; - #size-cells = <2>; + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = ; + }; }; serdes_wiz4: wiz@5050000 { @@ -839,6 +1006,7 @@ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -850,6 +1018,7 @@ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 278 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -861,6 +1030,7 @@ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 279 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart3: serial@2830000 { @@ -872,6 +1042,7 @@ power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 280 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart4: serial@2840000 { @@ -883,6 +1054,7 @@ power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 281 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart5: serial@2850000 { @@ -894,6 +1066,7 @@ power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 282 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart6: serial@2860000 { @@ -905,6 +1078,7 @@ power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 283 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart7: serial@2870000 { @@ -916,6 +1090,7 @@ power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 284 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart8: serial@2880000 { @@ -927,6 +1102,7 @@ power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 285 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart9: serial@2890000 { @@ -938,6 +1114,7 @@ power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 286 0>; clock-names = "fclk"; + status = "disabled"; }; main_gpio0: gpio@600000 { @@ -1084,8 +1261,8 @@ bus-width = <8>; mmc-hs200-1_8v; mmc-ddr-1_8v; - ti,otap-del-sel-legacy = <0xf>; - ti,otap-del-sel-mmc-hs = <0xf>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x6>; ti,otap-del-sel-hs400 = <0x0>; @@ -1106,11 +1283,12 @@ assigned-clocks = <&k3_clks 92 0>; assigned-clock-parents = <&k3_clks 92 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; @@ -1132,11 +1310,12 @@ assigned-clocks = <&k3_clks 93 0>; assigned-clock-parents = <&k3_clks 93 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; @@ -1217,6 +1396,7 @@ clock-names = "fck"; clocks = <&k3_clks 187 0>; power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; + status = "disabled"; }; main_i2c1: i2c@2010000 { @@ -1228,6 +1408,7 @@ clock-names = "fck"; clocks = <&k3_clks 188 0>; power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c2: i2c@2020000 { @@ -1239,6 +1420,7 @@ clock-names = "fck"; clocks = <&k3_clks 189 0>; power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c3: i2c@2030000 { @@ -1250,6 +1432,7 @@ clock-names = "fck"; clocks = <&k3_clks 190 0>; power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c4: i2c@2040000 { @@ -1261,6 +1444,7 @@ clock-names = "fck"; clocks = <&k3_clks 191 0>; power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c5: i2c@2050000 { @@ -1272,6 +1456,7 @@ clock-names = "fck"; clocks = <&k3_clks 192 0>; power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c6: i2c@2060000 { @@ -1283,6 +1468,24 @@ clock-names = "fck"; clocks = <&k3_clks 193 0>; power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + vxe384: video-encoder@4200000 { + compatible = "img,vxe384"; + reg = <0x00 0x04200000>, + <0x00 0x100000>; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + interrupts = ; + }; + + d5520: video-decoder@4300000 { + /* IMG D5520 driver configuration */ + compatible = "img,d5500-vxd"; + reg = <0x00 0x04300000>, + <0x00 0x100000>; + power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; + interrupts = ; }; ufs_wrapper: ufs-wrapper@4e80000 { @@ -1338,6 +1541,24 @@ }; }; + dsi0: dsi@48000000 { + compatible = "ti,j721e-dsi"; + reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>; + clocks = <&k3_clks 150 1>, <&k3_clks 150 5>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; + interrupt-parent = <&gic500>; + interrupts = ; + phys = <&dphy2>; + phy-names = "dphy"; + status = "disabled"; + + dsi0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = @@ -1406,6 +1627,7 @@ clocks = <&k3_clks 174 1>; clock-names = "fck"; power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp1: mcasp@2b10000 { @@ -1423,6 +1645,7 @@ clocks = <&k3_clks 175 1>; clock-names = "fck"; power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp2: mcasp@2b20000 { @@ -1440,6 +1663,7 @@ clocks = <&k3_clks 176 1>; clock-names = "fck"; power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp3: mcasp@2b30000 { @@ -1457,6 +1681,7 @@ clocks = <&k3_clks 177 1>; clock-names = "fck"; power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp4: mcasp@2b40000 { @@ -1474,6 +1699,7 @@ clocks = <&k3_clks 178 1>; clock-names = "fck"; power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp5: mcasp@2b50000 { @@ -1491,6 +1717,7 @@ clocks = <&k3_clks 179 1>; clock-names = "fck"; power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp6: mcasp@2b60000 { @@ -1508,6 +1735,7 @@ clocks = <&k3_clks 180 1>; clock-names = "fck"; power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp7: mcasp@2b70000 { @@ -1525,6 +1753,7 @@ clocks = <&k3_clks 181 1>; clock-names = "fck"; power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp8: mcasp@2b80000 { @@ -1542,6 +1771,7 @@ clocks = <&k3_clks 182 1>; clock-names = "fck"; power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp9: mcasp@2b90000 { @@ -1559,6 +1789,7 @@ clocks = <&k3_clks 183 1>; clock-names = "fck"; power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp10: mcasp@2ba0000 { @@ -1576,6 +1807,7 @@ clocks = <&k3_clks 184 1>; clock-names = "fck"; power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp11: mcasp@2bb0000 { @@ -1593,6 +1825,7 @@ clocks = <&k3_clks 185 1>; clock-names = "fck"; power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; watchdog0: watchdog@2200000 { @@ -1615,7 +1848,7 @@ main_r5fss0: r5fss@5c00000 { compatible = "ti,j721e-r5fss"; - ti,cluster-mode = <1>; + ti,cluster-mode = <0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x5c00000 0x00 0x5c00000 0x20000>, @@ -1655,7 +1888,7 @@ main_r5fss1: r5fss@5e00000 { compatible = "ti,j721e-r5fss"; - ti,cluster-mode = <1>; + ti,cluster-mode = <0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x5e00000 0x00 0x5e00000 0x20000>, @@ -1731,6 +1964,17 @@ firmware-name = "j7-c71_0-fw"; }; + timesync_router: pinctrl@a40000 { + compatible = "pinctrl-single"; + reg = <0x0 0xa40000 0x0 0x800>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000107ff>; + status = "disabled"; + }; + icssg0: icssg@b000000 { compatible = "ti,j721e-icssg"; reg = <0x00 0xb000000 0x00 0x80000>; @@ -1869,6 +2113,7 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -2010,9 +2255,18 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; + gpu: gpu@4e20000000 { + compatible = "ti,j721e-pvr", "img,pvr-ge8430"; + reg = <0x4e 0x20000000 0x00 0x80000>; + interrupts = ; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 125 0>; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, @@ -2025,6 +2279,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan1: can@2711000 { @@ -2039,6 +2294,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan2: can@2721000 { @@ -2053,6 +2309,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan3: can@2731000 { @@ -2067,6 +2324,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan4: can@2741000 { @@ -2081,6 +2339,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan5: can@2751000 { @@ -2095,6 +2354,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan6: can@2761000 { @@ -2109,6 +2369,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan7: can@2771000 { @@ -2123,6 +2384,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan8: can@2781000 { @@ -2137,6 +2399,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan9: can@2791000 { @@ -2151,6 +2414,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan10: can@27a1000 { @@ -2165,6 +2429,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan11: can@27b1000 { @@ -2179,6 +2444,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan12: can@27c1000 { @@ -2193,6 +2459,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan13: can@27d1000 { @@ -2207,5 +2474,241 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_spi0: spi@2100000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 266 1>; + status = "disabled"; + }; + + main_spi1: spi@2110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 267 1>; + status = "disabled"; + }; + + main_spi2: spi@2120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 268 1>; + status = "disabled"; + }; + + main_spi3: spi@2130000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02130000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 269 1>; + status = "disabled"; + }; + + main_spi4: spi@2140000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02140000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 270 1>; + status = "disabled"; + }; + + main_spi5: spi@2150000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02150000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 271 1>; + status = "disabled"; + }; + + main_spi6: spi@2160000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02160000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 272 1>; + status = "disabled"; + }; + + main_spi7: spi@2170000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02170000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 273 1>; + status = "disabled"; + }; + + ti_csi2rx0: ticsi2rx@4500000 { + status = "disabled"; + compatible = "ti,j721e-csi2rx"; + dmas = <&main_udmap 0x4940>, <&main_udmap 0x4941>, <&main_udmap 0x4942>, + <&main_udmap 0x4943>, <&main_udmap 0x4944>, <&main_udmap 0x4945>, + <&main_udmap 0x4946>, <&main_udmap 0x4947>, <&main_udmap 0x4948>, + <&main_udmap 0x4949>, <&main_udmap 0x494a>, <&main_udmap 0x494b>, + <&main_udmap 0x494c>, <&main_udmap 0x494d>, <&main_udmap 0x494e>, + <&main_udmap 0x494f>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15"; + reg = <0x0 0x4500000 0x0 0x1000>; + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "cdns,csi2rx"; + reg = <0x0 0x4504000 0x0 0x1000>; + clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + status = "disabled"; + compatible = "ti,j721e-csi2rx"; + dmas = <&main_udmap 0x4960>, <&main_udmap 0x4961>, <&main_udmap 0x4962>, + <&main_udmap 0x4963>, <&main_udmap 0x4964>, <&main_udmap 0x4965>, + <&main_udmap 0x4966>, <&main_udmap 0x4967>, <&main_udmap 0x4968>, + <&main_udmap 0x4969>, <&main_udmap 0x496a>, <&main_udmap 0x496b>, + <&main_udmap 0x496c>, <&main_udmap 0x496d>, <&main_udmap 0x496e>, + <&main_udmap 0x496f>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15"; + reg = <0x0 0x4510000 0x0 0x1000>; + power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "cdns,csi2rx"; + reg = <0x0 0x4514000 0x0 0x1000>; + clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, + <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + status = "disabled"; + compatible = "cdns,dphy-rx"; + reg = <0x0 0x4580000 0x0 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + }; + + dphy1: phy@4590000 { + status = "disabled"; + compatible = "cdns,dphy-rx"; + reg = <0x0 0x4590000 0x0 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + }; + + dphy2: phy@4480000 { + compatible = "ti,j721e-dphy"; + reg = <0x0 0x04480000 0x0 0x1000>; + clocks = <&k3_clks 296 1>, <&k3_clks 296 3>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 296 3>; + assigned-clock-parents = <&k3_clks 296 4>; + assigned-clock-rates = <19200000>; + status = "disabled"; }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -79,6 +79,7 @@ power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 287 0>; clock-names = "fclk"; + status = "disabled"; }; mcu_uart0: serial@40a00000 { @@ -90,6 +91,7 @@ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; + status = "disabled"; }; wkup_gpio_intr: interrupt-controller@42200000 { @@ -145,6 +147,7 @@ clock-names = "fck"; clocks = <&k3_clks 194 0>; power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_i2c1: i2c@40b10000 { @@ -156,6 +159,7 @@ clock-names = "fck"; clocks = <&k3_clks 195 0>; power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; wkup_i2c0: i2c@42120000 { @@ -167,15 +171,36 @@ clock-names = "fck"; clocks = <&k3_clks 197 0>; power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; + status = "disabled"; }; fss: fss@47000000 { - compatible = "simple-bus"; + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; reg = <0x0 0x47000000 0x0 0x100>; #address-cells = <2>; #size-cells = <2>; ranges; + hbmc_mux: mux-controller@47000004 { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4 0x2>; /* HBMC select */ + }; + + hbmc: hyperbus@47034000 { + compatible = "ti,am654-hbmc"; + reg = <0x00 0x47034000 0x00 0x100>, + <0x05 0x00000000 0x01 0x0000000>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 0>; + assigned-clocks = <&k3_clks 102 5>; + assigned-clock-rates = <333333333>; + #address-cells = <2>; + #size-cells = <1>; + mux-controls = <&hbmc_mux 0>; + status = "disabled"; + }; + ospi0: spi@47040000 { compatible = "ti,am654-ospi", "cdns,qspi-nor"; reg = <0x0 0x47040000 0x0 0x100>, @@ -353,7 +378,7 @@ mcu_r5fss0: r5fss@41000000 { compatible = "ti,j721e-r5fss"; - ti,cluster-mode = <1>; + ti,cluster-mode = <0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x41000000 0x00 0x41000000 0x20000>, @@ -403,6 +428,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; mcu_mcan1: can@40568000 { @@ -417,5 +443,48 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcu_spi0: spi@40300000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040300000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 274 0>; + status = "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040310000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 275 0>; + status = "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040320000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 0>; + status = "disabled"; + }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j721e-vtm"; + reg = <0x00 0x42040000 0x00 0x350>, + <0x00 0x42050000 0x00 0x350>, + <0x00 0x43000300 0x00 0x10>; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-ov5640.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-ov5640.dtso @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LI OV5640 MIPI Camera module on MIPI CSI connector. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&main_pmx0 { + csi2_exp_pins_default: csi2-exp-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x140, PIN_OUTPUT, 7) /* (AG29) PRG0_PRU1_GPO16.GPIO0_79 */ + >; + }; +}; + +&main_i2c3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-switch@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + ti_cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&csi2_exp_pins_default>; + powerdown-gpios = <&main_gpio0 79 GPIO_ACTIVE_LOW>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-rpi-imx219.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-rpi-imx219.dtso @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RPi Camera V2.1 (Sony IMX219) Camera module on RPI camera connector. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&main_pmx0 { + main_rpi_cam0_reset_pins_default: main-rpi-cam0-reset-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1D4, PIN_OUTPUT, 7) /* (Y3) SPI1_CS0 */ + >; + }; + + main_rpi_cam1_reset_pins_default: main-rpi-cam1-reset-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1E0, PIN_OUTPUT, 7) /* (Y5) SPI1_D0 */ + >; + }; + + main_csi_mux_sel2_pins_default: main-csi-mux-sel2-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */ + >; + }; +}; + +&main_gpio0 { + csi-mux-hog { + /* CSI_MUX_SEL_2 */ + gpio-hog; + gpios = <88 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI_MUX_SEL_2"; + }; +}; + +&main_i2c3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-switch@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_csi_mux_sel2_pins_default>; + + i2c-alias-pool = /bits/ 16 <0x10 0x11>; + + /* CAM0 I2C */ + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + imx219_0: imx219_0@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + pinctrl-names = "default"; + pinctrl-0 = <&main_rpi_cam0_reset_pins_default>; + reset-gpios = <&main_gpio0 116 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + cam1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + imx219_1: imx219_1@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + pinctrl-names = "default"; + pinctrl-0 = <&main_rpi_cam1_reset_pins_default>; + reset-gpios = <&main_gpio0 119 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; + +&csi1_port0 { + status = "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-sk-fusion.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-sk-fusion.dtso @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Fusion (FPD-Link III) board on J721E SK + * https://svtronics.com/portfolio/evm577pfusion-v1-0-fusion/ + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + + +&main_i2c3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + deser@3d { + compatible = "ti,ds90ub960-q1"; + reg = <0x3d>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + ds90ub960_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + ds90ub960_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + deser@36 { + compatible = "ti,ds90ub960-q1"; + reg = <0x36>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + ds90ub960_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + ds90ub960_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; +}; + +&csi1_port0 { + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-sk-rpi-hdr-ehrpwm.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-sk-rpi-hdr-ehrpwm.dtso @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling EHRPWMs on RPi expansion header on J721E SK board. + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-pinctrl.h" + +&main_pmx0 { + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ + J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AD28) PRG0_PRU1_GPO8.GPIO0_71 */ + J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO19.GPIO0_82 */ + J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ + J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ + J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ + J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ + J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ + J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ + J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ + J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ + J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ + J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ + J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ + J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ + J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ + J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ + J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ + J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ + >; + }; + + rpi_header_ehrpwm2_pins_default: rpi-header-ehrpwm2-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x178, PIN_INPUT, 6) /* (U27) RGMII5_RD3.EHRPWM2_A */ + J721E_IOPAD(0x17C, PIN_INPUT, 6) /* (U24) RGMII5_RD2.EHRPWM2_B */ + >; + }; + + rpi_header_ehrpwm3_pins_default: rpi-header-ehrpwm3-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x18C, PIN_INPUT, 6) /* (V23) RGMII6_RX_CTL.EHRPWM3_A */ + J721E_IOPAD(0x190, PIN_INPUT, 6) /* (W23) RGMII6_TD3.EHRPWM3_B */ + >; + }; +}; + +&main_ehrpwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm2_pins_default>; + status = "okay"; +}; + +&main_ehrpwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_ehrpwm3_pins_default>; + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-sk.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -33,6 +33,14 @@ #size-cells = <2>; ranges; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x20000000>; + linux,cma-default; + }; + secure_ddr: optee@9e800000 { reg = <0x00 0x9e800000 0x00 0x01800000>; alignment = <0x1000>; @@ -400,9 +408,66 @@ J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ >; }; + + main_i2c5_pins_default: main-i2c5-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ + J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ + >; + }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ + J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ + J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ + J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ + J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ + J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ + J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ + J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ + J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ + J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ + J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ + J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ + J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ + J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ + J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ + J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ + J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ + J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ + J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ + J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ + J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ + J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ + J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ + >; + }; + + rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ + >; + }; }; &wkup_pmx0 { + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ @@ -473,48 +538,27 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; -&main_uart2 { - /* Brought out on RPi header */ - status = "disabled"; -}; - -&main_uart3 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart5 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart6 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart7 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart8 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart9 { - /* Brought out on M.2 E Key */ - status = "disabled"; +&main_uart1 { + status = "okay"; + /* Default pinmux */ }; &main_sdhci0 { @@ -552,6 +596,52 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@7c0000 { + label = "ospi.env.backup"; + reg = <0x7c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; @@ -561,6 +651,7 @@ }; &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -588,18 +679,15 @@ }; &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; /* i2c1 is used for DVI DDC, so we need to use 100kHz */ clock-frequency = <100000>; }; -&main_i2c2 { - /* Unused */ - status = "disabled"; -}; - &main_i2c3 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c3_pins_default>; clock-frequency = <400000>; @@ -626,19 +714,22 @@ }; }; -&main_i2c4 { - /* Unused */ - status = "disabled"; -}; - &main_i2c5 { /* Brought out on RPi Header */ - status = "disabled"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; }; -&main_i2c6 { - /* Unused */ - status = "disabled"; +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio1_pins_default>; }; &main_gpio2 { @@ -783,6 +874,24 @@ phy-handle = <&phy0>; }; +&ti_csi2rx0 { + status = "okay"; + /* MIPI-CSI Connector */ +}; + +&ti_csi2rx1 { + status = "okay"; + /* MIPI-CSI Connector */ +}; + +&dphy0 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; + &dss { pinctrl-names = "default"; pinctrl-0 = <&dss_vout0_pins_default>; @@ -837,66 +946,6 @@ }; }; -&mcasp0 { - /* Unused */ - status = "disabled"; -}; - -&mcasp1 { - /* Unused */ - status = "disabled"; -}; - -&mcasp2 { - /* Unused */ - status = "disabled"; -}; - -&mcasp3 { - /* Unused */ - status = "disabled"; -}; - -&mcasp4 { - /* Unused */ - status = "disabled"; -}; - -&mcasp5 { - /* Unused */ - status = "disabled"; -}; - -&mcasp6 { - /* Brought out on RPi header */ - status = "disabled"; -}; - -&mcasp7 { - /* Unused */ - status = "disabled"; -}; - -&mcasp8 { - /* Unused */ - status = "disabled"; -}; - -&mcasp9 { - /* Unused */ - status = "disabled"; -}; - -&mcasp10 { - /* Unused */ - status = "disabled"; -}; - -&mcasp11 { - /* Brought out on M.2 E Key */ - status = "disabled"; -}; - &serdes0 { serdes0_pcie_link: phy@0 { reg = <0>; @@ -918,6 +967,7 @@ }; &pcie0_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ekey_reset_pins_default>; reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; @@ -928,6 +978,7 @@ }; &pcie1_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mkey_reset_pins_default>; reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; @@ -937,53 +988,12 @@ num-lanes = <2>; }; -&pcie2_rc { - /* Unused */ - status = "disabled"; -}; - -&pcie0_ep { - status = "disabled"; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&pcie1_ep { - status = "disabled"; - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&pcie2_ep { - /* Unused */ - status = "disabled"; -}; - -&pcie3_rc { - /* Unused */ - status = "disabled"; -}; - -&pcie3_ep { - /* Unused */ - status = "disabled"; -}; - -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - &ufs_wrapper { status = "disabled"; }; &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -998,6 +1008,7 @@ }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { @@ -1012,6 +1023,7 @@ }; &mailbox0_cluster2 { + status = "okay"; interrupts = <428>; mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { @@ -1026,6 +1038,7 @@ }; &mailbox0_cluster3 { + status = "okay"; interrupts = <424>; mbox_c66_0: mbox-c66-0 { @@ -1040,6 +1053,7 @@ }; &mailbox0_cluster4 { + status = "okay"; interrupts = <420>; mbox_c71_0: mbox-c71-0 { @@ -1048,34 +1062,6 @@ }; }; -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -20,6 +20,14 @@ #size-cells = <2>; ranges; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x20000000>; + linux,cma-default; + }; + secure_ddr: optee@9e800000 { reg = <0x00 0x9e800000 0x00 0x01800000>; alignment = <0x1000>; @@ -150,6 +158,12 @@ >; }; + pmic_irq_pins_default: pmic-irq-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* (G26) WKUP_GPIO0_9 */ + >; + }; + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ @@ -165,6 +179,25 @@ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ >; }; + + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */ + J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */ + J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */ + J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */ + J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */ + J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* MCU_HYPERBUS0_RWDS */ + J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ0 */ + J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ1 */ + J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ2 */ + J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ3 */ + J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ4 */ + J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */ + J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */ + J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */ + >; + }; }; &ospi0 { @@ -182,10 +215,109 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x20000>; + }; + + partition@6a0000 { + label = "ospi.env.backup"; + reg = <0x6a0000 0x20000>; + }; + + partition@6c0000 { + label = "ospi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fe0000 { + label = "ospi.phypattern"; + reg = <0x3fe0000 0x20000>; + }; + }; + }; +}; + +&hbmc { + /* OSPI and HBMC are muxed inside FSS, Bootloader will enable + * appropriate node based on board detection + */ + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; + ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ + <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ + + flash@0,0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0x00 0x00 0x4000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "hbmc.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "hbmc.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "hbmc.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "hbmc.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "hbmc.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "hbmc.rootfs"; + reg = <0x800000 0x3800000>; + }; + }; }; }; &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -200,6 +332,7 @@ }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { @@ -214,6 +347,7 @@ }; &mailbox0_cluster2 { + status = "okay"; interrupts = <428>; mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { @@ -228,6 +362,7 @@ }; &mailbox0_cluster3 { + status = "okay"; interrupts = <424>; mbox_c66_0: mbox-c66-0 { @@ -242,6 +377,7 @@ }; &mailbox0_cluster4 { + status = "okay"; interrupts = <420>; mbox_c71_0: mbox-c71-0 { @@ -250,34 +386,6 @@ }; }; -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, @@ -331,3 +439,200 @@ memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; + +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + tps659413: pmic@48 { + compatible = "ti,tps6594-q1"; + reg = <0x48>; + system-power-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&wkup_gpio0>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + ti,primary-pmic; + + gpio-controller; + #gpio-cells = <2>; + + buck12-supply = <&vsys_3v3>; + buck3-supply = <&vsys_3v3>; + buck4-supply = <&vsys_3v3>; + buck5-supply = <&vsys_3v3>; + ldo1-supply = <&vsys_3v3>; + ldo2-supply = <&vsys_3v3>; + ldo3-supply = <&vsys_3v3>; + ldo4-supply = <&vsys_3v3>; + + regulators { + bucka12: buck12 { + regulator-name = "vdd_cpu_avs"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka3: buck3 { + regulator-name = "vdd_mcu_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka4: buck4 { + regulator-name = "vdd_ddr_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name = "vdd_phyio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name = "vdd1_lpddr4_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name = "vdd_mcuio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name = "vdda_dll_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name = "vda_mcu_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659411: pmic@4c { + compatible = "ti,tps6594-q1"; + reg = <0x4c>; + system-power-controller; + interrupt-parent = <&wkup_gpio0>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + buck1234-supply = <&vsys_3v3>; + buck5-supply = <&vsys_3v3>; + ldo1-supply = <&vsys_3v3>; + ldo2-supply = <&vsys_3v3>; + ldo3-supply = <&vsys_3v3>; + ldo4-supply = <&vsys_3v3>; + + regulators { + buckb1234: buck1234 { + regulator-name = "vdd_core_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb5: buck5 { + regulator-name = "vdd_ram_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob1: ldo1 { + regulator-name = "vdd_sd_dv"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob2: ldo2 { + regulator-name = "vdd_usb_3v3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob3: ldo3 { + regulator-name = "vdd_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob4: ldo4 { + regulator-name = "vda_pll_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps65917: pmic@58 { + reg = <0x58>; + compatible = "ti,tps65917"; + status = "disabled"; + tps65917-pmic { + compatible = "ti,tps65917-pmic"; + + ldo1-in-supply = <&vsys_3v3>; + ldo2-in-supply = <&vsys_3v3>; + + tps65917_regulators: regulators { + ldo1_reg: ldo1 { + /* LDO1_OUT --> VDD_SD_DV_REG */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-allow-bypass; + }; + + ldo2_reg: ldo2 { + /* LDO2_OUT --> VDA_USB_3V3_REG */ + regulator-name = "ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allow-bypass; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + wkup_thermal: wkup-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup_crit: wkup-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + mpu_thermal: mpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + mpu_crit: mpu-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + c7x_thermal: c7x-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + c7x_crit: c7x-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 3>; + + trips { + gpu_crit: gpu-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + r5f_thermal: r5f-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 4>; + + trips { + r5f_crit: r5f-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -7,9 +7,10 @@ #include #include -#include #include +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 J721E SoC"; compatible = "ti,j721e"; @@ -86,6 +87,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -134,6 +136,7 @@ <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ + <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ @@ -181,6 +184,8 @@ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ }; }; + + #include "k3-j721e-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -9,6 +9,9 @@ #include "k3-j721s2-som-p0.dtsi" #include +#include +#include +#include / { compatible = "ti,j721s2-evm", "ti,j721s2"; @@ -16,10 +19,11 @@ chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,2880000"; + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2880000"; }; aliases { + serial0 = &wkup_uart0; serial1 = &mcu_uart0; serial2 = &main_uart8; mmc0 = &main_sdhci0; @@ -27,6 +31,8 @@ can0 = &main_mcan16; can1 = &mcu_mcan0; can2 = &mcu_mcan1; + can3 = &main_mcan3; + can4 = &main_mcan5; }; evm_12v0: fixedregulator-evm12v0 { @@ -107,6 +113,82 @@ standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; }; + transceiver3: can-phy3 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; + enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; + mux-states = <&mux0 1>; + }; + + transceiver4: can-phy4 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>; + mux-states = <&mux1 1>; + }; + + dp0_pwr_3v3: fixedregulator-dp0-prw { + compatible = "regulator-fixed"; + regulator-name = "dp0-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 0 0>; /* P0 - DP0_PWR_SW_EN */ + enable-active-high; + }; + + dp1_pwr_3v3: regulator-dp1-prw { + compatible = "regulator-fixed"; + regulator-name = "dp1-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; /* P1 - DP1_PWR_SW_EN */ + enable-active-high; + regulator-always-on; + }; + + dp0: dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; +}; + +&main_i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <400000>; + + exp4: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&main_i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; }; &main_pmx0 { @@ -144,57 +226,154 @@ J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; + + main_mcan3_pins_default: main-mcan3-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */ + J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */ + >; + }; + + main_mcan5_pins_default: main-mcan5-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */ + J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */ + >; + }; + + main_i2c4_pins_default: main-i2c4-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) I2C4_SCL */ + J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) I2C4_SDA */ + >; + }; + + main_i2c5_pins_default: main-i2c5-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ + J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */ + >; + }; + + dp0_pins_default: dp0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0b8, PIN_INPUT, 3) /* (AA24) MCASP1_ACLKX.DP0_HPD */ + >; + }; }; -&wkup_pmx0 { +&wkup_pmx1 { + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ + >; + }; +}; + +&wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ - J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ - J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ - J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ - J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ - J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ - J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ - J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ - J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ - J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ >; }; mcu_mdio_pins_default: mcu-mdio-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ - J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; }; mcu_mcan0_pins_default: mcu-mcan0-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ - J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ >; }; mcu_mcan1_pins_default: mcu-mcan1-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ + J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ >; }; mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ - J721S2_WKUP_IOPAD(0x0a8, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ + J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ >; }; mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ + J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ + >; + }; + + mcu_adc0_pins_default: mcu-adc0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ + J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ + J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */ + J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */ + J721S2_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */ + J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */ + J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */ + J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ + >; + }; + + mcu_adc1_pins_default: mcu-adc1-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ + J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ + J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */ + J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */ + J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */ + J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */ + J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ + J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; }; }; @@ -217,51 +396,24 @@ &wkup_uart0 { status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; -&main_uart0 { - status = "disabled"; -}; - -&main_uart1 { - status = "disabled"; -}; - -&main_uart2 { - status = "disabled"; -}; - -&main_uart3 { - status = "disabled"; -}; - -&main_uart4 { - status = "disabled"; -}; - -&main_uart5 { - status = "disabled"; -}; - -&main_uart6 { - status = "disabled"; -}; - -&main_uart7 { - status = "disabled"; +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart8 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart8_pins_default>; /* Shared with TFA on this platform */ power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; }; -&main_uart9 { - status = "disabled"; -}; - &main_i2c0 { clock-frequency = <400000>; @@ -291,30 +443,6 @@ }; }; -&main_i2c1 { - status = "disabled"; -}; - -&main_i2c2 { - status = "disabled"; -}; - -&main_i2c3 { - status = "disabled"; -}; - -&main_i2c4 { - status = "disabled"; -}; - -&main_i2c5 { - status = "disabled"; -}; - -&main_i2c6 { - status = "disabled"; -}; - &main_sdhci0 { /* eMMC */ non-removable; @@ -334,6 +462,11 @@ &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + + cpts@3d000 { + /* Map HW4_TS_PUSH to GENF1 */ + ti,pps = <3 1>; + }; }; &davinci_mdio { @@ -350,82 +483,311 @@ phy-handle = <&phy0>; }; +&serdes_ln_ctrl { + idle-states = , , + , ; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + status = "okay"; + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + +&usb_serdes_mux { + idle-states = <1>; /* USB0 to SERDES lane 1 */ +}; + +&edp_serdes_mux { + idle-states = <1>; /* EDP0 to SERDES lane 2/3 */ +}; + +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; +}; + +&ospi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + + ospi1_nor: flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qspi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "qspi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "qspi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "qspi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "qspi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "qspi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "qspi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; + +&pcie1_rc { + status = "okay"; + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + &mcu_mcan0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_mcan0_pins_default>; phys = <&transceiver1>; }; &mcu_mcan1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_mcan1_pins_default>; phys = <&transceiver2>; }; -&main_mcan0 { - status = "disabled"; +&main_mcan3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan3_pins_default>; + phys = <&transceiver3>; }; -&main_mcan1 { - status = "disabled"; +&main_mcan5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan5_pins_default>; + phys = <&transceiver4>; }; -&main_mcan2 { - status = "disabled"; +&tscadc0 { + pinctrl-0 = <&mcu_adc0_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; }; -&main_mcan3 { - status = "disabled"; +&tscadc1 { + pinctrl-0 = <&mcu_adc1_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; }; -&main_mcan4 { - status = "disabled"; +&dss { + /* + * These clock assignments are chosen to enable the following outputs: + * + * VP0 - DisplayPort SST + * VP1 - DPI0 + * VP2 - DSI + * VP3 - DPI1 + */ + status = "okay"; + assigned-clocks = <&k3_clks 158 2>, + <&k3_clks 158 5>, + <&k3_clks 158 14>, + <&k3_clks 158 18>; + assigned-clock-parents = <&k3_clks 158 3>, + <&k3_clks 158 7>, + <&k3_clks 158 16>, + <&k3_clks 158 22>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; + + port@2 { + reg = <2>; + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; }; -&main_mcan5 { - status = "disabled"; +&dsi0_ports { + port@0 { + reg = <0>; + dsi0_out: endpoint { + remote-endpoint = <&dp1_in>; + }; + }; + + port@1 { + reg = <1>; + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; }; -&main_mcan6 { - status = "disabled"; +&dsi_edp_bridge_ports { + port@0 { + reg = <0>; + dp1_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + dp1_out: endpoint { + remote-endpoint = <&dp1_panel_in>; + }; + }; }; -&main_mcan7 { - status = "disabled"; +&dsi_edp_bridge { + aux-bus { + panel { + compatible = "ti,panel-edp"; + power-supply = <&dp1_pwr_3v3>; + + port { + dp1_panel_in: endpoint { + remote-endpoint = <&dp1_out>; + }; + }; + }; + }; }; -&main_mcan8 { - status = "disabled"; +&mhdp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; + cdns,no-hpd; }; -&main_mcan9 { - status = "disabled"; +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; }; -&main_mcan10 { - status = "disabled"; +&ti_csi2rx0 { + status = "okay"; + /* MIPI-CSI Connector */ }; -&main_mcan11 { - status = "disabled"; +&ti_csi2rx1 { + status = "okay"; + /* MIPI-CSI Connector */ }; -&main_mcan12 { - status = "disabled"; +&dphy_rx0 { + status = "okay"; }; -&main_mcan13 { - status = "disabled"; +&dphy_rx1 { + status = "okay"; }; -&main_mcan14 { - status = "disabled"; +&dphy_tx0 { + status = "okay"; }; -&main_mcan15 { - status = "disabled"; +&dsi0 { + status = "okay"; }; -&main_mcan17 { - status = "disabled"; +#define K3_TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val) + +×ync_router { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_cpts>; + + /* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */ + mcu_cpsw_cpts: mcu-cpsw-cpts { + pinctrl-single,pins = < + /* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */ + K3_TS_OFFSET(25, 17) + >; + }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-evm-csi2-ov5640.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-evm-csi2-ov5640.dtso @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LI OV5640 MIPI Camera module on MIPI CSI connector. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&main_i2c5 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + powerdown-gpios = <&exp5 0 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-evm-fusion.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-evm-fusion.dtso @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Fusion (FPD-Link III) board on J721S2 and J784S4 EVM + * https://svtronics.com/portfolio/evm577pfusion-v1-0-fusion/ + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + + +&main_i2c5 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + deser@3d { + compatible = "ti,ds90ub960-q1"; + reg = <0x3d>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + ds90ub960_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + ds90ub960_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + deser@36 { + compatible = "ti,ds90ub960-q1"; + reg = <0x36>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + ds90ub960_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + ds90ub960_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; +}; + +&csi1_port0 { + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board. + * + * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; + }; +}; + +&main_pmx0 { + main_cpsw_mdio_pins_default: main-cpsw-mdio-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */ + J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + + rgmii1_pins_default: rgmii1-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */ + J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */ + J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */ + J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */ + J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */ + J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */ + J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */ + J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */ + J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */ + J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */ + J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */ + >; + }; +}; + +&exp1 { + p15 { + /* P15 - EXP_MUX2 */ + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_MUX2"; + }; +}; + +&main_cpsw { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins_default>; +}; + +&main_cpsw_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw_mdio_pins_default>; + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&main_cpsw_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&main_cpsw_phy0>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the + * J7 common processor board. + * + * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie1_rc { + status = "disabled"; +}; + +&cbass_main { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + max-link-speed = <3>; + num-lanes = <1>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 41>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -4,6 +4,18 @@ * * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include + +#include +#include + +/ { + serdes_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; &cbass_main { msmc_ram: sram@70000000 { @@ -26,6 +38,103 @@ }; }; + scm_conf: syscon@104000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00104000 0x00 0x18000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00104000 0x18000>; + + usb_serdes_mux: mux-controller@0 { + compatible = "mmio-mux"; + reg = <0x0 0x4>; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ + }; + + phy_gmii_sel_cpsw: phy@34 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x34 0x4>; + #phy-cells = <1>; + }; + + serdes_ln_ctrl: mux-controller@80 { + compatible = "mmio-mux"; + reg = <0x80 0x10>; + #mux-control-cells = <1>; + mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ + }; + + edp_serdes_mux: mux-controller@310 { + compatible = "mmio-mux"; + reg = <0x310 0x4>; + #mux-control-cells = <1>; + /* EDP0 to SERDES0 lane 0/1 or 2/3 mux */ + mux-reg-masks = <0x310 0x10000000>; + }; + + ehrpwm_tbclk: clock-controller@140 { + compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + reg = <0x140 0x18>; + #clock-cells = <1>; + }; + }; + + main_ehrpwm0: pwm@3000000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3000000 0x00 0x100>; + power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>; + clock-names = "tbclk", "fck"; + }; + + main_ehrpwm1: pwm@3010000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3010000 0x00 0x100>; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>; + clock-names = "tbclk", "fck"; + }; + + main_ehrpwm2: pwm@3020000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3020000 0x00 0x100>; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>; + clock-names = "tbclk", "fck"; + }; + + main_ehrpwm3: pwm@3030000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3030000 0x00 0x100>; + power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>; + clock-names = "tbclk", "fck"; + }; + + main_ehrpwm4: pwm@3040000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3040000 0x00 0x100>; + power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>; + clock-names = "tbclk", "fck"; + }; + + main_ehrpwm5: pwm@3050000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3050000 0x00 0x100>; + power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>; + clock-names = "tbclk", "fck"; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; @@ -72,6 +181,25 @@ pinctrl-single,function-mask = <0xffffffff>; }; + main_crypto: crypto@4e00000 { + compatible = "ti,j721e-sa2ul"; + reg = <0x00 0x04e00000 0x00 0x1200>; + power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; + + dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, + <&main_udmap 0x4a41>; + dma-names = "tx", "rx1", "rx2"; + + rng: rng@4e10000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x00 0x04e10000 0x00 0x7d>; + interrupts = ; + }; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; @@ -80,6 +208,7 @@ clocks = <&k3_clks 146 3>; clock-names = "fclk"; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -90,6 +219,7 @@ clocks = <&k3_clks 350 3>; clock-names = "fclk"; power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -100,6 +230,7 @@ clocks = <&k3_clks 351 3>; clock-names = "fclk"; power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart3: serial@2830000 { @@ -110,6 +241,7 @@ clocks = <&k3_clks 352 3>; clock-names = "fclk"; power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart4: serial@2840000 { @@ -120,6 +252,7 @@ clocks = <&k3_clks 353 3>; clock-names = "fclk"; power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart5: serial@2850000 { @@ -130,6 +263,7 @@ clocks = <&k3_clks 354 3>; clock-names = "fclk"; power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart6: serial@2860000 { @@ -140,6 +274,7 @@ clocks = <&k3_clks 355 3>; clock-names = "fclk"; power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart7: serial@2870000 { @@ -150,6 +285,7 @@ clocks = <&k3_clks 356 3>; clock-names = "fclk"; power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart8: serial@2880000 { @@ -160,6 +296,7 @@ clocks = <&k3_clks 357 3>; clock-names = "fclk"; power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart9: serial@2890000 { @@ -170,6 +307,15 @@ clocks = <&k3_clks 358 3>; clock-names = "fclk"; power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + gpu: gpu@4e20000000 { + compatible = "ti,j721s2-pvr", "img,pvr-bxs64"; + reg = <0x4e 0x20000000 0x00 0x80000>; + interrupts = ; + power-domains = <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 130 1>; }; main_gpio0: gpio@600000 { @@ -256,6 +402,7 @@ clocks = <&k3_clks 215 1>; clock-names = "fck"; power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c2: i2c@2020000 { @@ -267,6 +414,7 @@ clocks = <&k3_clks 216 1>; clock-names = "fck"; power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c3: i2c@2030000 { @@ -278,6 +426,7 @@ clocks = <&k3_clks 217 1>; clock-names = "fck"; power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c4: i2c@2040000 { @@ -289,6 +438,7 @@ clocks = <&k3_clks 218 1>; clock-names = "fck"; power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c5: i2c@2050000 { @@ -300,6 +450,7 @@ clocks = <&k3_clks 219 1>; clock-names = "fck"; power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c6: i2c@2060000 { @@ -311,6 +462,41 @@ clocks = <&k3_clks 220 1>; clock-names = "fck"; power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + vpu: video-codec@4210000 { + compatible = "cnm,cm521c-vpu"; + reg = <0x00 0x4210000 0x00 0x10000>; + interrupts = ; + clocks = <&k3_clks 179 2>; + clock-names = "vcodec"; + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + sram = <&main_navss_sram>; + sram-size = <0x10000>; + operating-points-v2 = <&vpu_opp_table>; + vpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-20000000 { + opp-hz = /bits/ 64 <20000000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + }; }; main_sdhci0: mmc@4f80000 { @@ -362,11 +548,10 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; + ti,itap-del-sel-ddr50 = <0x2>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; - /* Masking support for SDR104 capability */ - sdhci-caps-mask = <0x00000003 0x00000000>; }; main_navss: bus@30000000 { @@ -378,6 +563,14 @@ dma-coherent; dma-ranges; + main_navss_sram: navss-sram@30000000{ + compatible = "mmio-sram"; + reg = <0x00 0x30000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x30000000 0x10000>; + }; + main_navss_intr: interrupt-controller@310e0000 { compatible = "ti,sci-intr"; reg = <0x00 0x310e0000 0x00 0x4000>; @@ -402,6 +595,7 @@ ti,sci = <&sms>; ti,sci-dev-id = <265>; ti,interrupt-ranges = <0 0 256>; + ti,unmapped-event-sources = <&main_bcdma_csi>; }; secure_proxy_main: mailbox@32c00000 { @@ -673,6 +867,21 @@ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; + main_bcdma_csi: dma-controller@311a0000 { + compatible = "ti,j721s2-dmss-bcdma-csi"; + reg = <0x00 0x311a0000 0x00 0x100>, + <0x00 0x35d00000 0x00 0x20000>, + <0x00 0x35c00000 0x00 0x10000>, + <0x00 0x35e00000 0x00 0x80000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <3>; + ti,sci = <&sms>; + ti,sci-dev-id = <225>; + ti,sci-rm-range-rchan = <0x21>; + ti,sci-rm-range-tchan = <0x22>; + }; + cpts@310d0000 { compatible = "ti,j721e-cpts"; reg = <0x0 0x310d0000 0x0 0x400>; @@ -686,6 +895,195 @@ }; }; + main_cpsw: ethernet@c200000 { + compatible = "ti,j721e-cpsw-nuss"; + reg = <0x00 0xc200000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + dma-coherent; + clocks = <&k3_clks 28 28>; + clock-names = "fck"; + power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xc640>, + <&main_udmap 0xc641>, + <&main_udmap 0xc642>, + <&main_udmap 0xc643>, + <&main_udmap 0xc644>, + <&main_udmap 0xc645>, + <&main_udmap 0xc646>, + <&main_udmap 0xc647>, + <&main_udmap 0x4640>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + phys = <&phy_gmii_sel_cpsw 1>; + status = "disabled"; + }; + }; + + main_cpsw_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 28 28>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 28 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + + usbss0: cdns-usb@4104000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x04104000 0x00 0x100>; + clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 360 17>; + power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-coherent; + + status = "disabled"; /* Needs pinmux */ + + usb0: usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x06000000 0x00 0x10000>, + <0x00 0x06010000 0x00 0x10000>, + <0x00 0x06020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = , + , + ; + interrupt-names = "host", "peripheral", "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + serdes_wiz0: wiz@5060000 { + compatible = "ti,j721s2-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x5060000 0x0 0x5060000 0x10000>, + <0xa030a00 0x0 0xa030a00 0x40>; /* DPTX PHY */ + + assigned-clocks = <&k3_clks 365 3>; + assigned-clock-parents = <&k3_clks 365 7>; + + serdes0: serdes@5060000 { + /* + * Note: we also map DPTX PHY registers as the Torrent + * needs to manage those. + */ + compatible = "ti,j721e-serdes-10g"; + reg = <0x05060000 0x00010000>, + <0xa030a00 0x40>; /* DPTX PHY */ + reg-names = "torrent_phy", "dptx_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 365 3>, + <&k3_clks 365 3>, + <&k3_clks 365 3>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; /* Needs lane config */ + + torrent_phy_dp: phy@2 { + reg = <2>; + resets = <&serdes_wiz0 3>; + cdns,phy-type = ; + cdns,num-lanes = <2>; + cdns,max-bit-rate = <5400>; + #phy-cells = <0>; + }; + }; + }; + + pcie1_rc: pcie@2910000 { + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x800000>, + <0x00 0x18000000 0x00 0x1000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 41>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb013>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + + status = "disabled"; /* Needs gpio and serdes info */ + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, @@ -698,6 +1096,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan1: can@2711000 { @@ -712,6 +1111,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan2: can@2721000 { @@ -726,6 +1126,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan3: can@2731000 { @@ -740,6 +1141,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan4: can@2741000 { @@ -754,6 +1156,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan5: can@2751000 { @@ -768,6 +1171,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan6: can@2761000 { @@ -782,6 +1186,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan7: can@2771000 { @@ -796,6 +1201,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan8: can@2781000 { @@ -810,6 +1216,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan9: can@2791000 { @@ -824,6 +1231,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan10: can@27a1000 { @@ -838,6 +1246,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan11: can@27b1000 { @@ -852,6 +1261,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan12: can@27c1000 { @@ -866,6 +1276,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan13: can@27d1000 { @@ -880,6 +1291,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan14: can@2681000 { @@ -894,6 +1306,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan15: can@2691000 { @@ -908,6 +1321,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan16: can@26a1000 { @@ -922,6 +1336,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan17: can@26b1000 { @@ -936,5 +1351,562 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_spi0: spi@2100000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 339 1>; + status = "disabled"; + }; + + main_spi1: spi@2110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 340 1>; + status = "disabled"; + }; + + main_spi2: spi@2120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 341 1>; + status = "disabled"; + }; + + main_spi3: spi@2130000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02130000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 342 1>; + status = "disabled"; + }; + + main_spi4: spi@2140000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02140000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 343 1>; + status = "disabled"; + }; + + main_spi5: spi@2150000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02150000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 344 1>; + status = "disabled"; + }; + + main_spi6: spi@2160000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02160000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 345 1>; + status = "disabled"; + }; + + main_spi7: spi@2170000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02170000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 346 1>; + status = "disabled"; + }; + + timesync_router: pinctrl@a40000 { + compatible = "pinctrl-single"; + reg = <0x0 0xa40000 0x0 0x800>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000107ff>; + status = "disabled"; + }; + + mhdp: dp-bridge@a000000 { + compatible = "ti,j721e-mhdp8546"; + /* + * Note: we do not map DPTX PHY area, as that is handled by + * the PHY driver. + */ + reg = <0x0 0xa000000 0x0 0x30a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ + <0x0 0x4f40000 0x0 0x20>; /* DSS_EDP0_INTG_CFG_VP */ + reg-names = "mhdptx", "j721e-intg"; + + clocks = <&k3_clks 156 19>; + + phys = <&torrent_phy_dp>; + phy-names = "dpphy"; + + interrupt-parent = <&gic500>; + interrupts = ; + + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + + status = "disabled"; + + dp0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + dphy_tx0: phy@4480000 { + compatible = "ti,j721e-dphy"; + reg = <0x0 0x04480000 0x0 0x1000>; + clocks = <&k3_clks 363 8>, <&k3_clks 363 14>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 363 14>; + assigned-clock-parents = <&k3_clks 363 15>; + assigned-clock-rates = <19200000>; + status = "disabled"; + }; + + dsi0: dsi@4800000 { + compatible = "ti,j721e-dsi"; + reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>; + clocks = <&k3_clks 154 4>, <&k3_clks 154 1>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + interrupt-parent = <&gic500>; + interrupts = ; + phys = <&dphy_tx0>; + phy-names = "dphy"; + status = "disabled"; + + dsi0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + }; + }; + + dss: dss@4a00000 { + compatible = "ti,j721e-dss"; + reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ + <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ + <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ + <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ + <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ + <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ + <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ + <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ + <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ + <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ + <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ + <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ + <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ + <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ + <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ + <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ + <0x00 0x04af0000 0x00 0x10000>; /* wb */ + + reg-names = "common_m", "common_s0", + "common_s1", "common_s2", + "vidl1", "vidl2","vid1","vid2", + "ovr1", "ovr2", "ovr3", "ovr4", + "vp1", "vp2", "vp3", "vp4", + "wb"; + + clocks = <&k3_clks 158 0>, + <&k3_clks 158 2>, + <&k3_clks 158 5>, + <&k3_clks 158 14>, + <&k3_clks 158 18>; + clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; + + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + + interrupts = , + , + , + ; + interrupt-names = "common_m", + "common_s0", + "common_s1", + "common_s2"; + + status = "disabled"; + + dss_ports: ports { + }; + }; + + ti_csi2rx0: ticsi2rx@4500000 { + status = "disabled"; + compatible = "ti,j721e-csi2rx"; + dmas = <&main_bcdma_csi 0 0x4940 0>, <&main_bcdma_csi 0 0x4941 0>, + <&main_bcdma_csi 0 0x4942 0>, <&main_bcdma_csi 0 0x4943 0>, + <&main_bcdma_csi 0 0x4944 0>, <&main_bcdma_csi 0 0x4945 0>, + <&main_bcdma_csi 0 0x4946 0>, <&main_bcdma_csi 0 0x4947 0>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7"; + reg = <0x00 0x04500000 0x00 0x1000>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "cdns,csi2rx"; + reg = <0x00 0x04504000 0x00 0x1000>; + clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>, + <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy_rx0>; + phy-names = "dphy"; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + status = "disabled"; + compatible = "ti,j721e-csi2rx"; + dmas = <&main_bcdma_csi 0 0x4960 0>, <&main_bcdma_csi 0 0x4961 0>, + <&main_bcdma_csi 0 0x4962 0>, <&main_bcdma_csi 0 0x4963 0>, + <&main_bcdma_csi 0 0x4964 0>, <&main_bcdma_csi 0 0x4965 0>, + <&main_bcdma_csi 0 0x4966 0>, <&main_bcdma_csi 0 0x4967 0>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7"; + reg = <0x00 0x04510000 0x00 0x1000>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "cdns,csi2rx"; + reg = <0x00 0x04514000 0x00 0x1000>; + clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>, + <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy_rx1>; + phy-names = "dphy"; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy_rx0: phy@4580000 { + status = "disabled"; + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04580000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + }; + + dphy_rx1: phy@4590000 { + status = "disabled"; + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04590000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + }; + + main_r5fss0: r5fss@5c00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c00000 0x00 0x5c00000 0x20000>, + <0x5d00000 0x00 0x5d00000 0x20000>; + power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss0_core0: r5f@5c00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5c00000 0x00010000>, + <0x5c10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <279>; + ti,sci-proc-ids = <0x06 0xff>; + resets = <&k3_reset 279 1>; + firmware-name = "j721s2-main-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss0_core1: r5f@5d00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5d00000 0x00010000>, + <0x5d10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <280>; + ti,sci-proc-ids = <0x07 0xff>; + resets = <&k3_reset 280 1>; + firmware-name = "j721s2-main-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss1: r5fss@5e00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5e00000 0x00 0x5e00000 0x20000>, + <0x5f00000 0x00 0x5f00000 0x20000>; + power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss1_core0: r5f@5e00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5e00000 0x00010000>, + <0x5e10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <281>; + ti,sci-proc-ids = <0x08 0xff>; + resets = <&k3_reset 281 1>; + firmware-name = "j721s2-main-r5f1_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss1_core1: r5f@5f00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5f00000 0x00010000>, + <0x5f10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <282>; + ti,sci-proc-ids = <0x09 0xff>; + resets = <&k3_reset 282 1>; + firmware-name = "j721s2-main-r5f1_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + c71_0: dsp@64800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x64800000 0x00 0x00080000>, + <0x00 0x64e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <8>; + ti,sci-proc-ids = <0x30 0xff>; + resets = <&k3_reset 8 1>; + firmware-name = "j721s2-c71_0-fw"; + }; + + c71_1: dsp@65800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x65800000 0x00 0x00080000>, + <0x00 0x65e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <11>; + ti,sci-proc-ids = <0x31 0xff>; + resets = <&k3_reset 11 1>; + firmware-name = "j721s2-c71_1-fw"; + }; + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x700000 0x00 0x1000>; + ti,esm-pins = <688>, <689>; + bootph-pre-ram; + }; + + watchdog0: watchdog@2200000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2200000 0x00 0x100>; + clocks = <&k3_clks 286 1>; + power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 286 1>; + assigned-clock-parents = <&k3_clks 286 5>; + }; + + watchdog1: watchdog@2210000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2210000 0x00 0x100>; + clocks = <&k3_clks 287 1>; + power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 287 1>; + assigned-clock-parents = <&k3_clks 287 5>; + }; + + /* + * The following RTI instances are coupled with MCU R5Fs, c7x and + * GPU so keeping them reserved as these will be used by their + * respective firmware + */ + watchdog2: watchdog@22f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x22f0000 0x00 0x100>; + clocks = <&k3_clks 290 1>; + power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 290 1>; + assigned-clock-parents = <&k3_clks 290 5>; + /* reserved for GPU */ + status = "reserved"; + }; + + watchdog3: watchdog@2300000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2300000 0x00 0x100>; + clocks = <&k3_clks 288 1>; + power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 288 1>; + assigned-clock-parents = <&k3_clks 288 5>; + /* reserved for C7X_0 */ + status = "reserved"; + }; + + watchdog4: watchdog@2310000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2310000 0x00 0x100>; + clocks = <&k3_clks 289 1>; + power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 289 1>; + assigned-clock-parents = <&k3_clks 289 5>; + /* reserved for C7X_1 */ + status = "reserved"; + }; + + watchdog5: watchdog@23c0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23c0000 0x00 0x100>; + clocks = <&k3_clks 291 1>; + power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 291 1>; + assigned-clock-parents = <&k3_clks 291 5>; + /* reserved for MAIN_R5F0_0 */ + status = "reserved"; + }; + + watchdog6: watchdog@23d0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23d0000 0x00 0x100>; + clocks = <&k3_clks 292 1>; + power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 292 1>; + assigned-clock-parents = <&k3_clks 292 5>; + /* reserved for MAIN_R5F0_1 */ + status = "reserved"; + }; + + watchdog7: watchdog@23e0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23e0000 0x00 0x100>; + clocks = <&k3_clks 293 1>; + power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 293 1>; + assigned-clock-parents = <&k3_clks 293 5>; + /* reserved for MAIN_R5F1_0 */ + status = "reserved"; + }; + + watchdog8: watchdog@23f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23f0000 0x00 0x100>; + clocks = <&k3_clks 294 1>; + power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 294 1>; + assigned-clock-parents = <&k3_clks 294 5>; + /* reserved for MAIN_R5F1_1 */ + status = "reserved"; }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -50,7 +50,34 @@ wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; + reg = <0x00 0x4301c000 0x00 0x034>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx1: pinctrl@4301c038 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c038 0x00 0x02C>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx2: pinctrl@4301c068 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c068 0x00 0x120>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx3: pinctrl@4301c190 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c190 0x00 0x004>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; @@ -91,6 +118,7 @@ clocks = <&k3_clks 359 3>; clock-names = "fclk"; power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_uart0: serial@40a00000 { @@ -101,6 +129,7 @@ clocks = <&k3_clks 149 3>; clock-names = "fclk"; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; wkup_gpio0: gpio@42110000 { @@ -144,6 +173,7 @@ clocks = <&k3_clks 223 1>; clock-names = "fck"; power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_i2c0: i2c@40b00000 { @@ -155,6 +185,7 @@ clocks = <&k3_clks 221 1>; clock-names = "fck"; power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_i2c1: i2c@40b10000 { @@ -166,6 +197,7 @@ clocks = <&k3_clks 222 1>; clock-names = "fck"; power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_mcan0: can@40528000 { @@ -180,6 +212,7 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; mcu_mcan1: can@40568000 { @@ -194,6 +227,40 @@ ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcu_spi0: spi@40300000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040300000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 347 0>; + status = "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040310000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 348 0>; + status = "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040320000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 349 0>; + status = "disabled"; }; mcu_navss: bus@28380000{ @@ -299,4 +366,177 @@ ti,cpts-periodic-outputs = <2>; }; }; + + tscadc0: tscadc@40200000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40200000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 0 0>; + assigned-clocks = <&k3_clks 0 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&main_udmap 0x7400>, + <&main_udmap 0x7401>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + + tscadc1: tscadc@40210000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40210000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 1 0>; + assigned-clocks = <&k3_clks 1 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&main_udmap 0x7402>, + <&main_udmap 0x7403>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + + fss: bus@47000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + ospi0: spi@47040000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47040000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 109 5>; + assigned-clocks = <&k3_clks 109 5>; + assigned-clock-parents = <&k3_clks 109 7>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; /* Needs pinmux */ + }; + + ospi1: spi@47050000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47050000 0x00 0x100>, + <0x07 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 110 5>; + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; /* Needs pinmux */ + }; + }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j7200-vtm"; + reg = <0x0 0x42040000 0x0 0x350>, + <0x0 0x42050000 0x0 0x350>, + <0x0 0x43000300 0x0 0x10>; + power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>; + #thermal-sensor-cells = <1>; + }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41000000 0x00010000>, + <0x41010000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <284>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 284 1>; + firmware-name = "j721s2-mcu-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41400000 0x00010000>, + <0x41410000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <285>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 285 1>; + firmware-name = "j721s2-mcu-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + mcu_esm: esm@40800000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x40800000 0x00 0x1000>; + ti,esm-pins = <95>; + bootph-pre-ram; + }; + + wkup_esm: esm@42080000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x42080000 0x00 0x1000>; + ti,esm-pins = <63>; + bootph-pre-ram; + }; + + /* + * The 2 RTI instances are couple with MCU R5Fs so keeping them + * reserved as these will be used by their respective firmware + */ + mcu_watchdog0: watchdog@40600000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x40600000 0x00 0x100>; + clocks = <&k3_clks 295 1>; + power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 295 1>; + assigned-clock-parents = <&k3_clks 295 5>; + /* reserved for MCU_R5F0_0 */ + status = "reserved"; + }; + + mcu_watchdog1: watchdog@40610000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x40610000 0x00 0x100>; + clocks = <&k3_clks 296 1>; + power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 296 1>; + assigned-clock-parents = <&k3_clks 296 5>; + /* reserved for MCU_R5F0_1 */ + status = "reserved"; + }; }; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -24,11 +24,133 @@ #size-cells = <2>; ranges; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x38000000>; + linux,cma-default; + }; + secure_ddr: optee@9e800000 { reg = <0x00 0x9e800000 0x00 0x01800000>; alignment = <0x1000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a8000000 { + reg = <0x00 0xa8000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; + }; + + mux0: mux-controller0 { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; + }; + + mux1: mux-controller1 { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; }; transceiver0: can-phy0 { @@ -37,6 +159,58 @@ #phy-cells = <0>; max-bitrate = <5000000>; }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + edp1_refclk: clock-edp1-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; +}; + +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ + >; + }; +}; + +&wkup_pmx1 { + pmic_irq_pins_default: pmic-irq-pins-default { + pinctrl-single,pins = < + /* (C21) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 7) + >; + }; }; &main_pmx0 { @@ -56,6 +230,7 @@ }; &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -73,21 +248,403 @@ }; &main_mcan16 { + status = "okay"; pinctrl-0 = <&main_mcan16_pins_default>; pinctrl-names = "default"; phys = <&transceiver0>; }; +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup_i2c0_pins_default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ + >; + }; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + tps659411: pmic@48 { + compatible = "ti,tps6594-q1"; + reg = <0x48>; + ti,primary-pmic; + system-power-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&wkup_gpio0>; + interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + buck1234-supply = <&vsys_3v3>; + buck5-supply = <&vsys_3v3>; + ldo1-supply = <&vsys_3v3>; + ldo2-supply = <&vsys_3v3>; + ldo3-supply = <&vsys_3v3>; + ldo4-supply = <&vsys_3v3>; + + regulators { + bucka1234: buck1234 { + regulator-name = "vdd_cpu_avs"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name = "vdd_mcu_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name = "vdd_mcuwk_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name = "vdd_mcu_gpioret_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name = "vdd_mcuio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name = "vda_mcu_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659414: pmic@4c { + compatible = "ti,tps6594-q1"; + reg = <0x4c>; + system-power-controller; + interrupt-parent = <&wkup_gpio0>; + interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + buck1-supply = <&vsys_3v3>; + buck2-supply = <&vsys_3v3>; + buck3-supply = <&vsys_3v3>; + buck4-supply = <&vsys_3v3>; + buck5-supply = <&vsys_3v3>; + ldo1-supply = <&vsys_3v3>; + ldo2-supply = <&vsys_3v3>; + ldo3-supply = <&vsys_3v3>; + ldo4-supply = <&vsys_3v3>; + + regulators { + buckb1: buck1 { + regulator-name = "vdd_io_1v8_reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buckb2: buck2 { + regulator-name = "vdd_fpd_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb3: buck3 { + regulator-name = "vdd_phy_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb4: buck4 { + regulator-name = "vdd_ddr_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb5: buck5 { + regulator-name = "vdd_ram_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob1: ldo1 { + regulator-name = "vdd_wk_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob2: ldo2 { + regulator-name = "vdd_gpioret_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob3: ldo3 { + regulator-name = "vda_dll_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob4: ldo4 { + regulator-name = "vda_pll_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + lp876411: pmic@58 { + compatible = "ti,lp8764-q1"; + reg = <0x58>; + system-power-controller; + interrupt-parent = <&wkup_gpio0>; + interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + buck1234-supply = <&vsys_3v3>; + + regulators { + buckc1234: buck1234 { + regulator-name = "vdd_core_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + ospi0_nor: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; + + ospi0_nand: nand@0 { + compatible = "spi-nand"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi_nand.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi_nand.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi_nand.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi_nand.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi_nand.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@2000000 { + label = "ospi_nand.rootfs"; + reg = <0x2000000 0x5fc0000>; + }; + + partition@7fc0000 { + label = "ospi_nand.phypattern"; + reg = <0x7fc0000 0x40000>; + }; + }; + }; +}; + +&main_i2c4 { + dsi_edp_bridge: dsi-edp-bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clock-names = "refclk"; + clocks = <&edp1_refclk>; + + enable-gpios = <&exp_som 5 0>; + + vpll-supply = <&vsys_io_1v8>; + vccio-supply = <&vsys_io_1v8>; + vcca-supply = <&vsys_io_1v2>; + vcc-supply = <&vsys_io_1v2>; + + dsi_edp_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + }; + }; +}; + &mailbox0_cluster0 { - status = "disabled"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; }; &mailbox0_cluster1 { - status = "disabled"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; }; &mailbox0_cluster2 { - status = "disabled"; + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; }; &mailbox0_cluster3 { @@ -95,7 +652,17 @@ }; &mailbox0_cluster4 { - status = "disabled"; + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; }; &mailbox0_cluster5 { @@ -173,3 +740,51 @@ &mailbox1_cluster11 { status = "disabled"; }; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&c71_0 { + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +wkup0_thermal: wkup0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup0_crit: wkup0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +wkup1_thermal: wkup1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + wkup1_crit: wkup1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 3>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 4>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main3_thermal: main3-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 5>; + + trips { + main3_crit: main3-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main4_thermal: main4-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 6>; + + trips { + main4_crit: main4-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2.dtsi =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -10,9 +10,10 @@ #include #include -#include #include +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 J721S2 SoC"; @@ -50,6 +51,9 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&L2_0>; + clocks = <&k3_clks 202 0>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; }; cpu1: cpu@1 { @@ -64,11 +68,36 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&L2_0>; + clocks = <&k3_clks 203 0>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp4-2000000000 { + opp-hz = /bits/ 64 <2000000000>; + }; + + opp3-1000000000 { + opp-hz = /bits/ 64 <1000000000>; }; + + opp2-500000000 { + opp-hz = /bits/ 64 <500000000>; + }; + + opp1-250000000 { + opp-hz = /bits/ 64 <250000000>; + }; + }; L2_0: l2-cache0 { compatible = "cache"; + cache-unified; cache-level = <2>; cache-size = <0x100000>; cache-line-size = <64>; @@ -114,6 +143,7 @@ #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Time Sync Router */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ @@ -161,6 +191,10 @@ }; }; + + thermal_zones: thermal-zones { + #include "k3-j721s2-thermal.dtsi" + }; }; /* Now include peripherals from each bus segment */ Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-ov5640.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-ov5640.dtso @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LI OV5640 MIPI Camera module on MIPI CSI (CSI2-EXP-AUX) connector. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + + +&main_pmx0 { + cam0_reset_pins_default: cam0-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x0114, PIN_OUTPUT, 7) + >; + }; +}; + +&pca9543_0 { + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_reset_pins_default>; + powerdown-gpios = <&main_gpio0 68 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-rpi-cam-imx219.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-rpi-cam-imx219.dtso @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for RPi Camera V2.1 on J722S-EVM board. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + cam0_reset_pins_default: cam0-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x03c, PIN_OUTPUT, 7) + >; + }; + + cam1_reset_pins_default: cam1-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x044, PIN_OUTPUT, 7) + >; + }; + + cam2_reset_pins_default: cam2-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x04c, PIN_OUTPUT, 7) + >; + }; + + cam3_reset_pins_default: cam3-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x054, PIN_OUTPUT, 7) + >; + }; +}; + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&exp1 { + p06-hog{ + /* P06 - CSI01_MUX_SEL_2 */ + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI01_MUX_SEL_2"; + }; + + p07-hog{ + /* P01 - CSI23_MUX_SEL_2 */ + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI23_MUX_SEL_2"; + }; +}; + +&pca9543_0 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-alias-pool = /bits/ 16 <0x10 0x11>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + imx219_0: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam0_reset_pins_default>; + + reset-gpios = <&main_gpio0 15 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + imx219_1: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam1_reset_pins_default>; + + reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + +&pca9543_1 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-alias-pool = /bits/ 16 <0x10 0x11>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + imx219_2: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam2_reset_pins_default>; + + reset-gpios = <&main_gpio0 19 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam2: endpoint { + remote-endpoint = <&csi2rx2_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + imx219_3: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam3_reset_pins_default>; + + reset-gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam3: endpoint { + remote-endpoint = <&csi2rx3_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx2_in_sensor: endpoint { + remote-endpoint = <&csi2_cam2>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx3 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi3_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx3_in_sensor: endpoint { + remote-endpoint = <&csi2_cam3>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; + + +&ti_csi2rx2 { + status = "okay"; +}; + +&dphy2 { + status = "okay"; +}; + + +&ti_csi2rx3 { + status = "okay"; +}; + +&dphy3 { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-tevi-ov5640.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-tevi-ov5640.dtso @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TEVI OV5640 MIPI Camera module on RPI camera connector. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + + +&main_pmx0 { + cam0_reset_pins_default: cam0-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x03c, PIN_OUTPUT, 7) + >; + }; + + cam1_reset_pins_default: cam1-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x044, PIN_OUTPUT, 7) + >; + }; + + cam2_reset_pins_default: cam2-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x04c, PIN_OUTPUT, 7) + >; + }; + + cam3_reset_pins_default: cam3-reset-pins-default { + pinctrl-single,pins = < + J722S_IOPAD(0x054, PIN_OUTPUT, 7) + >; + }; +}; + +&exp1 { + p06-hog{ + /* P06 - CSI01_MUX_SEL_2 */ + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI01_MUX_SEL_2"; + }; + + p07-hog{ + /* P01 - CSI23_MUX_SEL_2 */ + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI23_MUX_SEL_2"; + }; +}; + +&main_gpio0 { + p15-hog { + /* P15 - CSI2_CAMERA_GPIO1 */ + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI2_CAMERA_GPIO1"; + }; + + p17-hog { + /* P17 - CSI2_CAMERA_GPIO2 */ + gpio-hog; + gpios = <17 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI2_CAMERA_GPIO2"; + }; + + p19-hog { + /* P19 - CSI2_CAMERA_GPIO3 */ + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI2_CAMERA_GPIO3"; + }; + + p21-hog { + /* P21 - CSI2_CAMERA_GPIO4 */ + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI2_CAMERA_GPIO4"; + }; +}; + +&pca9543_0 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-alias-pool = /bits/ 16 <0x3c 0x3d>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ov5640_0: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam0_reset_pins_default>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ov5640_1: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam1_reset_pins_default>; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + +&pca9543_1 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-alias-pool = /bits/ 16 <0x3c 0x3d>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ov5640_2: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam2_reset_pins_default>; + + port { + csi2_cam2: endpoint { + remote-endpoint = <&csi2rx2_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ov5640_3: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&cam3_reset_pins_default>; + + port { + csi2_cam3: endpoint { + remote-endpoint = <&csi2rx3_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx2_in_sensor: endpoint { + remote-endpoint = <&csi2_cam2>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx3 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi3_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx3_in_sensor: endpoint { + remote-endpoint = <&csi2_cam3>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; + + +&ti_csi2rx2 { + status = "okay"; +}; + +&dphy2 { + status = "okay"; +}; + + +&ti_csi2rx3 { + status = "okay"; +}; + +&dphy3 { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm-dsi-rpi-7inch-panel.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm-dsi-rpi-7inch-panel.dtso @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for RPi 7inch touchscreen panel interfaced with DSI on + * J722S EVM. + * + * RPi DSI Panel: https://www.raspberrypi.com/products/raspberry-pi-touch-display/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + panel0 { + compatible = "raspberrypi,7inch-dsi", "simple-panel"; + backlight = <&display_reg>; + power-supply = <&display_reg>; + + port { + panel_in: endpoint { + remote-endpoint = <&panel_bridge_out>; + }; + }; + }; + + bridge_reg: bridge-regulator { + compatible = "regulator-fixed"; + regulator-name = "bridge-reg"; + gpio = <&display_reg 0 0>; + vin-supply = <&display_reg>; + enable-active-high; + }; +}; + +&exp2 { + p00-hog { + /* P00 - DSI_Mux_SEL_2 */ + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "DSI_Mux_SEL_2"; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&main_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + display_reg: regulator@45 { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&dsi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&panel_bridge_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dss1_dpi1_out>; + }; + }; + }; + + bridge@0 { + status = "okay"; + compatible = "toshiba,tc358762"; + reg = <0>; + vddc-supply = <&bridge_reg>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + panel_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&dss1_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* DSS1-VP1: DSI Output */ + port@1 { + reg = <1>; + + dss1_dpi1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-fusion.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm-fpdlink-fusion.dtso @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Fusion (FPD-Link III) board on J721E EVM + * https://svtronics.com/portfolio/evm577pfusion-v1-0-fusion/ + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + + +&pca9543_0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + deser@3d { + compatible = "ti,ds90ub960-q1"; + reg = <0x3d>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + ds90ub960_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + ds90ub960_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + deser@36 { + compatible = "ti,ds90ub960-q1"; + reg = <0x36>; + clocks = <&clk_fusion_25M_fixed>; + clock-names = "refclk"; + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + ds90ub960_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + ds90ub960_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm-microtips-mf101hie-panel.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm-microtips-mf101hie-panel.dtso @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Microtips integrated OLDI panel (MF-101HIEBCAF0) and touch DT overlay for J722S-EVM + * + * Panel datasheet: https://simplespec.microtipsusa.com/uploads/spec/datasheetFile/2588/13-101HIEBCAF0-S_V1.1_20221104.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + display { + compatible = "microtips,mf-101hiebcaf0"; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * Swapping them will not make any difference. + */ + port@0 { + dual-lvds-odd-pixels; + + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + + port@1 { + dual-lvds-even-pixels; + + lcd_in1: endpoint { + remote-endpoint = <&oldi_out1>; + }; + }; + }; +}; + +&dss0 { + status = "okay"; +}; + +&dss0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: LVDS Output (OLDI TX 0) */ + port@0 { + reg = <0>; + + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; + + /* VP1: LVDS Output (OLDI TX 1) */ + port@2 { + reg = <2>; + + oldi_out1: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; +}; + +&main_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&exp2>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&exp2 3 GPIO_ACTIVE_LOW>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT Overlay for Arducam V3Link UC-A09 board + * https://www.arducam.com/fpd-link-3-cameras/ + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_fusion_25M_fixed: fixed-clock-25M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&exp1 { + p06-hog { + /* P06 - CSI01_MUX_SEL_2 */ + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI01_MUX_SEL_2"; + }; + + p07-hog { + /* P01 - CSI23_MUX_SEL_2 */ + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CSI23_MUX_SEL_2"; + }; +}; + +&pca9543_0 { + #address-cells = <1>; + #size-cells = <0>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + ds90ub960_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + ds90ub960_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25M_fixed>; + + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + ds90ub960_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + }; + + ds90ub960_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm.dts =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -0,0 +1,905 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the J722S-EVM + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://www.ti.com/lit/zip/sprr495 + */ + +/dts-v1/; + +#include +#include "k3-j722s.dtsi" +#include +#include +#include +#include + +/ { + compatible = "ti,j722s-evm", "ti,j722s"; + model = "Texas Instruments J722S EVM"; + + aliases { + serial0 = &wkup_uart0; + serial2 = &main_uart0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + stdout-path = &main_uart0; + }; + + memory@80000000 { + /* 8G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type = "memory"; + bootph-pre-ram; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x38000000>; + linux,cma-default; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + c7x_1_memory_region: c7x-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x1c00000>; + alignment = <0x1000>; + no-map; + }; + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vsys_5v0: regulator-vsys5v0 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-mmc1 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&exp1 15 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vdd_sd_dv: regulator-TLV71033 { + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_default>; + + led-0 { + label = "j722s-evm:red:heartbeat"; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "j722s-evm:green:disk-activity"; + gpios = <&exp1 16 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_DISK_ACTIVITY; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + }; + + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; +}; + +&main_pmx0 { + + /delete-property/ interrupts; + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */ + J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */ + >; + bootph-all; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */ + J722S_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A22) I2C1_SDA */ + >; + bootph-all; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (F19) UART0_RXD */ + J722S_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (F20) UART0_TXD */ + J722S_IOPAD(0x01d4, PIN_OUTPUT, 0) /* (B21) UART0_RTSn */ + J722S_IOPAD(0x01d0, PIN_INPUT, 0) /* (E22) UART0_CTSn */ + >; + bootph-all; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */ + >; + bootph-all; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ + J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ + J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ + J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */ + J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */ + J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ + J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ + >; + bootph-all; + }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0000, PIN_OUTPUT, 0) /* (P23) OSPI0_CLK */ + J722S_IOPAD(0x002c, PIN_OUTPUT, 0) /* (M25) OSPI0_CSn0 */ + J722S_IOPAD(0x000c, PIN_INPUT, 0) /* (L25) OSPI0_D0 */ + J722S_IOPAD(0x0010, PIN_INPUT, 0) /* (N24) OSPI0_D1 */ + J722S_IOPAD(0x0014, PIN_INPUT, 0) /* (N25) OSPI0_D2 */ + J722S_IOPAD(0x0018, PIN_INPUT, 0) /* (M24) OSPI0_D3 */ + J722S_IOPAD(0x001c, PIN_INPUT, 0) /* (N21) OSPI0_D4 */ + J722S_IOPAD(0x0020, PIN_INPUT, 0) /* (N22) OSPI0_D5 */ + J722S_IOPAD(0x0024, PIN_INPUT, 0) /* (P21) OSPI0_D6 */ + J722S_IOPAD(0x0028, PIN_INPUT, 0) /* (N20) OSPI0_D7 */ + J722S_IOPAD(0x0008, PIN_INPUT, 0) /* (P22) OSPI0_DQS */ + >; + bootph-all; + }; + + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ + J722S_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + mdio_pins_default: mdio-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ + J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ + >; + }; + + rgmii1_pins_default: rgmii1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ + J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ + J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ + J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ + J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ + J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ + J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ + J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ + J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ + J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ + J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ + J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ + >; + }; + + led_pins_default: led-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0244, PIN_INPUT, 7) /* (A24) MMC1_SDWP */ + >; + }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */ + >; + }; + + main_gpio0_ioexp_intr_pins_default: main-gpio0-ioexp-intr-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0110, PIN_INPUT, 7) /* (G27) MMC2_DAT1.GPIO0_67 */ + >; + }; + + main_dpi_pins_default: main-dpi-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AB23) VOUT0_VSYNC */ + J722S_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ + J722S_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC26) VOUT0_PCLK */ + J722S_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (AC27) VOUT0_DE */ + J722S_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (W27) VOUT0_DATA0 */ + J722S_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA1 */ + J722S_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA2 */ + J722S_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W23) VOUT0_DATA3 */ + J722S_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA4 */ + J722S_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA5 */ + J722S_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y26) VOUT0_DATA6 */ + J722S_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (Y27) VOUT0_DATA7 */ + J722S_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA8 */ + J722S_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (AA27) VOUT0_DATA9 */ + J722S_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA10 */ + J722S_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA11 */ + J722S_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA12 */ + J722S_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA22) VOUT0_DATA13 */ + J722S_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AB26) VOUT0_DATA14 */ + J722S_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AB27) VOUT0_DATA15 */ + J722S_IOPAD(0x005c, PIN_OUTPUT, 1) /* (U27) GPMC0_AD8.VOUT0_DATA16 */ + J722S_IOPAD(0x0060, PIN_OUTPUT, 1) /* (U26) GPMC0_AD9.VOUT0_DATA17 */ + J722S_IOPAD(0x0064, PIN_OUTPUT, 1) /* (V27) GPMC0_AD10.VOUT0_DATA18 */ + J722S_IOPAD(0x0068, PIN_OUTPUT, 1) /* (V25) GPMC0_AD11.VOUT0_DATA19 */ + J722S_IOPAD(0x006c, PIN_OUTPUT, 1) /* (V26) GPMC0_AD12.VOUT0_DATA20 */ + J722S_IOPAD(0x0070, PIN_OUTPUT, 1) /* (V24) GPMC0_AD13.VOUT0_DATA21 */ + J722S_IOPAD(0x0074, PIN_OUTPUT, 1) /* (V22) GPMC0_AD14.VOUT0_DATA22 */ + J722S_IOPAD(0x0078, PIN_OUTPUT, 1) /* (V23) GPMC0_AD15.VOUT0_DATA23 */ + J722S_IOPAD(0x009c, PIN_OUTPUT, 1) /* (W26) GPMC0_WAIT1.VOUT0_EXTPCLKIN */ + >; + }; +}; + +&main_gpio1 { + status = "okay"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; + bootph-all; +}; + +&mcu_pmx0 { + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ + J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ + J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ + J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ + >; + bootph-all; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0) /* (C7) WKUP_I2C0_SCL */ + J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_I2C1_SDA */ + >; + bootph-all; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "reserved"; + bootph-all; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + bootph-all; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + bootph-all; + + exp1: gpio@23 { + compatible = "ti,tca6424"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "TRC_MUX_SEL", "OSPI/ONAND_MUX_SEL", + "MCASP1_FET_SEL", "CTRL_PM_I2C_OE#", + "CSI_VIO_SEL", "USB2.0_MUX_SEL", + "CSI01_MUX_SEL_2", "CSI23_MUX_SEL_2", + "LMK1_OE1", "LMK1_OE0", + "LMK2_OE0", "LMK2_OE1", + "GPIO_RGMII1_RST#", "GPIO_AUD_RSTn", + "GPIO_eMMC_RSTn", "GPIO_uSD_PWR_EN", + "USER_LED2", "MCAN0_STB", + "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", + "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", + "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; + p01-hog { + /* P01 - TRC_MUX_SEL */ + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "TRC_MUX_SEL"; + }; + }; +}; + +&main_i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; + + pca9543_0: i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + }; + + pca9543_1: i2c-mux@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + }; +}; + +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <100000>; + + exp2: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "DSI_Mux_SEL_2", "GPIO_eDP_ENABLE", + "DP0_PWR_SW_EN", "GPIO_OLDI_RSTn", + "GPIO_HDMI_RSTn", "HDMI_LS_OE", + "", "", + "DSI_GPIO0", "DSI_GPIO1", + "DSI_EDID", "IO_eDP_IRQ", + "OLDI_INT#", "HDMI_INTn", + "", ""; + + interrupt-parent = <&main_gpio0>; + interrupts = <67 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio0_ioexp_intr_pins_default>; + bootph-all; + + p04-hog { + /* P04 - GPIO_HDMI_RSTn */ + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "GPIO_HDMI_RSTn"; + }; + + p03-hog { + /* P03 - GPIO_OLDI_RSTn */ + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-low; + line-name = "GPIO_OLDI_RSTn"; + }; + + p05-hog { + /* P05 - HDMI_LS_OE */ + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "HDMI_LS_OE"; + }; + }; + + sii9022: bridge-hdmi@3b { + compatible = "sil,sii9022"; + reg = <0x3b>; + interrupt-parent = <&exp2>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = < 0 >; + + hdmi_tx_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * HDMI can be serviced with 3 potential VPs - + * (DSS0 VP1 / DSS1 VP0 / DSS1 VP1). + * For now, we will service it with DSS1 VP0. + */ + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dss1_dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&sdhci0 { + /*eMMC*/ + status = "okay"; + ti,driver-strength-ohm = <50>; + disable-wp; + bootph-all; +}; + +&sdhci1 { + /* SD/MMC */ + status = "okay"; + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + bootph-all; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + bootph-all; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x00 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + bootph-all; + }; + }; + }; + + ospi0_nand: nand@0 { + compatible = "spi-nand"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi_nand.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi_nand.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi_nand.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi_nand.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi_nand.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@2000000 { + label = "ospi_nand.rootfs"; + reg = <0x2000000 0x5fc0000>; + }; + + partition@7fc0000 { + label = "ospi_nand.phypattern"; + reg = <0x7fc0000 0x40000>; + }; + }; + }; +}; + +&cpsw3g { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins_default>; +}; + +&cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&mailbox0_cluster0 { + status = "okay"; + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + mbox_main_r5_0: mbox-main-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c7x_1: mbox-c7x-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&main_r5fss0 { + status = "okay"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&c7x_0 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; +}; + +&c7x_1 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; + memory-region = <&c7x_1_dma_memory_region>, + <&c7x_1_memory_region>; +}; + +&serdes_ln_ctrl { + idle-states = , + ; +}; + +&serdes0 { + status = "okay"; + serdes0_usb_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes1 { + serdes1_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz1 1>; + }; +}; + +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usbss1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; + ti,vbus-divider; +}; + +&usb1 { + dr_mode = "host"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&pcie0_rc { + status = "okay"; + reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; +}; + +&dss1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_dpi_pins_default>; + + assigned-clocks = <&k3_clks 241 0>, /* DSS1-VP0 */ + <&k3_clks 240 0>, /* DSS1-VP1 */ + <&k3_clks 245 0>; /* DPI Output */ + + assigned-clock-parents = <&k3_clks 241 2>, /* PLL 17 HDMI */ + <&k3_clks 240 1>, /* PLL 18 DSI */ + <&k3_clks 245 2>; /* DSS1-DPI0 */ +}; + +&dss1_ports { + /* DSS1-VP0: DPI/HDMI Output */ + port@0 { + reg = <0>; + + dss1_dpi0_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -0,0 +1,545 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J722S SoC Family + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include +#include +#include + +#include "k3-am62p5.dtsi" + +/* + * USB1 controller on AM62P and J722S are of different IP. + * Delete AM62P's USBSS1 node definition and redefine it for J722S. + */ + +/delete-node/ &usbss1; + +/ { + model = "Texas Instruments K3 J722S SoC"; + compatible = "ti,j722s"; + + cbass_main: bus@f0000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_0 */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */ + <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */ + <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ + <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */ + <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */ + <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe0 DAT0 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00040000>, /* OCSRAM */ + <0x00 0x78400000 0x00 0x78400000 0x00 0x00008000>, /* MAIN R5FSS0 ATCM */ + <0x00 0x78500000 0x00 0x78500000 0x00 0x00008000>, /* MAIN R5FSS0 BTCM */ + <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00200000>, /* C7X_0 L2SRAM */ + <0x00 0x7e200000 0x00 0x7e200000 0x00 0x00200000>, /* C7X_1 L2SRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, + + /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; + }; + + serdes_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + usbss1: cdns-usb@f920000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x0f920000 0x00 0x100>; + power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 278 3>, <&k3_clks 278 1>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb1: usb@31200000{ + compatible = "cdns,usb3"; + reg = <0x00 0x31200000 0x00 0x10000>, + <0x00 0x31210000 0x00 0x10000>, + <0x00 0x31220000 0x00 0x10000>; + reg-names = "otg", + "xhci", + "dev"; + interrupts = , /* irq.0 */ + , /* irq.6 */ + ; /* otgirq */ + interrupt-names = "host", + "peripheral", + "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + serdes_wiz0: wiz@f000000 { + compatible = "ti,am64-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <1>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; + + assigned-clocks = <&k3_clks 279 1>; + assigned-clock-parents = <&k3_clks 279 5>; + + serdes0: serdes@f000000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x0f000000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 279 1>, + <&k3_clks 279 1>, + <&k3_clks 279 1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; /* Needs lane config */ + }; + }; + + serdes_wiz1: wiz@f010000 { + compatible = "ti,am64-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <1>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x0f010000 0x0 0x0f010000 0x00010000>; + + assigned-clocks = <&k3_clks 280 1>; + assigned-clock-parents = <&k3_clks 280 5>; + + serdes1: serdes@f010000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x0f010000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz1 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 280 1>, + <&k3_clks 280 1>, + <&k3_clks 280 1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + }; + }; + + pcie0_rc: pcie@f102000 { + compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x0f102000 0x00 0x1000>, + <0x00 0x0f100000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x68000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&wkup_conf 0x4070>; + max-link-speed = <3>; + num-lanes = <1>; + power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + cdns,no-bar-match-nbits = <64>; + vendor-id = <0x104c>; + device-id = <0xb010>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, + <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */ + <0 0 0 2 &pcie0_intc 0>, /* INT B */ + <0 0 0 3 &pcie0_intc 0>, /* INT C */ + <0 0 0 4 &pcie0_intc 0>; /* INT D */ + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; + }; +}; + +/* Main domain overrides */ + +&inta_main_dmss { + ti,interrupt-ranges = <7 71 21>; +}; + +&inta_main_dmss_csi { + ti,interrupt-ranges = <0 237 8>; +}; + +&main_bcdma_csi { + compatible = "ti,j722s-dmss-bcdma-csi"; + reg = <0x00 0x4e230000 0x00 0x100>, + <0x00 0x4e180000 0x00 0x20000>, + <0x00 0x4e300000 0x00 0x10000>, + <0x00 0x4e100000 0x00 0x80000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&inta_main_dmss_csi>; + #dma-cells = <3>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <199>; + ti,sci-rm-range-rchan = <0x21>; + ti,sci-rm-range-tchan = <0x22>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; +}; + +&main_conf { + serdes_ln_ctrl: mux-controller@4080 { + compatible = "reg-mux"; + reg = <0x4080 0x14>; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x3>, /* SERDES0 lane0 select */ + <0x10 0x3>; /* SERDES1 lane0 select */ + }; +}; + +&oc_sram { + reg = <0x00 0x70000000 0x00 0x40000>; + ranges = <0x00 0x00 0x70000000 0x40000>; +}; + +&cbass_main { + ti_csi2rx1: ticsi2rx@30122000 { + compatible = "ti,j721e-csi2rx"; + dmas = <&main_bcdma_csi 0 0x5100 0>, <&main_bcdma_csi 0 0x5101 0>, + <&main_bcdma_csi 0 0x5102 0>, <&main_bcdma_csi 0 0x5103 0>; + dma-names = "rx0", "rx1", "rx2", "rx3"; + reg = <0x00 0x30122000 0x00 0x1000>; + power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@30121000 { + compatible = "cdns,csi2rx"; + reg = <0x00 0x30121000 0x00 0x1000>; + clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>, + <&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@30142000 { + compatible = "ti,j721e-csi2rx"; + dmas = <&main_bcdma_csi 0 0x5200 0>, <&main_bcdma_csi 0 0x5201 0>, + <&main_bcdma_csi 0 0x5202 0>, <&main_bcdma_csi 0 0x5203 0>; + dma-names = "rx0", "rx1", "rx2", "rx3"; + reg = <0x00 0x30142000 0x00 0x1000>; + power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx2: csi-bridge@30141000 { + compatible = "cdns,csi2rx"; + reg = <0x00 0x30141000 0x00 0x1000>; + clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>, + <&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy2>; + phy-names = "dphy"; + power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi2_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi2_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi2_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi2_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx3: ticsi2rx@30162000 { + compatible = "ti,j721e-csi2rx"; + dmas = <&main_bcdma_csi 0 0x5300 0>, <&main_bcdma_csi 0 0x5301 0>, + <&main_bcdma_csi 0 0x5302 0>, <&main_bcdma_csi 0 0x5303 0>; + dma-names = "rx0", "rx1"; + reg = <0x00 0x30162000 0x00 0x1000>; + power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx3: csi-bridge@30161000 { + compatible = "cdns,csi2rx"; + reg = <0x00 0x30161000 0x00 0x1000>; + clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>, + <&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy3>; + phy-names = "dphy"; + power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi3_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi3_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi3_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi3_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi3_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy1: phy@30130000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30130000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy2: phy@30150000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30150000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy3: phy@30170000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30170000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_r5fss0: r5fss@78400000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x78400000 0x00 0x78400000 0x8000>, + <0x78500000 0x00 0x78500000 0x8000>; + power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + main_r5fss0_core0: r5f@78400000 { + compatible = "ti,am62-r5f"; + reg = <0x78400000 0x00008000>, + <0x78500000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <262>; + ti,sci-proc-ids = <0x04 0xff>; + resets = <&k3_reset 262 1>; + firmware-name = "j722s-main-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + c7x_0: dsp@7e000000 { + compatible = "ti,am62a-c7xv-dsp"; + reg = <0x00 0x7e000000 0x00 0x00200000>; + reg-names = "l2sram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <208>; + ti,sci-proc-ids = <0x30 0xff>; + resets = <&k3_reset 208 1>; + firmware-name = "j722s-c71_0-fw"; + status = "disabled"; + }; + + c7x_1: dsp@7e200000 { + compatible = "ti,am62a-c7xv-dsp"; + reg = <0x00 0x7e200000 0x00 0x00200000>; + reg-names = "l2sram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <268>; + ti,sci-proc-ids = <0x31 0xff>; + resets = <&k3_reset 268 1>; + firmware-name = "j722s-c71_1-fw"; + status = "disabled"; + }; + + e5010: e5010@fd20000 { + compatible = "img,e5010-jpeg-enc"; + reg = <0x00 0xfd20000 0x00 0x100>, + <0x00 0xfd20200 0x00 0x200>; + reg-names = "regjasper", "regmmu"; + clocks = <&k3_clks 201 0>; + clock-names = "core_clk"; + power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; + interrupts = ; + }; + +}; + +/* MCU domain overrides */ + +&mcu_r5fss0_core0 { + firmware-name = "j722s-mcu-r5f0_0-fw"; +}; + +/* Wakeup domain overrides */ + +&wkup_r5fss0_core0 { + firmware-name = "j722s-wkup-r5f0_0-fw"; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-evm-csi2-ov5640.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-evm-csi2-ov5640.dtso @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LI OV5640 MIPI Camera module on MIPI CSI (CSI2-EXP-AUX) connector. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&main_i2c5 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + powerdown-gpios = <&exp5 0 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx2_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_port0 { + status = "okay"; + + csi2rx2_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with + * J7AHP board. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the + * board. + * + * Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf + * Product Link: https://www.ti.com/tool/J721EXENETXPANEVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5"; + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6"; + ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7"; + ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8"; + }; +}; + +&main_cpsw0 { + status = "okay"; +}; + +&main_cpsw0_port5 { + status = "okay"; + phy-handle = <&cpsw9g_phy1>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>; + phy-names = "mac", "serdes"; +}; + +&main_cpsw0_port6 { + status = "okay"; + phy-handle = <&cpsw9g_phy2>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>; + phy-names = "mac", "serdes"; +}; + +&main_cpsw0_port7 { + status = "okay"; + phy-handle = <&cpsw9g_phy0>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>; + phy-names = "mac", "serdes"; +}; + +&main_cpsw0_port8 { + status = "okay"; + phy-handle = <&cpsw9g_phy3>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>; + phy-names = "mac", "serdes"; +}; + +&main_cpsw0_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default>; + bus_freq = <1000000>; + reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <120000>; + #address-cells = <1>; + #size-cells = <0>; + + cpsw9g_phy0: ethernet-phy@16 { + reg = <16>; + }; + cpsw9g_phy1: ethernet-phy@17 { + reg = <17>; + }; + cpsw9g_phy2: ethernet-phy@18 { + reg = <18>; + }; + cpsw9g_phy3: ethernet-phy@19 { + reg = <19>; + }; +}; + +&exp2 { + /* Power-up ENET1 EXPANDER PHY. */ + qsgmii-line-hog { + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-low; + }; + /* Toggle MUX2 for MDIO lines */ + mux-sel-hog { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&main_pmx0 { + mdio0_pins_default: mdio0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */ + J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */ + >; + }; +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , + , ; +}; + +&serdes_wiz2 { + status = "okay"; +}; + +&serdes2 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + serdes2_qsgmii_link: phy@0 { + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz2 3>; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1 + * and ENET-2 Expansion slots of J784S4 EVM. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +&main_cpsw0 { + status = "okay"; + pinctrl-names = "default"; +}; + +&main_cpsw0_port1 { + status = "okay"; + phy-mode = "usxgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>; + phy-names = "mac", "serdes"; + fixed-link { + speed = <5000>; + full-duplex; + }; +}; + +&main_cpsw0_port2 { + status = "okay"; + phy-mode = "usxgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>; + phy-names = "mac", "serdes"; + fixed-link { + speed = <5000>; + full-duplex; + }; +}; + +&serdes_wiz2 { + status = "okay"; + assigned-clock-parents = <&k3_clks 406 9>; +}; + +&serdes2 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + serdes2_usxgmii_link: phy@2 { + reg = <2>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>; + }; +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , + , ; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-evm-virt-mac-client.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-evm-virt-mac-client.dtso @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling CPSW Virt MAC Client driver in Linux to interface with EthFw via the + * Linux MAC Only port as well as the Switch Ports of the CPSW9G CPSW instance. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + cpsw9g_virt_mac: main-r5fss-cpsw9g-virt-mac0 { + compatible = "ti,j721e-cpsw-virt-mac"; + dma-coherent; + ti,psil-base = <0x4a00>; + ti,remote-name = "mpu_1_0_ethswitch-device-0"; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + virt-emac-port { + ti,label = "virt-port"; + /* local-mac-address = [0 0 0 0 0 0]; */ + }; + }; + + cpsw9g_virt_maconly: main-r5fss-cpsw9g-virt-mac1 { + compatible = "ti,j721e-cpsw-virt-mac"; + dma-coherent; + ti,psil-base = <0x4a00>; + ti,remote-name = "mpu_1_0_ethmac-device-1"; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + virt-emac-port { + ti,label = "virt-port"; + /* local-mac-address = [0 0 0 0 0 0]; */ + }; + }; +}; + +/* uart2 is assigned to cpsw9g eth-switch fw running on remote CPU core */ +&main_uart2 { + status = "reserved"; +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , + , ; +}; + +&main_udmass_inta { + status = "okay"; +}; + +&main_ringacc { + status = "okay"; +}; + +&main_udmap { + status = "okay"; +}; + +/* Reserve shared memory for inter-core network communication */ +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + + main_r5fss0_core0_shared_memory_queue_region:r5f-virtual-eth-queues@af000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaf000000 0x00 0x200000>; + no-map; + }; + + main_r5fss0_core0_shared_memory_bufpool_region:r5f-virtual-eth-buffers@af200000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaf200000 0x00 0x1e00000>; + no-map; + }; +}; + +&main_r5fss0_core0 { + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>, + <&main_r5fss0_core0_shared_memory_queue_region>, + <&main_r5fss0_core0_shared_memory_bufpool_region>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -0,0 +1,1532 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 + */ + +/dts-v1/; + +#include +#include +#include "k3-j784s4.dtsi" + +/ { + compatible = "ti,j784s4-evm", "ti,j784s4"; + model = "Texas Instruments J784S4 EVM"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart8; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + i2c0 = &main_i2c0; + }; + + memory@80000000 { + device_type = "memory"; + /* 32G RAM */ + reg = <0x00 0x80000000 0x00 0x80000000>, + <0x08 0x80000000 0x07 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x70000000>; + linux,cma-default; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core0_memory_region: r5f-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core1_memory_region: r5f-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a9000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a9100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9100000 0x00 0xf00000>; + no-map; + }; + + c71_2_dma_memory_region: c71-dma-memory@aa000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa000000 0x00 0x100000>; + no-map; + }; + + c71_2_memory_region: c71-memory@aa100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa100000 0x00 0xf00000>; + no-map; + }; + + c71_3_dma_memory_region: c71-dma-memory@ab000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab000000 0x00 0x100000>; + no-map; + }; + + c71_3_memory_region: c71-memory@ab100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab100000 0x00 0xf00000>; + no-map; + }; + }; + + evm_12v0: regulator-evm12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: regulator-vsys3v3 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_5v0: regulator-vsys5v0 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-sd { + /* Output of TPS22918 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vsys_3v3>; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: regulator-TLV71033 { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + dp0_pwr_3v3: regulator-dp0-prw { + compatible = "regulator-fixed"; + regulator-name = "dp0-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + dp0: dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + edp1_refclk: clock-edp1-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + dp1_pwr_3v3: regulator-dp1-prw { + compatible = "regulator-fixed"; + regulator-name = "dp1-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; /* P1 - DP1_PWR_SW_EN */ + enable-active-high; + regulator-always-on; + }; + + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver3: can-phy2 { + /* standby pin has been grounded by default */ + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&wkup_pmx1 { + pmic_irq_pins_default: pmic-irq-pins-default { + pinctrl-single,pins = < + /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) + >; + }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ + J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ + J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ + J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ + >; + }; + + mcu_fss0_ospi0_pins1_default: mcu-fss0-ospi0-pins1-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ + >; + }; +}; + +&wkup_pmx2 { + status = "okay"; + wkup_i2c0_pins_default: wkup_i2c0_pins_default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x09C, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) MCU_UART0_CTSn */ + J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) MCU_UART0_RTSn */ + J784S4_WKUP_IOPAD(0x08C, PIN_INPUT, 0) /* (K38) MCU_UART0_RXD */ + J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) MCU_UART0_TXD */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ + J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ + J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ + J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ + J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ + J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ + J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + >; + }; + + mcu_adc0_pins_default: mcu-adc0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ + J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ + J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ + J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ + J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ + J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ + J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ + J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ + >; + }; + + mcu_adc1_pins_default: mcu-adc1-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ + J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ + J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ + J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ + J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ + J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ + J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ + J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ + >; + }; + +}; + +&wkup_gpio0 { + status = "okay"; +}; + +&wkup_gpio_intr { + status = "okay"; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + tps659413: pmic@48 { + compatible = "ti,tps6594-q1"; + reg = <0x48>; + system-power-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&wkup_gpio0>; + interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + ti,primary-pmic; + + gpio-controller; + #gpio-cells = <2>; + + buck12-supply = <&vsys_3v3>; + buck3-supply = <&vsys_3v3>; + buck4-supply = <&vsys_3v3>; + buck5-supply = <&vsys_3v3>; + ldo1-supply = <&vsys_3v3>; + ldo2-supply = <&vsys_3v3>; + ldo3-supply = <&vsys_3v3>; + ldo4-supply = <&vsys_3v3>; + + regulators { + bucka12: buck12 { + regulator-name = "vdd_ddr_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka3: buck3 { + regulator-name = "vdd_ram_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka4: buck4 { + regulator-name = "vdd_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name = "vdd_mcu_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name = "vdd_mcuio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name = "vdd_mcuio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name = "vds_dll_0v8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name = "vda_mcu_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&main_pmx0 { + main_cpsw2g_pins_default: main-cpsw2g-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ + J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ + J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ + J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ + J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */ + J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ + J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ + J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ + J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ + J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ + J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */ + >; + }; + + main_cpsw2g_mdio_pins_default: main-cpsw2g-mdio-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ + J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + + main_uart8_pins_default: main-uart8-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ + J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ + J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ + J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ + J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ + >; + }; + + main_i2c5_pins_default: main-i2c5-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ + J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ + J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ + J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ + J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ + J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ + J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ + J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ + J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ + >; + }; + + dp0_pins_default: dp0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ + >; + }; + + main_i2c4_pins_default: main-i2c4-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ + J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ + >; + }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ + >; + }; + + main_mcan16_pins_default: main-mcan16-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */ + J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */ + >; + }; +}; + +&wkup_pmx0 { + typec_dir_gpio_pins_default: typec-dir-gpio-pins-default { + pinctrl-single,pins = < + /* (A33) MCU_OSPI0_CSn1.WKUP_GPIO0_28 */ + J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 7) + >; + }; + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ + J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ + >; + }; +}; + +&wkup_pmx2{ + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ + J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ + >; + }; + + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_69 */ + >; + }; + + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ + >; + }; +}; + +&main_uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart8_pins_default>; +}; + +&ufs_wrapper { + status = "okay"; +}; + +&fss { + status = "okay"; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + ospi0_nor: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; + + ospi0_nand: nand@0 { + compatible = "spi-nand"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi_nand.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi_nand.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi_nand.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi_nand.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi_nand.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@2000000 { + label = "ospi_nand.rootfs"; + reg = <0x2000000 0x5fc0000>; + }; + + partition@7fc0000 { + label = "ospi_nand.phypattern"; + reg = <0x7fc0000 0x40000>; + }; + }; + }; +}; + +&ospi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qspi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "qspi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "qspi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "qspi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "qspi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "qspi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "qspi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + + }; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + + clock-frequency = <400000>; + + exp1: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ", + "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", + "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", + "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", + "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; + }; + + exp2: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN", + "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", + "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", + "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", + "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", + "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", + "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", + "USER_INPUT1", "USER_LED1", "USER_LED2"; + }; +}; + +&main_sdhci0 { + /* eMMC */ + status = "okay"; + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; + no-mmc-hs400; +}; + +&main_sdhci1 { + /* SD card */ + status = "okay"; + pinctrl-0 = <&main_mmc1_pins_default>; + pinctrl-names = "default"; + disable-wp; + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; +}; + +&serdes0 { + status = "okay"; + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + + serdes0_usb_link: phy@3 { + reg = <3>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 4>; + }; +}; + +&serdes_wiz0 { + status = "okay"; +}; + +&usb_serdes_mux { + idle-states = <0>; /* USB0 to SERDES lane 3 */ +}; + +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&serdes1 { + status = "okay"; + serdes1_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; + }; +}; + +&serdes_wiz1 { + status = "okay"; +}; + +&pcie0_rc { + status = "okay"; + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; +}; + +&pcie0_ep { + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; +}; + +&pcie1_rc { + status = "okay"; + num-lanes = <2>; + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; +}; + +&pcie1_ep { + num-lanes = <2>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , ; +}; + +&main_gpio0 { + status = "okay"; +}; + +&mcu_cpsw { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default>; + + cpts@3d000 { + /* Map HW4_TS_PUSH to GENF1 */ + ti,pps = <3 1>; + }; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mdio_pins_default>; + + mcu_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&mcu_cpsw_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&mcu_phy0>; +}; + +&main_cpsw1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw2g_pins_default>; +}; + +&main_cpsw1_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw2g_mdio_pins_default>; + + main_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&main_cpsw1_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&main_phy0>; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&dss { + status = "okay"; + assigned-clocks = <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + assigned-clock-parents = <&k3_clks 218 3>, + <&k3_clks 218 7>, + <&k3_clks 218 16>, + <&k3_clks 218 22>; +}; + +&serdes_wiz4 { + status = "okay"; +}; + +&serdes4 { + status = "okay"; + serdes4_dp_link: phy@0 { + reg = <0>; + cdns,num-lanes = <4>; + #phy-cells = <0>; + cdns,phy-type = ; + cdns,max-bit-rate = <2700>; + resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, + <&serdes_wiz4 3>, <&serdes_wiz4 4>; + }; +}; + +&mhdp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; + phys = <&serdes4_dp_link>; + phy-names = "dpphy"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; + + port@2 { + reg = <2>; + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&main_i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <400000>; + + exp4: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + dsi_edp_bridge: dsi-edp-bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clock-names = "refclk"; + clocks = <&edp1_refclk>; + + enable-gpios = <&exp4 2 GPIO_ACTIVE_HIGH>; + + vpll-supply = <&vsys_io_1v8>; + vccio-supply = <&vsys_io_1v8>; + vcca-supply = <&vsys_io_1v2>; + vcc-supply = <&vsys_io_1v2>; + + dsi_edp_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp1_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + dp1_out: endpoint { + remote-endpoint = <&dp1_panel_in>; + }; + }; + }; + + aux-bus { + panel { + compatible = "ti,panel-edp"; + power-supply = <&dp1_pwr_3v3>; + + port { + dp1_panel_in: endpoint { + remote-endpoint = <&dp1_out>; + }; + }; + }; + }; + }; +}; + +&dsi0_ports { + port@0 { + reg = <0>; + dsi0_out: endpoint { + remote-endpoint = <&dp1_in>; + }; + }; + + port@1 { + reg = <1>; + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; +}; + +&main_i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + interrupts = <424>; + + mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster5 { + status = "okay"; + interrupts = <416>; + + mbox_c71_2: mbox-c71-2 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_3: mbox-c71-3 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mcu_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&main_r5fss2_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; + memory-region = <&main_r5fss2_core0_dma_memory_region>, + <&main_r5fss2_core0_memory_region>; +}; + +&main_r5fss2_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; + memory-region = <&main_r5fss2_core1_dma_memory_region>, + <&main_r5fss2_core1_memory_region>; +}; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; + +&c71_2 { + status = "okay"; + mboxes = <&mailbox0_cluster5 &mbox_c71_2>; + memory-region = <&c71_2_dma_memory_region>, + <&c71_2_memory_region>; +}; + +&c71_3 { + status = "okay"; + mboxes = <&mailbox0_cluster5 &mbox_c71_3>; + memory-region = <&c71_3_dma_memory_region>, + <&c71_3_memory_region>; +}; + +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; + /* MIPI-CSI Connector 0 */ +}; + +&ti_csi2rx1 { + status = "okay"; + /* MIPI-CSI Connector 0 */ +}; + +&ti_csi2rx2 { + status = "okay"; + /* MIPI-CSI Connector 1 */ +}; + +&dphy_rx0 { + status = "okay"; +}; + +&dphy_rx1 { + status = "okay"; +}; + +&dphy_rx2 { + status = "okay"; +}; + +&tscadc0 { + pinctrl-0 = <&mcu_adc0_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&tscadc1 { + pinctrl-0 = <&mcu_adc1_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +#define K3_TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val) + +×ync_router { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_cpts>; + + /* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */ + mcu_cpsw_cpts: mcu-cpsw-cpts { + pinctrl-single,pins = < + /* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */ + K3_TS_OFFSET(25, 17) + >; + }; +}; + +&wkup_uart0 { + status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; +}; + +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan16 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan16_pins_default>; + phys = <&transceiver3>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -0,0 +1,2601 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J784S4 SoC Family Main Domain peripherals + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include + +/ { + serdes_refclk: serdes-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; +}; + +&cbass_main { + msmc_ram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x00 0x70000000 0x00 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x70000000 0x800000>; + + atf-sram@0 { + reg = <0x00 0x20000>; + }; + + tifs-sram@1f0000 { + reg = <0x1f0000 0x10000>; + }; + + l3cache-sram@200000 { + reg = <0x200000 0x200000>; + }; + }; + + scm_conf: syscon@100000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00100000 0x00 0x1c000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00100000 0x1c000>; + + cpsw1_phy_gmii_sel: phy@4034 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4034 0x4>; + #phy-cells = <1>; + }; + + cpsw0_phy_gmii_sel: phy@4044 { + compatible = "ti,j784s4-cpsw9g-phy-gmii-sel"; + ti,qsgmii-main-ports = <7>, <7>; + reg = <0x4044 0x20>; + #phy-cells = <1>; + }; + + serdes_ln_ctrl: mux-controller@4080 { + compatible = "mmio-mux"; + reg = <0x00004080 0x30>; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + }; + + usb_serdes_mux: mux-controller@4000 { + compatible = "mmio-mux"; + reg = <0x4000 0x4>; + #mux-control-cells = <1>; + mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 3 mux */ + }; + + ehrpwm_tbclk: clock-controller@4140 { + compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + reg = <0x4140 0x18>; + #clock-cells = <1>; + }; + }; + + main_ehrpwm0: pwm@3000000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3000000 0x00 0x100>; + power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 0>, <&k3_clks 219 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm1: pwm@3010000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3010000 0x00 0x100>; + power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 1>, <&k3_clks 220 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm2: pwm@3020000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3020000 0x00 0x100>; + power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm3: pwm@3030000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3030000 0x00 0x100>; + power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 3>, <&k3_clks 222 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm4: pwm@3040000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3040000 0x00 0x100>; + power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 4>, <&k3_clks 223 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm5: pwm@3050000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3050000 0x00 0x100>; + power-domains = <&k3_pds 224 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 5>, <&k3_clks 224 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ + <0x00 0x01900000 0x00 0x100000>, /* GICR */ + <0x00 0x6f000000 0x00 0x2000>, /* GICC */ + <0x00 0x6f010000 0x00 0x1000>, /* GICH */ + <0x00 0x6f020000 0x00 0x2000>; /* GICV */ + + /* vcpumntirq: virtual CPU interface maintenance interrupt */ + interrupts = ; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_gpio_intr: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&sms>; + ti,sci-dev-id = <10>; + ti,interrupt-ranges = <8 392 56>; + }; + + main_pmx0: pinctrl@11c000 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x11c000 0x00 0x120>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_crypto: crypto@4e00000 { + compatible = "ti,j721e-sa2ul"; + reg = <0x00 0x4e00000 0x00 0x1200>; + power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; + + dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, + <&main_udmap 0x4a41>; + dma-names = "tx", "rx1", "rx2"; + + rng: rng@4e10000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x00 0x4e10000 0x00 0x7d>; + interrupts = ; + }; + }; + + main_uart0: serial@2800000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 146 0>; + clock-names = "fclk"; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 388 0>; + clock-names = "fclk"; + power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_uart2: serial@2820000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 389 0>; + clock-names = "fclk"; + power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_uart3: serial@2830000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 390 0>; + clock-names = "fclk"; + power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_uart4: serial@2840000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 391 0>; + clock-names = "fclk"; + power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_uart5: serial@2850000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 392 0>; + clock-names = "fclk"; + power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_uart6: serial@2860000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 393 0>; + clock-names = "fclk"; + power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_uart7: serial@2870000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02870000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 394 0>; + clock-names = "fclk"; + power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_uart8: serial@2880000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02880000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 395 0>; + clock-names = "fclk"; + power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_uart9: serial@2890000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02890000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 396 0>; + clock-names = "fclk"; + power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + gpu: gpu@4e20000000 { + compatible = "ti,j721s2-pvr", "img,pvr-bxs64"; + reg = <0x4e 0x20000000 0x00 0x80000>; + interrupts = ; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 181 1>; + }; + + main_gpio0: gpio@600000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00600000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <145>, <146>, <147>, <148>, <149>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <66>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 163 0>; + clock-names = "gpio"; + status = "disabled"; + }; + + main_gpio2: gpio@610000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00610000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <154>, <155>, <156>, <157>, <158>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <66>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 164 0>; + clock-names = "gpio"; + status = "disabled"; + }; + + main_gpio4: gpio@620000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00620000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <163>, <164>, <165>, <166>, <167>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <66>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 165 0>; + clock-names = "gpio"; + status = "disabled"; + }; + + main_gpio6: gpio@630000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00630000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <172>, <173>, <174>, <175>, <176>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <66>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 166 0>; + clock-names = "gpio"; + status = "disabled"; + }; + + usbss0: cdns-usb@4104000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x4104000 0x00 0x100>; + dma-coherent; + power-domains = <&k3_pds 398 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 398 21>, <&k3_clks 398 2>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 398 21>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 398 22>; /* HFOSC0 */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb0: usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x6000000 0x00 0x10000>, + <0x00 0x6010000 0x00 0x10000>, + <0x00 0x6020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = , /* irq.0 */ + , /* irq.6 */ + ; /* otgirq.0 */ + interrupt-names = "host", + "peripheral", + "otg"; + }; + }; + + main_i2c0: i2c@2000000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02000000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 270 2>; + clock-names = "fck"; + power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_i2c1: i2c@2010000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02010000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 271 2>; + clock-names = "fck"; + power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_i2c2: i2c@2020000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02020000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 272 2>; + clock-names = "fck"; + power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_i2c3: i2c@2030000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02030000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 273 2>; + clock-names = "fck"; + power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_i2c4: i2c@2040000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02040000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 274 2>; + clock-names = "fck"; + power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_i2c5: i2c@2050000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02050000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 275 2>; + clock-names = "fck"; + power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + main_i2c6: i2c@2060000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02060000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 276 2>; + clock-names = "fck"; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + vpu0: video-codec@4210000 { + compatible = "cnm,cm521c-vpu"; + reg = <0x00 0x4210000 0x00 0x10000>; + interrupts = ; + clocks = <&k3_clks 241 2>; + clock-names = "vcodec"; + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; + sram = <&main_navss_sram>; + sram-size = <0x10000>; + operating-points-v2 = <&vpu_opp_table_0>; + vpu_opp_table_0: opp-table { + compatible = "operating-points-v2"; + opp-20000000 { + opp-hz = /bits/ 64 <20000000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + }; + }; + + vpu1: video-codec@4220000 { + compatible = "cnm,cm521c-vpu"; + reg = <0x00 0x4220000 0x00 0x10000>; + interrupts = ; + clocks = <&k3_clks 242 2>; + clock-names = "vcodec"; + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + sram = <&main_navss_sram>; + sram-size = <0x10000>; + operating-points-v2 = <&vpu_opp_table_1>; + vpu_opp_table_1: opp-table { + compatible = "operating-points-v2"; + opp-20000000 { + opp-hz = /bits/ 64 <20000000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <600000000>; + }; + }; + }; + + main_sdhci0: mmc@4f80000 { + compatible = "ti,j721e-sdhci-8bit"; + reg = <0x00 0x04f80000 0x00 0x1000>, + <0x00 0x04f88000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 140 2>; + assigned-clock-parents = <&k3_clks 140 3>; + bus-width = <8>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-ddr52 = <0x6>; + ti,otap-del-sel-hs200 = <0x8>; + ti,otap-del-sel-hs400 = <0x5>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,strobe-sel = <0x77>; + ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + dma-coherent; + status = "disabled"; + }; + + main_sdhci1: mmc@4fb0000 { + compatible = "ti,j721e-sdhci-4bit"; + reg = <0x00 0x04fb0000 0x00 0x1000>, + <0x00 0x04fb8000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 141 4>; + assigned-clock-parents = <&k3_clks 141 5>; + bus-width = <4>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; + ti,otap-del-sel-ddr50 = <0xc>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,itap-del-sel-ddr50 = <0x2>; + ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; + dma-coherent; + status = "disabled"; + }; + + serdes_wiz0: wiz@5060000 { + compatible = "ti,j784s4-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; + assigned-clocks = <&k3_clks 404 6>; + assigned-clock-parents = <&k3_clks 404 10>; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x5060000 0x00 0x5060000 0x10000>; + + status = "disabled"; + + serdes0: serdes@5060000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05060000 0x010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 404 6>, + <&k3_clks 404 6>, + <&k3_clks 404 6>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; + }; + }; + + serdes_wiz1: wiz@5070000 { + compatible = "ti,j784s4-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; + assigned-clocks = <&k3_clks 405 6>; + assigned-clock-parents = <&k3_clks 405 10>; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x05070000 0x00 0x05070000 0x10000>; + + status = "disabled"; + + serdes1: serdes@5070000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05070000 0x010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz1 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 405 6>, + <&k3_clks 405 6>, + <&k3_clks 405 6>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; + }; + }; + + serdes_wiz2: wiz@5020000 { + compatible = "ti,j784s4-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; + assigned-clocks = <&k3_clks 406 6>; + assigned-clock-parents = <&k3_clks 406 10>; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x05020000 0x00 0x05020000 0x10000>; + + status = "disabled"; + + serdes2: serdes@5020000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05020000 0x010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz2 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz2 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 406 6>, + <&k3_clks 406 6>, + <&k3_clks 406 6>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; + }; + }; + + serdes_wiz4: wiz@5050000 { + compatible = "ti,j784s4-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; + assigned-clocks = <&k3_clks 407 6>; + assigned-clock-parents = <&k3_clks 407 10>; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x05050000 0x00 0x05050000 0x10000>, + <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ + + status = "disabled"; + + serdes4: serdes@5050000 { + /* + * Note: we also map DPTX PHY registers as the Torrent + * needs to manage those. + */ + compatible = "ti,j721e-serdes-10g"; + reg = <0x05050000 0x010000>, + <0x0a030a00 0x40>; /* DPTX PHY */ + reg-names = "torrent_phy"; + resets = <&serdes_wiz4 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 407 6>, + <&k3_clks 407 6>, + <&k3_clks 407 6>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; + }; + }; + + main_navss: bus@30000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; + ti,sci-dev-id = <280>; + dma-coherent; + dma-ranges; + + main_navss_sram: navss-sram@30000000{ + compatible = "mmio-sram"; + reg = <0x00 0x30000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x30000000 0x10000>; + }; + + main_navss_intr: interrupt-controller@310e0000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x310e0000 0x00 0x4000>; + ti,intr-trigger-type = <4>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&sms>; + ti,sci-dev-id = <283>; + ti,interrupt-ranges = <0 64 64>, + <64 448 64>, + <128 672 64>; + }; + + main_udmass_inta: msi-controller@33d00000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x33d00000 0x00 0x100000>; + interrupt-controller; + #interrupt-cells = <0>; + interrupt-parent = <&main_navss_intr>; + msi-controller; + ti,sci = <&sms>; + ti,sci-dev-id = <321>; + ti,interrupt-ranges = <0 0 256>; + ti,unmapped-event-sources = <&main_bcdma_csi>; + }; + + secure_proxy_main: mailbox@32c00000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x32c00000 0x00 0x100000>, + <0x00 0x32400000 0x00 0x100000>, + <0x00 0x32800000 0x00 0x100000>; + interrupt-names = "rx_011"; + interrupts = ; + }; + + hwspinlock: hwlock@30e00000 { + compatible = "ti,am654-hwspinlock"; + reg = <0x00 0x30e00000 0x00 0x1000>; + #hwlock-cells = <1>; + }; + + mailbox0_cluster0: mailbox@31f80000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f80000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox0_cluster1: mailbox@31f81000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f81000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox0_cluster2: mailbox@31f82000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f82000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox0_cluster3: mailbox@31f83000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f83000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox0_cluster4: mailbox@31f84000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f84000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox0_cluster5: mailbox@31f85000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f85000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox0_cluster6: mailbox@31f86000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f86000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox0_cluster7: mailbox@31f87000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f87000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox0_cluster8: mailbox@31f88000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f88000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox0_cluster9: mailbox@31f89000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f89000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox0_cluster10: mailbox@31f8a000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8a000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox0_cluster11: mailbox@31f8b000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8b000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox1_cluster0: mailbox@31f90000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f90000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox1_cluster1: mailbox@31f91000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f91000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox1_cluster2: mailbox@31f92000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f92000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox1_cluster3: mailbox@31f93000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f93000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox1_cluster4: mailbox@31f94000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f94000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox1_cluster5: mailbox@31f95000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f95000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox1_cluster6: mailbox@31f96000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f96000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox1_cluster7: mailbox@31f97000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f97000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox1_cluster8: mailbox@31f98000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f98000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox1_cluster9: mailbox@31f99000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f99000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox1_cluster10: mailbox@31f9a000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f9a000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + mailbox1_cluster11: mailbox@31f9b000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f9b000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + status = "disabled"; + }; + + main_ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x00 0x3c000000 0x00 0x400000>, + <0x00 0x38000000 0x00 0x400000>, + <0x00 0x31120000 0x00 0x100>, + <0x00 0x33000000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <1024>; + ti,sci-rm-range-gp-rings = <0x1>; + ti,sci = <&sms>; + ti,sci-dev-id = <315>; + msi-parent = <&main_udmass_inta>; + }; + + main_udmap: dma-controller@31150000 { + compatible = "ti,j721e-navss-main-udmap"; + reg = <0x00 0x31150000 0x00 0x100>, + <0x00 0x34000000 0x00 0x80000>, + <0x00 0x35000000 0x00 0x200000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&sms>; + ti,sci-dev-id = <319>; + ti,ringacc = <&main_ringacc>; + + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>, /* TX_HCHAN */ + <0x10>; /* TX_UHCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>, /* RX_HCHAN */ + <0x0c>; /* RX_UHCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; + + main_bcdma_csi: dma-controller@311a0000 { + compatible = "ti,j721s2-dmss-bcdma-csi"; + reg = <0x00 0x311a0000 0x00 0x100>, + <0x00 0x35d00000 0x00 0x20000>, + <0x00 0x35c00000 0x00 0x10000>, + <0x00 0x35e00000 0x00 0x80000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <3>; + ti,sci = <&sms>; + ti,sci-dev-id = <281>; + ti,sci-rm-range-rchan = <0x21>; + ti,sci-rm-range-tchan = <0x22>; + }; + + cpts@310d0000 { + compatible = "ti,j721e-cpts"; + reg = <0x00 0x310d0000 0x00 0x400>; + reg-names = "cpts"; + clocks = <&k3_clks 282 0>; + clock-names = "cpts"; + assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */ + assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */ + interrupts-extended = <&main_navss_intr 391>; + interrupt-names = "cpts"; + ti,cpts-periodic-outputs = <6>; + ti,cpts-ext-ts-inputs = <8>; + }; + }; + + main_cpsw0: ethernet@c000000 { + compatible = "ti,j784s4-cpswxg-nuss"; + reg = <0x00 0xc000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; + dma-coherent; + clocks = <&k3_clks 64 0>; + clock-names = "fck"; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw0_port1: port@1 { + reg = <1>; + label = "port1"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port2: port@2 { + reg = <2>; + label = "port2"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port3: port@3 { + reg = <3>; + label = "port3"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port4: port@4 { + reg = <4>; + label = "port4"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port5: port@5 { + reg = <5>; + label = "port5"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port6: port@6 { + reg = <6>; + label = "port6"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port7: port@7 { + reg = <7>; + label = "port7"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port8: port@8 { + reg = <8>; + label = "port8"; + ti,mac-only; + status = "disabled"; + }; + }; + + main_cpsw0_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 64 0>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 64 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + + main_cpsw1: ethernet@c200000 { + compatible = "ti,j721e-cpsw-nuss"; + reg = <0x00 0xc200000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + dma-coherent; + clocks = <&k3_clks 62 0>; + clock-names = "fck"; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xc640>, + <&main_udmap 0xc641>, + <&main_udmap 0xc642>, + <&main_udmap 0xc643>, + <&main_udmap 0xc644>, + <&main_udmap 0xc645>, + <&main_udmap 0xc646>, + <&main_udmap 0xc647>, + <&main_udmap 0x4640>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw1_port1: port@1 { + reg = <1>; + label = "port1"; + phys = <&cpsw1_phy_gmii_sel 1>; + ti,mac-only; + status = "disabled"; + }; + }; + + main_cpsw1_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 62 0>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 62 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + + pcie0_rc: pcie@2900000 { + compatible = "ti,j784s4-pcie-host"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 332 0>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 0>, + <0 0 0 3 &pcie0_intc 0>, + <0 0 0 4 &pcie0_intc 0>; + status = "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; + }; + + pcie0_ep: pcie-ep@2900000 { + compatible = "ti,j784s4-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 332 0>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + status = "disabled"; + }; + + pcie1_rc: pcie@2910000 { + compatible = "ti,j784s4-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + ti,syscon-pcie-refclk-out = <&scm_conf 0x9008 0x900c 0x18090 0x8074 0x1>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 333 0>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb013>; + msi-map = <0x0 &gic_its 0x10000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 0>, + <0 0 0 3 &pcie1_intc 0>, + <0 0 0 4 &pcie1_intc 0>; + status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j784s4-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 333 0>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + status = "disabled"; + }; + + pcie3_rc: pcie@2930000 { + compatible = "ti,j784s4-pcie-host"; + reg = <0x00 0x02930000 0x00 0x1000>, + <0x00 0x02937000 0x00 0x400>, + <0x00 0x0e800000 0x00 0x00800000>, + <0x44 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 335 0>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x30000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 0>, + <0 0 0 3 &pcie3_intc 0>, + <0 0 0 4 &pcie3_intc 0>; + status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = ; + }; + }; + + pcie3_ep: pcie-ep@2930000 { + compatible = "ti,j784s4-pcie-ep"; + reg = <0x00 0x02930000 0x00 0x1000>, + <0x00 0x02937000 0x00 0x400>, + <0x00 0x0e800000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 335 0>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + status = "disabled"; + }; + + main_mcan0: can@2701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02701000 0x00 0x200>, + <0x00 0x02708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 245 6>, <&k3_clks 245 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan1: can@2711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02711000 0x00 0x200>, + <0x00 0x02718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 246 6>, <&k3_clks 246 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan2: can@2721000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02721000 0x00 0x200>, + <0x00 0x02728000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 247 6>, <&k3_clks 247 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan3: can@2731000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02731000 0x00 0x200>, + <0x00 0x02738000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 248 6>, <&k3_clks 248 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan4: can@2741000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02741000 0x00 0x200>, + <0x00 0x02748000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 249 6>, <&k3_clks 249 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan5: can@2751000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02751000 0x00 0x200>, + <0x00 0x02758000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 250 6>, <&k3_clks 250 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan6: can@2761000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02761000 0x00 0x200>, + <0x00 0x02768000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 251 6>, <&k3_clks 251 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan7: can@2771000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02771000 0x00 0x200>, + <0x00 0x02778000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 252 6>, <&k3_clks 252 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan8: can@2781000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02781000 0x00 0x200>, + <0x00 0x02788000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 253 6>, <&k3_clks 253 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan9: can@2791000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02791000 0x00 0x200>, + <0x00 0x02798000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 254 6>, <&k3_clks 254 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan10: can@27a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027a1000 0x00 0x200>, + <0x00 0x027a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 255 6>, <&k3_clks 255 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan11: can@27b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027b1000 0x00 0x200>, + <0x00 0x027b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 256 6>, <&k3_clks 256 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan12: can@27c1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027c1000 0x00 0x200>, + <0x00 0x027c8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 257 6>, <&k3_clks 257 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan13: can@27d1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027d1000 0x00 0x200>, + <0x00 0x027d8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 258 6>, <&k3_clks 258 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan14: can@2681000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02681000 0x00 0x200>, + <0x00 0x02688000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 259 6>, <&k3_clks 259 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan15: can@2691000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02691000 0x00 0x200>, + <0x00 0x02698000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 260 6>, <&k3_clks 260 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan16: can@26a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x026a1000 0x00 0x200>, + <0x00 0x026a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 261 6>, <&k3_clks 261 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan17: can@26b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x026b1000 0x00 0x200>, + <0x00 0x026b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 262 6>, <&k3_clks 262 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_spi0: spi@2100000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 376 1>; + status = "disabled"; + }; + + main_spi1: spi@2110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 377 1>; + status = "disabled"; + }; + + main_spi2: spi@2120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 378 1>; + status = "disabled"; + }; + + main_spi3: spi@2130000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02130000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 379 1>; + status = "disabled"; + }; + + main_spi4: spi@2140000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02140000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 380 1>; + status = "disabled"; + }; + + main_spi5: spi@2150000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02150000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 381 1>; + status = "disabled"; + }; + + main_spi6: spi@2160000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02160000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 382 1>; + status = "disabled"; + }; + + main_spi7: spi@2170000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02170000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 383 1>; + status = "disabled"; + }; + + dphy_tx0: phy@4480000 { + compatible = "ti,j721e-dphy"; + reg = <0x0 0x04480000 0x0 0x1000>; + clocks = <&k3_clks 402 20>, <&k3_clks 402 3>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 402 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 402 3>; + assigned-clock-parents = <&k3_clks 402 4>; + assigned-clock-rates = <19200000>; + status = "disabled"; + }; + + dsi0: dsi@4800000 { + compatible = "ti,j721e-dsi"; + reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>; + clocks = <&k3_clks 215 2>, <&k3_clks 215 5>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; + interrupt-parent = <&gic500>; + interrupts = ; + phys = <&dphy_tx0>; + phy-names = "dphy"; + status = "disabled"; + + dsi0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + }; + }; + + timesync_router: pinctrl@a40000 { + compatible = "pinctrl-single"; + reg = <0x0 0xa40000 0x0 0x800>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000107ff>; + status = "disabled"; + }; + + mhdp: dp-bridge@a000000 { + compatible = "ti,j721e-mhdp8546"; + + reg = <0x0 0xa000000 0x0 0x30a00>, + <0x0 0x4f40000 0x0 0x20>; + reg-names = "mhdptx", "j721e-intg"; + + clocks = <&k3_clks 217 11>; + + interrupt-parent = <&gic500>; + interrupts = ; + + power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; + + status = "disabled"; + + dp0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + dss: dss@4a00000 { + compatible = "ti,j721e-dss"; + reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ + <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ + <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ + <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ + <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ + <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ + <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ + <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ + <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ + <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ + <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ + <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ + <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ + <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */ + <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */ + <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ + <0x00 0x04af0000 0x00 0x10000>; /* wb */ + + reg-names = "common_m", "common_s0", + "common_s1", "common_s2", + "vidl1", "vidl2","vid1","vid2", + "ovr1", "ovr2", "ovr3", "ovr4", + "vp1", "vp2", "vp3", "vp4", + "wb"; + + clocks = <&k3_clks 218 0>, + <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; + + power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; + + interrupts = , + , + , + ; + interrupt-names = "common_m", + "common_s0", + "common_s1", + "common_s2"; + + status = "disabled"; + + dss_ports: ports { + }; + }; + + ti_csi2rx0: ticsi2rx@4500000 { + status = "disabled"; + compatible = "ti,j721e-csi2rx"; + dmas = <&main_bcdma_csi 0 0x4940 0>, <&main_bcdma_csi 0 0x4941 0>, + <&main_bcdma_csi 0 0x4942 0>, <&main_bcdma_csi 0 0x4943 0>, + <&main_bcdma_csi 0 0x4944 0>, <&main_bcdma_csi 0 0x4945 0>, + <&main_bcdma_csi 0 0x4946 0>, <&main_bcdma_csi 0 0x4947 0>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7"; + reg = <0x00 0x04500000 0x00 0x00001000>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "cdns,csi2rx"; + reg = <0x00 0x04504000 0x00 0x00001000>; + clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, + <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy_rx0>; + phy-names = "dphy"; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + status = "disabled"; + compatible = "ti,j721e-csi2rx"; + dmas = <&main_bcdma_csi 0 0x4960 0>, <&main_bcdma_csi 0 0x4961 0>, + <&main_bcdma_csi 0 0x4962 0>, <&main_bcdma_csi 0 0x4963 0>, + <&main_bcdma_csi 0 0x4964 0>, <&main_bcdma_csi 0 0x4965 0>, + <&main_bcdma_csi 0 0x4966 0>, <&main_bcdma_csi 0 0x4967 0>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7"; + reg = <0x00 0x04510000 0x00 0x00001000>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "cdns,csi2rx"; + reg = <0x00 0x04514000 0x00 0x00001000>; + clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, + <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy_rx1>; + phy-names = "dphy"; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@4520000 { + status = "disabled"; + compatible = "ti,j721e-csi2rx"; + dmas = <&main_bcdma_csi 0 0x4980 0>, <&main_bcdma_csi 0 0x4981 0>, + <&main_bcdma_csi 0 0x4982 0>, <&main_bcdma_csi 0 0x4983 0>, + <&main_bcdma_csi 0 0x4984 0>, <&main_bcdma_csi 0 0x4985 0>, + <&main_bcdma_csi 0 0x4986 0>, <&main_bcdma_csi 0 0x4987 0>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7"; + reg = <0x00 0x04520000 0x00 0x00001000>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cdns_csi2rx2: csi-bridge@4524000 { + compatible = "cdns,csi2rx"; + reg = <0x00 0x04524000 0x00 0x00001000>; + clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, + <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy_rx2>; + phy-names = "dphy"; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi2_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi2_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi2_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi2_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy_rx0: phy@4580000 { + status = "disabled"; + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04580000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; + }; + + dphy_rx1: phy@4590000 { + status = "disabled"; + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04590000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; + }; + + dphy_rx2: phy@45a0000 { + status = "disabled"; + compatible = "cdns,dphy-rx"; + reg = <0x00 0x045a0000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; + }; + + ufs_wrapper: ufs-wrapper@4e80000 { + compatible = "ti,j721e-ufs"; + reg = <0x00 0x4e80000 0x00 0x100>; + power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 387 3>; + assigned-clocks = <&k3_clks 387 3>; + assigned-clock-parents = <&k3_clks 387 6>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + ufs@4e84000 { + compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; + reg = <0x00 0x4e84000 0x00 0x10000>; + interrupts = ; + freq-table-hz = <250000000 250000000>, <19200000 19200000>, + <19200000 19200000>; + clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>; + clock-names = "core_clk", "phy_clk", "ref_clk"; + dma-coherent; + }; + }; + + main_r5fss0: r5fss@5c00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c00000 0x00 0x5c00000 0x20000>, + <0x5d00000 0x00 0x5d00000 0x20000>; + power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss0_core0: r5f@5c00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5c00000 0x00010000>, + <0x5c10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <339>; + ti,sci-proc-ids = <0x06 0xff>; + resets = <&k3_reset 339 1>; + firmware-name = "j784s4-main-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss0_core1: r5f@5d00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5d00000 0x00010000>, + <0x5d10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <340>; + ti,sci-proc-ids = <0x07 0xff>; + resets = <&k3_reset 340 1>; + firmware-name = "j784s4-main-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss1: r5fss@5e00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5e00000 0x00 0x5e00000 0x20000>, + <0x5f00000 0x00 0x5f00000 0x20000>; + power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss1_core0: r5f@5e00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5e00000 0x00010000>, + <0x5e10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <341>; + ti,sci-proc-ids = <0x08 0xff>; + resets = <&k3_reset 341 1>; + firmware-name = "j784s4-main-r5f1_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss1_core1: r5f@5f00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5f00000 0x00010000>, + <0x5f10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <342>; + ti,sci-proc-ids = <0x09 0xff>; + resets = <&k3_reset 342 1>; + firmware-name = "j784s4-main-r5f1_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss2: r5fss@5900000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5900000 0x00 0x5900000 0x20000>, + <0x5a00000 0x00 0x5a00000 0x20000>; + power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss2_core0: r5f@5900000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5900000 0x00010000>, + <0x5910000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <343>; + ti,sci-proc-ids = <0x0a 0xff>; + resets = <&k3_reset 343 1>; + firmware-name = "j784s4-main-r5f2_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss2_core1: r5f@5a00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5a00000 0x00010000>, + <0x5a10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <344>; + ti,sci-proc-ids = <0x0b 0xff>; + resets = <&k3_reset 344 1>; + firmware-name = "j784s4-main-r5f2_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + c71_0: dsp@64800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x64800000 0x00 0x00080000>, + <0x00 0x64e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <30>; + ti,sci-proc-ids = <0x30 0xff>; + resets = <&k3_reset 30 1>; + firmware-name = "j784s4-c71_0-fw"; + }; + + c71_1: dsp@65800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x65800000 0x00 0x00080000>, + <0x00 0x65e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <33>; + ti,sci-proc-ids = <0x31 0xff>; + resets = <&k3_reset 33 1>; + firmware-name = "j784s4-c71_1-fw"; + }; + + c71_2: dsp@66800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x66800000 0x00 0x00080000>, + <0x00 0x66e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <37>; + ti,sci-proc-ids = <0x32 0xff>; + resets = <&k3_reset 37 1>; + firmware-name = "j784s4-c71_2-fw"; + }; + + c71_3: dsp@67800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x67800000 0x00 0x00080000>, + <0x00 0x67e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <40>; + ti,sci-proc-ids = <0x33 0xff>; + resets = <&k3_reset 40 1>; + firmware-name = "j784s4-c71_3-fw"; + }; + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x700000 0x00 0x1000>; + ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>, + <695>; + bootph-pre-ram; + }; + + watchdog0: watchdog@2200000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2200000 0x00 0x100>; + clocks = <&k3_clks 348 1>; + power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 348 0>; + assigned-clock-parents = <&k3_clks 348 4>; + }; + + watchdog1: watchdog@2210000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2210000 0x00 0x100>; + clocks = <&k3_clks 349 1>; + power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 349 0>; + assigned-clock-parents = <&k3_clks 349 4>; + }; + + watchdog2: watchdog@2220000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2220000 0x00 0x100>; + clocks = <&k3_clks 350 1>; + power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 350 0>; + assigned-clock-parents = <&k3_clks 350 4>; + }; + + watchdog3: watchdog@2230000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2230000 0x00 0x100>; + clocks = <&k3_clks 351 1>; + power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 351 0>; + assigned-clock-parents = <&k3_clks 351 4>; + }; + + watchdog4: watchdog@2240000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2240000 0x00 0x100>; + clocks = <&k3_clks 352 1>; + power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 352 0>; + assigned-clock-parents = <&k3_clks 352 4>; + }; + + watchdog5: watchdog@2250000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2250000 0x00 0x100>; + clocks = <&k3_clks 353 1>; + power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 353 0>; + assigned-clock-parents = <&k3_clks 353 4>; + }; + + watchdog6: watchdog@2260000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2260000 0x00 0x100>; + clocks = <&k3_clks 354 1>; + power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 354 0>; + assigned-clock-parents = <&k3_clks 354 4>; + }; + + watchdog7: watchdog@2270000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2270000 0x00 0x100>; + clocks = <&k3_clks 355 1>; + power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 355 0>; + assigned-clock-parents = <&k3_clks 355 4>; + }; + + /* + * The following RTI instances are coupled with MCU R5Fs, c7x and + * GPU so keeping them reserved as these will be used by their + * respective firmware + */ + watchdog8: watchdog@22f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x22f0000 0x00 0x100>; + clocks = <&k3_clks 360 1>; + power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 360 0>; + assigned-clock-parents = <&k3_clks 360 4>; + /* reserved for GPU */ + status = "reserved"; + }; + + watchdog9: watchdog@2300000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2300000 0x00 0x100>; + clocks = <&k3_clks 356 1>; + power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 356 0>; + assigned-clock-parents = <&k3_clks 356 4>; + /* reserved for C7X_0 DSP */ + status = "reserved"; + }; + + watchdog10: watchdog@2310000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2310000 0x00 0x100>; + clocks = <&k3_clks 357 1>; + power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 357 0>; + assigned-clock-parents = <&k3_clks 357 4>; + /* reserved for C7X_1 DSP */ + status = "reserved"; + }; + + watchdog11: watchdog@2320000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2320000 0x00 0x100>; + clocks = <&k3_clks 358 1>; + power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 358 0>; + assigned-clock-parents = <&k3_clks 358 4>; + /* reserved for C7X_2 DSP */ + status = "reserved"; + }; + + watchdog12: watchdog@2330000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2330000 0x00 0x100>; + clocks = <&k3_clks 359 1>; + power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 359 0>; + assigned-clock-parents = <&k3_clks 359 4>; + /* reserved for C7X_3 DSP */ + status = "reserved"; + }; + + watchdog13: watchdog@23c0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23c0000 0x00 0x100>; + clocks = <&k3_clks 361 1>; + power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 361 0>; + assigned-clock-parents = <&k3_clks 361 4>; + /* reserved for MAIN_R5F0_0 */ + status = "reserved"; + }; + + watchdog14: watchdog@23d0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23d0000 0x00 0x100>; + clocks = <&k3_clks 362 1>; + power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 362 0>; + assigned-clock-parents = <&k3_clks 362 4>; + /* reserved for MAIN_R5F0_1 */ + status = "reserved"; + }; + + watchdog15: watchdog@23e0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23e0000 0x00 0x100>; + clocks = <&k3_clks 363 1>; + power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 363 0>; + assigned-clock-parents = <&k3_clks 363 4>; + /* reserved for MAIN_R5F1_0 */ + status = "reserved"; + }; + + watchdog16: watchdog@23f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23f0000 0x00 0x100>; + clocks = <&k3_clks 364 1>; + power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 364 0>; + assigned-clock-parents = <&k3_clks 364 4>; + /* reserved for MAIN_R5F1_1 */ + status = "reserved"; + }; + + watchdog17: watchdog@2540000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2540000 0x00 0x100>; + clocks = <&k3_clks 365 1>; + power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 365 0>; + assigned-clock-parents = <&k3_clks 366 4>; + /* reserved for MAIN_R5F2_0 */ + status = "reserved"; + }; + + watchdog18: watchdog@2550000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2550000 0x00 0x100>; + clocks = <&k3_clks 366 1>; + power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 366 0>; + assigned-clock-parents = <&k3_clks 366 4>; + /* reserved for MAIN_R5F2_1 */ + status = "reserved"; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -0,0 +1,542 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu_wakeup { + sms: system-controller@44083000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + + mbox-names = "rx", "tx"; + + mboxes = <&secure_proxy_main 11>, + <&secure_proxy_main 13>; + + reg-names = "debug_messages"; + reg = <0x00 0x44083000 0x00 0x1000>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + + k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + chipid@43000014 { + compatible = "ti,am654-chipid"; + reg = <0x00 0x43000014 0x00 0x4>; + }; + + mcu_ram: sram@41c00000 { + compatible = "mmio-sram"; + reg = <0x00 0x41c00000 0x00 0x100000>; + ranges = <0x00 0x00 0x41c00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + wkup_pmx0: pinctrl@4301c000 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c000 0x00 0x034>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx1: pinctrl@4301c038 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c038 0x00 0x02c>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx2: pinctrl@4301c068 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c068 0x00 0x120>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx3: pinctrl@4301c190 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c190 0x00 0x004>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_gpio_intr: interrupt-controller@42200000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x42200000 0x00 0x400>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&sms>; + ti,sci-dev-id = <177>; + ti,interrupt-ranges = <16 960 16>; + }; + + mcu_conf: syscon@40f00000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x40f00000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x40f00000 0x20000>; + + phy_gmii_sel: phy@4040 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4040 0x4>; + #phy-cells = <1>; + }; + }; + + wkup_uart0: serial@42300000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x42300000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 397 0>; + clock-names = "fclk"; + power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcu_uart0: serial@40a00000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x40a00000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 149 0>; + clock-names = "fclk"; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + wkup_gpio0: gpio@42110000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x42110000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&wkup_gpio_intr>; + interrupts = <103>, <104>, <105>, <106>, <107>, <108>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <89>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 167 0>; + clock-names = "gpio"; + status = "disabled"; + }; + + wkup_gpio1: gpio@42100000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x42100000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&wkup_gpio_intr>; + interrupts = <112>, <113>, <114>, <115>, <116>, <117>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <89>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 168 0>; + clock-names = "gpio"; + status = "disabled"; + }; + + wkup_i2c0: i2c@42120000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x42120000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 279 2>; + clock-names = "fck"; + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcu_i2c0: i2c@40b00000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x40b00000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 277 2>; + clock-names = "fck"; + power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcu_i2c1: i2c@40b10000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x40b10000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 278 2>; + clock-names = "fck"; + power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcu_mcan0: can@40528000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40528000 0x00 0x200>, + <0x00 0x40500000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 263 6>, <&k3_clks 263 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcu_mcan1: can@40568000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40568000 0x00 0x200>, + <0x00 0x40540000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 264 6>, <&k3_clks 264 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcu_spi0: spi@40300000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040300000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 384 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 384 0>; + status = "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040310000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 385 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 385 0>; + status = "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040320000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 386 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 386 0>; + status = "disabled"; + }; + + mcu_navss: bus@28380000{ + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; + ti,sci-dev-id = <323>; + dma-coherent; + dma-ranges; + + mcu_ringacc: ringacc@2b800000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x00 0x2b800000 0x00 0x400000>, + <0x00 0x2b000000 0x00 0x400000>, + <0x00 0x28590000 0x00 0x100>, + <0x00 0x2a500000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <286>; + ti,sci-rm-range-gp-rings = <0x1>; + ti,sci = <&sms>; + ti,sci-dev-id = <328>; + msi-parent = <&main_udmass_inta>; + }; + + mcu_udmap: dma-controller@285c0000 { + compatible = "ti,j721e-navss-mcu-udmap"; + reg = <0x00 0x285c0000 0x00 0x100>, + <0x00 0x2a800000 0x00 0x40000>, + <0x00 0x2aa00000 0x00 0x40000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&sms>; + ti,sci-dev-id = <329>; + ti,ringacc = <&mcu_ringacc>; + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>; /* TX_HCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>; /* RX_HCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; + }; + + mcu_cpsw: ethernet@46000000 { + compatible = "ti,j721e-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0x46000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; + dma-coherent; + clocks = <&k3_clks 63 0>; + clock-names = "fck"; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&mcu_udmap 0xf000>, + <&mcu_udmap 0xf001>, + <&mcu_udmap 0xf002>, + <&mcu_udmap 0xf003>, + <&mcu_udmap 0xf004>, + <&mcu_udmap 0xf005>, + <&mcu_udmap 0xf006>, + <&mcu_udmap 0xf007>, + <&mcu_udmap 0x7000>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + mcu_cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + ti,syscon-efuse = <&mcu_conf 0x200>; + phys = <&phy_gmii_sel 1>; + }; + }; + + davinci_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 63 0>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 63 3>; + clock-names = "cpts"; + assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */ + assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */ + interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + + fss: bus@47000000 { + compatible = "simple-bus"; + reg = <0x00 0x47000000 0x00 0x100>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ospi0: spi@47040000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47040000 0x00 0x100>, + <0x05 0x0000000 0x01 0x0000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 161 7>; + assigned-clocks = <&k3_clks 161 7>; + assigned-clock-parents = <&k3_clks 161 9>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ospi1: spi@47050000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47050000 0x00 0x100>, + <0x07 0x0000000 0x01 0x0000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 162 7>; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j7200-vtm"; + reg = <0x0 0x42040000 0x0 0x350>, + <0x0 0x42050000 0x0 0x350>, + <0x0 0x43000300 0x0 0x10>; + power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>; + #thermal-sensor-cells = <1>; + }; + + tscadc0: tscadc@40200000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40200000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 0 0>; + assigned-clocks = <&k3_clks 0 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&main_udmap 0x7400>, + <&main_udmap 0x7401>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + + tscadc1: tscadc@40210000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40210000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 1 0>; + assigned-clocks = <&k3_clks 1 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&main_udmap 0x7402>, + <&main_udmap 0x7403>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41000000 0x00010000>, + <0x41010000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <346>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 346 1>; + firmware-name = "j784s4-mcu-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41400000 0x00010000>, + <0x41410000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <347>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 347 1>; + firmware-name = "j784s4-mcu-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + mcu_esm: esm@40800000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x40800000 0x00 0x1000>; + ti,esm-pins = <95>; + bootph-pre-ram; + }; + + wkup_esm: esm@42080000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x42080000 0x00 0x1000>; + ti,esm-pins = <63>; + bootph-pre-ram; + }; + + /* + * The 2 RTI instances are couple with MCU R5Fs so keeping them + * reserved as these will be used by their respective firmware + */ + mcu_watchdog0: watchdog@40600000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x40600000 0x00 0x100>; + clocks = <&k3_clks 367 1>; + power-domains = <&k3_pds 367 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 367 0>; + assigned-clock-parents = <&k3_clks 367 4>; + /* reserved for MCU_R5F0_0 */ + status = "reserved"; + }; + + mcu_watchdog1: watchdog@40610000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x40610000 0x00 0x100>; + clocks = <&k3_clks 368 1>; + power-domains = <&k3_pds 368 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 368 0>; + assigned-clock-parents = <&k3_clks 368 4>; + /* reserved for MCU_R5F0_1 */ + status = "reserved"; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +wkup0_thermal: wkup0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup0_crit: wkup0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +wkup1_thermal: wkup1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + wkup1_crit: wkup1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 3>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 4>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main3_thermal: main3-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 5>; + + trips { + main3_crit: main3-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main4_thermal: main4-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 6>; + + trips { + main4_crit: main4-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4.dtsi =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J784S4 SoC Family + * + * TRM (SPRUJ43 JULY 2022) : http://www.ti.com/lit/zip/spruj52 + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#include +#include +#include + +#include "k3-pinctrl.h" + +/ { + model = "Texas Instruments K3 J784S4 SoC"; + compatible = "ti,j784s4"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a72"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a72"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a72"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a72"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + + cpu4: cpu@100 { + compatible = "arm,cortex-a72"; + reg = <0x100>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_1>; + }; + + cpu5: cpu@101 { + compatible = "arm,cortex-a72"; + reg = <0x101>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_1>; + }; + + cpu6: cpu@102 { + compatible = "arm,cortex-a72"; + reg = <0x102>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_1>; + }; + + cpu7: cpu@103 { + compatible = "arm,cortex-a72"; + reg = <0x103>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_1>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <1024>; + next-level-cache = <&msmc_l3>; + }; + + L2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <1024>; + next-level-cache = <&msmc_l3>; + }; + + msmc_l3: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a72_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a72-pmu"; + /* Recommendation from GIC500 TRM Table A.3 */ + interrupts = ; + }; + + cbass_main: bus@100000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Time Sync Router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe1 Core*/ + <0x00 0x0e800000 0x00 0x0e800000 0x00 0x01000000>, /* PCIe3 Core*/ + <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */ + <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ + <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */ + <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */ + <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ + <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ + <0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */ + <0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */ + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ + <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ + <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ + <0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */ + <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ + + /* MCUSS_WKUP Range */ + <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + cbass_mcu_wakeup: bus@28380000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ + }; + }; + + thermal_zones: thermal-zones { + #include "k3-j784s4-thermal.dtsi" + }; +}; + +/* Now include peripherals from each bus segment */ +#include "k3-j784s4-main.dtsi" +#include "k3-j784s4-mcu-wakeup.dtsi" Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-pinctrl.h =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for pinctrl bindings for TI's K3 SoC + * family. + * + * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ +#ifndef DTS_ARM64_TI_K3_PINCTRL_H +#define DTS_ARM64_TI_K3_PINCTRL_H + +#define PULLUDEN_SHIFT (16) +#define PULLTYPESEL_SHIFT (17) +#define RXACTIVE_SHIFT (18) +#define DEBOUNCE_SHIFT (11) +#define WKUP_EN_SHIFT (29) + +#define PULL_DISABLE (1 << PULLUDEN_SHIFT) +#define PULL_ENABLE (0 << PULLUDEN_SHIFT) + +#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) +#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) + +#define INPUT_EN (1 << RXACTIVE_SHIFT) +#define INPUT_DISABLE (0 << RXACTIVE_SHIFT) + +/* Only these macros are expected be used directly in device tree files */ +#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) +#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) + +#define PIN_DEBOUNCE_DISABLE (0 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF1 (1 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF2 (2 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF3 (3 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF4 (4 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) + +#define WKUP_EN (1 << WKUP_EN_SHIFT) + +#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define J722S_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J722S_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#endif Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-0.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-0.dtso @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX219 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_00: imx219-xclk-00 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&ds90ub960_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 0 */ + port@0 { + reg = <0>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@0 { + reg = <0>; + i2c-alias = <0x44>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed_00>; + clock-names = "xclk"; + reset-gpios = <&serializer 1 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-1.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-1.dtso @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX219 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_01: imx219-xclk-01 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&ds90ub960_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 1 */ + port@1 { + reg = <1>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@1 { + reg = <1>; + i2c-alias = <0x45>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed_01>; + clock-names = "xclk"; + reset-gpios = <&serializer 1 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-2.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-2.dtso @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX219 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_02: imx219-xclk-02 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&ds90ub960_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 2 */ + port@2 { + reg = <2>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@2 { + reg = <2>; + i2c-alias = <0x46>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed_02>; + clock-names = "xclk"; + reset-gpios = <&serializer 1 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-3.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/ti/k3-v3link-imx219-0-3.dtso @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX219 Camera Module for V3-Link d-ch Adapter Board + * https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/ + * + * Copyright (c) 2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed_03: imx219-xclk-03 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&ds90ub960_0_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* FPDLink RX 3 */ + port@3 { + reg = <3>; + + ub960_fpd3_1_in: endpoint { + remote-endpoint = <&ub953_1_out>; + }; + }; +}; + +&ds90ub960_0_links { + #address-cells = <1>; + #size-cells = <0>; + + link@3 { + reg = <3>; + i2c-alias = <0x47>; + + ti,rx-mode = <3>; + + serializer: serializer { + compatible = "ti,ds90ub953-q1"; + gpio-controller; + #gpio-cells = <2>; + + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ub953_1_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&sensor_1_out>; + }; + }; + + port@1 { + reg = <1>; + + ub953_1_out: endpoint { + remote-endpoint = <&ub960_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed_03>; + clock-names = "xclk"; + reset-gpios = <&serializer 1 GPIO_ACTIVE_HIGH>; + + port { + sensor_1_out: endpoint { + remote-endpoint = <&ub953_1_in>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; + }; +}; Index: linux-6.1.80/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dts +++ /dev/null @@ -1,315 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for KV260 revA Carrier Card - * - * (C) Copyright 2020 - 2021, Xilinx, Inc. - * - * SD level shifter: - * "A" – A01 board un-modified (NXP) - * "Y" – A01 board modified with legacy interposer (Nexperia) - * "Z" – A01 board modified with Diode interposer - * - * Michal Simek - */ - -#include -#include -#include -#include - -/dts-v1/; -/plugin/; - -&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; - - /* u14 - 0x40 - ina260 */ - /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ -}; - -&amba { - si5332_0: si5332_0 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - si5332_1: si5332_1 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - si5332_2: si5332_2 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - si5332_3: si5332_3 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - si5332_4: si5332_4 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - si5332_5: si5332_5 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; -}; - -/* DP/USB 3.0 and SATA */ -&psgtr { - status = "okay"; - /* pcie, usb3, sata */ - clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; - clock-names = "ref0", "ref1", "ref2"; -}; - -&sata { - status = "okay"; - /* SATA OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - phy-names = "sata-phy"; - phys = <&psgtr 3 PHY_TYPE_SATA 1 2>; -}; - -&zynqmp_dpsub { - status = "disabled"; - phy-names = "dp-phy0", "dp-phy1"; - phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; -}; - -&zynqmp_dpdma { - status = "okay"; -}; - -&usb0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; - phy-names = "usb3-phy"; - phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; - /* missing usb5744 - u43 */ -}; - -&dwc3_0 { - status = "okay"; - dr_mode = "host"; - snps,usb3_lpm_capable; - maximum-speed = "super-speed"; -}; - -&sdhci1 { /* on CC with tuned parameters */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1_default>; - /* - * SD 3.0 requires level shifter and this property - * should be removed if the board has level shifter and - * need to work in UHS mode - */ - no-1-8-v; - disable-wp; - xlnx,mio-bank = <1>; -}; - -&gem3 { /* required by spec */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gem3_default>; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; - - phy0: ethernet-phy@1 { - #phy-cells = <1>; - reg = <1>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,dp83867-rxctrl-strap-quirk; - }; - }; -}; - -&pinctrl0 { /* required by spec */ - status = "okay"; - - pinctrl_uart1_default: uart1-default { - conf { - groups = "uart1_9_grp"; - slew-rate = ; - power-source = ; - drive-strength = <12>; - }; - - conf-rx { - pins = "MIO37"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO36"; - bias-disable; - }; - - mux { - groups = "uart1_9_grp"; - function = "uart1"; - }; - }; - - pinctrl_i2c1_default: i2c1-default { - conf { - groups = "i2c1_6_grp"; - bias-pull-up; - slew-rate = ; - power-source = ; - }; - - mux { - groups = "i2c1_6_grp"; - function = "i2c1"; - }; - }; - - pinctrl_i2c1_gpio: i2c1-gpio { - conf { - groups = "gpio0_24_grp", "gpio0_25_grp"; - slew-rate = ; - power-source = ; - }; - - mux { - groups = "gpio0_24_grp", "gpio0_25_grp"; - function = "gpio0"; - }; - }; - - pinctrl_gem3_default: gem3-default { - conf { - groups = "ethernet3_0_grp"; - slew-rate = ; - power-source = ; - }; - - conf-rx { - pins = "MIO70", "MIO72", "MIO74"; - bias-high-impedance; - low-power-disable; - }; - - conf-bootstrap { - pins = "MIO71", "MIO73", "MIO75"; - bias-disable; - low-power-disable; - }; - - conf-tx { - pins = "MIO64", "MIO65", "MIO66", - "MIO67", "MIO68", "MIO69"; - bias-disable; - low-power-enable; - }; - - conf-mdio { - groups = "mdio3_0_grp"; - slew-rate = ; - power-source = ; - bias-disable; - }; - - mux-mdio { - function = "mdio3"; - groups = "mdio3_0_grp"; - }; - - mux { - function = "ethernet3"; - groups = "ethernet3_0_grp"; - }; - }; - - pinctrl_usb0_default: usb0-default { - conf { - groups = "usb0_0_grp"; - slew-rate = ; - power-source = ; - }; - - conf-rx { - pins = "MIO52", "MIO53", "MIO55"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", - "MIO60", "MIO61", "MIO62", "MIO63"; - bias-disable; - }; - - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - }; - - pinctrl_sdhci1_default: sdhci1-default { - conf { - groups = "sdio1_0_grp"; - slew-rate = ; - power-source = ; - bias-disable; - }; - - conf-cd { - groups = "sdio1_cd_0_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = ; - power-source = ; - }; - - mux-cd { - groups = "sdio1_cd_0_grp"; - function = "sdio1_cd"; - }; - - mux { - groups = "sdio1_0_grp"; - function = "sdio1"; - }; - }; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; -}; Index: linux-6.1.80/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KV260 revA Carrier Card + * + * (C) Copyright 2020 - 2021, Xilinx, Inc. + * + * SD level shifter: + * "A" – A01 board un-modified (NXP) + * "Y" – A01 board modified with legacy interposer (Nexperia) + * "Z" – A01 board modified with Diode interposer + * + * Michal Simek + */ + +#include +#include +#include +#include + +/dts-v1/; +/plugin/; + +&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + + /* u14 - 0x40 - ina260 */ + /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ +}; + +&amba { + si5332_0: si5332_0 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + si5332_1: si5332_1 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + si5332_2: si5332_2 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + si5332_3: si5332_3 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + si5332_4: si5332_4 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + si5332_5: si5332_5 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; +}; + +/* DP/USB 3.0 and SATA */ +&psgtr { + status = "okay"; + /* pcie, usb3, sata */ + clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; + clock-names = "ref0", "ref1", "ref2"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&psgtr 3 PHY_TYPE_SATA 1 2>; +}; + +&zynqmp_dpsub { + status = "disabled"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; +}; + +&zynqmp_dpdma { + status = "okay"; +}; + +&usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; + /* missing usb5744 - u43 */ +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; +}; + +&sdhci1 { /* on CC with tuned parameters */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1_default>; + /* + * SD 3.0 requires level shifter and this property + * should be removed if the board has level shifter and + * need to work in UHS mode + */ + no-1-8-v; + disable-wp; + xlnx,mio-bank = <1>; +}; + +&gem3 { /* required by spec */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem3_default>; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; + + phy0: ethernet-phy@1 { + #phy-cells = <1>; + reg = <1>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + }; + }; +}; + +&pinctrl0 { /* required by spec */ + status = "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem3_default: gem3-default { + conf { + groups = "ethernet3_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO70", "MIO72", "MIO74"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO71", "MIO73", "MIO75"; + bias-disable; + low-power-disable; + }; + + conf-tx { + pins = "MIO64", "MIO65", "MIO66", + "MIO67", "MIO68", "MIO69"; + bias-disable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio3_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux-mdio { + function = "mdio3"; + groups = "mdio3_0_grp"; + }; + + mux { + function = "ethernet3"; + groups = "ethernet3_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_sdhci1_default: sdhci1-default { + conf { + groups = "sdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + conf-cd { + groups = "sdio1_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux-cd { + groups = "sdio1_cd_0_grp"; + function = "sdio1_cd"; + }; + + mux { + groups = "sdio1_0_grp"; + function = "sdio1"; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; Index: linux-6.1.80/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dts =================================================================== --- linux-6.1.80.orig/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dts +++ /dev/null @@ -1,298 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for KV260 revA Carrier Card - * - * (C) Copyright 2020 - 2021, Xilinx, Inc. - * - * Michal Simek - */ - -#include -#include -#include -#include - -/dts-v1/; -/plugin/; - -&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; - - /* u14 - 0x40 - ina260 */ - /* u43 - 0x2d - usb5744 */ - /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ -}; - -&amba { - si5332_0: si5332_0 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - si5332_1: si5332_1 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - si5332_2: si5332_2 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - si5332_3: si5332_3 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - si5332_4: si5332_4 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - si5332_5: si5332_5 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; -}; - -/* DP/USB 3.0 */ -&psgtr { - status = "okay"; - /* pcie, usb3, sata */ - clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; - clock-names = "ref0", "ref1", "ref2"; -}; - -&zynqmp_dpsub { - status = "disabled"; - phy-names = "dp-phy0", "dp-phy1"; - phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; -}; - -&zynqmp_dpdma { - status = "okay"; -}; - -&usb0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; - phy-names = "usb3-phy"; - phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; -}; - -&dwc3_0 { - status = "okay"; - dr_mode = "host"; - snps,usb3_lpm_capable; - maximum-speed = "super-speed"; -}; - -&sdhci1 { /* on CC with tuned parameters */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1_default>; - /* - * SD 3.0 requires level shifter and this property - * should be removed if the board has level shifter and - * need to work in UHS mode - */ - no-1-8-v; - disable-wp; - xlnx,mio-bank = <1>; - clk-phase-sd-hs = <126>, <60>; - clk-phase-uhs-sdr25 = <120>, <60>; - clk-phase-uhs-ddr50 = <126>, <48>; -}; - -&gem3 { /* required by spec */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gem3_default>; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; - - phy0: ethernet-phy@1 { - #phy-cells = <1>; - reg = <1>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,dp83867-rxctrl-strap-quirk; - }; - }; -}; - -&pinctrl0 { /* required by spec */ - status = "okay"; - - pinctrl_uart1_default: uart1-default { - conf { - groups = "uart1_9_grp"; - slew-rate = ; - power-source = ; - drive-strength = <12>; - }; - - conf-rx { - pins = "MIO37"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO36"; - bias-disable; - }; - - mux { - groups = "uart1_9_grp"; - function = "uart1"; - }; - }; - - pinctrl_i2c1_default: i2c1-default { - conf { - groups = "i2c1_6_grp"; - bias-pull-up; - slew-rate = ; - power-source = ; - }; - - mux { - groups = "i2c1_6_grp"; - function = "i2c1"; - }; - }; - - pinctrl_i2c1_gpio: i2c1-gpio { - conf { - groups = "gpio0_24_grp", "gpio0_25_grp"; - slew-rate = ; - power-source = ; - }; - - mux { - groups = "gpio0_24_grp", "gpio0_25_grp"; - function = "gpio0"; - }; - }; - - pinctrl_gem3_default: gem3-default { - conf { - groups = "ethernet3_0_grp"; - slew-rate = ; - power-source = ; - }; - - conf-rx { - pins = "MIO70", "MIO72", "MIO74"; - bias-high-impedance; - low-power-disable; - }; - - conf-bootstrap { - pins = "MIO71", "MIO73", "MIO75"; - bias-disable; - low-power-disable; - }; - - conf-tx { - pins = "MIO64", "MIO65", "MIO66", - "MIO67", "MIO68", "MIO69"; - bias-disable; - low-power-enable; - }; - - conf-mdio { - groups = "mdio3_0_grp"; - slew-rate = ; - power-source = ; - bias-disable; - }; - - mux-mdio { - function = "mdio3"; - groups = "mdio3_0_grp"; - }; - - mux { - function = "ethernet3"; - groups = "ethernet3_0_grp"; - }; - }; - - pinctrl_usb0_default: usb0-default { - conf { - groups = "usb0_0_grp"; - slew-rate = ; - power-source = ; - }; - - conf-rx { - pins = "MIO52", "MIO53", "MIO55"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", - "MIO60", "MIO61", "MIO62", "MIO63"; - bias-disable; - }; - - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - }; - - pinctrl_sdhci1_default: sdhci1-default { - conf { - groups = "sdio1_0_grp"; - slew-rate = ; - power-source = ; - bias-disable; - }; - - conf-cd { - groups = "sdio1_cd_0_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = ; - power-source = ; - }; - - mux-cd { - groups = "sdio1_cd_0_grp"; - function = "sdio1_cd"; - }; - - mux { - groups = "sdio1_0_grp"; - function = "sdio1"; - }; - }; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; -}; Index: linux-6.1.80/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso =================================================================== --- /dev/null +++ linux-6.1.80/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KV260 revA Carrier Card + * + * (C) Copyright 2020 - 2021, Xilinx, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include + +/dts-v1/; +/plugin/; + +&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + + /* u14 - 0x40 - ina260 */ + /* u43 - 0x2d - usb5744 */ + /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ +}; + +&amba { + si5332_0: si5332_0 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + si5332_1: si5332_1 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + si5332_2: si5332_2 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + si5332_3: si5332_3 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + si5332_4: si5332_4 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + si5332_5: si5332_5 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; +}; + +/* DP/USB 3.0 */ +&psgtr { + status = "okay"; + /* pcie, usb3, sata */ + clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; + clock-names = "ref0", "ref1", "ref2"; +}; + +&zynqmp_dpsub { + status = "disabled"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; +}; + +&zynqmp_dpdma { + status = "okay"; +}; + +&usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; +}; + +&sdhci1 { /* on CC with tuned parameters */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1_default>; + /* + * SD 3.0 requires level shifter and this property + * should be removed if the board has level shifter and + * need to work in UHS mode + */ + no-1-8-v; + disable-wp; + xlnx,mio-bank = <1>; + clk-phase-sd-hs = <126>, <60>; + clk-phase-uhs-sdr25 = <120>, <60>; + clk-phase-uhs-ddr50 = <126>, <48>; +}; + +&gem3 { /* required by spec */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem3_default>; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; + + phy0: ethernet-phy@1 { + #phy-cells = <1>; + reg = <1>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + }; + }; +}; + +&pinctrl0 { /* required by spec */ + status = "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem3_default: gem3-default { + conf { + groups = "ethernet3_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO70", "MIO72", "MIO74"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO71", "MIO73", "MIO75"; + bias-disable; + low-power-disable; + }; + + conf-tx { + pins = "MIO64", "MIO65", "MIO66", + "MIO67", "MIO68", "MIO69"; + bias-disable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio3_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux-mdio { + function = "mdio3"; + groups = "mdio3_0_grp"; + }; + + mux { + function = "ethernet3"; + groups = "ethernet3_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_sdhci1_default: sdhci1-default { + conf { + groups = "sdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + conf-cd { + groups = "sdio1_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux-cd { + groups = "sdio1_cd_0_grp"; + function = "sdio1_cd"; + }; + + mux { + groups = "sdio1_0_grp"; + function = "sdio1"; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; Index: linux-6.1.80/arch/arm64/configs/defconfig =================================================================== --- linux-6.1.80.orig/arch/arm64/configs/defconfig +++ linux-6.1.80/arch/arm64/configs/defconfig @@ -17,6 +17,8 @@ CONFIG_IKCONFIG_PROC=y CONFIG_NUMA_BALANCING=y CONFIG_MEMCG=y CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_PIDS=y CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_HUGETLB=y @@ -25,10 +27,12 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y +CONFIG_NAMESPACES=y CONFIG_USER_NS=y CONFIG_SCHED_AUTOGROUP=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y CONFIG_PROFILING=y CONFIG_ARCH_ACTIONS=y CONFIG_ARCH_SUNXI=y @@ -36,13 +40,12 @@ CONFIG_ARCH_ALPINE=y CONFIG_ARCH_APPLE=y CONFIG_ARCH_BCM=y CONFIG_ARCH_BCM2835=y -CONFIG_ARCH_BCMBCA=y CONFIG_ARCH_BCM_IPROC=y -CONFIG_ARCH_BERLIN=y +CONFIG_ARCH_BCMBCA=y CONFIG_ARCH_BRCMSTB=y +CONFIG_ARCH_BERLIN=y CONFIG_ARCH_EXYNOS=y CONFIG_ARCH_K3=y -CONFIG_ARCH_LAYERSCAPE=y CONFIG_ARCH_LG1K=y CONFIG_ARCH_HISI=y CONFIG_ARCH_KEEMBAY=y @@ -50,12 +53,13 @@ CONFIG_ARCH_MEDIATEK=y CONFIG_ARCH_MESON=y CONFIG_ARCH_MVEBU=y CONFIG_ARCH_NXP=y +CONFIG_ARCH_LAYERSCAPE=y CONFIG_ARCH_MXC=y +CONFIG_ARCH_S32=y CONFIG_ARCH_NPCM=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_RENESAS=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_ARCH_S32=y CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_INTEL_SOCFPGA=y CONFIG_ARCH_SYNQUACER=y @@ -112,20 +116,10 @@ CONFIG_ACPI_APEI_MEMORY_FAILURE=y CONFIG_ACPI_APEI_EINJ=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512_ARM64_CE=m -CONFIG_CRYPTO_SHA3_ARM64=m -CONFIG_CRYPTO_SM3_ARM64_CE=m -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_CHACHA20_NEON=m -CONFIG_CRYPTO_AES_ARM64_BS=m CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y +CONFIG_BLK_DEV_THROTTLING=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_COMPAT_BRK is not set CONFIG_MEMORY_HOTPLUG=y @@ -136,16 +130,21 @@ CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_XDP_SOCKETS=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y +CONFIG_INET_ESP=y CONFIG_IPV6=m CONFIG_NETFILTER=y CONFIG_BRIDGE_NETFILTER=m CONFIG_NF_CONNTRACK=m CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NETFILTER_XT_MARK=m CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_LOG=m @@ -153,11 +152,16 @@ CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_IPVS=m CONFIG_IP_VS=m +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_NFCT=y CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_MANGLE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_FILTER=m @@ -178,18 +182,38 @@ CONFIG_NET_SCH_TAPRIO=m CONFIG_NET_SCH_MQPRIO=m CONFIG_NET_SCH_INGRESS=m CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m CONFIG_NET_ACT_GATE=m +CONFIG_HSR=m CONFIG_QRTR_SMD=m CONFIG_QRTR_TUN=m +CONFIG_CGROUP_NET_PRIO=y CONFIG_CAN=m -CONFIG_CAN_FLEXCAN=m -CONFIG_CAN_RCAR=m -CONFIG_CAN_RCAR_CANFD=m -CONFIG_CAN_MCP251XFD=m CONFIG_BT=m CONFIG_BT_HIDP=m # CONFIG_BT_LE is not set @@ -206,7 +230,6 @@ CONFIG_BT_MRVL_SDIO=m CONFIG_BT_QCOMSMD=m CONFIG_CFG80211=m CONFIG_MAC80211=m -CONFIG_MAC80211_LEDS=y CONFIG_RFKILL=m CONFIG_NET_9P=y CONFIG_NET_9P_VIRTIO=y @@ -233,6 +256,8 @@ CONFIG_PCI_HOST_THUNDER_ECAM=y CONFIG_PCIE_ROCKCHIP_HOST=m CONFIG_PCIE_BRCMSTB=m CONFIG_PCI_IMX6=y +CONFIG_PCI_KEYSTONE_HOST=y +CONFIG_PCI_KEYSTONE_EP=y CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_HISI=y CONFIG_PCIE_QCOM=y @@ -242,9 +267,12 @@ CONFIG_PCIE_HISI_STB=y CONFIG_PCIE_TEGRA194_HOST=m CONFIG_PCIE_VISCONTI_HOST=y CONFIG_PCIE_LAYERSCAPE_GEN4=y +CONFIG_PCI_J721E_HOST=m +CONFIG_PCI_J721E_EP=m CONFIG_PCI_ENDPOINT=y CONFIG_PCI_ENDPOINT_CONFIGFS=y -CONFIG_PCI_EPF_TEST=m +CONFIG_PCI_EPF_TEST=y +CONFIG_PCI_EPF_NTB=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_FW_LOADER_USER_HELPER=y @@ -261,6 +289,8 @@ CONFIG_IMX_SCU_PD=y CONFIG_GNSS=m CONFIG_GNSS_MTK_SERIAL=m CONFIG_MTD=y +CONFIG_MTD_TESTS=m +CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -273,11 +303,17 @@ CONFIG_MTD_DATAFLASH=y CONFIG_MTD_SST25L=y CONFIG_MTD_RAW_NAND=y CONFIG_MTD_NAND_DENALI_DT=y +CONFIG_MTD_NAND_OMAP2=y +CONFIG_MTD_NAND_OMAP_BCH=y CONFIG_MTD_NAND_MARVELL=y CONFIG_MTD_NAND_BRCMNAND=m CONFIG_MTD_NAND_FSL_IFC=y CONFIG_MTD_NAND_QCOM=y +CONFIG_MTD_SPI_NAND=y CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_MTD_HYPERBUS=m +CONFIG_HBMC_AM654=m CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m CONFIG_VIRTIO_BLK=y @@ -285,6 +321,7 @@ CONFIG_BLK_DEV_NVME=m CONFIG_QCOM_COINCELL=m CONFIG_QCOM_FASTRPC=m CONFIG_SRAM=y +CONFIG_SRAM_DMA_HEAP=y CONFIG_PCI_ENDPOINT_TEST=m CONFIG_EEPROM_AT24=m CONFIG_EEPROM_AT25=m @@ -306,16 +343,19 @@ CONFIG_AHCI_XGENE=y CONFIG_AHCI_QORIQ=y CONFIG_SATA_SIL24=y CONFIG_SATA_RCAR=y -CONFIG_PATA_PLATFORM=y CONFIG_PATA_OF_PLATFORM=y CONFIG_MD=y CONFIG_BLK_DEV_MD=m CONFIG_BLK_DEV_DM=m +CONFIG_DM_THIN_PROVISIONING=m CONFIG_DM_MIRROR=m CONFIG_DM_ZERO=m CONFIG_NETDEVICES=y +CONFIG_DUMMY=m CONFIG_MACVLAN=m CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_VXLAN=m CONFIG_TUN=y CONFIG_VETH=m CONFIG_VIRTIO_NET=y @@ -362,8 +402,13 @@ CONFIG_SMSC911X=y CONFIG_SNI_AVE=y CONFIG_SNI_NETSEC=y CONFIG_STMMAC_ETH=m -CONFIG_DWMAC_TEGRA=m +CONFIG_TI_CPSW_PROXY_CLIENT=m CONFIG_TI_K3_AM65_CPSW_NUSS=y +CONFIG_TI_K3_AM65_CPSW_SWITCHDEV=y +CONFIG_TI_K3_AM65_CPTS=y +CONFIG_TI_AM65_CPSW_TAS=y +CONFIG_TI_RDEV_ETH_SWITCH_VIRT_EMAC=m +CONFIG_TI_ICSSG_PRUETH=m CONFIG_QCOM_IPA=m CONFIG_MESON_GXL_PHY=m CONFIG_AQUANTIA_PHY=y @@ -376,7 +421,16 @@ CONFIG_AT803X_PHY=y CONFIG_REALTEK_PHY=y CONFIG_ROCKCHIP_PHY=y CONFIG_DP83867_PHY=y +CONFIG_DP83869_PHY=y +CONFIG_DP83TD510_PHY=y CONFIG_VITESSE_PHY=y +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PLATFORM=m +CONFIG_CAN_RCAR=m +CONFIG_CAN_RCAR_CANFD=m +CONFIG_CAN_MCP251XFD=m +CONFIG_MDIO_GPIO=y CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y CONFIG_MDIO_BUS_MUX_MMIOREG=y CONFIG_USB_PEGASUS=m @@ -398,6 +452,9 @@ CONFIG_ATH11K=m CONFIG_ATH11K_AHB=m CONFIG_ATH11K_PCI=m CONFIG_BRCMFMAC=m +CONFIG_IWLWIFI=m +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m CONFIG_MWIFIEX=m CONFIG_MWIFIEX_SDIO=m CONFIG_MWIFIEX_PCIE=m @@ -412,10 +469,12 @@ CONFIG_KEYBOARD_CROS_EC=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ATMEL_MXT=m CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_ILI210X=m CONFIG_TOUCHSCREEN_EDT_FT5X06=m CONFIG_INPUT_MISC=y CONFIG_INPUT_PM8941_PWRKEY=y CONFIG_INPUT_PM8XXX_VIBRATOR=m +CONFIG_INPUT_TPS65219_PWRBUTTON=m CONFIG_INPUT_PWM_BEEPER=m CONFIG_INPUT_PWM_VIBRA=m CONFIG_INPUT_HISI_POWERKEY=y @@ -424,6 +483,8 @@ CONFIG_SERIO_AMBAKMI=y CONFIG_LEGACY_PTY_COUNT=16 CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=12 +CONFIG_SERIAL_8250_RUNTIME_UARTS=12 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_BCM2835AUX=y @@ -432,6 +493,7 @@ CONFIG_SERIAL_8250_EM=y CONFIG_SERIAL_8250_OMAP=y CONFIG_SERIAL_8250_MT6577=y CONFIG_SERIAL_8250_UNIPHIER=y +CONFIG_SERIAL_8250_PRUSS=m CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y @@ -505,6 +567,7 @@ CONFIG_SPI_IMX=m CONFIG_SPI_FSL_DSPI=y CONFIG_SPI_MESON_SPICC=m CONFIG_SPI_MESON_SPIFC=m +CONFIG_SPI_OMAP24XX=m CONFIG_SPI_ORION=y CONFIG_SPI_PL022=y CONFIG_SPI_ROCKCHIP=y @@ -519,6 +582,7 @@ CONFIG_SPI_SUN6I=y CONFIG_SPI_TEGRA210_QUAD=m CONFIG_SPI_TEGRA114=m CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SLAVE=y CONFIG_SPMI=y CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_SINGLE=y @@ -601,6 +665,7 @@ CONFIG_DEVFREQ_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_IMX_SC_THERMAL=m CONFIG_IMX8MM_THERMAL=m +CONFIG_K3_THERMAL=m CONFIG_QORIQ_THERMAL=m CONFIG_SUN8I_THERMAL=y CONFIG_ROCKCHIP_THERMAL=m @@ -625,7 +690,9 @@ CONFIG_ARM_SP805_WATCHDOG=y CONFIG_ARM_SBSA_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=y CONFIG_DW_WATCHDOG=y +CONFIG_K3_RTI_WATCHDOG=m CONFIG_SUNXI_WATCHDOG=m +CONFIG_NPCM7XX_WATCHDOG=y CONFIG_IMX2_WDT=y CONFIG_IMX_SC_WDT=m CONFIG_QCOM_WDT=m @@ -638,7 +705,6 @@ CONFIG_UNIPHIER_WATCHDOG=y CONFIG_PM8916_WATCHDOG=m CONFIG_BCM2835_WDT=y CONFIG_BCM7038_WDT=m -CONFIG_NPCM7XX_WATCHDOG=y CONFIG_MFD_ALTERA_SYSMGR=y CONFIG_MFD_BD9571MWV=y CONFIG_MFD_AXP20X_I2C=y @@ -653,6 +719,9 @@ CONFIG_MFD_SPMI_PMIC=y CONFIG_MFD_RK808=y CONFIG_MFD_SEC_CORE=y CONFIG_MFD_SL28CPLD=y +CONFIG_MFD_TI_AM335X_TSCADC=m +CONFIG_MFD_TPS65219=y +CONFIG_MFD_TPS6594_I2C=y CONFIG_MFD_ROHM_BD718XX=y CONFIG_MFD_WCD934X=m CONFIG_REGULATOR_FIXED_VOLTAGE=y @@ -677,9 +746,11 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_RPMH=y CONFIG_REGULATOR_QCOM_SMD_RPM=y CONFIG_REGULATOR_QCOM_SPMI=y +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m CONFIG_REGULATOR_RK808=y CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_TPS65132=m +CONFIG_REGULATOR_TPS65219=y CONFIG_REGULATOR_VCTRL=m CONFIG_RC_CORE=m CONFIG_RC_DECODERS=y @@ -687,17 +758,17 @@ CONFIG_RC_DEVICES=y CONFIG_IR_MESON=m CONFIG_IR_SUNXI=m CONFIG_MEDIA_SUPPORT=m -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -CONFIG_MEDIA_SDR_SUPPORT=y -CONFIG_MEDIA_PLATFORM_SUPPORT=y # CONFIG_DVB_NET is not set CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_SDR_PLATFORM_DRIVERS=y CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_CADENCE_CSI2RX=m +CONFIG_VIDEO_WAVE_VPU=m +CONFIG_VIDEO_IMG_VXD_DEC=m +CONFIG_VIDEO_IMG_VXE_ENC=m +CONFIG_VIDEO_E5010_JPEG_ENC=m CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_VIDEO_QCOM_VENUS=m CONFIG_VIDEO_RCAR_ISP=m @@ -711,9 +782,16 @@ CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m CONFIG_VIDEO_SAMSUNG_S5P_MFC=m CONFIG_VIDEO_SUN6I_CSI=m +CONFIG_VIDEO_TI_J721E_CSI2RX=m +CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX390=m +CONFIG_VIDEO_OV2312=m CONFIG_VIDEO_OV5640=m CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_OX05B1S=m +CONFIG_VIDEO_DS90UB953=m +CONFIG_VIDEO_DS90UB960=m CONFIG_DRM=m CONFIG_DRM_I2C_NXP_TDA998X=m CONFIG_DRM_HDLCD=m @@ -736,11 +814,7 @@ CONFIG_ROCKCHIP_INNO_HDMI=y CONFIG_ROCKCHIP_LVDS=y CONFIG_DRM_RCAR_DU=m CONFIG_DRM_RCAR_DW_HDMI=m -CONFIG_DRM_RCAR_MIPI_DSI=m CONFIG_DRM_SUN4I=m -CONFIG_DRM_SUN6I_DSI=m -CONFIG_DRM_SUN8I_DW_HDMI=m -CONFIG_DRM_SUN8I_MIXER=m CONFIG_DRM_MSM=m CONFIG_DRM_TEGRA=m CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m @@ -754,14 +828,18 @@ CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m CONFIG_DRM_LONTIUM_LT8912B=m CONFIG_DRM_LONTIUM_LT9611=m CONFIG_DRM_LONTIUM_LT9611UXC=m +CONFIG_DRM_ITE_IT66121=m CONFIG_DRM_NWL_MIPI_DSI=m CONFIG_DRM_PARADE_PS8640=m CONFIG_DRM_SII902X=m CONFIG_DRM_SIMPLE_BRIDGE=m CONFIG_DRM_THINE_THC63LVD1024=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_TI_TFP410=m CONFIG_DRM_TI_SN65DSI86=m CONFIG_DRM_I2C_ADV7511=m CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_DRM_CDNS_DSI=m CONFIG_DRM_CDNS_MHDP8546=m CONFIG_DRM_DW_HDMI_AHB_AUDIO=m CONFIG_DRM_DW_HDMI_CEC=m @@ -782,8 +860,11 @@ CONFIG_DRM_TIDSS=m CONFIG_FB=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_EFI=y +CONFIG_FB_SIMPLE=y CONFIG_BACKLIGHT_PWM=m CONFIG_BACKLIGHT_LP855X=m +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set @@ -791,6 +872,7 @@ CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_HDA_TEGRA=m CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=y CONFIG_SND_BCM2835_SOC_I2S=m CONFIG_SND_SOC_FSL_ASRC=m @@ -836,18 +918,19 @@ CONFIG_SND_SOC_TEGRA210_AMX=m CONFIG_SND_SOC_TEGRA210_ADX=m CONFIG_SND_SOC_TEGRA210_MIXER=m CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m +CONFIG_SND_SOC_J721E_EVM=m CONFIG_SND_SOC_AK4613=m CONFIG_SND_SOC_ES7134=m CONFIG_SND_SOC_ES7241=m CONFIG_SND_SOC_GTM601=m CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m -CONFIG_SND_SOC_PCM3168A_I2C=m CONFIG_SND_SOC_RT5659=m CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m CONFIG_SND_SOC_SIMPLE_MUX=m CONFIG_SND_SOC_TAS571X=m CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_TLV320AIC3X_I2C=m CONFIG_SND_SOC_WCD9335=m CONFIG_SND_SOC_WCD934X=m CONFIG_SND_SOC_WM8524=m @@ -859,8 +942,6 @@ CONFIG_SND_SOC_WSA881X=m CONFIG_SND_SOC_NAU8822=m CONFIG_SND_SOC_LPASS_WSA_MACRO=m CONFIG_SND_SOC_LPASS_VA_MACRO=m -CONFIG_SND_SOC_LPASS_RX_MACRO=m -CONFIG_SND_SOC_LPASS_TX_MACRO=m CONFIG_SND_SIMPLE_CARD=m CONFIG_SND_AUDIO_GRAPH_CARD=m CONFIG_SND_AUDIO_GRAPH_CARD2=m @@ -890,7 +971,7 @@ CONFIG_USB_CDNS3_HOST=y CONFIG_USB_MTU3=y CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_SUNXI=y -CONFIG_USB_DWC3=y +CONFIG_USB_DWC3=m CONFIG_USB_DWC2=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y @@ -903,6 +984,7 @@ CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_HSIC_USB3503=y CONFIG_NOP_USB_XCEIV=y CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=32 CONFIG_USB_RENESAS_USBHS_UDC=m CONFIG_USB_RENESAS_USB3=m CONFIG_USB_TEGRA_XUDC=m @@ -917,6 +999,14 @@ CONFIG_USB_CONFIGFS_RNDIS=y CONFIG_USB_CONFIGFS_EEM=y CONFIG_USB_CONFIGFS_MASS_STORAGE=y CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_CDC=y CONFIG_TYPEC=m CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_TCPCI=m @@ -930,8 +1020,8 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ACPI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_OF_ARASAN=y -CONFIG_MMC_SDHCI_OF_DWCMSHC=y CONFIG_MMC_SDHCI_OF_ESDHC=y +CONFIG_MMC_SDHCI_OF_DWCMSHC=y CONFIG_MMC_SDHCI_CADENCE=y CONFIG_MMC_SDHCI_ESDHC_IMX=y CONFIG_MMC_SDHCI_TEGRA=y @@ -953,10 +1043,13 @@ CONFIG_MMC_SDHCI_XENON=y CONFIG_MMC_SDHCI_AM654=y CONFIG_MMC_OWL=y CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFS_BSG=y CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_SCSI_UFS_CDNS_PLATFORM=m CONFIG_SCSI_UFS_QCOM=m CONFIG_SCSI_UFS_HISI=y CONFIG_SCSI_UFS_RENESAS=m +CONFIG_SCSI_UFS_TI_J721E=m CONFIG_SCSI_UFS_EXYNOS=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y @@ -984,6 +1077,7 @@ CONFIG_RTC_DRV_RK808=m CONFIG_RTC_DRV_PCF85063=m CONFIG_RTC_DRV_PCF85363=m CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_BQ32K=m CONFIG_RTC_DRV_RX8581=m CONFIG_RTC_DRV_RV3028=m CONFIG_RTC_DRV_RV8803=m @@ -1003,6 +1097,7 @@ CONFIG_RTC_DRV_SNVS=m CONFIG_RTC_DRV_IMX_SC=m CONFIG_RTC_DRV_MT6397=m CONFIG_RTC_DRV_XGENE=y +CONFIG_RTC_DRV_TI_K3=m CONFIG_DMADEVICES=y CONFIG_DMA_BCM2835=y CONFIG_DMA_SUN6I=m @@ -1025,6 +1120,10 @@ CONFIG_RENESAS_USB_DMAC=m CONFIG_RZ_DMAC=y CONFIG_TI_K3_UDMA=y CONFIG_TI_K3_UDMA_GLUE_LAYER=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_DMABUF_HEAPS_CARVEOUT=y CONFIG_VFIO=y CONFIG_VFIO_PCI=y CONFIG_VIRTIO_PCI=y @@ -1034,7 +1133,6 @@ CONFIG_XEN_GNTDEV=y CONFIG_XEN_GRANT_DEV_ALLOC=y CONFIG_STAGING=y CONFIG_STAGING_MEDIA=y -CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_IMX_MEDIA=m CONFIG_VIDEO_MAX96712=m CONFIG_CHROME_PLATFORMS=y @@ -1096,6 +1194,7 @@ CONFIG_RENESAS_OSTM=y CONFIG_ARM_MHU=y CONFIG_IMX_MBOX=y CONFIG_PLATFORM_MHU=y +CONFIG_OMAP2PLUS_MBOX=y CONFIG_BCM2835_MBOX=y CONFIG_QCOM_APCS_IPC=y CONFIG_QCOM_IPCC=y @@ -1106,16 +1205,23 @@ CONFIG_ARM_SMMU_V3=y CONFIG_MTK_IOMMU=y CONFIG_QCOM_IOMMU=y CONFIG_REMOTEPROC=y +CONFIG_MTK_SCP=m CONFIG_QCOM_Q6V5_ADSP=m CONFIG_QCOM_Q6V5_MSS=m CONFIG_QCOM_Q6V5_PAS=m CONFIG_QCOM_SYSMON=m CONFIG_QCOM_WCNSS_PIL=m +CONFIG_TI_K3_DSP_REMOTEPROC=m +CONFIG_TI_K3_M4_REMOTEPROC=m +CONFIG_TI_K3_R5_REMOTEPROC=m CONFIG_RPMSG_CHAR=m CONFIG_RPMSG_CTRL=m CONFIG_RPMSG_QCOM_GLINK_RPM=y CONFIG_RPMSG_QCOM_GLINK_SMEM=m CONFIG_RPMSG_QCOM_SMD=y +CONFIG_RPMSG_VIRTIO=m +CONFIG_RPMSG_PRU=m +CONFIG_RPMSG_KDRV_ETH_SWITCH=y CONFIG_SOUNDWIRE=m CONFIG_SOUNDWIRE_QCOM=m CONFIG_OWL_PM_DOMAINS=y @@ -1173,11 +1279,13 @@ CONFIG_ARCH_TEGRA_186_SOC=y CONFIG_ARCH_TEGRA_194_SOC=y CONFIG_ARCH_TEGRA_234_SOC=y CONFIG_TI_SCI_PM_DOMAINS=y +CONFIG_TI_PRUSS=m CONFIG_ARM_IMX_BUS_DEVFREQ=m CONFIG_ARM_IMX8M_DDRC_DEVFREQ=m CONFIG_EXTCON_PTN5150=m CONFIG_EXTCON_USB_GPIO=y CONFIG_EXTCON_USBC_CROS_EC=y +CONFIG_OMAP_GPMC=y CONFIG_RENESAS_RPCIF=m CONFIG_IIO=y CONFIG_EXYNOS_ADC=y @@ -1187,6 +1295,7 @@ CONFIG_QCOM_SPMI_ADC5=m CONFIG_ROCKCHIP_SARADC=m CONFIG_RZG2L_ADC=m CONFIG_TI_ADS1015=m +CONFIG_TI_AM335X_ADC=m CONFIG_IIO_CROS_EC_SENSORS_CORE=m CONFIG_IIO_CROS_EC_SENSORS=m CONFIG_IIO_ST_LSM6DSX=m @@ -1204,6 +1313,7 @@ CONFIG_PWM_IMX27=m CONFIG_PWM_MESON=m CONFIG_PWM_MTK_DISP=m CONFIG_PWM_MEDIATEK=m +CONFIG_PWM_OMAP_DMTIMER=m CONFIG_PWM_RCAR=m CONFIG_PWM_RENESAS_TPU=m CONFIG_PWM_ROCKCHIP=y @@ -1211,6 +1321,8 @@ CONFIG_PWM_SAMSUNG=y CONFIG_PWM_SL28CPLD=m CONFIG_PWM_SUN4I=m CONFIG_PWM_TEGRA=m +CONFIG_PWM_TIECAP=m +CONFIG_PWM_TIEHRPWM=m CONFIG_PWM_VISCONTI=m CONFIG_SL28CPLD_INTC=y CONFIG_QCOM_PDC=y @@ -1220,9 +1332,12 @@ CONFIG_RESET_QCOM_PDC=m CONFIG_RESET_RZG2L_USBPHY_CTRL=y CONFIG_RESET_TI_SCI=y CONFIG_PHY_XGENE=y +CONFIG_PHY_CAN_TRANSCEIVER=m CONFIG_PHY_SUN4I_USB=y -CONFIG_PHY_CADENCE_TORRENT=m -CONFIG_PHY_CADENCE_SIERRA=m +CONFIG_PHY_CADENCE_TORRENT=y +CONFIG_PHY_CADENCE_DPHY=m +CONFIG_PHY_CADENCE_DPHY_RX=m +CONFIG_PHY_CADENCE_SIERRA=y CONFIG_PHY_MIXEL_MIPI_DPHY=m CONFIG_PHY_FSL_IMX8M_PCIE=y CONFIG_PHY_HI6220_USB=y @@ -1251,29 +1366,30 @@ CONFIG_PHY_SAMSUNG_UFS=y CONFIG_PHY_UNIPHIER_USB2=y CONFIG_PHY_UNIPHIER_USB3=y CONFIG_PHY_TEGRA_XUSB=y -CONFIG_PHY_AM654_SERDES=m -CONFIG_PHY_J721E_WIZ=m +CONFIG_PHY_AM654_SERDES=y +CONFIG_PHY_J721E_WIZ=y +CONFIG_OMAP_USB2=m CONFIG_ARM_CCI_PMU=m CONFIG_ARM_CCN=m CONFIG_ARM_CMN=m CONFIG_ARM_SMMU_V3_PMU=m CONFIG_ARM_DSU_PMU=m CONFIG_FSL_IMX8_DDR_PMU=m -CONFIG_ARM_SPE_PMU=m -CONFIG_ARM_DMC620_PMU=m CONFIG_QCOM_L2_PMU=y CONFIG_QCOM_L3_PMU=y +CONFIG_ARM_SPE_PMU=m +CONFIG_ARM_DMC620_PMU=m CONFIG_HISI_PMU=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_IMX_OCOTP_SCU=y +CONFIG_NVMEM_LAYERSCAPE_SFP=m +CONFIG_NVMEM_MESON_EFUSE=m CONFIG_NVMEM_MTK_EFUSE=y CONFIG_NVMEM_QCOM_QFPROM=y +CONFIG_NVMEM_RMEM=m CONFIG_NVMEM_ROCKCHIP_EFUSE=y CONFIG_NVMEM_SUNXI_SID=y CONFIG_NVMEM_UNIPHIER_EFUSE=y -CONFIG_NVMEM_MESON_EFUSE=m -CONFIG_NVMEM_RMEM=m -CONFIG_NVMEM_LAYERSCAPE_SFP=m CONFIG_FPGA=y CONFIG_FPGA_MGR_ALTERA_CVP=m CONFIG_FPGA_MGR_STRATIX10_SOC=m @@ -1283,11 +1399,9 @@ CONFIG_FPGA_REGION=m CONFIG_OF_FPGA_REGION=m CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_MUX_MMIO=y -CONFIG_SLIMBUS=m +CONFIG_MUX_GPIO=y CONFIG_SLIM_QCOM_CTRL=m CONFIG_SLIM_QCOM_NGD_CTRL=m -CONFIG_INTERCONNECT=y CONFIG_INTERCONNECT_IMX=m CONFIG_INTERCONNECT_IMX8MM=m CONFIG_INTERCONNECT_IMX8MN=m @@ -1306,9 +1420,13 @@ CONFIG_INTERCONNECT_QCOM_SM8150=m CONFIG_INTERCONNECT_QCOM_SM8250=m CONFIG_INTERCONNECT_QCOM_SM8350=m CONFIG_INTERCONNECT_QCOM_SM8450=m +CONFIG_COUNTER=m +CONFIG_TI_EQEP=m +CONFIG_TI_ECAP_CAPTURE=m CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y CONFIG_FANOTIFY=y @@ -1321,8 +1439,8 @@ CONFIG_OVERLAY_FS=m CONFIG_VFAT_FS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_HUGETLBFS=y -CONFIG_CONFIGFS_FS=y CONFIG_EFIVAR_FS=y +CONFIG_UBIFS_FS=y CONFIG_SQUASHFS=y CONFIG_NFS_FS=y CONFIG_NFS_V4=y @@ -1333,10 +1451,22 @@ CONFIG_9P_FS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_SECURITY=y -CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64_CE=m +CONFIG_CRYPTO_SHA3_ARM64=m +CONFIG_CRYPTO_SM3_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_BS=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m CONFIG_CRYPTO_DEV_SUN8I_CE=m CONFIG_CRYPTO_DEV_FSL_CAAM=m CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m @@ -1346,9 +1476,10 @@ CONFIG_CRYPTO_DEV_HISI_SEC2=m CONFIG_CRYPTO_DEV_HISI_ZIP=m CONFIG_CRYPTO_DEV_HISI_HPRE=m CONFIG_CRYPTO_DEV_HISI_TRNG=m +CONFIG_CRYPTO_DEV_SA2UL=m +CONFIG_CRYPTO_DEV_TI_MCRC64=m CONFIG_CMA_SIZE_MBYTES=32 CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y CONFIG_DEBUG_INFO_REDUCED=y CONFIG_MAGIC_SYSRQ=y @@ -1356,6 +1487,8 @@ CONFIG_DEBUG_FS=y # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_PREEMPT is not set # CONFIG_FTRACE is not set +CONFIG_SAMPLES=y +CONFIG_SAMPLE_RPMSG_CLIENT=m CONFIG_CORESIGHT=m CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m CONFIG_CORESIGHT_CATU=m Index: linux-6.1.80/arch/powerpc/Makefile =================================================================== --- linux-6.1.80.orig/arch/powerpc/Makefile +++ linux-6.1.80/arch/powerpc/Makefile @@ -232,17 +232,7 @@ PHONY += bootwrapper_install bootwrapper_install: $(Q)$(MAKE) $(build)=$(boot) $(patsubst %,$(boot)/%,$@) -# Used to create 'merged defconfigs' -# To use it $(call) it with the first argument as the base defconfig -# and the second argument as a space separated list of .config files to merge, -# without the .config suffix. -define merge_into_defconfig - $(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh \ - -m -O $(objtree) $(srctree)/arch/$(ARCH)/configs/$(1) \ - $(foreach config,$(2),$(srctree)/arch/$(ARCH)/configs/$(config).config) - +$(Q)$(MAKE) -f $(srctree)/Makefile olddefconfig -endef - +include $(srctree)/scripts/Makefile.defconf PHONY += pseries_le_defconfig pseries_le_defconfig: $(call merge_into_defconfig,pseries_defconfig,le) Index: linux-6.1.80/crypto/tcrypt.c =================================================================== --- linux-6.1.80.orig/crypto/tcrypt.c +++ linux-6.1.80/crypto/tcrypt.c @@ -2308,6 +2308,11 @@ static int do_test(const char *alg, u32 generic_hash_speed_template); if (mode > 300 && mode < 400) break; fallthrough; + case 329: + test_hash_speed("crc64", sec, generic_hash_speed_template); + if (mode > 300 && mode < 400) + break; + fallthrough; case 399: break; Index: linux-6.1.80/drivers/Kconfig =================================================================== --- linux-6.1.80.orig/drivers/Kconfig +++ linux-6.1.80/drivers/Kconfig @@ -169,6 +169,8 @@ source "drivers/remoteproc/Kconfig" source "drivers/rpmsg/Kconfig" +source "drivers/rpmsg-kdrv/Kconfig" + source "drivers/soundwire/Kconfig" source "drivers/soc/Kconfig" Index: linux-6.1.80/drivers/Makefile =================================================================== --- linux-6.1.80.orig/drivers/Makefile +++ linux-6.1.80/drivers/Makefile @@ -155,6 +155,7 @@ obj-$(CONFIG_MAILBOX) += mailbox/ obj-$(CONFIG_HWSPINLOCK) += hwspinlock/ obj-$(CONFIG_REMOTEPROC) += remoteproc/ obj-$(CONFIG_RPMSG) += rpmsg/ +obj-$(CONFIG_RPMSG_KDRV) += rpmsg-kdrv/ obj-$(CONFIG_SOUNDWIRE) += soundwire/ # Virtualization drivers Index: linux-6.1.80/drivers/bus/Kconfig =================================================================== --- linux-6.1.80.orig/drivers/bus/Kconfig +++ linux-6.1.80/drivers/bus/Kconfig @@ -210,7 +210,8 @@ config TI_PWMSS config TI_SYSC bool "TI sysc interconnect target module driver" - depends on ARCH_OMAP2PLUS + depends on ARCH_OMAP2PLUS || ARCH_K3 + default y help Generic driver for Texas Instruments interconnect target module found on many TI SoCs. Index: linux-6.1.80/drivers/clk/keystone/sci-clk.c =================================================================== --- linux-6.1.80.orig/drivers/clk/keystone/sci-clk.c +++ linux-6.1.80/drivers/clk/keystone/sci-clk.c @@ -517,6 +517,7 @@ static int ti_sci_scan_clocks_from_dt(st struct sci_clk *sci_clk, *prev; int num_clks = 0; int num_parents; + bool state; int clk_id; const char * const clk_names[] = { "clocks", "assigned-clocks", "assigned-clock-parents", NULL @@ -584,16 +585,23 @@ static int ti_sci_scan_clocks_from_dt(st num_parents = 255; } - clk_id = args.args[1] + 1; + clk_id = args.args[1]; while (num_parents--) { + /* Check if this clock id is valid */ + ret = provider->ops->is_auto(provider->sci, + sci_clk->dev_id, ++clk_id, &state); + + if (ret) + continue; + sci_clk = devm_kzalloc(dev, sizeof(*sci_clk), GFP_KERNEL); if (!sci_clk) return -ENOMEM; sci_clk->dev_id = args.args[0]; - sci_clk->clk_id = clk_id++; + sci_clk->clk_id = clk_id; sci_clk->provider = provider; list_add_tail(&sci_clk->node, &clks); Index: linux-6.1.80/drivers/clk/keystone/syscon-clk.c =================================================================== --- linux-6.1.80.orig/drivers/clk/keystone/syscon-clk.c +++ linux-6.1.80/drivers/clk/keystone/syscon-clk.c @@ -4,10 +4,12 @@ */ #include +#include #include #include #include #include +#include struct ti_syscon_gate_clk_priv { struct clk_hw hw; @@ -61,21 +63,31 @@ static const struct clk_ops ti_syscon_ga static struct clk_hw *ti_syscon_gate_clk_register(struct device *dev, struct regmap *regmap, + const char *parent_name, const struct ti_syscon_gate_clk_data *data) { struct ti_syscon_gate_clk_priv *priv; struct clk_init_data init; + char *name = NULL; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return ERR_PTR(-ENOMEM); - init.name = data->name; init.ops = &ti_syscon_gate_clk_ops; - init.parent_names = NULL; - init.num_parents = 0; - init.flags = 0; + if (parent_name) { + name = kasprintf(GFP_KERNEL, "%s:%s", data->name, parent_name); + init.name = name; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = CLK_SET_RATE_PARENT; + } else { + init.name = data->name; + init.parent_names = NULL; + init.num_parents = 0; + init.flags = 0; + } priv->regmap = regmap; priv->reg = data->offset; @@ -83,6 +95,10 @@ static struct clk_hw priv->hw.init = &init; ret = devm_clk_hw_register(dev, &priv->hw); + + if (name) + kfree(init.name); + if (ret) return ERR_PTR(ret); @@ -94,25 +110,30 @@ static int ti_syscon_gate_clk_probe(stru const struct ti_syscon_gate_clk_data *data, *p; struct clk_hw_onecell_data *hw_data; struct device *dev = &pdev->dev; + int num_clks, num_parents, i; + const char *parent_name; struct regmap *regmap; - int num_clks, i; data = device_get_match_data(dev); if (!data) return -EINVAL; - regmap = syscon_node_to_regmap(dev->of_node); - if (IS_ERR(regmap)) { - if (PTR_ERR(regmap) == -EPROBE_DEFER) - return -EPROBE_DEFER; - dev_err(dev, "failed to find parent regmap\n"); - return PTR_ERR(regmap); - } + regmap = device_node_to_regmap(dev->of_node); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "failed to get regmap\n"); num_clks = 0; for (p = data; p->name; p++) num_clks++; + num_parents = of_clk_get_parent_count(dev->of_node); + if (of_device_is_compatible(dev->of_node, "ti,am62-audio-refclk") && + num_parents == 0) { + return dev_err_probe(dev, -EINVAL, + "must specify a parent clock\n"); + } + hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks), GFP_KERNEL); if (!hw_data) @@ -120,16 +141,20 @@ static int ti_syscon_gate_clk_probe(stru hw_data->num = num_clks; + parent_name = of_clk_get_parent_name(dev->of_node, 0); for (i = 0; i < num_clks; i++) { hw_data->hws[i] = ti_syscon_gate_clk_register(dev, regmap, + parent_name, &data[i]); if (IS_ERR(hw_data->hws[i])) dev_warn(dev, "failed to register %s\n", data[i].name); } - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, - hw_data); + if (num_clks == 1) + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + hw_data->hws[0]); + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data); } #define TI_SYSCON_CLK_GATE(_name, _offset, _bit_idx) \ @@ -169,6 +194,11 @@ static const struct ti_syscon_gate_clk_d { /* Sentinel */ }, }; +static const struct ti_syscon_gate_clk_data am62_audio_clk_data[] = { + TI_SYSCON_CLK_GATE("audio_refclk", 0x0, 15), + { /* Sentinel */ }, +}; + static const struct of_device_id ti_syscon_gate_clk_ids[] = { { .compatible = "ti,am654-ehrpwm-tbclk", @@ -182,6 +212,10 @@ static const struct of_device_id ti_sysc .compatible = "ti,am62-epwm-tbclk", .data = &am62_clk_data, }, + { + .compatible = "ti,am62-audio-refclk", + .data = &am62_audio_clk_data, + }, { } }; MODULE_DEVICE_TABLE(of, ti_syscon_gate_clk_ids); Index: linux-6.1.80/drivers/counter/Kconfig =================================================================== --- linux-6.1.80.orig/drivers/counter/Kconfig +++ linux-6.1.80/drivers/counter/Kconfig @@ -61,7 +61,7 @@ config STM32_LPTIMER_CNT config TI_EQEP tristate "TI eQEP counter driver" - depends on (SOC_AM33XX || COMPILE_TEST) + depends on SOC_AM33XX || COMPILE_TEST || ARCH_K3 select REGMAP_MMIO help Select this option to enable the Texas Instruments Enhanced Quadrature Index: linux-6.1.80/drivers/counter/ti-eqep.c =================================================================== --- linux-6.1.80.orig/drivers/counter/ti-eqep.c +++ linux-6.1.80/drivers/counter/ti-eqep.c @@ -6,7 +6,9 @@ */ #include +#include #include +#include #include #include #include @@ -67,6 +69,59 @@ #define QEPCTL_UTE BIT(1) #define QEPCTL_WDE BIT(0) +#define QEINT_UTO BIT(11) +#define QEINT_IEL BIT(10) +#define QEINT_SEL BIT(9) +#define QEINT_PCM BIT(8) +#define QEINT_PCR BIT(7) +#define QEINT_PCO BIT(6) +#define QEINT_PCU BIT(5) +#define QEINT_WTO BIT(4) +#define QEINT_QDC BIT(3) +#define QEINT_PHE BIT(2) +#define QEINT_PCE BIT(1) + +#define QFLG_UTO BIT(11) +#define QFLG_IEL BIT(10) +#define QFLG_SEL BIT(9) +#define QFLG_PCM BIT(8) +#define QFLG_PCR BIT(7) +#define QFLG_PCO BIT(6) +#define QFLG_PCU BIT(5) +#define QFLG_WTO BIT(4) +#define QFLG_QDC BIT(3) +#define QFLG_PHE BIT(2) +#define QFLG_PCE BIT(1) +#define QFLG_INT BIT(0) + +#define QCLR_UTO BIT(11) +#define QCLR_IEL BIT(10) +#define QCLR_SEL BIT(9) +#define QCLR_PCM BIT(8) +#define QCLR_PCR BIT(7) +#define QCLR_PCO BIT(6) +#define QCLR_PCU BIT(5) +#define QCLR_WTO BIT(4) +#define QCLR_QDC BIT(3) +#define QCLR_PHE BIT(2) +#define QCLR_PCE BIT(1) +#define QCLR_INT BIT(0) + +#define QEPSTS_UPEVNT BIT(7) +#define QEPSTS_FDF BIT(6) +#define QEPSTS_QDF BIT(5) +#define QEPSTS_QDLF BIT(4) +#define QEPSTS_COEF BIT(3) +#define QEPSTS_CDEF BIT(2) +#define QEPSTS_FIMF BIT(1) +#define QEPSTS_PCEF BIT(0) + +#define QCAPCTL_CEN BIT(15) +#define QCAPCTL_CCPS_SHIFT 4 +#define QCAPCTL_CCPS GENMASK(6, 4) +#define QCAPCTL_UPPS_SHIFT 0 +#define QCAPCTL_UPPS GENMASK(3, 0) + /* EQEP Inputs */ enum { TI_EQEP_SIGNAL_QEPA, /* QEPA/XCLK */ @@ -83,6 +138,7 @@ enum ti_eqep_count_func { struct ti_eqep_cnt { struct counter_device counter; + unsigned long clock_rate; struct regmap *regmap32; struct regmap *regmap16; }; @@ -238,12 +294,54 @@ static int ti_eqep_action_read(struct co } } +static int ti_eqep_events_configure(struct counter_device *counter) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + struct counter_event_node *event_node; + u32 qeint = 0; + + list_for_each_entry(event_node, &counter->events_list, l) { + switch (event_node->event) { + case COUNTER_EVENT_OVERFLOW: + qeint |= QEINT_PCO; + break; + case COUNTER_EVENT_UNDERFLOW: + qeint |= QEINT_PCU; + break; + case COUNTER_EVENT_DIRECTION_CHANGE: + qeint |= QEINT_QDC; + break; + case COUNTER_EVENT_TIMEOUT: + qeint |= QEINT_UTO; + break; + } + } + + return regmap_write_bits(priv->regmap16, QEINT, qeint, ~0); +} + +static int ti_eqep_watch_validate(struct counter_device *counter, + const struct counter_watch *watch) +{ + switch (watch->event) { + case COUNTER_EVENT_OVERFLOW: + case COUNTER_EVENT_UNDERFLOW: + case COUNTER_EVENT_DIRECTION_CHANGE: + case COUNTER_EVENT_TIMEOUT: + return 0; + default: + return -EINVAL; + } +} + static const struct counter_ops ti_eqep_counter_ops = { .count_read = ti_eqep_count_read, .count_write = ti_eqep_count_write, .function_read = ti_eqep_function_read, .function_write = ti_eqep_function_write, .action_read = ti_eqep_action_read, + .events_configure = ti_eqep_events_configure, + .watch_validate = ti_eqep_watch_validate, }; static int ti_eqep_position_ceiling_read(struct counter_device *counter, @@ -265,11 +363,17 @@ static int ti_eqep_position_ceiling_writ u64 ceiling) { struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + u32 qposmax = ceiling; - if (ceiling != (u32)ceiling) + /* ensure that value fits in 32-bit register */ + if (qposmax != ceiling) return -ERANGE; - regmap_write(priv->regmap32, QPOSMAX, ceiling); + /* protect against infinite overflow interrupts */ + if (qposmax == 0) + return -EINVAL; + + regmap_write(priv->regmap32, QPOSMAX, qposmax); return 0; } @@ -297,11 +401,43 @@ static int ti_eqep_position_enable_write return 0; } +static int ti_eqep_direction_read(struct counter_device *counter, + struct counter_count *count, + enum counter_count_direction *direction) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + u32 qepsts; + + regmap_read(priv->regmap16, QEPSTS, &qepsts); + + *direction = (qepsts & QEPSTS_QDF) ? COUNTER_COUNT_DIRECTION_FORWARD + : COUNTER_COUNT_DIRECTION_BACKWARD; + + return 0; +} + +static int ti_eqep_position_latched_count_read(struct counter_device *counter, + struct counter_count *count, + u64 *value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + u32 qposlat; + + regmap_read(priv->regmap32, QPOSLAT, &qposlat); + + *value = qposlat; + + return 0; +} + static struct counter_comp ti_eqep_position_ext[] = { COUNTER_COMP_CEILING(ti_eqep_position_ceiling_read, ti_eqep_position_ceiling_write), COUNTER_COMP_ENABLE(ti_eqep_position_enable_read, ti_eqep_position_enable_write), + COUNTER_COMP_DIRECTION(ti_eqep_direction_read), + COUNTER_COMP_COUNT_U64("latched_count", + ti_eqep_position_latched_count_read, NULL), }; static struct counter_signal ti_eqep_signals[] = { @@ -354,6 +490,314 @@ static struct counter_count ti_eqep_coun }, }; +static int ti_eqep_edge_capture_unit_enable_read(struct counter_device *counter, + u8 *value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + u32 qcapctl; + + regmap_read(priv->regmap16, QCAPCTL, &qcapctl); + *value = !!(qcapctl & QCAPCTL_CEN); + + return 0; +} + +static int ti_eqep_edge_capture_unit_enable_write(struct counter_device *counter, + u8 value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + + if (value) + regmap_set_bits(priv->regmap16, QCAPCTL, QCAPCTL_CEN); + else + regmap_clear_bits(priv->regmap16, QCAPCTL, QCAPCTL_CEN); + + return 0; +} + +static int ti_eqep_edge_capture_unit_latched_period_read(struct counter_device *counter, + u64 *value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + u32 qcprdlat, qcapctl; + u8 ccps; + + regmap_read(priv->regmap16, QCPRDLAT, &qcprdlat); + regmap_read(priv->regmap16, QCAPCTL, &qcapctl); + ccps = (qcapctl & QCAPCTL_CCPS) >> QCAPCTL_CCPS_SHIFT; + + /* convert timer ticks to nanoseconds */ + *value = mul_u64_u32_div(qcprdlat << ccps, NSEC_PER_SEC, priv->clock_rate); + + return 0; +} + +static int ti_eqep_edge_capture_unit_max_period_read(struct counter_device *counter, + u64 *value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + u32 qcapctl; + u8 ccps; + + regmap_read(priv->regmap16, QCAPCTL, &qcapctl); + ccps = (qcapctl & QCAPCTL_CCPS) >> QCAPCTL_CCPS_SHIFT; + + /* convert timer ticks to nanoseconds */ + *value = mul_u64_u32_div(USHRT_MAX << ccps, NSEC_PER_SEC, + priv->clock_rate); + + return 0; +} + +static int ti_eqep_edge_capture_unit_max_period_write(struct counter_device *counter, + u64 value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + u32 period; + u8 ccps; + + /* convert nanoseconds to timer ticks */ + period = value = mul_u64_u32_div(value, priv->clock_rate, NSEC_PER_SEC); + if (period != value) + return -ERANGE; + + /* find the smallest divider that will fit the requested period */ + for (ccps = 0; ccps <= 7; ccps++) + if (USHRT_MAX << ccps >= period) + break; + + if (ccps > 7) + return -EINVAL; + + regmap_write_bits(priv->regmap16, QCAPCTL, QCAPCTL_CCPS, + ccps << QCAPCTL_CCPS_SHIFT); + + return 0; +} + +static int ti_eqep_edge_capture_unit_prescaler_read(struct counter_device *counter, + u32 *value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + u32 qcapctl; + + regmap_read(priv->regmap16, QCAPCTL, &qcapctl); + *value = (qcapctl & QCAPCTL_UPPS) >> QCAPCTL_UPPS_SHIFT; + + return 0; +} + +static int ti_eqep_edge_capture_unit_prescaler_write(struct counter_device *counter, + u32 value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + + regmap_write_bits(priv->regmap16, QCAPCTL, QCAPCTL_UPPS, + value << QCAPCTL_UPPS_SHIFT); + + return 0; +} + +static const char *const ti_eqep_edge_capture_unit_prescaler_values[] = { + "1", + "2", + "4", + "8", + "16", + "32", + "64", + "128", + "256", + "512", + "1024", + "2048", +}; + +static DEFINE_COUNTER_ENUM(ti_eqep_edge_capture_unit_prescaler_available, + ti_eqep_edge_capture_unit_prescaler_values); + +static int ti_eqep_latch_mode_read(struct counter_device *counter, + u32 *value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + u32 qepctl; + + regmap_read(priv->regmap16, QEPCTL, &qepctl); + *value = !!(qepctl & QEPCTL_QCLM); + + return 0; +} + +static int ti_eqep_latch_mode_write(struct counter_device *counter, + u32 value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + + if (value) + regmap_set_bits(priv->regmap16, QEPCTL, QEPCTL_QCLM); + else + regmap_clear_bits(priv->regmap16, QEPCTL, QEPCTL_QCLM); + + return 0; +} + +static const char *const ti_eqep_latch_mode_names[] = { + "Read count", + "Unit timeout", +}; + +static DEFINE_COUNTER_ENUM(ti_eqep_latch_modes, ti_eqep_latch_mode_names); + +static int ti_eqep_unit_timer_time_read(struct counter_device *counter, + u64 *value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + u32 qutmr; + + regmap_read(priv->regmap32, QUTMR, &qutmr); + + /* convert timer ticks to nanoseconds */ + *value = mul_u64_u32_div(qutmr, NSEC_PER_SEC, priv->clock_rate); + + return 0; +} + +static int ti_eqep_unit_timer_time_write(struct counter_device *counter, + u64 value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + u32 qutmr; + + /* convert nanoseconds to timer ticks */ + qutmr = value = mul_u64_u32_div(value, priv->clock_rate, NSEC_PER_SEC); + if (qutmr != value) + return -ERANGE; + + regmap_write(priv->regmap32, QUTMR, qutmr); + + return 0; +} + +static int ti_eqep_unit_timer_period_read(struct counter_device *counter, + u64 *value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + u32 quprd; + + regmap_read(priv->regmap32, QUPRD, &quprd); + + /* convert timer ticks to nanoseconds */ + *value = mul_u64_u32_div(quprd, NSEC_PER_SEC, priv->clock_rate); + + return 0; +} + +static int ti_eqep_unit_timer_period_write(struct counter_device *counter, + u64 value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + u32 quprd; + + /* convert nanoseconds to timer ticks */ + quprd = value = mul_u64_u32_div(value, priv->clock_rate, NSEC_PER_SEC); + if (quprd != value) + return -ERANGE; + + /* protect against infinite unit timeout interrupts */ + if (quprd == 0) + return -EINVAL; + + regmap_write(priv->regmap32, QUPRD, quprd); + + return 0; +} + +static int ti_eqep_unit_timer_enable_read(struct counter_device *counter, + u8 *value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + u32 qepctl; + + regmap_read(priv->regmap16, QEPCTL, &qepctl); + *value = !!(qepctl & QEPCTL_UTE); + + return 0; +} + +static int ti_eqep_unit_timer_enable_write(struct counter_device *counter, + u8 value) +{ + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); + + if (value) + regmap_set_bits(priv->regmap16, QEPCTL, QEPCTL_UTE); + else + regmap_clear_bits(priv->regmap16, QEPCTL, QEPCTL_UTE); + + return 0; +} + +static struct counter_comp ti_eqep_device_ext[] = { + COUNTER_COMP_DEVICE_BOOL("edge_capture_unit_enable", + ti_eqep_edge_capture_unit_enable_read, + ti_eqep_edge_capture_unit_enable_write), + COUNTER_COMP_DEVICE_U64("edge_capture_unit_latched_period", + ti_eqep_edge_capture_unit_latched_period_read, + NULL), + COUNTER_COMP_DEVICE_U64("edge_capture_unit_max_period", + ti_eqep_edge_capture_unit_max_period_read, + ti_eqep_edge_capture_unit_max_period_write), + COUNTER_COMP_DEVICE_ENUM("edge_capture_unit_prescaler", + ti_eqep_edge_capture_unit_prescaler_read, + ti_eqep_edge_capture_unit_prescaler_write, + ti_eqep_edge_capture_unit_prescaler_available), + COUNTER_COMP_DEVICE_ENUM("latch_mode", ti_eqep_latch_mode_read, + ti_eqep_latch_mode_write, ti_eqep_latch_modes), + COUNTER_COMP_DEVICE_U64("unit_timer_time", ti_eqep_unit_timer_time_read, + ti_eqep_unit_timer_time_write), + COUNTER_COMP_DEVICE_U64("unit_timer_period", + ti_eqep_unit_timer_period_read, + ti_eqep_unit_timer_period_write), + COUNTER_COMP_DEVICE_BOOL("unit_timer_enable", + ti_eqep_unit_timer_enable_read, + ti_eqep_unit_timer_enable_write), +}; + +static irqreturn_t ti_eqep_irq_handler(int irq, void *dev_id) +{ + struct ti_eqep_cnt *priv = dev_id; + struct counter_device *counter = &priv->counter; + u32 qflg; + u32 qclr = 0; + + regmap_read(priv->regmap16, QFLG, &qflg); + + if (qflg & QFLG_PCO) { + qclr |= QFLG_PCO; + counter_push_event(counter, COUNTER_EVENT_OVERFLOW, 0); + } + + if (qflg & QFLG_PCU) { + qclr |= QFLG_PCU; + counter_push_event(counter, COUNTER_EVENT_UNDERFLOW, 0); + } + + if (qflg & QFLG_QDC) { + qclr |= QFLG_QDC; + counter_push_event(counter, COUNTER_EVENT_DIRECTION_CHANGE, 0); + } + + if (qflg & QFLG_UTO) { + qclr |= QFLG_UTO; + counter_push_event(counter, COUNTER_EVENT_TIMEOUT, 0); + } + + qclr |= QCLR_INT; + regmap_write_bits(priv->regmap16, QCLR, qclr, ~0); + + return IRQ_HANDLED; +} + static const struct regmap_config ti_eqep_regmap32_config = { .name = "32-bit", .reg_bits = 32, @@ -375,14 +819,29 @@ static int ti_eqep_probe(struct platform struct device *dev = &pdev->dev; struct counter_device *counter; struct ti_eqep_cnt *priv; + struct clk *clk; void __iomem *base; int err; + int irq; counter = devm_counter_alloc(dev, sizeof(*priv)); if (!counter) return -ENOMEM; priv = counter_priv(counter); + clk = devm_clk_get(dev, "fck"); + if (IS_ERR(clk)) { + if (PTR_ERR(clk) != -EPROBE_DEFER) + dev_err(dev, "failed to get fck clock"); + return PTR_ERR(clk); + } + + priv->clock_rate = clk_get_rate(clk); + if (priv->clock_rate == 0) { + dev_err(dev, "failed to get fck clock rate"); + return -EINVAL; + } + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); @@ -397,11 +856,22 @@ static int ti_eqep_probe(struct platform if (IS_ERR(priv->regmap16)) return PTR_ERR(priv->regmap16); + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + err = devm_request_threaded_irq(dev, irq, NULL, ti_eqep_irq_handler, + IRQF_ONESHOT, dev_name(dev), priv); + if (err < 0) + return err; + counter->name = dev_name(dev); counter->parent = dev; counter->ops = &ti_eqep_counter_ops; counter->counts = ti_eqep_counts; counter->num_counts = ARRAY_SIZE(ti_eqep_counts); + counter->ext = ti_eqep_device_ext; + counter->num_ext = ARRAY_SIZE(ti_eqep_device_ext); counter->signals = ti_eqep_signals; counter->num_signals = ARRAY_SIZE(ti_eqep_signals); @@ -415,6 +885,14 @@ static int ti_eqep_probe(struct platform pm_runtime_enable(dev); pm_runtime_get_sync(dev); + /* + * We can end up with an interrupt infinite loop (interrupts triggered + * as soon as they are cleared) if we leave these at the default value + * of 0 and events are enabled. + */ + regmap_write(priv->regmap32, QPOSMAX, UINT_MAX); + regmap_write(priv->regmap32, QUPRD, UINT_MAX); + err = counter_add(counter); if (err < 0) { pm_runtime_put_sync(dev); Index: linux-6.1.80/drivers/cpufreq/Kconfig.arm =================================================================== --- linux-6.1.80.orig/drivers/cpufreq/Kconfig.arm +++ linux-6.1.80/drivers/cpufreq/Kconfig.arm @@ -340,8 +340,8 @@ config ARM_TEGRA194_CPUFREQ config ARM_TI_CPUFREQ bool "Texas Instruments CPUFreq support" - depends on ARCH_OMAP2PLUS - default ARCH_OMAP2PLUS + depends on ARCH_OMAP2PLUS || ARCH_K3 + default y help This driver enables valid OPPs on the running platform based on values contained within the SoC in use. Enable this in order to Index: linux-6.1.80/drivers/cpufreq/cpufreq-dt-platdev.c =================================================================== --- linux-6.1.80.orig/drivers/cpufreq/cpufreq-dt-platdev.c +++ linux-6.1.80/drivers/cpufreq/cpufreq-dt-platdev.c @@ -162,6 +162,9 @@ static const struct of_device_id blockli { .compatible = "ti,am43", }, { .compatible = "ti,dra7", }, { .compatible = "ti,omap3", }, + { .compatible = "ti,am625", }, + { .compatible = "ti,am62a7", }, + { .compatible = "ti,am62p5", }, { .compatible = "qcom,ipq8064", }, { .compatible = "qcom,apq8064", }, Index: linux-6.1.80/drivers/cpufreq/ti-cpufreq.c =================================================================== --- linux-6.1.80.orig/drivers/cpufreq/ti-cpufreq.c +++ linux-6.1.80/drivers/cpufreq/ti-cpufreq.c @@ -39,6 +39,16 @@ #define OMAP34xx_ProdID_SKUID 0x4830A20C #define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270) +#define AM625_EFUSE_K_MPU_OPP 11 +#define AM625_EFUSE_S_MPU_OPP 19 +#define AM625_EFUSE_T_MPU_OPP 20 +#define AM625_EFUSE_U_MPU_OPP 21 +#define AM625_EFUSE_V_MPU_OPP 22 + +#define AM625_SUPPORT_K_MPU_OPP BIT(0) +#define AM625_SUPPORT_S_MPU_OPP BIT(1) +#define AM625_SUPPORT_T_MPU_OPP BIT(2) + #define VERSION_COUNT 2 struct ti_cpufreq_data; @@ -104,6 +114,27 @@ static unsigned long omap3_efuse_xlate(s return BIT(efuse); } +static unsigned long am625_efuse_xlate(struct ti_cpufreq_data *opp_data, + unsigned long efuse) +{ + unsigned long calculated_efuse = AM625_SUPPORT_K_MPU_OPP; + + switch (efuse) { + case AM625_EFUSE_V_MPU_OPP: + case AM625_EFUSE_U_MPU_OPP: + case AM625_EFUSE_T_MPU_OPP: + calculated_efuse |= AM625_SUPPORT_T_MPU_OPP; + fallthrough; + case AM625_EFUSE_S_MPU_OPP: + calculated_efuse |= AM625_SUPPORT_S_MPU_OPP; + fallthrough; + case AM625_EFUSE_K_MPU_OPP: + calculated_efuse |= AM625_SUPPORT_K_MPU_OPP; + } + + return calculated_efuse; +} + static struct ti_cpufreq_soc_data am3x_soc_data = { .efuse_xlate = amx3_efuse_xlate, .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ, @@ -198,6 +229,14 @@ static struct ti_cpufreq_soc_data am3517 .multi_regulator = false, }; +static struct ti_cpufreq_soc_data am625_soc_data = { + .efuse_xlate = am625_efuse_xlate, + .efuse_offset = 0x0018, + .efuse_mask = 0x07c0, + .efuse_shift = 0x6, + .rev_offset = 0x0014, + .multi_regulator = false, +}; /** * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC @@ -301,6 +340,9 @@ static const struct of_device_id ti_cpuf { .compatible = "ti,dra7", .data = &dra7_soc_data }, { .compatible = "ti,omap34xx", .data = &omap34xx_soc_data, }, { .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, }, + { .compatible = "ti,am625", .data = &am625_soc_data, }, + { .compatible = "ti,am62a7", .data = &am625_soc_data, }, + { .compatible = "ti,am62p5", .data = &am625_soc_data, }, /* legacy */ { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, }, { .compatible = "ti,omap3630", .data = &omap36xx_soc_data, }, Index: linux-6.1.80/drivers/crypto/Kconfig =================================================================== --- linux-6.1.80.orig/drivers/crypto/Kconfig +++ linux-6.1.80/drivers/crypto/Kconfig @@ -824,4 +824,6 @@ config CRYPTO_DEV_SA2UL source "drivers/crypto/keembay/Kconfig" source "drivers/crypto/aspeed/Kconfig" +source "drivers/crypto/ti/Kconfig" + endif # CRYPTO_HW Index: linux-6.1.80/drivers/crypto/Makefile =================================================================== --- linux-6.1.80.orig/drivers/crypto/Makefile +++ linux-6.1.80/drivers/crypto/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahar obj-$(CONFIG_CRYPTO_DEV_SL3516) += gemini/ obj-$(CONFIG_ARCH_STM32) += stm32/ obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o +obj-$(CONFIG_ARCH_K3) += ti/ obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/ obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/ obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/ Index: linux-6.1.80/drivers/crypto/sa2ul.h =================================================================== --- linux-6.1.80.orig/drivers/crypto/sa2ul.h +++ linux-6.1.80/drivers/crypto/sa2ul.h @@ -170,7 +170,7 @@ struct sa_tfm_ctx; * the following range, so avoid using it. */ #define SA_UNSAFE_DATA_SZ_MIN 240 -#define SA_UNSAFE_DATA_SZ_MAX 256 +#define SA_UNSAFE_DATA_SZ_MAX 255 struct sa_match_data; Index: linux-6.1.80/drivers/crypto/ti/Kconfig =================================================================== --- /dev/null +++ linux-6.1.80/drivers/crypto/ti/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only +config CRYPTO_DEV_TI_MCRC64 + tristate "Support for TI MCRC64 crc accelerators" + depends on ARCH_K3 + select CRYPTO_HASH + help + This enables support for the MCRC hw accelerator + which can be found on TI SOC. + MCRC support 64-bit CRC calculation using + Full-CPU mode. \ No newline at end of file Index: linux-6.1.80/drivers/crypto/ti/Makefile =================================================================== --- /dev/null +++ linux-6.1.80/drivers/crypto/ti/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_CRYPTO_DEV_TI_MCRC64) += mcrc.o Index: linux-6.1.80/drivers/crypto/ti/mcrc.c =================================================================== --- /dev/null +++ linux-6.1.80/drivers/crypto/ti/mcrc.c @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) Texas Instruments 2023 - http://www.ti.com + * Author: Kamlesh Gurudasani + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#define DRIVER_NAME "ti-mcrc" +#define CHKSUM_DIGEST_SIZE 8 +#define CHKSUM_BLOCK_SIZE 1 + +/* Registers */ +#define CRC_CTRL0 0x0000 /* CRC Global Control Register 0 */ +#define CH_PSA_SWRE(ch) BIT(((ch) - 1) << 3) /* PSA Software Reset */ + +#define CRC_CTRL1 0x0008 /* CRC Global Control Register 1 */ +#define PWDN BIT(0) /* Power Down */ + +#define CRC_CTRL2 0x0010 /* CRC Global Control Register 2 */ +#define CH_MODE(ch, m) ((m) << (((ch) - 1) << 3)) + +#define PSA_SIGREGL(ch) ((0x6 + (4 * ((ch) - 1))) << 4) /* Signature register */ + +#define MCRC_ALG_MASK 0x8000000000000000 +#define MCRC_CRC64_POLY 0x000000000000001b + +#define MCRC_AUTOSUSPEND_DELAY 50 + +static struct device *mcrc_k3_dev; + +static unsigned int burst_size; + +module_param(burst_size, uint, 0644); +MODULE_PARM_DESC(burst_size, "Select burst byte size (0 unlimited)"); + +enum mcrc_mode { + MCRC_MODE_DATA_CAPTURE = 0, + MCRC_MODE_AUTO, + MCRC_MODE_SEMI_CPU, + MCRC_MODE_FULL_CPU, + MCRC_MODE_INVALID, +}; + +enum mcrc_channel { + MCRC_CHANNEL_1 = 1, + MCRC_CHANNEL_2, + MCRC_CHANNEL_3, + MCRC_CHANNEL_4, + MCRC_CHANNEL_INVALID, +}; + +struct mcrc_data { + struct device *dev; + void __iomem *regs; +}; + +struct mcrc_ctx { + u32 key; +}; + +struct mcrc_desc_ctx { + u64 signature; +}; + +static int mcrc_set_mode(void __iomem *regs, u32 channel, u32 mode) +{ + u32 crc_ctrl2_reg, mode_set_val; + + if (mode < 0 || mode >= MCRC_MODE_INVALID) + return -EINVAL; + + if (channel <= 0 || channel >= MCRC_CHANNEL_INVALID) + return -EINVAL; + + crc_ctrl2_reg = readl_relaxed(regs + CRC_CTRL2); + + mode_set_val = crc_ctrl2_reg | CH_MODE(channel, mode); + + /* Write CRC_CTRL2, set mode */ + writel_relaxed(mode_set_val, regs + CRC_CTRL2); + + return 0; +} + +static int mcrc_reset_signature(void __iomem *regs, u32 channel) +{ + u32 crc_ctrl0_reg, reset_val, reset_undo_val; + + if (channel <= 0 || channel >= MCRC_CHANNEL_INVALID) + return -EINVAL; + + /* reset PSA */ + crc_ctrl0_reg = readl_relaxed(regs + CRC_CTRL0); + + reset_val = crc_ctrl0_reg | CH_PSA_SWRE(channel); + reset_undo_val = crc_ctrl0_reg & ~CH_PSA_SWRE(channel); + + /* Write CRC_CTRL0 register, reset PSA register */ + writel_relaxed(reset_val, regs + CRC_CTRL0); + writel_relaxed(reset_undo_val, regs + CRC_CTRL0); + + return 0; +} + +/* This helper implements crc64 calculation using CPU */ +static u64 mcrc_calculate_sw_crc(u64 crc, u8 byte) +{ + u64 bit = 0; + u8 j; + + for (j = 0; j < 8; j++) { + bit = crc & MCRC_ALG_MASK; + crc <<= 1; + if (byte & (0x80 >> j)) + bit ^= MCRC_ALG_MASK; + if (bit) + crc ^= MCRC_CRC64_POLY; + } + + return crc; +} + +static int mcrc_calculate_crc(void __iomem *regs, u32 channel, + const u8 *d8, size_t length, u64 *crc64) +{ + void __iomem *psa_reg; + u64 signature = 0; + + if (channel <= 0 || channel >= MCRC_CHANNEL_INVALID) + return -EINVAL; + + psa_reg = regs + PSA_SIGREGL(channel); + + for (; length >= sizeof(u64); d8 += sizeof(u64), length -= sizeof(u64)) { + writeq_relaxed(cpu_to_be64p((u64 *)d8), psa_reg); + signature = readq_relaxed(psa_reg); + } + + while (length--) + signature = mcrc_calculate_sw_crc(signature, *d8++); + + *crc64 = signature; + + return 0; +} + +static int mcrc_cra_init(struct crypto_tfm *tfm) +{ + struct mcrc_ctx *mctx = crypto_tfm_ctx(tfm); + + struct mcrc_data *dev_data = dev_get_drvdata(mcrc_k3_dev); + + pm_runtime_get_sync(dev_data->dev); + + mctx->key = 0; + + return 0; +} + +static void mcrc_cra_exit(struct crypto_tfm *tfm) +{ + struct mcrc_data *dev_data = dev_get_drvdata(mcrc_k3_dev); + + pm_runtime_mark_last_busy(dev_data->dev); + pm_runtime_put_autosuspend(dev_data->dev); +} + +static int mcrc_setkey(struct crypto_shash *tfm, const u8 *key, + unsigned int keylen) +{ + struct mcrc_ctx *mctx = crypto_shash_ctx(tfm); + + if (keylen != sizeof(u32)) + return -EINVAL; + + mctx->key = get_unaligned_le32(key); + + return 0; +} + +static int mcrc_init(struct shash_desc *desc) +{ + struct mcrc_data *dev_data = dev_get_drvdata(mcrc_k3_dev); + + /* set full cpu mode */ + int ret = mcrc_set_mode(dev_data->regs, MCRC_CHANNEL_1, + MCRC_MODE_FULL_CPU); + if (ret) + return ret; + + /* reset PSA */ + return mcrc_reset_signature(dev_data->regs, MCRC_CHANNEL_1); +} + +static int burst_update(struct shash_desc *desc, const u8 *d8, + size_t length) +{ + struct mcrc_desc_ctx *ctx = shash_desc_ctx(desc); + struct mcrc_data *dev_data = dev_get_drvdata(mcrc_k3_dev); + + return mcrc_calculate_crc(dev_data->regs, MCRC_CHANNEL_1, + d8, length, &ctx->signature); +} + +static int mcrc_update(struct shash_desc *desc, const u8 *d8, + unsigned int length) +{ + const unsigned int burst_sz = burst_size; + unsigned int rem_sz; + const u8 *cur; + size_t size; + int ret; + + if (!burst_sz) + return burst_update(desc, d8, length); + + /* Digest first bytes not 64bit aligned at first pass in the loop */ + size = min_t(size_t, length, burst_sz + (size_t)d8 - + ALIGN_DOWN((size_t)d8, sizeof(u64))); + for (rem_sz = length, cur = d8; rem_sz; + rem_sz -= size, cur += size, size = min(rem_sz, burst_sz)) { + ret = burst_update(desc, cur, size); + if (ret) + return ret; + } + + return 0; +} + +static int mcrc_final(struct shash_desc *desc, u8 *out) +{ + struct mcrc_desc_ctx *ctx = shash_desc_ctx(desc); + + /* Send computed CRC */ + put_unaligned_le64(ctx->signature, out); + return 0; +} + +static int mcrc_finup(struct shash_desc *desc, const u8 *data, + unsigned int length, u8 *out) +{ + return mcrc_update(desc, data, length) ?: + mcrc_final(desc, out); +} + +static int mcrc_digest(struct shash_desc *desc, const u8 *data, + unsigned int length, u8 *out) +{ + return mcrc_init(desc) ?: mcrc_finup(desc, data, length, out); +} + +static struct shash_alg algs[] = { + /* CRC-64 */ + { + .setkey = mcrc_setkey, + .init = mcrc_init, + .update = mcrc_update, + .final = mcrc_final, + .finup = mcrc_finup, + .digest = mcrc_digest, + .descsize = sizeof(struct mcrc_desc_ctx), + .digestsize = CHKSUM_DIGEST_SIZE, + .base = { + .cra_name = "crc64", + .cra_driver_name = "mcrc", + .cra_priority = 200, + .cra_flags = CRYPTO_ALG_OPTIONAL_KEY, + .cra_blocksize = CHKSUM_BLOCK_SIZE, + .cra_alignmask = 7, + .cra_ctxsize = sizeof(struct mcrc_ctx), + .cra_module = THIS_MODULE, + .cra_init = mcrc_cra_init, + .cra_exit = mcrc_cra_exit, + } + } +}; + +static int mcrc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mcrc_data *dev_data; + + dev_data = devm_kzalloc(dev, sizeof(*dev_data), GFP_KERNEL); + if (!dev_data) + return -ENOMEM; + + mcrc_k3_dev = dev; + dev_data->dev = dev; + dev_data->regs = devm_platform_ioremap_resource(pdev, 0); + + platform_set_drvdata(pdev, dev_data); + dev_set_drvdata(mcrc_k3_dev, dev_data); + + crypto_register_shashes(algs, ARRAY_SIZE(algs)); + + pm_runtime_set_autosuspend_delay(dev, MCRC_AUTOSUSPEND_DELAY); + pm_runtime_use_autosuspend(dev); + + pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + pm_runtime_put_sync(dev); + + return 0; +} + +static int mcrc_remove(struct platform_device *pdev) +{ + struct mcrc_data *dev_data = platform_get_drvdata(pdev); + + int ret = pm_runtime_get_sync(dev_data->dev); + + if (ret < 0) { + pm_runtime_put_noidle(dev_data->dev); + return ret; + } + + crypto_unregister_shashes(algs, ARRAY_SIZE(algs)); + + pm_runtime_disable(dev_data->dev); + pm_runtime_put_noidle(dev_data->dev); + + return 0; +} + +static int __maybe_unused mcrc_suspend(struct device *dev) +{ + return pm_runtime_force_suspend(dev); +} + +static int __maybe_unused mcrc_resume(struct device *dev) +{ + return pm_runtime_force_resume(dev); +} + +static const struct dev_pm_ops mcrc_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(mcrc_suspend, + mcrc_resume) +}; + +static const struct of_device_id of_match[] = { + { .compatible = "ti,mcrc", }, + {}, +}; +MODULE_DEVICE_TABLE(of, of_match); + +static struct platform_driver mcrc_driver = { + .probe = mcrc_probe, + .remove = mcrc_remove, + .driver = { + .name = DRIVER_NAME, + .pm = &mcrc_pm_ops, + .of_match_table = of_match, + }, +}; + +module_platform_driver(mcrc_driver); + +MODULE_AUTHOR("Kamlesh Gurudasani "); +MODULE_DESCRIPTION("Texas Instruments MCRC hardware driver"); +MODULE_LICENSE("GPL"); Index: linux-6.1.80/drivers/dma-buf/dma-heap.c =================================================================== --- linux-6.1.80.orig/drivers/dma-buf/dma-heap.c +++ linux-6.1.80/drivers/dma-buf/dma-heap.c @@ -323,4 +323,4 @@ static int dma_heap_init(void) return 0; } -subsys_initcall(dma_heap_init); +core_initcall(dma_heap_init); Index: linux-6.1.80/drivers/dma-buf/heaps/Kconfig =================================================================== --- linux-6.1.80.orig/drivers/dma-buf/heaps/Kconfig +++ linux-6.1.80/drivers/dma-buf/heaps/Kconfig @@ -12,3 +12,13 @@ config DMABUF_HEAPS_CMA Choose this option to enable dma-buf CMA heap. This heap is backed by the Contiguous Memory Allocator (CMA). If your system has these regions, you should say Y here. + +config DMABUF_HEAPS_CARVEOUT + bool "DMA-BUF Carveout Heap" + depends on DMABUF_HEAPS && HAS_IOMEM + depends on OF_RESERVED_MEM + select GENERIC_ALLOCATOR + help + Choose this option to enable dma-buf Carveout heap. This heap is + backed by the a carved-out of memory. If your system has these + regions, you should say Y here. Index: linux-6.1.80/drivers/dma-buf/heaps/Makefile =================================================================== --- linux-6.1.80.orig/drivers/dma-buf/heaps/Makefile +++ linux-6.1.80/drivers/dma-buf/heaps/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_DMABUF_HEAPS_SYSTEM) += system_heap.o obj-$(CONFIG_DMABUF_HEAPS_CMA) += cma_heap.o +obj-$(CONFIG_DMABUF_HEAPS_CARVEOUT) += carveout-heap.o Index: linux-6.1.80/drivers/dma-buf/heaps/carveout-heap.c =================================================================== --- /dev/null +++ linux-6.1.80/drivers/dma-buf/heaps/carveout-heap.c @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Carveout DMA-Heap userspace exporter + * + * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Andrew Davis + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct carveout_dma_heap { + struct dma_heap *heap; + struct gen_pool *pool; + bool cached; +}; + +struct carveout_dma_heap_buffer { + struct gen_pool *pool; + struct list_head attachments; + struct mutex attachments_lock; + struct mutex vmap_lock; + int vmap_cnt; + unsigned long len; + void *vaddr; + phys_addr_t paddr; + bool cached; +}; + +struct dma_heap_attachment { + struct device *dev; + struct sg_table *table; + struct list_head list; +}; + +static int dma_heap_attach(struct dma_buf *dmabuf, + struct dma_buf_attachment *attachment) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + struct dma_heap_attachment *a; + struct sg_table *table; + + a = kzalloc(sizeof(*a), GFP_KERNEL); + if (!a) + return -ENOMEM; + + table = kmalloc(sizeof(*table), GFP_KERNEL); + if (!table) { + kfree(a); + return -ENOMEM; + } + if (sg_alloc_table(table, 1, GFP_KERNEL)) { + kfree(a); + return -ENOMEM; + } + sg_set_page(table->sgl, pfn_to_page(PFN_DOWN(buffer->paddr)), buffer->len, 0); + + a->table = table; + a->dev = attachment->dev; + INIT_LIST_HEAD(&a->list); + + attachment->priv = a; + + mutex_lock(&buffer->attachments_lock); + list_add(&a->list, &buffer->attachments); + mutex_unlock(&buffer->attachments_lock); + + return 0; +} + +static void dma_heap_detatch(struct dma_buf *dmabuf, + struct dma_buf_attachment *attachment) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + struct dma_heap_attachment *a = attachment->priv; + + mutex_lock(&buffer->attachments_lock); + list_del(&a->list); + mutex_unlock(&buffer->attachments_lock); + + sg_free_table(a->table); + kfree(a->table); + kfree(a); +} + +static struct sg_table *dma_heap_map_dma_buf(struct dma_buf_attachment *attachment, + enum dma_data_direction direction) +{ + struct carveout_dma_heap_buffer *buffer = attachment->dmabuf->priv; + struct dma_heap_attachment *a = attachment->priv; + struct sg_table *table = a->table; + + unsigned long attrs = buffer->cached ? 0 : DMA_ATTR_SKIP_CPU_SYNC; + + if (!dma_map_sg_attrs(attachment->dev, table->sgl, table->nents, + direction, attrs)) + return ERR_PTR(-ENOMEM); + + return table; +} + +static void dma_heap_unmap_dma_buf(struct dma_buf_attachment *attachment, + struct sg_table *table, + enum dma_data_direction direction) +{ + struct carveout_dma_heap_buffer *buffer = attachment->dmabuf->priv; + unsigned long attrs = buffer->cached ? 0 : DMA_ATTR_SKIP_CPU_SYNC; + + dma_unmap_sg_attrs(attachment->dev, table->sgl, table->nents, + direction, attrs); +} + +static void dma_heap_dma_buf_release(struct dma_buf *dmabuf) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + + if (buffer->vmap_cnt > 0) { + WARN(1, "%s: buffer still mapped in the kernel\n", __func__); + memunmap(buffer->vaddr); + } + + gen_pool_free(buffer->pool, buffer->paddr, buffer->len); + kfree(buffer); +} + +static int dma_heap_dma_buf_begin_cpu_access(struct dma_buf *dmabuf, + enum dma_data_direction direction) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + struct dma_heap_attachment *a; + + if (!buffer->cached) + return 0; + + mutex_lock(&buffer->vmap_lock); + if (buffer->vmap_cnt) + invalidate_kernel_vmap_range(buffer->vaddr, buffer->len); + mutex_unlock(&buffer->vmap_lock); + + mutex_lock(&buffer->attachments_lock); + list_for_each_entry(a, &buffer->attachments, list) { + dma_sync_sg_for_cpu(a->dev, a->table->sgl, a->table->nents, + direction); + } + mutex_unlock(&buffer->attachments_lock); + + return 0; +} + +static int dma_heap_dma_buf_end_cpu_access(struct dma_buf *dmabuf, + enum dma_data_direction direction) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + struct dma_heap_attachment *a; + + if (!buffer->cached) + return 0; + + mutex_lock(&buffer->vmap_lock); + if (buffer->vmap_cnt) + flush_kernel_vmap_range(buffer->vaddr, buffer->len); + mutex_unlock(&buffer->vmap_lock); + + mutex_lock(&buffer->attachments_lock); + list_for_each_entry(a, &buffer->attachments, list) { + dma_sync_sg_for_device(a->dev, a->table->sgl, a->table->nents, + direction); + } + mutex_unlock(&buffer->attachments_lock); + + return 0; +} + +static int dma_heap_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + int ret; + + if (!buffer->cached) + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + + ret = vm_iomap_memory(vma, buffer->paddr, buffer->len); + if (ret) + pr_err("Could not map buffer to userspace\n"); + + return ret; +} + +static int dma_heap_vmap(struct dma_buf *dmabuf, struct iosys_map *map) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + void *vaddr; + int ret = 0; + + mutex_lock(&buffer->vmap_lock); + + if (buffer->vmap_cnt) { + buffer->vmap_cnt++; + iosys_map_set_vaddr(map, buffer->vaddr); + goto exit; + } + if (buffer->cached) + vaddr = memremap(buffer->paddr, buffer->len, MEMREMAP_WB); + else + vaddr = memremap(buffer->paddr, buffer->len, MEMREMAP_WC); + if (!vaddr) { + pr_err("Could not memremap buffer\n"); + ret = -ENOMEM; + goto exit; + } + if (IS_ERR(vaddr)) { + ret = PTR_ERR(vaddr); + goto exit; + } + + buffer->vaddr = vaddr; + buffer->vmap_cnt++; + iosys_map_set_vaddr(map, buffer->vaddr); +exit: + mutex_unlock(&buffer->vmap_lock); + + return ret; +} + +static void dma_heap_vunmap(struct dma_buf *dmabuf, struct iosys_map *map) +{ + struct carveout_dma_heap_buffer *buffer = dmabuf->priv; + + mutex_lock(&buffer->vmap_lock); + if (!--buffer->vmap_cnt) { + memunmap(buffer->vaddr); + buffer->vaddr = NULL; + } + mutex_unlock(&buffer->vmap_lock); +} + +static const struct dma_buf_ops carveout_dma_heap_buf_ops = { + .attach = dma_heap_attach, + .detach = dma_heap_detatch, + .map_dma_buf = dma_heap_map_dma_buf, + .unmap_dma_buf = dma_heap_unmap_dma_buf, + .release = dma_heap_dma_buf_release, + .begin_cpu_access = dma_heap_dma_buf_begin_cpu_access, + .end_cpu_access = dma_heap_dma_buf_end_cpu_access, + .mmap = dma_heap_mmap, + .vmap = dma_heap_vmap, + .vunmap = dma_heap_vunmap, +}; + +static struct dma_buf *carveout_dma_heap_allocate(struct dma_heap *heap, + unsigned long len, + unsigned long fd_flags, + unsigned long heap_flags) +{ + struct carveout_dma_heap *carveout_dma_heap = dma_heap_get_drvdata(heap); + struct carveout_dma_heap_buffer *buffer; + + DEFINE_DMA_BUF_EXPORT_INFO(exp_info); + struct dma_buf *dmabuf; + int ret = 0; + + buffer = kzalloc(sizeof(*buffer), GFP_KERNEL); + if (!buffer) + return ERR_PTR(ret); + buffer->pool = carveout_dma_heap->pool; + buffer->cached = carveout_dma_heap->cached; + INIT_LIST_HEAD(&buffer->attachments); + mutex_init(&buffer->attachments_lock); + mutex_init(&buffer->vmap_lock); + buffer->len = len; + + buffer->paddr = gen_pool_alloc(buffer->pool, buffer->len); + if (!buffer->paddr) { + ret = -ENOMEM; + goto free_buffer; + } + + /* create the dmabuf */ + exp_info.exp_name = dma_heap_get_name(heap); + exp_info.ops = &carveout_dma_heap_buf_ops; + exp_info.size = buffer->len; + exp_info.flags = fd_flags; + exp_info.priv = buffer; + dmabuf = dma_buf_export(&exp_info); + if (IS_ERR(dmabuf)) { + ret = PTR_ERR(dmabuf); + goto free_pool; + } + + return dmabuf; + +free_pool: + gen_pool_free(buffer->pool, buffer->paddr, buffer->len); +free_buffer: + kfree(buffer); + + return ERR_PTR(ret); +} + +static struct dma_heap_ops carveout_dma_heap_ops = { + .allocate = carveout_dma_heap_allocate, +}; + +static int carveout_dma_heap_export(phys_addr_t base, size_t size, const char *name, bool cached) +{ + struct carveout_dma_heap *carveout_dma_heap; + struct dma_heap_export_info exp_info; + int ret; + + carveout_dma_heap = kzalloc(sizeof(*carveout_dma_heap), GFP_KERNEL); + if (!carveout_dma_heap) + return -ENOMEM; + + carveout_dma_heap->pool = gen_pool_create(PAGE_SHIFT, NUMA_NO_NODE); + if (IS_ERR(carveout_dma_heap->pool)) { + pr_err("Carveout Heap: Could not create memory pool\n"); + ret = PTR_ERR(carveout_dma_heap->pool); + goto free_carveout_dma_heap; + } + ret = gen_pool_add(carveout_dma_heap->pool, base, size, NUMA_NO_NODE); + if (ret) { + pr_err("Carveout Heap: Could not add memory to pool\n"); + goto free_pool; + } + + carveout_dma_heap->cached = cached; + + exp_info.name = kasprintf(GFP_KERNEL, "carveout_%s", name); + exp_info.ops = &carveout_dma_heap_ops; + exp_info.priv = carveout_dma_heap; + carveout_dma_heap->heap = dma_heap_add(&exp_info); + if (IS_ERR(carveout_dma_heap->heap)) { + pr_err("Carveout Heap: Could not add DMA-Heap\n"); + ret = PTR_ERR(carveout_dma_heap->heap); + goto free_pool; + } + + pr_info("Carveout Heap: Exported %zu MiB at %pa\n", size / SZ_1M, &base); + + return 0; + +free_pool: + gen_pool_destroy(carveout_dma_heap->pool); +free_carveout_dma_heap: + kfree(carveout_dma_heap); + return ret; +} + +#ifdef CONFIG_OF_RESERVED_MEM +#include +#include +#include + +#define MAX_HEAP_AREAS 7 +struct reserved_mem heap_areas[MAX_HEAP_AREAS]; +size_t heap_area_count; + +static int __init carveout_dma_heap_init_areas(void) +{ + int i; + + for (i = 0; i < heap_area_count; i++) { + struct reserved_mem *rmem = &heap_areas[i]; + bool cached = !of_get_flat_dt_prop(rmem->fdt_node, "no-map", NULL); + int ret = carveout_dma_heap_export(rmem->base, rmem->size, rmem->name, cached); + if (ret) { + pr_err("Carveout Heap: could not export as DMA-Heap\n"); + return ret; + } + } + + return 0; +} +fs_initcall(carveout_dma_heap_init_areas); + +static int __init rmem_dma_heap_carveout_setup(struct reserved_mem *rmem) +{ + phys_addr_t align = PAGE_SIZE; + phys_addr_t mask = align - 1; + + if ((rmem->base & mask) || (rmem->size & mask)) { + pr_err("Carveout Heap: incorrect alignment of region\n"); + return -EINVAL; + } + + /* Sanity check */ + if (heap_area_count == ARRAY_SIZE(heap_areas)) { + pr_err("Not enough slots for DMA-Heap reserved regions!\n"); + return -ENOSPC; + } + + /* + * Each reserved area must be initialized later, when more kernel + * subsystems (like slab allocator) are available. + */ + heap_areas[heap_area_count] = *rmem; + heap_area_count++; + + return 0; +} +RESERVEDMEM_OF_DECLARE(dma_heap_carveout, "dma-heap-carveout", rmem_dma_heap_carveout_setup); + +#endif Index: linux-6.1.80/drivers/dma/ti/Kconfig =================================================================== --- linux-6.1.80.orig/drivers/dma/ti/Kconfig +++ linux-6.1.80/drivers/dma/ti/Kconfig @@ -35,7 +35,7 @@ config DMA_OMAP DMA engine is found on OMAP and DRA7xx parts. config TI_K3_UDMA - bool "Texas Instruments UDMA support" + tristate "Texas Instruments UDMA support" depends on ARCH_K3 depends on TI_SCI_PROTOCOL depends on TI_SCI_INTA_IRQCHIP @@ -48,7 +48,7 @@ config TI_K3_UDMA DMA engine is used in AM65x and j721e. config TI_K3_UDMA_GLUE_LAYER - bool "Texas Instruments UDMA Glue layer for non DMAengine users" + tristate "Texas Instruments UDMA Glue layer for non DMAengine users" depends on ARCH_K3 depends on TI_K3_UDMA help @@ -56,7 +56,8 @@ config TI_K3_UDMA_GLUE_LAYER If unsure, say N. config TI_K3_PSIL - bool + tristate + default TI_K3_UDMA config TI_DMA_CROSSBAR bool Index: linux-6.1.80/drivers/dma/ti/Makefile =================================================================== --- linux-6.1.80.orig/drivers/dma/ti/Makefile +++ linux-6.1.80/drivers/dma/ti/Makefile @@ -4,11 +4,15 @@ obj-$(CONFIG_TI_EDMA) += edma.o obj-$(CONFIG_DMA_OMAP) += omap-dma.o obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o obj-$(CONFIG_TI_K3_UDMA_GLUE_LAYER) += k3-udma-glue.o -obj-$(CONFIG_TI_K3_PSIL) += k3-psil.o \ - k3-psil-am654.o \ - k3-psil-j721e.o \ - k3-psil-j7200.o \ - k3-psil-am64.o \ - k3-psil-j721s2.o \ - k3-psil-am62.o +k3-psil-lib-objs := k3-psil.o \ + k3-psil-am654.o \ + k3-psil-j721e.o \ + k3-psil-j7200.o \ + k3-psil-am64.o \ + k3-psil-j721s2.o \ + k3-psil-am62.o \ + k3-psil-am62a.o \ + k3-psil-j784s4.o \ + k3-psil-am62p.o +obj-$(CONFIG_TI_K3_PSIL) += k3-psil-lib.o obj-$(CONFIG_TI_DMA_CROSSBAR) += dma-crossbar.o Index: linux-6.1.80/drivers/dma/ti/k3-psil-am62.c =================================================================== --- linux-6.1.80.orig/drivers/dma/ti/k3-psil-am62.c +++ linux-6.1.80/drivers/dma/ti/k3-psil-am62.c @@ -74,7 +74,9 @@ static struct psil_ep am62_src_ep_map[] PSIL_SAUL(0x7505, 21, 35, 8, 36, 0), PSIL_SAUL(0x7506, 22, 43, 8, 43, 0), PSIL_SAUL(0x7507, 23, 43, 8, 44, 0), - /* PDMA_MAIN0 - SPI0-3 */ + /* PDMA_MAIN0 - SPI0-2 */ + PSIL_PDMA_XY_PKT(0x4300), + PSIL_PDMA_XY_PKT(0x4301), PSIL_PDMA_XY_PKT(0x4302), PSIL_PDMA_XY_PKT(0x4303), PSIL_PDMA_XY_PKT(0x4304), @@ -85,8 +87,6 @@ static struct psil_ep am62_src_ep_map[] PSIL_PDMA_XY_PKT(0x4309), PSIL_PDMA_XY_PKT(0x430a), PSIL_PDMA_XY_PKT(0x430b), - PSIL_PDMA_XY_PKT(0x430c), - PSIL_PDMA_XY_PKT(0x430d), /* PDMA_MAIN1 - UART0-6 */ PSIL_PDMA_XY_PKT(0x4400), PSIL_PDMA_XY_PKT(0x4401), @@ -141,7 +141,9 @@ static struct psil_ep am62_dst_ep_map[] /* SAUL */ PSIL_SAUL(0xf500, 27, 83, 8, 83, 1), PSIL_SAUL(0xf501, 28, 91, 8, 91, 1), - /* PDMA_MAIN0 - SPI0-3 */ + /* PDMA_MAIN0 - SPI0-2 */ + PSIL_PDMA_XY_PKT(0xc300), + PSIL_PDMA_XY_PKT(0xc301), PSIL_PDMA_XY_PKT(0xc302), PSIL_PDMA_XY_PKT(0xc303), PSIL_PDMA_XY_PKT(0xc304), @@ -152,8 +154,6 @@ static struct psil_ep am62_dst_ep_map[] PSIL_PDMA_XY_PKT(0xc309), PSIL_PDMA_XY_PKT(0xc30a), PSIL_PDMA_XY_PKT(0xc30b), - PSIL_PDMA_XY_PKT(0xc30c), - PSIL_PDMA_XY_PKT(0xc30d), /* PDMA_MAIN1 - UART0-6 */ PSIL_PDMA_XY_PKT(0xc400), PSIL_PDMA_XY_PKT(0xc401), Index: linux-6.1.80/drivers/dma/ti/k3-psil-am62a.c =================================================================== --- /dev/null +++ linux-6.1.80/drivers/dma/ti/k3-psil-am62a.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com + */ + +#include + +#include "k3-psil-priv.h" + +#define PSIL_PDMA_XY_TR(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .mapped_channel_id = -1, \ + .default_flow_id = -1, \ + }, \ + } + +#define PSIL_PDMA_XY_PKT(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .mapped_channel_id = -1, \ + .default_flow_id = -1, \ + .pkt_mode = 1, \ + }, \ + } + +#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 16, \ + .mapped_channel_id = ch, \ + .flow_start = flow_base, \ + .flow_num = flow_cnt, \ + .default_flow_id = flow_base, \ + }, \ + } + +#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 64, \ + .mapped_channel_id = ch, \ + .flow_start = flow_base, \ + .flow_num = flow_cnt, \ + .default_flow_id = default_flow, \ + .notdpkt = tx, \ + }, \ + } + +#define PSIL_PDMA_MCASP(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .pdma_acc32 = 1, \ + .pdma_burst = 1, \ + }, \ + } + +#define PSIL_CSI2RX(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + }, \ + } + +/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ +static struct psil_ep am62a_src_ep_map[] = { + /* SAUL */ + PSIL_SAUL(0x7504, 20, 35, 8, 35, 0), + PSIL_SAUL(0x7505, 21, 35, 8, 36, 0), + PSIL_SAUL(0x7506, 22, 43, 8, 43, 0), + PSIL_SAUL(0x7507, 23, 43, 8, 44, 0), + /* PDMA_MAIN0 - SPI0-2 */ + PSIL_PDMA_XY_PKT(0x4300), + PSIL_PDMA_XY_PKT(0x4301), + PSIL_PDMA_XY_PKT(0x4302), + PSIL_PDMA_XY_PKT(0x4303), + PSIL_PDMA_XY_PKT(0x4304), + PSIL_PDMA_XY_PKT(0x4305), + PSIL_PDMA_XY_PKT(0x4306), + PSIL_PDMA_XY_PKT(0x4307), + PSIL_PDMA_XY_PKT(0x4308), + PSIL_PDMA_XY_PKT(0x4309), + PSIL_PDMA_XY_PKT(0x430a), + PSIL_PDMA_XY_PKT(0x430b), + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0x4400), + PSIL_PDMA_XY_PKT(0x4401), + PSIL_PDMA_XY_PKT(0x4402), + PSIL_PDMA_XY_PKT(0x4403), + PSIL_PDMA_XY_PKT(0x4404), + PSIL_PDMA_XY_PKT(0x4405), + PSIL_PDMA_XY_PKT(0x4406), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0x4500), + PSIL_PDMA_MCASP(0x4501), + PSIL_PDMA_MCASP(0x4502), + /* CPSW3G */ + PSIL_ETHERNET(0x4600, 19, 19, 16), + /* CSI2RX */ + PSIL_CSI2RX(0x5000), + PSIL_CSI2RX(0x5001), + PSIL_CSI2RX(0x5002), + PSIL_CSI2RX(0x5003), + PSIL_CSI2RX(0x5004), + PSIL_CSI2RX(0x5005), + PSIL_CSI2RX(0x5006), + PSIL_CSI2RX(0x5007), + PSIL_CSI2RX(0x5008), + PSIL_CSI2RX(0x5009), + PSIL_CSI2RX(0x500a), + PSIL_CSI2RX(0x500b), + PSIL_CSI2RX(0x500c), + PSIL_CSI2RX(0x500d), + PSIL_CSI2RX(0x500e), + PSIL_CSI2RX(0x500f), + PSIL_CSI2RX(0x5010), + PSIL_CSI2RX(0x5011), + PSIL_CSI2RX(0x5012), + PSIL_CSI2RX(0x5013), + PSIL_CSI2RX(0x5014), + PSIL_CSI2RX(0x5015), + PSIL_CSI2RX(0x5016), + PSIL_CSI2RX(0x5017), + PSIL_CSI2RX(0x5018), + PSIL_CSI2RX(0x5019), + PSIL_CSI2RX(0x501a), + PSIL_CSI2RX(0x501b), + PSIL_CSI2RX(0x501c), + PSIL_CSI2RX(0x501d), + PSIL_CSI2RX(0x501e), + PSIL_CSI2RX(0x501f), +}; + +/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ +static struct psil_ep am62a_dst_ep_map[] = { + /* SAUL */ + PSIL_SAUL(0xf500, 27, 83, 8, 83, 1), + PSIL_SAUL(0xf501, 28, 91, 8, 91, 1), + /* PDMA_MAIN0 - SPI0-2 */ + PSIL_PDMA_XY_PKT(0xc300), + PSIL_PDMA_XY_PKT(0xc301), + PSIL_PDMA_XY_PKT(0xc302), + PSIL_PDMA_XY_PKT(0xc303), + PSIL_PDMA_XY_PKT(0xc304), + PSIL_PDMA_XY_PKT(0xc305), + PSIL_PDMA_XY_PKT(0xc306), + PSIL_PDMA_XY_PKT(0xc307), + PSIL_PDMA_XY_PKT(0xc308), + PSIL_PDMA_XY_PKT(0xc309), + PSIL_PDMA_XY_PKT(0xc30a), + PSIL_PDMA_XY_PKT(0xc30b), + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0xc400), + PSIL_PDMA_XY_PKT(0xc401), + PSIL_PDMA_XY_PKT(0xc402), + PSIL_PDMA_XY_PKT(0xc403), + PSIL_PDMA_XY_PKT(0xc404), + PSIL_PDMA_XY_PKT(0xc405), + PSIL_PDMA_XY_PKT(0xc406), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0xc500), + PSIL_PDMA_MCASP(0xc501), + PSIL_PDMA_MCASP(0xc502), + /* CPSW3G */ + PSIL_ETHERNET(0xc600, 19, 19, 8), + PSIL_ETHERNET(0xc601, 20, 27, 8), + PSIL_ETHERNET(0xc602, 21, 35, 8), + PSIL_ETHERNET(0xc603, 22, 43, 8), + PSIL_ETHERNET(0xc604, 23, 51, 8), + PSIL_ETHERNET(0xc605, 24, 59, 8), + PSIL_ETHERNET(0xc606, 25, 67, 8), + PSIL_ETHERNET(0xc607, 26, 75, 8), +}; + +struct psil_ep_map am62a_ep_map = { + .name = "am62a", + .src = am62a_src_ep_map, + .src_count = ARRAY_SIZE(am62a_src_ep_map), + .dst = am62a_dst_ep_map, + .dst_count = ARRAY_SIZE(am62a_dst_ep_map), +}; Index: linux-6.1.80/drivers/dma/ti/k3-psil-am62p.c =================================================================== --- /dev/null +++ linux-6.1.80/drivers/dma/ti/k3-psil-am62p.c @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com + */ + +#include + +#include "k3-psil-priv.h" + +#define PSIL_PDMA_XY_TR(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .mapped_channel_id = -1, \ + .default_flow_id = -1, \ + }, \ + } + +#define PSIL_PDMA_XY_PKT(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .mapped_channel_id = -1, \ + .default_flow_id = -1, \ + .pkt_mode = 1, \ + }, \ + } + +#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 16, \ + .mapped_channel_id = ch, \ + .flow_start = flow_base, \ + .flow_num = flow_cnt, \ + .default_flow_id = flow_base, \ + }, \ + } + +#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 64, \ + .mapped_channel_id = ch, \ + .flow_start = flow_base, \ + .flow_num = flow_cnt, \ + .default_flow_id = default_flow, \ + .notdpkt = tx, \ + }, \ + } + +#define PSIL_PDMA_MCASP(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .pdma_acc32 = 1, \ + .pdma_burst = 1, \ + }, \ + } + +#define PSIL_CSI2RX(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + }, \ + } + +/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ +static struct psil_ep am62p_src_ep_map[] = { + /* SAUL */ + PSIL_SAUL(0x7504, 20, 35, 8, 35, 0), + PSIL_SAUL(0x7505, 21, 35, 8, 36, 0), + PSIL_SAUL(0x7506, 22, 43, 8, 43, 0), + PSIL_SAUL(0x7507, 23, 43, 8, 44, 0), + /* PDMA_MAIN0 - SPI0-2 */ + PSIL_PDMA_XY_PKT(0x4300), + PSIL_PDMA_XY_PKT(0x4301), + PSIL_PDMA_XY_PKT(0x4302), + PSIL_PDMA_XY_PKT(0x4303), + PSIL_PDMA_XY_PKT(0x4304), + PSIL_PDMA_XY_PKT(0x4305), + PSIL_PDMA_XY_PKT(0x4306), + PSIL_PDMA_XY_PKT(0x4307), + PSIL_PDMA_XY_PKT(0x4308), + PSIL_PDMA_XY_PKT(0x4309), + PSIL_PDMA_XY_PKT(0x430a), + PSIL_PDMA_XY_PKT(0x430b), + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0x4400), + PSIL_PDMA_XY_PKT(0x4401), + PSIL_PDMA_XY_PKT(0x4402), + PSIL_PDMA_XY_PKT(0x4403), + PSIL_PDMA_XY_PKT(0x4404), + PSIL_PDMA_XY_PKT(0x4405), + PSIL_PDMA_XY_PKT(0x4406), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0x4500), + PSIL_PDMA_MCASP(0x4501), + PSIL_PDMA_MCASP(0x4502), + /* CPSW3G */ + PSIL_ETHERNET(0x4600, 19, 19, 16), + /* CSI2RX */ + PSIL_CSI2RX(0x5000), + PSIL_CSI2RX(0x5001), + PSIL_CSI2RX(0x5002), + PSIL_CSI2RX(0x5003), + PSIL_CSI2RX(0x5004), + PSIL_CSI2RX(0x5005), + PSIL_CSI2RX(0x5006), + PSIL_CSI2RX(0x5007), + PSIL_CSI2RX(0x5008), + PSIL_CSI2RX(0x5009), + PSIL_CSI2RX(0x500a), + PSIL_CSI2RX(0x500b), + PSIL_CSI2RX(0x500c), + PSIL_CSI2RX(0x500d), + PSIL_CSI2RX(0x500e), + PSIL_CSI2RX(0x500f), + PSIL_CSI2RX(0x5010), + PSIL_CSI2RX(0x5011), + PSIL_CSI2RX(0x5012), + PSIL_CSI2RX(0x5013), + PSIL_CSI2RX(0x5014), + PSIL_CSI2RX(0x5015), + PSIL_CSI2RX(0x5016), + PSIL_CSI2RX(0x5017), + PSIL_CSI2RX(0x5018), + PSIL_CSI2RX(0x5019), + PSIL_CSI2RX(0x501a), + PSIL_CSI2RX(0x501b), + PSIL_CSI2RX(0x501c), + PSIL_CSI2RX(0x501d), + PSIL_CSI2RX(0x501e), + PSIL_CSI2RX(0x501f), + /* CSIRX 1-3 (only for J722S) */ + PSIL_CSI2RX(0x5100), + PSIL_CSI2RX(0x5101), + PSIL_CSI2RX(0x5102), + PSIL_CSI2RX(0x5103), + PSIL_CSI2RX(0x5104), + PSIL_CSI2RX(0x5105), + PSIL_CSI2RX(0x5106), + PSIL_CSI2RX(0x5107), + PSIL_CSI2RX(0x5108), + PSIL_CSI2RX(0x5109), + PSIL_CSI2RX(0x510a), + PSIL_CSI2RX(0x510b), + PSIL_CSI2RX(0x510c), + PSIL_CSI2RX(0x510d), + PSIL_CSI2RX(0x510e), + PSIL_CSI2RX(0x510f), + PSIL_CSI2RX(0x5110), + PSIL_CSI2RX(0x5111), + PSIL_CSI2RX(0x5112), + PSIL_CSI2RX(0x5113), + PSIL_CSI2RX(0x5114), + PSIL_CSI2RX(0x5115), + PSIL_CSI2RX(0x5116), + PSIL_CSI2RX(0x5117), + PSIL_CSI2RX(0x5118), + PSIL_CSI2RX(0x5119), + PSIL_CSI2RX(0x511a), + PSIL_CSI2RX(0x511b), + PSIL_CSI2RX(0x511c), + PSIL_CSI2RX(0x511d), + PSIL_CSI2RX(0x511e), + PSIL_CSI2RX(0x511f), + PSIL_CSI2RX(0x5200), + PSIL_CSI2RX(0x5201), + PSIL_CSI2RX(0x5202), + PSIL_CSI2RX(0x5203), + PSIL_CSI2RX(0x5204), + PSIL_CSI2RX(0x5205), + PSIL_CSI2RX(0x5206), + PSIL_CSI2RX(0x5207), + PSIL_CSI2RX(0x5208), + PSIL_CSI2RX(0x5209), + PSIL_CSI2RX(0x520a), + PSIL_CSI2RX(0x520b), + PSIL_CSI2RX(0x520c), + PSIL_CSI2RX(0x520d), + PSIL_CSI2RX(0x520e), + PSIL_CSI2RX(0x520f), + PSIL_CSI2RX(0x5210), + PSIL_CSI2RX(0x5211), + PSIL_CSI2RX(0x5212), + PSIL_CSI2RX(0x5213), + PSIL_CSI2RX(0x5214), + PSIL_CSI2RX(0x5215), + PSIL_CSI2RX(0x5216), + PSIL_CSI2RX(0x5217), + PSIL_CSI2RX(0x5218), + PSIL_CSI2RX(0x5219), + PSIL_CSI2RX(0x521a), + PSIL_CSI2RX(0x521b), + PSIL_CSI2RX(0x521c), + PSIL_CSI2RX(0x521d), + PSIL_CSI2RX(0x521e), + PSIL_CSI2RX(0x521f), + PSIL_CSI2RX(0x5300), + PSIL_CSI2RX(0x5301), + PSIL_CSI2RX(0x5302), + PSIL_CSI2RX(0x5303), + PSIL_CSI2RX(0x5304), + PSIL_CSI2RX(0x5305), + PSIL_CSI2RX(0x5306), + PSIL_CSI2RX(0x5307), + PSIL_CSI2RX(0x5308), + PSIL_CSI2RX(0x5309), + PSIL_CSI2RX(0x530a), + PSIL_CSI2RX(0x530b), + PSIL_CSI2RX(0x530c), + PSIL_CSI2RX(0x530d), + PSIL_CSI2RX(0x530e), + PSIL_CSI2RX(0x530f), + PSIL_CSI2RX(0x5310), + PSIL_CSI2RX(0x5311), + PSIL_CSI2RX(0x5312), + PSIL_CSI2RX(0x5313), + PSIL_CSI2RX(0x5314), + PSIL_CSI2RX(0x5315), + PSIL_CSI2RX(0x5316), + PSIL_CSI2RX(0x5317), + PSIL_CSI2RX(0x5318), + PSIL_CSI2RX(0x5319), + PSIL_CSI2RX(0x531a), + PSIL_CSI2RX(0x531b), + PSIL_CSI2RX(0x531c), + PSIL_CSI2RX(0x531d), + PSIL_CSI2RX(0x531e), + PSIL_CSI2RX(0x531f), + +}; + +/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ +static struct psil_ep am62p_dst_ep_map[] = { + /* SAUL */ + PSIL_SAUL(0xf500, 27, 83, 8, 83, 1), + PSIL_SAUL(0xf501, 28, 91, 8, 91, 1), + /* PDMA_MAIN0 - SPI0-2 */ + PSIL_PDMA_XY_PKT(0xc300), + PSIL_PDMA_XY_PKT(0xc301), + PSIL_PDMA_XY_PKT(0xc302), + PSIL_PDMA_XY_PKT(0xc303), + PSIL_PDMA_XY_PKT(0xc304), + PSIL_PDMA_XY_PKT(0xc305), + PSIL_PDMA_XY_PKT(0xc306), + PSIL_PDMA_XY_PKT(0xc307), + PSIL_PDMA_XY_PKT(0xc308), + PSIL_PDMA_XY_PKT(0xc309), + PSIL_PDMA_XY_PKT(0xc30a), + PSIL_PDMA_XY_PKT(0xc30b), + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0xc400), + PSIL_PDMA_XY_PKT(0xc401), + PSIL_PDMA_XY_PKT(0xc402), + PSIL_PDMA_XY_PKT(0xc403), + PSIL_PDMA_XY_PKT(0xc404), + PSIL_PDMA_XY_PKT(0xc405), + PSIL_PDMA_XY_PKT(0xc406), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0xc500), + PSIL_PDMA_MCASP(0xc501), + PSIL_PDMA_MCASP(0xc502), + /* CPSW3G */ + PSIL_ETHERNET(0xc600, 19, 19, 8), + PSIL_ETHERNET(0xc601, 20, 27, 8), + PSIL_ETHERNET(0xc602, 21, 35, 8), + PSIL_ETHERNET(0xc603, 22, 43, 8), + PSIL_ETHERNET(0xc604, 23, 51, 8), + PSIL_ETHERNET(0xc605, 24, 59, 8), + PSIL_ETHERNET(0xc606, 25, 67, 8), + PSIL_ETHERNET(0xc607, 26, 75, 8), +}; + +struct psil_ep_map am62p_ep_map = { + .name = "am62p", + .src = am62p_src_ep_map, + .src_count = ARRAY_SIZE(am62p_src_ep_map), + .dst = am62p_dst_ep_map, + .dst_count = ARRAY_SIZE(am62p_dst_ep_map), +}; Index: linux-6.1.80/drivers/dma/ti/k3-psil-j721s2.c =================================================================== --- linux-6.1.80.orig/drivers/dma/ti/k3-psil-j721s2.c +++ linux-6.1.80/drivers/dma/ti/k3-psil-j721s2.c @@ -57,6 +57,14 @@ }, \ } +#define PSIL_CSI2RX(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + }, \ + } + /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ static struct psil_ep j721s2_src_ep_map[] = { /* PDMA_MCASP - McASP0-4 */ @@ -99,6 +107,8 @@ static struct psil_ep j721s2_src_ep_map[ PSIL_PDMA_XY_PKT(0x461d), PSIL_PDMA_XY_PKT(0x461e), PSIL_PDMA_XY_PKT(0x461f), + /* MAIN_CPSW2G */ + PSIL_ETHERNET(0x4640), /* PDMA_USART_G0 - UART0-1 */ PSIL_PDMA_XY_PKT(0x4700), PSIL_PDMA_XY_PKT(0x4701), @@ -112,6 +122,71 @@ static struct psil_ep j721s2_src_ep_map[ PSIL_PDMA_XY_PKT(0x4707), PSIL_PDMA_XY_PKT(0x4708), PSIL_PDMA_XY_PKT(0x4709), + /* CSI2RX */ + PSIL_CSI2RX(0x4940), + PSIL_CSI2RX(0x4941), + PSIL_CSI2RX(0x4942), + PSIL_CSI2RX(0x4943), + PSIL_CSI2RX(0x4944), + PSIL_CSI2RX(0x4945), + PSIL_CSI2RX(0x4946), + PSIL_CSI2RX(0x4947), + PSIL_CSI2RX(0x4948), + PSIL_CSI2RX(0x4949), + PSIL_CSI2RX(0x494a), + PSIL_CSI2RX(0x494b), + PSIL_CSI2RX(0x494c), + PSIL_CSI2RX(0x494d), + PSIL_CSI2RX(0x494e), + PSIL_CSI2RX(0x494f), + PSIL_CSI2RX(0x4950), + PSIL_CSI2RX(0x4951), + PSIL_CSI2RX(0x4952), + PSIL_CSI2RX(0x4953), + PSIL_CSI2RX(0x4954), + PSIL_CSI2RX(0x4955), + PSIL_CSI2RX(0x4956), + PSIL_CSI2RX(0x4957), + PSIL_CSI2RX(0x4958), + PSIL_CSI2RX(0x4959), + PSIL_CSI2RX(0x495a), + PSIL_CSI2RX(0x495b), + PSIL_CSI2RX(0x495c), + PSIL_CSI2RX(0x495d), + PSIL_CSI2RX(0x495e), + PSIL_CSI2RX(0x495f), + PSIL_CSI2RX(0x4960), + PSIL_CSI2RX(0x4961), + PSIL_CSI2RX(0x4962), + PSIL_CSI2RX(0x4963), + PSIL_CSI2RX(0x4964), + PSIL_CSI2RX(0x4965), + PSIL_CSI2RX(0x4966), + PSIL_CSI2RX(0x4967), + PSIL_CSI2RX(0x4968), + PSIL_CSI2RX(0x4969), + PSIL_CSI2RX(0x496a), + PSIL_CSI2RX(0x496b), + PSIL_CSI2RX(0x496c), + PSIL_CSI2RX(0x496d), + PSIL_CSI2RX(0x496e), + PSIL_CSI2RX(0x496f), + PSIL_CSI2RX(0x4970), + PSIL_CSI2RX(0x4971), + PSIL_CSI2RX(0x4972), + PSIL_CSI2RX(0x4973), + PSIL_CSI2RX(0x4974), + PSIL_CSI2RX(0x4975), + PSIL_CSI2RX(0x4976), + PSIL_CSI2RX(0x4977), + PSIL_CSI2RX(0x4978), + PSIL_CSI2RX(0x4979), + PSIL_CSI2RX(0x497a), + PSIL_CSI2RX(0x497b), + PSIL_CSI2RX(0x497c), + PSIL_CSI2RX(0x497d), + PSIL_CSI2RX(0x497e), + PSIL_CSI2RX(0x497f), /* MAIN SA2UL */ PSIL_SA2UL(0x4a40, 0), PSIL_SA2UL(0x4a41, 0), @@ -161,6 +236,15 @@ static struct psil_ep j721s2_dst_ep_map[ PSIL_ETHERNET(0xf005), PSIL_ETHERNET(0xf006), PSIL_ETHERNET(0xf007), + /* MAIN_CPSW2G */ + PSIL_ETHERNET(0xc640), + PSIL_ETHERNET(0xc641), + PSIL_ETHERNET(0xc642), + PSIL_ETHERNET(0xc643), + PSIL_ETHERNET(0xc644), + PSIL_ETHERNET(0xc645), + PSIL_ETHERNET(0xc646), + PSIL_ETHERNET(0xc647), /* SA2UL */ PSIL_SA2UL(0xf500, 1), PSIL_SA2UL(0xf501, 1), Index: linux-6.1.80/drivers/dma/ti/k3-psil-j784s4.c =================================================================== --- /dev/null +++ linux-6.1.80/drivers/dma/ti/k3-psil-j784s4.c @@ -0,0 +1,354 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com + */ + +#include + +#include "k3-psil-priv.h" + +#define PSIL_PDMA_XY_TR(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + }, \ + } + +#define PSIL_PDMA_XY_PKT(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .pkt_mode = 1, \ + }, \ + } + +#define PSIL_PDMA_MCASP(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .pdma_acc32 = 1, \ + .pdma_burst = 1, \ + }, \ + } + +#define PSIL_ETHERNET(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 16, \ + }, \ + } + +#define PSIL_SA2UL(x, tx) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 64, \ + .notdpkt = tx, \ + }, \ + } + +#define PSIL_CSI2RX(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + }, \ + } + +/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ +static struct psil_ep j784s4_src_ep_map[] = { + /* PDMA_MCASP - McASP0-4 */ + PSIL_PDMA_MCASP(0x4400), + PSIL_PDMA_MCASP(0x4401), + PSIL_PDMA_MCASP(0x4402), + PSIL_PDMA_MCASP(0x4403), + PSIL_PDMA_MCASP(0x4404), + /* PDMA_SPI_G0 - SPI0-3 */ + PSIL_PDMA_XY_PKT(0x4600), + PSIL_PDMA_XY_PKT(0x4601), + PSIL_PDMA_XY_PKT(0x4602), + PSIL_PDMA_XY_PKT(0x4603), + PSIL_PDMA_XY_PKT(0x4604), + PSIL_PDMA_XY_PKT(0x4605), + PSIL_PDMA_XY_PKT(0x4606), + PSIL_PDMA_XY_PKT(0x4607), + PSIL_PDMA_XY_PKT(0x4608), + PSIL_PDMA_XY_PKT(0x4609), + PSIL_PDMA_XY_PKT(0x460a), + PSIL_PDMA_XY_PKT(0x460b), + PSIL_PDMA_XY_PKT(0x460c), + PSIL_PDMA_XY_PKT(0x460d), + PSIL_PDMA_XY_PKT(0x460e), + PSIL_PDMA_XY_PKT(0x460f), + /* PDMA_SPI_G1 - SPI4-7 */ + PSIL_PDMA_XY_PKT(0x4620), + PSIL_PDMA_XY_PKT(0x4621), + PSIL_PDMA_XY_PKT(0x4622), + PSIL_PDMA_XY_PKT(0x4623), + PSIL_PDMA_XY_PKT(0x4624), + PSIL_PDMA_XY_PKT(0x4625), + PSIL_PDMA_XY_PKT(0x4626), + PSIL_PDMA_XY_PKT(0x4627), + PSIL_PDMA_XY_PKT(0x4628), + PSIL_PDMA_XY_PKT(0x4629), + PSIL_PDMA_XY_PKT(0x462a), + PSIL_PDMA_XY_PKT(0x462b), + PSIL_PDMA_XY_PKT(0x462c), + PSIL_PDMA_XY_PKT(0x462d), + PSIL_PDMA_XY_PKT(0x462e), + PSIL_PDMA_XY_PKT(0x462f), + /* MAIN_CPSW2G */ + PSIL_ETHERNET(0x4640), + /* PDMA_USART_G0 - UART0-1 */ + PSIL_PDMA_XY_PKT(0x4700), + PSIL_PDMA_XY_PKT(0x4701), + /* PDMA_USART_G1 - UART2-3 */ + PSIL_PDMA_XY_PKT(0x4702), + PSIL_PDMA_XY_PKT(0x4703), + /* PDMA_USART_G2 - UART4-9 */ + PSIL_PDMA_XY_PKT(0x4704), + PSIL_PDMA_XY_PKT(0x4705), + PSIL_PDMA_XY_PKT(0x4706), + PSIL_PDMA_XY_PKT(0x4707), + PSIL_PDMA_XY_PKT(0x4708), + PSIL_PDMA_XY_PKT(0x4709), + /* CSI2RX */ + PSIL_CSI2RX(0x4900), + PSIL_CSI2RX(0x4901), + PSIL_CSI2RX(0x4902), + PSIL_CSI2RX(0x4903), + PSIL_CSI2RX(0x4940), + PSIL_CSI2RX(0x4941), + PSIL_CSI2RX(0x4942), + PSIL_CSI2RX(0x4943), + PSIL_CSI2RX(0x4944), + PSIL_CSI2RX(0x4945), + PSIL_CSI2RX(0x4946), + PSIL_CSI2RX(0x4947), + PSIL_CSI2RX(0x4948), + PSIL_CSI2RX(0x4949), + PSIL_CSI2RX(0x494a), + PSIL_CSI2RX(0x494b), + PSIL_CSI2RX(0x494c), + PSIL_CSI2RX(0x494d), + PSIL_CSI2RX(0x494e), + PSIL_CSI2RX(0x494f), + PSIL_CSI2RX(0x4950), + PSIL_CSI2RX(0x4951), + PSIL_CSI2RX(0x4952), + PSIL_CSI2RX(0x4953), + PSIL_CSI2RX(0x4954), + PSIL_CSI2RX(0x4955), + PSIL_CSI2RX(0x4956), + PSIL_CSI2RX(0x4957), + PSIL_CSI2RX(0x4958), + PSIL_CSI2RX(0x4959), + PSIL_CSI2RX(0x495a), + PSIL_CSI2RX(0x495b), + PSIL_CSI2RX(0x495c), + PSIL_CSI2RX(0x495d), + PSIL_CSI2RX(0x495e), + PSIL_CSI2RX(0x495f), + PSIL_CSI2RX(0x4960), + PSIL_CSI2RX(0x4961), + PSIL_CSI2RX(0x4962), + PSIL_CSI2RX(0x4963), + PSIL_CSI2RX(0x4964), + PSIL_CSI2RX(0x4965), + PSIL_CSI2RX(0x4966), + PSIL_CSI2RX(0x4967), + PSIL_CSI2RX(0x4968), + PSIL_CSI2RX(0x4969), + PSIL_CSI2RX(0x496a), + PSIL_CSI2RX(0x496b), + PSIL_CSI2RX(0x496c), + PSIL_CSI2RX(0x496d), + PSIL_CSI2RX(0x496e), + PSIL_CSI2RX(0x496f), + PSIL_CSI2RX(0x4970), + PSIL_CSI2RX(0x4971), + PSIL_CSI2RX(0x4972), + PSIL_CSI2RX(0x4973), + PSIL_CSI2RX(0x4974), + PSIL_CSI2RX(0x4975), + PSIL_CSI2RX(0x4976), + PSIL_CSI2RX(0x4977), + PSIL_CSI2RX(0x4978), + PSIL_CSI2RX(0x4979), + PSIL_CSI2RX(0x497a), + PSIL_CSI2RX(0x497b), + PSIL_CSI2RX(0x497c), + PSIL_CSI2RX(0x497d), + PSIL_CSI2RX(0x497e), + PSIL_CSI2RX(0x497f), + PSIL_CSI2RX(0x4980), + PSIL_CSI2RX(0x4981), + PSIL_CSI2RX(0x4982), + PSIL_CSI2RX(0x4983), + PSIL_CSI2RX(0x4984), + PSIL_CSI2RX(0x4985), + PSIL_CSI2RX(0x4986), + PSIL_CSI2RX(0x4987), + PSIL_CSI2RX(0x4988), + PSIL_CSI2RX(0x4989), + PSIL_CSI2RX(0x498a), + PSIL_CSI2RX(0x498b), + PSIL_CSI2RX(0x498c), + PSIL_CSI2RX(0x498d), + PSIL_CSI2RX(0x498e), + PSIL_CSI2RX(0x498f), + PSIL_CSI2RX(0x4990), + PSIL_CSI2RX(0x4991), + PSIL_CSI2RX(0x4992), + PSIL_CSI2RX(0x4993), + PSIL_CSI2RX(0x4994), + PSIL_CSI2RX(0x4995), + PSIL_CSI2RX(0x4996), + PSIL_CSI2RX(0x4997), + PSIL_CSI2RX(0x4998), + PSIL_CSI2RX(0x4999), + PSIL_CSI2RX(0x499a), + PSIL_CSI2RX(0x499b), + PSIL_CSI2RX(0x499c), + PSIL_CSI2RX(0x499d), + PSIL_CSI2RX(0x499e), + PSIL_CSI2RX(0x499f), + /* MAIN_CPSW9G */ + PSIL_ETHERNET(0x4a00), + /* MAIN-SA2UL */ + PSIL_SA2UL(0x4a40, 0), + PSIL_SA2UL(0x4a41, 0), + PSIL_SA2UL(0x4a42, 0), + PSIL_SA2UL(0x4a43, 0), + /* MCU_CPSW0 */ + PSIL_ETHERNET(0x7000), + /* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */ + PSIL_PDMA_XY_PKT(0x7100), + PSIL_PDMA_XY_PKT(0x7101), + PSIL_PDMA_XY_PKT(0x7102), + PSIL_PDMA_XY_PKT(0x7103), + /* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */ + PSIL_PDMA_XY_PKT(0x7200), + PSIL_PDMA_XY_PKT(0x7201), + PSIL_PDMA_XY_PKT(0x7202), + PSIL_PDMA_XY_PKT(0x7203), + PSIL_PDMA_XY_PKT(0x7204), + PSIL_PDMA_XY_PKT(0x7205), + PSIL_PDMA_XY_PKT(0x7206), + PSIL_PDMA_XY_PKT(0x7207), + /* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */ + PSIL_PDMA_XY_PKT(0x7300), + /* MCU_PDMA_ADC - ADC0-1 */ + PSIL_PDMA_XY_TR(0x7400), + PSIL_PDMA_XY_TR(0x7401), + PSIL_PDMA_XY_TR(0x7402), + PSIL_PDMA_XY_TR(0x7403), + /* MCU_SA2UL */ + PSIL_SA2UL(0x7500, 0), + PSIL_SA2UL(0x7501, 0), + PSIL_SA2UL(0x7502, 0), + PSIL_SA2UL(0x7503, 0), +}; + +/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ +static struct psil_ep j784s4_dst_ep_map[] = { + /* MAIN_CPSW2G */ + PSIL_ETHERNET(0xc640), + PSIL_ETHERNET(0xc641), + PSIL_ETHERNET(0xc642), + PSIL_ETHERNET(0xc643), + PSIL_ETHERNET(0xc644), + PSIL_ETHERNET(0xc645), + PSIL_ETHERNET(0xc646), + PSIL_ETHERNET(0xc647), + /* MAIN_CPSW9G */ + PSIL_ETHERNET(0xca00), + PSIL_ETHERNET(0xca01), + PSIL_ETHERNET(0xca02), + PSIL_ETHERNET(0xca03), + PSIL_ETHERNET(0xca04), + PSIL_ETHERNET(0xca05), + PSIL_ETHERNET(0xca06), + PSIL_ETHERNET(0xca07), + /* MAIN-SA2UL */ + PSIL_SA2UL(0xca40, 1), + PSIL_SA2UL(0xca41, 1), + /* PDMA_SPI_G0 - SPI0-3 */ + PSIL_PDMA_XY_PKT(0xc600), + PSIL_PDMA_XY_PKT(0xc601), + PSIL_PDMA_XY_PKT(0xc602), + PSIL_PDMA_XY_PKT(0xc603), + PSIL_PDMA_XY_PKT(0xc604), + PSIL_PDMA_XY_PKT(0xc605), + PSIL_PDMA_XY_PKT(0xc606), + PSIL_PDMA_XY_PKT(0xc607), + PSIL_PDMA_XY_PKT(0xc608), + PSIL_PDMA_XY_PKT(0xc609), + PSIL_PDMA_XY_PKT(0xc60a), + PSIL_PDMA_XY_PKT(0xc60b), + PSIL_PDMA_XY_PKT(0xc60c), + PSIL_PDMA_XY_PKT(0xc60d), + PSIL_PDMA_XY_PKT(0xc60e), + PSIL_PDMA_XY_PKT(0xc60f), + /* PDMA_SPI_G1 - SPI4-7 */ + PSIL_PDMA_XY_PKT(0xc620), + PSIL_PDMA_XY_PKT(0xc621), + PSIL_PDMA_XY_PKT(0xc622), + PSIL_PDMA_XY_PKT(0xc623), + PSIL_PDMA_XY_PKT(0xc624), + PSIL_PDMA_XY_PKT(0xc625), + PSIL_PDMA_XY_PKT(0xc626), + PSIL_PDMA_XY_PKT(0xc627), + PSIL_PDMA_XY_PKT(0xc628), + PSIL_PDMA_XY_PKT(0xc629), + PSIL_PDMA_XY_PKT(0xc62a), + PSIL_PDMA_XY_PKT(0xc62b), + PSIL_PDMA_XY_PKT(0xc62c), + PSIL_PDMA_XY_PKT(0xc62d), + PSIL_PDMA_XY_PKT(0xc62e), + PSIL_PDMA_XY_PKT(0xc62f), + /* MCU_CPSW0 */ + PSIL_ETHERNET(0xf000), + PSIL_ETHERNET(0xf001), + PSIL_ETHERNET(0xf002), + PSIL_ETHERNET(0xf003), + PSIL_ETHERNET(0xf004), + PSIL_ETHERNET(0xf005), + PSIL_ETHERNET(0xf006), + PSIL_ETHERNET(0xf007), + /* MCU_PDMA_MISC_G0 - SPI0 */ + PSIL_PDMA_XY_PKT(0xf100), + PSIL_PDMA_XY_PKT(0xf101), + PSIL_PDMA_XY_PKT(0xf102), + PSIL_PDMA_XY_PKT(0xf103), + /* MCU_PDMA_MISC_G1 - SPI1-2 */ + PSIL_PDMA_XY_PKT(0xf200), + PSIL_PDMA_XY_PKT(0xf201), + PSIL_PDMA_XY_PKT(0xf202), + PSIL_PDMA_XY_PKT(0xf203), + PSIL_PDMA_XY_PKT(0xf204), + PSIL_PDMA_XY_PKT(0xf205), + PSIL_PDMA_XY_PKT(0xf206), + PSIL_PDMA_XY_PKT(0xf207), + /* MCU_SA2UL */ + PSIL_SA2UL(0xf500, 1), + PSIL_SA2UL(0xf501, 1), +}; + +struct psil_ep_map j784s4_ep_map = { + .name = "j784s4", + .src = j784s4_src_ep_map, + .src_count = ARRAY_SIZE(j784s4_src_ep_map), + .dst = j784s4_dst_ep_map, + .dst_count = ARRAY_SIZE(j784s4_dst_ep_map), +}; Index: linux-6.1.80/drivers/dma/ti/k3-psil-priv.h =================================================================== --- linux-6.1.80.orig/drivers/dma/ti/k3-psil-priv.h +++ linux-6.1.80/drivers/dma/ti/k3-psil-priv.h @@ -43,5 +43,8 @@ extern struct psil_ep_map j7200_ep_map; extern struct psil_ep_map am64_ep_map; extern struct psil_ep_map j721s2_ep_map; extern struct psil_ep_map am62_ep_map; +extern struct psil_ep_map am62a_ep_map; +extern struct psil_ep_map j784s4_ep_map; +extern struct psil_ep_map am62p_ep_map; #endif /* K3_PSIL_PRIV_H_ */ Index: linux-6.1.80/drivers/dma/ti/k3-psil.c =================================================================== --- linux-6.1.80.orig/drivers/dma/ti/k3-psil.c +++ linux-6.1.80/drivers/dma/ti/k3-psil.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -23,6 +24,10 @@ static const struct soc_device_attribute { .family = "AM64X", .data = &am64_ep_map }, { .family = "J721S2", .data = &j721s2_ep_map }, { .family = "AM62X", .data = &am62_ep_map }, + { .family = "AM62AX", .data = &am62a_ep_map }, + { .family = "J784S4", .data = &j784s4_ep_map }, + { .family = "AM62PX", .data = &am62p_ep_map }, + { .family = "J722S", .data = &am62p_ep_map }, { /* sentinel */ } }; @@ -101,3 +106,4 @@ int psil_set_new_ep_config(struct device return 0; } EXPORT_SYMBOL_GPL(psil_set_new_ep_config); +MODULE_LICENSE("GPL v2"); Index: linux-6.1.80/drivers/dma/ti/k3-udma-glue.c =================================================================== --- linux-6.1.80.orig/drivers/dma/ti/k3-udma-glue.c +++ linux-6.1.80/drivers/dma/ti/k3-udma-glue.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include @@ -110,6 +111,35 @@ static int of_k3_udma_glue_parse(struct return 0; } +static int of_k3_udma_glue_parse_chn_common(struct k3_udma_glue_common *common, u32 thread_id, + bool tx_chn) +{ + if (tx_chn && !(thread_id & K3_PSIL_DST_THREAD_ID_OFFSET)) + return -EINVAL; + + if (!tx_chn && (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET)) + return -EINVAL; + + /* get psil endpoint config */ + common->ep_config = psil_get_ep_config(thread_id); + if (IS_ERR(common->ep_config)) { + dev_err(common->dev, + "No configuration for psi-l thread 0x%04x\n", + thread_id); + return PTR_ERR(common->ep_config); + } + + common->epib = common->ep_config->needs_epib; + common->psdata_size = common->ep_config->psd_size; + + if (tx_chn) + common->dst_thread = thread_id; + else + common->src_thread = thread_id; + + return 0; +} + static int of_k3_udma_glue_parse_chn(struct device_node *chn_np, const char *name, struct k3_udma_glue_common *common, bool tx_chn) @@ -152,38 +182,32 @@ static int of_k3_udma_glue_parse_chn(str common->atype_asel = dma_spec.args[1]; } - if (tx_chn && !(thread_id & K3_PSIL_DST_THREAD_ID_OFFSET)) { - ret = -EINVAL; - goto out_put_spec; - } + ret = of_k3_udma_glue_parse_chn_common(common, thread_id, tx_chn); - if (!tx_chn && (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET)) { - ret = -EINVAL; - goto out_put_spec; - } +out_put_spec: + of_node_put(dma_spec.np); + return ret; +} - /* get psil endpoint config */ - common->ep_config = psil_get_ep_config(thread_id); - if (IS_ERR(common->ep_config)) { - dev_err(common->dev, - "No configuration for psi-l thread 0x%04x\n", - thread_id); - ret = PTR_ERR(common->ep_config); - goto out_put_spec; - } +static int +of_k3_udma_glue_parse_chn_by_id(struct device_node *udmax_np, struct k3_udma_glue_common *common, + bool tx_chn, u32 thread_id) +{ + int ret = 0; - common->epib = common->ep_config->needs_epib; - common->psdata_size = common->ep_config->psd_size; + if (unlikely(!udmax_np)) + return -EINVAL; - if (tx_chn) - common->dst_thread = thread_id; - else - common->src_thread = thread_id; + ret = of_k3_udma_glue_parse(udmax_np, common); + if (ret) + goto out_put_spec; + + ret = of_k3_udma_glue_parse_chn_common(common, thread_id, tx_chn); out_put_spec: - of_node_put(dma_spec.np); + of_node_put(udmax_np); return ret; -}; +} static void k3_udma_glue_dump_tx_chn(struct k3_udma_glue_tx_channel *tx_chn) { @@ -250,29 +274,13 @@ static int k3_udma_glue_cfg_tx_chn(struc return tisci_rm->tisci_udmap_ops->tx_ch_cfg(tisci_rm->tisci, &req); } -struct k3_udma_glue_tx_channel *k3_udma_glue_request_tx_chn(struct device *dev, - const char *name, struct k3_udma_glue_tx_channel_cfg *cfg) +static int +k3_udma_glue_request_tx_chn_common(struct device *dev, + struct k3_udma_glue_tx_channel *tx_chn, + struct k3_udma_glue_tx_channel_cfg *cfg) { - struct k3_udma_glue_tx_channel *tx_chn; int ret; - tx_chn = devm_kzalloc(dev, sizeof(*tx_chn), GFP_KERNEL); - if (!tx_chn) - return ERR_PTR(-ENOMEM); - - tx_chn->common.dev = dev; - tx_chn->common.swdata_size = cfg->swdata_size; - tx_chn->tx_pause_on_err = cfg->tx_pause_on_err; - tx_chn->tx_filt_einfo = cfg->tx_filt_einfo; - tx_chn->tx_filt_pswords = cfg->tx_filt_pswords; - tx_chn->tx_supr_tdpkt = cfg->tx_supr_tdpkt; - - /* parse of udmap channel */ - ret = of_k3_udma_glue_parse_chn(dev->of_node, name, - &tx_chn->common, true); - if (ret) - goto err; - tx_chn->common.hdesc_size = cppi5_hdesc_calc_size(tx_chn->common.epib, tx_chn->common.psdata_size, tx_chn->common.swdata_size); @@ -288,23 +296,22 @@ struct k3_udma_glue_tx_channel *k3_udma_ if (IS_ERR(tx_chn->udma_tchanx)) { ret = PTR_ERR(tx_chn->udma_tchanx); dev_err(dev, "UDMAX tchanx get err %d\n", ret); - goto err; + return ret; } tx_chn->udma_tchan_id = xudma_tchan_get_id(tx_chn->udma_tchanx); - tx_chn->common.chan_dev.class = &k3_udma_glue_devclass; - tx_chn->common.chan_dev.parent = xudma_get_device(tx_chn->common.udmax); - dev_set_name(&tx_chn->common.chan_dev, "tchan%d-0x%04x", - tx_chn->udma_tchan_id, tx_chn->common.dst_thread); - ret = device_register(&tx_chn->common.chan_dev); - if (ret) { - dev_err(dev, "Channel Device registration failed %d\n", ret); - put_device(&tx_chn->common.chan_dev); - tx_chn->common.chan_dev.parent = NULL; - goto err; - } - if (xudma_is_pktdma(tx_chn->common.udmax)) { + tx_chn->common.chan_dev.class = &k3_udma_glue_devclass; + tx_chn->common.chan_dev.parent = xudma_get_device(tx_chn->common.udmax); + dev_set_name(&tx_chn->common.chan_dev, "tchan%d-0x%04x", + tx_chn->udma_tchan_id, tx_chn->common.dst_thread); + ret = device_register(&tx_chn->common.chan_dev); + if (ret) { + dev_err(dev, "Channel Device registration failed %d\n", ret); + tx_chn->common.chan_dev.parent = NULL; + return ret; + } + /* prepare the channel device as coherent */ tx_chn->common.chan_dev.dma_coherent = true; dma_coerce_mask_and_coherent(&tx_chn->common.chan_dev, @@ -325,7 +332,7 @@ struct k3_udma_glue_tx_channel *k3_udma_ &tx_chn->ringtxcq); if (ret) { dev_err(dev, "Failed to get TX/TXCQ rings %d\n", ret); - goto err; + return ret; } /* Set the dma_dev for the rings to be configured */ @@ -341,13 +348,13 @@ struct k3_udma_glue_tx_channel *k3_udma_ ret = k3_ringacc_ring_cfg(tx_chn->ringtx, &cfg->tx_cfg); if (ret) { dev_err(dev, "Failed to cfg ringtx %d\n", ret); - goto err; + return ret; } ret = k3_ringacc_ring_cfg(tx_chn->ringtxcq, &cfg->txcq_cfg); if (ret) { dev_err(dev, "Failed to cfg ringtx %d\n", ret); - goto err; + return ret; } /* request and cfg psi-l */ @@ -358,11 +365,42 @@ struct k3_udma_glue_tx_channel *k3_udma_ ret = k3_udma_glue_cfg_tx_chn(tx_chn); if (ret) { dev_err(dev, "Failed to cfg tchan %d\n", ret); - goto err; + return ret; } k3_udma_glue_dump_tx_chn(tx_chn); + return 0; +} + +struct k3_udma_glue_tx_channel * +k3_udma_glue_request_tx_chn(struct device *dev, const char *name, + struct k3_udma_glue_tx_channel_cfg *cfg) +{ + struct k3_udma_glue_tx_channel *tx_chn; + int ret; + + tx_chn = devm_kzalloc(dev, sizeof(*tx_chn), GFP_KERNEL); + if (!tx_chn) + return ERR_PTR(-ENOMEM); + + tx_chn->common.dev = dev; + tx_chn->common.swdata_size = cfg->swdata_size; + tx_chn->tx_pause_on_err = cfg->tx_pause_on_err; + tx_chn->tx_filt_einfo = cfg->tx_filt_einfo; + tx_chn->tx_filt_pswords = cfg->tx_filt_pswords; + tx_chn->tx_supr_tdpkt = cfg->tx_supr_tdpkt; + + /* parse of udmap channel */ + ret = of_k3_udma_glue_parse_chn(dev->of_node, name, + &tx_chn->common, true); + if (ret) + goto err; + + ret = k3_udma_glue_request_tx_chn_common(dev, tx_chn, cfg); + if (ret) + goto err; + return tx_chn; err: @@ -371,6 +409,40 @@ err: } EXPORT_SYMBOL_GPL(k3_udma_glue_request_tx_chn); +struct k3_udma_glue_tx_channel * +k3_udma_glue_request_tx_chn_by_id(struct device *dev, struct k3_udma_glue_tx_channel_cfg *cfg, + struct device_node *udmax_np, u32 thread_id) +{ + struct k3_udma_glue_tx_channel *tx_chn; + int ret; + + tx_chn = devm_kzalloc(dev, sizeof(*tx_chn), GFP_KERNEL); + if (!tx_chn) + return ERR_PTR(-ENOMEM); + + tx_chn->common.dev = dev; + tx_chn->common.swdata_size = cfg->swdata_size; + tx_chn->tx_pause_on_err = cfg->tx_pause_on_err; + tx_chn->tx_filt_einfo = cfg->tx_filt_einfo; + tx_chn->tx_filt_pswords = cfg->tx_filt_pswords; + tx_chn->tx_supr_tdpkt = cfg->tx_supr_tdpkt; + + ret = of_k3_udma_glue_parse_chn_by_id(udmax_np, &tx_chn->common, true, thread_id); + if (ret) + goto err; + + ret = k3_udma_glue_request_tx_chn_common(dev, tx_chn, cfg); + if (ret) + goto err; + + return tx_chn; + +err: + k3_udma_glue_release_tx_chn(tx_chn); + return ERR_PTR(ret); +} +EXPORT_SYMBOL_GPL(k3_udma_glue_request_tx_chn_by_id); + void k3_udma_glue_release_tx_chn(struct k3_udma_glue_tx_channel *tx_chn) { if (tx_chn->psil_paired) { @@ -911,19 +983,18 @@ k3_udma_glue_request_rx_chn_priv(struct } rx_chn->udma_rchan_id = xudma_rchan_get_id(rx_chn->udma_rchanx); - rx_chn->common.chan_dev.class = &k3_udma_glue_devclass; - rx_chn->common.chan_dev.parent = xudma_get_device(rx_chn->common.udmax); - dev_set_name(&rx_chn->common.chan_dev, "rchan%d-0x%04x", - rx_chn->udma_rchan_id, rx_chn->common.src_thread); - ret = device_register(&rx_chn->common.chan_dev); - if (ret) { - dev_err(dev, "Channel Device registration failed %d\n", ret); - put_device(&rx_chn->common.chan_dev); - rx_chn->common.chan_dev.parent = NULL; - goto err; - } - if (xudma_is_pktdma(rx_chn->common.udmax)) { + rx_chn->common.chan_dev.class = &k3_udma_glue_devclass; + rx_chn->common.chan_dev.parent = xudma_get_device(rx_chn->common.udmax); + dev_set_name(&rx_chn->common.chan_dev, "rchan%d-0x%04x", + rx_chn->udma_rchan_id, rx_chn->common.src_thread); + ret = device_register(&rx_chn->common.chan_dev); + if (ret) { + dev_err(dev, "Channel Device registration failed %d\n", ret); + rx_chn->common.chan_dev.parent = NULL; + goto err; + } + /* prepare the channel device as coherent */ rx_chn->common.chan_dev.dma_coherent = true; dma_coerce_mask_and_coherent(&rx_chn->common.chan_dev, @@ -996,12 +1067,59 @@ err: return ERR_PTR(ret); } +static int +k3_udma_glue_request_remote_rx_chn_common(struct k3_udma_glue_rx_channel *rx_chn, + struct k3_udma_glue_rx_channel_cfg *cfg, + struct device *dev) +{ + int ret, i; + + rx_chn->common.hdesc_size = cppi5_hdesc_calc_size(rx_chn->common.epib, + rx_chn->common.psdata_size, + rx_chn->common.swdata_size); + + rx_chn->flows = devm_kcalloc(dev, rx_chn->flow_num, + sizeof(*rx_chn->flows), GFP_KERNEL); + if (!rx_chn->flows) + return -ENOMEM; + + if (xudma_is_pktdma(rx_chn->common.udmax)) { + rx_chn->common.chan_dev.class = &k3_udma_glue_devclass; + rx_chn->common.chan_dev.parent = xudma_get_device(rx_chn->common.udmax); + dev_set_name(&rx_chn->common.chan_dev, "rchan_remote-0x%04x-0x%02x", + rx_chn->common.src_thread, rx_chn->flow_id_base); + + ret = device_register(&rx_chn->common.chan_dev); + if (ret) { + dev_err(dev, "Channel Device registration failed %d\n", ret); + rx_chn->common.chan_dev.parent = NULL; + return ret; + } + + /* prepare the channel device as coherent */ + rx_chn->common.chan_dev.dma_coherent = true; + dma_coerce_mask_and_coherent(&rx_chn->common.chan_dev, + DMA_BIT_MASK(48)); + } + + ret = k3_udma_glue_allocate_rx_flows(rx_chn, cfg); + if (ret) + return ret; + + for (i = 0; i < rx_chn->flow_num; i++) + rx_chn->flows[i].udma_rflow_id = rx_chn->flow_id_base + i; + + k3_udma_glue_dump_rx_chn(rx_chn); + + return 0; +} + static struct k3_udma_glue_rx_channel * k3_udma_glue_request_remote_rx_chn(struct device *dev, const char *name, struct k3_udma_glue_rx_channel_cfg *cfg) { struct k3_udma_glue_rx_channel *rx_chn; - int ret, i; + int ret; if (cfg->flow_id_num <= 0 || cfg->flow_id_use_rxchan_id || @@ -1032,44 +1150,54 @@ k3_udma_glue_request_remote_rx_chn(struc if (ret) goto err; - rx_chn->common.hdesc_size = cppi5_hdesc_calc_size(rx_chn->common.epib, - rx_chn->common.psdata_size, - rx_chn->common.swdata_size); - - rx_chn->flows = devm_kcalloc(dev, rx_chn->flow_num, - sizeof(*rx_chn->flows), GFP_KERNEL); - if (!rx_chn->flows) { - ret = -ENOMEM; + ret = k3_udma_glue_request_remote_rx_chn_common(rx_chn, cfg, dev); + if (ret) goto err; - } - rx_chn->common.chan_dev.class = &k3_udma_glue_devclass; - rx_chn->common.chan_dev.parent = xudma_get_device(rx_chn->common.udmax); - dev_set_name(&rx_chn->common.chan_dev, "rchan_remote-0x%04x", - rx_chn->common.src_thread); - ret = device_register(&rx_chn->common.chan_dev); - if (ret) { - dev_err(dev, "Channel Device registration failed %d\n", ret); - put_device(&rx_chn->common.chan_dev); - rx_chn->common.chan_dev.parent = NULL; - goto err; - } + return rx_chn; - if (xudma_is_pktdma(rx_chn->common.udmax)) { - /* prepare the channel device as coherent */ - rx_chn->common.chan_dev.dma_coherent = true; - dma_coerce_mask_and_coherent(&rx_chn->common.chan_dev, - DMA_BIT_MASK(48)); - } +err: + k3_udma_glue_release_rx_chn(rx_chn); + return ERR_PTR(ret); +} - ret = k3_udma_glue_allocate_rx_flows(rx_chn, cfg); +struct k3_udma_glue_rx_channel * +k3_udma_glue_request_remote_rx_chn_by_id(struct device *dev, struct device_node *udmax_np, + struct k3_udma_glue_rx_channel_cfg *cfg, u32 thread_id) +{ + struct k3_udma_glue_rx_channel *rx_chn; + int ret; + + if (cfg->flow_id_num <= 0 || + cfg->flow_id_use_rxchan_id || + cfg->def_flow_cfg || + cfg->flow_id_base < 0) + return ERR_PTR(-EINVAL); + + /* + * Remote RX channel is under control of Remote CPU core, so + * Linux can only request and manipulate by dedicated RX flows + */ + + rx_chn = devm_kzalloc(dev, sizeof(*rx_chn), GFP_KERNEL); + if (!rx_chn) + return ERR_PTR(-ENOMEM); + + rx_chn->common.dev = dev; + rx_chn->common.swdata_size = cfg->swdata_size; + rx_chn->remote = true; + rx_chn->udma_rchan_id = -1; + rx_chn->flow_num = cfg->flow_id_num; + rx_chn->flow_id_base = cfg->flow_id_base; + rx_chn->psil_paired = false; + + ret = of_k3_udma_glue_parse_chn_by_id(udmax_np, &rx_chn->common, false, thread_id); if (ret) goto err; - for (i = 0; i < rx_chn->flow_num; i++) - rx_chn->flows[i].udma_rflow_id = rx_chn->flow_id_base + i; - - k3_udma_glue_dump_rx_chn(rx_chn); + ret = k3_udma_glue_request_remote_rx_chn_common(rx_chn, cfg, dev); + if (ret) + goto err; return rx_chn; @@ -1077,6 +1205,7 @@ err: k3_udma_glue_release_rx_chn(rx_chn); return ERR_PTR(ret); } +EXPORT_SYMBOL_GPL(k3_udma_glue_request_remote_rx_chn_by_id); struct k3_udma_glue_rx_channel * k3_udma_glue_request_rx_chn(struct device *dev, const char *name, @@ -1436,4 +1565,6 @@ static int __init k3_udma_glue_class_ini { return class_register(&k3_udma_glue_devclass); } -arch_initcall(k3_udma_glue_class_init); + +module_init(k3_udma_glue_class_init); +MODULE_LICENSE("GPL v2"); Index: linux-6.1.80/drivers/dma/ti/k3-udma.c =================================================================== --- linux-6.1.80.orig/drivers/dma/ti/k3-udma.c +++ linux-6.1.80/drivers/dma/ti/k3-udma.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -54,6 +55,8 @@ struct udma_static_tr { #define UDMA_RFLOW_DSTTAG_DST_TAG_LO 4 #define UDMA_RFLOW_DSTTAG_DST_TAG_HI 5 +#define UDMA_J722S_BCDMA_PSIL_BASE 0x3100 + struct udma_chan; enum k3_dma_type { @@ -134,6 +137,8 @@ struct udma_match_data { u32 flags; u32 statictr_z_mask; u8 burst_size[3]; + struct udma_soc_data *soc_data; + u8 order_id; }; struct udma_soc_data { @@ -303,6 +308,8 @@ struct udma_chan { /* Channel configuration parameters */ struct udma_chan_config config; + /* Channel configuration parameters (backup) */ + struct udma_chan_config backup_config; /* dmapool for packet mode descriptors */ bool use_dma_pool; @@ -1009,9 +1016,14 @@ static int udma_stop(struct udma_chan *u if (!uc->cyclic && !uc->desc) udma_push_to_ring(uc, -1); - udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_RT_EN_REG, - UDMA_PEER_RT_EN_ENABLE | - UDMA_PEER_RT_EN_TEARDOWN); + /* FIXME: Doing a forced teardown for McASP PDMA to prevent channel corruption */ + if (uc->cyclic && uc->config.ep_type == PSIL_EP_PDMA_XY && + uc->config.enable_acc32 && uc->config.enable_burst) + udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_RT_EN_REG, 0); + else + udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_RT_EN_REG, + UDMA_PEER_RT_EN_ENABLE | + UDMA_PEER_RT_EN_TEARDOWN); break; case DMA_MEM_TO_DEV: udma_tchanrt_write(uc, UDMA_CHAN_RT_PEER_RT_EN_REG, @@ -2107,6 +2119,7 @@ static int udma_tisci_rx_channel_config( static int bcdma_tisci_rx_channel_config(struct udma_chan *uc) { struct udma_dev *ud = uc->ud; + const struct udma_match_data *match_data = ud->match_data; struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; struct udma_rchan *rchan = uc->rchan; @@ -2117,6 +2130,11 @@ static int bcdma_tisci_rx_channel_config req_rx.nav_id = tisci_rm->tisci_dev_id; req_rx.index = rchan->id; + if (match_data->order_id) { + req_rx.valid_params |= TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID; + req_rx.rx_orderid = match_data->order_id; + } + ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx); if (ret) dev_err(ud->dev, "rchan%d cfg failed %d\n", rchan->id, ret); @@ -2962,6 +2980,7 @@ udma_prep_slave_sg_triggered_tr(struct u struct scatterlist *sgent; struct cppi5_tr_type15_t *tr_req = NULL; enum dma_slave_buswidth dev_width; + u32 csf = CPPI5_TR_CSF_SUPR_EVT; u16 tr_cnt0, tr_cnt1; dma_addr_t dev_addr; struct udma_desc *d; @@ -3032,6 +3051,7 @@ udma_prep_slave_sg_triggered_tr(struct u if (uc->ud->match_data->type == DMA_TYPE_UDMA) { asel = 0; + csf |= CPPI5_TR_CSF_EOL_ICNT0; } else { asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; dev_addr |= asel; @@ -3055,7 +3075,7 @@ udma_prep_slave_sg_triggered_tr(struct u cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, false, true, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT); + cppi5_tr_csf_set(&tr_req[tr_idx].flags, csf); cppi5_tr_set_trigger(&tr_req[tr_idx].flags, uc->config.tr_trigger_type, CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC, 0, 0); @@ -3101,8 +3121,7 @@ udma_prep_slave_sg_triggered_tr(struct u cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, false, true, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[tr_idx].flags, - CPPI5_TR_CSF_SUPR_EVT); + cppi5_tr_csf_set(&tr_req[tr_idx].flags, csf); cppi5_tr_set_trigger(&tr_req[tr_idx].flags, uc->config.tr_trigger_type, CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC, @@ -3146,8 +3165,7 @@ udma_prep_slave_sg_triggered_tr(struct u d->residue += sg_len; } - cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, - CPPI5_TR_CSF_SUPR_EVT | CPPI5_TR_CSF_EOP); + cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, csf | CPPI5_TR_CSF_EOP); return d; } @@ -3676,6 +3694,7 @@ udma_prep_dma_memcpy(struct dma_chan *ch int num_tr; size_t tr_size = sizeof(struct cppi5_tr_type15_t); u16 tr0_cnt0, tr0_cnt1, tr1_cnt0; + u32 csf = CPPI5_TR_CSF_SUPR_EVT; if (uc->config.dir != DMA_MEM_TO_MEM) { dev_err(chan->device->dev, @@ -3706,13 +3725,15 @@ udma_prep_dma_memcpy(struct dma_chan *ch if (uc->ud->match_data->type != DMA_TYPE_UDMA) { src |= (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT; dest |= (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT; + } else { + csf |= CPPI5_TR_CSF_EOL_ICNT0; } tr_req = d->hwdesc[0].tr_req_base; cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[0].flags, CPPI5_TR_CSF_SUPR_EVT); + cppi5_tr_csf_set(&tr_req[0].flags, csf); tr_req[0].addr = src; tr_req[0].icnt0 = tr0_cnt0; @@ -3731,7 +3752,7 @@ udma_prep_dma_memcpy(struct dma_chan *ch if (num_tr == 2) { cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[1].flags, CPPI5_TR_CSF_SUPR_EVT); + cppi5_tr_csf_set(&tr_req[1].flags, csf); tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0; tr_req[1].icnt0 = tr1_cnt0; @@ -3746,8 +3767,7 @@ udma_prep_dma_memcpy(struct dma_chan *ch tr_req[1].dicnt3 = 1; } - cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, - CPPI5_TR_CSF_SUPR_EVT | CPPI5_TR_CSF_EOP); + cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, csf | CPPI5_TR_CSF_EOP); if (uc->config.metadata_size) d->vd.tx.metadata_ops = &metadata_ops; @@ -4301,6 +4321,61 @@ static struct udma_match_data j721e_mcu_ }, }; +static struct udma_soc_data j721s2_bcdma_soc_data = { + .oes = { + .bcdma_tchan_data = 0x800, + .bcdma_tchan_ring = 0xa00, + .bcdma_rchan_data = 0xe00, + .bcdma_rchan_ring = 0x1000, + }, +}; + +static struct udma_soc_data am62a_dmss_csi_soc_data = { + .oes = { + .bcdma_rchan_data = 0xe00, + .bcdma_rchan_ring = 0x1000, + }, +}; + +static struct udma_match_data am62a_bcdma_csirx_data = { + .type = DMA_TYPE_BCDMA, + .psil_base = 0x3100, + .enable_memcpy_support = false, + .burst_size = { + TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */ + 0, /* No H Channels */ + 0, /* No UH Channels */ + }, + .soc_data = &am62a_dmss_csi_soc_data, + .order_id = 8, +}; + +static struct udma_match_data j721s2_bcdma_data = { + .type = DMA_TYPE_BCDMA, + .psil_base = 0x2000, + .enable_memcpy_support = false, + .burst_size = { + TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */ + 0, /* No H Channels */ + 0, /* No UH Channels */ + }, + .soc_data = &j721s2_bcdma_soc_data, + .order_id = 15, +}; + +static struct udma_match_data j722s_bcdma_data = { + .type = DMA_TYPE_BCDMA, + .psil_base = UDMA_J722S_BCDMA_PSIL_BASE, + .enable_memcpy_support = false, + .burst_size = { + TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */ + 0, /* No H Channels */ + 0, /* No UH Channels */ + }, + .soc_data = &j721s2_bcdma_soc_data, + .order_id = 15, +}; + static struct udma_match_data am64_bcdma_data = { .type = DMA_TYPE_BCDMA, .psil_base = 0x2000, /* for tchan and rchan, not applicable to bchan */ @@ -4342,22 +4417,26 @@ static const struct of_device_id udma_of .compatible = "ti,j721e-navss-mcu-udmap", .data = &j721e_mcu_data, }, - { /* Sentinel */ }, -}; - -static const struct of_device_id bcdma_of_match[] = { { .compatible = "ti,am64-dmss-bcdma", .data = &am64_bcdma_data, }, - { /* Sentinel */ }, -}; - -static const struct of_device_id pktdma_of_match[] = { { .compatible = "ti,am64-dmss-pktdma", .data = &am64_pktdma_data, }, + { + .compatible = "ti,am62a-dmss-bcdma-csirx", + .data = &am62a_bcdma_csirx_data, + }, + { + .compatible = "ti,j721s2-dmss-bcdma-csi", + .data = &j721s2_bcdma_data, + }, + { + .compatible = "ti,j722s-dmss-bcdma-csi", + .data = &j722s_bcdma_data, + }, { /* Sentinel */ }, }; @@ -4400,6 +4479,10 @@ static const struct soc_device_attribute { .family = "AM64X", .data = &am64_soc_data }, { .family = "J721S2", .data = &j721e_soc_data}, { .family = "AM62X", .data = &am64_soc_data }, + { .family = "AM62AX", .data = &am64_soc_data }, + { .family = "J784S4", .data = &j721e_soc_data }, + { .family = "AM62PX", .data = &am64_soc_data }, + { .family = "J722S", .data = &am64_soc_data }, { /* sentinel */ } }; @@ -4424,6 +4507,7 @@ static int udma_get_mmrs(struct platform break; case DMA_TYPE_BCDMA: ud->bchan_cnt = BCDMA_CAP2_BCHAN_CNT(cap2); + ud->bchan_cnt += BCDMA_CAP3_HBCHAN_CNT(cap3) + BCDMA_CAP3_UBCHAN_CNT(cap3); ud->tchan_cnt = BCDMA_CAP2_TCHAN_CNT(cap2); ud->rchan_cnt = BCDMA_CAP2_RCHAN_CNT(cap2); ud->rflow_cnt = ud->rchan_cnt; @@ -4788,7 +4872,10 @@ static int bcdma_setup_resources(struct irq_res.desc[i].num = rm_res->desc[i].num; } } + } else { + i = 0; } + if (ud->tchan_cnt) { rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; if (IS_ERR(rm_res)) { @@ -5278,23 +5365,21 @@ static int udma_probe(struct platform_de return -ENOMEM; match = of_match_node(udma_of_match, dev->of_node); - if (!match) - match = of_match_node(bcdma_of_match, dev->of_node); if (!match) { - match = of_match_node(pktdma_of_match, dev->of_node); - if (!match) { - dev_err(dev, "No compatible match found\n"); - return -ENODEV; - } + dev_err(dev, "No compatible match found\n"); + return -ENODEV; } ud->match_data = match->data; - soc = soc_device_match(k3_soc_devices); - if (!soc) { - dev_err(dev, "No compatible SoC found\n"); - return -ENODEV; + ud->soc_data = ud->match_data->soc_data; + if (!ud->soc_data) { + soc = soc_device_match(k3_soc_devices); + if (!soc) { + dev_err(dev, "No compatible SoC found\n"); + return -ENODEV; + } + ud->soc_data = soc->data; } - ud->soc_data = soc->data; ret = udma_get_mmrs(pdev, ud); if (ret) @@ -5363,7 +5448,6 @@ static int udma_probe(struct platform_de dev->msi.domain = of_msi_get_domain(dev, dev->of_node, DOMAIN_BUS_TI_SCI_INTA_MSI); if (!dev->msi.domain) { - dev_err(dev, "Failed to get MSI domain\n"); return -EPROBE_DEFER; } @@ -5510,35 +5594,69 @@ static int udma_probe(struct platform_de return ret; } +static int udma_pm_suspend(struct device *dev) +{ + struct udma_dev *ud = dev_get_drvdata(dev); + struct dma_device *dma_dev = &ud->ddev; + struct dma_chan *chan; + struct udma_chan *uc; + + list_for_each_entry(chan, &dma_dev->channels, device_node) { + if (chan->client_count) { + uc = to_udma_chan(chan); + /* backup the channel configuration */ + memcpy(&uc->backup_config, &uc->config, + sizeof(struct udma_chan_config)); + dev_dbg(dev, "Suspending channel %s\n", + dma_chan_name(chan)); + ud->ddev.device_free_chan_resources(chan); + } + } + + return 0; +} + +static int udma_pm_resume(struct device *dev) +{ + struct udma_dev *ud = dev_get_drvdata(dev); + struct dma_device *dma_dev = &ud->ddev; + struct dma_chan *chan; + struct udma_chan *uc; + int ret; + + list_for_each_entry(chan, &dma_dev->channels, device_node) { + if (chan->client_count) { + uc = to_udma_chan(chan); + /* restore the channel configuration */ + memcpy(&uc->config, &uc->backup_config, + sizeof(struct udma_chan_config)); + dev_dbg(dev, "Resuming channel %s\n", + dma_chan_name(chan)); + ret = ud->ddev.device_alloc_chan_resources(chan); + if (ret) + return ret; + } + } + + return 0; +} + +static const struct dev_pm_ops udma_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(udma_pm_suspend, udma_pm_resume) +}; + static struct platform_driver udma_driver = { .driver = { .name = "ti-udma", .of_match_table = udma_of_match, .suppress_bind_attrs = true, + .pm = &udma_pm_ops, }, .probe = udma_probe, }; -builtin_platform_driver(udma_driver); -static struct platform_driver bcdma_driver = { - .driver = { - .name = "ti-bcdma", - .of_match_table = bcdma_of_match, - .suppress_bind_attrs = true, - }, - .probe = udma_probe, -}; -builtin_platform_driver(bcdma_driver); - -static struct platform_driver pktdma_driver = { - .driver = { - .name = "ti-pktdma", - .of_match_table = pktdma_of_match, - .suppress_bind_attrs = true, - }, - .probe = udma_probe, -}; -builtin_platform_driver(pktdma_driver); +module_platform_driver(udma_driver); +MODULE_LICENSE("GPL v2"); /* Private interfaces to UDMA */ #include "k3-udma-private.c" Index: linux-6.1.80/drivers/firmware/ti_sci.c =================================================================== --- linux-6.1.80.orig/drivers/firmware/ti_sci.c +++ linux-6.1.80/drivers/firmware/ti_sci.c @@ -10,7 +10,9 @@ #include #include +#include #include +#include #include #include #include @@ -21,10 +23,16 @@ #include #include #include +#include #include #include "ti_sci.h" +/* Low power mode memory context size */ +#define LPM_CTX_MEM_SIZE 0x80000 + +#define AM62X_DEV_MCU_M4FSS0_CORE0_DEV_ID 9 + /* List of all TI SCI devices active in system */ static LIST_HEAD(ti_sci_list); /* Protection for the entire list */ @@ -96,6 +104,9 @@ struct ti_sci_desc { * @minfo: Message info * @node: list head * @host_id: Host ID + * @ctx_mem_addr: Low power context memory phys address + * @ctx_mem_buf: Low power context memory buffer + * @fw_caps: FW/SoC low power capabilities * @users: Number of users of this instance */ struct ti_sci_info { @@ -113,8 +124,14 @@ struct ti_sci_info { struct ti_sci_xfers_info minfo; struct list_head node; u8 host_id; + dma_addr_t ctx_mem_addr; + void *ctx_mem_buf; + u64 fw_caps; /* protected by ti_sci_list_mutex */ int users; + + int nr_wakeup_sources; + struct device_node **wakeup_source_nodes; }; #define cl_to_ti_sci_info(c) container_of(c, struct ti_sci_info, cl) @@ -196,11 +213,6 @@ static inline int ti_sci_debugfs_create( { return 0; } - -static inline void ti_sci_debugfs_destroy(struct platform_device *dev, - struct ti_sci_info *info) -{ -} #endif /* CONFIG_DEBUG_FS */ /** @@ -381,6 +393,28 @@ static void ti_sci_put_one_xfer(struct t } /** + * ti_sci_do_send() - Do one send, do not expect a response + * @info: Pointer to SCI entity information + * @xfer: Transfer to initiate + * + * Return: If send error, return corresponding error, else + * if all goes well, return 0. + */ +static inline int ti_sci_do_send(struct ti_sci_info *info, + struct ti_sci_xfer *xfer) +{ + int ret; + + ret = mbox_send_message(info->chan_tx, &xfer->tx_message); + if (ret < 0) + return ret; + + mbox_client_txdone(info->chan_tx, ret); + + return 0; +} + +/** * ti_sci_do_xfer() - Do one transfer * @info: Pointer to SCI entity information * @xfer: Transfer to initiate and wait for response @@ -1651,6 +1685,232 @@ fail: return ret; } +/** + * ti_sci_cmd_prepare_sleep() - Prepare system for system suspend + * @handle: pointer to TI SCI handle + * @mode: Device identifier + * @ctx_lo: Low part of address for context save + * @ctx_hi: High part of address for context save + * @debug_flags: Debug flags to pass to firmware + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_prepare_sleep(const struct ti_sci_handle *handle, u8 mode, + u32 ctx_lo, u32 ctx_hi, u32 debug_flags) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_prepare_sleep *req; + struct ti_sci_msg_hdr *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_PREPARE_SLEEP, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + + req = (struct ti_sci_msg_req_prepare_sleep *)xfer->xfer_buf; + req->mode = mode; + req->ctx_lo = ctx_lo; + req->ctx_hi = ctx_hi; + req->debug_flags = debug_flags; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf; + + ret = ti_sci_is_response_ack(resp) ? 0 : -ENODEV; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_msg_cmd_query_fw_caps() - Get the FW/SoC capabilities + * @handle: Pointer to TI SCI handle + * @fw_caps: Each bit in fw_caps indicating one FW/SOC capability + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_msg_cmd_query_fw_caps(const struct ti_sci_handle *handle, + u64 *fw_caps) +{ + struct ti_sci_info *info; + struct ti_sci_xfer *xfer; + struct ti_sci_msg_resp_query_fw_caps *resp; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_QUERY_FW_CAPS, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(struct ti_sci_msg_hdr), + sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_resp_query_fw_caps *)xfer->xfer_buf; + + if (!ti_sci_is_response_ack(resp)) { + ret = -ENODEV; + goto fail; + } + + if (fw_caps) + *fw_caps = resp->fw_caps; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_msg_cmd_lpm_wake_reason() - Get the wakeup source from LPM + * @handle: Pointer to TI SCI handle + * @source: The wakeup source that woke the SoC from LPM + * @timestamp: Timestamp of the wakeup event + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_msg_cmd_lpm_wake_reason(const struct ti_sci_handle *handle, + u32 *source, u64 *timestamp) +{ + struct ti_sci_info *info; + struct ti_sci_xfer *xfer; + struct ti_sci_msg_resp_lpm_wake_reason *resp; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_LPM_WAKE_REASON, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(struct ti_sci_msg_hdr), + sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_resp_lpm_wake_reason *)xfer->xfer_buf; + + if (!ti_sci_is_response_ack(resp)) { + ret = -ENODEV; + goto fail; + } + + if (source) + *source = resp->wake_source; + if (timestamp) + *timestamp = resp->wake_timestamp; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_cmd_set_io_isolation() - Enable IO isolation in LPM + * @handle: Pointer to TI SCI handle + * @state: The desired state of the IO isolation + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_set_io_isolation(const struct ti_sci_handle *handle, + u8 state) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_set_io_isolation *req; + struct ti_sci_msg_hdr *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_SET_IO_ISOLATION, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_req_set_io_isolation *)xfer->xfer_buf; + req->state = state; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf; + + ret = ti_sci_is_response_ack(resp) ? 0 : -ENODEV; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + static int ti_sci_cmd_core_reboot(const struct ti_sci_handle *handle) { struct ti_sci_info *info; @@ -2792,6 +3052,7 @@ static void ti_sci_setup_ops(struct ti_s struct ti_sci_core_ops *core_ops = &ops->core_ops; struct ti_sci_dev_ops *dops = &ops->dev_ops; struct ti_sci_clk_ops *cops = &ops->clk_ops; + struct ti_sci_pm_ops *pmops = &ops->pm_ops; struct ti_sci_rm_core_ops *rm_core_ops = &ops->rm_core_ops; struct ti_sci_rm_irq_ops *iops = &ops->rm_irq_ops; struct ti_sci_rm_ringacc_ops *rops = &ops->rm_ring_ops; @@ -2831,6 +3092,10 @@ static void ti_sci_setup_ops(struct ti_s cops->set_freq = ti_sci_cmd_clk_set_freq; cops->get_freq = ti_sci_cmd_clk_get_freq; + pmops->prepare_sleep = ti_sci_cmd_prepare_sleep; + pmops->lpm_wake_reason = ti_sci_msg_cmd_lpm_wake_reason; + pmops->set_io_isolation = ti_sci_cmd_set_io_isolation; + rm_core_ops->get_range = ti_sci_cmd_get_resource_range; rm_core_ops->get_range_from_shost = ti_sci_cmd_get_resource_range_from_shost; @@ -3267,6 +3532,180 @@ static int tisci_reboot_handler(struct n return NOTIFY_BAD; } +static int ti_sci_prepare_system_suspend(struct ti_sci_info *info) +{ +#if IS_ENABLED(CONFIG_SUSPEND) + u8 mode, unused; + u8 mcu_state = 0; + + /* + * Dev ID 9 is AM62X_DEV_MCU_M4FSS0_CORE0. Check state to determine + * MCU only or deep sleep mode + */ + ti_sci_get_device_state(&info->handle, AM62X_DEV_MCU_M4FSS0_CORE0_DEV_ID, + NULL, NULL, &mcu_state, &unused); + + /* Map and validate the target Linux suspend state to TISCI LPM. */ + switch (pm_suspend_target_state) { + case PM_SUSPEND_MEM: + /* S2MEM is not supported by the firmware. */ + if (!(info->fw_caps & MSG_FLAG_CAPS_LPM_DEEP_SLEEP)) + return 0; + + mode = mcu_state ? TISCI_MSG_VALUE_SLEEP_MODE_MCU_ONLY + : TISCI_MSG_VALUE_SLEEP_MODE_DEEP_SLEEP; + + break; + default: + /* + * Do not fail if we don't have action to take for a + * specific suspend mode. + */ + return 0; + } + + return ti_sci_cmd_prepare_sleep(&info->handle, mode, + (u32)(info->ctx_mem_addr & 0xffffffff), + (u32)((u64)info->ctx_mem_addr >> 32), 0); +#else + return 0; +#endif +} + +static int ti_sci_suspend(struct device *dev) +{ + struct ti_sci_info *info = dev_get_drvdata(dev); + int ret; + + ret = ti_sci_cmd_set_io_isolation(&info->handle, TISCI_MSG_VALUE_IO_ENABLE); + if (ret) + return ret; + dev_dbg(dev, "%s: set isolation: %d\n", __func__, ret); + + ret = ti_sci_prepare_system_suspend(info); + if (ret) + return ret; + + return 0; +} + +static int ti_sci_resume(struct device *dev) +{ + struct ti_sci_info *info = dev_get_drvdata(dev); + u32 source; + u64 time; + int ret = 0; + + ret = ti_sci_cmd_set_io_isolation(&info->handle, TISCI_MSG_VALUE_IO_DISABLE); + if (ret) + return ret; + dev_dbg(dev, "%s: disable isolation: %d\n", __func__, ret); + + ti_sci_msg_cmd_lpm_wake_reason(&info->handle, &source, &time); + dev_info(dev, "%s: wakeup source: 0x%X\n", __func__, source); + + return 0; +} + +static const struct dev_pm_ops ti_sci_pm_ops = { + .suspend_noirq = ti_sci_suspend, + .resume_noirq = ti_sci_resume, +}; + +/* Does not return if successful */ +static int tisci_enter_partial_io(struct ti_sci_info *info) +{ + struct ti_sci_msg_req_prepare_sleep *req; + struct ti_sci_xfer *xfer; + struct device *dev = info->dev; + u32 ctx_lo = (u32)(info->ctx_mem_addr & 0xffffffff); + u32 ctx_hi = (u32)((u64)info->ctx_mem_addr >> 32); + int ret = 0; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_PREPARE_SLEEP, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(struct ti_sci_msg_hdr)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + + req = (struct ti_sci_msg_req_prepare_sleep *)xfer->xfer_buf; + req->mode = TISCI_MSG_VALUE_SLEEP_MODE_PARTIAL_IO; + req->ctx_lo = ctx_lo; + req->ctx_hi = ctx_hi; + req->debug_flags = 0; + + ret = ti_sci_do_send(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +static int tisci_sys_off_handler(struct sys_off_data *data) +{ + struct ti_sci_info *info = data->cb_data; + int i; + int ret; + bool enter_partial_io = false; + + for (i = 0; i != info->nr_wakeup_sources; ++i) { + struct platform_device *pdev = + of_find_device_by_node(info->wakeup_source_nodes[i]); + + if (!pdev) + continue; + + if (device_may_wakeup(&pdev->dev)) { + dev_dbg(info->dev, "%pOFp identified as wakeup source\n", + info->wakeup_source_nodes[i]); + enter_partial_io = true; + } + } + + if (!enter_partial_io) + return NOTIFY_DONE; + + ret = tisci_enter_partial_io(info); + + if (ret) + dev_err(info->dev, + "Failed to enter Partial-IO %pe, halting system\n", + ERR_PTR(ret)); + + /* Halt system/code execution */ + while (1) + ; + + return NOTIFY_DONE; +} + +static int ti_sci_init_suspend(struct platform_device *pdev, + struct ti_sci_info *info) +{ + struct device *dev = &pdev->dev; + + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); + info->ctx_mem_buf = dma_alloc_attrs(info->dev, LPM_CTX_MEM_SIZE, + &info->ctx_mem_addr, + GFP_KERNEL, + DMA_ATTR_NO_KERNEL_MAPPING | + DMA_ATTR_FORCE_CONTIGUOUS); + if (!info->ctx_mem_buf) { + dev_err(info->dev, "Failed to allocate LPM context memory\n"); + return -ENOMEM; + } + + return 0; +} + /* Description for K2G */ static const struct ti_sci_desc ti_sci_pmmc_k2g_desc = { .default_host_id = 2, @@ -3419,6 +3858,44 @@ static int ti_sci_probe(struct platform_ } } + if (of_property_read_bool(dev->of_node, "ti,partial-io-wakeup-sources")) { + info->nr_wakeup_sources = + of_count_phandle_with_args(dev->of_node, + "ti,partial-io-wakeup-sources", + NULL); + info->wakeup_source_nodes = + devm_kzalloc(dev, sizeof(*info->wakeup_source_nodes), + GFP_KERNEL); + + for (i = 0; i != info->nr_wakeup_sources; ++i) { + struct device_node *devnode = + of_parse_phandle(dev->of_node, + "ti,partial-io-wakeup-sources", + i); + info->wakeup_source_nodes[i] = devnode; + } + + ret = devm_register_sys_off_handler(dev, + SYS_OFF_MODE_POWER_OFF, + SYS_OFF_PRIO_FIRMWARE, + tisci_sys_off_handler, + info); + if (ret) { + dev_err(dev, "Failed to register sys_off_handler %pe\n", + ERR_PTR(ret)); + goto unregister_restart; + } + } + + /* + * Check if the firmware supports any optional low power modes + * and initialize them if present. Old revisions of TIFS (< 08.04) + * will NACK the request. + */ + ret = ti_sci_msg_cmd_query_fw_caps(&info->handle, &info->fw_caps); + if (!ret && (info->fw_caps & MSG_MASK_CAPS_LPM)) + ti_sci_init_suspend(pdev, info); + dev_info(dev, "ABI: %d.%d (firmware rev 0x%04x '%s')\n", info->handle.version.abi_major, info->handle.version.abi_minor, info->handle.version.firmware_revision, @@ -3428,7 +3905,17 @@ static int ti_sci_probe(struct platform_ list_add_tail(&info->node, &ti_sci_list); mutex_unlock(&ti_sci_list_mutex); - return of_platform_populate(dev->of_node, NULL, NULL, dev); + ret = of_platform_populate(dev->of_node, NULL, NULL, dev); + if (ret) { + dev_err(dev, "platform_populate failed %pe\n", ERR_PTR(ret)); + goto unregister_restart; + } + return 0; + +unregister_restart: + if (info->nb.notifier_call) + unregister_restart_handler(&info->nb); + out: if (!IS_ERR(info->chan_tx)) mbox_free_channel(info->chan_tx); @@ -3444,6 +3931,7 @@ static struct platform_driver ti_sci_dri .name = "ti-sci", .of_match_table = of_match_ptr(ti_sci_of_match), .suppress_bind_attrs = true, + .pm = &ti_sci_pm_ops, }, }; module_platform_driver(ti_sci_driver); Index: linux-6.1.80/drivers/firmware/ti_sci.h =================================================================== --- linux-6.1.80.orig/drivers/firmware/ti_sci.h +++ linux-6.1.80/drivers/firmware/ti_sci.h @@ -6,7 +6,7 @@ * The system works in a message response protocol * See: http://processors.wiki.ti.com/index.php/TISCI for details * - * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2015-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __TI_SCI_H @@ -19,6 +19,7 @@ #define TI_SCI_MSG_WAKE_REASON 0x0003 #define TI_SCI_MSG_GOODBYE 0x0004 #define TI_SCI_MSG_SYS_RESET 0x0005 +#define TI_SCI_MSG_QUERY_FW_CAPS 0x0022 /* Device requests */ #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200 @@ -35,6 +36,11 @@ #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e +/* Low Power Mode Requests */ +#define TI_SCI_MSG_PREPARE_SLEEP 0x0300 +#define TI_SCI_MSG_LPM_WAKE_REASON 0x0306 +#define TI_SCI_MSG_SET_IO_ISOLATION 0x0307 + /* Resource Management Requests */ #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500 @@ -133,6 +139,31 @@ struct ti_sci_msg_req_reboot { } __packed; /** + * struct ti_sci_msg_resp_query_fw_caps - Response for query firmware caps + * @hdr: Generic header + * @fw_caps: Each bit in fw_caps indicating one FW/SOC capability + * MSG_FLAG_CAPS_GENERIC: Generic capability (LPM not supported) + * MSG_FLAG_CAPS_LPM_DEEP_SLEEP: Deep Sleep LPM + * MSG_FLAG_CAPS_LPM_MCU_ONLY: MCU only LPM + * MSG_FLAG_CAPS_LPM_STANDBY: Standby LPM + * MSG_FLAG_CAPS_LPM_PARTIAL_IO: Partial IO in LPM + * + * Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS + * providing currently available SOC/firmware capabilities. SoC that don't + * support low power modes return only MSG_FLAG_CAPS_GENERIC capability. + */ +struct ti_sci_msg_resp_query_fw_caps { + struct ti_sci_msg_hdr hdr; +#define MSG_FLAG_CAPS_GENERIC TI_SCI_MSG_FLAG(0) +#define MSG_FLAG_CAPS_LPM_DEEP_SLEEP TI_SCI_MSG_FLAG(1) +#define MSG_FLAG_CAPS_LPM_MCU_ONLY TI_SCI_MSG_FLAG(2) +#define MSG_FLAG_CAPS_LPM_STANDBY TI_SCI_MSG_FLAG(3) +#define MSG_FLAG_CAPS_LPM_PARTIAL_IO TI_SCI_MSG_FLAG(4) +#define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1) + u64 fw_caps; +} __packed; + +/** * struct ti_sci_msg_req_set_device_state - Set the desired state of the device * @hdr: Generic header * @id: Indicates which device to modify @@ -545,6 +576,64 @@ struct ti_sci_msg_resp_get_clock_freq { u64 freq_hz; } __packed; +#define TISCI_MSG_VALUE_SLEEP_MODE_DEEP_SLEEP 0x0 +#define TISCI_MSG_VALUE_SLEEP_MODE_MCU_ONLY 0x1 +#define TISCI_MSG_VALUE_SLEEP_MODE_STANDBY 0x2 +#define TISCI_MSG_VALUE_SLEEP_MODE_PARTIAL_IO 0x3 + +/** + * struct tisci_msg_prepare_sleep_req - Request for TISCI_MSG_PREPARE_SLEEP. + * + * @hdr TISCI header to provide ACK/NAK flags to the host. + * @mode Low power mode to enter. + * @ctx_lo Low 32-bits of physical pointer to address to use for context save. + * @ctx_hi High 32-bits of physical pointer to address to use for context save. + * @debug_flags Flags that can be set to halt the sequence during suspend or + * resume to allow JTAG connection and debug. + * + * This message is used as the first step of entering a low power mode. It + * allows configurable information, including which state to enter to be + * easily shared from the application, as this is a non-secure message and + * therefore can be sent by anyone. + */ +struct ti_sci_msg_req_prepare_sleep { + struct ti_sci_msg_hdr hdr; + u8 mode; + u32 ctx_lo; + u32 ctx_hi; + u32 debug_flags; +} __packed; + +/** + * struct ti_sci_msg_resp_lpm_wake_reason - Response for TI_SCI_MSG_LPM_WAKE_REASON. + * + * @hdr: Generic header. + * @wake_source: The wake up source that woke soc from LPM. + * @wake_timestamp: Timestamp at which soc woke. + * + * Response to a generic message with message type TI_SCI_MSG_LPM_WAKE_REASON, + * used to query the wake up source from low power mode. + */ +struct ti_sci_msg_resp_lpm_wake_reason { + struct ti_sci_msg_hdr hdr; + u32 wake_source; + u64 wake_timestamp; +} __packed; + +/** + * struct tisci_msg_set_io_isolation_req - Request for TI_SCI_MSG_SET_IO_ISOLATION. + * + * @hdr: Generic header + * @state: The deseared state of the IO isolation. + * + * This message is used to enable/disable IO isolation for low power modes. + * Response is generic ACK / NACK message. + */ +struct ti_sci_msg_req_set_io_isolation { + struct ti_sci_msg_hdr hdr; + u8 state; +} __packed; + #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff /** Index: linux-6.1.80/drivers/gpu/drm/bridge/Kconfig =================================================================== --- linux-6.1.80.orig/drivers/gpu/drm/bridge/Kconfig +++ linux-6.1.80/drivers/gpu/drm/bridge/Kconfig @@ -15,17 +15,6 @@ config DRM_PANEL_BRIDGE menu "Display Interface Bridges" depends on DRM && DRM_BRIDGE -config DRM_CDNS_DSI - tristate "Cadence DPI/DSI bridge" - select DRM_KMS_HELPER - select DRM_MIPI_DSI - select DRM_PANEL_BRIDGE - select GENERIC_PHY_MIPI_DPHY - depends on OF - help - Support Cadence DPI to DSI bridge. This is an internal - bridge and is meant to be directly embedded in a SoC. - config DRM_CHIPONE_ICN6211 tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge" depends on OF Index: linux-6.1.80/drivers/gpu/drm/bridge/Makefile =================================================================== --- linux-6.1.80.orig/drivers/gpu/drm/bridge/Makefile +++ linux-6.1.80/drivers/gpu/drm/bridge/Makefile @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o obj-$(CONFIG_DRM_CHIPONE_ICN6211) += chipone-icn6211.o obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o Index: linux-6.1.80/drivers/gpu/drm/bridge/cadence/Kconfig =================================================================== --- linux-6.1.80.orig/drivers/gpu/drm/bridge/cadence/Kconfig +++ linux-6.1.80/drivers/gpu/drm/bridge/cadence/Kconfig @@ -1,4 +1,25 @@ # SPDX-License-Identifier: GPL-2.0-only +config DRM_CDNS_DSI + tristate "Cadence DPI/DSI bridge" + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL_BRIDGE + select GENERIC_PHY_MIPI_DPHY + depends on OF + help + Support Cadence DPI to DSI bridge. This is an internal + bridge and is meant to be directly embedded in a SoC. + +if DRM_CDNS_DSI + +config DRM_CDNS_DSI_J721E + bool "J721E Cadence DSI wrapper support" + default y + help + Support J721E Cadence DSI wrapper. The wrapper manages + the routing of the DSS DPI signal to the Cadence DSI. +endif + config DRM_CDNS_MHDP8546 tristate "Cadence DPI/DP bridge" select DRM_DISPLAY_DP_HELPER Index: linux-6.1.80/drivers/gpu/drm/bridge/cadence/Makefile =================================================================== --- linux-6.1.80.orig/drivers/gpu/drm/bridge/cadence/Makefile +++ linux-6.1.80/drivers/gpu/drm/bridge/cadence/Makefile @@ -1,4 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o +cdns-dsi-y := cdns-dsi-core.o +cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o Index: linux-6.1.80/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c =================================================================== --- /dev/null +++ linux-6.1.80/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c @@ -0,0 +1,1298 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright: 2017 Cadence Design Systems, Inc. + * + * Author: Boris Brezillon + */ + +#include +#include +#include +#include