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2024-05-16 - 14:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Thu May 16, 2024 12:45:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22872221159,23sleep10-21swapper/107:09:151
20702213149,51sleep00-21swapper/007:06:250
21352201162,25sleep30-21swapper/307:07:163
11802201160,26sleep20-21swapper/207:05:222
171012590,0sleep10-21swapper/109:39:051
277852170,0sleep00-21swapper/011:20:120
2448991211,1cyclictest35-21ksoftirqd/311:35:003
2448991110,1cyclictest35-21ksoftirqd/310:05:013
2437991110,1cyclictest28-21ksoftirqd/211:20:232
243799110,10cyclictest0-21swapper/210:23:542
2427991110,1cyclictest9-21ksoftirqd/010:40:000
244899109,1cyclictest35-21ksoftirqd/312:05:163
244899109,1cyclictest35-21ksoftirqd/310:35:113
244899109,1cyclictest35-21ksoftirqd/309:09:593
243799109,1cyclictest28-21ksoftirqd/212:35:152
243799108,1cyclictest28-21ksoftirqd/209:35:132
243799108,1cyclictest28-21ksoftirqd/209:10:142
243799107,2cyclictest28-21ksoftirqd/210:45:012
243799106,3cyclictest0-21swapper/210:40:012
2437991010,0cyclictest28-21ksoftirqd/211:25:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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