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2026-08-12 - 05:59

Dates and Events:

OSADL Articles:

2024-10-02 12:00

Linux is now an RTOS!

PREEMPT_RT is mainline - What's next?


2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50039,99212.08. 01:10
r0s0sx86_​644 x 23,40054,39212.08. 01:11
r0s1x86_​644 x 22,30056,00012.08. 01:11
r0s1sx86_​644 x 23,30052,80012.08. 01:11
r0s2x86_​644 x 23,50055,87212.08. 01:12
r0s2sx86_​6410 x 13,70073,99012.08. 01:12
r0s3x86_​648 x 23,600115,20012.08. 01:13
r0s3sx86_​644 x 23,60067,20012.08. 01:15
r0s4x86_​648 x 23,600115,20012.08. 01:16
r0s4sx86_​648 x 23,600115,20012.08. 01:16
r0s5x86_​648 x 23,500115,20012.08. 01:17
r0s5sx86_​648 x 23,600115,20012.08. 01:18
r0s6x86_​648 x 23,600115,20012.08. 01:18
r0s6sx86_​6410 x 23,700147,98012.08. 01:19
r0s7x86_​6410 x 13,70073,99012.08. 01:20
r0s7sx86_​642 x 23,70029,53223.05. 13:21
r0s8x86_​648 x 23,600115,20014.03. 13:20
r0s8sx86_​646 x 23,47083,38812.08. 01:21
r1s0x86_​644 x 13,10024,80012.08. 01:21
r1s1x86_​642 x 22,60021,69612.08. 01:22
r1s2x86_​644 x 12,30027,99612.08. 01:22
r1s2sx86_​644 x 12,30028,00012.08. 01:23
r1s3x86_​644 x 12,80022,42412.08. 01:23
r1s3saarch​646 x 12,00028812.08. 01:24
r1s4arm​v7l2 x 11,2004812.08. 01:25
r1s4sarm​v7l2 x 14004812.08. 01:25
r1s5aarch​644 x 11,20079612.08. 01:26
r1s6x86_​642 x 22,13017,06412.08. 01:26
r1s6sx86_​642 x 21,66713,33212.08. 01:27
r1s7arm​v6l1 x 11,66753012.08. 01:27
r1s8i6861 x 21,6006,40012.08. 01:28
r1s8sx86_​644 x 11,90015,19612.08. 01:28
r2s0x86_​644 x 13,60024,79612.08. 01:29
r2s1arm​v5tejl1 x 120019912.08. 01:30
r2s2arm​v7l1 x 172049912.08. 01:30
r2s3arm​v7l0 x 1 x 162462412.08. 01:30
r2s3sarm​v7l0 x 2 x 16001,20012.08. 01:31
r2s4mips​641 x 180053129.09. 13:34
r2s5ppc1 x 13966626.07. 13:34
r2s5sarm​v7l4 x 11,20015212.08. 01:32
r2s6i6861 x 11,5002,99912.08. 01:34
r2s6saarch​644 x 11,3506412.08. 01:34
r2s7aarch​644 x 12,40043212.08. 01:35
r2s7saarch​644 x 11,50043212.08. 01:35
r2s8ppc1 x 14006612.08. 01:36
r3s0i6864 x 23,50055,99212.08. 01:37
r3s1i6864 x 12,40019,12812.08. 01:38
r3s2riscv641 x 11,00028412.08. 01:38
r3s2sriscv644 x 1028412.08. 01:39
r3s3x86_​646 x 23,33379,99212.08. 01:40
r3s3sx86_​644 x 13,40011,98012.08. 01:40
r3s4aarch​646 x 11,3009612.08. 01:41
r3s5i5861 x 113326512.08. 01:42
r3s5sppc2 x 11,20040012.08. 01:43
r3s6x86_​641 x 21,6606,66612.08. 01:44
r3s6sx86_​642 x 22,66721,33212.08. 01:44
r3s7i6861 x 15331,06612.08. 01:45
r4s0x86_​642 x 22,30018,39612.08. 01:46
r4s1aarch​644 x 11,50043212.08. 01:46
r4s1sarm​v7l4 x 11,50093612.08. 01:47
r4s2arm​v7l1 x 180079612.08. 01:48
r4s2sarm​v7l1 x 180053012.08. 01:49
r4s3i5861 x 150099612.08. 01:51
r4s3si6861 x 11,4662,93228.07. 02:17
r4s4ppc4 x 11,20049812.08. 01:52
r4s5arm​v7l1 x 1500012.08. 01:56
r4s5saarch​644 x 11,60020012.08. 01:56
r4s6x86_​644 x 23,40054,25612.08. 01:56
r4s6sarm​v7l0 x 1 x 11,0006612.08. 01:57
r4s7i6864 x 11,83314,66412.08. 01:59
r4s7sx86_​642 x 11,8337,33212.08. 01:59
r4s8arm​v7l1 x 140039812.08. 02:00
r4s8sarm​v7l1 x 140039812.08. 02:00
r5s0x86_​642 x 22,20017,58412.08. 02:01
r5s1x86_​646 x 13,33340,09212.08. 02:01
r5s2x86_​644 x 12,70021,69912.08. 02:02
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87212.08. 02:02
r5s3sx86_​644 x 11,60012,74812.08. 02:03
r5s4x86_​642 x 22,53020,26412.08. 02:04
r5s4sx86_​644 x 11,60012,74812.08. 02:05
r5s5arm​v7l1 x 160059712.08. 02:07
r5s5sarm​v7l1 x 160060012.08. 02:08
r5s6ppc1 x 153313312.08. 02:12
r5s7arm​v7l1 x 15286412.08. 02:12
r5s7sarm​v7l1 x 15286412.08. 02:14
r5s8x86_​644 x 12,00015,97212.08. 02:15
r6s0x86_​642 x 10 x 21,700136,14012.08. 02:16
r6s1x86_​642 x 12,0007,97812.12. 02:21
r6s2x86_​642 x 11,6679,57812.08. 02:16
r6s3x86_​644 x 22,20035,12012.08. 02:17
r6s4x86_​642 x 11,1004,37612.08. 02:17
r6s5i6861 x 11,5002,99212.08. 02:18
r6s6i6861 x 11,6003,19212.08. 02:19
r6s7i6862 x 12,3009,17612.08. 02:20
r6s8x86_​642 x 22,30018,35612.08. 02:21
r7s0x86_​642 x 22,30018,40012.08. 02:21
r7s1x86_​644 x 11,60012,83912.08. 02:22
r7s2aarch​642 x 11,7009612.08. 02:22
r7s2sriscv644 x 1028412.08. 02:23
r7s3arm​v6l1 x 1700512.08. 02:24
r7s3sarm​v7l4 x 11,40015212.08. 02:26
r7s4arm​v7l1 x 153634812.08. 02:27
r7s4sarm​v7l4 x 11,5001,08012.08. 02:28
r7s5i6861 x 11,3002,59312.08. 02:28
r7s6arm​v7l1 x 11,00039802.07. 02:27
r7s7x86_​644 x 11,60012,76712.08. 02:29
r7s7sx86_​642 x 22,30018,39612.08. 02:29
r7s8arm​v7l1 x 11,00099512.08. 02:30
r7s8sarm​v7l1 x 11,00079612.08. 02:32
r8s0x86_​642 x 22,30018,40012.08. 02:32
r8s1i5861 x 135070112.08. 02:33
r8s2aarch​644 x 11,4001,60012.08. 02:33
r8s2saarch​644 x 11,4001,60012.08. 02:34
r8s3x86_​644 x 12,66721,28012.08. 02:35
r8s4x86_​644 x 21,60028,80012.08. 02:36
r8s4sx86_​644 x 21,60028,80011.08. 02:36
r8s5i6864 x 23,40054,40012.08. 02:36
r8s6arm​v7l1 x 150049812.08. 02:37
r8s6sx86_​644 x 13,30026,41611.08. 02:38
r8s7x86_​644 x 13,20025,49612.08. 02:37
r8s7sx86_​642 x 13,00011,98012.08. 02:37
r8s8x86_​642 x 11,3005,14412.08. 02:38
r9s0x86_​644 x 23,60057,60012.08. 02:39
r9s1x86_​642 x 12,0007,98412.02. 14:30
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2arm​v7l0 x 1 x 155040012.08. 02:40
r9s2sarm​v7l0 x 1 x 155040012.08. 02:41
r9s3x86_​644 x 11,60012,74812.08. 02:41
r9s3sx86_​644 x 13,00024,00012.08. 02:42
r9s4i6861 x 21,0003,99012.08. 02:43
r9s4sx86_​642 x 11,3335,34712.08. 02:43
r9s5x86_​644 x 21,90028,80012.08. 02:44
r9s5sx86_​642 x 13,30013,19812.08. 02:44
r9s6x86_​642 x 23,00023,94412.08. 02:45
r9s7arm​v7l2 x 11,000012.08. 02:46
r9s8aarch​644 x 11,50043212.08. 02:46
r9s8sriscv644 x 1028412.08. 02:47
ras0x86_​642 x 22,30018,41812.08. 02:47
ras1i6861 x 11,4002,79912.08. 02:48
ras2x86_​642 x 11,0674,26612.08. 02:48
ras2sx86_​644 x 11,90015,05230.07. 14:50
ras3aarch​648 x 12,0004,00006.05. 03:01
ras3sarm​v7l1 x 11,30084012.08. 02:57
ras4aarch​648 x 12,40038412.08. 02:57
ras4saarch​648 x 12,40038429.09. 03:02
ras5arm​v7l2 x 11,0002412.08. 02:58
ras5sarm​v7l2 x 11,0002412.08. 02:58
ras6aarch​648 x 12,0003,20012.08. 02:59
ras6sarm​v7l1 x 11,0001,98712.08. 02:59
ras7ppc1 x 13966512.08. 03:00
ras8x86_​644 x 11,60014,40012.08. 03:01
ras8sx86_​644 x 11,60012,74812.08. 03:01
rbs0i6862 x 22,50017,60012.08. 03:02
rbs3arm​v7l4 x 19962412.08. 03:02
rbs3sarm​v7l4 x 11,40035612.08. 03:03
rbs4x86_​644 x 11,2009,60012.08. 03:03
rbs4sx86_​644 x 11,60012,74812.08. 03:04
rbs5i6864 x 2052,36512.08. 03:05
rbs5saarch​644 x 11,6006412.08. 03:05
rbs6x86_​644 x 11,91515,32412.08. 03:06
rbs6sx86_​642 x 11,3335,33229.08. 03:00
rbs7arm​v7l4 x 19961212.08. 03:06
rbs7sarm​v7l4 x 19962412.08. 03:08
rbs8arm​v7l2 x 16662,65012.08. 03:09
rbs8sx86_​644 x 22,40038,70412.08. 03:10
rcs0x86_​648 x 22,40076,59212.08. 03:11
rcs1x86_​646 x 23,46783,37712.08. 03:12
rcs2x86_​642 x 12,80011,23212.08. 03:13
rcs3i6862 x 11,4005,58612.08. 03:13
rcs3sx86_​644 x 13,30026,39612.08. 03:14
rcs4x86_​642 x 11,1004,37612.08. 03:15
rcs5x86_​642 x 12,80011,19812.08. 03:16
rcs5sx86_​642 x 12,80011,19812.08. 03:17
rcs6x86_​644 x 23,50063,99212.08. 03:18
rcs7x86_​642 x 21,80014,40012.08. 03:19
rcs7sx86_​644 x 11,50011,98012.08. 03:20
rcs8x86_​6416 x 23,700217,18412.08. 03:23
rcs8sx86_​644 x 23,30052,80012.08. 03:24
rds0x86_​644 x 21,80031,99212.08. 03:25
rds1x86_​644 x 11,60012,74812.08. 03:26
rds2x86_​644 x 11,60012,74812.08. 03:26
rds3x86_​644 x 11,60012,74812.08. 03:27
rds4x86_​644 x 11,60012,74812.08. 03:27
rds5x86_​644 x 11,60012,74812.08. 03:28
rds6x86_​644 x 11,60012,74812.08. 03:28
rds7x86_​644 x 11,60012,74812.08. 03:29
rds8x86_​644 x 11,60012,74812.08. 03:29
res0x86_​644 x 23,40054,39212.08. 03:30
res1x86_​644 x 11,60014,40012.08. 03:31
res1sx86_​644 x 11,60014,40012.08. 03:31
res2x86_​644 x 11,60014,40012.08. 03:32
res3x86_​644 x 12,00015,97212.08. 03:32
res3saarch​640 x 1 x 11,0001,60012.08. 03:33
res4x86_​644 x 11,90015,05212.08. 03:34
res4sx86_​644 x 11,90015,05212.08. 03:34
res5x86_​642 x 22,20019,20012.08. 03:35
res5sx86_​642 x 22,20019,20012.08. 03:35
res6x86_​644 x 11,1008,75212.08. 03:36
res6saarch​644 x 101,60012.08. 03:37
res7arm​v7l0 x 1 x 11,0001211.08. 15:38
res7sarm​v7l0 x 1 x 11,0001212.08. 03:38
res8x86_​644 x 11,90015,05212.08. 03:38
res8sx86_​644 x 11,90015,05212.08. 03:39
rfs0x86_​6416 x 22,000128,00012.08. 03:40
rfs1aarch​644 x 11,50043212.08. 03:40
rfs1saarch​644 x 11,50043212.08. 03:40
rfs2x86_​644 x 13,00024,00012.08. 03:41
rfs2sx86_​642 x 13,00011,99812.08. 03:41
rfs3x86_​644 x 11,60012,74812.08. 03:41
rfs3sx86_​644 x 11,60012,74812.08. 03:42
rfs4aarch​641 x 11,4001,60012.08. 03:43
rfs4sarm​v7l1 x 180080012.08. 03:44
rfs5aarch​644 x 11,2006412.08. 03:45
rfs5saarch​644 x 11,2006412.08. 03:46
rfs6arm​v7l1 x 16671,33212.08. 03:46
rfs6sarm​v7l1 x 16671,33212.08. 03:47
rfs7x86_​644 x 22,60041,60012.08. 03:47
rfs7sx86_​644 x 17006,44812.08. 03:48
rfs8arm​v7l1 x 11,00012012.08. 03:49
 

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