You are here: Home / Projects / OSADL QA Farm Real-time / 
2024-06-15 - 21:45

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00015.06. 13:10
r0s1x86_​644 x 22,30055,99215.06. 13:11
r0s1sx86_​644 x 23,30052,67215.06. 13:13
r0s2x86_​644 x 23,50055,86415.06. 13:15
r0s2sx86_​6410 x 13,70073,99015.06. 13:16
r0s3x86_​648 x 23,600115,20015.06. 13:18
r0s3sx86_​644 x 23,60067,20015.06. 13:24
r0s4x86_​648 x 23,600115,20015.06. 13:26
r0s4sx86_​648 x 23,600115,20015.06. 13:28
r0s5x86_​648 x 23,500115,20015.06. 13:30
r0s5sx86_​648 x 23,600115,20015.06. 13:32
r0s6x86_​648 x 23,600115,20015.06. 13:35
r0s6sx86_​6410 x 23,700147,98015.06. 13:36
r0s7x86_​648 x 23,600115,20015.06. 13:41
r0s7sx86_​642 x 23,70029,52815.06. 13:46
r0s8x86_​648 x 23,600115,20015.06. 13:48
r0s8sx86_​646 x 23,47083,38815.06. 13:50
r1s0x86_​644 x 13,10024,80015.06. 13:52
r1s1x86_​642 x 22,60021,69615.06. 13:54
r1s2x86_​644 x 12,30028,00015.06. 13:56
r1s2sx86_​644 x 12,30028,00015.06. 13:58
r1s3x86_​644 x 12,80022,42415.06. 14:00
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004815.06. 14:01
r1s4sarm​v7l2 x 14004815.06. 14:03
r1s5aarch​644 x 11,20079615.06. 14:04
r1s6x86_​642 x 22,13017,06415.06. 14:05
r1s6sx86_​642 x 21,66713,33215.06. 14:07
r1s7arm​v6l1 x 11,66753015.06. 14:09
r1s8i6861 x 21,6006,39815.06. 14:10
r1s8sx86_​644 x 11,90015,19615.06. 14:11
r2s0x86_​644 x 13,10024,80015.06. 14:12
r2s1arm​v5tejl1 x 120019915.06. 14:14
r2s2arm​v7l1 x 172049915.06. 14:15
r2s3arm​v7l0 x 1 x 162462415.06. 14:16
r2s3sarm​v7l0 x 1 x 16001,20015.06. 14:17
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966627.03. 13:43
r2s6i6861 x 11,5002,99915.06. 14:19
r2s6saarch​644 x 11,3506415.06. 14:20
r2s7aarch​644 x 12,40043215.06. 14:21
r2s7saarch​644 x 11,50043215.06. 14:24
r2s8ppc1 x 14006615.06. 14:26
r3s0i6864 x 23,50055,99215.06. 14:27
r3s1i6864 x 12,40019,12715.06. 14:30
r3s2riscv641 x 11,00028415.06. 14:31
r3s2sriscv644 x 1028415.06. 14:32
r3s3x86_​646 x 23,33379,99215.06. 14:33
r3s4aarch​646 x 11,3009615.06. 14:35
r3s5i5861 x 113326504.06. 14:45
r3s5sppc2 x 11,20040015.06. 14:42
r3s6x86_​641 x 11,6603,33315.06. 02:39
r3s6sx86_​642 x 22,66721,33215.06. 14:43
r3s7i6861 x 15331,06615.06. 14:45
r3s8i6866 x 13,20038,52615.06. 14:46
r4s0x86_​642 x 22,30018,39615.06. 14:48
r4s1arm​v7l4 x 11,5001,08015.06. 14:50
r4s1sarm​v7l4 x 11,5001,08015.06. 14:52
r4s2arm​v7l1 x 180079615.06. 14:56
r4s2sarm​v7l1 x 180053015.06. 14:58
r4s3i5861 x 150099615.06. 15:02
r4s3si6861 x 11,4662,93215.06. 15:04
r4s4ppc4 x 11,20049815.06. 03:02
r4s5arm​v7l1 x 1500015.06. 15:10
r4s5saarch​644 x 11,60020015.06. 15:11
r4s6x86_​644 x 23,40054,25615.06. 15:12
r4s6sarm​v7l0 x 1 x 11,0006615.06. 15:16
r4s7i6864 x 11,83314,66415.06. 15:19
r4s7sx86_​642 x 11,8337,33215.06. 15:20
r4s8arm​v7l1 x 140039815.06. 15:22
r4s8sarm​v7l1 x 140039815.06. 15:23
r5s0x86_​642 x 22,20017,58115.06. 15:24
r5s1x86_​646 x 13,33340,09215.06. 15:25
r5s2x86_​644 x 12,70021,69915.06. 15:27
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87215.06. 15:30
r5s3sx86_​644 x 11,60012,74815.06. 15:31
r5s4x86_​642 x 22,53020,26415.06. 15:34
r5s4sx86_​642 x 22,53020,26415.06. 15:35
r5s5arm​v7l1 x 160059715.06. 15:39
r5s5sarm​v7l1 x 160060015.06. 15:42
r5s6ppc1 x 153313315.06. 15:49
r5s7arm​v7l1 x 15286415.06. 15:50
r5s7sarm​v7l1 x 15284815.06. 03:53
r6s0x86_​642 x 10 x 21,700136,18015.06. 15:53
r6s1x86_​642 x 12,0007,97815.06. 15:55
r6s2x86_​642 x 11,6679,57815.06. 15:58
r6s3x86_​644 x 22,20035,12015.06. 16:00
r6s4x86_​642 x 11,1004,37615.06. 16:02
r6s5i6861 x 11,5002,99215.06. 16:05
r6s6i6861 x 11,6003,19115.06. 16:07
r6s7i6862 x 12,3009,17611.01. 02:44
r6s8x86_​642 x 22,30018,35615.06. 16:09
r7s0x86_​642 x 22,30018,40015.06. 16:11
r7s1x86_​644 x 11,60012,84015.06. 16:12
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r7s3arm​v6l1 x 1700515.06. 16:14
r7s3sarm​v7l4 x 11,40035615.06. 16:17
r7s4arm​v7l1 x 153634815.06. 16:20
r7s4sarm​v7l4 x 11,5001,08015.06. 16:23
r7s5i6861 x 11,3002,59315.06. 16:25
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76715.06. 16:26
r7s7sx86_​642 x 22,30018,39615.06. 16:28
r7s8arm​v7l1 x 11,00099515.06. 16:31
r7s8sarm​v7l1 x 11,00079615.06. 16:33
r8s0x86_​642 x 22,30018,40015.06. 16:34
r8s1i5861 x 135070115.06. 16:36
r8s2x86_​642 x 22,10016,76015.06. 16:38
r8s2sx86_​642 x 22,10016,76015.06. 16:40
r8s3x86_​644 x 12,66721,28015.06. 16:42
r8s4x86_​644 x 21,60028,80015.06. 16:44
r8s4sx86_​644 x 21,60028,80015.06. 16:46
r8s5i6864 x 23,40054,40015.06. 16:48
r8s6arm​v7l1 x 150049815.06. 16:50
r8s7x86_​642 x 12,70010,77615.06. 16:51
r8s7sx86_​642 x 13,30013,19815.06. 16:53
r8s8x86_​642 x 11,3005,14415.06. 05:00
r9s0x86_​642 x 22,30018,39615.06. 16:55
r9s1x86_​642 x 12,0003,99215.06. 16:57
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74815.06. 16:59
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74815.06. 17:01
r9s3sx86_​644 x 13,00024,00015.06. 17:03
r9s4i6861 x 21,0003,99015.06. 17:05
r9s4sx86_​642 x 11,3335,34715.06. 17:11
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,50013,99815.06. 17:13
r9s6x86_​642 x 23,00023,94415.06. 17:15
r9s7arm​v7l2 x 11,000015.06. 17:17
r9s8sarm​v7l1 x 180079615.06. 17:18
ras0x86_​642 x 22,30018,41615.06. 17:19
ras1i6861 x 11,4002,79915.06. 17:21
ras2x86_​642 x 11,0674,26615.06. 17:23
ras3aarch​648 x 12,0004,00015.06. 17:24
ras3sarm​v7l1 x 11,30084015.06. 17:25
ras4arm​v7l1 x 150039815.06. 17:25
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002415.06. 17:26
ras5sarm​v7l2 x 11,0002415.06. 17:27
ras6aarch​648 x 12,0003,20020.05. 17:01
ras6sarm​v7l1 x 11,0001,98715.06. 17:29
ras7ppc1 x 13966515.06. 17:30
ras8x86_​644 x 11,60014,40015.06. 17:31
ras8sx86_​644 x 11,60012,74815.06. 17:34
rbs0i6862 x 22,50017,60015.06. 17:35
rbs1x86_​644 x 12,00015,97215.06. 17:37
rbs2x86_​644 x 12,00015,97215.06. 17:38
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962815.06. 17:40
rbs3sarm​v7l4 x 11,40035615.06. 17:41
rbs4x86_​644 x 11,2009,60015.06. 17:45
rbs4sx86_​644 x 11,60012,74815.06. 17:46
rbs5i6864 x 2049,53915.06. 17:47
rbs5saarch​644 x 11,6006415.06. 17:48
rbs6x86_​644 x 11,91515,32415.06. 17:50
rbs6sx86_​642 x 11,3335,33215.06. 17:52
rbs7arm​v7l4 x 19962815.06. 17:55
rbs7sarm​v7l4 x 19962415.06. 17:57
rbs8arm​v7l2 x 16662,65015.06. 18:01
rbs8sx86_​644 x 22,40038,70415.06. 18:03
rcs0x86_​648 x 22,40076,60015.06. 18:08
rcs1x86_​646 x 23,46783,37615.06. 18:11
rcs2x86_​642 x 12,80011,23215.06. 06:16
rcs3i6862 x 11,4005,58815.06. 18:13
rcs3sx86_​644 x 23,30052,69615.06. 18:15
rcs4x86_​642 x 11,1004,37615.06. 18:19
rcs4sx86_​644 x 11,1008,75215.06. 18:21
rcs5x86_​642 x 12,80011,19815.06. 18:22
rcs5sx86_​642 x 12,80011,19815.06. 18:25
rcs6x86_​644 x 23,50063,99215.06. 18:27
rcs7x86_​642 x 21,80014,39615.06. 18:29
rcs7sx86_​644 x 11,50011,98015.06. 18:31
rcs8x86_​6416 x 23,700217,15215.06. 18:38
rcs8sx86_​644 x 23,30052,79215.06. 18:40
rds0x86_​644 x 21,80031,99215.06. 18:41
rds1x86_​644 x 11,91015,32415.06. 18:43
rds2x86_​644 x 11,91015,32415.06. 18:45
rds3x86_​644 x 11,91015,32415.06. 18:46
rds4x86_​644 x 11,91015,32415.06. 18:48
rds5x86_​644 x 11,60012,74815.06. 06:55
rds6x86_​644 x 11,60012,74815.06. 18:50
rds7x86_​644 x 11,60012,74815.06. 18:52
rds8x86_​644 x 11,60012,74815.06. 18:53
res0x86_​644 x 21,80031,99215.06. 18:54
res1x86_​644 x 11,60014,40015.06. 18:56
res1sx86_​644 x 11,60014,40015.06. 18:57
res2x86_​644 x 11,60014,40015.06. 18:58
res3x86_​644 x 12,00015,97215.06. 19:00
res3saarch​640 x 1 x 11,0001,60015.06. 19:01
res4x86_​644 x 11,90015,05215.06. 19:03
res4sx86_​644 x 11,90015,05215.06. 19:05
res5x86_​642 x 22,20019,20015.06. 19:06
res5sx86_​642 x 22,20019,20015.06. 19:08
res6x86_​644 x 11,1008,75215.06. 19:10
res6saarch​644 x 101,60015.06. 19:11
res7arm​v7l0 x 1 x 11,0001215.06. 19:13
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
res8x86_​644 x 11,90015,05215.06. 19:15
res8sx86_​644 x 11,90015,05215.06. 19:17
rfs0x86_​6416 x 22,000128,00015.06. 19:19
rfs1aarch​644 x 11,50043215.06. 19:20
rfs2aarch​644 x 11,50043215.06. 19:21
rfs4arm​v7l1 x 180080015.06. 19:22
rfs4sarm​v7l1 x 180080015.06. 19:30
rfs6arm​v7l1 x 16671,33215.06. 19:37
rfs6sarm​v7l1 x 16671,33215.06. 19:38
 

Valid XHTML 1.0 Transitional