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2024-02-23 - 07:26

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50039,99223.02. 01:10
r0s1x86_​644 x 22,30055,99223.02. 01:11
r0s1sx86_​644 x 23,30052,67223.02. 01:12
r0s2x86_​644 x 23,50055,86423.02. 01:12
r0s2sx86_​6410 x 13,70073,99023.02. 01:13
r0s3x86_​648 x 23,600115,20023.02. 01:14
r0s3sx86_​644 x 23,60067,20023.02. 01:17
r0s4x86_​648 x 23,600115,20023.02. 01:18
r0s4sx86_​648 x 23,600115,20023.02. 01:19
r0s5x86_​648 x 23,500115,20023.02. 01:20
r0s5sx86_​648 x 23,600115,20023.02. 01:21
r0s6x86_​648 x 23,600115,20023.02. 01:24
r0s6sx86_​6410 x 23,700147,98023.02. 01:26
r0s7x86_​648 x 23,600115,20023.02. 01:27
r0s7sx86_​642 x 23,70029,52823.02. 01:29
r0s8x86_​648 x 23,600115,20023.02. 01:30
r0s8sx86_​646 x 23,47083,38823.02. 01:34
r1s0x86_​644 x 13,10024,79623.02. 01:35
r1s1x86_​642 x 22,60021,69623.02. 01:36
r1s2x86_​644 x 12,30028,00023.02. 01:37
r1s2sx86_​644 x 12,30028,00023.02. 01:38
r1s3x86_​644 x 12,80022,42423.02. 01:39
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004823.02. 01:40
r1s4sarm​v7l2 x 14004823.02. 01:41
r1s5aarch​644 x 11,20079623.02. 01:41
r1s6x86_​642 x 22,13017,06423.02. 01:42
r1s6sx86_​642 x 21,66713,33223.02. 01:43
r1s7arm​v6l1 x 11,66753023.02. 01:44
r1s8i6861 x 21,6006,39823.02. 01:45
r1s8sx86_​644 x 11,90015,19623.02. 01:46
r2s0x86_​644 x 13,10024,79623.02. 01:46
r2s1arm​v5tejl1 x 120019923.02. 01:47
r2s2arm​v7l1 x 172049923.02. 01:47
r2s3arm​v7l0 x 1 x 162462423.02. 01:48
r2s3sarm​v7l0 x 1 x 16001,20013.02. 01:50
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966621.02. 13:54
r2s6i6861 x 11,5002,99923.02. 01:50
r2s6saarch​644 x 11,3506423.02. 01:51
r2s7aarch​644 x 12,40043223.02. 01:51
r2s7saarch​644 x 11,50043223.02. 01:53
r2s8ppc1 x 14006623.02. 01:54
r3s0i6864 x 23,50055,99223.02. 01:55
r3s1i6864 x 12,40019,12723.02. 01:56
r3s2riscv641 x 11,00028423.02. 01:57
r3s2sriscv644 x 1028422.02. 13:54
r3s3x86_​646 x 23,33379,99223.02. 01:59
r3s4x86_​641 x 21,4005,60010.01. 01:28
r3s5i5861 x 113326523.02. 02:00
r3s5sppc2 x 11,20040023.02. 02:02
r3s6x86_​641 x 11,6603,33323.02. 02:03
r3s6sx86_​642 x 22,66721,33223.02. 02:04
r3s7i6861 x 15331,06622.02. 14:00
r3s8i6866 x 13,20038,52623.02. 02:05
r4s0x86_​642 x 22,30018,39623.02. 02:06
r4s1arm​v7l4 x 11,50072023.02. 02:07
r4s1sarm​v7l4 x 11,50079223.02. 02:09
r4s2arm​v7l1 x 180079623.02. 02:10
r4s2sarm​v7l1 x 180053023.02. 02:12
r4s3i5861 x 150099623.02. 02:15
r4s3si6861 x 11,4662,93223.02. 02:16
r4s4ppc4 x 11,20049823.02. 02:17
r4s5arm​v7l1 x 1500023.02. 02:22
r4s5saarch​644 x 11,60020022.02. 14:15
r4s6x86_​644 x 23,40054,25623.02. 02:23
r4s6sarm​v7l0 x 1 x 11,0006623.02. 02:24
r4s7i6864 x 11,83314,66423.02. 02:25
r4s7sx86_​642 x 11,8337,33223.02. 02:26
r4s8arm​v7l1 x 140039823.02. 02:27
r4s8sarm​v7l1 x 140039820.02. 14:30
r5s0x86_​642 x 22,20017,58223.02. 02:28
r5s1x86_​646 x 13,33340,09223.02. 02:28
r5s2x86_​644 x 12,70021,69923.02. 02:29
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87223.02. 02:31
r5s3sx86_​644 x 11,60012,74823.02. 02:32
r5s4x86_​642 x 22,53020,26423.02. 02:33
r5s4sx86_​642 x 22,53020,26423.02. 02:34
r5s5arm​v7l1 x 160059723.02. 02:37
r5s5sarm​v7l1 x 160060023.02. 02:39
r5s6ppc1 x 153313323.02. 02:42
r5s7arm​v7l1 x 15286423.02. 02:43
r5s7sarm​v7l1 x 15286423.02. 02:45
r6s0x86_​642 x 10 x 21,700136,14023.02. 02:46
r6s1x86_​642 x 12,0007,97823.02. 02:47
r6s2x86_​642 x 11,6679,57823.02. 02:48
r6s3x86_​644 x 22,20035,12023.02. 02:48
r6s4x86_​642 x 11,1004,37623.02. 02:49
r6s5i6861 x 11,5001,12222.02. 02:56
r6s6i6861 x 11,6003,19123.02. 02:51
r6s7i6862 x 12,3009,17611.01. 02:44
r6s8x86_​642 x 22,30018,35623.02. 02:52
r7s0x86_​642 x 22,30018,40023.02. 02:53
r7s1x86_​644 x 11,60012,84023.02. 02:53
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r7s3arm​v6l1 x 1700523.02. 02:54
r7s3sarm​v7l4 x 11,40035623.02. 02:57
r7s4arm​v7l1 x 153634823.02. 02:58
r7s4sarm​v7l4 x 11,5001,08023.02. 02:59
r7s5i6861 x 11,3002,59323.02. 03:00
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76723.02. 03:01
r7s7sx86_​642 x 22,30018,39623.02. 03:01
r7s8arm​v7l1 x 11,00099523.02. 03:02
r7s8sarm​v7l1 x 11,00079623.02. 03:03
r8s0x86_​642 x 22,30018,40023.02. 03:04
r8s1i5861 x 130060122.02. 14:52
r8s2x86_​642 x 22,10016,76023.02. 03:05
r8s2sx86_​642 x 22,10016,76023.02. 03:06
r8s3x86_​644 x 12,66721,28023.02. 03:06
r8s4x86_​644 x 21,60028,80023.02. 03:07
r8s4sx86_​644 x 21,60028,80023.02. 03:08
r8s5i6864 x 23,40054,39223.02. 03:09
r8s6arm​v7l1 x 150049823.02. 03:10
r8s7x86_​642 x 12,70010,77623.02. 03:10
r8s7sx86_​642 x 13,30013,19823.02. 03:11
r8s8x86_​642 x 11,3005,14423.02. 03:12
r9s0x86_​642 x 22,30018,40023.02. 03:13
r9s1x86_​642 x 12,0003,99223.02. 03:14
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74823.02. 03:15
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74823.02. 03:16
r9s3sx86_​644 x 13,00024,00023.02. 03:17
r9s4i6861 x 21,0003,98823.02. 03:17
r9s4sx86_​642 x 11,3335,34723.02. 03:18
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,50013,99823.02. 03:19
r9s6x86_​642 x 23,00023,94423.02. 03:20
r9s7arm​v7l2 x 11,000023.02. 03:22
r9s8sarm​v7l1 x 180079623.02. 03:23
ras0x86_​642 x 22,30018,41623.02. 03:24
ras1i6861 x 11,4002,79923.02. 03:25
ras2x86_​642 x 11,0674,26623.02. 03:25
ras3aarch​648 x 12,0004,00023.02. 03:26
ras3sarm​v7l1 x 11,30084023.02. 03:26
ras4arm​v7l1 x 150039823.02. 03:27
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002423.02. 03:27
ras5sarm​v7l2 x 11,0002423.02. 03:28
ras6arm​v7l1 x 11,0001,98723.02. 03:28
ras6sarm​v7l1 x 11,0001,98723.02. 03:29
ras7ppc1 x 13966523.02. 03:30
ras8x86_​644 x 11,60014,40023.02. 03:31
ras8sx86_​644 x 11,60012,74823.02. 03:32
rbs0i6862 x 22,50017,60023.02. 03:33
rbs1x86_​644 x 13,10028,80023.02. 03:33
rbs2x86_​644 x 23,20051,20023.02. 03:34
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962423.02. 03:35
rbs3sarm​v7l4 x 11,40035623.02. 03:35
rbs4x86_​644 x 11,2009,60023.02. 03:37
rbs4sx86_​644 x 11,60012,74823.02. 03:37
rbs5i6864 x 2049,53923.02. 03:38
rbs5saarch​644 x 11,6006423.02. 03:39
rbs6x86_​644 x 11,91515,32423.02. 03:39
rbs6sx86_​642 x 11,3335,33223.02. 03:41
rbs7arm​v7l4 x 19961223.02. 03:42
rbs7sarm​v7l4 x 19962423.02. 03:43
rbs8arm​v7l2 x 16662,65023.02. 03:44
rbs8sx86_​644 x 22,40038,70423.02. 03:45
rcs0x86_​648 x 22,40076,60023.02. 03:47
rcs1x86_​646 x 23,46783,37623.02. 03:49
rcs2x86_​642 x 12,80011,23223.02. 03:50
rcs3i6862 x 11,4005,58623.02. 03:51
rcs3sx86_​644 x 23,30052,69623.02. 03:53
rcs4x86_​642 x 11,1004,37623.02. 03:55
rcs4sx86_​644 x 11,1008,75223.02. 03:57
rcs5x86_​642 x 12,80011,19823.02. 03:58
rcs5sx86_​642 x 12,80011,19823.02. 04:02
rcs6x86_​644 x 23,50063,99223.02. 04:03
rcs7x86_​642 x 21,80014,39623.02. 04:04
rcs7sx86_​644 x 11,50011,98023.02. 04:06
rcs8x86_​6416 x 23,700217,15223.02. 04:09
rcs8sx86_​644 x 23,30052,79223.02. 04:11
rds0x86_​644 x 21,80031,99223.02. 04:12
rds1x86_​644 x 11,91015,32423.02. 04:12
rds2x86_​644 x 11,91015,32423.02. 04:13
rds3x86_​644 x 11,91015,32423.02. 04:14
rds4x86_​644 x 11,91015,32423.02. 04:15
rds5x86_​644 x 11,60012,74823.02. 04:16
rds6x86_​644 x 11,60012,74823.02. 04:16
rds7x86_​644 x 11,60012,74823.02. 04:17
rds8x86_​644 x 11,60012,74823.02. 04:18
res0x86_​644 x 11,80015,99623.02. 04:19
res1x86_​644 x 11,60014,40023.02. 04:20
res1sx86_​644 x 11,60014,40023.02. 04:21
res2x86_​644 x 11,60014,40023.02. 04:21
res3x86_​644 x 12,00015,97223.02. 04:23
res3saarch​640 x 1 x 11,0001,60023.02. 04:24
res4x86_​644 x 11,90015,05223.02. 04:25
res4sx86_​644 x 11,90015,05223.02. 04:26
res5x86_​642 x 22,20019,20023.02. 04:27
res5sx86_​642 x 22,20019,20023.02. 04:29
res6x86_​644 x 11,1008,75223.02. 04:30
res6saarch​644 x 101,60023.02. 04:31
res7arm​v7l0 x 1 x 11,0001223.02. 04:32
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
res8x86_​644 x 11,90015,05223.02. 04:33
res8sx86_​644 x 11,90015,05223.02. 04:34
rfs1aarch​644 x 11,50043223.02. 04:35
rfs2aarch​644 x 11,50043223.02. 04:35
r9s8sarm​v7l1 x 180079608.02. 11:18
 

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