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2022-07-04 - 05:46

Dates and Events:

OSADL Articles:

2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available


2016-11-12 12:00

Raspberry Pi and real-time Linux

Let's have a look at the OSADL QA Farm data


2016-09-17 12:00

Preemption latency of real-time Linux systems

How to measure it – and how to fix it, if it's too high?



Real Time Linux Workshops

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17th Real Time Linux Workshop, October 21 to 22, 2015 at the Virtual Vehicle Research Center, Graz, Austria

Announcement - Call for participation (ASCII) - Hotels - Directions - Agenda - Paper Abstracts - Presentations - Registration - Abstract Submission - Exhibitors and Sponsors - Gallery

On the Design of the Jailhouse Partitioning Hypervisor

Jan Kiszka, Siemens AG, Corporate Technology
Valentine Sinitsyn, Ural Federal University

Integrating heterogeneous workloads on multi-core systems and isolating them form each other to enable hard real-time, safety and security scenarios is a recurring requirement. The Jailhouse partitioning hypervisor is designed to fulfill this requirement, augmenting the Linux ecosystem with a complete open source solution.

In this paper, we will look deeper into the Jailhouse design. The goal is to provide a profound insight into the hypervisor to enabled new contributors getting started more quickly, but also to support independent reviews of the design and its implementation.

We will explain the basic principles on which Jailhouse is built and according to which it shall evolve, such as simplicity, the separation of duties between core and supplementary tools or the exploitation of hardware-assisted virtualization. We will describe key features like the boot concept that used Linux as loader, the hypervisor configuration and its runtime management model, including the integrity-ensuring configuration lock-down. The hypervisor exposes two types of execution environments for its guests. Both will be presented, including the specific interfaces that are available for the guests.

Beyond that, we will dive deeper and present the execution model of the hypervisor, internal inter-processor signaling and locking inside the core. The hypervisor contains a simple but essential subsystem for managing memory pages and their mapping into the different address spaces. How this subsystem is designed and how it applied will be explained in particular. Furthermore, the architectural splits will be described that enable support of both AMD and Intel x86 systems as well as ARMv7 and, soon, ARMv8 platforms.

The paper will conclude with presenting a few experiments conducted so far on x86 systems to demonstrate the isolation properties of the hypervisor.