You are here: Home / RTLWS 1999-2017 / RTLWS Submitted Papers / 
2022-08-13 - 04:35

Real Time Linux Workshops

1999 - 2000 - 2001 - 2002 - 2003 - 2004 - 2005 - 2006 - 2007 - 2008 - 2009 - 2010 - 2011 - 2012 - 2013 - 2014 - 2015

13th Real-Time Linux Workshop from October 20 to 22 at the Faculty of Electrical Engineering, Czech Technical University in Prague

Announcement - Hotels - Directions - Agenda - Paper Abstracts - Presentations - Registration - Abstract Submission - Sponsoring - Gallery

High-speed Inter-Process Communication based on Shared Cache

Chenggang Qin, Graduate University of Chinese Academy of Sciences
Dong Yu, Shenyang institute of computing technology, Chinese Academy of Sciences
Wenjiang Wu, Shenyang institute of computing technology, Chinese Academy of Sciences

Because of the application of multicore processor being more and more extensive in the high-end real-time systems, the RTOS (real-time operating system) should be optimized to fulfill the special structure of the multicore processor. Among the vast majority of mainstream multi-core processors, many cores share one L2 Cache or L3 Cache. RTOS is required to manage the shared Cache effectively to avoid Cache thrashing and decrease the access conflicts. The Cache Thrashing and cache access conflicts would aggravate the unpredictability of the real-time system. The memory page is stored continuously in the shared Cache; and an overlapping bit-field exists between the linear address of Linux and the Cache set number. Therefore, each cache set is corresponding to certain specific physical page frames while RTOS can manage the shared Cache in terms of controlling the allocation of physical page frames. The shared memory is one of the basic patterns of inter-process communication. In many real-time systems, the shared memory space is small; however, it could be the whole work set of many real-time tasks. The concurrent tasks might require visiting this small memory space frequently as the accesses to the shared memory are far more than other memory spaces. For the multicore processor, the cache lines, which are mapped by the shared memory, could be flushed by other memory accesses; and the real-time tasks have to get these data from RAM when they access the shared memory again. The execution time of these tasks will be prolonged, and the predictability of the real-time system is decreased. According to the page-coloring technology, this paper separates the shared Cache into communication region and normal region. The communication region is only used to map the shared memory. The accesses to other memory space will not flush the cache lines of communication region. The normal region is used to map the memory space except the shared memory. The size of the communication region can be adjusted by adjusting the number of colors that allocated to communication region. Because of avoiding the access conflicts, the high-speed shared memory which based on the shared Cache is not only increasing the speed of inter-process communication, but also increasing the predictability of the real-time systems. Many inter-process communication models are based on the shared memory, such as FIFO, mailbox, We implemented the high-speed shared memory, high-speed FIFO, high-speed mailbox and other inter-process communication models based on shared Cache in Xenomai. Xenomai is an open source RTOS basing on Linux. The effectiveness of the high-speed communication model is approved through a large number of tests for real-time task sets.