Dates and Events:
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OSADL Articles:
2023-11-12 12:00
Open Source License Obligations Checklists even better nowImport the checklists to other tools, create context diffs and merged lists
2022-07-11 12:00
Call for participation in phase #4 of Open Source OPC UA open62541 support projectLetter of Intent fulfills wish list from recent survey
2022-01-13 12:00
Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completedAnother important milestone on the way to interoperable Open Source real-time Ethernet has been reached
2021-02-09 12:00
Open Source OPC UA PubSub over TSN project phase #3 launchedLetter of Intent with call for participation is now available |
A Latency Model of Linux 2.6 for Digital Signal Processing in Real Time
Sergio A. Rodríguez and Phillip M. S. Burt, Escola Politécnica, University of São Paulo, Brazil
This paper develops a new qualitative latency model of the Linux 2.6 OS for the Intel x86 architecture. The proposed model analyses aspects related to digital signal processing in real time. In this context, the study identifies all latency sources since the arrival of a signal sample (or block of samples) up to the execution of the first instruction related to processing that sample. The interrupt latency is divided into seven components, including hardware latency sources such as microprocessor operation and interrupt controller queue. The dispatch latency is divided into six components, adding new components such as interrupts stack latency and deferrable functions latency to the known sources such as scheduler latency and switch context latency. The paper also identifies further overhead sources such as memory allocation by demand paging. Finally, some of the new latency components are measured using an instrumented kernel. The measures are obtained with and without computational load for the purpose of analyzing its influence in the latency components.