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Porting RT-PREEMPT to loongson 2F

Zhangjin Wu, DSLab, SISE, Lanzhou University, Gansu, China
Nicholas Mc Guire, DSLab, SISE, Lanzhou University, Gansu, China

The 2nd generation of CPUs from Loongson is currently at the 2F release, with the 2G to be expected this year. This MIPS based single core cpu is a low-power, mid-range performance CPU primarily targeting desktop and net-books. Due to its low power-consumption, fanless operation and integration in form-factors suitable for industrial usage, we have been working on porting suitable RTOS to the loongson 2F, the primary targets for this effort have been the XtratuM hypervisor and mainline RT-PREEMPT. We will not further cover XtratuM (which is in an early development stage) but rather focus on the mainline RT-PREEMPT porting to the 2F, to enhance its usability in industrial applications requiring reliable real-time services.

In this article we will briefly outline the motivation of selecting RT-PREEMPT and then focus on the technical issues of porting RT-PREEMPT to a new architecture, describing the specifics of the loongson 2F. Further we cover the non-technical issues of how to integrate such work into mainstream development, and finally present some preliminary benchmark results based on community tools (notably cyclictest).