Various Zephyr reference systems undergo repeated load phases and latency measurements in the OSADL QA farm using the Zephyr zyclictest module. The two measurement phases, which determine the system’s worst-case latency, have a fixed duration of five hours and 33 minutes. They begin at 7:10 a.m. and 7:10 p.m. The number of cycles required depends on the measurement interval. To keep the fixed duration of five hours and 33 minutes with an interval of 200 µs, 100,000,000 cycles are needed, with 400 µs, 50,000,000 cycles are needed. Although the "zyclictest" program generates a relatively high interrupt load, it does not cause any other significant loads that could affect the system. Therefore, an additional load is generated in different ways depending on the board.

On the Olimex STM32F407 board (Zephyr 4.3.0), an additional background load is generated by continuously reading a sensor.

On the Raspberry Pi Pico board (Zephyr 4.3.99), the additional load is generated by a computational load on the CPU.

The results of the latest test run and the observed worst-case latencies of the last seven days are listed below. More information on building Zephyr can be found here. The Zephyr configuration (prj.conf) used for each board is specified as well.

• CPU Data: 1 core Arm Cortex-M4 @ 168 MHz, Zephyr was built with this prj.conf

• CPU Data: Dual-core Arm Cortex-M0+ @ 133 MHz, Zephyr was built with this prj.conf