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2024-04-17 - 00:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Tue Apr 16, 2024 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
168923225621,30sleep70-21swapper/707:08:337
168909423828,7sleep50-21swapper/507:06:395
168910523625,7sleep60-21swapper/607:06:486
168904723222,7sleep40-21swapper/407:05:574
1689610993129,2cyclictest2008904-21kworker/u16:0+events_unbound10:52:386
168961499274,14cyclictest0-21swapper/710:22:597
1689610992411,5cyclictest0-21swapper/610:57:486
168961499230,22cyclictest0-21swapper/707:47:357
1689610992319,3cyclictest2264932-21kworker/u16:2+flush-8:012:09:196
1689604992320,2cyclictest1901459-21kworker/u16:3+flush-8:009:09:204
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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