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2025-12-01 - 21:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the highest latencies:
System rack6slot6 (updated Mon Dec 01, 2025 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
203099910676153455,53306cyclictest0-21swapper08:26:360
203099910674053409,53265cyclictest0-21swapper08:14:220
203099910669753486,53211cyclictest0-21swapper09:16:000
203099910666153468,53193cyclictest0-21swapper12:08:300
203099910660153480,53121cyclictest0-21swapper11:02:310
203099910659253454,53071cyclictest0-21swapper10:14:070
203099910657953466,53113cyclictest20308-21cyclictest10:40:140
203099910657953447,53041cyclictest0-21swapper12:15:520
203099910653653442,53030cyclictest3950irq/9-acpi11:39:510
203099910653453436,53098cyclictest0-21swapper07:13:450
203099910651453456,53058cyclictest0-21swapper11:47:240
203099910649853466,53032cyclictest0-21swapper10:46:260
203099910649053421,53069cyclictest0-21swapper08:19:340
203099910648253474,52944cyclictest3950irq/9-acpi12:33:070
203099910643753396,53041cyclictest0-21swapper07:21:570
203099910642353436,52987cyclictest0-21swapper10:29:510
203099910641453435,52979cyclictest0-21swapper11:31:390
203099910640953420,52989cyclictest0-21swapper09:57:420
203099910639253477,52915cyclictest0-21swapper08:37:390
203099910631153475,52744cyclictest0-21swapper09:01:060
203099910626353407,52856cyclictest0-21swapper08:42:200
203099910625253384,52803cyclictest0-21swapper12:22:240
203099910624053441,52799cyclictest0-21swapper07:15:050
203099910622153477,52744cyclictest0-21swapper08:24:350
203099910621453469,52745cyclictest0-21swapper08:50:530
203099910619853421,52777cyclictest0-21swapper08:02:390
203099910617853456,52722cyclictest0-21swapper07:37:520
203099910617153455,52716cyclictest0-21swapper07:53:560
203099910615053443,52707cyclictest0-21swapper07:58:480
203099910613653431,52705cyclictest0-21swapper10:54:380
203099910613553433,52702cyclictest0-21swapper08:33:280
203099910612853435,52693cyclictest0-21swapper12:10:300
203099910586353345,52518cyclictest0-21swapper12:02:580
203099910533253096,52227cyclictest0-21swapper08:06:300
203099910500452913,52089cyclictest0-21swapper11:58:470
20309995377553410,269cyclictest18118-21ssh09:27:030
20309995371723,0cyclictest0-21swapper12:38:280
20309995364853379,207cyclictest133750irq/9-eth010:30:210
20309995354824,53429cyclictest0-21swapper09:31:350
20309995350224,0cyclictest0-21swapper09:24:220
20309995348725,53462cyclictest0-21swapper09:54:010
20309995347126,53445cyclictest0-21swapper07:45:040
20309995344924,53425cyclictest0-21swapper09:43:180
20309995319824,389cyclictest0-21swapper09:39:270
20309995317653105,68cyclictest4897-21ssh10:39:140
2030999531248,53114cyclictest0-21swapper10:17:080
20309995306725,53042cyclictest0-21swapper08:49:320
20309995303625,53011cyclictest0-21swapper07:42:230
20309995303152998,28cyclictest0-21swapper11:53:560
203099923971084,1188cyclictest18187-21ssh11:42:120
203099922871066,1167cyclictest3950irq/9-acpi11:10:430
203099922161026,1097cyclictest3950irq/9-acpi09:49:400
203099920441052,897cyclictest0-21swapper10:58:300
203099919871012,939cyclictest5157-21diskmemload10:24:100
20309991927928,965cyclictest0-21swapper10:04:240
203099919241066,858cyclictest0-21swapper10:06:040
20309991922932,970cyclictest0-21swapper09:06:170
203099918351094,648cyclictest0-21swapper11:19:050
20309991826923,867cyclictest5157-21diskmemload09:11:390
203099917981057,675cyclictest140749irq/7-s-b4311:24:570
20309991791923,834cyclictest0-21swapper08:58:450
203099917761062,650cyclictest9-21ksoftirqd/007:26:280
203099917461092,654cyclictest0-21swapper11:07:020
203099915161042,474cyclictest0-21swapper07:34:210
203099915061036,470cyclictest0-21swapper12:25:350
203099915011088,349cyclictest3950irq/9-acpi11:27:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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