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2026-01-14 - 02:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack8slot4.osadl.org (updated Wed Jan 14, 2026 00:44:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
838432241186,18sleep70-21swapper/719:07:237
859422226194,21sleep60-21swapper/619:09:396
836982219166,42sleep10-21swapper/119:05:161
859492215185,19sleep40-21swapper/419:09:464
859082215185,20sleep00-21swapper/019:09:090
837092214186,18sleep30-21swapper/319:05:273
838862213186,17sleep20-21swapper/219:08:002
838322213184,19sleep50-21swapper/519:07:145
1774822460,0sleep30-21swapper/321:58:163
8620299320,31cyclictest369-21systemd-journal19:55:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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