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2026-02-14 - 15:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Sat Feb 14, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1068911120,4ptp4l401ktimersoftd/307:40:513
106891740,1ptp4l401ktimersoftd/311:45:383
106891740,11ptp4l401ktimersoftd/308:10:523
106891700,1ptp4l401ktimersoftd/312:36:353
147042670,5sleep214708-21ptp4l-jitter12:15:552
106891670,10ptp4l401ktimersoftd/311:36:553
265972620,5sleep0140899cyclictest11:55:450
31442600,2sleep10-21swapper/110:58:131
89182560,2sleep10-21swapper/109:58:471
45972560,3sleep125-21ksoftirqd/112:40:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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