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2026-01-19 - 01:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Sun Jan 18, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
106891990,3ptp4l401ktimersoftd/307:27:063
106891710,1ptp4l401ktimersoftd/309:43:033
106891650,1ptp4l401ktimersoftd/308:21:063
167972634,10sleep20-21swapper/207:26:262
106891620,7ptp4l401ktimersoftd/311:44:393
18682600,3sleep00-21swapper/012:43:410
106891590,1ptp4l401ktimersoftd/311:07:553
215502580,4sleep11722699cyclictest11:25:341
106891580,2ptp4l401ktimersoftd/312:00:113
47562570,3sleep11722699cyclictest10:35:391
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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