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2026-02-26 - 01:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Wed Feb 25, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2954921630,5sleep31861199cyclictest12:54:453
2954921630,5sleep31861199cyclictest12:54:453
136121580,3sleep11859699cyclictest11:19:121
1068911040,4ptp4l401ktimersoftd/307:47:053
276112720,2sleep30-21swapper/308:06:513
30042700,2sleep30-21swapper/312:26:593
51292660,3sleep31861199cyclictest09:36:483
183492654,10sleep00-21swapper/007:49:460
1861199640,3cyclictest7179-21ssh13:05:223
183202634,10sleep10-21swapper/107:49:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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