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2026-01-30 - 04:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Fri Jan 30, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3198721770,3sleep32313199cyclictest22:25:273
1760921570,3sleep02310999cyclictest21:37:140
1068911460,8ptp4l13014-21kworker/3:219:34:093
106891740,1ptp4l401ktimersoftd/300:00:533
106891720,1ptp4l401ktimersoftd/321:57:003
106891700,1ptp4l401ktimersoftd/300:29:003
17152670,2sleep30-21swapper/300:06:563
227252654,10sleep00-21swapper/019:33:120
23109996452,6cyclictest9-21ksoftirqd/023:47:080
85222630,2sleep30-21swapper/300:12:233
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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