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2026-02-21 - 07:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Sat Feb 21, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
76021700,1sleep20-21swapper/221:58:212
1367021660,5sleep03115599cyclictest23:55:470
821921640,2sleep33116999cyclictest23:14:423
3206121590,2sleep13116099cyclictest20:54:291
1068911000,4ptp4l401ktimersoftd/319:45:113
160522760,1sleep00-21swapper/001:09:100
106891750,1ptp4l401ktimersoftd/322:26:273
106891710,1ptp4l401ktimersoftd/300:38:033
195552670,3sleep0101ktimersoftd/000:37:380
106891670,1ptp4l401ktimersoftd/323:34:063
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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