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2026-03-04 - 00:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Tue Mar 03, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1927721690,4sleep11845699cyclictest11:40:091
433121600,4sleep21846699cyclictest11:25:082
765221530,5sleep21846699cyclictest09:45:082
106891990,4ptp4l401ktimersoftd/307:53:473
126412770,2sleep00-21swapper/013:10:460
126412770,2sleep00-21swapper/013:10:460
106891750,1ptp4l401ktimersoftd/310:41:373
133552660,2sleep30-21swapper/311:34:413
133552660,2sleep30-21swapper/311:34:413
318482650,2sleep20-21swapper/209:25:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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