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2026-01-14 - 11:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Wed Jan 14, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1619421860,4sleep0591799cyclictest22:50:360
1023321760,5sleep0591799cyclictest22:11:330
3124721520,3sleep0591799cyclictest20:18:120
140221400,4sleep1592499cyclictest23:43:041
106891960,3ptp4l401ktimersoftd/319:27:423
119042840,4sleep011900-21tune2fs22:13:180
274162710,3sleep20-21swapper/221:55:422
106891700,1ptp4l401ktimersoftd/323:26:183
106891690,1ptp4l401ktimersoftd/321:08:193
106891670,1ptp4l401ktimersoftd/323:37:533
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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