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2026-02-28 - 20:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Sat Feb 28, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
566621760,3sleep11567699cyclictest10:54:071
2208221730,5sleep01567199cyclictest12:18:180
1068911090,4ptp4l401ktimersoftd/307:49:023
129112750,4sleep1241ktimersoftd/109:56:301
106891720,1ptp4l401ktimersoftd/312:11:383
106891660,2ptp4l32569-21kworker/3:211:01:043
106891660,1ptp4l401ktimersoftd/312:14:323
106891650,1ptp4l401ktimersoftd/309:08:313
114742600,2sleep30-21swapper/313:13:293
23582590,2sleep30-21swapper/311:58:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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