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2026-02-12 - 06:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Thu Feb 12, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
949721560,5sleep01907999cyclictest00:57:150
1748921500,3sleep21909199cyclictest23:27:082
1686121160,5sleep20-21swapper/219:39:142
1068911030,4ptp4l401ktimersoftd/319:42:353
55832850,1sleep30-21swapper/323:48:333
114862810,4sleep211488-21mailstats21:39:282
55202760,3sleep20-21swapper/200:53:522
106891740,1ptp4l401ktimersoftd/301:12:393
112882700,2sleep30-21swapper/322:48:273
34192690,2sleep30-21swapper/300:19:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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