You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-14 - 09:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Sat Feb 14, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2061121530,4sleep2265199cyclictest00:21:182
1068911040,4ptp4l401ktimersoftd/319:40:493
259032640,2sleep0263999cyclictest01:00:350
106891590,1ptp4l401ktimersoftd/301:04:303
106891590,1ptp4l401ktimersoftd/300:35:443
106891590,1ptp4l401ktimersoftd/300:35:443
264699583,38cyclictest16063-21apt-get22:05:241
106891570,1ptp4l401ktimersoftd/300:24:093
106891570,1ptp4l401ktimersoftd/300:07:003
106891560,1ptp4l401ktimersoftd/300:26:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional