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2026-02-09 - 05:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Mon Feb 09, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2664721490,2sleep00-21swapper/001:10:350
1068911170,8ptp4l7696-21kworker/3:119:40:453
106172800,2sleep30-21swapper/320:17:543
23905997259,6cyclictest25-21ksoftirqd/100:32:431
106891710,1ptp4l401ktimersoftd/322:54:093
55582670,2sleep30-21swapper/323:07:563
26962640,2sleep00-21swapper/021:59:320
234672624,10sleep00-21swapper/019:38:070
23909996150,5cyclictest33-21ksoftirqd/200:07:402
23905996047,7cyclictest25-21ksoftirqd/100:22:421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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