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2026-03-08 - 03:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Sun Mar 08, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2163821760,5sleep1602599cyclictest22:18:321
3105521690,4sleep3604199cyclictest21:52:483
3210121460,3sleep3604199cyclictest21:57:343
2190421360,5sleep2603599cyclictest01:05:152
106891980,4ptp4l401ktimersoftd/319:54:343
106891740,1ptp4l401ktimersoftd/322:13:073
106891740,1ptp4l401ktimersoftd/300:24:123
106891740,1ptp4l401ktimersoftd/300:24:123
200462700,2sleep00-21swapper/023:57:400
106891700,1ptp4l401ktimersoftd/322:03:413
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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