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2026-03-01 - 19:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Sun Mar 01, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1068911800,5ptp4l401ktimersoftd/307:51:003
2114421530,5sleep21499699cyclictest10:39:052
1608621400,4sleep11499199cyclictest12:12:101
1311321290,3sleep01498499cyclictest11:04:040
263602630,2sleep20-21swapper/212:54:232
15004996352,6cyclictest41-21ksoftirqd/308:13:573
251602590,2sleep30-21swapper/311:15:233
14984995947,6cyclictest9-21ksoftirqd/012:19:020
15004995833,3cyclictest41-21ksoftirqd/312:09:033
14984995849,5cyclictest9-21ksoftirqd/011:19:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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