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2026-03-06 - 01:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Thu Mar 05, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
923722060,9sleep20-21swapper/207:51:192
2159221750,2sleep31026699cyclictest11:51:593
254221530,5sleep21025799cyclictest10:26:262
2497421280,3sleep31026699cyclictest11:56:203
1068911040,4ptp4l401ktimersoftd/307:54:063
106891720,14ptp4l14866-21kworker/3:110:40:523
196732710,4sleep3401ktimersoftd/308:11:263
196732710,4sleep3401ktimersoftd/308:11:263
198532700,2sleep00-21swapper/012:56:320
101122664,10sleep00-21swapper/007:55:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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