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2026-03-03 - 09:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Tue Mar 03, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1545421580,5sleep02375899cyclictest21:49:530
3114921570,4sleep22376999cyclictest21:14:542
1292721570,3sleep32377899cyclictest23:27:283
1068911030,4ptp4l401ktimersoftd/319:51:263
16352940,3sleep10-21swapper/122:44:061
292962760,2sleep20-21swapper/222:39:252
172782730,2sleep10-21swapper/120:44:581
278202720,3sleep127739-21ssh00:15:001
106891660,1ptp4l401ktimersoftd/321:29:523
106891660,1ptp4l401ktimersoftd/321:29:523
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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