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2026-02-28 - 13:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Sat Feb 28, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
413921750,2sleep31095799cyclictest00:37:093
1006021710,5sleep31095799cyclictest22:30:223
1977521600,2sleep21095399cyclictest23:46:452
1797921520,4sleep31095799cyclictest23:11:533
1068911030,4ptp4l401ktimersoftd/319:50:223
173612760,5sleep017365-21timerandwakeup21:08:250
19912620,3sleep01094399cyclictest22:54:440
23332590,2sleep20-21swapper/223:28:182
10953995847,6cyclictest33-21ksoftirqd/222:38:092
103862552,15sleep1241ktimersoftd/119:48:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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