You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-01 - 12:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Sun Mar 01, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
584021680,4sleep2444499cyclictest01:13:352
1464121570,3sleep2444499cyclictest00:16:062
1068911410,10ptp4l28166-21kworker/3:219:53:263
106891740,1ptp4l401ktimersoftd/323:07:223
106891690,10ptp4l401ktimersoftd/322:25:263
8962670,3sleep0876-21ssh01:08:360
56012660,3sleep2321ktimersoftd/221:56:222
4444996451,6cyclictest33-21ksoftirqd/221:43:432
40572644,10sleep20-21swapper/219:49:552
106891630,1ptp4l401ktimersoftd/301:19:503
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional