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2026-02-02 - 04:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Mon Feb 02, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1068911800,5ptp4l401ktimersoftd/319:36:213
3219921560,5sleep21921499cyclictest23:39:042
644421430,3sleep11920999cyclictest22:40:491
240392780,27sleep01920399cyclictest00:38:160
106891720,1ptp4l401ktimersoftd/300:01:593
106891720,1ptp4l401ktimersoftd/300:01:593
124282680,5sleep112431-21cpuspeed_turbos00:58:521
19214996751,7cyclictest33-21ksoftirqd/220:13:432
106891650,1ptp4l401ktimersoftd/322:49:053
224272640,2sleep20-21swapper/200:03:372
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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