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2026-02-18 - 15:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Wed Feb 18, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3216321400,3sleep21104799cyclictest11:56:112
1068911170,8ptp4l8380-21kworker/3:007:46:523
276782650,2sleep20-21swapper/209:27:522
106891640,1ptp4l401ktimersoftd/310:24:243
14742630,2sleep30-21swapper/313:04:133
259502590,2sleep30-21swapper/308:17:403
11041995947,5cyclictest25-21ksoftirqd/111:27:561
106891580,1ptp4l401ktimersoftd/312:08:493
251962560,2sleep325197-21diskmemload10:42:013
106891560,1ptp4l401ktimersoftd/308:48:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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