You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-02 - 08:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Mon Mar 02, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1061423160,4sleep00-21swapper/019:49:170
1077421800,5sleep21247099cyclictest22:29:442
643321760,4sleep21247099cyclictest00:37:202
643321760,4sleep21247099cyclictest00:37:202
2449221640,3sleep01246099cyclictest22:11:520
1068911020,42ptp4l401ktimersoftd/319:53:133
106891960,1ptp4l401ktimersoftd/301:19:073
106891710,1ptp4l401ktimersoftd/322:27:033
106891700,1ptp4l401ktimersoftd/322:01:033
106891700,1ptp4l401ktimersoftd/300:20:503
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional