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2026-02-15 - 05:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Sun Feb 15, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1068911820,5ptp4l401ktimersoftd/319:43:313
674921740,4sleep2552999cyclictest01:12:432
2099821500,2sleep2552999cyclictest23:14:432
1363121450,4sleep1552399cyclictest00:46:161
269822830,3sleep10-21swapper/101:01:061
5535996713,21cyclictest7644-21sh23:33:503
30722660,2sleep10-21swapper/121:50:151
264832620,3sleep3553599cyclictest22:13:053
219822620,2sleep10-21swapper/100:56:041
51052594,10sleep10-21swapper/119:41:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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