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2026-02-17 - 02:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Mon Feb 16, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
325922510,3sleep00-21swapper/007:41:570
775521660,5sleep1416399cyclictest11:02:301
2143521650,4sleep0415799cyclictest10:43:300
1068911050,4ptp4l401ktimersoftd/307:42:053
106891770,1ptp4l401ktimersoftd/310:29:493
206502680,7sleep0101ktimersoftd/008:16:570
296192670,5sleep029622-21latency_hist11:26:380
6952600,5sleep09-21ksoftirqd/013:10:410
39832604,10sleep20-21swapper/207:45:402
263082600,3sleep3417599cyclictest13:02:093
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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