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2026-02-13 - 20:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Fri Feb 13, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1068911740,5ptp4l401ktimersoftd/307:44:163
664621600,3sleep2139799cyclictest09:55:252
1385997014,17cyclictest26755-21diskmemload12:28:160
220002680,4sleep3140199cyclictest11:18:293
95512670,4sleep09554-21switchtime12:10:250
309462670,4sleep3140199cyclictest08:45:053
1385996714,17cyclictest29006-21ptp4l-jitter12:30:220
9622635,46sleep00-21swapper/007:40:490
1385996313,18cyclictest20613-21sed09:30:140
139099621,28cyclictest22841-21ssh10:45:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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