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2026-02-26 - 09:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Thu Feb 26, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1096221660,4sleep21873099cyclictest21:47:142
2373921540,4sleep11872299cyclictest23:08:351
453421380,4sleep21873099cyclictest23:56:542
106891890,3ptp4l401ktimersoftd/319:50:003
183482684,10sleep00-21swapper/019:48:280
121022620,2sleep30-21swapper/322:24:213
18736996112,26cyclictest29993-21sh23:48:153
18715995948,6cyclictest9-21ksoftirqd/000:52:040
18715995948,6cyclictest9-21ksoftirqd/000:52:040
1873699580,23cyclictest15935-21taskset21:55:443
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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