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2026-01-26 - 03:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Mon Jan 26, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3129821860,4sleep21785999cyclictest23:00:072
895921530,5sleep21785999cyclictest23:44:442
1204521490,3sleep21785999cyclictest22:07:442
953021480,5sleep01784899cyclictest21:30:000
1964521410,5sleep11785499cyclictest22:49:341
1068911000,38ptp4l401ktimersoftd/319:32:373
106891730,1ptp4l401ktimersoftd/321:53:513
106891710,1ptp4l401ktimersoftd/322:39:093
7682680,4sleep31786899cyclictest21:10:043
106891680,1ptp4l401ktimersoftd/321:44:413
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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