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2026-01-24 - 09:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Sat Jan 24, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
961726957,8sleep10-21swapper/119:05:101
33582690,0sleep10-21swapper/123:33:251
924326832,31sleep00-21swapper/019:05:050
10235993510,1cyclictest0-21swapper/023:55:040
10235993131,0cyclictest0-21swapper/020:01:230
10235993110,18cyclictest0-21swapper/022:33:320
10236993010,13cyclictest0-21swapper/120:22:181
10236992810,1cyclictest0-21swapper/123:14:241
10236992722,2cyclictest0-21swapper/123:59:351
10236992712,9cyclictest1657-21apache200:17:351
10236992710,5cyclictest0-21swapper/122:12:031
10235992713,10cyclictest0-21swapper/023:14:570
1023599271,25cyclictest0-21swapper/023:08:410
10235992710,0cyclictest0-21swapper/022:51:240
10236992626,0cyclictest0-21swapper/120:51:191
10236992621,2cyclictest6403-21sh22:54:441
10236992617,7cyclictest1657-21apache223:25:031
10236992610,15cyclictest0-21swapper/122:48:301
10236992610,0cyclictest0-21swapper/119:50:001
10235992512,11cyclictest0-21swapper/022:13:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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