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2025-12-01 - 18:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Mon Dec 01, 2025 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1660322040,2sleep10-21swapper/107:01:581
215512680,0sleep00-21swapper/011:40:360
1767426856,8sleep00-21swapper/007:03:120
18192994110,9cyclictest0-21swapper/112:03:171
18192994010,8cyclictest0-21swapper/108:36:541
18192993810,6cyclictest0-21swapper/109:45:051
18192993710,3cyclictest0-21swapper/109:56:551
18191993710,3cyclictest0-21swapper/011:55:440
18192993636,0cyclictest0-21swapper/112:34:521
18192993410,23cyclictest0-21swapper/109:54:581
18192993410,21cyclictest0-21swapper/111:33:091
1819299340,8cyclictest0-21swapper/109:32:571
18191993310,23cyclictest0-21swapper/011:11:240
18191993131,0cyclictest0-21swapper/010:37:250
1819299303,4cyclictest0-21swapper/110:57:021
18192992910,3cyclictest0-21swapper/111:41:171
1819299290,4cyclictest1536-21diskmemload09:07:301
1819299283,13cyclictest0-21swapper/111:02:021
1819299281,5cyclictest0-21swapper/112:16:261
1819299280,0cyclictest3599-21kworker/u4:109:17:041
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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