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2025-12-08 - 19:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Mon Dec 08, 2025 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2737427058,8sleep10-21swapper/107:03:101
2755226957,8sleep00-21swapper/007:05:000
27890994210,31cyclictest0-21swapper/012:26:510
27890994210,20cyclictest91rcu_preempt08:01:310
27890994110,30cyclictest0-21swapper/010:16:590
27890994010,30cyclictest0-21swapper/011:55:270
27890994010,30cyclictest0-21swapper/010:01:590
27890994010,29cyclictest0-21swapper/010:51:520
27890994010,18cyclictest91rcu_preempt09:07:340
27890993913,25cyclictest0-21swapper/008:06:500
27890993910,28cyclictest15545-21ls10:37:010
27890993910,28cyclictest0-21swapper/009:27:020
27890993910,26cyclictest0-21swapper/011:09:030
27890993910,25cyclictest0-21swapper/007:50:130
27890993910,18cyclictest0-21swapper/011:47:140
27890993811,17cyclictest91rcu_preempt09:50:300
27890993810,28cyclictest0-21swapper/011:29:150
27890993810,28cyclictest0-21swapper/009:15:270
27890993810,27cyclictest0-21swapper/012:34:560
27890993810,27cyclictest0-21swapper/011:05:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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