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2025-10-31 - 16:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Fri Oct 31, 2025 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3199927158,9sleep00-21swapper/007:04:020
3220727057,8sleep10-21swapper/107:06:141
32459993410,21cyclictest0-21swapper/109:40:171
32458993131,0cyclictest0-21swapper/010:19:460
32459992929,0cyclictest0-21swapper/111:33:531
32458992919,7cyclictest9904-21apache211:16:270
32459992812,8cyclictest97750irq/106-eth1-rx12:36:111
32459992727,0cyclictest0-21swapper/109:36:121
32459992719,6cyclictest9904-21apache209:08:241
32459992710,12cyclictest0-21swapper/112:27:111
3245999270,24cyclictest0-21swapper/111:56:021
32458992721,3cyclictest9904-21apache208:50:340
32459992611,6cyclictest0-21swapper/112:02:111
32458992610,11cyclictest0-21swapper/011:03:230
32459992519,2cyclictest9904-21apache209:50:401
32459992518,5cyclictest9876-21apache212:21:461
32459992513,8cyclictest9904-21apache209:58:491
32459992512,11cyclictest13600-21kworker/1:207:40:171
32459992510,9cyclictest0-21swapper/110:10:011
3245999245,18cyclictest0-21swapper/112:12:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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