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2025-11-28 - 18:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Fri Nov 28, 2025 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
566827056,9sleep00-21swapper/007:02:260
599026957,8sleep10-21swapper/107:05:461
212682570,0sleep00-21swapper/009:48:310
87092470,1sleep08680-21latency10:57:000
6262993810,27cyclictest0-21swapper/011:23:080
6262993410,19cyclictest11505-21kworker/u4:110:43:470
6262993215,14cyclictest0-21swapper/009:19:060
6262993112,18cyclictest0-21swapper/012:01:150
6262993010,20cyclictest0-21swapper/010:04:580
6262993010,1cyclictest0-21swapper/008:33:420
6263992923,2cyclictest16102-21apache209:20:091
626399291,27cyclictest0-21swapper/111:10:341
6263992828,0cyclictest0-21swapper/112:24:271
6263992827,0cyclictest231ktimersoftd/111:56:531
6262992814,14cyclictest0-21swapper/009:09:100
6262992727,0cyclictest0-21swapper/009:30:210
626299271,2cyclictest16462-21/usr/sbin/munin08:57:070
6263992621,3cyclictest16076-21apache208:07:011
6262992626,0cyclictest0-21swapper/012:12:250
6263992514,4cyclictest16076-21apache208:12:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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