You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-23 - 10:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Mon Feb 23, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2274427054,8sleep10-21swapper/119:09:061
2239827057,9sleep00-21swapper/019:05:290
144342690,1sleep0121rcuc/022:49:500
22967993410,0cyclictest0-21swapper/022:06:270
2296799320,4cyclictest0-21swapper/021:37:540
22967993110,8cyclictest0-21swapper/021:21:040
2296799310,10cyclictest27066-21awk20:44:320
2296799300,14cyclictest0-21swapper/023:43:410
2296799292,8cyclictest0-21swapper/000:23:220
22967992821,7cyclictest0-21swapper/020:19:320
2296799281,7cyclictest0-21swapper/021:49:520
22967992817,11cyclictest0-21swapper/021:18:120
2296899273,6cyclictest0-21swapper/122:44:491
22968992727,0cyclictest0-21swapper/120:25:431
22968992719,8cyclictest0-21swapper/122:58:261
22968992710,15cyclictest0-21swapper/100:29:511
2296799271,8cyclictest0-21swapper/022:09:380
2296899261,6cyclictest167-21systemd-journal19:12:011
22968992610,15cyclictest0-21swapper/123:42:151
2296799262,8cyclictest0-21swapper/022:34:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional