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2024-05-08 - 15:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Wed May 08, 2024 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
161642740,1sleep12336199cyclictest22:38:051
2285926846,18sleep10-21swapper/119:01:311
2274026855,8sleep00-21swapper/019:00:240
66122190,0sleep00-21swapper/021:45:170
23361991810,7cyclictest24837-21ssh22:49:171
23361991716,1cyclictest5137-21ssh21:44:421
23361991716,1cyclictest31353-21ssh22:16:201
23361991716,1cyclictest15857-21ssh23:59:001
23360991716,1cyclictest15833-21ssh21:16:510
23361991616,0cyclictest0-21swapper/121:15:281
23361991615,1cyclictest29752-21ssh00:17:371
23361991615,0cyclictest22267-21ssh00:06:331
23361991614,1cyclictest28369-21ls19:15:141
23361991610,6cyclictest0-21swapper/121:10:291
23361991610,0cyclictest0-21swapper/122:43:321
23360991616,0cyclictest16547-21ssh00:00:030
23360991615,1cyclictest5816-21ssh00:28:230
23360991615,1cyclictest31855-21ssh21:36:380
23360991615,1cyclictest24538-21ssh21:28:160
23360991615,0cyclictest7322-21seq21:07:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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