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2025-12-23 - 13:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Tue Dec 23, 2025 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2951926847,17sleep00-21swapper/019:06:200
2967126754,8sleep10-21swapper/119:07:551
3004699300,8cyclictest9039-21awk19:39:570
30047992929,0cyclictest0-21swapper/123:50:411
3004699280,28cyclictest0-21swapper/022:30:050
30047992711,15cyclictest6495-21kworker/1:019:54:071
30046992726,1cyclictest0-21swapper/023:18:280
30047992613,7cyclictest20732-21apache220:15:141
30047992610,7cyclictest24-21ksoftirqd/121:10:171
30046992610,16cyclictest0-21swapper/022:52:490
30046992510,5cyclictest0-21swapper/021:35:080
30047992421,3cyclictest20712-21apache220:25:141
30047992419,3cyclictest24-21ksoftirqd/123:34:561
30047992411,8cyclictest0-21swapper/123:10:121
30046992410,8cyclictest0-21swapper/023:40:100
30046992410,7cyclictest0-21swapper/022:20:160
30046992317,5cyclictest27296-21munin-node22:13:030
30046992310,4cyclictest0-21swapper/019:40:100
30046992310,4cyclictest0-21swapper/019:15:150
30046992310,4cyclictest0-21swapper/000:15:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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