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2025-11-21 - 18:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Fri Nov 21, 2025 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2884326956,8sleep00-21swapper/007:02:140
2899626754,8sleep10-21swapper/107:03:501
29457994311,20cyclictest91rcu_preempt12:17:130
29457994111,28cyclictest91rcu_preempt09:31:060
29457994110,31cyclictest0-21swapper/010:57:290
29457994110,30cyclictest0-21swapper/011:36:160
29457994010,30cyclictest0-21swapper/009:41:570
29457994010,29cyclictest0-21swapper/009:10:020
29457993911,24cyclictest91rcu_preempt10:30:510
29457993910,29cyclictest0-21swapper/008:52:050
29457993910,28cyclictest0-21swapper/007:12:070
29457993910,28cyclictest0-21swapper/007:07:070
29457993910,17cyclictest91rcu_preempt09:14:210
29457993813,23cyclictest91rcu_preempt08:20:570
29457993811,25cyclictest91rcu_preempt09:52:000
29457993712,23cyclictest91rcu_preempt12:02:450
29457993711,25cyclictest0-21swapper/012:11:580
29457993710,27cyclictest0-21swapper/011:20:580
2945799370,36cyclictest6134-21uptime10:22:060
29457993610,26cyclictest0-21swapper/011:47:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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