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2025-09-18 - 18:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Thu Sep 18, 2025 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2190421350,0sleep021905-21dump-pmu-power08:47:130
1551027361,7sleep10-21swapper/107:06:341
165542720,1sleep00-21swapper/010:14:310
1527626855,8sleep00-21swapper/007:04:060
108802650,1sleep00-21swapper/009:23:280
1575799364,0cyclictest91rcu_preempt11:51:291
15757993534,0cyclictest97950irq/108-eth1-tx09:13:221
1575799326,3cyclictest91rcu_preempt11:44:351
15757993211,2cyclictest91rcu_preempt09:27:101
15756993231,1cyclictest0-21swapper/008:50:180
1575799316,3cyclictest91rcu_preempt10:57:221
15757993110,2cyclictest91rcu_preempt11:11:331
15756993130,1cyclictest0-21swapper/008:35:000
15757993028,2cyclictest0-21swapper/109:02:341
15757993024,5cyclictest24-21ksoftirqd/111:56:511
15757993017,3cyclictest91rcu_preempt09:29:181
15757992929,0cyclictest24-21ksoftirqd/112:27:261
1575799292,1cyclictest91rcu_preempt10:15:041
15757992921,2cyclictest24-21ksoftirqd/111:17:331
15757992920,5cyclictest3941-21ssh12:15:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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