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2025-11-06 - 14:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot6.osadl.org (updated Thu Nov 06, 2025 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
208838421190,5sleep00-21swapper/019:05:280
208872329342,12sleep50-21swapper/519:09:455
2088972999116,41cyclictest0-21swapper/622:28:126
23516422900,1sleep7621rcuc/723:36:277
23516422900,1sleep7621rcuc/723:36:277
2088972998916,40cyclictest0-21swapper/619:23:116
2088972998816,37cyclictest0-21swapper/600:23:116
216999860,72rtkit-daemon0-21swapper/619:08:286
2088979998521,35cyclictest0-21swapper/719:13:117
2088979998521,35cyclictest0-21swapper/719:13:117
2088972998516,35cyclictest0-21swapper/623:13:116
208856928445,13sleep20-21swapper/219:07:332
2088972998015,34cyclictest0-21swapper/621:38:126
23670952780,0sleep30-21swapper/323:50:013
2088965997815,27cyclictest0-21swapper/519:58:115
2088972997517,33cyclictest0-21swapper/620:53:116
24166822740,0sleep50-21swapper/500:28:555
21226712740,0sleep20-21swapper/220:00:192
21006032740,0sleep70-21swapper/719:25:167
21279522730,0sleep442-21ksoftirqd/420:10:144
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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