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2026-03-09 - 08:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot6.osadl.org (updated Mon Mar 09, 2026 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
352669899372371,1cyclictest0-21swapper/600:05:026
352669899369366,2cyclictest97550irq/166-enp0s3123:56:036
352669899367366,1cyclictest3638156-21kworker/6:023:07:026
352669899366365,1cyclictest3820311-21kworker/6:219:20:026
352669899366364,2cyclictest0-21swapper/622:05:026
352669899366364,1cyclictest0-21swapper/600:20:026
352669899366363,2cyclictest3638156-21kworker/6:022:49:026
352669899365364,1cyclictest3638156-21kworker/6:022:20:036
352669899365364,1cyclictest0-21swapper/622:15:026
352669899365363,1cyclictest97550irq/166-enp0s3122:13:036
352669899365363,1cyclictest0-21swapper/600:04:026
352669899364363,1cyclictest0-21swapper/623:49:026
352669899364363,1cyclictest0-21swapper/623:23:026
352669899364363,1cyclictest0-21swapper/620:55:026
352669899364362,1cyclictest97550irq/166-enp0s3122:35:026
352669899363362,1cyclictest3638156-21kworker/6:022:57:026
352669899363362,1cyclictest3638156-21kworker/6:021:53:026
352669899363362,1cyclictest0-21swapper/600:38:026
352669899363361,1cyclictest3596691-21kworker/6:121:23:026
352669899363361,1cyclictest0-21swapper/621:43:036
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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