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2025-11-23 - 16:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot6.osadl.org (updated Sun Nov 23, 2025 12:46:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17854832130112,2sleep20-21swapper/207:05:172
178446829576,17sleep40-21swapper/407:05:114
216999910,44rtkit-daemon0-21swapper/507:07:165
1787378999116,42cyclictest0-21swapper/212:08:142
1787378999116,42cyclictest0-21swapper/212:08:142
1787378998816,40cyclictest0-21swapper/208:48:132
1787366998717,39cyclictest0-21swapper/109:13:121
1787378998616,37cyclictest0-21swapper/212:18:142
1787359998613,40cyclictest0-21swapper/011:08:130
1787359998517,36cyclictest0-21swapper/010:43:130
1787359998517,36cyclictest0-21swapper/010:43:130
1787378998415,36cyclictest0-21swapper/210:33:132
1787359998316,35cyclictest0-21swapper/007:13:130
1787359998315,36cyclictest0-21swapper/008:13:130
1787359998312,36cyclictest0-21swapper/008:03:130
1787366998215,36cyclictest0-21swapper/111:18:131
1787366998215,36cyclictest0-21swapper/109:23:131
178735999808,38cyclictest0-21swapper/011:33:130
1787366997915,35cyclictest0-21swapper/110:08:131
18147692760,0sleep60-21swapper/607:50:166
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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