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2025-11-13 - 17:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot6.osadl.org (updated Thu Nov 13, 2025 12:46:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24265792135116,3sleep20-21swapper/207:05:222
24258162134116,3sleep50-21swapper/507:05:175
242609829890,4sleep70-21swapper/707:05:197
2428149999628,38cyclictest0-21swapper/108:03:121
2428157999417,41cyclictest0-21swapper/211:43:132
2428157999118,38cyclictest0-21swapper/208:18:132
2428157999116,40cyclictest0-21swapper/212:18:122
2428157998816,38cyclictest0-21swapper/209:48:132
2428164998716,39cyclictest0-21swapper/311:33:123
2428157998717,37cyclictest0-21swapper/208:48:132
2428157998617,36cyclictest0-21swapper/210:08:132
2428149998417,37cyclictest0-21swapper/107:28:131
242791228440,13sleep60-21swapper/607:09:366
2428149998326,37cyclictest0-21swapper/110:33:131
242716128362,18sleep00-21swapper/007:05:270
2428164998215,34cyclictest0-21swapper/309:23:133
2428164998116,35cyclictest0-21swapper/308:28:133
242793128042,13sleep40-21swapper/407:09:504
25770972760,0sleep3341rcuc/311:00:153
25767742750,0sleep20-21swapper/211:00:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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