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2026-06-28 - 13:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot6.osadl.org (updated Sun Jun 28, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1880018994010,400cyclictest0-21swapper/519:37:035
1880018993990,398cyclictest0-21swapper/519:48:035
1879980993990,398cyclictest0-21swapper/020:26:020
1879980993990,398cyclictest0-21swapper/019:23:020
1880018993980,397cyclictest0-21swapper/521:07:025
1880018993980,397cyclictest0-21swapper/520:18:025
1880018993980,397cyclictest0-21swapper/519:34:035
1879980993980,1cyclictest0-21swapper/020:51:020
1880018993970,396cyclictest0-21swapper/519:28:025
1879980993970,397cyclictest0-21swapper/020:23:020
1879980993970,396cyclictest0-21swapper/020:14:030
1879980993970,1cyclictest0-21swapper/019:38:020
187998699394392,1cyclictest0-21swapper/123:59:021
187998699394392,1cyclictest0-21swapper/123:07:021
187998699393391,1cyclictest0-21swapper/121:25:021
187998699392391,1cyclictest0-21swapper/122:06:021
187998699391389,1cyclictest0-21swapper/123:49:021
187998699391389,1cyclictest0-21swapper/121:57:021
187998699390389,1cyclictest0-21swapper/121:18:021
187998699390389,1cyclictest0-21swapper/100:22:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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