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2025-11-16 - 17:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot6.osadl.org (updated Sun Nov 16, 2025 12:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35033382129111,3sleep20-21swapper/207:05:232
35040002940,3sleep10-21swapper/107:05:291
216999920,45rtkit-daemon0-21swapper/507:05:195
350425729143,12sleep40-21swapper/407:08:554
3504574998630,35cyclictest0-21swapper/711:23:127
3504574998616,38cyclictest0-21swapper/712:08:137
350427128543,13sleep00-21swapper/007:09:070
350403128543,13sleep70-21swapper/707:05:447
35751592840,0sleep00-21swapper/009:00:160
3504567998428,37cyclictest0-21swapper/611:33:136
3504567998415,38cyclictest0-21swapper/611:43:126
3504574998316,37cyclictest0-21swapper/710:23:137
3504567998315,38cyclictest0-21swapper/607:33:136
3504567998315,36cyclictest0-21swapper/612:33:136
3504567998115,35cyclictest0-21swapper/609:38:136
3504567998015,34cyclictest0-21swapper/607:23:136
3504574997715,34cyclictest0-21swapper/707:43:137
3504574997714,36cyclictest0-21swapper/710:13:137
35136182760,1sleep763-21ksoftirqd/707:20:187
3504574997532,36cyclictest0-21swapper/710:38:137
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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