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2026-02-06 - 04:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Thu Feb 05, 2026 00:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13635499367366,1cyclictest0-21swapper/023:17:020
13638799358356,1cyclictest348883-21kworker/4:123:17:014
13635499357355,1cyclictest0-21swapper/023:24:020
13635499356355,1cyclictest348616-21kworker/0:323:50:020
13635499356355,1cyclictest200368-21kworker/0:221:20:020
13635499355353,1cyclictest200368-21kworker/0:222:27:010
13635499354353,1cyclictest348616-21kworker/0:323:41:010
13635499354351,2cyclictest348616-21kworker/0:300:12:010
13635499354351,2cyclictest200368-21kworker/0:221:56:020
13635499353352,1cyclictest437019-21kworker/0:000:25:010
13635499353352,1cyclictest437019-21kworker/0:000:23:020
13635499353352,1cyclictest3343822-21kworker/0:119:55:020
13635499353352,1cyclictest0-21swapper/022:58:020
13635499352351,1cyclictest3343822-21kworker/0:120:21:020
13635499352351,1cyclictest200368-21kworker/0:222:07:020
13635499352351,1cyclictest200368-21kworker/0:221:35:010
13635499352351,1cyclictest0-21swapper/023:48:020
13640299351350,1cyclictest0-21swapper/622:48:016
13640299351350,1cyclictest0-21swapper/622:06:026
13635499351350,1cyclictest348616-21kworker/0:323:56:020
13635499351350,1cyclictest3343822-21kworker/0:119:36:020
13635499351350,1cyclictest200368-21kworker/0:221:15:020
13635499351350,1cyclictest200368-21kworker/0:221:13:010
13635499351350,1cyclictest0-21swapper/023:07:020
13640299350348,1cyclictest232971-21kworker/6:122:55:016
13635499350349,1cyclictest348616-21kworker/0:300:15:020
13635499350349,1cyclictest200368-21kworker/0:222:45:010
13635499350349,1cyclictest200368-21kworker/0:221:43:010
13635499350349,1cyclictest0-21swapper/019:15:020
13635499350349,1cyclictest0-21swapper/000:01:010
13635499350348,1cyclictest200368-21kworker/0:222:15:020
13640299349347,1cyclictest0-21swapper/623:00:016
13635499349348,1cyclictest437019-21kworker/0:000:32:010
13635499349348,1cyclictest3343822-21kworker/0:119:50:020
13635499349348,1cyclictest200368-21kworker/0:221:48:020
13635499349348,1cyclictest0-21swapper/023:12:020
13635499349348,1cyclictest0-21swapper/022:30:020
13640299348347,1cyclictest0-21swapper/600:35:016
13638799348346,1cyclictest0-21swapper/423:50:014
13638799348345,2cyclictest191352-21kworker/4:021:20:014
13635499348347,1cyclictest348616-21kworker/0:323:32:020
13635499348347,1cyclictest3343822-21kworker/0:119:20:020
13635499348347,1cyclictest200368-21kworker/0:220:55:020
13635499348347,1cyclictest0-21swapper/023:36:010
13635499348347,1cyclictest0-21swapper/021:27:020
13635499348347,1cyclictest0-21swapper/000:36:010
13635499348347,1cyclictest0-21swapper/000:05:010
13640299347345,1cyclictest0-21swapper/622:21:026
13635499347346,1cyclictest200368-21kworker/0:222:13:020
13635499347346,1cyclictest200368-21kworker/0:222:02:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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