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2026-02-26 - 08:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Thu Feb 26, 2026 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
376673299382380,1cyclictest4034237-21kworker/0:200:13:020
376678599380377,2cyclictest3899720-21ssh22:00:027
376678599380377,1cyclictest3945152-21kworker/7:300:15:027
376673299380379,1cyclictest4034237-21kworker/0:200:26:020
376673299380379,1cyclictest3797644-21kworker/0:023:36:020
376673299380379,1cyclictest3797644-21kworker/0:022:52:020
376673299380379,1cyclictest3797644-21kworker/0:022:41:020
376673299380379,1cyclictest3797644-21kworker/0:020:13:020
376673299380379,1cyclictest0-21swapper/023:05:030
376673299380378,1cyclictest3797644-21kworker/0:023:43:020
3766732993800,379cyclictest0-21swapper/022:28:020
3766732993800,379cyclictest0-21swapper/022:02:020
3766732993800,379cyclictest0-21swapper/021:33:020
3766732993800,1cyclictest0-21swapper/022:47:020
376673299379378,1cyclictest3797644-21kworker/0:023:51:020
376673299379378,1cyclictest0-21swapper/021:42:030
376673299378377,1cyclictest3797644-21kworker/0:022:08:020
376673299377376,1cyclictest0-21swapper/020:30:020
376673299377376,1cyclictest0-21swapper/019:38:020
376678599376374,1cyclictest0-21swapper/721:14:027
376673299376375,1cyclictest3734328-21kworker/0:119:46:020
376673299376375,1cyclictest0-21swapper/019:40:020
376673299376374,1cyclictest0-21swapper/019:19:020
376678599375374,1cyclictest0-21swapper/700:09:027
376673299375374,1cyclictest3797644-21kworker/0:020:54:020
376673299375374,1cyclictest0-21swapper/020:41:020
376673299375374,1cyclictest0-21swapper/020:38:030
376673299375374,1cyclictest0-21swapper/019:57:030
376673299375373,1cyclictest0-21swapper/020:45:020
376678599374373,1cyclictest0-21swapper/721:50:027
376673299374373,1cyclictest3797644-21kworker/0:021:03:030
376673299374373,1cyclictest0-21swapper/020:27:020
376673299374373,1cyclictest0-21swapper/020:27:020
376673299374373,1cyclictest0-21swapper/019:54:020
376673299374373,1cyclictest0-21swapper/019:32:020
376673299373372,1cyclictest3797644-21kworker/0:020:03:020
376673299373372,1cyclictest0-21swapper/019:21:020
376678599372371,1cyclictest0-21swapper/722:06:027
376673299372371,1cyclictest0-21swapper/020:56:020
376678599371370,1cyclictest0-21swapper/723:34:027
376673299371370,1cyclictest0-21swapper/021:09:020
376678599370368,1cyclictest0-21swapper/723:52:027
376678599369368,1cyclictest0-21swapper/723:42:027
376678599369368,1cyclictest0-21swapper/721:47:027
376678599368367,1cyclictest3794645-21kworker/7:021:15:027
376678599368367,1cyclictest0-21swapper/722:25:027
376678599367366,1cyclictest3945152-21kworker/7:323:39:027
376678599367366,1cyclictest0-21swapper/721:29:027
376678599367365,1cyclictest0-21swapper/700:22:027
376678599366365,1cyclictest3945152-21kworker/7:322:59:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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