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2026-02-16 - 07:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Mon Feb 16, 2026 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
65477993810,380cyclictest0-21swapper/321:11:013
6550599371370,1cyclictest0-21swapper/723:03:017
6550599369368,1cyclictest0-21swapper/700:07:027
6550599368367,1cyclictest0-21swapper/722:01:017
6550599366365,1cyclictest0-21swapper/723:53:017
6550599365363,1cyclictest0-21swapper/719:45:017
6550599364363,1cyclictest0-21swapper/723:41:027
6550599364363,1cyclictest0-21swapper/700:15:027
6550599363362,1cyclictest0-21swapper/719:25:017
6550599363361,1cyclictest0-21swapper/719:21:027
6550599362361,1cyclictest0-21swapper/720:55:027
6550599362361,1cyclictest0-21swapper/720:55:017
6550599361359,1cyclictest362016-21kworker/7:119:13:027
6550599360359,1cyclictest0-21swapper/721:36:027
6550599360358,1cyclictest362016-21kworker/7:119:53:017
6550599360358,1cyclictest105407-21kworker/7:221:09:027
6550599359356,1cyclictest0-21swapper/720:43:027
6550599358357,1cyclictest0-21swapper/723:33:017
6550599357355,1cyclictest0-21swapper/719:36:027
6550599356354,1cyclictest0-21swapper/720:27:017
6550599355353,1cyclictest0-21swapper/723:21:017
6550599355353,1cyclictest0-21swapper/719:17:027
6550599354352,1cyclictest0-21swapper/700:01:017
6547799354352,1cyclictest260822-21kworker/3:123:03:023
6550599353352,1cyclictest255687-21kworker/7:200:30:037
6550599353352,1cyclictest255687-21kworker/7:200:24:017
6550599353352,1cyclictest0-21swapper/721:46:017
6550599353351,2cyclictest209651-21kworker/7:122:15:017
6550599353351,1cyclictest255687-21kworker/7:200:37:037
6550599353351,1cyclictest209651-21kworker/7:122:34:017
6547799353351,1cyclictest309220-21kworker/3:200:07:013
6550599352351,1cyclictest255687-21kworker/7:223:09:017
6550599352351,1cyclictest0-21swapper/722:47:027
6550599352350,1cyclictest0-21swapper/723:57:017
6550599352349,2cyclictest0-21swapper/723:28:027
6550599351350,1cyclictest105407-21kworker/7:221:42:027
6550599351349,1cyclictest105407-21kworker/7:222:05:027
6550599351349,1cyclictest0-21swapper/722:43:017
6550599351349,1cyclictest0-21swapper/722:35:017
6550599351348,2cyclictest209651-21kworker/7:122:10:027
6547799351349,2cyclictest162488-21kworker/3:122:01:023
6550599349348,1cyclictest105407-21kworker/7:221:21:017
6547799349348,1cyclictest309220-21kworker/3:223:53:013
6550599348347,1cyclictest255687-21kworker/7:222:55:017
6550599348347,1cyclictest255687-21kworker/7:200:11:037
6550599348347,1cyclictest209651-21kworker/7:122:23:027
6550599348347,1cyclictest209651-21kworker/7:122:23:017
6550599348347,1cyclictest0-21swapper/721:16:017
6550599348347,1cyclictest0-21swapper/720:20:017
6547799348346,1cyclictest53303-21kworker/3:019:45:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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