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2026-03-27 - 08:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Fri Mar 27, 2026 00:49:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19782994048,198cyclictest151rcu_preempt21:49:0726
19782994048,198cyclictest151rcu_preempt21:49:0626
3273913050,298ptp4l0-21swapper/119:08:161
19782992037,3cyclictest40-21ksoftirqd/422:21:1126
19782992037,3cyclictest40-21ksoftirqd/422:21:1126
1979899190186,1cyclictest151rcu_preempt00:32:2229
198439918113,160cyclictest0-21swapper/1320:45:195
197989917932,106cyclictest0-21swapper/723:00:4029
198439917812,130cyclictest0-21swapper/1321:47:205
198439917812,130cyclictest0-21swapper/1321:47:195
19763991774,168cyclictest0-21swapper/121:55:251
185092177169,6sleep280-21swapper/2819:09:4121
19763991765,135cyclictest0-21swapper/123:05:091
198439917012,115cyclictest0-21swapper/1321:32:215
198439917012,115cyclictest0-21swapper/1321:32:215
197989916623,103cyclictest0-21swapper/719:35:1329
197989916518,121cyclictest26116-21taskset19:10:2329
19876991562,146cyclictest0-21swapper/1921:34:3611
19876991562,146cyclictest0-21swapper/1921:34:3511
19876991562,129cyclictest0-21swapper/1900:25:3811
19876991552,152cyclictest0-21swapper/1922:18:2511
19876991552,152cyclictest0-21swapper/1922:18:2511
198439915512,105cyclictest0-21swapper/1321:58:295
19876991513,147cyclictest0-21swapper/1920:35:1711
19876991512,102cyclictest0-21swapper/1923:30:2011
198439915112,91cyclictest0-21swapper/1322:03:215
198439915112,91cyclictest0-21swapper/1322:03:215
19763991505,93cyclictest0-21swapper/100:33:521
19869991493,127cyclictest0-21swapper/1822:25:2210
19869991493,127cyclictest0-21swapper/1822:25:2110
19869991483,119cyclictest0-21swapper/1800:04:1210
198439914812,118cyclictest0-21swapper/1300:10:195
19869991473,126cyclictest0-21swapper/1822:48:2010
198439914412,100cyclictest0-21swapper/1321:40:135
198439914412,100cyclictest0-21swapper/1321:40:135
19763991444,89cyclictest0-21swapper/100:09:171
19843991420,85cyclictest0-21swapper/1300:15:225
1976399142121,20cyclictest22-21ksoftirqd/123:54:341
19881991407,85cyclictest0-21swapper/2019:55:2013
199209913953,51cyclictest0-21swapper/2523:36:2518
19881991396,108cyclictest0-21swapper/2000:17:0213
19869991383,85cyclictest0-21swapper/1800:06:0510
19869991382,93cyclictest0-21swapper/1822:20:0010
19869991382,93cyclictest0-21swapper/1822:20:0010
198889913712,72cyclictest0-21swapper/2100:28:2914
198819913628,67cyclictest0-21swapper/2019:50:1313
19876991362,82cyclictest0-21swapper/1900:30:2611
19876991362,81cyclictest0-21swapper/1922:46:1311
198439913640,58cyclictest0-21swapper/1323:05:055
19928991350,88cyclictest0-21swapper/2621:11:4419
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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