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2022-07-07 - 15:20

x86 AMD 1950X @3700 MHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #c, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Wed Jul 06, 2022 12:49:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2188399331135,2cyclictest151rcu_preempt09:28:5331
2193999190189,1cyclictest151rcu_preempt12:00:0110
2193999190189,1cyclictest151rcu_preempt12:00:0110
219399918811,146cyclictest0-21swapper/1811:31:0910
219399918811,146cyclictest0-21swapper/1811:31:0910
219399917811,119cyclictest0-21swapper/1809:39:5910
218149917449,82cyclictest0-21swapper/111:05:131
21854991694,107cyclictest151rcu_preempt10:22:0128
219689916731,106cyclictest0-21swapper/2209:51:1715
219689916336,77cyclictest0-21swapper/2211:54:4515
219689916336,77cyclictest0-21swapper/2211:54:4415
218149915831,124cyclictest151rcu_preempt09:57:051
21903991570,92cyclictest0-21swapper/1408:37:246
218149915729,99cyclictest0-21swapper/112:20:021
218149915729,99cyclictest0-21swapper/112:20:021
219039915631,99cyclictest0-21swapper/1409:30:186
219399915111,99cyclictest0-21swapper/1811:50:2510
219399915111,99cyclictest0-21swapper/1811:50:2410
218149915142,70cyclictest0-21swapper/111:10:021
218149915142,70cyclictest0-21swapper/111:10:021
218149914819,99cyclictest0-21swapper/107:45:221
21895991455,139cyclictest0-21swapper/1212:00:154
21895991455,139cyclictest0-21swapper/1212:00:154
21895991445,89cyclictest0-21swapper/1210:44:544
21895991435,91cyclictest0-21swapper/1211:25:154
21895991435,91cyclictest0-21swapper/1211:25:154
21895991435,106cyclictest0-21swapper/1211:41:154
21895991435,106cyclictest0-21swapper/1211:41:154
21968991420,85cyclictest0-21swapper/2210:05:4315
21900991420,85cyclictest0-21swapper/1309:25:165
21895991425,101cyclictest0-21swapper/1210:05:224
21968991410,83cyclictest0-21swapper/2211:15:1115
21895991415,118cyclictest0-21swapper/1211:31:084
21895991415,118cyclictest0-21swapper/1211:31:074
21968991400,82cyclictest0-21swapper/2210:35:0615
218149914024,78cyclictest0-21swapper/110:43:351
219039913936,94cyclictest0-21swapper/1412:22:246
219039913936,94cyclictest0-21swapper/1412:22:246
21968991371,81cyclictest0-21swapper/2210:30:1815
21900991370,85cyclictest0-21swapper/1309:32:585
21895991375,99cyclictest10711-21diskmemload10:45:424
21895991375,115cyclictest0-21swapper/1212:35:024
21895991375,115cyclictest0-21swapper/1212:35:024
219689913645,53cyclictest0-21swapper/2211:35:3015
219689913645,53cyclictest0-21swapper/2211:35:3015
219689913628,71cyclictest0-21swapper/2212:30:0115
219689913628,71cyclictest0-21swapper/2212:30:0115
21968991360,81cyclictest0-21swapper/2211:40:1915
21968991360,81cyclictest0-21swapper/2211:40:1815
219399913643,59cyclictest0-21swapper/1810:10:5710
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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