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2026-02-25 - 23:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Feb 25, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1513399260,2cyclictest25099-21sed07:25:170
1513399251,19cyclictest17029-21sed10:05:010
15133992413,6cyclictest2457-21/usr/sbin/munin08:40:140
1513599230,5cyclictest0-21swapper/207:45:532
1513399230,1cyclictest0-21swapper/007:45:150
15133992216,5cyclictest12000-21awk10:50:180
1513399220,2cyclictest31168-21ls08:35:140
1513399220,2cyclictest30813-21expr11:25:130
1513399220,2cyclictest29433-21wc08:30:160
1513399220,2cyclictest29069-21latency_hist07:35:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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