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2026-08-17 - 21:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Aug 17, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13914993324,9cyclictest0-21swapper/109:15:011
13914993029,0cyclictest0-21swapper/112:33:301
1391599282,19cyclictest3986-21H222:10:212
1391599282,19cyclictest3986-21H222:10:212
13914992827,0cyclictest0-21swapper/112:27:001
1391399280,1cyclictest0-21swapper/007:35:130
1391599230,5cyclictest0-21swapper/211:48:512
1391499220,18cyclictest0-21swapper/111:40:251
1391499220,18cyclictest0-21swapper/111:40:251
13913992118,2cyclictest9-21ksoftirqd/010:10:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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