You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-11 - 20:57
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Mar 11, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
692299230,5cyclictest0-21swapper/211:15:182
692199220,11cyclictest0-21swapper/109:25:181
692299214,11cyclictest0-21swapper/208:50:182
692299214,11cyclictest0-21swapper/208:50:182
692299210,3cyclictest0-21swapper/207:39:052
692199210,3cyclictest0-21swapper/111:56:371
692199200,19cyclictest843-21systemd-network08:34:071
692199192,16cyclictest0-21swapper/112:00:121
692099192,16cyclictest24881-21cpuspeed_turbos11:30:120
6920991914,4cyclictest0-21swapper/009:33:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional