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2026-05-20 - 00:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue May 19, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2129299261,24cyclictest0-21swapper/108:27:151
2129299252,20cyclictest19836-21fschecks_time09:00:161
2129299242,21cyclictest22277-21fschecks_time07:10:161
2129299242,21cyclictest11612-21mii-tool12:35:181
2129299232,6cyclictest32411-21chrt09:23:181
2129299232,6cyclictest25667-21chrt12:04:171
21292992312,10cyclictest0-21swapper/108:45:151
2129299230,5cyclictest0-21swapper/112:18:301
2129299230,22cyclictest7936-21latency_hist10:35:001
2129299230,22cyclictest1093-21expr11:20:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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