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2026-07-30 - 17:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Jul 30, 2026 12:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2321099250,1cyclictest0-21swapper/008:35:140
2321299230,22cyclictest0-21swapper/212:15:462
2321299230,22cyclictest0-21swapper/212:15:462
2321199230,5cyclictest0-21swapper/107:54:511
23210992314,5cyclictest0-21swapper/009:50:010
2321299226,15cyclictest0-21swapper/209:34:162
23212992117,3cyclictest3053-21systemd-logind08:54:522
23212992117,3cyclictest3053-21systemd-logind08:54:522
2321099215,15cyclictest0-21swapper/010:50:170
2321299201,18cyclictest31849-21cpuspeed_turbos11:05:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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