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2026-07-09 - 13:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Jul 09, 2026 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3091999233,1cyclictest0-21swapper/022:25:170
3091999232,15cyclictest192572chrt00:31:010
30919992316,2cyclictest21338-21nfsd420:45:180
3091999230,17cyclictest0-21swapper/022:59:270
3091999230,17cyclictest0-21swapper/022:59:270
3091999230,16cyclictest3317-21apache_volume22:10:120
3092899225,16cyclictest4035-21H222:10:212
3092399220,21cyclictest31613-21fschecks_count23:00:141
30919992213,0cyclictest0-21swapper/021:05:140
3091999221,1cyclictest0-21swapper/000:09:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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