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2026-07-12 - 13:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Jul 12, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1728499310,30cyclictest0-21swapper/120:50:131
17289992928,1cyclictest0-21swapper/222:00:172
1727799234,18cyclictest0-21swapper/019:45:200
17277992321,1cyclictest1508-21cron23:30:000
1728999210,20cyclictest843-21systemd-network22:26:512
17277992117,3cyclictest0-21swapper/022:27:260
1727799210,3cyclictest0-21swapper/019:53:080
1727799210,16cyclictest8013-21grep23:40:120
17289992018,1cyclictest0-21swapper/221:38:502
1728999200,3cyclictest3987-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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