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2026-04-04 - 09:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Apr 04, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1952899350,24cyclictest0-21swapper/120:33:261
1952399220,3cyclictest0-21swapper/000:34:340
1952899215,9cyclictest0-21swapper/122:49:471
1952899214,16cyclictest6213-21idleruntime23:30:151
19528992118,2cyclictest880-21rs:main1
19531992017,2cyclictest18746-21cpuspeed_turbos20:05:152
19531992014,5cyclictest0-21swapper/220:04:382
19523992017,2cyclictest4099-21H222:10:210
1952399200,19cyclictest426-21systemd-udevd19:24:520
1952399200,19cyclictest426-21systemd-udevd19:12:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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