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2026-01-17 - 12:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Jan 17, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2757999234,17cyclictest14644-21cat00:30:122
2757999225,16cyclictest15644-21expr23:35:142
27579992219,2cyclictest21104-21cut22:45:162
27579992219,2cyclictest18498-21ntpq22:40:172
27579992218,3cyclictest26978-21tr23:55:122
27579992218,3cyclictest26686-21cut20:05:132
27578992213,0cyclictest0-21swapper/100:25:181
2757799220,4cyclictest0-21swapper/022:52:360
2757799220,21cyclictest843-21systemd-network20:30:160
2757999214,2cyclictest3802-21expr00:10:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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