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2026-04-24 - 07:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Apr 24, 2026 00:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13604992410,1cyclictest0-21swapper/023:55:170
1360499220,4cyclictest0-21swapper/021:14:020
1361399210,3cyclictest0-21swapper/200:40:012
13613991914,4cyclictest0-21swapper/220:00:162
13613991914,2cyclictest2005-21fschecks_time00:30:142
1361399190,17cyclictest4035-21H222:10:212
1360899192,1cyclictest0-21swapper/120:36:071
1360899192,16cyclictest32502-21wc20:40:131
1360499193,15cyclictest0-21swapper/020:46:400
13604991917,1cyclictest0-21swapper/020:32:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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