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2026-11-11 - 01:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Nov 10, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2098899230,18cyclictest0-21swapper/210:20:212
2098499235,17cyclictest1107-21apache_accesses12:35:111
20979992113,4cyclictest0-21swapper/008:45:280
20988992017,2cyclictest3981-21H222:10:212
2098499204,15cyclictest0-21swapper/107:26:241
20984992017,1cyclictest0-21swapper/111:20:161
2097999204,15cyclictest0-21swapper/012:20:260
2097999204,15cyclictest0-21swapper/012:20:250
20979992017,2cyclictest455-21plymouthd10:30:120
2098899192,16cyclictest0-21swapper/207:18:482
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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