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2026-03-03 - 15:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Mar 03, 2026 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18108992914,14cyclictest0-21swapper/112:30:171
18108992914,14cyclictest0-21swapper/112:30:161
1811299220,18cyclictest0-21swapper/207:11:092
1811299213,13cyclictest20313-21latency_hist08:10:012
18112992116,4cyclictest20563-21needreboot10:00:172
1811299210,5cyclictest0-21swapper/209:12:112
18112992016,3cyclictest0-21swapper/209:15:472
18112991917,1cyclictest0-21swapper/209:50:172
18112991917,1cyclictest0-21swapper/209:50:172
18112991910,5cyclictest0-21swapper/207:25:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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