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2026-06-30 - 11:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Jun 30, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10023993331,2cyclictest0-21swapper/019:30:160
10033992617,9cyclictest0-21swapper/223:26:412
10033992414,0cyclictest0-21swapper/200:20:172
1002399230,0cyclictest0-21swapper/023:50:160
10033992119,1cyclictest19047-21apache_processe00:10:152
1002999215,15cyclictest21-21ksoftirqd/119:24:421
1002999215,15cyclictest21-21ksoftirqd/119:24:421
10029992115,3cyclictest0-21swapper/123:10:011
1002999210,0cyclictest0-21swapper/123:53:591
10033992020,0cyclictest0-21swapper/221:03:332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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