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2025-11-09 - 09:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Nov 09, 2025 00:45:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1318399252,16cyclictest21801-21cpu20:20:152
13183992512,4cyclictest0-21swapper/220:08:312
13183992422,2cyclictest0-21swapper/221:16:532
13183992420,2cyclictest24016-21kworker/u16:119:11:042
1318399240,16cyclictest28237-21cat20:30:192
1318399233,1cyclictest0-21swapper/219:59:272
13183992323,0cyclictest0-21swapper/219:42:402
13183992317,5cyclictest1104-21lldpd22:53:122
13183992317,5cyclictest0-21swapper/200:30:482
1318399230,22cyclictest0-21swapper/220:35:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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