You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-19 - 01:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Jan 18, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19020992610,15cyclictest12653-21ls10:00:011
1901699252,1cyclictest0-21swapper/011:15:310
19016992517,2cyclictest1765-21cat10:35:220
1902699230,5cyclictest0-21swapper/212:10:012
1902099230,5cyclictest0-21swapper/109:13:021
1902699210,18cyclictest0-21swapper/208:05:112
1902099212,18cyclictest0-21swapper/112:10:181
1902099211,17cyclictest0-21swapper/107:44:441
1901699210,2cyclictest3985-21H222:10:210
1902699202,17cyclictest13749-21perf09:05:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional