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2026-04-02 - 07:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Apr 02, 2026 00:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1617999254,20cyclictest0-21swapper/221:46:382
1617999254,20cyclictest0-21swapper/221:46:372
1617599253,16cyclictest20545-21kernelversion19:15:161
1617999240,1cyclictest22021-21kernelversion22:10:172
1617999240,1cyclictest22021-21kernelversion22:10:172
1617599240,19cyclictest0-21swapper/122:25:211
1617999233,1cyclictest0-21swapper/223:24:562
1617999230,5cyclictest0-21swapper/222:19:522
1617999230,5cyclictest0-21swapper/220:34:222
1617599236,16cyclictest0-21swapper/119:10:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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