You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-23 - 16:13
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Mar 23, 2026 12:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1473499225,11cyclictest0-21swapper/211:20:022
1473499224,10cyclictest0-21swapper/210:44:592
1473499220,4cyclictest0-21swapper/211:25:202
1473499202,15cyclictest0-21swapper/208:07:462
14734992013,2cyclictest17763-21cpuspeed_turbos11:00:122
14734992010,0cyclictest0-21swapper/208:10:142
14733992013,6cyclictest24985-21grep12:10:121
1473399200,18cyclictest7309-21grep10:40:151
1473399200,17cyclictest0-21swapper/108:40:001
1473499190,16cyclictest0-21swapper/210:56:292
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional