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2026-03-09 - 18:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Mar 09, 2026 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9043993129,0cyclictest0-21swapper/010:00:150
9043993129,0cyclictest0-21swapper/010:00:150
905699220,18cyclictest0-21swapper/208:02:392
9052992213,0cyclictest0-21swapper/110:40:441
904399226,14cyclictest0-21swapper/011:52:200
904399220,18cyclictest0-21swapper/010:30:130
9043992121,0cyclictest0-21swapper/011:05:140
9043992121,0cyclictest0-21swapper/008:30:130
905699203,1cyclictest0-21swapper/209:12:392
905699202,17cyclictest0-21swapper/211:42:402
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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