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2026-01-24 - 15:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Jan 24, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27489992311,8cyclictest9-21ksoftirqd/012:29:590
2748999220,21cyclictest870-21systemd-logind09:38:510
2749199210,20cyclictest399-20systemd-journal08:41:362
2749199210,20cyclictest399-20systemd-journal08:41:362
2749099210,3cyclictest0-21swapper/108:11:081
2749099210,1cyclictest0-21swapper/112:20:001
27489992112,6cyclictest27441-21tr10:00:140
27491992017,2cyclictest1476-21snapd07:40:182
2748999204,15cyclictest3991-21H222:10:210
2749199193,2cyclictest3983-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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