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2026-01-07 - 01:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Jan 06, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3070699233,19cyclictest29519-21awk10:00:002
3069699230,8cyclictest32759-21sed11:00:210
3069699230,5cyclictest32243-21latency_hist10:05:000
3069699230,22cyclictest9196-21ls11:15:190
3069699230,22cyclictest25157-21latency_hist08:55:010
3069699230,22cyclictest2007-21systemd-journal12:39:160
3069699230,22cyclictest11862-21systemctl09:25:220
3070699226,15cyclictest0-21swapper/210:23:462
3069699222,19cyclictest28912-21timerandwakeup11:50:200
30696992214,7cyclictest3987-21H222:10:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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