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2025-10-18 - 19:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Oct 18, 2025 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1159699248,16cyclictest16728-21kworker/2:012:38:122
1159499240,18cyclictest0-21swapper/011:45:010
1159699222,13cyclictest26715-21apt-key11:25:012
1159699203,11cyclictest0-21swapper/211:50:002
1159499206,13cyclictest0-21swapper/007:39:380
11594992018,1cyclictest0-21swapper/010:30:220
11596991917,1cyclictest28-21ksoftirqd/207:11:572
11596991917,1cyclictest0-21swapper/212:17:492
11596991917,1cyclictest0-21swapper/208:35:392
11596991914,4cyclictest0-21swapper/210:42:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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