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2026-10-25 - 01:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Oct 24, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22516992319,3cyclictest10249-21php7.009:39:002
2251699230,5cyclictest0-21swapper/209:55:542
2251499225,8cyclictest0-21swapper/108:14:091
22512992219,2cyclictest1856-21systemd-udevd11:00:510
22516992018,1cyclictest0-21swapper/210:40:192
22514992018,1cyclictest21-21ksoftirqd/110:01:591
2251299204,9cyclictest0-21swapper/009:29:180
2251299202,3cyclictest0-21swapper/012:09:370
2251299202,3cyclictest0-21swapper/012:09:360
2251299200,14cyclictest0-21swapper/012:20:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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