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2026-04-30 - 23:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Apr 30, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20481993028,2cyclictest0-21swapper/111:00:011
2048199235,2cyclictest0-21swapper/112:20:151
2048199230,18cyclictest0-21swapper/107:57:041
20480992117,3cyclictest0-21swapper/007:15:020
2048199204,15cyclictest12192-21tr11:35:141
20481992017,2cyclictest20331-21ntp_kernel_pll_10:00:191
2048199200,16cyclictest4099-21H222:10:211
2048299193,2cyclictest12962-21cut10:40:002
2048299192,1cyclictest3983-21H222:10:212
2048299192,1cyclictest3983-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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