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2026-04-25 - 08:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Apr 25, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1540299230,22cyclictest870-21systemd-logind00:08:521
15403992114,6cyclictest843-21systemd-network21:37:422
15402992113,7cyclictest870-21systemd-logind22:28:521
1540199213,15cyclictest0-21swapper/021:04:570
1540399202,1cyclictest0-21swapper/223:10:172
1540399200,19cyclictest0-21swapper/223:47:252
15402992015,4cyclictest3211-21JS22:10:211
1540199200,5cyclictest0-21swapper/020:11:560
15403991917,1cyclictest0-21swapper/200:30:192
1540399190,18cyclictest3982-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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