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2026-03-22 - 18:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Mar 22, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11695992323,0cyclictest0-21swapper/212:05:162
1169599230,5cyclictest0-21swapper/212:23:502
11690992314,0cyclictest0-21swapper/110:59:011
1169099230,6cyclictest9938-21awk11:49:591
1169099230,22cyclictest0-21swapper/112:31:091
1169599223,13cyclictest20424-21munin-run08:20:002
11695992219,2cyclictest0-21swapper/207:40:162
1169599202,17cyclictest22727-21nfsd412:10:182
11695992012,4cyclictest0-21swapper/209:40:432
11690992016,1cyclictest0-21swapper/107:31:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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