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2026-11-05 - 00:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Nov 04, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2047599270,26cyclictest14550-21snapd12:10:071
20475992220,1cyclictest16704-21awk08:55:191
20475992213,0cyclictest0-21swapper/108:07:031
20476992111,5cyclictest0-21swapper/212:10:502
2047499212,16cyclictest0-21swapper/007:24:390
20474992113,3cyclictest0-21swapper/009:05:010
2047499210,20cyclictest0-21swapper/012:39:590
2047699201,13cyclictest0-21swapper/210:12:302
2047699200,2cyclictest16100-21fschecks_count08:55:152
20474992018,1cyclictest0-21swapper/010:29:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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