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2026-05-15 - 20:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri May 15, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3132899281,17cyclictest0-21swapper/110:40:141
31327992624,1cyclictest1100-21snmpd08:22:370
31328992514,10cyclictest0-21swapper/111:10:151
3132999233,11cyclictest3415-21python308:15:012
3132899230,5cyclictest0-21swapper/108:20:011
3132999210,19cyclictest0-21swapper/209:15:172
31328992119,1cyclictest0-21swapper/112:30:141
31328992117,3cyclictest0-21swapper/110:46:141
31328992114,3cyclictest0-21swapper/107:49:301
31328992113,4cyclictest0-21swapper/110:39:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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