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2026-06-21 - 10:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Jun 21, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23203992313,10cyclictest0-21swapper/122:30:201
23204992113,4cyclictest0-21swapper/222:18:252
23203992114,4cyclictest11330-21grep00:30:131
2320299215,15cyclictest0-21swapper/022:45:140
2320499204,2cyclictest3983-21H222:10:212
23204992018,1cyclictest0-21swapper/219:35:002
2320299205,11cyclictest0-21swapper/020:25:000
2320299204,15cyclictest1100-21snmpd22:03:470
23202992015,4cyclictest12463-21nfsd400:30:180
2320299200,18cyclictest0-21swapper/021:55:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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