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2026-01-11 - 00:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Jan 10, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2726999220,4cyclictest0-21swapper/010:21:270
2726999220,4cyclictest0-21swapper/007:40:050
2726999220,21cyclictest843-21systemd-network11:16:020
2726999220,21cyclictest843-21systemd-network11:16:020
2727399210,16cyclictest2926-21sessionclean12:09:002
2727399204,15cyclictest4035-21H222:10:212
2727399204,15cyclictest4035-21H222:10:212
2727399204,15cyclictest28-21ksoftirqd/211:51:312
2727399202,11cyclictest10728-21perf10:30:002
27273992017,2cyclictest27106-21switchtime09:00:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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