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2026-03-10 - 06:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Mar 10, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2276499262,18cyclictest3450-21gsd-color20:10:000
2276499260,5cyclictest0-21swapper/020:15:030
22765992423,0cyclictest0-21swapper/121:30:141
22766992313,5cyclictest0-21swapper/221:00:172
22765992220,1cyclictest12135-21mii-tool23:35:141
22765992212,0cyclictest0-21swapper/100:14:011
2276499223,1cyclictest0-21swapper/021:25:190
2276499221,2cyclictest24541-21chrt23:57:490
2276499221,1cyclictest44402sleep000:15:510
2276499220,1cyclictest0-21swapper/020:24:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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