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2026-05-01 - 13:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri May 01, 2026 00:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
736399263,18cyclictest0-21swapper/021:45:010
7364992321,1cyclictest0-21swapper/119:50:151
736499220,21cyclictest0-21swapper/121:45:201
736399220,4cyclictest0-21swapper/022:30:190
736499214,2cyclictest22280-21munin-run23:25:001
7364992118,2cyclictest2069-21systemd-udevd23:18:511
736399210,4cyclictest0-21swapper/020:20:010
7365992017,2cyclictest4035-21H222:10:212
7365992015,4cyclictest0-21swapper/220:30:362
7364992018,1cyclictest0-21swapper/123:45:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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