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2026-05-28 - 07:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu May 28, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16504992928,1cyclictest0-21swapper/200:00:122
1650099288,5cyclictest47252chrt21:35:521
1650099270,6cyclictest0-21swapper/119:17:081
1650099240,2cyclictest28526-21nfsd420:25:161
1650099240,22cyclictest0-21swapper/123:10:161
1650099240,18cyclictest12908-21sort22:50:141
1650099232,1cyclictest0-21swapper/122:56:221
1650099232,15cyclictest189822chrt23:56:491
16500992314,8cyclictest5660-21dpkg21:40:111
16500992313,8cyclictest4266-21needreboot23:30:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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