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2025-09-16 - 14:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Sep 16, 2025 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12318992717,10cyclictest0-21swapper/219:47:412
12308992724,2cyclictest4456-21mii-tool00:35:170
12313992424,0cyclictest28314-21mii-tool00:20:161
12313992421,2cyclictest14352-21mii-tool23:55:161
1231899230,5cyclictest0-21swapper/223:09:582
1231399220,4cyclictest0-21swapper/121:02:061
1231899210,20cyclictest823-21systemd-network00:01:172
12313992121,0cyclictest0-21swapper/121:30:011
12313992119,1cyclictest9600-21cat21:55:011
12313992117,3cyclictest0-21swapper/120:00:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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