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2025-11-29 - 18:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Nov 29, 2025 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
631399242,18cyclictest0-21swapper/007:30:010
6319992322,0cyclictest0-21swapper/107:50:191
631999220,4cyclictest0-21swapper/110:35:131
631999220,18cyclictest0-21swapper/110:16:541
632199214,14cyclictest0-21swapper/210:34:102
632199210,20cyclictest893-21systemd-logind08:44:082
631999202,3cyclictest4530-21H212:26:331
6319992014,3cyclictest0-21swapper/110:20:161
632199194,1cyclictest0-21swapper/211:36:162
632199194,11cyclictest26671-21perf09:40:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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