You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-27 - 14:19
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Mar 27, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1025992214,5cyclictest0-21swapper/221:10:172
102599210,4cyclictest13582-21cstates23:40:142
1019992017,2cyclictest1652-21expr19:10:131
1015992017,2cyclictest3053-21systemd-logind20:08:520
1015992012,4cyclictest0-21swapper/022:50:140
102599192,16cyclictest0-21swapper/223:07:002
1025991914,3cyclictest0-21swapper/200:20:272
102599190,16cyclictest4035-21H222:10:212
101999193,1cyclictest17785-21timerandwakeup23:45:211
101999190,16cyclictest32534-21tr20:05:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional