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2026-07-15 - 13:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jul 15, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1487999230,20cyclictest0-21swapper/122:04:291
14879992212,7cyclictest0-21swapper/119:55:181
14878992214,4cyclictest0-21swapper/020:56:120
14880992119,1cyclictest28-21ksoftirqd/200:25:282
1487999210,20cyclictest0-21swapper/100:35:201
1487899211,3cyclictest0-21swapper/019:35:470
1488099202,17cyclictest0-21swapper/223:07:252
1488099202,17cyclictest0-21swapper/200:15:412
1488099200,3cyclictest0-21swapper/222:10:212
1488099200,19cyclictest0-21swapper/222:00:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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