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2026-01-01 - 07:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Jan 01, 2026 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21695992422,2cyclictest0-21swapper/123:30:171
2169999226,15cyclictest0-21swapper/220:21:162
2169599227,14cyclictest0-21swapper/121:31:241
2169599210,19cyclictest9975-21fschecks_time00:35:161
2169499210,18cyclictest0-21swapper/022:55:340
21699992016,3cyclictest0-21swapper/219:17:442
2169999200,19cyclictest0-21swapper/200:00:012
2169599207,11cyclictest12130-21cut20:45:191
2169599207,11cyclictest12130-21cut20:45:181
21695992016,3cyclictest23369-21munin-run00:00:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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