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2026-06-03 - 07:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jun 03, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
976999264,1cyclictest0-21swapper/020:16:170
976999252,5cyclictest0-21swapper/021:30:000
977999240,7cyclictest0-21swapper/222:01:112
977399240,23cyclictest3305-21fschecks_count20:05:181
976999242,1cyclictest0-21swapper/023:59:300
976999230,3cyclictest23099-21python321:40:010
977999226,15cyclictest19143-21ntp_kernel_err23:25:182
977999210,20cyclictest0-21swapper/221:51:422
976999216,14cyclictest0-21swapper/019:35:150
9779992018,1cyclictest0-21swapper/220:20:362
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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