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2026-04-23 - 03:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Apr 23, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14837992414,5cyclictest0-21swapper/220:50:212
1483799240,19cyclictest0-21swapper/221:50:152
14837992119,1cyclictest28258-21date20:30:002
14837992119,1cyclictest0-21swapper/221:40:182
14837992116,4cyclictest0-21swapper/223:00:482
14837992018,1cyclictest28-21ksoftirqd/219:11:072
1483799200,19cyclictest426-21systemd-udevd22:50:512
1483599204,14cyclictest0-21swapper/020:05:380
1483599203,16cyclictest0-21swapper/000:29:130
14835992017,1cyclictest0-21swapper/022:15:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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