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2026-01-13 - 09:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Jan 13, 2026 00:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23612992321,1cyclictest0-21swapper/021:15:190
2361299230,23cyclictest0-21swapper/019:10:160
2361299225,2cyclictest3991-21H222:10:210
23612992221,1cyclictest7983-21mii-tool21:35:140
23619992117,3cyclictest0-21swapper/219:30:142
23619992117,3cyclictest0-21swapper/219:30:132
23619992113,4cyclictest0-21swapper/223:34:172
2361799213,17cyclictest0-21swapper/119:22:511
23617992114,3cyclictest0-21swapper/121:43:161
2361299214,16cyclictest0-21swapper/021:15:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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