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2026-03-06 - 23:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Mar 06, 2026 12:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
611799242,18cyclictest0-21swapper/008:35:010
6129992112,8cyclictest0-21swapper/208:00:152
612499210,3cyclictest0-21swapper/109:50:171
6124992018,1cyclictest9788-21mii-tool12:00:161
611799200,18cyclictest0-21swapper/011:28:450
612999194,1cyclictest0-21swapper/211:51:142
612999193,15cyclictest0-21swapper/207:46:552
612999192,11cyclictest4585-21perf10:00:012
6129991916,2cyclictest17330-21needreboot08:25:172
612499193,9cyclictest27648-21perf10:39:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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