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2026-04-07 - 07:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Apr 07, 2026 00:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2463499340,34cyclictest0-21swapper/221:10:152
2463499260,25cyclictest0-21swapper/219:50:012
2463499244,13cyclictest30074-21python319:20:002
2463499244,13cyclictest30074-21python319:20:002
2463499230,20cyclictest0-21swapper/222:41:042
24632992314,8cyclictest4593-21nvmesmart_nvme022:20:200
2463299230,17cyclictest0-21swapper/021:40:180
2463299230,16cyclictest8560-21ls23:25:170
2463399223,18cyclictest0-21swapper/121:20:011
2463399220,21cyclictest843-21systemd-network21:12:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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