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2026-02-10 - 18:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Feb 10, 2026 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2788799350,34cyclictest0-21swapper/010:10:130
27888993222,9cyclictest0-21swapper/109:35:011
27888993222,9cyclictest0-21swapper/109:35:011
2788999214,16cyclictest0-21swapper/208:40:182
27888992121,0cyclictest0-21swapper/107:25:151
2788899210,20cyclictest870-21systemd-logind10:16:521
2788999203,2cyclictest14408-21python308:40:012
2788899200,19cyclictest426-21systemd-udevd09:08:511
27887992014,3cyclictest29179-21needreboot10:00:170
2788999193,15cyclictest4644-21latency08:20:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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