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2026-02-15 - 22:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Feb 15, 2026 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3265399230,5cyclictest0-21swapper/010:04:060
32654992115,4cyclictest10270-21fschecks_count12:10:121
32653992117,3cyclictest0-21swapper/009:27:300
3265399204,1cyclictest0-21swapper/009:42:280
32660991917,1cyclictest0-21swapper/211:50:112
32660991915,3cyclictest13029-21munin-plugin-st09:25:012
32660991915,3cyclictest13029-21munin-plugin-st09:25:002
3266099190,18cyclictest0-21swapper/207:45:132
32654991916,2cyclictest16828-21ntp_offset07:35:201
32654991916,2cyclictest16828-21ntp_offset07:35:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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