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2026-08-08 - 19:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Aug 08, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
365299230,22cyclictest0-21swapper/209:40:182
365299220,21cyclictest843-21systemd-network09:34:582
3648992219,2cyclictest4262-21grep10:00:171
3648992113,0cyclictest0-21swapper/107:47:551
364899203,16cyclictest7603-21fschecks_count12:00:161
364899203,16cyclictest7603-21fschecks_count12:00:151
364899203,16cyclictest11648-21cat08:20:181
364899202,3cyclictest24253-21expr12:30:141
364899200,19cyclictest22352-21tr08:40:141
364899200,18cyclictest399-20systemd-journal10:35:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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