You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-12-02 - 18:38
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Dec 02, 2025 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273199250,19cyclictest0-21swapper/007:50:010
32731992414,5cyclictest0-21swapper/010:50:000
32731992311,7cyclictest0-21swapper/012:20:190
3273299224,17cyclictest0-21swapper/111:27:221
32732992214,4cyclictest0-21swapper/108:45:191
32731992213,4cyclictest0-21swapper/009:00:320
3273199220,4cyclictest0-21swapper/009:18:580
32733992121,0cyclictest0-21swapper/208:25:162
32733992118,2cyclictest573-21mii-tool08:05:192
32733992112,5cyclictest0-21swapper/210:05:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional