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2026-01-20 - 02:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Jan 19, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2364099350,0cyclictest0-21swapper/011:30:150
23640992814,0cyclictest0-21swapper/008:39:220
2364299241,15cyclictest0-21swapper/210:55:082
2364299230,5cyclictest0-21swapper/208:17:252
2364199230,5cyclictest0-21swapper/110:46:531
23640992213,0cyclictest0-21swapper/008:55:170
2364099220,18cyclictest0-21swapper/010:25:060
23642992117,3cyclictest0-21swapper/211:13:132
23642992013,6cyclictest843-21systemd-network11:21:452
2364299200,19cyclictest0-21swapper/209:36:462
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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