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2026-03-16 - 03:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Mar 16, 2026 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
616499230,22cyclictest0-21swapper/023:51:460
616699212,3cyclictest0-21swapper/200:35:002
616599206,13cyclictest0-21swapper/120:16:591
6164992016,3cyclictest3732-21sed22:55:000
616699190,17cyclictest0-21swapper/221:29:342
6165991917,1cyclictest21-21ksoftirqd/123:07:111
616599190,4cyclictest32737-21taskset20:54:041
616599190,18cyclictest0-21swapper/100:18:071
616599190,0cyclictest0-21swapper/120:55:101
6164991914,3cyclictest0-21swapper/020:26:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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