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2026-07-27 - 16:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Jul 27, 2026 12:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
724299345,16cyclictest0-21swapper/009:55:540
7251992414,5cyclictest0-21swapper/208:30:142
725199230,5cyclictest0-21swapper/211:44:292
724699230,5cyclictest0-21swapper/111:10:241
724699230,5cyclictest0-21swapper/109:01:371
7246992222,0cyclictest0-21swapper/108:45:211
7246992213,5cyclictest0-21swapper/110:15:181
724299220,18cyclictest0-21swapper/009:20:510
724299220,18cyclictest0-21swapper/009:20:510
725199210,18cyclictest0-21swapper/210:35:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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