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2026-01-12 - 23:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Jan 12, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4629992422,1cyclictest21-21ksoftirqd/107:45:021
4629992119,1cyclictest0-21swapper/108:46:171
462999203,16cyclictest0-21swapper/112:00:001
462999200,19cyclictest0-21swapper/110:03:571
462899203,16cyclictest32052-21timerwakeupswit07:55:210
462899200,16cyclictest0-21swapper/010:45:130
463099192,16cyclictest17156-21smtpd12:19:202
4630991917,1cyclictest0-21swapper/210:06:142
4630991916,2cyclictest0-21swapper/209:35:432
463099191,17cyclictest7497-21nfsd409:05:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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