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2026-08-14 - 20:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Aug 14, 2026 12:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28121993331,2cyclictest0-21swapper/112:05:211
28121993129,2cyclictest0-21swapper/110:00:131
28121993029,0cyclictest0-21swapper/108:45:191
28121993028,2cyclictest0-21swapper/112:28:291
28121992827,0cyclictest0-21swapper/107:35:401
28121992617,0cyclictest0-21swapper/112:13:331
2812199250,20cyclictest13273-21wc07:40:121
2812399240,11cyclictest0-21swapper/212:39:262
2812099244,11cyclictest12924-21sed09:35:020
2812399222,17cyclictest0-21swapper/208:30:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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