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2026-06-24 - 10:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jun 24, 2026 00:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23738993433,1cyclictest0-21swapper/123:05:571
23738993432,2cyclictest0-21swapper/123:10:111
23738993432,2cyclictest0-21swapper/121:42:071
23738993332,1cyclictest0-21swapper/123:35:121
23738993129,2cyclictest0-21swapper/122:45:231
23738993129,2cyclictest0-21swapper/121:24:271
23738993129,0cyclictest0-21swapper/121:38:271
23738993028,2cyclictest0-21swapper/122:35:551
23738993028,2cyclictest0-21swapper/122:13:311
23738992929,0cyclictest0-21swapper/122:19:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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