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2025-11-12 - 11:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Nov 12, 2025 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
538799214,6cyclictest0-21swapper/223:20:172
538599212,18cyclictest0-21swapper/022:45:440
5385992119,1cyclictest9-21ksoftirqd/020:02:340
5385992113,4cyclictest0-21swapper/021:50:160
538699200,18cyclictest414-20systemd-journal00:38:591
538599202,17cyclictest0-21swapper/022:55:010
538599200,4cyclictest16237-21grep21:25:010
538799193,15cyclictest24060-21readlink00:25:232
538799193,15cyclictest0-21swapper/223:31:112
538799193,10cyclictest15220-21python322:20:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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