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2026-03-09 - 08:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Mar 09, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2360999273,19cyclictest0-21swapper/022:35:010
2361499230,7cyclictest0-21swapper/122:10:161
2361499230,5cyclictest0-21swapper/120:20:011
23614992211,6cyclictest29565-21cpuspeed_turbos19:20:121
2361899200,19cyclictest399-20systemd-journal00:05:012
2361499200,17cyclictest0-21swapper/121:14:541
23609992014,3cyclictest0-21swapper/023:13:050
23609992013,4cyclictest9560-21munin-run00:30:010
23618991915,1cyclictest0-21swapper/200:05:142
2361899190,16cyclictest3987-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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