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2026-02-14 - 22:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Feb 14, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3159199262,15cyclictest0-21swapper/211:15:192
3159199240,23cyclictest1785-21fschecks_time08:10:152
31591992117,3cyclictest0-21swapper/210:09:062
31591992117,3cyclictest0-21swapper/207:18:312
31591992115,5cyclictest10777-21perf09:25:002
31591992114,3cyclictest0-21swapper/211:04:402
3159199204,15cyclictest0-21swapper/210:04:422
31591992016,3cyclictest0-21swapper/207:58:112
3159099201,18cyclictest18607-21cpuspeed_turbos08:40:141
3159199192,1cyclictest0-21swapper/209:44:072
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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