You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-26 - 04:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Jan 26, 2026 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1307899260,25cyclictest0-21swapper/120:10:291
1307899254,20cyclictest0-21swapper/122:50:191
1307899245,13cyclictest0-21swapper/120:58:101
1307899240,5cyclictest0-21swapper/119:52:111
1307899232,15cyclictest211022chrt19:24:121
1307899231,2cyclictest28504-21sh00:16:591
1307899230,22cyclictest26407-21cat20:30:011
1307799230,5cyclictest0-21swapper/020:19:570
13078992215,6cyclictest0-21swapper/100:35:231
13078992213,8cyclictest32426-21timerandwakeup23:25:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional