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2026-04-24 - 19:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Apr 24, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3108499246,17cyclictest0-21swapper/212:29:592
31083992415,9cyclictest1964-21kworker/1:112:08:561
3108499230,22cyclictest0-21swapper/211:10:262
3108399220,21cyclictest843-21systemd-network10:47:271
31084992119,1cyclictest28-21ksoftirqd/210:24:282
3108499200,19cyclictest426-21systemd-udevd09:24:522
3108299203,3cyclictest0-21swapper/009:22:360
3108499190,18cyclictest25362-21nfsd410:45:162
3108499190,18cyclictest0-21swapper/209:04:522
31083991916,2cyclictest31862-21anacron09:03:451
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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