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2026-04-17 - 09:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Apr 17, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2401199260,25cyclictest0-21swapper/120:20:151
2400699252,18cyclictest0-21swapper/000:30:000
2400699252,18cyclictest0-21swapper/000:29:590
2401199210,3cyclictest0-21swapper/120:51:131
2401599200,17cyclictest0-21swapper/220:29:272
2401199204,1cyclictest0-21swapper/121:10:131
2401199202,3cyclictest0-21swapper/100:10:221
2401199202,17cyclictest0-21swapper/123:47:261
24011992016,3cyclictest0-21swapper/123:56:071
24006992016,3cyclictest9-21ksoftirqd/021:20:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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