You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-09-02 - 03:55
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Sep 02, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
521999310,18cyclictest0-21swapper/121:10:271
522399220,18cyclictest0-21swapper/223:45:082
521999220,4cyclictest0-21swapper/123:10:301
521999220,4cyclictest0-21swapper/123:10:301
522399204,15cyclictest0-21swapper/220:15:562
522399201,2cyclictest31313-21nvmesmart_nvme020:50:182
5219992017,2cyclictest0-21swapper/121:33:551
521999200,19cyclictest426-21systemd-udevd19:20:521
521999200,19cyclictest426-21systemd-udevd19:20:521
522399193,15cyclictest22142-21sensors_temp00:20:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional