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2026-10-31 - 00:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Oct 30, 2026 12:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1209299354,23cyclictest0-21swapper/210:05:012
12092992525,0cyclictest23347-21mii-tool08:25:162
1209299246,15cyclictest0-21swapper/210:55:072
1207999230,18cyclictest0-21swapper/011:14:460
1207999220,4cyclictest0-21swapper/011:23:430
1209299210,6cyclictest1947-21grep08:45:142
1208599210,19cyclictest15892-21snapd09:50:051
1209299204,15cyclictest0-21swapper/210:47:412
1209299204,15cyclictest0-21swapper/209:14:102
1209299202,16cyclictest3979-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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