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2026-03-10 - 22:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Mar 10, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
742199220,18cyclictest0-21swapper/212:05:102
7416992214,7cyclictest843-21systemd-network08:33:171
742199214,11cyclictest3650-21munin-run09:55:012
741299219,11cyclictest0-21swapper/012:34:160
741299210,20cyclictest843-21systemd-network11:03:120
742199203,11cyclictest0-21swapper/212:14:132
742199202,17cyclictest0-21swapper/211:12:162
7416992016,1cyclictest0-21swapper/109:25:181
741699197,11cyclictest0-21swapper/111:54:121
741699197,11cyclictest0-21swapper/111:54:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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