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2026-03-26 - 18:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System (updated Thu Mar 26, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19177993524,0cyclictest0-21swapper/111:04:401
1917399263,19cyclictest3020-21sed11:25:000
1917799230,20cyclictest29616-21cron11:15:001
19173992323,0cyclictest29678-21mii-tool12:10:150
1917399220,6cyclictest6598-21tr08:40:120
1918299217,13cyclictest0-21swapper/207:19:392
1918299210,5cyclictest28-21ksoftirqd/210:14:212
1917799210,1cyclictest111rcu_preempt09:21:421
19173992116,5cyclictest0-21swapper/009:55:000
1917399210,20cyclictest0-21swapper/010:10:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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