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2026-05-09 - 17:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat May 09, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
972999230,18cyclictest0-21swapper/108:40:011
973399212,16cyclictest0-21swapper/211:20:012
9733992117,3cyclictest0-21swapper/210:02:162
973399202,17cyclictest0-21swapper/212:20:142
9724992018,1cyclictest0-21swapper/011:15:130
9724992017,2cyclictest14499-21snapd08:25:350
9733991916,2cyclictest20146-21needreboot09:20:182
973399190,2cyclictest4035-21H222:10:212
973399190,2cyclictest3983-21H222:10:212
973399190,17cyclictest3981-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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