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2026-09-17 - 06:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Sep 16, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2787699241,5cyclictest0-21swapper/110:15:011
2788199234,18cyclictest28-21ksoftirqd/208:34:432
27876992314,8cyclictest23141-21ntpq07:55:181
2787699230,2cyclictest30613-21fschecks_count09:05:131
2787699230,22cyclictest835-21perf07:20:011
2787699230,22cyclictest17561-21awk07:45:171
2787699230,21cyclictest2956-21latency_hist11:10:001
2787699230,1cyclictest0-21swapper/112:25:141
27876992213,8cyclictest10229-21perf10:25:001
2787699221,20cyclictest18733-21nfsd409:40:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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