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2026-01-25 - 15:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Jan 25, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2913199240,23cyclictest870-21systemd-logind08:26:522
2913099231,21cyclictest26724-21df09:55:141
29129992320,2cyclictest26616-21tlsmgr07:18:550
29129992314,6cyclictest0-21swapper/008:39:090
2913199220,21cyclictest870-21systemd-logind11:23:512
29130992216,5cyclictest14307-21basename12:25:011
29130992215,6cyclictest31749-21munin-run07:15:011
29130992214,7cyclictest29341-21expr10:00:161
29130992213,5cyclictest0-21swapper/111:37:481
2913099221,16cyclictest23083-21sed09:50:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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