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2026-02-09 - 05:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Feb 09, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1419899223,18cyclictest0-21swapper/121:15:131
1419299227,14cyclictest0-21swapper/021:47:020
14192992220,1cyclictest9-21ksoftirqd/022:35:490
1419299210,21cyclictest0-21swapper/022:10:030
1419299210,18cyclictest0-21swapper/023:27:030
14203992013,3cyclictest0-21swapper/219:17:182
1420399200,17cyclictest0-21swapper/220:35:132
1419899204,15cyclictest29418-21latency_hist22:30:001
14203991916,2cyclictest3991-21H222:10:212
1420399191,3cyclictest3937-21java21:05:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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