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2025-11-02 - 08:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Nov 02, 2025 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1917999240,23cyclictest0-21swapper/222:05:582
1917999230,20cyclictest0-21swapper/223:35:062
1917699230,5cyclictest0-21swapper/020:27:290
1917699210,20cyclictest823-21systemd-network20:09:000
1917799204,15cyclictest0-21swapper/121:25:461
19177992020,0cyclictest0-21swapper/120:14:451
1917699204,15cyclictest0-21swapper/021:24:330
19179991917,1cyclictest0-21swapper/223:32:332
19177991917,1cyclictest0-21swapper/100:20:131
19177991917,1cyclictest0-21swapper/100:10:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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