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2026-04-29 - 22:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Apr 29, 2026 12:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17695992213,5cyclictest0-21swapper/210:40:392
1769399220,3cyclictest0-21swapper/012:05:130
17695992118,2cyclictest25539-21ntp_offset11:10:172
17695992118,2cyclictest25539-21ntp_offset11:10:172
1769599203,16cyclictest8736-21ntpq12:35:172
17694992017,2cyclictest6504-21sessionclean10:38:591
17694992017,2cyclictest3981-21H222:10:211
1769499200,18cyclictest3979-21H222:10:211
1769399208,11cyclictest0-21swapper/010:45:130
1769599193,15cyclictest3979-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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