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2026-03-01 - 00:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Feb 28, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1731992725,2cyclictest0-21swapper/110:50:211
1732992625,0cyclictest0-21swapper/212:30:152
1732992625,0cyclictest0-21swapper/212:30:142
173299230,18cyclictest0-21swapper/210:55:172
1730992322,0cyclictest0-21swapper/010:50:200
1732992118,2cyclictest14172-21cat12:15:152
173299210,20cyclictest45352sleep207:13:222
173099210,20cyclictest843-21systemd-network08:03:180
173299203,11cyclictest0-21swapper/208:08:432
1732992015,3cyclictest0-21swapper/211:30:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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