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2026-05-11 - 19:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon May 11, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8227993025,2cyclictest18210-21ls08:25:011
8227992920,9cyclictest21-21ksoftirqd/110:50:331
8227992819,0cyclictest0-21swapper/110:27:251
822899232,13cyclictest0-21swapper/208:56:122
8227992217,4cyclictest0-21swapper/111:49:571
822799210,20cyclictest426-21systemd-udevd10:20:521
822899193,15cyclictest16615-21cat10:15:132
822899193,15cyclictest16615-21cat10:15:132
822899193,15cyclictest0-21swapper/211:09:212
8228991915,2cyclictest4209-21nfsd411:45:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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