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2025-11-22 - 13:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Nov 22, 2025 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1114699230,5cyclictest0-21swapper/223:59:392
1113599230,5cyclictest0-21swapper/019:43:320
11141992214,4cyclictest0-21swapper/120:16:161
1114199220,18cyclictest0-21swapper/121:44:421
1114199220,18cyclictest0-21swapper/121:44:421
1114199220,18cyclictest0-21swapper/100:05:241
1113599220,18cyclictest0-21swapper/019:40:010
1114699210,3cyclictest0-21swapper/220:12:572
11141992113,4cyclictest0-21swapper/123:01:231
11141992113,4cyclictest0-21swapper/123:01:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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