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2026-05-31 - 07:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun May 31, 2026 00:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
332299264,21cyclictest0-21swapper/020:49:530
333199240,6cyclictest824-21perf21:00:012
3322992416,7cyclictest0-21swapper/000:30:000
3322992416,7cyclictest0-21swapper/000:30:000
3322992414,2cyclictest25621-21ls23:35:140
3322992414,2cyclictest25621-21ls23:35:140
3322992317,5cyclictest3983-21H222:10:210
332299230,3cyclictest21779-21sed20:39:000
3331992217,4cyclictest3981-21H222:10:212
3322992214,2cyclictest25205-21cat23:35:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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