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2025-12-03 - 07:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Dec 03, 2025 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1311999261,19cyclictest0-21swapper/022:15:010
1312199250,1cyclictest0-21swapper/219:50:182
13121992420,3cyclictest32708-21php7.021:39:012
1312199237,15cyclictest28-21ksoftirqd/200:17:132
13121992314,9cyclictest0-21swapper/223:38:002
1312099230,5cyclictest0-21swapper/121:40:201
1312099220,21cyclictest0-21swapper/100:00:361
1312199212,18cyclictest12146-21fschecks_time22:55:162
1312199212,18cyclictest12146-21fschecks_time22:55:162
13121992121,0cyclictest0-21swapper/223:05:172
13121992118,2cyclictest4538-21H212:26:332
1312099215,15cyclictest21-21ksoftirqd/120:49:131
13119992121,0cyclictest0-21swapper/023:05:160
1311999210,4cyclictest0-21swapper/023:40:580
1312199203,2cyclictest4530-21H212:26:332
13121992011,8cyclictest0-21swapper/219:14:292
1312199200,19cyclictest823-21systemd-network21:52:282
1312099203,16cyclictest16109-21cut19:15:021
13119992018,1cyclictest9-21ksoftirqd/000:20:540
13119992017,2cyclictest4530-21H212:26:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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