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2026-08-27 - 21:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Aug 27, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21192992413,10cyclictest1587-21grep12:15:132
2119199220,3cyclictest427-21perf12:15:001
2119299213,2cyclictest17734-21ntp_kernel_pll_09:50:192
2119199213,2cyclictest14118-21cat08:50:011
21192992018,1cyclictest0-21swapper/210:23:232
21192992017,3cyclictest0-21swapper/209:03:002
2119299200,17cyclictest3985-21H222:10:212
2119299200,17cyclictest3985-21H222:10:212
2119199203,11cyclictest0-21swapper/108:05:471
21191992017,2cyclictest3976-21H222:10:211
2119199200,18cyclictest399-20systemd-journal10:20:001
21190992018,1cyclictest0-21swapper/008:02:330
21190992011,5cyclictest0-21swapper/011:55:140
2119099200,4cyclictest0-21swapper/010:45:180
21192991915,3cyclictest4099-21H222:10:212
2119299190,2cyclictest3983-21H222:10:212
2119299190,18cyclictest3985-21H222:10:212
2119299190,18cyclictest3985-21H222:10:212
2119299190,16cyclictest3976-21H222:10:212
2119199194,9cyclictest29720-21perf12:10:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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