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2026-07-18 - 12:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Jul 18, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30529992312,1cyclictest0-21swapper/223:33:362
30529992312,1cyclictest0-21swapper/223:33:352
3052899220,21cyclictest843-21systemd-network20:16:401
3052799220,4cyclictest0-21swapper/023:25:160
3052799220,17cyclictest0-21swapper/000:05:010
3052999210,20cyclictest843-21systemd-network23:23:322
3052799214,11cyclictest0-21swapper/021:12:230
3052999204,15cyclictest0-21swapper/223:52:582
3052999204,15cyclictest0-21swapper/220:24:592
30528992016,3cyclictest0-21swapper/122:56:501
30529991917,1cyclictest0-21swapper/222:09:112
30529991916,2cyclictest6117-21wc19:20:212
3052999190,18cyclictest0-21swapper/221:00:222
30528991916,2cyclictest5010-21wc22:10:181
30528991914,4cyclictest11075-21cat20:30:011
3052799190,15cyclictest0-21swapper/000:16:510
3052999182,15cyclictest14162-21cpuspeed_turbos20:35:142
3052999182,15cyclictest0-21swapper/223:25:152
30529991816,1cyclictest0-21swapper/223:57:302
30529991814,3cyclictest0-21swapper/222:29:052
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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