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2026-05-21 - 05:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu May 21, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3022399340,33cyclictest0-21swapper/022:00:120
30224992928,0cyclictest0-21swapper/123:19:261
30225992514,5cyclictest3989-21H222:10:212
3022599244,2cyclictest4738-21sort22:10:172
3022599243,1cyclictest0-21swapper/220:56:212
3022599240,2cyclictest9397-21gpgv19:30:022
3022399242,18cyclictest0-21swapper/000:15:010
3022599231,1cyclictest237402chrt23:41:082
30225992212,5cyclictest26513-21python321:55:012
3022599220,21cyclictest26028-21munin-run19:59:592
3022599220,16cyclictest6433-21munin-run00:09:592
3022599220,16cyclictest4551-21awk20:15:202
3022399220,18cyclictest0-21swapper/021:15:000
30225992114,6cyclictest30616-21grep19:10:102
30225992114,6cyclictest21599-21fschecks_count21:45:142
30225992114,6cyclictest17025-21ls20:40:202
30225992114,6cyclictest0-21swapper/223:09:002
30225992114,6cyclictest0-21swapper/200:25:122
30225992113,7cyclictest11070-21cut00:15:192
3022599211,15cyclictest0-21swapper/220:52:052
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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