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2026-03-11 - 12:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Mar 11, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21207992423,0cyclictest0-21swapper/223:45:152
2120699225,8cyclictest0-21swapper/119:39:421
21206992220,2cyclictest0-21swapper/123:31:501
21206992219,2cyclictest4099-21H222:10:211
2120599220,20cyclictest399-20systemd-journal00:24:010
2120599214,16cyclictest0-21swapper/020:12:590
21205992117,3cyclictest0-21swapper/000:15:010
2120799203,15cyclictest0-21swapper/200:31:212
21207992017,2cyclictest13595-21head23:40:182
21207992016,3cyclictest0-21swapper/219:47:292
2120799201,17cyclictest3976-21H222:10:212
21206992017,2cyclictest3983-21H222:10:211
2120699201,1cyclictest0-21swapper/120:35:171
2120699201,1cyclictest0-21swapper/120:35:161
2120799193,15cyclictest13823-21date00:40:002
2120799192,3cyclictest0-21swapper/220:26:222
21207991916,2cyclictest0-21swapper/223:50:122
21207991914,4cyclictest0-21swapper/219:29:102
2120799190,4cyclictest17435-21fschecks_time22:50:152
2120799190,1cyclictest0-21swapper/222:45:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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