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2026-07-24 - 22:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Jul 24, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16168992221,1cyclictest0-21swapper/207:46:182
1616899220,21cyclictest870-21systemd-logind11:48:512
1616899210,18cyclictest0-21swapper/207:41:372
1616799213,11cyclictest15161-21ls11:55:001
1616899203,11cyclictest0-21swapper/212:34:252
16168992016,3cyclictest0-21swapper/211:04:232
1616899200,19cyclictest843-21systemd-network08:31:012
1616899200,19cyclictest843-21systemd-network08:31:012
16167992010,9cyclictest21-21ksoftirqd/110:14:091
1616799200,19cyclictest843-21systemd-network09:22:301
1616799200,19cyclictest426-21systemd-udevd10:04:521
16165992014,3cyclictest0-21swapper/007:55:190
16168991917,1cyclictest28-21ksoftirqd/211:30:012
16168991914,3cyclictest4099-21H222:10:212
1616899190,2cyclictest3985-21H222:10:212
1616899190,16cyclictest3985-21H222:10:212
1616899190,16cyclictest3983-21H222:10:212
16167991917,1cyclictest21-21ksoftirqd/107:46:071
16167991914,4cyclictest3983-21H222:10:211
1616799190,18cyclictest426-21systemd-udevd11:16:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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