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2026-03-08 - 10:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Mar 08, 2026 00:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17713992514,6cyclictest31816-21iwlist20:30:162
17713992414,9cyclictest4120-21nfsd421:35:182
1770899240,23cyclictest870-21systemd-logind00:18:511
1770899240,19cyclictest22003-21cat22:10:001
1770899230,5cyclictest201rcuc/119:30:471
1770899230,22cyclictest870-21systemd-logind23:06:521
1771399210,18cyclictest0-21swapper/220:44:482
17708992119,1cyclictest21-21ksoftirqd/122:45:011
17708992119,1cyclictest21-21ksoftirqd/122:45:011
17703992118,2cyclictest3991-21H222:10:210
17703992118,2cyclictest29248-21fschecks_count22:20:140
1771399202,16cyclictest0-21swapper/222:56:472
1771399201,18cyclictest10664-21munin-run22:45:002
1771399201,18cyclictest10664-21munin-run22:45:002
1771399200,17cyclictest0-21swapper/220:25:132
1770399204,15cyclictest5595-21date19:45:010
17703992013,6cyclictest0-21swapper/020:30:010
1771399192,16cyclictest7197-21proc_pri19:45:232
17713991917,1cyclictest28-21ksoftirqd/222:03:472
17713991915,3cyclictest0-21swapper/200:12:552
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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