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2026-08-24 - 18:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Aug 24, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3049799263,18cyclictest5119-21cat11:10:010
30499992212,5cyclictest0-21swapper/208:10:192
3049999220,4cyclictest0-21swapper/212:20:152
3049999210,5cyclictest0-21swapper/212:36:402
30499992016,3cyclictest4099-21H222:10:212
30499992014,5cyclictest4035-21H222:10:212
3049899204,1cyclictest0-21swapper/107:33:171
30499991917,1cyclictest28-21ksoftirqd/211:03:592
3049999190,18cyclictest0-21swapper/210:06:312
3049999190,18cyclictest0-21swapper/210:06:302
3049899193,15cyclictest31048-21expr07:10:151
30498991917,1cyclictest21-21ksoftirqd/111:26:311
30497991917,1cyclictest0-21swapper/011:17:080
30497991914,2cyclictest3981-21H222:10:210
30497991910,8cyclictest843-21systemd-network11:27:180
3049799190,17cyclictest3058-21rs:main0
3049799190,16cyclictest4035-21H222:10:210
3049799190,16cyclictest3983-21H222:10:210
3049999186,11cyclictest0-21swapper/210:39:172
30499991816,1cyclictest0-21swapper/212:29:392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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