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2026-02-06 - 00:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Feb 05, 2026 00:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1565699230,15cyclictest0-21swapper/021:10:000
1565699221,6cyclictest8798-21cat19:55:010
1565799203,16cyclictest0-21swapper/120:41:071
1565799203,16cyclictest0-21swapper/120:41:071
15657992016,3cyclictest0-21swapper/100:35:341
1565699203,16cyclictest0-21swapper/023:50:150
15656992016,3cyclictest10228-21sort21:50:140
1565899192,9cyclictest0-21swapper/222:36:552
15658991917,1cyclictest0-21swapper/221:54:282
1565899190,4cyclictest25421-21tail00:10:162
1565899190,4cyclictest25421-21tail00:10:162
1565799192,6cyclictest0-21swapper/120:06:391
15657991916,2cyclictest29668-21cut00:20:001
1565799190,18cyclictest0-21swapper/120:15:221
1565699194,1cyclictest0-21swapper/020:30:340
1565699193,15cyclictest9-21ksoftirqd/021:35:020
1565699193,15cyclictest9-21ksoftirqd/021:20:120
15656991915,3cyclictest23716-21fgrep21:15:200
1565699191,16cyclictest14564-21nfsd422:55:170
1565699190,5cyclictest0-21swapper/023:15:390
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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