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2026-08-04 - 03:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Aug 04, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20548993029,0cyclictest0-21swapper/100:31:501
20548993028,2cyclictest21-21ksoftirqd/100:21:441
20548993021,9cyclictest0-21swapper/122:45:161
20548993021,9cyclictest0-21swapper/122:45:161
20548993021,9cyclictest0-21swapper/100:10:161
20548992617,9cyclictest0-21swapper/122:20:291
2055299240,5cyclictest0-21swapper/221:43:592
20548992320,2cyclictest3983-21H222:10:211
2054899230,22cyclictest0-21swapper/122:40:041
20548992214,4cyclictest0-21swapper/122:11:211
2054899220,21cyclictest843-21systemd-network22:59:201
20552992117,3cyclictest0-21swapper/200:29:382
2054899210,19cyclictest3991-21H222:10:211
2054899210,19cyclictest3987-21H222:10:211
2055299204,15cyclictest0-21swapper/220:05:112
2055299202,3cyclictest993-21dbus-daemon00:35:202
20552992019,1cyclictest0-21swapper/200:10:162
20552992017,2cyclictest23702-21sshd23:59:162
20552992016,3cyclictest0-21swapper/221:09:152
20552992014,5cyclictest426-21systemd-udevd22:40:522
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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