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2025-11-17 - 16:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Nov 17, 2025 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32527993633,2cyclictest0-21swapper/220:15:222
32527992310,7cyclictest28-21ksoftirqd/223:40:002
3251499214,15cyclictest0-21swapper/019:15:000
3252799202,2cyclictest4534-21H212:26:332
3252799202,17cyclictest967-21thermald23:40:202
32527992014,5cyclictest4581-21H212:26:332
3252799200,18cyclictest4536-21H212:26:332
3252099200,17cyclictest0-21swapper/120:35:201
3252799192,2cyclictest14004-21chrt19:34:062
32527991917,1cyclictest28-21ksoftirqd/221:35:462
32527991913,2cyclictest0-21swapper/223:00:412
3252799190,2cyclictest4593-21H212:26:332
3252799190,2cyclictest4538-21H212:26:332
3252799190,2cyclictest4532-21H212:26:332
3252799190,16cyclictest4536-21H212:26:332
3252099193,1cyclictest0-21swapper/123:53:311
3252099192,16cyclictest4530-21H212:26:331
3252099190,16cyclictest4581-21H212:26:331
3252099190,16cyclictest4581-21H212:26:331
3252099190,16cyclictest4523-21H212:26:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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