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2026-01-30 - 11:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Jan 30, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2388999220,2cyclictest4975-21cut00:20:012
2388999220,16cyclictest3987-21H222:10:212
23884992221,1cyclictest21-21ksoftirqd/122:46:451
2388499220,21cyclictest843-21systemd-network20:51:181
2387999220,18cyclictest0-21swapper/019:35:380
23889992116,4cyclictest0-21swapper/221:30:182
2388999210,15cyclictest0-21swapper/219:25:132
23884992121,0cyclictest21-21ksoftirqd/123:10:341
23884992117,3cyclictest0-21swapper/123:31:091
23889992014,5cyclictest0-21swapper/200:20:172
23889992014,3cyclictest0-21swapper/219:21:452
23884992020,0cyclictest0-21swapper/119:54:531
2388999192,2cyclictest30105-21processes00:05:212
2388999192,2cyclictest30105-21processes00:05:212
2388999192,16cyclictest21293-21nfsd420:00:202
23889991917,1cyclictest28397-21readlink21:10:202
23889991916,1cyclictest0-21swapper/222:03:232
2388999191,16cyclictest19990-21munin-plugin-st20:00:002
2388999190,17cyclictest4035-21H222:10:212
2388999190,17cyclictest0-21swapper/200:00:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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