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2026-01-16 - 18:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Jan 16, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6417992814,14cyclictest0-21swapper/208:05:132
6412992719,0cyclictest0-21swapper/007:45:150
6413992323,0cyclictest0-21swapper/107:45:141
641299230,5cyclictest0-21swapper/010:26:530
641299230,5cyclictest0-21swapper/009:51:370
641799202,17cyclictest0-21swapper/210:27:352
641299204,1cyclictest0-21swapper/009:03:480
641799190,1cyclictest0-21swapper/210:55:132
641399193,15cyclictest0-21swapper/108:09:281
6413991916,2cyclictest16841-21cut10:15:191
6413991914,2cyclictest4099-21H222:10:211
641399190,16cyclictest3983-21H222:10:211
641399190,16cyclictest0-21swapper/111:07:401
6412991917,1cyclictest3997-21ntp_kernel_pll_10:50:170
641299190,18cyclictest0-21swapper/007:36:260
641299190,17cyclictest3983-21H222:10:210
641799182,1cyclictest28-21ksoftirqd/212:35:342
641799182,15cyclictest28-21ksoftirqd/212:09:532
6417991815,2cyclictest31733-21cat10:45:012
6417991815,2cyclictest29423-21munin-run07:50:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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