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2026-01-14 - 16:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Jan 14, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21059993028,2cyclictest0-21swapper/112:26:361
21059993028,0cyclictest0-21swapper/112:23:171
21059992718,9cyclictest0-21swapper/107:12:151
21059992616,10cyclictest27774-21kworker/1:111:27:471
2105999260,25cyclictest0-21swapper/108:38:471
2105999220,18cyclictest0-21swapper/111:58:001
2105999220,18cyclictest0-21swapper/111:58:001
21064992014,5cyclictest0-21swapper/208:43:312
21064992013,3cyclictest0-21swapper/210:29:352
2106499200,16cyclictest0-21swapper/211:36:392
21059992016,1cyclictest0-21swapper/110:40:171
2105499203,16cyclictest0-21swapper/009:23:420
2105499203,16cyclictest0-21swapper/009:23:410
21064991916,1cyclictest0-21swapper/207:12:092
21064991915,2cyclictest0-21swapper/209:05:172
2105999198,11cyclictest0-21swapper/110:12:011
2105999197,12cyclictest0-21swapper/111:16:001
2105999197,12cyclictest0-21swapper/110:20:321
2105999196,13cyclictest0-21swapper/111:54:251
2105999196,12cyclictest0-21swapper/111:41:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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