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2026-07-13 - 08:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Jul 13, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16039992914,14cyclictest0-21swapper/200:05:002
16039992211,8cyclictest8016-21nfsd419:50:182
1603999203,16cyclictest3985-21H222:10:212
1603999202,17cyclictest0-21swapper/223:30:212
16031992017,2cyclictest3976-21H222:10:210
1603999193,15cyclictest0-21swapper/221:55:422
1603999192,16cyclictest13413-21cat22:55:022
16039991917,1cyclictest8870-21latency20:50:172
16039991917,1cyclictest0-21swapper/223:00:002
16039991916,2cyclictest5184-21nfsd421:40:182
16039991916,2cyclictest14969-21mailstats21:00:192
16039991914,3cyclictest3987-21H222:10:212
1603999190,18cyclictest0-21swapper/219:16:562
1603999190,16cyclictest3981-21H222:10:212
1603699193,2cyclictest15154-21expr22:00:131
16036991917,1cyclictest0-21swapper/122:41:341
16036991916,2cyclictest23175-21missed_timers21:15:171
16036991915,1cyclictest0-21swapper/119:49:401
1603699190,2cyclictest3985-21H222:10:211
1603699190,1cyclictest0-21swapper/120:31:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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