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2026-07-07 - 02:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Jul 06, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3060399283,19cyclictest23495-21latency_hist08:50:010
3060599225,11cyclictest0-21swapper/207:45:152
30603992214,4cyclictest0-21swapper/008:44:150
3060599213,11cyclictest9158-21python308:25:012
3060599211,17cyclictest23716-21perf10:45:002
3060399215,12cyclictest0-21swapper/011:05:160
3060499209,10cyclictest455-21plymouthd12:30:141
30603992011,3cyclictest0-21swapper/007:50:150
3060399200,2cyclictest0-21swapper/009:42:220
3060599197,11cyclictest0-21swapper/212:25:162
3060599193,2cyclictest3989-21H222:10:212
30605991916,2cyclictest8461-21cut11:15:012
30605991916,2cyclictest8461-21cut11:15:012
30605991916,2cyclictest2479-21if_lxdbr010:05:152
30605991916,2cyclictest14652-21seq08:30:502
3060499198,10cyclictest0-21swapper/110:24:001
3060499193,15cyclictest0-21swapper/110:42:221
3060499193,15cyclictest0-21swapper/108:26:151
3060499192,16cyclictest9107-21nfsd412:10:171
30604991917,1cyclictest28172-21expr09:55:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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