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2025-11-27 - 18:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Nov 27, 2025 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16776992711,15cyclictest29163-21mii-tool07:30:150
16776992522,2cyclictest24970-21mii-tool11:10:150
1677899230,5cyclictest0-21swapper/210:26:372
1677699230,22cyclictest0-21swapper/010:26:580
1677699220,18cyclictest0-21swapper/007:10:190
1677899210,20cyclictest0-21swapper/209:13:322
1677799204,15cyclictest0-21swapper/109:05:291
1677799200,19cyclictest823-21systemd-network11:25:071
1677699206,13cyclictest0-21swapper/009:48:460
1677699202,3cyclictest0-21swapper/009:30:190
16776992017,2cyclictest4581-21H212:26:330
16778991916,2cyclictest11762-21expr11:45:152
16778991915,1cyclictest0-21swapper/209:30:172
16778991914,2cyclictest4526-21H212:26:332
1677899190,17cyclictest4523-21H212:26:332
1677899190,16cyclictest4526-21H212:26:332
1677899190,16cyclictest4523-21H212:26:332
16777991917,1cyclictest0-21swapper/107:38:561
1677799190,2cyclictest4581-21H212:26:331
1677799190,16cyclictest4530-21H212:26:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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