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2026-01-11 - 08:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Jan 11, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13019992514,10cyclictest22394-21perf23:15:011
13027992424,0cyclictest0-21swapper/222:47:092
1302799220,8cyclictest0-21swapper/219:50:152
1302799220,8cyclictest0-21swapper/200:35:162
1301899220,21cyclictest843-21systemd-network19:57:250
1302799203,16cyclictest0-21swapper/220:33:022
13027992016,1cyclictest0-21swapper/223:44:212
1301899204,15cyclictest0-21swapper/000:32:390
13018992014,3cyclictest0-21swapper/021:26:270
1302799192,3cyclictest0-21swapper/220:00:002
1302799192,16cyclictest21492-21chrt19:24:512
1302799192,16cyclictest19665-21turbostat23:10:012
1302799192,16cyclictest11625-21cstates22:55:122
1302799192,16cyclictest0-21swapper/223:15:282
1302799192,16cyclictest0-21swapper/221:39:342
13027991917,1cyclictest0-21swapper/220:10:142
13027991916,2cyclictest9739-21cat23:49:552
1302799191,3cyclictest0-21swapper/222:20:502
13027991913,5cyclictest0-21swapper/219:37:522
1302799191,1cyclictest0-21swapper/222:09:542
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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