You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-09-15 - 14:57
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Sep 15, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3125899300,29cyclictest0-21swapper/022:50:120
3126099220,21cyclictest843-21systemd-network23:29:252
3126099220,21cyclictest843-21systemd-network22:56:542
3126099212,18cyclictest0-21swapper/220:25:512
3125999215,9cyclictest0-21swapper/121:38:571
31259992112,3cyclictest0-21swapper/120:42:081
3126099202,17cyclictest3981-21H222:10:212
3126099202,17cyclictest19639-21smtpd22:37:402
3126099200,5cyclictest0-21swapper/220:18:232
31259992017,2cyclictest3414-21master20:12:041
3125899203,9cyclictest11345-21python320:30:010
31260991917,1cyclictest0-21swapper/221:21:012
31260991916,2cyclictest426-21systemd-udevd19:26:522
3126099191,3cyclictest0-21swapper/223:33:482
3126099190,2cyclictest3979-21H222:10:212
3126099190,1cyclictest0-21swapper/222:13:552
3126099190,16cyclictest3991-21H222:10:212
3126099190,16cyclictest3987-21H222:10:212
3126099190,16cyclictest3981-21H222:10:212
3126099190,16cyclictest3976-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional