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2026-02-26 - 12:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Feb 26, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3087399232,2cyclictest32190-21expr23:55:191
3087399231,15cyclictest0-21swapper/119:35:121
3087399230,3cyclictest0-21swapper/119:28:551
3087399230,1cyclictest273452sleep121:53:541
3087099234,13cyclictest13698-21munin-run23:25:010
30873992220,2cyclictest0-21swapper/122:10:131
30873992212,9cyclictest13575-21cat19:35:021
3087399221,20cyclictest4739-21http19:20:001
3087399220,2cyclictest3334-21sed00:00:211
3087399220,2cyclictest11685-21date20:30:001
3087399220,21cyclictest9280-21chrt22:19:501
3087399220,21cyclictest455-21plymouthd19:20:201
3087399220,21cyclictest31425-21awk20:05:171
3087399220,21cyclictest20773-21expr20:45:141
3087399220,21cyclictest0-21swapper/122:50:171
3087399220,1cyclictest0-21swapper/123:13:121
3087399220,17cyclictest0-21swapper/123:52:371
3087399220,16cyclictest31418-21if_enp1s022:00:161
3087399220,16cyclictest31418-21if_enp1s022:00:161
3087099222,3cyclictest0-21swapper/020:04:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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