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2026-04-01 - 21:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Apr 01, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
100399250,23cyclictest8173-21irqstats07:20:170
1004992320,2cyclictest13861-21grep08:30:021
100499230,20cyclictest0-21swapper/107:45:331
1005992221,0cyclictest2227-21mii-tool07:10:182
100599220,18cyclictest0-21swapper/209:34:592
100599220,18cyclictest0-21swapper/208:22:192
1004992214,4cyclictest0-21swapper/109:45:221
1003992218,3cyclictest22229-21munin-plugin-st11:34:590
100399220,18cyclictest0-21swapper/009:20:560
100599210,3cyclictest0-21swapper/209:27:132
100499219,10cyclictest0-21swapper/108:59:461
1004992117,3cyclictest0-21swapper/107:28:591
1004992116,4cyclictest0-21swapper/108:04:151
100399214,3cyclictest0-21swapper/010:02:110
100399210,3cyclictest0-21swapper/012:28:290
1005992016,3cyclictest0-21swapper/212:26:532
1005992016,3cyclictest0-21swapper/208:17:052
100399202,17cyclictest15879-21pzem11:20:210
100599192,2cyclictest4169-21switchtime11:55:222
100599192,2cyclictest14238-21grep12:15:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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