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2026-08-08 - 08:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Aug 08, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26126992313,9cyclictest19298-21php7.000:39:000
2612799220,21cyclictest843-21systemd-network20:25:431
2612699220,21cyclictest843-21systemd-network20:36:300
2613199214,16cyclictest2069-21systemd-udevd00:20:512
2613199210,20cyclictest870-21systemd-logind20:56:532
2612699210,20cyclictest843-21systemd-network20:34:280
2613199202,17cyclictest0-21swapper/222:25:142
26131992017,2cyclictest4723-21chrt19:26:502
26127992019,0cyclictest0-21swapper/120:40:161
26127992018,1cyclictest21-21ksoftirqd/122:11:231
2612799200,19cyclictest843-21systemd-network20:17:581
2612799200,17cyclictest3976-21H222:10:211
26126992016,3cyclictest0-21swapper/022:52:360
2613199193,15cyclictest0-21swapper/219:20:142
2613199192,1cyclictest3985-21H222:10:212
2613199192,16cyclictest3991-21H222:10:212
2613199190,3cyclictest24284-21tail23:50:162
2613199190,2cyclictest3976-21H222:10:212
2613199190,17cyclictest3983-21H222:10:212
2613199190,16cyclictest3991-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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