You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-29 - 22:48
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Jun 29, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2741399261,1cyclictest28-21ksoftirqd/209:37:122
2741299266,14cyclictest0-21swapper/108:50:421
27412992414,7cyclictest0-21swapper/112:20:161
2741299230,5cyclictest1-21systemd08:35:011
27413992221,1cyclictest28-21ksoftirqd/209:46:382
27413992121,0cyclictest28-21ksoftirqd/209:31:062
27413992121,0cyclictest28-21ksoftirqd/209:27:502
27413992121,0cyclictest28-21ksoftirqd/209:03:392
27413992118,2cyclictest31404-21uname12:00:232
2741199210,20cyclictest0-21swapper/007:54:430
27413992020,0cyclictest28-21ksoftirqd/210:49:062
27413992020,0cyclictest28-21ksoftirqd/209:55:352
27413992020,0cyclictest28-21ksoftirqd/209:06:302
27413992020,0cyclictest28-21ksoftirqd/208:55:062
27413992020,0cyclictest0-21swapper/208:29:352
2741199202,3cyclictest23757-21grep09:55:010
27411992018,1cyclictest0-21swapper/009:40:140
2741199200,3cyclictest0-21swapper/010:30:210
2741399192,16cyclictest271rcuc/210:05:232
27413991919,0cyclictest0-21swapper/209:50:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional