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2026-06-27 - 22:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Jun 27, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26982993027,1cyclictest0-21swapper/209:15:162
26981993024,5cyclictest0-21swapper/108:00:001
2698199280,5cyclictest0-21swapper/109:00:151
26981992711,11cyclictest16842-21smartctl09:40:191
2698199253,21cyclictest0-21swapper/109:55:241
26981992518,6cyclictest1348-21lxd09:50:011
26981992518,6cyclictest1100-21snmpd10:04:541
26981992514,4cyclictest0-21swapper/108:20:491
26981992514,10cyclictest19869-21munin-plugin-st07:55:001
26981992512,7cyclictest18833-21postgres08:49:151
26980992523,1cyclictest9-21ksoftirqd/009:06:430
2698099250,24cyclictest0-21swapper/008:49:030
2698299240,19cyclictest4146-21cut07:25:152
2698199242,2cyclictest24248-21ntpq08:00:191
26981992417,6cyclictest1100-21snmpd08:27:041
2698199240,20cyclictest0-21swapper/109:20:401
2698299230,5cyclictest0-21swapper/211:34:012
2698299230,5cyclictest0-21swapper/209:23:132
2698299230,1cyclictest0-21swapper/210:25:012
26981992314,5cyclictest0-21swapper/109:49:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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