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2026-04-19 - 23:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Apr 19, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2322992323,0cyclictest0-21swapper/208:00:012
232299230,18cyclictest0-21swapper/210:25:192
231399234,18cyclictest0-21swapper/008:45:000
2322992222,0cyclictest0-21swapper/209:00:152
232299220,8cyclictest843-21systemd-network12:30:222
231799220,21cyclictest843-21systemd-network07:31:001
2322992118,2cyclictest16061-21dump-pmu-power08:30:012
2322991917,1cyclictest9612-21timerandwakeup08:15:212
2322991917,1cyclictest9612-21timerandwakeup08:15:202
2322991917,1cyclictest6075-21latency08:10:172
2322991917,1cyclictest0-21swapper/208:20:162
2322991916,2cyclictest0-21swapper/210:50:162
2322991916,1cyclictest0-21swapper/207:15:182
2322991915,3cyclictest0-21swapper/211:01:582
232299191,17cyclictest0-21swapper/208:05:172
232299190,3cyclictest0-21swapper/211:35:192
232299190,18cyclictest0-21swapper/209:35:012
231799193,2cyclictest9453-21perf11:10:011
231799192,1cyclictest0-21swapper/111:32:131
2317991912,3cyclictest0-21swapper/112:06:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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