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2025-07-12 - 10:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Jul 12, 2025 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1784999250,21cyclictest0-21swapper/219:15:562
1784599243,1cyclictest0-21swapper/121:13:291
1784599242,3cyclictest0-21swapper/120:50:221
1784999230,3cyclictest32615-21if_lxdbr021:30:172
1784999230,22cyclictest13209-21sh20:00:012
1784999230,17cyclictest23646-21sed00:05:212
1784999221,20cyclictest4539-21H212:26:332
1784999221,20cyclictest30980-21taskset21:25:352
1784999221,20cyclictest0-21swapper/222:10:172
1784999220,21cyclictest966-21expr20:35:152
1784999220,21cyclictest7291-21cat19:45:272
1784999220,21cyclictest6840-21mailstats23:35:252
1784999220,21cyclictest6005-21sed22:39:012
1784999220,21cyclictest25434-21date22:15:192
1784999220,21cyclictest18354-21tr19:10:142
1784999220,1cyclictest0-21swapper/222:50:162
1784999220,1cyclictest0-21swapper/200:25:162
1784999220,0cyclictest0-21swapper/220:59:332
1784599222,19cyclictest29581-21taskset00:16:181
1784599222,16cyclictest967-21thermald22:10:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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