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2026-08-09 - 10:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Aug 09, 2026 00:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1956899240,18cyclictest0-21swapper/122:04:381
1956899231,21cyclictest5809-21cat21:35:151
1956999220,18cyclictest0-21swapper/222:15:162
1956899222,1cyclictest5245-21chrt23:28:041
19568992214,7cyclictest15376-21apache_processe22:50:121
19568992214,7cyclictest15376-21apache_processe22:50:121
19568992214,7cyclictest10238-21apache_processe00:35:121
1956899220,3cyclictest6932-21tr20:40:131
1956899220,2cyclictest3450-21gsd-color20:55:141
1956899220,2cyclictest19526-21cut22:00:011
1956899220,21cyclictest27730-21expr20:20:141
1956899220,1cyclictest26898-21ntpq00:05:201
1956899220,1cyclictest26898-21ntpq00:05:201
1956899220,1cyclictest0-21swapper/123:00:211
1956899220,1cyclictest0-21swapper/120:25:151
1956899220,1cyclictest0-21swapper/100:01:001
1956899220,17cyclictest4282-21sort19:39:011
1956899220,16cyclictest32436-21awk19:30:171
1956899220,16cyclictest31531-21http_loadtime22:20:171
1956899220,16cyclictest0-21swapper/119:25:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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