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2026-03-31 - 06:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Mar 31, 2026 00:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1659099260,16cyclictest0-21swapper/120:59:551
1659199247,13cyclictest0-21swapper/220:02:192
1659099220,21cyclictest3573-21latency_hist22:35:021
1659199214,2cyclictest3903-21cpuspeed_turbos22:35:142
16590992117,3cyclictest0-21swapper/120:38:571
1658999215,9cyclictest0-21swapper/019:17:140
1659199202,15cyclictest11526-21ntp_kernel_pll_21:50:182
1659199194,1cyclictest0-21swapper/223:21:072
16591991916,2cyclictest17177-21cut21:05:012
1659199190,17cyclictest6749-21proc_pri23:35:202
1659199190,16cyclictest3981-21H222:10:212
16590991916,1cyclictest0-21swapper/123:49:011
1659099190,18cyclictest29635-21nfsd421:25:171
1659099190,16cyclictest0-21swapper/119:12:461
16589991914,4cyclictest0-21swapper/023:15:000
16589991914,2cyclictest15231-21awk22:00:000
16591991814,3cyclictest0-21swapper/200:27:072
1659199181,16cyclictest30614-21grep19:35:012
1659199180,2cyclictest3989-21H222:10:212
1659199180,17cyclictest28578-21cstates21:25:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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