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2026-07-23 - 20:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Jul 23, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1945399231,7cyclictest13902-21fschecks_time11:45:142
1945399230,20cyclictest0-21swapper/208:12:562
1945299234,18cyclictest0-21swapper/109:59:471
19453992214,4cyclictest0-21swapper/208:45:022
1945399220,3cyclictest21729-21cut10:05:132
1945399214,1cyclictest0-21swapper/209:25:522
1945399214,16cyclictest0-21swapper/212:40:012
1945399210,20cyclictest25848-21cut07:20:152
1945299210,19cyclictest28544-21df07:25:141
19453992017,2cyclictest21033-21missed_timers09:05:172
19452992017,2cyclictest3987-21H222:10:211
1945399193,15cyclictest25673-21proc_pri12:05:202
1945399193,15cyclictest0-21swapper/208:27:532
1945399192,3cyclictest0-21swapper/208:08:392
1945399192,2cyclictest22535-21chrt11:04:152
1945399192,1cyclictest0-21swapper/209:19:032
1945399192,16cyclictest0-21swapper/209:00:372
19453991916,2cyclictest27666-21grep08:20:182
19453991915,3cyclictest0-21swapper/211:55:132
1945399191,3cyclictest0-21swapper/210:10:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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