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2026-02-06 - 12:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Feb 06, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15685992416,8cyclictest21-21ksoftirqd/119:17:591
15685992414,10cyclictest0-21swapper/122:27:051
15685992414,10cyclictest0-21swapper/122:27:051
1568699204,1cyclictest0-21swapper/222:16:592
1568699203,16cyclictest0-21swapper/200:16:252
1568699200,16cyclictest20693-21perf23:10:002
1568599202,17cyclictest0-21swapper/123:44:441
15686991917,1cyclictest0-21swapper/220:47:192
15686991916,1cyclictest0-21swapper/220:35:362
1568699190,17cyclictest26950-21cron21:25:002
1568599191,16cyclictest18860-21fschecks_count22:05:141
1568599190,4cyclictest25078-21turbostat00:15:001
1568599190,4cyclictest25078-21turbostat00:14:591
1568599190,18cyclictest870-21systemd-logind00:36:511
1568599190,18cyclictest0-21swapper/121:09:391
1568499193,15cyclictest0-21swapper/020:05:210
15684991918,1cyclictest9-21ksoftirqd/021:34:480
15684991914,4cyclictest0-21swapper/019:24:300
15684991912,6cyclictest870-21systemd-logind21:58:520
1568499190,18cyclictest426-21systemd-udevd00:08:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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