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2026-05-19 - 01:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon May 18, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23762992313,10cyclictest0-21swapper/109:35:011
2376199220,18cyclictest0-21swapper/011:38:260
2376299212,16cyclictest3976-21H222:10:211
2376299209,0cyclictest0-21swapper/109:01:351
2376299202,17cyclictest0-21swapper/109:11:381
2376199203,11cyclictest30367-21munin-run09:15:010
2376699192,16cyclictest22691-21nfsd411:50:172
2376699192,16cyclictest0-21swapper/208:05:202
23766991917,1cyclictest28-21ksoftirqd/211:02:272
23766991917,1cyclictest0-21swapper/211:28:192
2376699190,18cyclictest12917-21perf09:40:012
2376699190,16cyclictest3983-21H222:10:212
23762991918,0cyclictest0-21swapper/112:30:151
23762991917,1cyclictest0-21swapper/108:54:561
23762991916,2cyclictest3979-21H222:10:211
23762991916,2cyclictest21-21ksoftirqd/110:24:291
2376299190,18cyclictest843-21systemd-network10:56:491
2376299190,16cyclictest3987-21H222:10:211
2376299190,16cyclictest3979-21H222:10:211
23761991915,2cyclictest3976-21H222:10:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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