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2026-04-27 - 12:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Apr 27, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1043499210,20cyclictest0-21swapper/200:38:172
1043299212,16cyclictest0-21swapper/123:21:441
1043299210,18cyclictest0-21swapper/123:40:421
10431992114,4cyclictest0-21swapper/022:35:540
1043299202,17cyclictest31850irq/133-nvme0q219:35:011
1043299200,6cyclictest0-21swapper/119:45:011
1043299200,4cyclictest0-21swapper/122:40:121
1043499192,2cyclictest4099-21H222:10:212
10434991916,2cyclictest20090-21latency_hist23:15:012
10434991916,2cyclictest10863-21missed_timers20:05:172
1043499190,16cyclictest3991-21H222:10:212
1043299193,1cyclictest0-21swapper/121:59:181
1043299191,17cyclictest0-21swapper/122:15:011
10431991916,2cyclictest1859-21chrt21:42:240
1043199190,17cyclictest31668-21https21:40:010
1043499182,15cyclictest28-21ksoftirqd/221:55:192
10434991815,2cyclictest3987-21H222:10:212
1043499181,2cyclictest25334-21smtpd23:22:202
1043499181,1cyclictest0-21swapper/219:37:162
1043499181,16cyclictest3709-21qmgr20:34:322
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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