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2026-01-27 - 05:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Jan 27, 2026 00:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14484992626,0cyclictest0-21swapper/220:30:152
14484992312,10cyclictest0-21swapper/220:10:142
1448499220,21cyclictest843-21systemd-network20:29:022
14472992214,4cyclictest0-21swapper/022:00:000
14484992112,0cyclictest0-21swapper/223:50:162
14477992117,3cyclictest0-21swapper/123:44:491
14477992113,4cyclictest0-21swapper/122:00:171
1447799210,3cyclictest0-21swapper/120:45:251
1448499200,17cyclictest0-21swapper/223:32:482
1447799200,19cyclictest399-20systemd-journal22:39:001
1447799200,17cyclictest0-21swapper/100:14:521
14472992013,4cyclictest0-21swapper/000:00:140
1447299200,6cyclictest843-21systemd-network23:10:460
14484991917,1cyclictest0-21swapper/200:30:122
14484991916,2cyclictest24212-21cat00:10:182
1447799194,1cyclictest0-21swapper/119:35:251
14477991917,1cyclictest21-21ksoftirqd/122:50:151
14477991917,1cyclictest0-21swapper/119:25:131
14477991915,3cyclictest0-21swapper/122:24:241
1447799190,18cyclictest0-21swapper/123:19:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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