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2026-07-03 - 01:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Jul 02, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2271399264,9cyclictest20923-21perf08:05:010
2271399264,9cyclictest20923-21perf08:05:000
2271499240,3cyclictest0-21swapper/112:03:271
2271599233,13cyclictest20948-21python310:54:592
22715992314,5cyclictest0-21swapper/207:48:112
2271599230,5cyclictest0-21swapper/209:39:582
22714992313,6cyclictest3991-21H222:10:211
2271599220,18cyclictest0-21swapper/208:30:562
2271499222,16cyclictest25263-21sed12:00:011
22714992215,6cyclictest20662-21irqstats09:55:181
2271499220,2cyclictest8211-21sed08:35:191
2271499220,2cyclictest13149-21apache_volume08:45:111
2271499220,2cyclictest12526-21if_eno111:35:161
2271499220,21cyclictest0-21swapper/109:20:161
2271499220,20cyclictest3979-21H222:10:211
2271499220,16cyclictest30613-21expr11:10:151
2271499220,15cyclictest0-21swapper/108:15:021
2271599210,20cyclictest0-21swapper/211:06:332
22714992114,6cyclictest24923-21ls08:10:121
22714992114,6cyclictest22271-21df10:55:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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