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2025-11-28 - 18:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Nov 28, 2025 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15935992726,0cyclictest0-21swapper/109:05:011
1593799240,23cyclictest0-21swapper/208:28:372
1593799240,1cyclictest271rcuc/208:05:142
1593599230,5cyclictest0-21swapper/107:48:471
15937992216,5cyclictest271rcuc/209:40:212
1593599220,21cyclictest0-21swapper/108:32:521
15934992216,5cyclictest0-21swapper/010:20:000
1593799203,2cyclictest23166-21nfsd410:10:192
15937992018,1cyclictest0-21swapper/211:13:282
1593799200,19cyclictest0-21swapper/210:30:032
1593599204,15cyclictest0-21swapper/111:36:411
1593499200,19cyclictest0-21swapper/008:25:080
1593799193,1cyclictest28-21ksoftirqd/212:30:182
1593799192,16cyclictest0-21swapper/212:27:372
1593799190,1cyclictest0-21swapper/211:17:522
15934991916,2cyclictest7986-21sed11:40:010
1593499190,1cyclictest0-21swapper/007:49:580
1593499190,18cyclictest0-21swapper/011:54:260
1593499190,18cyclictest0-21swapper/009:05:030
1593799189,5cyclictest0-21swapper/209:04:492
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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