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2026-08-28 - 22:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Aug 28, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2676099240,19cyclictest0-21swapper/210:40:172
2676099232,14cyclictest4197-21munin-run08:25:002
2676099232,14cyclictest4197-21munin-run08:25:002
2675899230,5cyclictest0-21swapper/012:06:430
26760992117,3cyclictest0-21swapper/207:54:232
26760992116,3cyclictest15018-21grep10:35:132
26760992017,2cyclictest859-21if_enp1s012:05:152
26760992011,5cyclictest0-21swapper/211:25:122
2676099200,3cyclictest22950-21smartctl11:45:152
2676099200,19cyclictest0-21swapper/207:41:262
26759992017,2cyclictest3981-21H222:10:211
2676099193,1cyclictest0-21swapper/210:02:062
2676099192,16cyclictest2077-21cat07:20:222
26760991917,1cyclictest5439-21expr11:15:142
26760991917,1cyclictest24819-21expr09:00:142
26760991917,1cyclictest22107-21sed10:45:202
26760991917,1cyclictest0-21swapper/211:30:202
26760991917,1cyclictest0-21swapper/208:15:222
26760991916,2cyclictest8570-21date12:20:002
26760991915,3cyclictest0-21swapper/212:39:032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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