You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-04-05 - 05:21
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Apr 05, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2411799310,31cyclictest0-21swapper/119:10:151
24116992625,0cyclictest0-21swapper/020:55:170
2411799230,22cyclictest0-21swapper/100:00:561
2411799230,20cyclictest0-21swapper/121:06:051
24117992213,8cyclictest0-21swapper/100:14:501
2411699220,6cyclictest0-21swapper/000:32:190
2411699220,4cyclictest0-21swapper/019:19:360
2411799203,11cyclictest0-21swapper/121:45:511
2411799202,17cyclictest0-21swapper/121:14:061
2411799202,15cyclictest0-21swapper/122:01:391
24117992016,3cyclictest0-21swapper/121:36:561
2411799200,17cyclictest28404-21python322:10:011
2411699202,17cyclictest0-21swapper/022:21:080
24116992014,3cyclictest0-21swapper/023:55:190
2411899192,16cyclictest25889-21chrt23:56:372
24118991915,3cyclictest0-21swapper/220:51:242
24118991915,2cyclictest16273-21nvmesmart_nvme019:50:192
2411899191,17cyclictest6205-21cpuspeed_turbos21:30:152
2411899190,18cyclictest0-21swapper/219:38:122
2411799192,16cyclictest13133-21cat19:45:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional