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2026-02-14 - 00:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Feb 13, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3217899265,20cyclictest0-21swapper/109:20:161
32178992519,5cyclictest31905-21date10:00:001
3217899243,1cyclictest0-21swapper/110:39:591
3217899242,1cyclictest79902chrt07:20:541
3217899231,16cyclictest24439-21chrt11:40:101
3217899230,2cyclictest10837-21nfsd407:25:181
3217899230,16cyclictest21761-21/usr/sbin/munin07:45:151
32178992215,6cyclictest16970-21cut10:30:121
3217899220,2cyclictest16723-21cat09:30:201
3217899220,21cyclictest12744-21expr07:30:121
3217899220,1cyclictest0-21swapper/110:15:221
3217899220,1cyclictest0-21swapper/109:27:361
3217899220,17cyclictest31518-21cut09:00:171
3217899220,17cyclictest29326-21bounce11:48:111
3217899220,16cyclictest5380-21ntp_offset09:10:181
3217899220,16cyclictest24743-21ls09:45:161
3217899220,16cyclictest23006-21processes11:35:181
3217899212,1cyclictest0-21swapper/107:11:431
3217899212,13cyclictest30314-21python310:55:001
32178992113,7cyclictest8395-21ls08:20:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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