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2026-08-29 - 23:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Aug 29, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28527992118,2cyclictest6814-21invoke-rc.d08:25:001
2852899204,1cyclictest20271-21sort10:40:182
2852899204,15cyclictest0-21swapper/210:10:132
2852799200,18cyclictest16780-21fschecks_count07:45:141
2852699201,18cyclictest28111-21fschecks_time10:55:150
2852899193,15cyclictest28-21ksoftirqd/210:59:172
2852899192,15cyclictest0-21swapper/207:54:452
28528991916,2cyclictest19148-21cpuspeed_turbos08:45:142
28528991914,3cyclictest0-21swapper/208:33:462
28528991914,2cyclictest4035-21H222:10:212
2852899190,18cyclictest0-21swapper/211:52:262
2852899190,18cyclictest0-21swapper/209:30:002
2852899190,16cyclictest3989-21H222:10:212
2852899190,16cyclictest3985-21H222:10:212
2852899190,16cyclictest3981-21H222:10:212
28527991914,3cyclictest3987-21H222:10:211
2852799191,15cyclictest12218-21tr09:30:121
2852799190,2cyclictest3983-21H222:10:211
2852799190,16cyclictest3989-21H222:10:211
2852799190,16cyclictest3976-21H222:10:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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