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2026-08-20 - 15:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Aug 20, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7806992724,2cyclictest1856-21systemd-udevd09:02:521
7806992724,2cyclictest1856-21systemd-udevd09:02:521
780299240,15cyclictest0-21swapper/010:44:340
780699230,18cyclictest0-21swapper/108:20:111
781199220,18cyclictest0-21swapper/210:09:142
7806992119,1cyclictest21-21ksoftirqd/109:44:321
780699204,15cyclictest0-21swapper/110:11:051
780699202,3cyclictest3030-21gmain07:17:011
780699200,17cyclictest0-21swapper/110:24:431
780299201,18cyclictest4035-21H222:10:210
781199193,15cyclictest0-21swapper/209:10:032
7811991917,1cyclictest28-21ksoftirqd/211:14:152
7811991916,1cyclictest0-21swapper/211:47:172
7811991915,3cyclictest4035-21H222:10:212
7811991914,4cyclictest3976-21H222:10:212
781199190,16cyclictest3991-21H222:10:212
7806991916,2cyclictest3985-21H222:10:211
7806991915,3cyclictest0-21swapper/112:36:501
7806991914,4cyclictest870-21systemd-logind10:04:511
780699190,16cyclictest3989-21H222:10:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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