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2026-03-29 - 08:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Mar 29, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24016992517,7cyclictest0-21swapper/219:34:082
2401499240,3cyclictest28604-21munin-run22:10:000
2401699231,16cyclictest0-21swapper/221:27:502
2401699230,2cyclictest29068-21ntp_states23:05:182
2401699230,22cyclictest2643-21expr00:15:132
2401699230,21cyclictest399-20systemd-journal22:10:002
2401499234,1cyclictest0-21swapper/000:34:150
2401499232,1cyclictest205682sleep023:50:060
24014992313,5cyclictest23564-21fschecks_time22:00:150
2401499230,3cyclictest12236-21fschecks_count19:45:150
2401499230,3cyclictest10031-21munin-run20:40:000
2401499230,2cyclictest8508-21latency_hist00:25:010
2401499230,2cyclictest8363-21expr22:30:130
2401499230,2cyclictest2773-21cut19:30:010
2401499230,2cyclictest16162-21timerandwakeup00:35:220
2401499230,17cyclictest25259-21cron20:09:000
24016992215,6cyclictest14122-21timerwakeupswit23:35:222
24016992214,7cyclictest3985-21H222:10:212
24016992214,7cyclictest27761-21smartctl19:15:162
2401699221,1cyclictest3682chrt23:14:362
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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