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2025-12-24 - 16:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Dec 24, 2025 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2303999230,22cyclictest13004-21wc10:40:130
2304999225,16cyclictest3976-21H222:10:212
2303999222,2cyclictest3981-21H222:10:210
23039992214,7cyclictest17082-21expr11:45:140
23039992214,7cyclictest0-21swapper/008:26:150
23039992214,7cyclictest0-21swapper/007:35:180
2303999220,2cyclictest5485-21latency_hist11:25:010
2303999220,21cyclictest6447-21chrt08:34:120
2303999220,21cyclictest21236-21chrt08:01:120
2303999220,16cyclictest5516-21expr12:20:140
2303999220,16cyclictest20068-21cat11:50:130
23049992117,3cyclictest0-21swapper/212:27:232
2304999210,3cyclictest0-21swapper/212:03:212
23039992114,6cyclictest8868-21chrt10:31:050
23039992114,6cyclictest24829-21kernelversion11:00:170
23039992114,6cyclictest1914-21chrt11:15:250
23039992114,6cyclictest14615-21nvmesmart_nvme012:35:200
23039992114,6cyclictest0-21swapper/011:59:020
23039992114,6cyclictest0-21swapper/011:35:000
23039992114,6cyclictest0-21swapper/010:01:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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