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2026-08-23 - 17:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Aug 23, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
621992414,6cyclictest0-21swapper/111:50:001
621992313,9cyclictest25904-21sshd08:50:141
621992312,7cyclictest15039-21chrt07:35:111
62199231,21cyclictest3450-21gsd-color10:10:191
621992311,7cyclictest9453-21chrt09:17:551
62199230,2cyclictest3746-21nfsd408:10:171
62199230,1cyclictest9603-21apt-get07:25:121
62199221,1cyclictest0-21swapper/110:01:081
62199220,2cyclictest25662-21sed12:38:591
62199220,2cyclictest16096-21uname12:20:161
62199220,2cyclictest13043-21expr11:20:131
62199220,21cyclictest23840-21nfsd408:45:181
62199220,21cyclictest18809-21tr09:35:141
62199220,21cyclictest0-21swapper/111:40:181
62199220,16cyclictest26816-21cat09:50:011
62199220,16cyclictest25727-21perf07:55:001
62199220,15cyclictest0-21swapper/110:25:171
61699227,14cyclictest0-21swapper/010:46:030
621992114,6cyclictest9544-21pzem_current08:20:211
621992114,6cyclictest7860-21sort08:20:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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