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2026-04-27 - 18:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Apr 27, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2580399240,23cyclictest0-21swapper/111:30:131
2580799214,16cyclictest7354-21basename07:35:002
25803992114,3cyclictest0-21swapper/112:01:401
25803992114,3cyclictest0-21swapper/112:01:401
2580799202,16cyclictest455-21plymouthd12:00:142
2580799202,16cyclictest455-21plymouthd12:00:132
25807992019,1cyclictest0-21swapper/208:25:152
2580799193,15cyclictest10717-21missed_timers12:25:152
2580799192,16cyclictest27831-21cat07:10:212
25807991915,3cyclictest28950-21cron11:05:012
25807991914,2cyclictest3983-21H222:10:212
2580799190,18cyclictest0-21swapper/209:10:112
2580799190,17cyclictest3987-21H222:10:212
2580799190,16cyclictest3991-21H222:10:212
2580799190,16cyclictest3979-21H222:10:212
2580399192,8cyclictest0-21swapper/107:55:171
2580399192,3cyclictest0-21swapper/109:07:281
25803991917,1cyclictest21-21ksoftirqd/111:11:491
25803991916,2cyclictest3987-21H222:10:211
2580399190,16cyclictest4035-21H222:10:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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