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2025-11-14 - 13:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Nov 14, 2025 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
300199290,19cyclictest0-21swapper/219:52:102
299999232,4cyclictest0-21swapper/022:20:000
3001992217,1cyclictest0-21swapper/222:44:552
300099220,5cyclictest16842-21cron21:30:001
3001992018,1cyclictest0-21swapper/220:06:372
3001992012,4cyclictest0-21swapper/223:02:242
300199201,18cyclictest22231-21fschecks_time22:35:162
3000992017,2cyclictest1494-21cron20:05:011
3001991917,1cyclictest0-21swapper/221:31:582
3001991916,2cyclictest4532-21H212:26:332
3001991916,2cyclictest24563-21smartctl23:35:212
3001991916,2cyclictest11852-21nfsd420:20:182
3001991912,6cyclictest8540-21fschecks_count22:10:162
300199190,18cyclictest0-21swapper/221:49:282
300199190,16cyclictest4530-21H212:26:332
300199190,16cyclictest4530-21H212:26:332
300099192,2cyclictest7308-21sessionclean22:09:001
3000991917,1cyclictest0-21swapper/119:30:221
300099191,17cyclictest0-21swapper/123:30:161
300099190,3cyclictest0-21swapper/119:25:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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