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2026-05-28 - 02:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed May 27, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
424199290,28cyclictest0-21swapper/011:35:010
424599260,1cyclictest0-21swapper/107:40:131
424199253,4cyclictest0-21swapper/008:50:010
424199240,10cyclictest0-21swapper/012:00:140
424599231,4cyclictest0-21swapper/108:15:211
424199225,2cyclictest13708-21cron08:25:010
425099214,6cyclictest0-21swapper/209:08:512
424599212,18cyclictest0-21swapper/108:30:161
424599210,3cyclictest0-21swapper/109:28:171
4241992117,3cyclictest0-21swapper/010:10:010
425099204,15cyclictest0-21swapper/210:37:542
424199203,2cyclictest31551-21timerandwakeup09:50:210
425099194,1cyclictest0-21swapper/209:42:592
425099190,1cyclictest0-21swapper/212:05:562
425099190,18cyclictest0-21swapper/211:00:202
425099190,17cyclictest2007-21systemd-journal11:08:592
424599193,15cyclictest11417-21latency11:10:161
4245991915,2cyclictest1614-21nvmesmart_nvme009:55:191
424599190,17cyclictest0-21swapper/110:39:371
424599190,15cyclictest0-21swapper/111:20:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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