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2026-07-02 - 00:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Jul 01, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20505993230,2cyclictest0-21swapper/107:50:051
20509992726,1cyclictest0-21swapper/210:15:162
20505992611,1cyclictest21-21ksoftirqd/109:51:591
2050999244,1cyclictest0-21swapper/208:45:172
2050599230,20cyclictest0-21swapper/108:04:141
2050099230,5cyclictest0-21swapper/010:44:080
20505992220,1cyclictest12416-21cut09:45:181
2050099220,18cyclictest0-21swapper/007:40:190
20505992112,6cyclictest2672-21nfsd408:30:191
2050599210,20cyclictest0-21swapper/108:25:201
2050099213,1cyclictest0-21swapper/009:05:190
2050099210,18cyclictest0-21swapper/010:05:010
2050999204,15cyclictest0-21swapper/210:52:592
20509992017,2cyclictest21662-21timerandwakeup10:00:212
2050999200,16cyclictest4099-21H222:10:212
2050599200,5cyclictest0-21swapper/107:48:121
2050599200,19cyclictest0-21swapper/112:10:131
2050099203,11cyclictest0-21swapper/012:31:130
2050099200,18cyclictest0-21swapper/009:10:370
2050999193,15cyclictest9364-21cut07:45:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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