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2026-06-02 - 22:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Jun 02, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22795992515,9cyclictest21-21ksoftirqd/108:00:591
22795992424,0cyclictest0-21swapper/112:30:171
22796992213,5cyclictest0-21swapper/208:54:522
2279599220,4cyclictest0-21swapper/110:31:101
22793992222,0cyclictest0-21swapper/008:00:580
2279699210,20cyclictest870-21systemd-logind09:18:512
2279699210,20cyclictest870-21systemd-logind08:48:512
2279399210,20cyclictest843-21systemd-network10:27:440
2279699200,17cyclictest0-21swapper/210:56:422
22795992017,2cyclictest2069-21systemd-udevd08:56:521
22793992017,2cyclictest31707-21if_lxdbr010:15:170
22793992017,2cyclictest31707-21if_lxdbr010:15:170
2279699193,15cyclictest9663-21cat09:35:172
22796991917,1cyclictest28-21ksoftirqd/209:00:212
22796991917,1cyclictest28-21ksoftirqd/209:00:202
2279699190,1cyclictest0-21swapper/208:10:132
2279699190,12cyclictest917-21sed10:20:012
2279699190,12cyclictest917-21sed10:20:002
2279599193,15cyclictest0-21swapper/109:54:571
22795991917,1cyclictest0-21swapper/112:01:521
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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