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2026-07-22 - 20:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Jul 22, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2470799223,16cyclictest3979-21H222:10:210
2470999213,11cyclictest11237-21gpgv08:40:012
24707992121,0cyclictest0-21swapper/010:10:170
2470799210,20cyclictest843-21systemd-network09:34:550
2470999204,9cyclictest0-21swapper/210:45:012
2470999203,16cyclictest0-21swapper/208:28:222
2470799200,19cyclictest14499-21snapd08:02:300
2470799200,19cyclictest14499-21snapd08:02:300
2470999193,15cyclictest0-21swapper/209:23:092
2470899193,1cyclictest3991-21H222:10:211
2470899192,16cyclictest2715-21smtpd12:13:451
24708991915,3cyclictest0-21swapper/107:16:431
2470799193,15cyclictest0-21swapper/009:09:450
2470799190,2cyclictest3976-21H222:10:210
24709991814,3cyclictest4035-21H222:10:212
24709991814,3cyclictest1522-21lxd11:44:432
24709991813,2cyclictest0-21swapper/209:00:552
2470999181,2cyclictest14505-21snapd10:20:282
2470999181,16cyclictest15964-21grep11:40:012
24708991816,1cyclictest0-21swapper/112:37:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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