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2025-11-29 - 08:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Nov 29, 2025 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3237799230,5cyclictest0-21swapper/223:12:552
3237799222,4cyclictest9005-21apache_processe23:15:112
32377992112,5cyclictest0-21swapper/219:15:212
3237799210,3cyclictest0-21swapper/220:50:142
3236899210,20cyclictest0-21swapper/022:35:170
3237299200,4cyclictest24521-21fschecks_count20:50:161
32368992018,1cyclictest9-21ksoftirqd/022:06:450
3237799194,1cyclictest0-21swapper/220:44:372
3237799192,1cyclictest0-21swapper/219:12:022
3237799192,16cyclictest4523-21H212:26:332
3237799190,18cyclictest0-21swapper/220:31:202
3237799190,16cyclictest4538-21H212:26:332
3237799190,16cyclictest4530-21H212:26:332
3237799190,16cyclictest4530-21H212:26:332
3237799190,15cyclictest0-21swapper/223:43:132
32372991915,3cyclictest4538-21H212:26:331
32372991915,3cyclictest4526-21H212:26:331
32372991914,2cyclictest4526-21H212:26:331
3237299190,1cyclictest0-21swapper/121:18:011
3237299190,1cyclictest0-21swapper/120:18:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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