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2026-01-28 - 19:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Jan 28, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6589993733,2cyclictest0-21swapper/212:25:152
6588993029,0cyclictest0-21swapper/108:30:181
6588993029,0cyclictest0-21swapper/107:25:471
6588992717,0cyclictest0-21swapper/107:20:451
6588992424,0cyclictest0-21swapper/111:30:161
658999230,18cyclictest0-21swapper/209:00:012
6589992015,3cyclictest20208-21grep12:20:132
658899205,15cyclictest0-21swapper/108:20:251
658899200,3cyclictest26098-21dump-pmu-power09:40:001
658799204,15cyclictest0-21swapper/012:00:000
6589991916,2cyclictest27217-21nfsd412:30:152
658999191,17cyclictest0-21swapper/211:10:222
658999190,1cyclictest0-21swapper/211:55:582
658999190,18cyclictest0-21swapper/208:14:542
6588991916,2cyclictest31198-21idleruntime-cro12:39:591
658899191,3cyclictest0-21swapper/112:12:241
658899190,18cyclictest0-21swapper/109:27:411
658799191,2cyclictest0-21swapper/007:20:140
658799190,1cyclictest0-21swapper/009:38:290
658999186,11cyclictest0-21swapper/210:28:532
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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