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2026-08-30 - 23:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Aug 30, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2767199236,14cyclictest0-21swapper/008:18:520
2767199236,14cyclictest0-21swapper/008:18:510
2767199202,17cyclictest28097-21fschecks_time10:00:150
2767799193,15cyclictest0-21swapper/211:08:512
27677991916,2cyclictest7952-21timerandwakeup11:15:222
2767299193,15cyclictest25471-21sh10:55:001
27672991917,1cyclictest0-21swapper/108:46:201
27672991915,1cyclictest0-21swapper/108:55:171
2767299191,3cyclictest0-21swapper/111:15:161
2767299190,3cyclictest6439-21ps12:10:191
2767299190,18cyclictest5834-21cat11:15:001
2767199196,12cyclictest0-21swapper/008:28:520
2767199190,3cyclictest20637-21grep08:50:140
2767799183,1cyclictest0-21swapper/212:07:312
2767799183,1cyclictest0-21swapper/212:07:312
2767799182,15cyclictest3976-21H222:10:212
2767799182,15cyclictest10879-21latency_hist08:35:002
2767799182,15cyclictest0-21swapper/207:15:132
27677991816,1cyclictest184742chrt12:33:142
27677991816,1cyclictest184742chrt12:33:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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