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2026-01-05 - 12:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Jan 05, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2322992525,0cyclictest0-21swapper/100:25:161
232299230,22cyclictest0-21swapper/123:45:161
232199226,15cyclictest1493-21timerwakeupswit21:00:260
2322992010,0cyclictest0-21swapper/120:13:021
232299200,16cyclictest0-21swapper/122:30:571
2321992017,2cyclictest23280-21timerwakeupswit00:30:230
2323991917,1cyclictest8211-21http_loadtime00:05:162
2323991914,3cyclictest0-21swapper/221:30:272
232399190,16cyclictest7033-21expr21:10:192
232299192,2cyclictest31668-21kernelversion23:50:161
232299190,5cyclictest0-21swapper/100:04:271
232299190,18cyclictest12937-21timerwakeupswit23:15:231
232199192,16cyclictest6941-21grep21:10:180
2321991917,1cyclictest0-21swapper/000:08:590
2321991914,3cyclictest1478-21snapd00:02:390
2323991815,3cyclictest0-21swapper/222:55:332
2323991815,2cyclictest32697-21vmstat23:50:232
232399180,1cyclictest0-21swapper/222:36:122
232399180,17cyclictest455-21plymouthd21:50:012
232399180,16cyclictest24763-21nvmesmart_nvme022:40:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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