You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-04-02 - 11:09
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Apr 02, 2026 00:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1617999254,20cyclictest0-21swapper/221:46:382
1617999254,20cyclictest0-21swapper/221:46:372
1617599253,16cyclictest20545-21kernelversion19:15:161
1617999240,1cyclictest22021-21kernelversion22:10:172
1617999240,1cyclictest22021-21kernelversion22:10:172
1617599240,19cyclictest0-21swapper/122:25:211
1617999233,1cyclictest0-21swapper/223:24:562
1617999230,5cyclictest0-21swapper/222:19:522
1617999230,5cyclictest0-21swapper/220:34:222
1617599236,16cyclictest0-21swapper/119:10:211
16179992214,7cyclictest2534-21chrt00:29:002
16179992214,6cyclictest843-21systemd-network20:27:522
1617999221,16cyclictest5242-21timerwakeupswit20:40:202
1617999220,3cyclictest0-21swapper/222:58:462
1617999220,2cyclictest8009-21sed22:40:222
1617999220,2cyclictest1085-21gdbus19:15:192
1617999220,2cyclictest10775-21chrt22:45:272
1617999220,1cyclictest0-21swapper/219:20:132
1617999220,16cyclictest7523-21grep20:45:182
1617999220,16cyclictest2996-21cat20:40:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional