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2026-04-09 - 17:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Apr 09, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7535992323,0cyclictest0-21swapper/208:28:262
7535992314,4cyclictest25971-21python312:25:002
753299220,18cyclictest0-21swapper/007:50:010
7532992121,0cyclictest0-21swapper/011:51:580
753299210,16cyclictest0-21swapper/011:19:110
753599202,17cyclictest0-21swapper/210:45:422
753599200,19cyclictest843-21systemd-network08:11:412
753399206,13cyclictest0-21swapper/108:20:131
753299203,11cyclictest0-21swapper/012:10:150
753599192,16cyclictest8042-21expr10:55:112
7535991915,3cyclictest0-21swapper/207:42:182
7535991915,1cyclictest0-21swapper/208:09:162
753599190,18cyclictest0-21swapper/211:33:392
753599190,18cyclictest0-21swapper/211:33:392
753599190,17cyclictest0-21swapper/212:25:142
753599190,16cyclictest3234-21cron11:45:002
753599190,16cyclictest0-21swapper/208:35:192
7533991915,3cyclictest0-21swapper/111:20:401
753399190,16cyclictest0-21swapper/109:11:301
7532991915,3cyclictest0-21swapper/007:52:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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