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2026-09-02 - 00:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Sep 01, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2391299240,19cyclictest7314-21fschecks_count11:25:140
2391299240,19cyclictest0-21swapper/011:15:000
2392199230,16cyclictest4036-21H222:10:212
2391299230,18cyclictest0-21swapper/011:21:300
2391699220,17cyclictest0-21swapper/111:05:151
23921992117,3cyclictest22671-21smtp09:58:022
23916992116,4cyclictest0-21swapper/108:07:371
2392199203,16cyclictest3989-21H222:10:212
23921992016,3cyclictest0-21swapper/212:13:462
2392199200,3cyclictest0-21swapper/207:46:202
2391699202,3cyclictest3370-21ls11:20:001
23916992017,2cyclictest16438-21nvmesmart_nvme011:40:201
23912992017,2cyclictest3985-21H222:10:210
2391299200,5cyclictest0-21swapper/011:15:050
23921991916,1cyclictest0-21swapper/208:50:142
23921991915,3cyclictest0-21swapper/212:29:472
23921991913,3cyclictest0-21swapper/211:34:252
2392199191,16cyclictest1829-21systemd-journal08:13:222
2392199190,3cyclictest0-21swapper/209:35:152
2392199190,2cyclictest3987-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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