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2026-01-12 - 10:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Jan 12, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14607992424,0cyclictest0-21swapper/120:45:151
14607992421,2cyclictest3874-21pzem20:40:221
1460999220,21cyclictest843-21systemd-network22:09:212
1460799220,18cyclictest0-21swapper/123:05:341
1460699220,21cyclictest843-21systemd-network19:17:110
1460799210,3cyclictest0-21swapper/121:14:261
1460799210,20cyclictest843-21systemd-network22:39:141
1460799210,20cyclictest0-21swapper/120:25:181
1460799200,19cyclictest25225-21latency_hist21:20:001
14606992018,1cyclictest0-21swapper/021:05:210
14606992016,3cyclictest0-21swapper/020:52:060
14606992014,3cyclictest0-21swapper/000:25:000
14609991919,0cyclictest0-21swapper/221:05:212
14609991916,2cyclictest6544-21mailstats23:35:212
1460999190,2cyclictest2333-21grep20:40:152
1460999190,1cyclictest0-21swapper/200:05:002
1460999190,18cyclictest3983-21H222:10:212
1460999190,16cyclictest3989-21H222:10:212
1460999190,16cyclictest3985-21H222:10:212
1460999190,16cyclictest3985-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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