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2026-01-19 - 03:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Jan 19, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1810992714,10cyclictest7181-21chrt21:10:361
181099240,3cyclictest0-21swapper/122:14:541
181099233,19cyclictest0-21swapper/100:05:241
181099232,16cyclictest24776-21seq23:35:301
1810992311,8cyclictest12925-21tune2fs20:25:141
181199220,16cyclictest0-21swapper/223:20:002
181099222,15cyclictest17858-21chrt22:26:211
1810992215,6cyclictest21305-21nfsd423:30:171
1810992212,5cyclictest32211-21grep21:00:141
181099221,20cyclictest2335-21grep19:10:151
181099221,1cyclictest0-21swapper/123:55:181
181099221,16cyclictest11823-21turbostat20:25:011
181099220,16cyclictest2901-21perf23:00:001
181099220,16cyclictest21624-21cat22:35:141
181099220,15cyclictest29311-21python322:50:001
181099220,15cyclictest0-21swapper/120:50:181
1811992114,3cyclictest0-21swapper/222:05:162
1810992114,6cyclictest31391-21grep22:50:171
1810992114,6cyclictest25332-21needreboot22:40:171
1810992114,6cyclictest15239-21ls19:30:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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