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2025-07-06 - 02:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Jul 05, 2025 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1818199230,5cyclictest0-21swapper/107:24:051
1818199228,13cyclictest0-21swapper/107:50:461
1818199228,13cyclictest0-21swapper/107:50:461
1818199220,4cyclictest0-21swapper/112:35:441
18181992116,4cyclictest28911-21apache208:25:011
18180992113,3cyclictest0-21swapper/010:05:010
1818299200,3cyclictest25213-21if_lxdbr010:10:182
1818199206,13cyclictest0-21swapper/111:06:101
18181992016,3cyclictest0-21swapper/112:20:131
1818299192,2cyclictest17764-21ntpq11:50:222
18182991910,5cyclictest0-21swapper/212:10:182
1818199192,16cyclictest29588-21cat10:20:011
18181991917,1cyclictest0-21swapper/109:25:171
18181991916,2cyclictest6940-21http_loadtime07:45:171
1818199190,2cyclictest16485-21cpuspeed_turbos11:50:171
1818299188,9cyclictest0-21swapper/211:35:162
1818299182,15cyclictest199152chrt10:56:032
1818299182,15cyclictest0-21swapper/210:54:222
1818299182,15cyclictest0-21swapper/210:54:222
18182991815,2cyclictest902-21nfsd408:30:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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