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2026-08-25 - 20:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Aug 25, 2026 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2519899230,5cyclictest0-21swapper/211:10:132
2519499230,5cyclictest0-21swapper/011:22:460
2519899220,21cyclictest843-21systemd-network10:37:052
2519499226,2cyclictest3053-21systemd-logind08:28:520
2519499220,4cyclictest0-21swapper/010:20:000
2519899216,14cyclictest0-21swapper/210:46:052
25195992112,0cyclictest0-21swapper/110:01:321
25194992114,4cyclictest0-21swapper/010:42:030
2519499210,0cyclictest9-21ksoftirqd/009:20:030
2519499202,3cyclictest26885-21ntpq07:10:170
25198991917,1cyclictest28-21ksoftirqd/207:51:302
25198991916,2cyclictest16537-21grep10:40:152
2519899191,17cyclictest19111-21nfsd408:50:182
2519899191,11cyclictest6758-21latency_hist07:35:002
2519899190,18cyclictest0-21swapper/207:45:522
25195991916,2cyclictest13920-21cstates09:40:151
2519499192,2cyclictest23288-21sed09:00:020
2519499192,16cyclictest1840-21munin-plugin-st09:20:000
25194991917,1cyclictest0-21swapper/008:34:270
25194991916,2cyclictest21291-21latency_hist10:50:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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