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2025-12-09 - 02:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Dec 08, 2025 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17288993433,0cyclictest0-21swapper/012:10:140
17288993433,0cyclictest0-21swapper/012:10:140
17292992313,9cyclictest26476-21kworker/2:108:08:302
1729099236,2cyclictest20297-21latency_hist08:10:011
17288992320,2cyclictest6510-21cat07:45:170
1728899230,5cyclictest0-21swapper/009:05:140
1728899221,4cyclictest0-21swapper/011:00:000
1728899220,18cyclictest0-21swapper/011:35:180
1729299204,15cyclictest0-21swapper/212:13:392
1729299204,15cyclictest0-21swapper/212:13:382
17292992010,1cyclictest0-21swapper/211:46:042
1729099202,17cyclictest0-21swapper/108:15:011
17290991916,1cyclictest0-21swapper/111:35:151
17288991917,1cyclictest0-21swapper/009:48:230
17288991917,1cyclictest0-21swapper/009:10:210
1728899190,2cyclictest11735-21latency_hist10:45:000
1728899190,18cyclictest0-21swapper/011:31:470
1729299182,15cyclictest0-21swapper/209:51:372
1729299182,15cyclictest0-21swapper/209:18:382
17292991816,1cyclictest0-21swapper/210:03:312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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