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2026-06-08 - 07:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Jun 08, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3065992624,1cyclictest0-21swapper/221:55:192
306599220,8cyclictest0-21swapper/220:54:502
3054992220,1cyclictest0-21swapper/020:00:190
305499220,18cyclictest0-21swapper/022:01:200
306599210,2cyclictest29357-21apt-key22:50:002
305499210,4cyclictest399-20systemd-journal19:35:000
3065992017,2cyclictest22503-21date21:40:012
3065992017,2cyclictest22503-21date21:40:012
306599193,11cyclictest26487-21munin-run20:50:012
306599192,13cyclictest0-21swapper/221:52:152
3065991916,2cyclictest3429-21tr21:05:132
306199193,15cyclictest22776-21switchtime22:35:221
306199192,16cyclictest0-21swapper/119:26:411
306199192,16cyclictest0-21swapper/119:26:411
3061991917,1cyclictest21-21ksoftirqd/100:21:571
3054991916,2cyclictest3414-21master20:36:480
306599182,1cyclictest69782chrt22:09:352
306599182,15cyclictest3991-21H222:10:212
306599182,15cyclictest28-21ksoftirqd/223:05:012
306599182,15cyclictest17987-21idleruntime21:30:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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