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2026-08-26 - 20:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Aug 26, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26202992515,6cyclictest0-21swapper/209:50:192
26202992219,2cyclictest29041-21sessionclean09:09:002
26202992218,3cyclictest399-20systemd-journal11:20:012
26202992218,3cyclictest22755-21wc10:50:212
26193992214,3cyclictest0-21swapper/011:30:160
2619399221,17cyclictest0-21swapper/010:35:000
2620299214,16cyclictest17623-21fschecks_time07:50:152
2620299214,16cyclictest0-21swapper/210:13:222
2620299213,3cyclictest25107-21munin-plugin-st10:00:012
26202992118,2cyclictest2282-21sed07:25:012
26202992118,2cyclictest1156-21http12:10:012
2619799214,16cyclictest0-21swapper/110:25:551
2619399215,15cyclictest25718-21ls11:55:120
2620299203,16cyclictest3396-21cat09:20:142
2620299203,16cyclictest3396-21cat09:20:142
2620299203,16cyclictest26687-21expr07:10:142
2620299203,16cyclictest16620-21expr12:35:132
26202992017,2cyclictest9348-21cut07:35:172
26202992017,2cyclictest9348-21cut07:35:172
26202992017,2cyclictest848-21sed11:10:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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