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2025-09-17 - 07:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Sep 17, 2025 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
464499254,13cyclictest0-21swapper/019:15:220
4644992414,5cyclictest0-21swapper/020:55:170
465699230,20cyclictest0-21swapper/222:22:072
4651992214,4cyclictest0-21swapper/122:37:031
4656992112,0cyclictest0-21swapper/223:10:562
464499206,13cyclictest0-21swapper/023:50:470
464499200,9cyclictest0-21swapper/000:10:490
465699192,2cyclictest32065-21proc_pri21:50:212
465699192,2cyclictest1764-21nfsd420:00:192
4656991917,1cyclictest0-21swapper/219:36:442
465699190,2cyclictest4528-21H212:26:332
465699190,16cyclictest4528-21H212:26:332
464499190,3cyclictest0-21swapper/020:05:180
465699182,15cyclictest28-21ksoftirqd/222:30:442
4656991816,1cyclictest0-21swapper/223:30:192
4656991816,1cyclictest0-21swapper/221:28:562
4656991815,2cyclictest20956-21processes21:30:222
4656991814,3cyclictest4536-21H212:26:332
4656991813,3cyclictest10988-21nfsd420:15:212
465699180,17cyclictest4538-21H212:26:332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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