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2026-04-12 - 19:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Apr 12, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1052599247,16cyclictest21849-21mii-tool12:15:151
1052599230,5cyclictest0-21swapper/111:00:021
1052599220,18cyclictest0-21swapper/111:17:261
1052999214,13cyclictest10793-21latency_hist11:00:002
1052599210,3cyclictest0-21swapper/109:16:151
1052099202,1cyclictest0-21swapper/011:01:060
1052999192,2cyclictest21968-21chrt09:21:572
1052999192,16cyclictest376-21smtpd07:49:292
1052599192,1cyclictest0-21swapper/108:51:571
1052599190,5cyclictest0-21swapper/111:30:001
1052599190,5cyclictest0-21swapper/109:06:391
1052599190,3cyclictest0-21swapper/108:29:221
1052599190,17cyclictest426-21systemd-udevd09:48:511
1052099193,15cyclictest0-21swapper/011:06:180
10520991915,3cyclictest0-21swapper/008:29:130
10520991914,3cyclictest0-21swapper/009:25:220
1052099190,17cyclictest3976-21H222:10:210
10529991815,2cyclictest30253-21if_lxdbr008:40:162
10529991815,2cyclictest29803-21chrt07:41:132
1052999181,16cyclictest8297-21wc11:50:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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