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2026-07-17 - 12:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Jul 17, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2272499310,0cyclictest0-21swapper/123:05:141
22718993027,2cyclictest14550-21snapd21:45:280
22724992724,2cyclictest31808-21python321:20:001
2272499242,20cyclictest16833-21grep19:55:121
2272999230,22cyclictest0-21swapper/222:24:432
2272999230,22cyclictest0-21swapper/221:33:482
2272999230,18cyclictest16089-21nfsd400:35:182
2272999214,16cyclictest0-21swapper/220:38:382
22718992119,1cyclictest20057-21kworker/0:021:20:010
22729992018,1cyclictest0-21swapper/222:03:352
22729992017,2cyclictest30625-21plymouth22:10:212
22729992016,3cyclictest3339-21ls20:30:012
22729992016,3cyclictest3339-21ls20:30:002
22729992014,5cyclictest0-21swapper/222:05:152
22729992014,3cyclictest0-21swapper/200:30:222
22729992013,6cyclictest843-21systemd-network00:14:152
2272499204,15cyclictest0-21swapper/120:47:511
2271899202,15cyclictest0-21swapper/023:40:180
2272999192,16cyclictest0-21swapper/220:22:282
22729991917,1cyclictest0-21swapper/219:35:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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