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2026-06-10 - 21:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Jun 10, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15745993130,0cyclictest0-21swapper/110:51:231
1574699243,20cyclictest0-21swapper/210:50:502
1574699241,2cyclictest28444-21ps07:30:192
1574699240,23cyclictest29478-21fschecks_count08:30:132
1574699240,23cyclictest29478-21fschecks_count08:30:132
1574699230,2cyclictest4651-21apt-get12:35:002
1574699230,22cyclictest17559-21dpkg12:00:012
1574699230,22cyclictest0-21swapper/210:30:162
1574699230,1cyclictest0-21swapper/212:30:202
1574699230,1cyclictest0-21swapper/209:20:002
1574699230,17cyclictest11399-21sshd07:58:392
1574499230,5cyclictest0-21swapper/007:15:140
1574699224,17cyclictest0-21swapper/208:04:562
15746992214,7cyclictest30513-21expr09:30:132
1574699220,2cyclictest25584-21gzip08:25:012
1574699220,2cyclictest2285-21timerwakeupswit11:30:212
1574699220,2cyclictest17385-21perf10:05:012
1574699220,2cyclictest14923-21cat10:00:012
1574699220,21cyclictest2781-21cat07:45:012
1574699220,21cyclictest0-21swapper/210:20:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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