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2026-06-05 - 05:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Jun 05, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1713992414,7cyclictest3789-21cpuspeed_turbos22:05:130
171699225,13cyclictest0-21swapper/219:10:122
1715992219,2cyclictest26616-21tlsmgr20:29:121
1713992216,5cyclictest0-21swapper/019:50:010
1713992213,7cyclictest4099-21H222:10:210
171699210,20cyclictest843-21systemd-network00:00:012
1716992014,5cyclictest0-21swapper/221:35:052
171699200,17cyclictest2007-21systemd-journal21:17:342
171399203,11cyclictest20989-21munin-run00:30:000
171399201,5cyclictest0-21swapper/023:00:180
171699194,1cyclictest28-21ksoftirqd/220:36:032
171699193,15cyclictest0-21swapper/223:28:552
171699192,1cyclictest0-21swapper/221:50:182
1716991917,1cyclictest0-21swapper/223:08:372
1716991916,2cyclictest27270-21munin-plugin-st21:50:012
171699190,3cyclictest0-21swapper/222:35:372
171699190,2cyclictest4099-21H222:10:212
171699190,2cyclictest3987-21H222:10:212
171699190,16cyclictest4035-21H222:10:212
171699190,16cyclictest4035-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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