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2026-07-11 - 05:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Jul 11, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13071992613,12cyclictest0-21swapper/020:45:160
13080992424,0cyclictest0-21swapper/220:55:162
13080992424,0cyclictest0-21swapper/220:55:162
1307599240,19cyclictest0-21swapper/121:45:171
1308099230,5cyclictest0-21swapper/219:37:342
1308099230,22cyclictest0-21swapper/223:56:362
1308099210,20cyclictest843-21systemd-network22:47:552
1307599216,13cyclictest0-21swapper/123:25:191
1307199210,20cyclictest843-21systemd-network00:04:070
13080992017,2cyclictest25810-21grep00:15:142
1307199204,9cyclictest0-21swapper/021:05:180
1307199202,17cyclictest0-21swapper/021:30:010
13080991917,1cyclictest0-21swapper/220:30:452
13080991917,1cyclictest0-21swapper/220:30:442
1308099190,18cyclictest19176-21tr00:05:142
1307599193,15cyclictest21792-21expr19:25:141
1307599192,2cyclictest5428-21cut00:35:181
1307599192,16cyclictest14550-21snapd20:37:571
13075991916,2cyclictest26931-21gpgv20:30:011
13075991916,2cyclictest26931-21gpgv20:30:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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