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2026-07-05 - 03:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Jul 05, 2026 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1706199246,2cyclictest3991-21H222:10:212
1706199231,17cyclictest28-21ksoftirqd/221:40:132
1705799230,22cyclictest843-21systemd-network20:33:261
17052992322,0cyclictest0-21swapper/021:10:170
1705299220,21cyclictest0-21swapper/019:19:490
17061992118,2cyclictest3987-21H222:10:212
1706199210,3cyclictest0-21swapper/200:30:152
1706199210,1cyclictest0-21swapper/200:14:542
1705299210,5cyclictest0-21swapper/023:20:120
1706199204,2cyclictest3991-21H222:10:212
17061992018,1cyclictest0-21swapper/200:15:282
17052992017,2cyclictest4035-21H222:10:210
1705299201,4cyclictest17353-21uname22:00:170
17061991919,0cyclictest0-21swapper/221:10:172
17061991918,0cyclictest0-21swapper/223:31:002
17061991916,2cyclictest26973-21open_files19:25:192
1706199190,2cyclictest4035-21H222:10:212
1706199190,2cyclictest3981-21H222:10:212
1706199190,2cyclictest3976-21H222:10:212
1706199190,2cyclictest3976-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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