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2026-06-21 - 18:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Jun 21, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
739999230,5cyclictest0-21swapper/107:11:581
739999230,20cyclictest0-21swapper/110:02:331
739899230,3cyclictest0-21swapper/011:45:470
7399992217,2cyclictest29881-21kernelversion08:45:171
739999214,2cyclictest25581-21ldconfig.real08:40:001
7399992114,3cyclictest0-21swapper/109:28:131
739899214,3cyclictest0-21swapper/008:08:190
740499204,15cyclictest0-21swapper/208:35:172
740499203,2cyclictest15749-21nvmesmart_nvme008:20:212
739999200,5cyclictest399-20systemd-journal12:20:081
739999200,5cyclictest399-20systemd-journal12:20:071
739999200,1cyclictest0-21swapper/111:26:341
739899202,17cyclictest0-21swapper/011:44:200
7398992018,1cyclictest9-21ksoftirqd/009:25:110
7398992018,1cyclictest9-21ksoftirqd/007:29:040
739899201,4cyclictest10167-21grep08:10:180
7398992012,4cyclictest0-21swapper/011:12:080
739899201,16cyclictest7799-21sort09:00:230
739899200,5cyclictest0-21swapper/008:35:190
739899200,18cyclictest0-21swapper/011:18:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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