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2026-01-22 - 00:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Jan 21, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1284999245,13cyclictest0-21swapper/111:08:491
1284999230,22cyclictest843-21systemd-network09:31:001
1284999230,22cyclictest0-21swapper/111:24:121
1284999220,21cyclictest843-21systemd-network08:50:491
1284899220,21cyclictest843-21systemd-network09:17:050
1285099210,3cyclictest0-21swapper/211:17:172
12849992117,3cyclictest0-21swapper/107:21:381
12849992113,7cyclictest843-21systemd-network10:42:051
1284899210,17cyclictest0-21swapper/010:05:130
1284999203,16cyclictest0-21swapper/110:11:091
1284999200,3cyclictest4035-21H222:10:211
1284899203,1cyclictest0-21swapper/010:53:440
1285099193,15cyclictest28-21ksoftirqd/209:53:292
1285099193,10cyclictest31948-21python312:30:002
1285099192,16cyclictest0-21swapper/208:29:462
12850991916,2cyclictest4099-21H222:10:212
1285099190,2cyclictest4099-21H222:10:212
1285099190,2cyclictest3983-21H222:10:212
1285099190,18cyclictest0-21swapper/208:53:332
1285099190,16cyclictest3987-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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