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2026-06-26 - 22:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Jun 26, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32274993129,0cyclictest0-21swapper/111:01:111
32274993028,2cyclictest0-21swapper/110:07:451
32274992927,2cyclictest0-21swapper/110:11:441
32274992919,10cyclictest0-21swapper/110:44:271
32274992827,0cyclictest0-21swapper/110:18:331
32274992818,0cyclictest0-21swapper/109:14:111
32275992710,16cyclictest3987-21H222:10:212
32274992718,9cyclictest21-21ksoftirqd/109:05:551
32275992610,15cyclictest28-21ksoftirqd/209:12:542
32274992617,0cyclictest0-21swapper/108:50:551
32274992616,10cyclictest0-21swapper/111:15:451
32274992516,9cyclictest0-21swapper/108:12:271
3227499250,20cyclictest21545-21fschecks_time11:35:141
32274992415,9cyclictest21-21ksoftirqd/109:42:431
32274992415,9cyclictest0-21swapper/109:52:381
32274992415,0cyclictest0-21swapper/108:42:431
3227399242,21cyclictest532-21chrt07:10:130
32273992422,1cyclictest3660-21cut09:10:000
3227399240,5cyclictest29428-21uname08:00:170
3227599236,11cyclictest0-21swapper/211:08:532
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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