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2026-01-29 - 07:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Jan 29, 2026 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2171799230,5cyclictest0-21swapper/022:43:210
21717992214,7cyclictest870-21systemd-logind19:16:510
21719992120,0cyclictest0-21swapper/222:30:522
2171999210,18cyclictest10161-21turbostat21:40:012
2171899210,18cyclictest23350-21nfsd419:10:181
2171799215,14cyclictest0-21swapper/021:25:130
2171999200,17cyclictest20297-21perf22:55:002
21718992017,2cyclictest14075-21nfsd419:50:171
2171899200,19cyclictest870-21systemd-logind19:20:191
21717992016,3cyclictest0-21swapper/023:58:020
2171999194,14cyclictest0-21swapper/200:08:052
2171999194,14cyclictest0-21swapper/200:08:042
2171999192,16cyclictest3976-21H222:10:212
2171999192,16cyclictest0-21swapper/219:20:162
21719991917,1cyclictest0-21swapper/219:40:062
21719991915,3cyclictest1551-21snapd00:18:002
2171999190,16cyclictest3991-21H222:10:212
2171899192,16cyclictest0-21swapper/121:55:411
21718991916,2cyclictest5463-21cat23:25:001
21718991915,3cyclictest0-21swapper/123:58:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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