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2026-07-21 - 19:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Jul 21, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2600699239,13cyclictest0-21swapper/210:00:412
2599799230,19cyclictest0-21swapper/007:23:370
2600699220,21cyclictest843-21systemd-network08:23:412
2599799220,18cyclictest0-21swapper/007:51:170
2600199210,20cyclictest843-21systemd-network12:36:161
2599799214,11cyclictest0-21swapper/007:25:240
25997992117,2cyclictest5088-21sed08:25:010
2599799210,3cyclictest0-21swapper/012:26:200
26006992017,2cyclictest20608-21ntp_kernel_pll_08:50:192
26006992017,2cyclictest20608-21ntp_kernel_pll_08:50:192
2599799204,15cyclictest0-21swapper/010:31:510
25997992017,2cyclictest4035-21H222:10:210
25997992014,5cyclictest0-21swapper/010:25:010
26006991917,1cyclictest28-21ksoftirqd/209:04:422
26006991917,1cyclictest0-21swapper/210:48:192
26006991914,4cyclictest8385-21wc08:30:162
2600699190,18cyclictest0-21swapper/212:27:502
2600699190,16cyclictest3981-21H222:10:212
2600699190,16cyclictest3979-21H222:10:212
2600699190,16cyclictest0-21swapper/207:20:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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