You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-07 - 21:46
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Jan 07, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
820999270,21cyclictest19628-21chrt09:21:422
820799260,25cyclictest0-21swapper/009:00:130
820999250,0cyclictest0-21swapper/210:25:172
8209992414,9cyclictest16640-21http_loadtime08:20:162
820999238,1cyclictest0-21swapper/207:20:122
820999232,1cyclictest0-21swapper/207:53:522
8209992320,2cyclictest8536-21cpuspeed_turbos11:55:142
8209992317,5cyclictest0-21swapper/208:45:182
8209992314,8cyclictest27945-21fschecks_time10:35:162
8209992314,8cyclictest22553-21cat12:20:132
820999230,5cyclictest0-21swapper/207:15:002
820999230,2cyclictest32532-21if_enp1s011:40:132
820999230,22cyclictest21395-21idleruntime11:20:172
8209992217,4cyclictest0-21swapper/210:50:142
8209992214,7cyclictest4346-21chrt08:55:152
8209992214,7cyclictest29290-21expr11:35:112
8209992214,7cyclictest0-21swapper/210:30:222
820999221,16cyclictest28719-21missed_timers12:30:162
820999220,2cyclictest7820-21grep09:00:182
820999220,2cyclictest562-21sed12:40:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional