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2026-08-10 - 10:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Aug 10, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1048099251,6cyclictest32455-21grep20:45:192
1047999247,16cyclictest28931-21latency23:30:181
10480992213,0cyclictest0-21swapper/222:25:162
1047999220,17cyclictest0-21swapper/121:30:201
10479992115,3cyclictest0-21swapper/122:13:081
1047899210,5cyclictest0-21swapper/023:30:010
1048099202,17cyclictest5915-21expr22:50:132
10480992020,0cyclictest0-21swapper/200:20:002
10480992016,1cyclictest0-21swapper/221:50:112
1048099200,2cyclictest3976-21H222:10:212
10480991917,1cyclictest0-21swapper/220:15:182
10480991917,1cyclictest0-21swapper/219:40:282
10480991916,2cyclictest26881-21/usr/sbin/munin00:25:222
10480991915,3cyclictest0-21swapper/222:36:172
10480991915,3cyclictest0-21swapper/221:25:182
10480991913,3cyclictest0-21swapper/220:25:182
1048099190,18cyclictest0-21swapper/223:39:042
1048099190,16cyclictest3981-21H222:10:212
1047999192,2cyclictest28287-21date20:40:001
1047999192,1cyclictest0-21swapper/120:25:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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