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2026-06-16 - 13:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Jun 16, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28126992626,0cyclictest0-21swapper/222:15:182
2812699230,5cyclictest0-21swapper/223:25:202
28124992322,1cyclictest13358-21mii-tool00:25:140
2812599220,22cyclictest0-21swapper/123:35:101
2812499220,21cyclictest0-21swapper/022:47:150
28126992112,5cyclictest0-21swapper/220:05:012
2812599214,16cyclictest21-21ksoftirqd/122:15:191
2812599210,20cyclictest843-21systemd-network23:49:501
2812499210,3cyclictest0-21swapper/020:21:300
2812599200,18cyclictest18664-21latency_hist21:45:011
2812599200,18cyclictest18664-21latency_hist21:45:011
28124992017,2cyclictest30740-21latency_hist19:15:010
2812499200,17cyclictest0-21swapper/021:48:360
2812499200,16cyclictest0-21swapper/021:42:430
2812499200,16cyclictest0-21swapper/021:42:430
2812699194,1cyclictest0-21swapper/222:43:322
2812699192,2cyclictest3979-21H222:10:212
2812699192,1cyclictest0-21swapper/219:19:482
2812699191,16cyclictest0-21swapper/223:55:002
2812699190,16cyclictest3987-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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