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2026-05-15 - 03:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu May 14, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3360993517,17cyclictest0-21swapper/007:30:120
336099240,0cyclictest0-21swapper/012:30:120
336799230,18cyclictest0-21swapper/111:43:391
336099220,18cyclictest0-21swapper/012:19:500
336799210,3cyclictest0-21swapper/107:25:181
336099210,3cyclictest11707-21nvmesmart_nvme012:05:170
336099210,20cyclictest0-21swapper/011:18:470
336099210,18cyclictest0-21swapper/008:55:190
336099204,15cyclictest0-21swapper/011:45:150
336099203,11cyclictest9359-21munin-run10:10:010
336099202,17cyclictest0-21swapper/011:20:160
3360992018,1cyclictest0-21swapper/010:00:120
337299193,15cyclictest16070-21grep12:15:122
337299192,2cyclictest24227-21fschecks_time07:45:132
337299190,17cyclictest5307-21python311:00:012
3367991914,4cyclictest4649-21iwlist07:10:161
336799190,16cyclictest3976-21H222:10:211
336099192,9cyclictest14022-21python311:15:000
337299182,15cyclictest4608-21idleruntime07:10:172
337299182,15cyclictest28-21ksoftirqd/207:19:442
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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