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2026-02-19 - 12:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Feb 19, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17826992717,0cyclictest0-21swapper/120:56:071
17826992515,10cyclictest21-21ksoftirqd/122:04:571
17826992515,10cyclictest17441-21kworker/u16:022:34:201
1782599253,4cyclictest0-21swapper/000:30:000
17826992314,6cyclictest0-21swapper/120:30:151
17830992215,4cyclictest0-21swapper/219:55:562
1782599220,5cyclictest0-21swapper/021:10:190
1783099210,20cyclictest0-21swapper/219:40:202
1782699213,11cyclictest13769-21munin-run22:50:011
1783099200,19cyclictest18897-21if_lxdbr022:00:162
1782599204,15cyclictest0-21swapper/023:00:070
1782599201,15cyclictest0-21swapper/019:20:270
1783099194,1cyclictest0-21swapper/222:40:182
1783099194,1cyclictest0-21swapper/222:40:182
1783099192,2cyclictest968-21perf23:25:002
1783099192,1cyclictest0-21swapper/219:26:572
1783099192,15cyclictest13598-21fschecks_time20:55:162
17830991917,1cyclictest0-21swapper/219:50:012
17830991916,2cyclictest9158-21grep21:45:002
1783099191,3cyclictest21441-21grep21:10:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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