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2026-07-08 - 02:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Jul 07, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
792099262,19cyclictest31786-21cat12:35:010
792199230,5cyclictest0-21swapper/112:25:221
792099214,1cyclictest0-21swapper/008:09:560
792099214,1cyclictest0-21swapper/008:09:560
7921992012,7cyclictest843-21systemd-network11:58:551
7921992012,7cyclictest843-21systemd-network11:58:541
792299192,3cyclictest0-21swapper/209:00:002
792299192,16cyclictest27062-21smtpd11:25:522
7922991917,1cyclictest0-21swapper/208:25:012
7922991914,4cyclictest29214-21grep10:35:142
792299190,1cyclictest0-21swapper/211:39:172
7921991917,1cyclictest0-21swapper/110:45:121
7921991917,1cyclictest0-21swapper/109:00:141
7921991916,2cyclictest16478-21perf11:10:011
7921991915,3cyclictest0-21swapper/109:35:191
7920991916,2cyclictest0-21swapper/007:52:580
7920991915,3cyclictest2945-21cpuspeed_turbos10:45:130
7920991913,5cyclictest0-21swapper/011:00:000
792299182,2cyclictest25946-21date10:30:002
792299182,15cyclictest0-21swapper/208:52:582
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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