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2026-02-03 - 12:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Feb 03, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1869899230,5cyclictest0-21swapper/100:25:311
18697992117,3cyclictest0-21swapper/000:39:550
18697992016,3cyclictest0-21swapper/021:05:000
1869999192,2cyclictest2069-21systemd-udevd19:18:522
1869999192,2cyclictest18987-21expr23:55:132
1869999192,16cyclictest30682-21idleruntime19:30:162
18699991915,3cyclictest6361-21latency22:35:172
18699991912,3cyclictest0-21swapper/219:20:182
1869999190,18cyclictest399-20systemd-journal19:49:492
1869899193,1cyclictest9505-21date00:34:591
18698991914,2cyclictest3983-21H222:10:211
1869899190,18cyclictest0-21swapper/123:16:461
1869899190,18cyclictest0-21swapper/100:20:031
18697991917,1cyclictest0-21swapper/022:54:240
1869799190,16cyclictest13061-21cat23:45:010
1869999182,15cyclictest7307-21cat20:40:232
18699991815,2cyclictest31776-21ls20:30:012
18699991814,3cyclictest3351-21lxd21:18:502
18699991814,3cyclictest24157-21dpkg00:05:012
1869999181,16cyclictest20115-21smtp22:02:072
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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