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2026-06-20 - 18:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Jun 20, 2026 12:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7447992927,1cyclictest0-21swapper/010:25:020
745699230,5cyclictest271rcuc/207:16:162
744799230,5cyclictest0-21swapper/008:11:570
744799220,18cyclictest0-21swapper/007:44:580
7456992119,1cyclictest28-21ksoftirqd/208:50:012
745199210,17cyclictest0-21swapper/112:37:171
744799214,16cyclictest14417-21gpgconf08:20:010
744799210,3cyclictest0-21swapper/009:43:190
744799210,18cyclictest0-21swapper/010:18:030
745699203,11cyclictest17378-21updatedb.mlocat08:25:012
745699203,11cyclictest17378-21updatedb.mlocat08:25:002
745699202,17cyclictest0-21swapper/211:30:142
745699200,19cyclictest399-20systemd-journal12:02:422
745199204,15cyclictest0-21swapper/110:21:181
744799204,15cyclictest0-21swapper/008:35:030
744799203,16cyclictest14193-21sh11:09:000
744799203,16cyclictest0-21swapper/010:24:040
744799202,17cyclictest0-21swapper/012:09:130
744799202,17cyclictest0-21swapper/011:15:140
7447992017,2cyclictest8119-21cpuspeed_turbos10:00:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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