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2026-07-29 - 04:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Jul 29, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17808993028,1cyclictest0-21swapper/219:20:152
1780199226,13cyclictest0-21swapper/121:15:161
1779999220,20cyclictest870-21systemd-logind21:26:520
17808992118,2cyclictest26007-21sshd23:11:492
17799992119,1cyclictest9-21ksoftirqd/000:20:010
1780199202,17cyclictest15817-21tr22:55:151
1780199200,1cyclictest3450-21gsd-color21:30:131
17799992016,1cyclictest0-21swapper/020:21:440
1779999200,18cyclictest455-21plymouthd20:40:190
1780899192,2cyclictest2872-21systemd-logind00:22:512
17808991917,1cyclictest0-21swapper/221:40:002
17808991916,2cyclictest20804-21munin-run21:10:002
17808991915,3cyclictest8305-21cat19:50:012
1780899191,17cyclictest30692-21cpuspeed_turbos20:30:142
1780899190,5cyclictest0-21swapper/219:31:552
17801991916,2cyclictest27002-21cat00:10:161
1779999192,1cyclictest0-21swapper/022:00:180
1779999190,1cyclictest0-21swapper/023:13:310
1780899182,15cyclictest0-21swapper/221:56:012
17808991816,1cyclictest0-21swapper/222:20:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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