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2026-04-20 - 12:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Apr 20, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1669299225,11cyclictest0-21swapper/022:10:210
1670399216,1cyclictest0-21swapper/220:16:212
1669799212,18cyclictest0-21swapper/120:17:061
1669299210,18cyclictest0-21swapper/022:51:540
16692992016,3cyclictest0-21swapper/022:49:540
16692992013,4cyclictest0-21swapper/021:31:530
1670399193,15cyclictest28-21ksoftirqd/220:00:172
1670399192,16cyclictest25729-21fschecks_time00:10:152
16703991917,1cyclictest28-21ksoftirqd/200:20:542
1670399190,5cyclictest870-21systemd-logind21:56:522
1670399190,4cyclictest426-21systemd-udevd19:12:522
1669799193,15cyclictest0-21swapper/119:41:101
1669799192,1cyclictest0-21swapper/122:16:391
16697991913,4cyclictest0-21swapper/119:17:471
1669799190,4cyclictest399-20systemd-journal22:30:011
1669799190,18cyclictest0-21swapper/100:13:561
16692991916,1cyclictest0-21swapper/023:15:490
1669299191,3cyclictest0-21swapper/020:47:240
1669299191,16cyclictest0-21swapper/022:55:140
1669299190,16cyclictest4099-21H222:10:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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