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2026-02-08 - 09:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Feb 08, 2026 00:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1165299247,11cyclictest0-21swapper/223:20:162
1165299247,11cyclictest0-21swapper/223:20:152
1164699240,23cyclictest17883-21latency_hist00:05:001
1164399242,2cyclictest28400-21cat23:25:170
1164699231,7cyclictest31199-21cut22:35:141
11646992314,8cyclictest12754-21cat23:00:011
11646992314,8cyclictest12754-21cat23:00:001
1164699231,21cyclictest29158-21mailstats23:25:211
1164699230,8cyclictest18083-21cut19:20:141
1164699230,22cyclictest7028-21latency_hist22:50:001
1164699230,22cyclictest3299-21cut22:40:191
1164699230,22cyclictest13922-21sed23:00:161
1164399233,19cyclictest0-21swapper/022:48:150
11643992312,6cyclictest2489-21expr19:50:130
1164399230,22cyclictest0-21swapper/022:34:520
1164399230,1cyclictest0-21swapper/023:10:010
1164399230,16cyclictest18514-21tune2fs19:20:170
1164399230,16cyclictest12977-21dpkg23:00:120
1164699221,20cyclictest0-21swapper/123:40:121
1164699220,7cyclictest9748-21sed21:00:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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