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2026-07-10 - 03:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Jul 10, 2026 00:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4022992421,2cyclictest20930-21grep23:25:181
4022992421,2cyclictest20930-21grep23:25:171
402999230,5cyclictest0-21swapper/221:47:032
402999230,5cyclictest0-21swapper/221:47:032
402299236,13cyclictest0-21swapper/100:14:091
402999220,4cyclictest0-21swapper/220:35:162
402999220,18cyclictest0-21swapper/220:55:152
402299210,17cyclictest0-21swapper/120:13:081
4029992018,1cyclictest0-21swapper/221:06:582
4029992017,2cyclictest30956-21tr22:45:202
4022992018,1cyclictest21-21ksoftirqd/119:31:501
402199202,2cyclictest28105-21cpuspeed_turbos23:40:140
4021992015,3cyclictest6684-21grep19:15:000
402999193,2cyclictest3981-21H222:10:212
402999192,16cyclictest3989-21H222:10:212
402999192,16cyclictest3983-21H222:10:212
402999192,16cyclictest10075-21cut19:20:122
402999192,16cyclictest0-21swapper/223:09:142
402999190,16cyclictest3983-21H222:10:212
402999190,16cyclictest3983-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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