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2026-05-22 - 18:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri May 22, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27971993120,10cyclictest0-21swapper/120:15:011
27971992918,10cyclictest16254-21grep19:45:141
27971992415,9cyclictest0-21swapper/120:56:171
2796799224,2cyclictest3991-21H222:10:210
2796799220,6cyclictest0-21swapper/022:34:280
2797699215,7cyclictest0-21swapper/221:44:422
27976992016,3cyclictest3976-21H222:10:212
27971992017,2cyclictest3981-21H222:10:211
27971992017,2cyclictest21-21ksoftirqd/123:02:561
2797199201,4cyclictest6875-21python321:25:011
2797699193,15cyclictest3989-21H222:10:212
2797699193,15cyclictest28-21ksoftirqd/220:40:332
2797699193,15cyclictest0-21swapper/222:05:002
2797699193,15cyclictest0-21swapper/220:25:022
27976991917,1cyclictest0-21swapper/219:15:112
27976991915,3cyclictest4032-21accounts22:10:212
2797699190,16cyclictest3991-21H222:10:212
27971991917,1cyclictest22783-21awk21:50:191
27971991917,1cyclictest0-21swapper/119:16:211
2797199191,3cyclictest3954-21VM22:10:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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