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2026-08-12 - 11:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Aug 12, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3033499304,8cyclictest0-21swapper/000:09:160
3033699230,20cyclictest11190-21nfsd421:25:202
3033699224,17cyclictest0-21swapper/219:42:562
3033699223,18cyclictest0-21swapper/220:40:182
30335992213,5cyclictest0-21swapper/121:18:501
3033599220,21cyclictest843-21systemd-network20:20:421
3033599220,17cyclictest30939-21cpuspeed_turbos23:00:111
30334992217,5cyclictest0-21swapper/022:10:010
30335992119,1cyclictest21-21ksoftirqd/122:35:281
30335992111,9cyclictest0-21swapper/121:55:091
3033599210,4cyclictest0-21swapper/123:18:561
3033499214,16cyclictest2462-21cpuspeed_turbos20:15:150
3033699202,17cyclictest0-21swapper/219:19:122
3033699200,19cyclictest0-21swapper/221:45:002
3033599204,1cyclictest0-21swapper/100:32:321
3033499204,15cyclictest0-21swapper/023:53:000
3033499202,3cyclictest0-21swapper/023:25:000
3033699193,15cyclictest28-21ksoftirqd/221:15:152
3033699192,1cyclictest0-21swapper/223:40:272
3033699192,16cyclictest4035-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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