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2026-06-19 - 17:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Jun 19, 2026 12:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
876399230,5cyclictest0-21swapper/112:35:011
876499220,18cyclictest0-21swapper/212:07:092
876399225,16cyclictest0-21swapper/111:26:101
8763992222,0cyclictest0-21swapper/107:30:231
8762992118,2cyclictest6345-21latency_hist09:00:010
876499203,16cyclictest3979-21H222:10:212
876499202,17cyclictest0-21swapper/211:00:182
8763992017,2cyclictest3991-21H222:10:211
876399200,18cyclictest758-21cut08:50:131
8762992011,5cyclictest0-21swapper/011:40:010
876299200,19cyclictest843-21systemd-network12:01:520
8764991917,1cyclictest0-21swapper/208:45:422
8764991916,2cyclictest20931-21expr10:20:152
8764991916,2cyclictest20931-21expr10:20:152
8764991916,2cyclictest19163-21open_inodes10:15:182
8764991915,3cyclictest3985-21H222:10:212
8764991915,3cyclictest2020-21cut09:45:172
876499191,2cyclictest3987-21H222:10:212
876499190,2cyclictest3983-21H222:10:212
876499190,2cyclictest3979-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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