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2026-03-05 - 08:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Mar 05, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13129993819,18cyclictest21-21ksoftirqd/121:55:121
13129992918,10cyclictest9558-21sed22:50:141
1313099230,5cyclictest24384-21grep20:25:172
1312899223,13cyclictest7839-21apt-key22:50:010
1312899220,21cyclictest843-21systemd-network19:13:060
1313099214,16cyclictest31287-21grep00:25:172
13130992117,3cyclictest0-21swapper/219:41:162
1312899213,3cyclictest12872-21perf23:55:000
13130992020,0cyclictest0-21swapper/222:35:142
13130992016,3cyclictest0-21swapper/223:11:472
13129992018,1cyclictest21-21ksoftirqd/119:12:561
1312999201,4cyclictest1567-21grep00:30:151
1312999200,19cyclictest32570-21fschecks_count20:40:131
1312899202,17cyclictest0-21swapper/019:30:080
13128992016,3cyclictest0-21swapper/019:42:250
1312899200,17cyclictest0-21swapper/019:45:140
13130991916,2cyclictest30816-21cat22:30:202
1313099191,17cyclictest21643-21grep20:20:162
1313099190,18cyclictest3983-21H222:10:212
1313099190,16cyclictest21429-21cat19:25:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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