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2026-01-20 - 10:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Jan 20, 2026 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12191992622,1cyclictest0-21swapper/000:30:130
1220399234,13cyclictest5475-21needreboot22:45:182
1219199236,13cyclictest0-21swapper/000:15:180
1219199220,3cyclictest0-21swapper/021:30:240
1220399214,10cyclictest0-21swapper/220:50:182
1220399202,17cyclictest0-21swapper/221:41:162
1220399193,15cyclictest31697-21cat00:30:172
1220399192,2cyclictest18098-21chrt21:15:082
12203991917,1cyclictest0-21swapper/221:39:082
12203991917,1cyclictest0-21swapper/221:24:232
12203991917,1cyclictest0-21swapper/221:24:232
12203991915,3cyclictest13223-21perf20:10:002
1220399190,18cyclictest3979-21H222:10:212
1220399190,17cyclictest810-21munin-plugin-st22:40:012
1220399190,16cyclictest3981-21H222:10:212
1220399190,16cyclictest0-21swapper/223:27:032
1219999193,15cyclictest21-21ksoftirqd/120:40:541
1219999192,1cyclictest3987-21H222:10:211
1219999190,16cyclictest3981-21H222:10:211
1219199193,1cyclictest32675-21interrupts19:45:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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