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2026-06-18 - 16:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Jun 18, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12508993029,1cyclictest0-21swapper/212:05:162
12503992313,10cyclictest0-21swapper/107:35:161
1249999230,5cyclictest0-21swapper/011:37:040
1249999230,5cyclictest0-21swapper/008:26:420
1249999230,18cyclictest0-21swapper/010:30:480
12503992222,0cyclictest0-21swapper/112:05:161
1250399203,16cyclictest3677-21latency_hist09:45:011
12503992016,3cyclictest22390-21cron08:25:011
1250899192,16cyclictest32733-21nfsd410:35:172
12508991917,1cyclictest0-21swapper/211:07:352
1250899190,1cyclictest0-21swapper/208:20:282
1250399193,15cyclictest0-21swapper/112:25:161
1250399192,16cyclictest10852-21nvmesmart_nvme011:50:201
1250399192,16cyclictest10852-21nvmesmart_nvme011:50:201
12503991917,1cyclictest0-21swapper/111:32:161
12503991917,1cyclictest0-21swapper/109:31:231
12503991916,2cyclictest3989-21H222:10:211
12503991916,2cyclictest24262-21cat12:15:171
1250399190,18cyclictest455-21plymouthd09:25:011
1249999194,1cyclictest0-21swapper/010:21:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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