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2025-12-08 - 01:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Dec 07, 2025 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15490993231,0cyclictest0-21swapper/209:10:012
15490992819,9cyclictest0-21swapper/208:02:582
15489992826,2cyclictest0-21swapper/109:20:191
15488992414,0cyclictest0-21swapper/012:25:160
15490992314,0cyclictest0-21swapper/210:30:152
1549099230,5cyclictest0-21swapper/211:29:062
1549099230,20cyclictest0-21swapper/211:44:502
15489992321,2cyclictest201rcuc/107:55:171
15489992321,2cyclictest201rcuc/107:55:161
1549099223,11cyclictest24165-21sed09:20:012
15490992222,0cyclictest0-21swapper/209:20:182
15490992220,1cyclictest28-21ksoftirqd/212:09:492
15488992213,9cyclictest0-21swapper/008:40:180
1548899220,18cyclictest0-21swapper/012:05:220
1548899220,18cyclictest0-21swapper/008:57:250
15489992017,2cyclictest6845-21tr09:45:151
15489992017,2cyclictest4532-21H212:26:331
1548999200,5cyclictest0-21swapper/108:37:011
1548899202,17cyclictest0-21swapper/009:41:470
1548899202,16cyclictest0-21swapper/008:08:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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