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2026-04-06 - 09:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Apr 06, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2569299260,25cyclictest0-21swapper/121:55:101
2569199230,22cyclictest0-21swapper/020:40:410
2569399210,20cyclictest843-21systemd-network21:01:252
2569399204,1cyclictest0-21swapper/220:50:012
2569299204,2cyclictest14232-21fschecks_count22:35:151
2569199203,16cyclictest3987-21H222:10:210
2569399192,16cyclictest9648-21ntp_kernel_pll_00:20:172
2569399192,16cyclictest3983-21H222:10:212
2569399192,16cyclictest0-21swapper/221:17:102
25693991917,1cyclictest0-21swapper/220:28:002
25693991916,2cyclictest3989-21H222:10:212
25693991916,2cyclictest3987-21H222:10:212
25693991916,2cyclictest24525-21date21:00:012
25693991914,4cyclictest4035-21H222:10:212
2569399190,2cyclictest3983-21H222:10:212
2569399190,16cyclictest3987-21H222:10:212
2569299192,1cyclictest0-21swapper/123:26:121
25692991915,3cyclictest25362-21fschecks_time22:55:141
25692991911,7cyclictest8921-21perf23:25:001
2569299190,2cyclictest4099-21H222:10:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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