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2026-05-21 - 17:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu May 21, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1331099253,15cyclictest13979-21latency_hist11:00:000
13310992313,5cyclictest0-21swapper/011:20:210
1331199220,20cyclictest455-21plymouthd10:50:131
1331299202,17cyclictest0-21swapper/212:25:122
13312992017,2cyclictest23105-21switchtime12:10:212
13311992018,1cyclictest21-21ksoftirqd/111:00:001
13311992014,3cyclictest0-21swapper/110:33:261
1331099200,17cyclictest0-21swapper/012:20:000
1331099200,17cyclictest0-21swapper/011:07:210
1331299195,13cyclictest0-21swapper/208:42:572
1331299194,1cyclictest0-21swapper/211:12:352
13312991911,5cyclictest0-21swapper/208:26:412
1331299190,18cyclictest0-21swapper/209:45:152
1331299190,16cyclictest3985-21H222:10:212
13311991915,3cyclictest0-21swapper/112:20:181
1331199191,2cyclictest0-21swapper/107:30:171
1331199191,2cyclictest0-21swapper/107:30:171
1331199190,5cyclictest0-21swapper/111:45:161
1331199190,3cyclictest0-21swapper/112:15:381
1331199190,18cyclictest16121-21pluginstate07:15:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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