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2026-04-22 - 02:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Apr 21, 2026 12:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3172999230,19cyclictest0-21swapper/012:16:280
3172999230,19cyclictest0-21swapper/012:16:280
3173599222,17cyclictest0-21swapper/210:12:252
3173599212,17cyclictest0-21swapper/209:09:292
31735992114,4cyclictest27931-21nfsd409:50:182
3173599210,20cyclictest5362-21cut11:05:152
3173099210,3cyclictest0-21swapper/112:27:591
31735992011,5cyclictest0-21swapper/211:40:192
3173599200,19cyclictest27271-21latency_hist08:55:012
3173599200,17cyclictest0-21swapper/208:00:182
3172999204,15cyclictest0-21swapper/012:33:420
3173599193,15cyclictest15467-21basename08:30:222
3173599192,2cyclictest32166-21cat09:00:222
3173599192,16cyclictest0-21swapper/211:12:152
31735991918,1cyclictest0-21swapper/208:55:162
31735991917,1cyclictest0-21swapper/212:15:002
31735991916,2cyclictest9423-21sh12:09:002
31735991916,2cyclictest19943-21sed11:30:162
31735991916,2cyclictest17329-21cat10:30:142
31735991916,2cyclictest14799-21ls10:25:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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