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2025-12-07 - 12:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Dec 07, 2025 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3080499236,16cyclictest4528-21H212:26:332
3080499230,5cyclictest0-21swapper/219:27:022
3080299234,18cyclictest0-21swapper/122:42:521
3080199231,0cyclictest0-21swapper/022:35:110
3080199230,18cyclictest0-21swapper/023:21:120
30801992214,4cyclictest0-21swapper/021:43:400
3080499210,20cyclictest414-20systemd-journal00:29:552
3080499210,20cyclictest0-21swapper/219:42:082
30801992120,1cyclictest9-21ksoftirqd/023:50:150
30801992112,5cyclictest9-21ksoftirqd/019:58:150
3080199210,1cyclictest0-21swapper/021:50:180
3080499191,2cyclictest4523-21H212:26:332
3080499190,16cyclictest4581-21H212:26:332
3080499190,16cyclictest4534-21H212:26:332
3080499190,15cyclictest0-21swapper/219:10:182
3080299192,16cyclictest0-21swapper/121:43:241
30802991917,1cyclictest0-21swapper/123:23:281
30802991916,2cyclictest4523-21H212:26:331
30802991915,3cyclictest0-21swapper/122:11:061
30802991914,4cyclictest0-21swapper/119:16:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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