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2026-05-05 - 01:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon May 04, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8415992214,4cyclictest0-21swapper/110:59:381
841599220,21cyclictest843-21systemd-network12:04:351
841199220,18cyclictest0-21swapper/008:45:150
8420992114,6cyclictest0-21swapper/211:45:172
841199210,20cyclictest843-21systemd-network11:13:030
842099202,17cyclictest4099-21H222:10:212
8420991916,2cyclictest0-21swapper/209:56:432
8415991914,1cyclictest0-21swapper/110:45:371
841599190,16cyclictest3979-21H222:10:211
841199193,14cyclictest0-21swapper/011:05:510
8411991917,1cyclictest3981-21H222:10:210
8411991913,3cyclictest0-21swapper/010:31:110
841199190,1cyclictest0-21swapper/010:15:170
842099182,1cyclictest0-21swapper/211:13:162
842099182,15cyclictest0-21swapper/207:51:432
8420991813,2cyclictest3985-21H222:10:212
842099181,16cyclictest3987-21H222:10:212
842099181,16cyclictest1504-21tail08:50:152
842099180,17cyclictest0-21swapper/212:35:012
841599182,15cyclictest21-21ksoftirqd/109:56:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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