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2026-04-23 - 02:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Apr 22, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2851699230,18cyclictest0-21swapper/207:35:162
2851199213,17cyclictest0-21swapper/012:33:050
28516992016,3cyclictest0-21swapper/211:44:572
2851699200,9cyclictest0-21swapper/212:00:182
2851699200,19cyclictest843-21systemd-network09:30:022
2851299200,17cyclictest0-21swapper/108:36:311
28516991916,2cyclictest993-21dbus-daemon08:05:202
28516991915,3cyclictest0-21swapper/209:19:412
2851699190,13cyclictest0-21swapper/210:30:172
2851299190,18cyclictest843-21systemd-network08:59:061
2851199193,15cyclictest0-21swapper/012:05:130
2851199190,2cyclictest3981-21H222:10:210
2851699182,15cyclictest178132chrt11:33:352
28516991815,2cyclictest7745-21cat09:20:212
2851699181,16cyclictest21613-21expr08:50:132
2851699181,16cyclictest10042-21missed_timers12:15:162
2851699181,15cyclictest3985-21H222:10:212
2851699180,3cyclictest2502-21cut09:15:012
2851699180,3cyclictest20789-21smtp08:49:172
2851699180,2cyclictest11079-21apache208:25:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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