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2026-09-03 - 01:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Sep 02, 2026 12:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2383899274,18cyclictest11782-21latency_hist09:40:010
2383899274,18cyclictest11782-21latency_hist09:40:000
2383899248,1cyclictest9-21ksoftirqd/009:25:400
2384099230,5cyclictest0-21swapper/108:52:431
2383899235,17cyclictest9-21ksoftirqd/008:20:010
23838992322,1cyclictest11284-21mii-tool11:30:150
2383899224,17cyclictest0-21swapper/010:34:540
23844992012,4cyclictest0-21swapper/208:43:392
23840992018,1cyclictest26985-21munin-plugin-st09:10:011
2384099200,19cyclictest0-21swapper/107:30:281
23838992012,3cyclictest0-21swapper/011:28:120
2384499193,1cyclictest28-21ksoftirqd/210:07:032
2384499193,15cyclictest28-21ksoftirqd/211:40:112
23844991917,1cyclictest28-21ksoftirqd/211:45:112
23844991917,1cyclictest28-21ksoftirqd/211:45:102
2384499190,3cyclictest0-21swapper/207:38:192
2384499190,2cyclictest3976-21H222:10:212
2384499190,18cyclictest3976-21H222:10:212
2384499190,16cyclictest3991-21H222:10:212
2384499190,16cyclictest3991-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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