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2026-04-26 - 16:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Apr 26, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26893992414,10cyclictest0-21swapper/111:30:011
26894992114,4cyclictest0-21swapper/209:26:532
2689299210,3cyclictest0-21swapper/012:31:440
2689499203,16cyclictest17196-21fschecks_time10:40:132
2689299204,15cyclictest0-21swapper/011:17:350
2689299203,2cyclictest14501-21snapd07:32:580
26892992015,4cyclictest0-21swapper/010:46:270
2689299200,17cyclictest0-21swapper/008:18:510
26894991917,1cyclictest0-21swapper/211:45:492
26894991917,1cyclictest0-21swapper/211:40:032
26894991917,1cyclictest0-21swapper/210:45:022
2689499190,17cyclictest3989-21H222:10:212
2689499190,16cyclictest4099-21H222:10:212
2689499190,16cyclictest3989-21H222:10:212
2689399190,2cyclictest3991-21H222:10:211
2689399190,2cyclictest3987-21H222:10:211
2689399190,2cyclictest3987-21H222:10:211
2689399190,1cyclictest0-21swapper/108:30:141
2689399190,1cyclictest0-21swapper/108:30:131
2689399190,17cyclictest0-21swapper/112:25:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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