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2026-02-11 - 09:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Feb 11, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1347799232,3cyclictest0-21swapper/021:02:310
1347799230,2cyclictest10695-21cat20:00:170
1347799230,16cyclictest22601-21ls21:20:130
1347899222,3cyclictest0-21swapper/121:02:311
13477992214,3cyclictest0-21swapper/022:40:200
13477992214,2cyclictest30328-21grep23:25:180
13477992214,2cyclictest27680-21apt-config19:35:020
13477992214,1cyclictest15187-21sensors23:55:190
1347799221,1cyclictest23204-21chrt20:20:530
1347799220,2cyclictest20396-21python322:15:000
1347799220,2cyclictest2030-21cat21:40:160
1347799220,2cyclictest19255-21sed23:05:210
1347799220,16cyclictest16816-21expr19:15:130
1347799220,15cyclictest0-21swapper/000:20:180
13477992114,2cyclictest8174-21nfsd419:55:210
13477992114,2cyclictest8148-21latency_hist20:55:000
13477992114,2cyclictest26506-21date20:30:010
13477992114,2cyclictest26281-21netstat21:25:190
13477992114,2cyclictest26077-21awk19:30:190
13477992114,2cyclictest16579-21proc_pri22:05:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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