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2026-03-26 - 21:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Mar 26, 2026 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28615996728,8cyclictest41-21ksoftirqd/308:37:433
28615996629,4cyclictest41-21ksoftirqd/312:25:013
28615996629,4cyclictest41-21ksoftirqd/312:25:013
28615996531,10cyclictest41-21ksoftirqd/307:25:013
28615996430,4cyclictest41-21ksoftirqd/311:45:133
28615996429,4cyclictest41-21ksoftirqd/307:50:003
28615996424,10cyclictest41-21ksoftirqd/307:38:353
134491640,5ptp4l0-21swapper/109:30:151
28615996331,7cyclictest41-21ksoftirqd/311:40:153
28615996325,3cyclictest41-21ksoftirqd/310:15:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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