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2026-05-10 - 19:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun May 10, 2026 12:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2941321530,6sleep12367499cyclictest08:30:201
55892780,5sleep20-21swapper/207:40:142
134491690,4ptp4l121rcu_preempt07:05:153
134491620,4ptp4l5736-21idleruntime10:00:161
134491620,4ptp4l0-21swapper/010:19:570
134491590,4ptp4l0-21swapper/309:32:303
2367399582,15cyclictest15340-21cat08:00:190
2367399581,14cyclictest0-21swapper/012:20:180
134491580,4ptp4l0-21swapper/308:35:183
134491580,3ptp4l0-21swapper/107:45:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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