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2026-01-31 - 08:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jan 31, 2026 00:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3088821830,4sleep02738599cyclictest19:15:200
1192321440,6sleep32738899cyclictest20:54:593
134491690,4ptp4l22719-21/usr/sbin/munin21:15:223
11052660,6sleep20-21swapper/219:20:242
134491620,4ptp4l0-21swapper/119:16:201
120142620,4sleep00-21swapper/022:03:400
134491610,5ptp4l20284-21date00:40:002
134491610,4ptp4l0-21swapper/322:40:143
134491600,3ptp4l0-21swapper/119:35:111
27387995925,4cyclictest33-21ksoftirqd/222:50:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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