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2026-02-26 - 19:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Feb 26, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2038821520,3sleep11401699cyclictest07:20:241
2038821520,3sleep11401699cyclictest07:20:241
134491810,4ptp4l0-21swapper/309:09:513
231252710,2sleep323128-21proc_pri09:45:253
134491660,4ptp4l0-21swapper/310:15:243
134491650,3ptp4l25781-21ntp_states12:10:213
134491650,3ptp4l23451-21ntp_states10:55:213
1401699622,24cyclictest3382-21/usr/sbin/munin10:15:141
1401599623,13cyclictest0-21swapper/008:15:250
134491610,3ptp4l27173-21/usr/sbin/munin12:15:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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