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2026-08-21 - 14:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Aug 21, 2026 00:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491650,6ptp4l25-21ksoftirqd/119:26:591
10052996432,6cyclictest33-21ksoftirqd/223:15:242
10052996333,5cyclictest33-21ksoftirqd/222:50:222
10052996326,3cyclictest33-21ksoftirqd/220:44:132
10052996232,5cyclictest33-21ksoftirqd/222:10:142
10052996232,5cyclictest33-21ksoftirqd/222:10:142
10052996231,6cyclictest33-21ksoftirqd/222:55:162
1005299622,16cyclictest0-21swapper/219:42:582
185512610,5sleep018557-21timerwakeupswit19:25:280
10052996131,5cyclictest33-21ksoftirqd/220:25:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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