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2026-03-24 - 15:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Mar 24, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
917621460,6sleep22217399cyclictest07:50:192
134491600,3ptp4l27581-21iostat08:30:160
22173995738,17cyclictest33-21ksoftirqd/210:30:002
134491570,5ptp4l0-21swapper/012:20:160
134491570,5ptp4l0-21swapper/007:55:140
134491560,3ptp4l0-21swapper/210:50:012
134491560,3ptp4l0-21swapper/110:35:261
134491560,3ptp4l0-21swapper/108:44:531
134491560,3ptp4l0-21swapper/108:38:591
134491560,3ptp4l0-21swapper/011:50:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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