You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-23 - 13:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Feb 23, 2026 00:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
67121660,6sleep30-21swapper/319:05:223
190499771,74cyclictest0-21swapper/220:45:292
190499721,3cyclictest0-21swapper/219:30:292
190499691,2cyclictest0-21swapper/219:45:292
190299673,62cyclictest11756-21kworker/1:019:35:091
190299668,17cyclictest12006-21date23:00:001
134491630,4ptp4l32440-21/usr/sbin/munin20:15:220
134491630,4ptp4l0-21swapper/321:20:233
190499590,57cyclictest0-21swapper/221:59:292
134491590,4ptp4l0-21swapper/100:20:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional