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2026-09-05 - 13:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Sep 05, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
360621490,7sleep11446299cyclictest19:55:161
490921240,3sleep20-21swapper/200:35:202
1446499682,33cyclictest0-21swapper/320:00:163
1446499672,35cyclictest0-21swapper/319:45:193
134491670,4ptp4l0-21swapper/020:00:020
134491660,5ptp4l0-21swapper/022:40:130
134491650,20ptp4l26122-21users23:00:270
134491630,4ptp4l0-21swapper/020:48:150
134491620,4ptp4l0-21swapper/020:40:250
134491610,3ptp4l10948-21memory21:20:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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