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2026-08-25 - 18:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Aug 25, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491820,1ptp4l101ktimersoftd/010:11:000
134491690,35ptp4l41-21ksoftirqd/309:09:173
134491670,18ptp4l0-21swapper/208:05:172
134491620,4ptp4l0-21swapper/110:45:281
134491610,5ptp4l0-21swapper/012:00:270
134491610,4ptp4l0-21swapper/211:10:322
214502590,6sleep3200699cyclictest11:20:133
134491590,7ptp4l0-21swapper/007:05:100
134491580,4ptp4l0-21swapper/107:19:401
134491570,3ptp4l0-21swapper/109:35:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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