You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-18 - 21:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Feb 18, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1628421530,6sleep02612499cyclictest11:25:180
555721450,4sleep12612599cyclictest07:35:121
267232780,5sleep00-21swapper/008:20:150
124272780,4sleep20-21swapper/211:15:252
254802700,1sleep125479-21memory09:25:201
134491680,9ptp4l0-21swapper/007:45:170
265272640,5sleep30-21swapper/307:10:153
26127996330,8cyclictest41-21ksoftirqd/310:31:253
26127996121,6cyclictest41-21ksoftirqd/309:15:553
26127996121,6cyclictest41-21ksoftirqd/309:15:543
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional