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2026-04-20 - 02:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Apr 19, 2026 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2340221690,6sleep32309899cyclictest11:50:003
1101721660,5sleep02309599cyclictest09:00:280
3109321410,7sleep32309899cyclictest10:55:163
3097521220,5sleep22309799cyclictest07:25:182
81752710,7sleep02309599cyclictest12:25:180
134491640,4ptp4l9157-21sshd12:26:571
2309599613,15cyclictest0-21swapper/007:35:000
2309599604,15cyclictest18566-21latency_hist10:30:000
134491600,19ptp4l0-21swapper/310:45:143
2309599591,15cyclictest25551-21/usr/sbin/munin09:35:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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