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2026-04-29 - 19:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Apr 29, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2900921170,4sleep10-21swapper/112:20:131
272302650,5sleep327226-21sendmail_mailqu09:55:263
134491650,5ptp4l0-21swapper/210:53:182
134491650,32ptp4l41-21ksoftirqd/308:20:253
134491620,4ptp4l0-21swapper/209:43:132
134491610,4ptp4l0-21swapper/210:25:172
134491600,4ptp4l0-21swapper/012:14:240
134491600,4ptp4l0-21swapper/007:55:380
134491600,3ptp4l0-21swapper/010:46:040
1362799594,53cyclictest0-21swapper/311:15:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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