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2026-08-07 - 04:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Aug 07, 2026 00:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491680,5ptp4l0-21swapper/019:05:210
18952670,4sleep20-21swapper/220:00:262
134491670,4ptp4l0-21swapper/223:40:122
99072640,3sleep30-21swapper/320:20:003
9898996312,9cyclictest27172-21seq23:13:121
134491630,3ptp4l0-21swapper/221:40:042
989899619,11cyclictest28064-21chrt20:57:491
989899619,11cyclictest15703-21chrt23:56:501
989899609,11cyclictest3942-21chrt23:31:221
989899609,10cyclictest30501-21chrt21:04:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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