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2026-05-15 - 13:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri May 15, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26248997410,62cyclictest29576-21kworker/1:200:31:491
26249997337,4cyclictest33-21ksoftirqd/200:00:002
101302690,4sleep110134-21timerandwakeup20:50:261
26249996834,4cyclictest33-21ksoftirqd/200:40:012
26249996828,7cyclictest33-21ksoftirqd/223:19:442
26249996733,7cyclictest33-21ksoftirqd/222:16:192
26249996729,4cyclictest33-21ksoftirqd/200:25:142
2624899670,24cyclictest2844-21hddtemp_smartct00:05:201
2624899670,22cyclictest5635-21cut00:10:191
134491670,3ptp4l9850-21ntp_states23:10:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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