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2026-08-23 - 17:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Aug 23, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3184021870,6sleep184099cyclictest09:25:141
2570621350,5sleep284199cyclictest11:30:152
122321320,5sleep384299cyclictest07:10:153
841997124,9cyclictest33-21ksoftirqd/212:00:272
108262660,4sleep10-21swapper/112:05:281
134491630,4ptp4l0-21swapper/109:00:211
841996230,6cyclictest33-21ksoftirqd/210:40:212
841996224,4cyclictest33-21ksoftirqd/212:19:092
841996223,6cyclictest33-21ksoftirqd/210:05:252
841996127,5cyclictest33-21ksoftirqd/208:40:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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