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2026-08-02 - 19:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Aug 02, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
634622510,4sleep30-21swapper/307:08:093
634622510,4sleep30-21swapper/307:08:093
2398622490,3sleep2311rcuc/207:08:252
2398622490,3sleep2311rcuc/207:08:252
1621822010,8sleep116249-21multi.sh07:09:481
1621822010,8sleep116249-21multi.sh07:09:481
1438921980,3sleep00-21swapper/007:06:500
1438921980,3sleep00-21swapper/007:06:500
134491710,3ptp4l121rcu_preempt10:45:130
134491700,35ptp4l9-21ksoftirqd/007:11:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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