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2026-05-07 - 17:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu May 07, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2612021380,6sleep12216799cyclictest10:45:241
187692690,4sleep00-21swapper/010:30:180
22167996630,9cyclictest25-21ksoftirqd/111:30:001
22167996529,4cyclictest25-21ksoftirqd/108:45:161
22167996433,8cyclictest25-21ksoftirqd/107:15:001
22167996427,9cyclictest25-21ksoftirqd/112:29:591
22167996230,8cyclictest25-21ksoftirqd/107:25:161
22167996228,9cyclictest25-21ksoftirqd/108:15:261
22167996226,9cyclictest25-21ksoftirqd/112:15:201
22167996226,9cyclictest25-21ksoftirqd/110:05:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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