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2026-06-26 - 22:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Jun 26, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21664997033,4cyclictest9-21ksoftirqd/007:40:000
2166599692,55cyclictest20675-21cut10:35:181
21665996815,49cyclictest6264-21/usr/sbin/munin08:55:161
21665996615,48cyclictest30640-21seq07:29:531
21665996513,11cyclictest12373-21chrt10:16:431
21665996513,11cyclictest12373-21chrt10:16:431
2166599647,11cyclictest25078-21ntpq07:15:261
21665996411,9cyclictest4068-21sed07:40:191
2166599639,12cyclictest17278-21df_abs08:10:141
2166599638,10cyclictest0-21swapper/108:05:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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