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2026-08-22 - 16:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Aug 22, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14953996828,6cyclictest9-21ksoftirqd/012:05:000
14953996633,6cyclictest9-21ksoftirqd/009:30:190
14953996332,5cyclictest9-21ksoftirqd/009:20:180
14953996329,6cyclictest9-21ksoftirqd/009:40:280
14953996325,5cyclictest9-21ksoftirqd/012:10:250
14953996226,7cyclictest9-21ksoftirqd/011:00:160
188032610,4sleep20-21swapper/209:35:202
14953996136,6cyclictest9-21ksoftirqd/007:25:000
14953996132,3cyclictest9-21ksoftirqd/009:25:200
14953996130,5cyclictest9-21ksoftirqd/008:00:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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