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2026-07-29 - 17:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jul 29, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1017921490,6sleep12674599cyclictest10:00:241
134491670,3ptp4l0-21swapper/111:10:281
134491670,3ptp4l0-21swapper/010:40:220
46652630,5sleep10-21swapper/111:00:141
134491620,23ptp4l0-21swapper/210:08:162
131212610,5sleep341-21ksoftirqd/309:00:003
26744996032,3cyclictest121rcu_preempt10:04:110
134491580,3ptp4l11762-21phc2sys07:45:241
134491570,5ptp4l0-21swapper/210:50:212
134491570,5ptp4l0-21swapper/009:50:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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