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2025-12-19 - 15:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Dec 19, 2025 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1520321710,4sleep1637999cyclictest10:55:191
1073121630,7sleep3638199cyclictest08:25:243
134491770,4ptp4l0-21swapper/011:19:020
134491750,12ptp4l0-21swapper/111:24:551
116712730,6sleep30-21swapper/307:20:133
6380996530,10cyclictest33-21ksoftirqd/208:19:592
9482640,4sleep30-21swapper/310:25:163
6380996434,4cyclictest33-21ksoftirqd/211:20:262
134491640,5ptp4l19256-21idleruntime-cro12:15:000
6380996333,4cyclictest33-21ksoftirqd/209:50:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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