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2026-08-04 - 10:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Aug 04, 2026 00:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
500799791,76cyclictest0-21swapper/222:35:282
500799790,2cyclictest1030-21users23:35:292
134491660,5ptp4l0-21swapper/021:10:280
265532610,5sleep10-21swapper/119:55:011
265532610,5sleep10-21swapper/119:55:011
134491610,2ptp4l0-21swapper/023:10:270
134491590,4ptp4l0-21swapper/120:55:161
134491590,4ptp4l0-21swapper/019:50:200
134491590,16ptp4l0-21swapper/023:05:140
134491580,4ptp4l0-21swapper/222:10:312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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