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2026-07-04 - 07:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jul 04, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1541022460,6sleep10-21swapper/119:05:181
1541022460,6sleep10-21swapper/119:05:181
3076121620,6sleep01712299cyclictest00:15:180
1981921440,6sleep31712599cyclictest19:15:153
241542650,4sleep20-21swapper/222:50:242
17122996328,6cyclictest9-21ksoftirqd/023:50:180
17122996233,4cyclictest9-21ksoftirqd/023:25:120
17122996229,6cyclictest9-21ksoftirqd/019:20:000
17122996131,5cyclictest9-21ksoftirqd/022:25:150
17122996129,4cyclictest9-21ksoftirqd/023:15:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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