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2026-06-09 - 00:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Jun 08, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
607522610,4sleep30-21swapper/307:05:223
264021660,5sleep3730899cyclictest11:35:283
7308996826,10cyclictest41-21ksoftirqd/307:21:323
96132670,4sleep29616-21unixbench_singl11:50:272
7308996727,9cyclictest41-21ksoftirqd/309:55:523
7308996634,4cyclictest41-21ksoftirqd/310:10:153
7308996530,4cyclictest41-21ksoftirqd/312:40:013
7308996527,7cyclictest41-21ksoftirqd/310:37:043
7308996526,8cyclictest41-21ksoftirqd/307:59:103
7308996429,7cyclictest41-21ksoftirqd/311:05:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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