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2026-04-10 - 13:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Apr 10, 2026 00:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491770,4ptp4l0-21swapper/220:35:242
16418996824,3cyclictest9-21ksoftirqd/019:55:180
134491670,4ptp4l0-21swapper/120:15:281
16418996623,4cyclictest9-21ksoftirqd/022:50:150
274742630,6sleep00-21swapper/021:50:200
16419996126,5cyclictest25-21ksoftirqd/121:30:001
134491610,9ptp4l0-21swapper/223:30:252
134491610,4ptp4l0-21swapper/219:32:452
16418996018,4cyclictest9-21ksoftirqd/020:11:440
134491600,5ptp4l0-21swapper/319:05:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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