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2026-02-16 - 13:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Feb 16, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1802521420,6sleep32803099cyclictest21:05:263
134491820,2ptp4l19746-21kworker/2:223:30:462
134491720,2ptp4l121rcu_preempt23:15:202
2802899719,60cyclictest12006-21kworker/1:221:58:091
2802899717,62cyclictest10481-21kworker/1:100:00:481
28028996717,48cyclictest12006-21kworker/1:220:15:291
28028996714,16cyclictest13875-21taskset20:56:011
2802799677,17cyclictest26627-21perl22:35:170
28028996613,48cyclictest174322sleep123:25:121
28028996512,12cyclictest13709-21taskset19:46:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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