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2026-04-11 - 10:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Apr 11, 2026 00:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1794099630,61cyclictest0-21swapper/321:00:483
1793799638,51cyclictest5359-21awk21:00:220
17937996314,11cyclictest15395-21seq20:12:540
17937996216,9cyclictest7941-21python19:55:240
17937996115,10cyclictest25009-21taskset00:01:510
1793799606,17cyclictest0-21swapper/000:30:150
134491600,3ptp4l0-21swapper/219:55:182
265732590,6sleep21793999cyclictest00:05:202
1793899597,6cyclictest0-21swapper/121:10:241
134491580,4ptp4l0-21swapper/221:10:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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