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2026-06-16 - 20:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Jun 16, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41321620,4sleep10-21swapper/108:25:221
2853221390,6sleep32949499cyclictest10:35:173
29494997030,8cyclictest41-21ksoftirqd/308:20:003
29494996927,8cyclictest41-21ksoftirqd/311:50:013
134491690,8ptp4l0-21swapper/007:05:140
29494996634,8cyclictest41-21ksoftirqd/308:10:263
29494996530,7cyclictest41-21ksoftirqd/308:05:003
29494996530,7cyclictest41-21ksoftirqd/308:05:003
29494996426,8cyclictest41-21ksoftirqd/312:00:143
29494996328,7cyclictest41-21ksoftirqd/311:40:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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