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2026-07-15 - 15:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jul 15, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491650,4ptp4l0-21swapper/207:28:382
24697996231,3cyclictest41-21ksoftirqd/310:15:203
24697996231,3cyclictest41-21ksoftirqd/310:15:203
24697996122,4cyclictest41-21ksoftirqd/307:50:013
24697996025,8cyclictest41-21ksoftirqd/312:21:223
179372600,5sleep117941-21cpuspeed_turbos08:05:141
134491600,4ptp4l0-21swapper/112:20:131
134491600,3ptp4l25-21ksoftirqd/109:30:141
134491570,4ptp4l0-21swapper/209:25:212
134491570,4ptp4l0-21swapper/208:59:052
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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