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2026-06-23 - 20:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Jun 23, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2929721460,5sleep22520999cyclictest11:55:172
2520899810,69cyclictest31439-21sed12:00:181
3522670,5sleep2344-21awk10:55:002
2520899671,22cyclictest31995-21sed07:25:001
2520899668,18cyclictest2182-21date08:40:001
2520899660,24cyclictest26134-21ls10:40:111
134491660,2ptp4l0-21swapper/207:05:232
2520899650,25cyclictest12473-21missed_timers07:50:211
2520899650,23cyclictest5500-21cstates11:05:121
2520899630,60cyclictest19322-21memory09:15:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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