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2026-09-25 - 01:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Sep 24, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1164921170,2sleep01441199cyclictest11:40:260
14414998532,11cyclictest41-21ksoftirqd/307:45:193
297642770,4sleep129769-21switchtime08:50:241
14414997325,8cyclictest41-21ksoftirqd/307:10:163
14414997032,4cyclictest41-21ksoftirqd/309:05:283
14413996836,4cyclictest33-21ksoftirqd/210:40:162
320412670,5sleep30-21swapper/312:25:173
14414996726,10cyclictest41-21ksoftirqd/308:25:003
14414996636,3cyclictest41-21ksoftirqd/307:30:143
14414996635,3cyclictest41-21ksoftirqd/309:25:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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