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2026-06-04 - 03:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jun 04, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1930221620,5sleep048999cyclictest22:55:130
493996834,4cyclictest33-21ksoftirqd/222:00:162
493996733,10cyclictest33-21ksoftirqd/223:05:232
493996725,6cyclictest33-21ksoftirqd/221:30:012
493996534,9cyclictest33-21ksoftirqd/223:20:012
493996534,6cyclictest33-21ksoftirqd/222:05:242
493996532,4cyclictest33-21ksoftirqd/220:10:212
493996532,4cyclictest33-21ksoftirqd/220:10:202
493996531,6cyclictest33-21ksoftirqd/222:20:142
493996529,5cyclictest33-21ksoftirqd/222:55:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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