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2026-07-18 - 06:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jul 18, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491790,4ptp4l0-21swapper/222:35:172
29376997316,12cyclictest9315-21chrt23:03:303
29376997116,12cyclictest20885-21chrt23:28:323
29376997114,11cyclictest29947-21chrt22:36:053
29376996916,12cyclictest18512-21chrt23:22:343
29376996915,12cyclictest6300-21taskset20:38:593
29376996914,11cyclictest29993-21taskset23:47:103
29376996914,11cyclictest16399-21taskset00:26:033
29376996912,15cyclictest7463-21irqrtprio20:40:203
134491690,6ptp4l0-21swapper/219:09:292
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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