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2026-04-28 - 23:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Apr 28, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3269721600,3sleep12181599cyclictest09:50:181
813421590,4sleep32181799cyclictest10:05:283
179212770,1sleep317922-21/usr/sbin/munin08:10:153
21816996734,4cyclictest33-21ksoftirqd/207:30:192
21816996733,6cyclictest33-21ksoftirqd/210:10:002
21815996732,6cyclictest25-21ksoftirqd/111:30:001
21816996630,8cyclictest33-21ksoftirqd/210:35:162
21816996531,7cyclictest33-21ksoftirqd/211:50:242
134491650,15ptp4l0-21swapper/007:45:190
21816996330,9cyclictest33-21ksoftirqd/211:25:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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