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2026-05-11 - 07:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon May 11, 2026 00:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1067321450,5sleep21272499cyclictest20:15:152
12725998332,4cyclictest41-21ksoftirqd/321:25:183
12725997033,7cyclictest41-21ksoftirqd/322:22:423
12725996931,5cyclictest41-21ksoftirqd/322:30:103
12725996832,4cyclictest41-21ksoftirqd/322:15:153
12724996746,14cyclictest33-21ksoftirqd/222:39:592
12724996734,7cyclictest33-21ksoftirqd/221:32:452
12724996730,7cyclictest33-21ksoftirqd/223:54:592
12725996635,4cyclictest41-21ksoftirqd/323:57:493
12725996633,4cyclictest41-21ksoftirqd/320:50:323
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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