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2026-03-29 - 07:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Mar 29, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1605321480,7sleep2701199cyclictest22:55:222
3079121330,4sleep2701199cyclictest00:35:272
701199772,33cyclictest0-21swapper/200:25:272
104202770,6sleep0700999cyclictest19:15:230
701199752,31cyclictest0-21swapper/223:15:282
701199712,32cyclictest0-21swapper/219:35:142
134491650,31ptp4l25-21ksoftirqd/100:12:311
134491640,5ptp4l0-21swapper/023:35:200
134491640,5ptp4l0-21swapper/023:35:200
7011996331,4cyclictest33-21ksoftirqd/223:15:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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