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2026-05-16 - 04:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat May 16, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1336121610,4sleep313363-21latency_hist19:55:013
2803521250,7sleep02500799cyclictest22:45:150
134491640,5ptp4l27895-21latency_hist23:55:011
134491620,4ptp4l3230-21irqstats23:00:182
134491620,4ptp4l0-21swapper/123:02:481
134491610,17ptp4l10530-21sed19:45:293
134491600,5ptp4l0-21swapper/220:30:142
134491590,3ptp4l0-21swapper/023:50:130
134491590,3ptp4l0-21swapper/000:20:190
134491570,3ptp4l0-21swapper/121:30:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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