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2026-05-12 - 23:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue May 12, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491720,10ptp4l16691-21meminfo07:05:210
167472680,7sleep30-21swapper/307:05:223
18235996531,6cyclictest9-21ksoftirqd/010:40:010
18235996329,5cyclictest9-21ksoftirqd/007:55:140
18235996328,5cyclictest9-21ksoftirqd/009:45:000
134491630,5ptp4l0-21swapper/111:20:191
18235996227,5cyclictest9-21ksoftirqd/008:40:270
134491620,5ptp4l0-21swapper/011:40:270
18235996122,9cyclictest9-21ksoftirqd/012:35:000
134491610,4ptp4l0-21swapper/208:40:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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