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2026-07-11 - 05:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jul 11, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1381321560,5sleep03147799cyclictest00:15:260
134491640,22ptp4l11205-21chrt00:10:200
134491620,4ptp4l0-21swapper/300:05:153
31479996129,7cyclictest33-21ksoftirqd/220:00:002
134491600,4ptp4l0-21swapper/320:55:273
31479995929,4cyclictest33-21ksoftirqd/222:45:002
31479995822,4cyclictest33-21ksoftirqd/219:22:162
134491580,3ptp4l0-21swapper/220:05:262
134491570,3ptp4l0-21swapper/221:45:142
31479995621,6cyclictest33-21ksoftirqd/222:45:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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