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2026-07-07 - 14:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Jul 07, 2026 00:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
526622420,3sleep20-21swapper/219:09:402
506121970,4sleep00-21swapper/019:08:560
1228421930,4sleep10-21swapper/119:06:461
1973821910,7sleep319749-21sh19:09:153
36521450,5sleep21522799cyclictest21:00:162
15228996811,18cyclictest22924-21cron20:39:593
15225996426,6cyclictest9-21ksoftirqd/020:25:010
15225996326,6cyclictest9-21ksoftirqd/019:35:000
15225996230,4cyclictest9-21ksoftirqd/020:05:000
15225996129,3cyclictest9-21ksoftirqd/020:20:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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