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2026-06-11 - 14:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jun 11, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30692996328,8cyclictest25-21ksoftirqd/119:30:261
247212630,6sleep03069199cyclictest22:25:140
134491620,19ptp4l0-21swapper/000:20:130
30692995927,7cyclictest25-21ksoftirqd/119:50:231
134491590,3ptp4l8739-21ntp_states19:30:213
30692995831,7cyclictest25-21ksoftirqd/120:23:111
30692995830,4cyclictest25-21ksoftirqd/121:00:201
30692995828,7cyclictest25-21ksoftirqd/121:15:001
30692995826,3cyclictest25-21ksoftirqd/123:44:381
30692995826,3cyclictest25-21ksoftirqd/119:40:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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