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2026-06-19 - 01:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jun 18, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2434821630,2sleep0531899cyclictest10:10:100
1190821250,6sleep2532099cyclictest09:40:272
5321997029,8cyclictest41-21ksoftirqd/310:02:223
5321996632,7cyclictest41-21ksoftirqd/309:20:013
5321996627,7cyclictest41-21ksoftirqd/307:40:273
5321996624,11cyclictest41-21ksoftirqd/310:54:013
5321996529,5cyclictest41-21ksoftirqd/307:45:253
5321996528,4cyclictest41-21ksoftirqd/311:34:373
5321996425,8cyclictest41-21ksoftirqd/307:13:443
5321996422,11cyclictest41-21ksoftirqd/309:10:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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