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2026-04-03 - 01:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Apr 02, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
195621420,3sleep0282199cyclictest12:05:270
2823997112,13cyclictest31976-21chrt10:51:042
282399705,62cyclictest0-21swapper/209:50:292
2823997013,11cyclictest22695-21chrt10:30:462
2823996913,11cyclictest20886-21chrt11:37:262
2823996612,11cyclictest17914-21chrt09:10:312
2823996612,11cyclictest17914-21chrt09:10:312
2823996611,12cyclictest17833-21chrt08:04:072
2823996611,12cyclictest17833-21chrt08:04:072
2823996611,11cyclictest13400-21ntpq07:45:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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