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2026-05-20 - 12:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed May 20, 2026 00:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
63692800,2sleep36370-21irqrtprio21:10:193
1477999803,75cyclictest0-21swapper/200:20:292
1477999801,77cyclictest0-21swapper/220:55:282
203782740,6sleep30-21swapper/321:40:203
1477999685,61cyclictest0-21swapper/221:25:282
1477999671,64cyclictest0-21swapper/219:50:282
134491640,4ptp4l0-21swapper/119:20:161
134491640,3ptp4l26998-21diskstats23:05:141
134491630,4ptp4l0-21swapper/123:35:141
14779996214,46cyclictest0-21swapper/222:03:492
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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