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2025-11-17 - 20:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Nov 17, 2025 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2847191810,4ptp4l0-21swapper/109:15:161
2847191680,3ptp4l0-21swapper/310:36:123
2847191650,5ptp4l0-21swapper/207:50:232
2847191650,4ptp4l5225-21ls07:55:293
2847191650,3ptp4l20974-21meminfo08:30:222
2847191640,5ptp4l0-21swapper/308:35:143
2847191620,4ptp4l0-21swapper/308:45:003
2847191610,4ptp4l0-21swapper/310:05:273
2847191610,4ptp4l0-21swapper/310:05:263
2847191610,3ptp4l0-21swapper/311:05:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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