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2026-04-10 - 23:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Apr 10, 2026 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
981721250,2sleep10-21swapper/110:15:251
134491710,3ptp4l0-21swapper/012:20:210
134491620,5ptp4l0-21swapper/007:10:220
134491620,17ptp4l0-21swapper/110:25:201
300202610,6sleep10-21swapper/108:40:251
134491590,4ptp4l0-21swapper/107:49:541
134491580,5ptp4l0-21swapper/107:09:451
134491580,3ptp4l0-21swapper/310:05:223
134491580,3ptp4l0-21swapper/111:15:201
134491570,4ptp4l0-21swapper/308:07:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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