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2026-05-26 - 23:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue May 26, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3141421500,5sleep02854499cyclictest09:35:130
2401721450,6sleep22854699cyclictest08:10:142
134491800,3ptp4l0-21swapper/010:19:480
28545996734,4cyclictest25-21ksoftirqd/107:20:001
28545996633,7cyclictest25-21ksoftirqd/110:55:171
28545996332,4cyclictest25-21ksoftirqd/110:05:001
28545996330,8cyclictest25-21ksoftirqd/111:00:161
28545996330,3cyclictest25-21ksoftirqd/110:55:001
28545996323,7cyclictest25-21ksoftirqd/108:15:011
134491630,4ptp4l19524-21diskstats09:10:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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