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2026-02-21 - 21:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Feb 21, 2026 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2626221730,6sleep13089899cyclictest10:25:271
460021580,5sleep23089999cyclictest12:00:152
244402940,3sleep30-21swapper/309:15:003
30900996617,8cyclictest41-21ksoftirqd/311:52:233
303302660,4sleep13089899cyclictest08:15:251
134491650,4ptp4l25562-21systemctl08:05:252
30900996433,3cyclictest41-21ksoftirqd/308:40:233
30900996430,4cyclictest41-21ksoftirqd/308:05:163
30900996420,9cyclictest41-21ksoftirqd/310:30:193
30900996332,4cyclictest41-21ksoftirqd/309:05:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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