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2026-07-14 - 00:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Jul 13, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1588721870,7sleep12777299cyclictest10:10:281
903621620,1sleep12777299cyclictest12:15:201
2295821440,6sleep02777199cyclictest10:25:260
27774996834,2cyclictest41-21ksoftirqd/309:40:173
134491680,4ptp4l0-21swapper/009:19:250
27774996634,4cyclictest41-21ksoftirqd/310:00:583
27774996534,8cyclictest41-21ksoftirqd/310:40:003
27774996533,3cyclictest41-21ksoftirqd/307:25:443
27774996531,8cyclictest41-21ksoftirqd/309:21:223
27774996528,4cyclictest41-21ksoftirqd/308:15:473
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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