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2025-11-10 - 14:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Nov 10, 2025 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2810522200,5sleep31317-21lldpd19:05:293
1290421390,4sleep22891899cyclictest19:44:592
2847191820,3ptp4l1317-21lldpd20:49:380
2847191740,3ptp4l121rcu_preempt20:40:521
2891899722,67cyclictest0-21swapper/200:18:072
2891899720,68cyclictest27494-21taskset22:32:002
2847191720,4ptp4l11532-21taskset23:07:533
2847191710,4ptp4l1317-21lldpd00:25:270
2891899700,67cyclictest3301-21grep00:00:222
2847191700,3ptp4l207-21systemd-journal19:24:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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