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2025-10-17 - 15:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Oct 17, 2025 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1333321600,6sleep31998899cyclictest10:20:253
178182810,8sleep217823-21cpuspeed_turbos07:05:112
2847191760,5ptp4l0-21swapper/107:08:371
2847191690,5ptp4l0-21swapper/307:40:123
2847191650,4ptp4l0-21swapper/011:45:160
2847191610,4ptp4l22487-21cpuspeed_turbos07:15:140
2847191600,3ptp4l0-21swapper/307:26:553
2847191600,3ptp4l0-21swapper/107:43:241
2847191590,4ptp4l0-21swapper/208:57:592
2847191590,4ptp4l0-21swapper/010:05:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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