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2026-03-30 - 08:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Mar 30, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3131221680,6sleep30-21swapper/319:10:013
134691870,11getstats0-21swapper/200:10:122
305162760,3sleep30-21swapper/320:15:283
134491760,9ptp4l30739-21users19:05:261
134491650,5ptp4l0-21swapper/019:45:210
31406996428,10cyclictest25-21ksoftirqd/100:20:251
38622620,6sleep03140599cyclictest19:20:130
58662610,4sleep10-21swapper/121:45:001
3140699616,8cyclictest3432-21latency_hist20:30:001
31406996126,6cyclictest25-21ksoftirqd/123:55:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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