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2026-08-26 - 21:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Aug 26, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1448621760,5sleep12441899cyclictest12:35:171
24419997213,11cyclictest3619-21taskset08:44:062
2441999707,61cyclictest0-21swapper/211:10:142
24419996914,12cyclictest12591-21chrt09:01:102
24419996913,11cyclictest29255-21chrt11:56:352
24419996911,11cyclictest172742chrt09:12:222
134491690,4ptp4l2143-21/usr/sbin/munin08:40:171
24419996712,11cyclictest28678-21chrt07:17:442
24419996712,11cyclictest10711-21chrt10:09:352
24419996618,12cyclictest1043-21chrt07:28:392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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