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2026-07-19 - 08:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Jul 19, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1211521560,6sleep2630699cyclictest20:30:172
2365421240,7sleep0630499cyclictest20:55:180
3013321220,5sleep30-21swapper/322:20:023
120142740,5sleep125-21ksoftirqd/120:30:161
6306996939,2cyclictest33-21ksoftirqd/200:00:132
6306996632,2cyclictest33-21ksoftirqd/220:45:242
134491650,3ptp4l0-21swapper/320:30:253
6306996229,3cyclictest33-21ksoftirqd/223:00:192
6306996226,6cyclictest33-21ksoftirqd/221:30:192
134491620,6ptp4l0-21swapper/019:10:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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