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2026-04-29 - 13:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Apr 29, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11703997817,4cyclictest33-21ksoftirqd/219:18:222
11698997325,4cyclictest9-21ksoftirqd/019:18:200
132342720,5sleep00-21swapper/022:35:280
172792700,3sleep317282-21ntp_offset22:45:223
11702996926,8cyclictest25-21ksoftirqd/120:35:191
11702996730,4cyclictest25-21ksoftirqd/119:18:191
11703996631,8cyclictest33-21ksoftirqd/220:20:192
11703996630,8cyclictest33-21ksoftirqd/219:54:512
11702996626,4cyclictest25-21ksoftirqd/120:25:281
134491650,5ptp4l0-21swapper/219:09:482
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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