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2026-02-14 - 12:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Feb 14, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2663221530,6sleep20-21swapper/223:25:272
134491740,3ptp4l0-21swapper/323:43:103
134491650,3ptp4l20633-21ntpq20:55:220
134491610,5ptp4l0-21swapper/023:20:140
134491610,4ptp4l1226-21latency_hist22:35:003
134491580,4ptp4l0-21swapper/300:33:563
134491570,3ptp4l0-21swapper/121:04:361
134491570,1ptp4l0-21swapper/119:41:201
134491560,5ptp4l0-21swapper/300:16:123
134491560,4ptp4l0-21swapper/220:14:412
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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