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2026-06-12 - 15:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Jun 12, 2026 12:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
176622990,5sleep00-21swapper/010:15:270
2703399692,25cyclictest0-21swapper/208:32:212
2703399670,31cyclictest27149-21taskset10:38:332
2703399660,38cyclictest26970-21chrt08:17:362
2703399660,35cyclictest6602-21taskset12:14:202
134491660,4ptp4l21639-21ntp_states08:05:243
2703399643,36cyclictest0-21swapper/209:05:092
2703399641,61cyclictest0-21swapper/212:20:282
2703399641,61cyclictest0-21swapper/210:45:292
2703399640,30cyclictest20206-21taskset10:22:562
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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