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2026-05-28 - 18:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu May 28, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1109221620,2sleep2315199cyclictest08:35:162
2938721550,3sleep0314999cyclictest10:25:010
315099682,37cyclictest0-21swapper/108:00:221
315099650,62cyclictest13439-21iostat07:30:171
157582650,5sleep20-21swapper/207:35:132
315099641,60cyclictest1110-21users10:30:281
326322630,5sleep132470-21irqrtprio09:20:191
315099631,24cyclictest24292-21timerandwakeup11:20:271
226552630,7sleep3315299cyclictest10:10:113
134491620,5ptp4l0-21swapper/310:00:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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