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2026-07-02 - 06:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jul 02, 2026 00:45:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2103199642,19cyclictest0-21swapper/021:55:230
134491640,4ptp4l0-21swapper/323:30:253
2103299618,22cyclictest766-21gdbus00:35:241
134491600,4ptp4l0-21swapper/322:30:153
134491600,4ptp4l0-21swapper/319:40:173
2103199590,18cyclictest14547-21cat23:35:010
134491590,3ptp4l0-21swapper/300:35:183
2103199580,24cyclictest32711-21seq20:45:060
134491580,4ptp4l0-21swapper/322:36:513
134491580,4ptp4l0-21swapper/221:13:562
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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