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2026-08-05 - 11:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Aug 05, 2026 00:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3258821760,6sleep12516499cyclictest19:25:171
2516599782,74cyclictest0-21swapper/221:05:282
134491640,4ptp4l0-21swapper/021:45:150
134491640,22ptp4l5129-21df23:05:150
134491600,5ptp4l0-21swapper/119:20:291
134491600,4ptp4l0-21swapper/222:15:262
134491600,4ptp4l0-21swapper/100:25:251
134491590,4ptp4l0-21swapper/119:05:121
134491590,4ptp4l0-21swapper/022:35:150
134491580,4ptp4l0-21swapper/021:15:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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