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2026-03-05 - 06:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Mar 05, 2026 00:45:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491820,1ptp4l321ktimersoftd/220:19:582
310722700,3sleep00-21swapper/019:15:180
27879996530,6cyclictest41-21ksoftirqd/322:20:003
27879996428,5cyclictest41-21ksoftirqd/323:05:153
27879996230,4cyclictest41-21ksoftirqd/322:27:563
27879996229,7cyclictest41-21ksoftirqd/300:20:013
27879996229,4cyclictest41-21ksoftirqd/320:59:313
27879996226,4cyclictest41-21ksoftirqd/320:49:213
27879996135,4cyclictest41-21ksoftirqd/300:36:593
27879996132,4cyclictest41-21ksoftirqd/323:29:423
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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