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2026-05-20 - 19:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed May 20, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2042621430,4sleep21891499cyclictest10:40:192
2729121360,6sleep01891299cyclictest09:45:210
18915996733,5cyclictest41-21ksoftirqd/310:40:113
18915996432,4cyclictest41-21ksoftirqd/309:55:183
34542630,6sleep00-21swapper/012:25:120
18915996333,6cyclictest41-21ksoftirqd/309:35:193
18915996329,4cyclictest41-21ksoftirqd/308:05:143
18915996225,8cyclictest41-21ksoftirqd/312:35:223
134491620,4ptp4l26864-21memory07:25:201
18915996133,8cyclictest41-21ksoftirqd/307:25:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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