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2026-07-30 - 19:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jul 30, 2026 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2367021280,3sleep11369899cyclictest10:55:201
141972820,5sleep00-21swapper/011:45:140
1369999760,10cyclictest33-21ksoftirqd/208:50:502
274312690,6sleep31370099cyclictest11:05:133
13699996934,6cyclictest33-21ksoftirqd/212:35:142
13699996731,6cyclictest33-21ksoftirqd/209:30:002
134491670,6ptp4l0-21swapper/007:09:290
13699996633,7cyclictest33-21ksoftirqd/210:40:002
13699996532,4cyclictest33-21ksoftirqd/207:46:472
13699996531,7cyclictest33-21ksoftirqd/209:48:322
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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