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2026-06-06 - 19:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jun 06, 2026 00:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1364721570,5sleep2500599cyclictest20:35:242
193721360,4sleep2500599cyclictest20:10:242
500499740,70cyclictest1114-21/usr/sbin/munin20:10:151
500499730,41cyclictest3140-21chrt23:42:281
500499730,2cyclictest4700-21ntpq23:45:211
500499700,30cyclictest31262-21date22:25:001
27792660,6sleep20-21swapper/219:05:132
500499652,27cyclictest0-21swapper/123:15:141
64242640,4sleep30-21swapper/323:50:183
500499640,24cyclictest23689-21latency_hist19:50:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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