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2026-06-28 - 13:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Jun 28, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
162599690,66cyclictest30770-21wc20:10:203
162599684,22cyclictest137891phc2sys22:05:593
293392630,3sleep20-21swapper/221:15:302
162599620,23cyclictest1301-21snmpd00:25:493
162599620,23cyclictest1301-21snmpd00:25:493
162599620,18cyclictest5629-21unixbench_singl19:15:293
162599612,21cyclictest0-21swapper/323:14:473
162599610,58cyclictest14993-21phc2sys-jitter20:45:243
162599610,58cyclictest14993-21phc2sys-jitter20:45:243
162599610,26cyclictest15959-21taskset23:07:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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