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2026-03-25 - 19:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Mar 25, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2789521620,4sleep32537599cyclictest10:41:273
142221430,3sleep12537399cyclictest12:05:131
316012750,7sleep02537299cyclictest09:40:180
140642750,5sleep20-21swapper/211:20:252
200552650,3sleep220059-21needreboot09:15:202
134491640,8ptp4l13780-21ls10:10:262
134491600,4ptp4l0-21swapper/109:33:591
134491600,4ptp4l0-21swapper/109:33:591
134491580,5ptp4l5054-21latency_hist09:54:590
134491580,4ptp4l0-21swapper/110:30:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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