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2026-02-03 - 08:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Feb 03, 2026 00:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3093621750,5sleep22153199cyclictest00:05:232
3101221350,4sleep02152999cyclictest21:47:340
2153299627,15cyclictest603-21latency_hist20:45:003
159422620,5sleep20-21swapper/222:25:182
134491620,4ptp4l0-21swapper/220:10:262
134491600,4ptp4l0-21swapper/221:05:252
134491600,17ptp4l4849-21ls20:50:272
182632570,4sleep00-21swapper/022:30:170
134491570,4ptp4l0-21swapper/121:15:211
134491570,3ptp4l15763-21hwlatdetect22:25:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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