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2026-05-15 - 01:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu May 14, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491670,4ptp4l0-21swapper/010:40:240
134491640,4ptp4l0-21swapper/307:15:243
69532630,5sleep20-21swapper/210:05:242
134491620,22ptp4l0-21swapper/010:15:270
134491610,4ptp4l4063-21cut11:10:162
134491600,4ptp4l0-21swapper/011:22:440
134491590,4ptp4l0-21swapper/210:00:462
134491590,3ptp4l0-21swapper/008:12:430
134491580,4ptp4l0-21swapper/309:44:573
134491580,3ptp4l0-21swapper/309:29:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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