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2026-06-21 - 17:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Jun 21, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2206021570,3sleep33042899cyclictest12:35:273
99421420,4sleep13042699cyclictest11:50:281
3042799722,68cyclictest0-21swapper/208:50:282
3042799722,68cyclictest0-21swapper/208:50:282
3042899680,24cyclictest5075-21cpu07:25:123
111612620,7sleep03042599cyclictest07:35:270
134491610,5ptp4l0-21swapper/012:15:110
134491600,18ptp4l0-21swapper/109:05:181
30428995912,45cyclictest0-21swapper/309:49:483
3042899590,4cyclictest5637-21unixbench_multi12:00:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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