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2026-04-07 - 04:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Apr 07, 2026 00:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1476321660,6sleep01449899cyclictest21:30:010
1782221530,5sleep11449999cyclictest21:35:161
214221360,4sleep30-21swapper/319:50:263
617121330,3sleep11449999cyclictest20:00:191
1450099792,75cyclictest0-21swapper/200:30:292
14501996925,9cyclictest41-21ksoftirqd/321:45:163
14501996734,4cyclictest41-21ksoftirqd/320:05:003
14501996729,8cyclictest41-21ksoftirqd/320:15:003
14501996632,4cyclictest41-21ksoftirqd/300:15:153
14501996628,9cyclictest41-21ksoftirqd/322:05:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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