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2026-01-02 - 19:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Jan 02, 2026 12:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
694021620,7sleep23096799cyclictest08:35:152
216922670,3sleep10-21swapper/109:05:221
134491570,3ptp4l0-21swapper/310:30:283
134491560,12ptp4l29524-21memory07:05:200
134491550,3ptp4l0-21swapper/208:34:362
134491540,12ptp4l0-21swapper/209:44:492
134491530,4ptp4l0-21swapper/312:12:503
134491530,4ptp4l0-21swapper/209:24:422
134491530,4ptp4l0-21swapper/207:28:562
134491530,4ptp4l0-21swapper/007:45:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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