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2026-07-07 - 00:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Jul 06, 2026 00:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26124997616,56cyclictest10243-21unixbench_singl22:00:282
246602670,5sleep00-21swapper/020:15:150
26124996326,5cyclictest33-21ksoftirqd/221:10:002
26124996024,7cyclictest33-21ksoftirqd/200:31:162
155282600,4sleep00-21swapper/021:05:130
134491600,5ptp4l0-21swapper/220:25:252
134491600,4ptp4l0-21swapper/019:41:300
40982590,5sleep30-21swapper/321:50:143
26124995927,4cyclictest33-21ksoftirqd/223:01:252
26124995924,2cyclictest33-21ksoftirqd/200:20:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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