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2026-08-27 - 22:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Aug 27, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
111112850,5sleep10-21swapper/111:20:271
141462810,4sleep00-21swapper/011:30:000
285182680,5sleep10-21swapper/108:30:211
134491660,27ptp4l15140-21meminfo10:20:211
134491620,4ptp4l0-21swapper/209:00:012
134491610,4ptp4l0-21swapper/208:38:042
134491610,18ptp4l0-21swapper/107:45:001
134491590,4ptp4l0-21swapper/211:00:222
134491590,4ptp4l0-21swapper/008:12:310
134491580,3ptp4l0-21swapper/308:34:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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