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2026-02-15 - 12:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Feb 15, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
599221590,4sleep22872599cyclictest20:40:112
263132720,5sleep00-21swapper/022:30:250
28726997136,4cyclictest41-21ksoftirqd/323:40:003
28726997035,4cyclictest41-21ksoftirqd/320:20:003
28726996533,3cyclictest41-21ksoftirqd/323:15:243
28726996529,7cyclictest41-21ksoftirqd/321:00:203
134491650,4ptp4l17325-21ntp_states00:30:231
134491650,4ptp4l0-21swapper/119:15:241
28726996430,7cyclictest41-21ksoftirqd/322:00:213
28726996429,7cyclictest41-21ksoftirqd/319:45:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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