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2026-09-03 - 23:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Sep 03, 2026 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2574499820,79cyclictest11412-21cat10:05:262
2574499820,79cyclictest11412-21cat10:05:262
25744997713,62cyclictest0-21swapper/209:40:292
2574499707,61cyclictest0-21swapper/212:30:282
2574499706,61cyclictest0-21swapper/211:10:282
2574499690,22cyclictest5129-21latency_hist09:54:592
75542680,4sleep00-21swapper/011:10:000
2574499670,29cyclictest28246-21chrt10:44:192
2574499670,27cyclictest25090-21phc2sys10:35:242
2574499670,27cyclictest25090-21phc2sys10:35:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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