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2026-03-11 - 09:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Mar 11, 2026 00:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20096996534,5cyclictest33-21ksoftirqd/200:35:182
20096996432,6cyclictest33-21ksoftirqd/223:20:272
20096996432,10cyclictest33-21ksoftirqd/220:00:242
20096996422,8cyclictest33-21ksoftirqd/221:10:242
20096996235,3cyclictest33-21ksoftirqd/220:15:262
20096996231,3cyclictest33-21ksoftirqd/219:50:252
20096996230,6cyclictest33-21ksoftirqd/219:45:002
20096996227,5cyclictest33-21ksoftirqd/223:35:012
20096996227,5cyclictest33-21ksoftirqd/223:35:012
134491620,4ptp4l0-21swapper/023:22:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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