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2026-02-22 - 05:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Feb 22, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
818521400,6sleep3443699cyclictest21:35:183
48562870,4sleep20-21swapper/220:20:002
443699812,77cyclictest0-21swapper/322:10:203
443699740,61cyclictest8551-21seq19:16:403
443699732,68cyclictest17580-21irqrtprio23:05:183
443699730,28cyclictest10635-21cut00:00:163
443699701,25cyclictest25446-21mailstats23:20:243
443699700,28cyclictest1301-21snmpd23:35:143
443699691,25cyclictest20100-21tune2fs00:20:173
443699690,29cyclictest28722-21/usr/sbin/munin23:30:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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