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2026-06-05 - 05:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Jun 05, 2026 00:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1845121580,6sleep3745899cyclictest21:50:263
1953021510,6sleep3745899cyclictest20:45:153
2710821280,5sleep3745899cyclictest21:00:193
110442730,4sleep00-21swapper/021:35:220
134491650,4ptp4l0-21swapper/020:49:100
134491630,23ptp4l0-21swapper/120:11:461
7458996230,7cyclictest41-21ksoftirqd/323:40:003
7458996223,6cyclictest41-21ksoftirqd/300:30:163
7458996128,8cyclictest41-21ksoftirqd/322:15:083
745899612,29cyclictest0-21swapper/300:27:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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