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2026-09-24 - 09:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Sep 24, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2080321670,6sleep12335899cyclictest22:30:251
495221340,3sleep02335799cyclictest21:55:270
2336099762,71cyclictest0-21swapper/322:05:003
134491630,4ptp4l0-21swapper/120:45:201
134491630,3ptp4l8413-21/usr/sbin/munin00:25:292
2336099613,16cyclictest0-21swapper/321:50:273
134491610,4ptp4l0-21swapper/320:25:023
134491600,4ptp4l2617-21ntp_states00:10:192
134491600,18ptp4l0-21swapper/220:00:282
134491600,17ptp4l0-21swapper/220:54:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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