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2025-11-15 - 03:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Nov 15, 2025 00:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2847191670,25ptp4l22386-21latency_hist20:10:010
2847191620,4ptp4l0-21swapper/022:54:030
2847191610,4ptp4l0-21swapper/321:04:503
2847191610,4ptp4l0-21swapper/320:01:283
2847191610,3ptp4l30153-21/usr/sbin/munin19:15:220
2847191600,10ptp4l23741-21kworker/2:200:15:252
300632590,4sleep00-21swapper/020:25:200
2847191590,3ptp4l0-21swapper/123:25:001
2847191580,3ptp4l14394-21ls19:50:260
2847191580,3ptp4l0-21swapper/221:42:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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