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2026-02-20 - 11:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Feb 20, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2797399822,3cyclictest0-21swapper/219:40:282
2797399811,3cyclictest0-21swapper/222:05:292
2797499672,45cyclictest0-21swapper/321:45:213
2797199651,2cyclictest134491ptp4l20:50:000
2797499632,35cyclictest0-21swapper/300:22:433
27974996228,8cyclictest41-21ksoftirqd/322:35:003
2797499622,32cyclictest0-21swapper/321:05:213
134491620,3ptp4l20432-21meminfo21:10:201
134491620,24ptp4l33-21ksoftirqd/219:07:592
27974996129,6cyclictest41-21ksoftirqd/320:15:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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