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2026-04-06 - 12:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Apr 06, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1297721640,5sleep22378899cyclictest23:25:142
72632800,6sleep00-21swapper/022:00:300
6402700,5sleep20-21swapper/220:40:002
134491620,4ptp4l10662-21taskset00:28:530
134491610,5ptp4l0-21swapper/121:30:151
36812590,3sleep32378999cyclictest23:05:123
134491590,5ptp4l27595-21memory21:35:210
134491590,3ptp4l23397-21ps22:35:231
134491580,3ptp4l4455-21memory21:55:191
134491580,3ptp4l0-21swapper/119:30:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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