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2026-09-17 - 01:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Sep 16, 2026 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
271692880,4sleep30-21swapper/312:20:143
134491700,4ptp4l20599-21/usr/sbin/munin07:25:260
133302660,4sleep30-21swapper/308:20:193
134491650,5ptp4l0-21swapper/111:15:201
134491600,4ptp4l0-21swapper/310:15:213
134491600,4ptp4l0-21swapper/308:06:323
134491590,4ptp4l0-21swapper/008:00:240
134491580,4ptp4l0-21swapper/212:35:322
134491580,3ptp4l0-21swapper/210:58:392
134491580,3ptp4l0-21swapper/111:50:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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