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2026-03-02 - 06:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Mar 02, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
314452740,4sleep10-21swapper/120:30:211
25744997331,9cyclictest41-21ksoftirqd/300:25:013
134491700,4ptp4l0-21swapper/022:04:570
25744996631,4cyclictest41-21ksoftirqd/322:35:173
25744996532,9cyclictest41-21ksoftirqd/321:15:123
25744996433,9cyclictest41-21ksoftirqd/323:50:153
25744996330,10cyclictest41-21ksoftirqd/321:40:263
25744996330,10cyclictest41-21ksoftirqd/321:40:263
25744996324,8cyclictest41-21ksoftirqd/300:35:213
220292630,2sleep222033-21cpuspeed_turbos23:40:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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