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2025-11-16 - 19:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Nov 16, 2025 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2847191700,22ptp4l1174-21/usr/sbin/munin12:05:271
2847191640,10ptp4l0-21swapper/307:15:173
309352630,4sleep10-21swapper/112:00:241
309352630,4sleep10-21swapper/112:00:241
2847191620,3ptp4l0-21swapper/111:41:461
2847191610,4ptp4l0-21swapper/312:33:003
2847191590,19ptp4l0-21swapper/210:20:152
94152580,4sleep00-21swapper/012:25:180
2847191580,4ptp4l0-21swapper/309:35:213
2847191580,4ptp4l0-21swapper/309:35:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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