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2026-02-24 - 17:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Feb 24, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2089721510,5sleep0634299cyclictest10:00:000
3157021270,3sleep1634399cyclictest09:10:271
165521150,4sleep0101ktimersoftd/009:17:000
6344997713,62cyclictest0-21swapper/209:09:282
6345997331,10cyclictest41-21ksoftirqd/309:17:063
6344996913,54cyclictest0-21swapper/208:25:292
6345996631,8cyclictest41-21ksoftirqd/311:48:463
6345996631,8cyclictest41-21ksoftirqd/311:48:463
134491660,4ptp4l0-21swapper/109:40:151
6345996325,5cyclictest41-21ksoftirqd/311:40:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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