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2026-05-12 - 02:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon May 11, 2026 12:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
319692750,3sleep231968-21grep09:25:252
319692750,3sleep231968-21grep09:25:252
176342750,4sleep10-21swapper/110:05:201
134491630,2ptp4l6698-21ls09:40:251
134491620,5ptp4l0-21swapper/010:30:200
37299597,6cyclictest0-21swapper/011:50:280
37299577,6cyclictest0-21swapper/011:00:130
134491570,5ptp4l0-21swapper/010:15:200
134491570,3ptp4l0-21swapper/008:40:350
37499566,6cyclictest0-21swapper/212:15:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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