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2026-02-25 - 06:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Feb 25, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2089121410,3sleep2413599cyclictest00:20:292
134491720,3ptp4l1640-21ls23:40:262
206792710,3sleep120675-21gpgv23:15:011
134491640,17ptp4l0-21swapper/321:00:173
134491620,17ptp4l0-21swapper/022:15:150
134491590,3ptp4l3499-21ls20:15:262
134491590,17ptp4l25517-21wc23:25:002
134491580,4ptp4l0-21swapper/323:23:323
134491580,4ptp4l0-21swapper/219:50:212
134491580,3ptp4l0-21swapper/320:08:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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