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2026-05-30 - 08:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat May 30, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
913921750,6sleep0895699cyclictest21:30:110
895799802,76cyclictest28642-21kworker/1:219:15:291
8956996629,6cyclictest9-21ksoftirqd/022:30:190
8956996532,5cyclictest9-21ksoftirqd/023:30:260
8958996429,4cyclictest33-21ksoftirqd/222:50:252
895799640,62cyclictest28642-21kworker/1:222:55:291
8956996431,5cyclictest9-21ksoftirqd/021:05:010
8956996430,6cyclictest9-21ksoftirqd/023:25:260
8956996328,9cyclictest9-21ksoftirqd/019:55:000
8956996231,6cyclictest9-21ksoftirqd/020:30:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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