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2026-07-22 - 08:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jul 22, 2026 00:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3125999775,70cyclictest0-21swapper/321:50:193
3125999756,6cyclictest137891phc2sys23:01:403
3125999746,40cyclictest0-21swapper/319:30:233
31258997412,60cyclictest0-21swapper/200:05:292
3125899684,62cyclictest0-21swapper/223:25:292
31259996713,18cyclictest18710-21taskset00:27:453
31259996613,11cyclictest20822-21taskset23:24:503
31259996612,19cyclictest8294-21taskset21:49:473
31259996514,16cyclictest14530-21taskset00:20:103
31259996513,12cyclictest21964-21taskset21:07:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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