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2026-08-21 - 02:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Aug 20, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1689721690,5sleep11418099cyclictest08:25:111
2250121170,3sleep21418199cyclictest09:45:202
134491750,7ptp4l121rcu_preempt11:05:013
134491750,7ptp4l121rcu_preempt11:05:013
134491680,3ptp4l121rcu_preempt09:50:173
134491680,3ptp4l121rcu_preempt08:50:293
134491620,4ptp4l0-21swapper/210:30:282
134491620,19ptp4l0-21swapper/311:30:263
134691600,5getstats0-21swapper/107:05:041
134491600,3ptp4l0-21swapper/208:35:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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