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2026-01-10 - 06:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jan 10, 2026 00:45:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
856998142,3cyclictest33-21ksoftirqd/200:00:152
856996629,6cyclictest33-21ksoftirqd/219:55:152
856996531,11cyclictest33-21ksoftirqd/220:30:532
856996429,4cyclictest33-21ksoftirqd/221:35:262
856996330,9cyclictest33-21ksoftirqd/222:35:272
854996310,9cyclictest3051-21tail22:40:260
134491630,4ptp4l19996-21df_inode19:50:151
856996130,3cyclictest33-21ksoftirqd/221:35:012
856996129,5cyclictest33-21ksoftirqd/220:15:262
856996127,7cyclictest33-21ksoftirqd/220:00:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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