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2025-11-27 - 22:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Nov 27, 2025 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2182721720,3sleep20-21swapper/207:05:292
2847191710,4ptp4l8987-21taskset08:57:180
2847191650,5ptp4l21492-21proc_pri07:05:261
2847191650,4ptp4l25283-21interrupts11:50:170
2847191640,4ptp4l26418-21systemctl08:25:240
2847191640,3ptp4l0-21swapper/010:35:280
2847191630,4ptp4l0-21swapper/009:32:020
2847191620,3ptp4l13199-21irqstats10:15:210
2847191610,5ptp4l0-21swapper/009:55:150
2847191600,5ptp4l0-21swapper/112:20:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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