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2026-05-16 - 17:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat May 16, 2026 12:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22364997735,4cyclictest41-21ksoftirqd/307:35:003
2236499712,31cyclictest0-21swapper/310:52:093
22364997027,8cyclictest41-21ksoftirqd/310:45:233
134491700,5ptp4l0-21swapper/011:30:110
22364996928,4cyclictest41-21ksoftirqd/312:10:003
22363996938,3cyclictest33-21ksoftirqd/208:50:002
22363996933,5cyclictest33-21ksoftirqd/210:30:012
22364996826,9cyclictest41-21ksoftirqd/310:40:243
22364996731,3cyclictest41-21ksoftirqd/310:10:233
2236499672,32cyclictest0-21swapper/307:55:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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