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2026-07-12 - 08:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Jul 12, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
539621870,3sleep20-21swapper/219:05:272
250121430,6sleep3630299cyclictest23:39:593
2670021200,5sleep00-21swapper/023:20:240
6300997124,4cyclictest25-21ksoftirqd/120:18:281
6300996924,4cyclictest25-21ksoftirqd/122:33:321
6300996923,8cyclictest25-21ksoftirqd/120:20:201
134491670,20ptp4l0-21swapper/200:05:182
6300996425,4cyclictest25-21ksoftirqd/123:15:201
6300995922,4cyclictest25-21ksoftirqd/122:57:551
134491580,5ptp4l0-21swapper/021:50:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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