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2025-11-13 - 15:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Nov 13, 2025 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1410321740,2sleep32184499cyclictest20:00:263
2847191670,21ptp4l30527-21df00:05:142
210462620,6sleep20-21swapper/222:35:182
2847191610,9ptp4l0-21swapper/221:40:222
63802600,3sleep20-21swapper/219:45:212
2847191600,4ptp4l0-21swapper/221:39:072
2847191600,3ptp4l0-21swapper/121:40:291
21842996027,7cyclictest25-21ksoftirqd/100:00:001
2847191590,4ptp4l0-21swapper/223:10:242
2847191590,4ptp4l0-21swapper/200:05:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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