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2026-04-21 - 15:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Apr 21, 2026 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2271021540,4sleep2651099cyclictest07:45:122
6509997612,62cyclictest11819-21kworker/1:111:25:491
134491620,3ptp4l0-21swapper/010:40:290
650999601,57cyclictest11819-21kworker/1:109:31:091
134491580,22ptp4l9-21ksoftirqd/012:20:190
164082570,3sleep10-21swapper/108:40:151
134491570,4ptp4l0-21swapper/208:47:062
134491570,4ptp4l0-21swapper/108:05:191
134491570,3ptp4l0-21swapper/011:20:130
134491570,3ptp4l0-21swapper/010:20:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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