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2025-11-03 - 13:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Nov 03, 2025 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2263121330,2sleep22811199cyclictest22:25:212
2847191690,5ptp4l6963-21grep21:50:243
2847191660,5ptp4l0-21swapper/121:35:191
2847191640,28ptp4l9-21ksoftirqd/022:10:170
2847191640,28ptp4l9-21ksoftirqd/022:10:170
267052620,6sleep30-21swapper/319:05:193
2847191600,4ptp4l0-21swapper/122:10:281
2847191600,4ptp4l0-21swapper/122:10:281
2810999601,5cyclictest2849491getstats20:50:300
2847191590,3ptp4l0-21swapper/000:30:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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