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2025-12-11 - 22:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Dec 11, 2025 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2695421660,7sleep02676399cyclictest08:20:000
126692770,5sleep20-21swapper/210:05:242
2847191610,3ptp4l0-21swapper/007:35:210
2847191600,20ptp4l0-21swapper/009:20:590
2847191590,5ptp4l0-21swapper/107:20:221
2847191590,4ptp4l30307-21hddtemp_smartct09:35:171
2847191590,4ptp4l0-21swapper/111:35:191
2847191590,3ptp4l0-21swapper/311:35:283
2847191580,4ptp4l0-21swapper/311:13:513
2847191580,4ptp4l0-21swapper/208:50:362
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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