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2026-03-06 - 08:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Mar 06, 2026 00:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2202099772,33cyclictest0-21swapper/320:25:473
2202099732,32cyclictest0-21swapper/300:00:263
134491680,4ptp4l0-21swapper/122:50:561
134491680,4ptp4l0-21swapper/122:50:561
177632670,6sleep02201799cyclictest20:10:010
22019996634,4cyclictest33-21ksoftirqd/222:05:162
134491660,17ptp4l11290-21hddtemp_smartct21:05:181
22019996530,6cyclictest33-21ksoftirqd/223:51:172
22019996330,4cyclictest33-21ksoftirqd/222:45:532
22019996131,3cyclictest33-21ksoftirqd/221:05:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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