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2026-05-17 - 06:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun May 17, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1865799763,31cyclictest0-21swapper/223:25:232
134491720,3ptp4l0-21swapper/120:44:561
134491700,22ptp4l17507-21/usr/sbin/munin22:35:160
1865799683,30cyclictest0-21swapper/222:50:152
134491660,5ptp4l4062-21phc2sys-jitter20:55:251
18657996535,6cyclictest33-21ksoftirqd/222:15:192
18657996531,9cyclictest33-21ksoftirqd/220:15:002
18657996531,9cyclictest33-21ksoftirqd/220:15:002
18657996128,4cyclictest33-21ksoftirqd/223:40:262
134491610,5ptp4l0-21swapper/220:29:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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