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2026-05-09 - 03:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri May 08, 2026 12:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26632880,4sleep00-21swapper/011:20:170
1532099738,62cyclictest0-21swapper/212:15:302
1532099738,62cyclictest0-21swapper/212:15:292
15320996233,9cyclictest33-21ksoftirqd/208:10:232
15320996123,5cyclictest33-21ksoftirqd/209:00:132
134491610,4ptp4l0-21swapper/110:50:151
134491610,17ptp4l0-21swapper/112:15:141
134491610,17ptp4l0-21swapper/112:15:141
212212600,6sleep21532099cyclictest08:30:172
15320996028,5cyclictest33-21ksoftirqd/210:57:372
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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