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2026-02-28 - 17:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Feb 28, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2293221690,6sleep11342799cyclictest09:45:271
239621590,6sleep11342799cyclictest11:20:261
1342999782,32cyclictest0-21swapper/309:05:153
1342999742,30cyclictest0-21swapper/309:10:133
134491690,4ptp4l7201-21hddtemp_smartct08:05:151
13429996733,8cyclictest41-21ksoftirqd/310:10:003
134491660,4ptp4l0-21swapper/107:20:251
13429996532,7cyclictest41-21ksoftirqd/308:35:143
13429996530,9cyclictest41-21ksoftirqd/308:10:153
13429996529,10cyclictest41-21ksoftirqd/309:00:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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