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2026-04-08 - 16:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Apr 08, 2026 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7352997837,7cyclictest41-21ksoftirqd/310:20:013
7351997331,3cyclictest33-21ksoftirqd/212:35:282
7352997233,4cyclictest41-21ksoftirqd/312:20:003
7352997127,9cyclictest41-21ksoftirqd/311:15:163
7352996920,8cyclictest41-21ksoftirqd/307:40:003
7352996835,4cyclictest41-21ksoftirqd/308:40:153
7352996827,4cyclictest41-21ksoftirqd/310:30:143
7349996832,4cyclictest9-21ksoftirqd/009:30:170
7352996634,4cyclictest41-21ksoftirqd/309:25:003
7352996626,8cyclictest41-21ksoftirqd/307:52:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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