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2026-05-09 - 15:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat May 09, 2026 12:45:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1404721570,6sleep32704499cyclictest07:50:193
2704399762,33cyclictest0-21swapper/207:30:232
27043996730,5cyclictest33-21ksoftirqd/209:25:002
27043996534,4cyclictest33-21ksoftirqd/208:55:002
27043996330,5cyclictest33-21ksoftirqd/211:50:012
27043996231,6cyclictest33-21ksoftirqd/207:45:192
27043996231,5cyclictest33-21ksoftirqd/207:10:152
27043996229,8cyclictest33-21ksoftirqd/209:40:002
27043996228,5cyclictest33-21ksoftirqd/209:55:282
27043996227,4cyclictest33-21ksoftirqd/208:41:332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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