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2026-02-26 - 06:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Feb 26, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
626621350,4sleep31177099cyclictest21:15:193
11768996934,7cyclictest25-21ksoftirqd/122:40:231
11770996712,52cyclictest9312-21taskset20:13:153
1177099665,17cyclictest0-21swapper/320:05:273
1177099659,10cyclictest23986-21tune2fs19:35:153
11770996512,11cyclictest16760-21chrt22:45:373
11770996511,10cyclictest26332-21awk22:00:003
11770996510,11cyclictest22751-21sed23:00:183
11768996530,7cyclictest25-21ksoftirqd/100:00:001
11768996528,8cyclictest25-21ksoftirqd/123:35:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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