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2026-03-21 - 12:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Mar 21, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
489899684,62cyclictest20804-21kworker/1:219:50:481
134491650,5ptp4l0-21swapper/321:40:123
4897996429,4cyclictest9-21ksoftirqd/022:15:170
4897996330,6cyclictest9-21ksoftirqd/021:15:000
134491610,4ptp4l0-21swapper/023:20:250
4897996021,6cyclictest9-21ksoftirqd/000:35:230
4897996021,6cyclictest9-21ksoftirqd/000:35:230
134491600,3ptp4l22473-21ls20:55:202
4897995927,3cyclictest9-21ksoftirqd/019:25:450
4897995923,6cyclictest9-21ksoftirqd/021:49:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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