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2025-11-20 - 22:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Nov 20, 2025 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2847191670,4ptp4l14062-21irqrtprio08:10:193
2847191640,1ptp4l241ktimersoftd/112:16:061
2847191630,4ptp4l0-21swapper/209:11:242
2847191620,4ptp4l0-21swapper/110:54:271
2847191610,5ptp4l0-21swapper/209:00:272
2847191600,5ptp4l0-21swapper/208:20:142
2847191600,5ptp4l0-21swapper/109:35:181
51572590,6sleep30-21swapper/307:50:223
2847191590,4ptp4l0-21swapper/009:40:200
2847191580,4ptp4l0-21swapper/209:55:292
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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