You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-07-22 - 20:24
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jul 22, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491700,11ptp4l0-21swapper/211:35:242
15828996728,8cyclictest41-21ksoftirqd/308:06:463
15828996728,8cyclictest41-21ksoftirqd/308:06:463
15828996728,7cyclictest41-21ksoftirqd/310:53:553
15828996626,8cyclictest41-21ksoftirqd/311:24:563
15828996530,8cyclictest41-21ksoftirqd/310:00:143
15828996526,8cyclictest41-21ksoftirqd/309:02:303
15828996526,8cyclictest41-21ksoftirqd/308:10:073
134491650,4ptp4l0-21swapper/110:30:211
15828996433,4cyclictest41-21ksoftirqd/307:45:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional