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2026-08-16 - 06:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Aug 16, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
265682710,5sleep30-21swapper/319:35:213
1407299673,61cyclictest0-21swapper/200:05:292
14071996632,7cyclictest25-21ksoftirqd/123:20:221
1407299654,59cyclictest0-21swapper/220:40:292
1407299635,56cyclictest0-21swapper/221:40:092
14071996329,4cyclictest25-21ksoftirqd/122:35:201
14071996231,7cyclictest25-21ksoftirqd/122:30:251
14071996221,7cyclictest25-21ksoftirqd/119:50:251
14071996221,7cyclictest25-21ksoftirqd/119:50:251
14071996130,8cyclictest25-21ksoftirqd/122:25:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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