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2025-11-14 - 15:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Nov 14, 2025 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2847191790,11ptp4l23796-21hddtemp_smartct19:05:151
231232720,4sleep00-21swapper/020:10:340
25710996420,4cyclictest25-21ksoftirqd/121:20:571
25711996332,6cyclictest33-21ksoftirqd/220:00:002
25711996332,6cyclictest33-21ksoftirqd/220:00:002
25711996328,9cyclictest33-21ksoftirqd/223:13:552
186592630,3sleep018662-21cpuspeed_turbos23:30:170
2847191620,4ptp4l10358-21apt-get22:05:042
2847191620,4ptp4l0-21swapper/319:16:563
25709996218,4cyclictest9-21ksoftirqd/019:20:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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