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2026-08-02 - 05:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Aug 02, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2289221600,4sleep2672799cyclictest23:10:292
134491700,3ptp4l33-21ksoftirqd/223:21:542
134491630,3ptp4l13435-1kworker/0:1H20:00:140
134491630,26ptp4l0-21swapper/021:45:200
134491610,5ptp4l0-21swapper/122:50:221
134491600,5ptp4l0-21swapper/120:15:261
134491600,5ptp4l0-21swapper/120:15:261
134491580,4ptp4l0-21swapper/019:35:200
134491580,3ptp4l0-21swapper/319:10:143
134491560,4ptp4l0-21swapper/022:50:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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