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2026-06-26 - 11:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Jun 26, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
171721570,6sleep2420599cyclictest23:40:262
171721570,6sleep2420599cyclictest23:40:262
1976321510,5sleep1420499cyclictest00:20:171
420499832,78cyclictest28473-21kworker/1:220:05:091
420499762,72cyclictest25273-21kworker/1:021:55:291
134491690,3ptp4l41-21ksoftirqd/322:18:173
134491660,32ptp4l0-21swapper/200:28:282
134491640,4ptp4l0-21swapper/023:50:160
193952600,5sleep00-21swapper/023:10:200
4204995917,40cyclictest23724-21kworker/1:223:05:481
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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