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2026-08-13 - 14:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Aug 13, 2026 00:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2470321710,6sleep22878099cyclictest23:40:012
2976421590,5sleep12877999cyclictest19:10:211
2976421590,5sleep12877999cyclictest19:10:211
3077821440,4sleep22878099cyclictest21:30:272
28781997232,5cyclictest41-21ksoftirqd/323:33:183
313362680,3sleep10-21swapper/120:25:151
28781996722,4cyclictest41-21ksoftirqd/321:05:173
28781996639,4cyclictest41-21ksoftirqd/323:38:083
134491660,23ptp4l648-21ntp_states23:55:251
28781996531,4cyclictest41-21ksoftirqd/322:20:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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