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2026-04-13 - 11:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Apr 13, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1626321660,7sleep0909899cyclictest20:35:160
910199646,16cyclictest2117-21grep20:05:123
134491640,6ptp4l0-21swapper/019:05:190
910199604,15cyclictest16128-21/usr/sbin/munin21:45:153
910199604,11cyclictest13581-21latency_hist21:40:003
910199604,11cyclictest13581-21latency_hist21:40:003
254522600,4sleep30-21swapper/319:45:163
134491600,4ptp4l0-21swapper/120:50:271
134491600,4ptp4l0-21swapper/120:50:271
134491570,4ptp4l0-21swapper/122:15:421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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