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2026-03-30 - 19:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Mar 30, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491910,3ptp4l0-21swapper/311:34:463
280322850,4sleep30-21swapper/311:55:173
103192820,5sleep233-21ksoftirqd/212:25:252
2402199792,32cyclictest0-21swapper/212:15:142
134491790,27ptp4l3387-21chrt09:53:441
2402199772,33cyclictest0-21swapper/208:20:222
275812740,4sleep09-21ksoftirqd/010:45:170
24021997312,59cyclictest0-21swapper/212:05:282
2402199672,36cyclictest0-21swapper/207:50:292
2402199672,35cyclictest0-21swapper/209:30:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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