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2026-04-12 - 11:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Apr 12, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491610,4ptp4l26053-21diskstats20:15:170
134491590,4ptp4l0-21swapper/122:34:061
134491580,17ptp4l0-21swapper/119:25:011
134491570,4ptp4l0-21swapper/300:21:383
134491570,4ptp4l0-21swapper/122:10:231
134491570,4ptp4l0-21swapper/120:05:591
134491570,3ptp4l0-21swapper/000:35:260
134491560,4ptp4l0-21swapper/220:46:472
134491560,16ptp4l0-21swapper/119:40:271
134491550,5ptp4l0-21swapper/021:00:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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