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2026-05-19 - 16:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue May 19, 2026 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
768021720,6sleep02854799cyclictest11:00:170
255421530,6sleep02854799cyclictest10:50:140
28547997626,5cyclictest9-21ksoftirqd/009:40:010
2854999694,63cyclictest0-21swapper/211:45:292
134491620,4ptp4l11218-21meminfo07:40:180
134491600,4ptp4l0-21swapper/112:15:171
134491600,3ptp4l29364-21df09:30:140
134491600,3ptp4l29364-21df09:30:140
134491600,2ptp4l30010-21ssh07:10:273
134491600,16ptp4l0-21swapper/308:35:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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