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2026-02-21 - 08:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Feb 21, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
179312780,4sleep10-21swapper/119:40:131
134491730,4ptp4l0-21swapper/219:40:372
134491620,17ptp4l27068-21apt-get21:10:113
134491600,3ptp4l28918-21apt-get20:05:033
134491590,5ptp4l22564-21cat22:10:010
72622580,4sleep20-21swapper/220:25:192
369999589,9cyclictest25-21ksoftirqd/119:15:001
134491580,7ptp4l9134-21df_abs21:40:143
134491580,3ptp4l0-21swapper/221:45:292
134491570,3ptp4l0-21swapper/220:40:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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