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2026-05-07 - 04:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu May 07, 2026 00:45:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
48252740,5sleep34828-21switchtime00:25:253
18399997411,13cyclictest7175-21chrt22:11:022
18399997312,11cyclictest4459-21chrt20:58:162
18399997212,18cyclictest16453-21chrt20:15:042
18399997112,12cyclictest5286-21chrt23:19:222
18399997112,11cyclictest12039-21chrt22:24:132
18399997012,12cyclictest2869-21chrt22:04:442
1839999699,12cyclictest30359-21ls20:45:132
18399996912,16cyclictest9832-21chrt23:28:282
18399996912,12cyclictest1317-21runrttasks23:06:482
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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