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2025-11-16 - 06:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Nov 16, 2025 00:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
303421510,5sleep32687699cyclictest22:55:183
403521420,7sleep32687699cyclictest19:30:153
1116321260,7sleep22687599cyclictest19:45:172
9252760,2sleep20-21swapper/222:50:192
2847191670,4ptp4l0-21swapper/019:40:200
2687699641,60cyclictest10331-21cut22:00:213
2847191610,4ptp4l0-21swapper/020:17:370
2847191600,3ptp4l0-21swapper/019:10:210
2847191600,2ptp4l5309-21gzip00:09:330
2847191590,3ptp4l0-21swapper/300:29:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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