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2026-04-27 - 07:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Apr 27, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1733221530,5sleep2678299cyclictest00:10:132
1719721510,4sleep2678299cyclictest19:30:252
678299662,2cyclictest0-21swapper/221:54:092
274572640,6sleep3678399cyclictest22:10:283
134491630,4ptp4l0-21swapper/022:29:040
678199620,3cyclictest134491ptp4l23:45:181
134491620,4ptp4l0-21swapper/023:45:260
678199590,3cyclictest134491ptp4l22:45:271
134491590,4ptp4l0-21swapper/320:15:123
134491590,4ptp4l0-21swapper/222:17:042
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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