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2026-03-23 - 20:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Mar 23, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16720996535,9cyclictest33-21ksoftirqd/211:50:152
134491610,3ptp4l0-21swapper/309:55:183
134491610,3ptp4l0-21swapper/011:45:150
134491610,20ptp4l0-21swapper/108:02:131
134491600,4ptp4l0-21swapper/208:05:202
134491590,3ptp4l1301-21snmpd10:23:123
134491580,4ptp4l0-21swapper/209:05:272
134491580,4ptp4l0-21swapper/109:55:281
134491580,3ptp4l0-21swapper/109:15:301
134491580,17ptp4l0-21swapper/109:10:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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