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2026-05-21 - 07:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu May 21, 2026 00:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
478521420,4sleep1692599cyclictest23:40:181
68812750,4sleep00-21swapper/022:35:230
6926997035,6cyclictest33-21ksoftirqd/220:30:012
134491700,17ptp4l0-21swapper/019:34:140
6926996734,5cyclictest33-21ksoftirqd/221:24:592
134491660,5ptp4l0-21swapper/019:25:210
134491660,4ptp4l0-21swapper/022:45:130
6926996535,9cyclictest33-21ksoftirqd/220:40:212
6926996532,9cyclictest33-21ksoftirqd/223:45:222
6926996532,10cyclictest33-21ksoftirqd/222:45:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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