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2026-05-04 - 05:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon May 04, 2026 00:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
123162820,6sleep01870699cyclictest22:20:260
1870899742,30cyclictest0-21swapper/221:55:262
18708996833,6cyclictest33-21ksoftirqd/221:50:012
138202680,6sleep1241ktimersoftd/121:15:251
134491670,18ptp4l6287-21seq00:26:591
18708996430,4cyclictest33-21ksoftirqd/200:15:152
194282620,4sleep00-21swapper/020:20:140
134491610,4ptp4l0-21swapper/319:35:313
18708995929,3cyclictest33-21ksoftirqd/222:20:112
134491590,4ptp4l0-21swapper/022:45:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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