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2026-04-11 - 18:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Apr 11, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1363621630,5sleep2157799cyclictest12:15:132
286721560,3sleep2157799cyclictest11:50:222
1419421420,7sleep0157599cyclictest07:35:210
271832800,6sleep10-21swapper/111:35:011
271832800,6sleep10-21swapper/111:35:001
134491700,5ptp4l0-21swapper/210:31:392
134491680,4ptp4l0-21swapper/207:25:242
134491650,4ptp4l0-21swapper/211:02:532
134491650,4ptp4l0-21swapper/211:02:532
1578996429,8cyclictest41-21ksoftirqd/310:35:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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