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2026-05-13 - 12:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed May 13, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20537997933,9cyclictest25-21ksoftirqd/100:10:001
20537997933,9cyclictest25-21ksoftirqd/100:10:001
20537997427,8cyclictest25-21ksoftirqd/119:25:261
20538997232,9cyclictest33-21ksoftirqd/222:30:202
2053799712,36cyclictest0-21swapper/122:25:201
20537996926,7cyclictest25-21ksoftirqd/119:22:211
20538996834,5cyclictest33-21ksoftirqd/220:05:012
20538996732,6cyclictest33-21ksoftirqd/223:50:222
20538996728,9cyclictest33-21ksoftirqd/222:43:122
2053899672,43cyclictest0-21swapper/220:42:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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