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2026-09-17 - 13:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Sep 17, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3237021430,5sleep31099499cyclictest19:55:163
145502770,1sleep214551-21/usr/sbin/munin23:55:172
10991997031,6cyclictest9-21ksoftirqd/019:20:130
10991996930,11cyclictest9-21ksoftirqd/000:15:120
10991996729,9cyclictest9-21ksoftirqd/023:20:010
134491650,19ptp4l0-21swapper/220:20:272
134491640,5ptp4l0-21swapper/219:10:212
134491640,4ptp4l0-21swapper/321:40:253
10991996424,10cyclictest9-21ksoftirqd/022:20:010
134491630,4ptp4l0-21swapper/220:40:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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