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2026-06-05 - 11:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Fri Jun 05, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
195774123950,4sleep4411rcuc/419:05:194
195900699380379,1cyclictest2114960-21kworker/3:122:38:023
195899999369367,1cyclictest2157992-21kworker/2:223:39:022
195899999369367,1cyclictest2157992-21kworker/2:223:39:022
195902899368366,1cyclictest0-21swapper/623:39:036
195902899368366,1cyclictest0-21swapper/623:39:026
195900699368364,3cyclictest2156836-21kworker/3:023:53:023
195900699366365,1cyclictest0-21swapper/321:19:023
195900699366364,1cyclictest0-21swapper/321:49:023
195900699366362,3cyclictest0-21swapper/322:08:023
195900699366362,3cyclictest0-21swapper/322:08:023
195900699365364,1cyclictest0-21swapper/323:49:023
195900699364363,1cyclictest0-21swapper/322:40:023
195900699364363,1cyclictest0-21swapper/322:33:033
195900699364362,1cyclictest0-21swapper/321:53:023
195900699363362,1cyclictest0-21swapper/319:15:033
195900699363362,1cyclictest0-21swapper/300:14:023
195900699362360,1cyclictest0-21swapper/323:12:023
195900699362360,1cyclictest0-21swapper/323:06:023
195900699362360,1cyclictest0-21swapper/321:41:023
195900699361360,1cyclictest0-21swapper/323:34:033
195900699361359,1cyclictest0-21swapper/323:19:023
195900699361359,1cyclictest0-21swapper/321:24:023
195900699361359,1cyclictest0-21swapper/300:26:023
195900699361359,1cyclictest0-21swapper/300:01:033
195900699360359,1cyclictest2114960-21kworker/3:122:23:023
195900699360359,1cyclictest0-21swapper/322:49:023
195900699360359,1cyclictest0-21swapper/320:30:023
195900699360358,1cyclictest0-21swapper/323:55:023
195900699360358,1cyclictest0-21swapper/323:24:023
195900699360358,1cyclictest0-21swapper/322:50:033
195900699360358,1cyclictest0-21swapper/322:19:033
195900699360358,1cyclictest0-21swapper/321:05:023
195900699360358,1cyclictest0-21swapper/320:50:023
195900699359358,1cyclictest0-21swapper/322:27:023
195900699359357,1cyclictest0-21swapper/322:58:033
195900699359357,1cyclictest0-21swapper/320:05:023
195900699358357,1cyclictest0-21swapper/300:35:033
195900699358356,2cyclictest97550irq/166-enp0s3121:32:023
195900699358355,2cyclictest2156836-21kworker/3:023:27:023
195900699357356,1cyclictest0-21swapper/319:55:023
195900699355354,1cyclictest2246091-21kworker/3:200:19:023
195900699355354,1cyclictest1983894-21kworker/3:021:14:023
195900699354353,1cyclictest2055856-21kworker/3:222:10:023
195900699354353,1cyclictest0-21swapper/320:44:023
195900699354353,1cyclictest0-21swapper/320:44:023
195900699354352,1cyclictest0-21swapper/319:49:023
195900699354352,1cyclictest0-21swapper/319:29:023
195900699353352,1cyclictest2246091-21kworker/3:200:24:023
195900699353352,1cyclictest1983894-21kworker/3:021:29:033
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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