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2026-05-11 - 04:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Mon May 11, 2026 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122015299364361,1cyclictest1216999-21kworker/3:119:12:023
122013599364363,1cyclictest0-21swapper/100:37:021
122013599363361,1cyclictest0-21swapper/123:21:021
122013599361360,1cyclictest0-21swapper/120:59:021
122013599361360,1cyclictest0-21swapper/120:37:021
122013599361359,2cyclictest1378009-21kworker/1:223:51:021
122013599361359,1cyclictest1290163-21kworker/1:022:05:021
122013599361359,1cyclictest0-21swapper/122:29:021
122016899360359,1cyclictest1504887-21kworker/5:219:12:025
122013599360359,1cyclictest0-21swapper/123:25:021
122013599360359,1cyclictest0-21swapper/122:11:021
122013599360359,1cyclictest0-21swapper/100:13:021
122017799359357,1cyclictest1438535-21kworker/6:223:39:026
122013599359358,1cyclictest1290163-21kworker/1:021:15:021
122013599359358,1cyclictest1290163-21kworker/1:021:15:021
122013599359358,1cyclictest0-21swapper/123:43:021
122013599359358,1cyclictest0-21swapper/122:01:021
122013599359358,1cyclictest0-21swapper/121:37:021
122013599359358,1cyclictest0-21swapper/100:19:021
122013599359357,1cyclictest0-21swapper/122:33:021
122013599358357,1cyclictest0-21swapper/123:49:021
122013599358357,1cyclictest0-21swapper/123:01:031
122013599358357,1cyclictest0-21swapper/122:43:021
122013599358357,1cyclictest0-21swapper/122:23:031
122013599358357,1cyclictest0-21swapper/121:21:021
122013599358357,1cyclictest0-21swapper/119:37:021
122013599358356,1cyclictest0-21swapper/122:15:021
122013599358356,1cyclictest0-21swapper/121:25:031
122013599357356,1cyclictest1378009-21kworker/1:222:35:031
122013599357356,1cyclictest0-21swapper/122:45:021
122013599357356,1cyclictest0-21swapper/121:59:021
122013599357356,1cyclictest0-21swapper/121:13:021
122013599357356,1cyclictest0-21swapper/121:09:021
122013599357355,1cyclictest0-21swapper/120:03:021
122013599357355,1cyclictest0-21swapper/100:26:031
122012799357356,1cyclictest1316196-21kworker/0:000:06:020
122012799357355,1cyclictest1316196-21kworker/0:000:37:020
122013599356355,1cyclictest1247953-21kworker/1:220:05:021
122013599356355,1cyclictest0-21swapper/119:45:021
122013599356355,1cyclictest0-21swapper/119:45:021
122013599356355,1cyclictest0-21swapper/119:19:021
122013599355354,1cyclictest1247953-21kworker/1:220:29:021
122013599355354,1cyclictest0-21swapper/120:45:021
122013599355354,1cyclictest0-21swapper/120:43:021
122013599355354,1cyclictest0-21swapper/120:17:031
122013599355353,1cyclictest1483845-21kworker/1:119:29:021
122013599355353,1cyclictest0-21swapper/123:17:021
122012799355354,1cyclictest0-21swapper/022:17:020
122013599354353,1cyclictest0-21swapper/119:51:021
122013599354352,2cyclictest0-21swapper/100:00:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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