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2026-04-19 - 09:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Apr 19, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1865999252,18cyclictest0-21swapper/019:35:010
1866899237,13cyclictest0-21swapper/220:49:122
1866399230,5cyclictest0-21swapper/100:25:011
1865999220,4cyclictest0-21swapper/022:39:000
1865999220,18cyclictest0-21swapper/023:20:000
1866899210,19cyclictest399-20systemd-journal21:10:012
1866899204,15cyclictest0-21swapper/200:30:322
1866399200,5cyclictest0-21swapper/100:19:331
1866399200,3cyclictest4099-21H222:10:211
1866399200,17cyclictest0-21swapper/100:00:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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