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2025-12-04 - 15:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Dec 04, 2025 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28032992726,1cyclictest0-21swapper/208:54:182
2802799260,15cyclictest0-21swapper/111:20:191
28032992415,0cyclictest0-21swapper/210:30:162
2803299230,5cyclictest0-21swapper/208:28:182
2803299230,18cyclictest0-21swapper/209:23:372
2802799220,18cyclictest0-21swapper/111:06:521
2802799220,18cyclictest0-21swapper/111:06:521
2802799220,18cyclictest0-21swapper/107:35:211
28032992118,2cyclictest7450-21lockfile-remove11:20:012
2803299210,3cyclictest0-21swapper/209:09:352
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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