You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-12-01 - 11:23
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Dec 01, 2025 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22173992811,2cyclictest0-21swapper/222:35:202
2217399251,23cyclictest0-21swapper/200:36:372
2216899252,22cyclictest0-21swapper/122:49:191
2217399242,4cyclictest0-21swapper/219:32:272
2217399230,22cyclictest0-21swapper/221:33:592
2216899230,5cyclictest0-21swapper/100:31:401
2217399223,18cyclictest0-21swapper/223:58:562
2217399214,16cyclictest8716-21awk23:30:182
2217399213,17cyclictest20864-21cut21:00:192
22173992118,2cyclictest21469-21sort22:55:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional