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2025-12-02 - 14:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Dec 02, 2025 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17647992423,1cyclictest16241-21kworker/0:223:40:150
1764899230,18cyclictest0-21swapper/120:25:211
1764899230,18cyclictest0-21swapper/120:25:201
1764899230,16cyclictest25230-21grep20:20:161
17647992214,4cyclictest0-21swapper/019:14:130
17649992114,3cyclictest11002-21apt00:39:592
1764999210,19cyclictest414-20systemd-journal20:25:012
17648992116,4cyclictest9959-21tr23:40:141
1764899210,19cyclictest13746-21grep21:55:171
17647992119,1cyclictest9-21ksoftirqd/023:05:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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