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2025-12-04 - 03:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Dec 03, 2025 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3073199230,19cyclictest0-21swapper/211:17:212
3072499230,18cyclictest0-21swapper/111:40:011
3073199222,17cyclictest0-21swapper/210:30:002
30731992112,6cyclictest0-21swapper/212:11:192
3072299210,19cyclictest414-20systemd-journal07:59:560
3072299210,18cyclictest0-21swapper/007:25:150
3073199202,17cyclictest16600-21cpuspeed_turbos12:25:152
30731992017,2cyclictest12169-21cut12:15:182
3073199200,17cyclictest24270-21cpuspeed_turbos07:55:142
30724992017,2cyclictest4532-21H212:26:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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