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2026-02-18 - 13:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Feb 18, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20428992914,1cyclictest0-21swapper/200:10:212
20428992424,0cyclictest14332-21mii-tool19:55:162
20428992314,5cyclictest0-21swapper/219:35:012
2042799230,18cyclictest0-21swapper/121:55:131
20428992020,0cyclictest0-21swapper/223:30:212
20428992018,1cyclictest0-21swapper/200:15:042
20428992016,3cyclictest0-21swapper/223:16:182
20428992012,4cyclictest0-21swapper/220:25:262
2042899200,19cyclictest0-21swapper/220:35:142
2042899200,19cyclictest0-21swapper/220:04:042
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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