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2026-05-04 - 08:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon May 04, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2788099245,11cyclictest0-21swapper/122:50:191
27883992321,0cyclictest0-21swapper/222:25:142
27880992314,0cyclictest0-21swapper/123:43:421
2787999233,19cyclictest0-21swapper/000:05:000
2787999230,22cyclictest0-21swapper/021:09:030
27880992213,0cyclictest21-21ksoftirqd/123:46:521
2788099220,18cyclictest0-21swapper/123:56:261
2788399212,3cyclictest0-21swapper/221:41:092
2788399212,3cyclictest0-21swapper/221:41:082
2788399210,3cyclictest0-21swapper/220:38:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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