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2026-08-28 - 14:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Aug 28, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7812992510,15cyclictest0-21swapper/121:42:181
7812992510,15cyclictest0-21swapper/121:42:181
781299241,19cyclictest21-21ksoftirqd/123:00:571
781299234,18cyclictest0-21swapper/100:18:581
781299230,20cyclictest21-21ksoftirqd/119:25:001
7808992316,6cyclictest3632-21cat20:00:010
781799225,11cyclictest0-21swapper/219:57:122
781299228,14cyclictest21-21ksoftirqd/121:55:541
781299221,1cyclictest21-21ksoftirqd/100:01:521
780899220,21cyclictest843-21systemd-network22:04:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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