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2026-06-14 - 01:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Jun 13, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2394999240,4cyclictest5039-21dpkg08:26:312
2394399240,19cyclictest3759-21cpuspeed_turbos07:30:141
2394999232,6cyclictest26279-21cut10:05:012
23949992312,6cyclictest399-20systemd-journal10:54:552
2394999231,21cyclictest0-21swapper/207:26:022
2394999224,17cyclictest0-21swapper/209:06:452
23949992214,7cyclictest3987-21H222:10:212
2394999220,3cyclictest8458-21smtp07:37:452
2394999220,2cyclictest9835-21ntp_states11:25:202
2394999220,2cyclictest8742-21chrt10:29:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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