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2026-01-31 - 06:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Jan 31, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26104992617,0cyclictest0-21swapper/021:55:140
26104992617,0cyclictest0-21swapper/021:55:130
26104992424,0cyclictest17235-21mii-tool00:35:160
26104992424,0cyclictest17235-21mii-tool00:35:150
26105992323,0cyclictest0-21swapper/100:35:161
26105992323,0cyclictest0-21swapper/100:35:161
2610699222,17cyclictest0-21swapper/222:25:352
2610499220,17cyclictest12784-21grep20:40:010
2610699210,17cyclictest0-21swapper/221:28:242
26104992116,4cyclictest0-21swapper/020:55:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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