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2026-07-26 - 14:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Jul 26, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2701399310,0cyclictest0-21swapper/121:00:151
2701799300,1cyclictest0-21swapper/221:05:132
2700899233,13cyclictest31308-21munin-run22:10:000
27013992213,9cyclictest0-21swapper/100:10:021
2701399220,4cyclictest0-21swapper/120:06:481
2701799210,3cyclictest0-21swapper/219:25:562
2701799210,20cyclictest843-21systemd-network20:26:022
2701799210,20cyclictest3991-21H222:10:212
27008992118,2cyclictest3599-21sed21:20:000
27008992118,2cyclictest31808-21cat22:10:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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