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2026-04-10 - 16:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Apr 10, 2026 12:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12776992623,2cyclictest3768-21mii-tool12:35:152
1277499250,11cyclictest0-21swapper/009:16:480
1277599230,5cyclictest0-21swapper/109:37:311
1277699220,18cyclictest0-21swapper/207:50:012
12776992114,4cyclictest0-21swapper/212:14:142
1277699210,3cyclictest0-21swapper/208:51:272
1277599212,18cyclictest0-21swapper/109:45:311
1277599210,5cyclictest0-21swapper/108:55:031
1277599210,5cyclictest0-21swapper/107:24:431
1277599210,3cyclictest0-21swapper/108:12:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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