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2026-07-20 - 09:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Jul 20, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2024993027,2cyclictest0-21swapper/120:15:221
2019993014,15cyclictest7145-21missed_timers23:05:180
202499230,18cyclictest0-21swapper/100:17:231
202499230,18cyclictest0-21swapper/100:17:231
202899220,20cyclictest0-21swapper/223:18:302
202899211,17cyclictest20233-21grep19:40:162
2024992121,0cyclictest0-21swapper/123:45:161
202499210,6cyclictest20235-21fschecks_count19:40:161
202899203,16cyclictest27140-21mailstats21:45:202
2028992018,1cyclictest28-21ksoftirqd/220:37:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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