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2026-04-14 - 07:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Apr 14, 2026 00:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24306992617,0cyclictest0-21swapper/219:55:162
24306992525,0cyclictest0-21swapper/220:35:172
24306992414,5cyclictest0-21swapper/221:01:432
24306992414,5cyclictest0-21swapper/221:01:432
24305992315,7cyclictest0-21swapper/100:30:181
24305992314,1cyclictest0-21swapper/119:35:171
2430599230,2cyclictest11094-21perf00:29:591
2430599230,16cyclictest30528-21awk21:15:121
2430699220,5cyclictest0-21swapper/221:27:052
24305992214,2cyclictest4067-21awk22:20:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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