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2026-03-30 - 14:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Mar 30, 2026 00:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2082499237,15cyclictest0-21swapper/121:15:191
2082499230,2cyclictest31352-21/usr/sbin/munin22:20:161
2082499230,17cyclictest23680-21latency_hist19:15:001
2082599226,1cyclictest0-21swapper/221:25:012
20825992212,5cyclictest0-21swapper/223:20:182
20824992214,7cyclictest0-21swapper/123:45:161
2082499220,2cyclictest5331-21expr22:30:191
2082499220,21cyclictest843-21systemd-network23:59:001
2082499220,21cyclictest30895-21cut00:15:011
2082499220,15cyclictest1407-21cat22:25:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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