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2026-03-16 - 22:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Mar 16, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2369499230,5cyclictest0-21swapper/112:04:391
2369499230,5cyclictest0-21swapper/107:27:121
23695992117,3cyclictest0-21swapper/208:40:172
2369499212,18cyclictest32139-21munin-run07:25:011
2369499210,3cyclictest0-21swapper/110:14:031
2369499209,1cyclictest0-21swapper/111:45:001
2369499202,17cyclictest0-21swapper/109:54:571
2369499200,17cyclictest0-21swapper/111:47:011
2369399206,13cyclictest0-21swapper/012:03:170
2369399204,15cyclictest0-21swapper/007:45:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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