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2026-05-16 - 17:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat May 16, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25136992928,0cyclictest0-21swapper/012:05:160
25148992827,0cyclictest0-21swapper/212:30:172
2514899240,23cyclictest0-21swapper/209:28:072
2514899230,5cyclictest0-21swapper/209:50:202
2514299230,18cyclictest0-21swapper/110:25:121
2514899220,21cyclictest843-21systemd-network07:10:112
2514899210,3cyclictest0-21swapper/208:30:562
2514299214,16cyclictest3058-21rs:main1
25136992117,3cyclictest0-21swapper/009:42:290
25136992117,3cyclictest0-21swapper/009:42:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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