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2026-03-20 - 03:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Mar 20, 2026 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26658992514,6cyclictest0-21swapper/022:39:010
26658992112,5cyclictest0-21swapper/023:00:170
26660992016,3cyclictest0-21swapper/221:30:142
2665899203,11cyclictest31783-21python322:10:000
26658992015,2cyclictest13243-21cut19:40:160
26658992012,4cyclictest0-21swapper/021:13:240
2665999190,3cyclictest16766-21snapd20:17:491
2665899191,17cyclictest27845-21nfsd422:00:170
2665899190,4cyclictest0-21swapper/021:25:130
2665899190,18cyclictest0-21swapper/023:15:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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