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2026-03-31 - 15:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Mar 31, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
811992018,1cyclictest0-21swapper/210:35:002
811992016,3cyclictest0-21swapper/210:27:182
81199200,17cyclictest0-21swapper/208:04:312
79799204,15cyclictest0-21swapper/012:28:420
79799200,6cyclictest843-21systemd-network08:29:250
81199192,2cyclictest6136-21nfsd411:05:172
81199192,2cyclictest6136-21nfsd411:05:172
81199192,16cyclictest20898-21seq09:38:202
811991917,1cyclictest0-21swapper/209:59:482
811991916,2cyclictest993-21dbus-daemon12:10:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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