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2026-04-08 - 13:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Apr 08, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2172499230,5cyclictest0-21swapper/123:19:471
2171999236,16cyclictest0-21swapper/019:11:120
21719992214,3cyclictest0-21swapper/000:27:370
2171999220,6cyclictest0-21swapper/021:47:190
2171999210,4cyclictest0-21swapper/022:55:000
2171999210,1cyclictest0-21swapper/023:57:020
2172899203,11cyclictest0-21swapper/222:31:342
2172499202,11cyclictest13866-21python300:40:011
2172499202,11cyclictest13866-21python300:40:001
2172499200,19cyclictest2488-21/usr/sbin/munin23:20:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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