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2026-03-02 - 09:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Mar 02, 2026 00:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
89999220,18cyclictest0-21swapper/021:17:180
89999210,18cyclictest0-21swapper/000:34:280
907992016,3cyclictest0-21swapper/222:27:112
907992016,3cyclictest0-21swapper/220:52:462
89999204,15cyclictest0-21swapper/021:26:150
90799190,18cyclictest1949-21grep19:10:152
90799190,17cyclictest0-21swapper/221:13:202
90099193,1cyclictest0-21swapper/120:55:221
90099192,16cyclictest25501-21cron23:39:001
90099190,4cyclictest399-20systemd-journal21:33:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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