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2026-02-14 - 12:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Feb 14, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16162993229,2cyclictest0-21swapper/100:20:151
16162992827,0cyclictest0-21swapper/123:55:171
16162992726,0cyclictest0-21swapper/123:45:471
1616699234,13cyclictest0-21swapper/221:00:142
1616699234,13cyclictest0-21swapper/221:00:132
16162992314,5cyclictest0-21swapper/121:10:191
1616299220,21cyclictest843-21systemd-network21:22:031
16162992112,0cyclictest0-21swapper/122:35:141
1615699210,20cyclictest843-21systemd-network23:39:580
1616299204,2cyclictest21955-21nfsd420:15:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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