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2026-06-08 - 00:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Jun 07, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14891992422,1cyclictest28-21ksoftirqd/210:40:152
1487999220,4cyclictest0-21swapper/012:15:010
1487999212,1cyclictest0-21swapper/010:42:150
1489199200,17cyclictest0-21swapper/209:50:142
1489199200,17cyclictest0-21swapper/209:50:142
1488499204,15cyclictest21-21ksoftirqd/108:35:431
14884992017,2cyclictest6225-21php7.011:39:001
14884992012,3cyclictest0-21swapper/107:35:321
1488499200,4cyclictest0-21swapper/110:47:531
1487999201,18cyclictest22385-21cpuspeed_turbos11:10:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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