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2026-09-06 - 16:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Sep 06, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2309299270,4cyclictest0-21swapper/112:13:381
2309299270,22cyclictest0-21swapper/108:20:071
2309299240,23cyclictest0-21swapper/112:24:501
2309399230,20cyclictest0-21swapper/211:16:592
2309299232,1cyclictest0-21swapper/108:30:201
23092992312,6cyclictest5741-21sort09:30:141
2309299230,2cyclictest14855-21fschecks_count12:35:171
2309299230,2cyclictest11916-21fschecks_count09:40:141
2309299230,22cyclictest0-21swapper/108:45:131
2309199230,5cyclictest0-21swapper/010:17:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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