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2026-03-06 - 10:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Mar 06, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1744699270,1cyclictest0-21swapper/021:20:120
17453992017,1cyclictest0-21swapper/220:51:492
17453992017,1cyclictest0-21swapper/220:51:482
17448992017,2cyclictest3414-21master00:13:021
1744899200,19cyclictest843-21systemd-network22:13:411
17453991914,3cyclictest0-21swapper/222:38:572
1745399190,18cyclictest0-21swapper/219:28:462
1744899196,7cyclictest0-21swapper/100:08:241
17448991917,1cyclictest0-21swapper/100:20:161
17446991916,1cyclictest0-21swapper/019:11:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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