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2026-03-13 - 12:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Mar 13, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30194992925,3cyclictest0-21swapper/021:20:150
30195992818,10cyclictest0-21swapper/120:30:501
3019499270,18cyclictest0-21swapper/021:10:010
30195992415,0cyclictest0-21swapper/123:15:161
30195992415,0cyclictest0-21swapper/123:15:151
30195992414,5cyclictest0-21swapper/122:10:011
3019599240,24cyclictest0-21swapper/120:05:161
3019699230,22cyclictest870-21systemd-logind22:56:512
30195992114,6cyclictest0-21swapper/122:15:161
3019499210,18cyclictest0-21swapper/020:12:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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