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2026-06-29 - 04:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Jun 29, 2026 00:46:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1186999250,20cyclictest15614-21fschecks_time21:10:150
1187999247,15cyclictest0-21swapper/223:50:162
11874992321,1cyclictest1100-21snmpd23:12:161
1187499230,5cyclictest0-21swapper/122:47:111
11874992222,0cyclictest0-21swapper/100:28:311
1187499220,18cyclictest0-21swapper/123:09:141
1186999220,21cyclictest843-21systemd-network00:13:030
1186999220,18cyclictest0-21swapper/019:32:400
11879992117,3cyclictest19953-21php7.000:09:012
1186999211,2cyclictest1114-21lldpd23:34:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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