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2026-01-24 - 05:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Jan 24, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9991992118,2cyclictest17637-21sessionclean00:09:001
9995992016,3cyclictest0-21swapper/223:03:532
9995992016,3cyclictest0-21swapper/221:07:072
9995992016,1cyclictest0-21swapper/223:15:202
999199202,17cyclictest0-21swapper/100:13:431
999599191,16cyclictest5114-21apache_volume20:55:132
999599190,18cyclictest0-21swapper/221:49:042
999199192,16cyclictest12397-21cstates22:05:121
9991991915,3cyclictest0-21swapper/123:50:001
9991991915,3cyclictest0-21swapper/119:10:541
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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