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2026-02-04 - 21:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Feb 04, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3076399250,4cyclictest0-21swapper/008:10:010
3076999230,5cyclictest0-21swapper/111:30:001
3077599222,13cyclictest1911-21python309:09:592
30775992213,5cyclictest0-21swapper/208:30:132
3077599220,21cyclictest843-21systemd-network10:36:302
3077599220,21cyclictest843-21systemd-network09:18:142
3076399220,18cyclictest0-21swapper/007:59:400
3077599217,13cyclictest0-21swapper/210:45:222
30775992117,3cyclictest16504-21php7.008:39:012
3077599210,18cyclictest0-21swapper/208:05:512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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