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2025-11-30 - 23:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Nov 30, 2025 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5343992516,9cyclictest0-21swapper/210:15:562
5343992516,9cyclictest0-21swapper/210:15:562
5338992415,5cyclictest29939-21cpuspeed_turbos08:50:141
533799230,5cyclictest0-21swapper/011:45:010
5337992214,4cyclictest0-21swapper/007:44:180
5338992120,1cyclictest21-21ksoftirqd/111:14:251
5338992112,5cyclictest0-21swapper/111:15:201
533899210,4cyclictest0-21swapper/107:27:371
5343992017,2cyclictest4523-21H212:26:332
5343992015,4cyclictest7023-21cstates09:05:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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