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2025-12-17 - 22:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Dec 17, 2025 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
250399230,5cyclictest0-21swapper/009:11:340
250399230,18cyclictest15896-21sed12:20:000
250599210,20cyclictest843-21systemd-network11:13:012
2505991916,2cyclictest3991-21H222:10:212
2505991916,2cyclictest0-21swapper/207:15:122
2505991916,2cyclictest0-21swapper/207:15:122
250599190,2cyclictest3976-21H222:10:212
250599190,18cyclictest0-21swapper/208:34:122
250599190,16cyclictest3979-21H222:10:212
250499192,16cyclictest0-21swapper/108:35:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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