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2026-05-02 - 06:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat May 02, 2026 00:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5179993432,1cyclictest0-21swapper/122:00:121
5179993331,2cyclictest0-21swapper/121:23:561
5179992525,0cyclictest0-21swapper/123:45:181
5179992422,1cyclictest3157-21mii-tool21:00:151
5179992313,9cyclictest870-21systemd-logind00:38:511
517899236,2cyclictest23107-21latency_hist00:29:590
5180992219,2cyclictest29972-21sed20:50:152
5178992113,4cyclictest0-21swapper/021:25:010
5180992018,1cyclictest0-21swapper/222:35:152
517899205,1cyclictest9-21ksoftirqd/019:54:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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