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2025-12-16 - 11:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Dec 16, 2025 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2344499263,5cyclictest16686-21cut19:55:000
2344699220,21cyclictest843-21systemd-network20:31:442
23445992117,3cyclictest0-21swapper/100:02:571
23444992114,6cyclictest0-21swapper/022:05:010
23444992114,6cyclictest0-21swapper/022:05:000
23446992014,3cyclictest0-21swapper/220:38:442
2344599204,14cyclictest0-21swapper/123:07:531
2344499203,11cyclictest30660-21logrotate00:09:280
2344699192,3cyclictest0-21swapper/200:16:442
2344699192,13cyclictest16668-21/usr/sbin/munin19:55:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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