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2026-09-03 - 16:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Sep 03, 2026 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1802899294,18cyclictest18587-21perf09:05:000
1803099247,2cyclictest3983-21H222:10:212
1802999220,18cyclictest0-21swapper/108:00:211
1803099214,16cyclictest3987-21H222:10:212
1803099214,11cyclictest0-21swapper/209:13:322
1803099214,11cyclictest0-21swapper/209:13:322
1803099210,20cyclictest0-21swapper/207:43:162
18028992115,5cyclictest0-21swapper/008:40:000
18030992017,2cyclictest3987-21H222:10:212
18030992014,5cyclictest0-21swapper/207:38:372
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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