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2026-08-01 - 11:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Aug 01, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3819992321,1cyclictest0-21swapper/220:15:182
381999230,5cyclictest0-21swapper/200:01:042
381999230,18cyclictest0-21swapper/222:20:162
381799230,5cyclictest0-21swapper/022:54:140
381799230,5cyclictest0-21swapper/022:27:220
3817992214,4cyclictest0-21swapper/022:30:440
381999210,19cyclictest25292-21grep21:40:152
381899214,16cyclictest0-21swapper/123:26:421
381999200,19cyclictest0-21swapper/220:06:022
381899202,1cyclictest0-21swapper/119:50:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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