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2026-04-01 - 07:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Apr 01, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1566299260,15cyclictest0-21swapper/123:35:131
1566299232,1cyclictest0-21swapper/119:20:491
15662992315,7cyclictest28504-21python320:30:001
15662992314,1cyclictest0-21swapper/122:25:181
1566299230,21cyclictest0-21swapper/123:48:551
1566699220,18cyclictest0-21swapper/220:42:282
1566299222,1cyclictest0-21swapper/122:17:491
1566299222,19cyclictest0-21swapper/121:13:421
15662992214,2cyclictest8486-21cat21:45:141
15662992214,2cyclictest14909-21ntp_states21:55:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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