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2025-12-05 - 19:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Dec 05, 2025 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7885992827,1cyclictest0-21swapper/112:20:151
788599248,2cyclictest1086-21snmpd11:55:261
788599248,2cyclictest1086-21snmpd11:55:261
789099230,22cyclictest0-21swapper/207:55:242
788599230,18cyclictest3441-21gsd-color08:42:251
7881992319,3cyclictest17681-21plymouth07:40:010
789099190,17cyclictest0-21swapper/208:57:302
788599192,2cyclictest1057-21smartctl08:25:191
788599192,2cyclictest1057-21smartctl08:25:181
788599192,16cyclictest27028-21smtpd08:08:581
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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