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2026-07-02 - 06:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Jul 02, 2026 00:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4439992523,0cyclictest0-21swapper/122:05:101
4441992417,6cyclictest29384-21sh00:39:002
4441992316,6cyclictest7769-21chrt21:09:332
444199231,3cyclictest1100-21snmpd23:25:152
444199230,3cyclictest0-21swapper/219:57:532
444199230,22cyclictest17800-21ntp_states23:20:202
444199230,16cyclictest28301-21apache_processe20:50:112
444199222,19cyclictest21689-21cpuspeed_turbos00:25:142
4441992217,4cyclictest27003-21fschecks_time22:40:142
4441992216,5cyclictest22403-21cpuspeed_turbos21:35:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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