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2026-04-06 - 02:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Apr 05, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1089199240,23cyclictest26208-21iwlist09:30:150
10891992314,8cyclictest0-21swapper/007:35:010
10891992314,4cyclictest0-21swapper/010:00:000
1089199222,4cyclictest7651-21perf11:50:000
10891992213,5cyclictest0-21swapper/012:34:270
1089199220,18cyclictest0-21swapper/008:24:390
10893992117,3cyclictest0-21swapper/211:40:552
10893992117,3cyclictest0-21swapper/208:51:002
1089199210,17cyclictest0-21swapper/007:45:130
10892992018,1cyclictest15293-21ntp_kernel_err07:15:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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