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2025-12-21 - 08:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Dec 21, 2025 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32164992213,4cyclictest0-21swapper/223:25:122
3216499214,11cyclictest27743-21munin-run20:55:012
3216299212,18cyclictest23452-21awk00:35:000
3216299212,18cyclictest23452-21awk00:34:590
32162992119,1cyclictest23460-21kworker/0:222:50:440
32164992017,2cyclictest2069-21systemd-udevd22:58:522
32164992016,3cyclictest0-21swapper/219:50:082
3216299200,17cyclictest0-21swapper/000:10:190
3216499193,15cyclictest28-21ksoftirqd/222:08:302
3216499193,15cyclictest0-21swapper/221:12:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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