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2026-05-07 - 13:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu May 07, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6039992321,1cyclictest0-21swapper/121:50:201
603899237,15cyclictest0-21swapper/019:47:030
603899230,23cyclictest0-21swapper/021:55:150
604099220,4cyclictest0-21swapper/200:09:572
6040992117,3cyclictest0-21swapper/222:20:322
604099204,15cyclictest0-21swapper/220:20:432
604099201,17cyclictest3058-21rs:main2
604099193,1cyclictest10411-21sessionclean22:08:592
604099192,1cyclictest3987-21H222:10:212
604099192,15cyclictest3987-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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