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2025-10-21 - 05:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Oct 21, 2025 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
358299212,4cyclictest20927-21perf22:35:010
358299201,18cyclictest0-21swapper/021:05:240
358299200,15cyclictest26536-21cron22:45:000
358499192,16cyclictest14950-21cut23:20:172
3584991917,1cyclictest0-21swapper/220:18:492
3584991916,2cyclictest2939-21cpu23:00:162
3584991915,3cyclictest0-21swapper/220:10:172
358399194,1cyclictest0-21swapper/119:50:531
358399192,16cyclictest29337-21nfsd421:50:181
3583991915,2cyclictest14664-21nfsd420:25:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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