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2026-03-24 - 07:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Mar 24, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
119699232,18cyclictest1816-21apache_accesses21:05:111
119699230,22cyclictest0-21swapper/123:52:311
119699230,22cyclictest0-21swapper/123:25:141
120099226,15cyclictest0-21swapper/223:35:162
1200992212,3cyclictest0-21swapper/220:00:152
119699220,21cyclictest843-21systemd-network19:12:251
119699220,18cyclictest0-21swapper/122:18:571
119599223,11cyclictest14524-21munin-run23:20:000
119699212,16cyclictest0-21swapper/120:37:001
1196992114,3cyclictest0-21swapper/122:20:481
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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