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2025-11-15 - 20:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Nov 15, 2025 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1395499220,18cyclictest0-21swapper/208:49:452
13949992214,4cyclictest0-21swapper/008:49:260
1394999220,6cyclictest0-21swapper/008:50:550
1395099212,3cyclictest0-21swapper/108:45:041
1395499204,15cyclictest0-21swapper/210:50:462
13950992017,2cyclictest4526-21H212:26:331
1395499192,9cyclictest0-21swapper/211:44:172
1395499192,16cyclictest29770-21chrt11:20:382
1395499192,16cyclictest0-21swapper/209:26:132
13954991916,2cyclictest8383-21processes10:45:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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