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2025-11-18 - 22:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Nov 18, 2025 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1763899260,5cyclictest0-21swapper/209:30:212
17636992423,1cyclictest1042-21mii-tool10:25:171
17638992322,1cyclictest28-21ksoftirqd/209:09:582
17638992319,3cyclictest28-21ksoftirqd/207:12:492
17638992316,3cyclictest0-21swapper/210:09:102
1763899230,22cyclictest823-21systemd-network08:16:542
1763899230,18cyclictest26306-21updatedb.mlocat07:25:002
1763899230,18cyclictest0-21swapper/212:13:082
1763599230,4cyclictest0-21swapper/010:00:200
1763899222,19cyclictest0-21swapper/211:23:352
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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