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2026-06-17 - 01:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Jun 16, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1057199225,16cyclictest870-21systemd-logind11:11:521
10570992214,4cyclictest0-21swapper/007:15:130
10570992214,4cyclictest0-21swapper/007:15:120
1057099220,5cyclictest0-21swapper/008:20:400
10571992017,2cyclictest29588-21http_loadtime09:35:161
1057299192,16cyclictest17450-21cpuspeed_turbos07:20:152
10572991916,2cyclictest27602-21processes09:30:192
1057299191,3cyclictest3065-21turbostat.cron08:50:022
10571991917,1cyclictest0-21swapper/111:32:151
10570991917,1cyclictest0-21swapper/010:13:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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