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2026-07-14 - 08:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Jul 14, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1682599264,21cyclictest0-21swapper/119:33:101
16829992514,10cyclictest0-21swapper/220:55:162
16829992424,0cyclictest0-21swapper/222:33:392
1682599241,22cyclictest0-21swapper/100:13:591
1682599240,1cyclictest0-21swapper/122:40:001
16829992322,1cyclictest0-21swapper/222:41:002
16829992313,5cyclictest0-21swapper/222:00:132
1682999230,5cyclictest0-21swapper/223:00:152
1682999230,0cyclictest0-21swapper/222:05:122
16825992314,7cyclictest20992-21pzem_energy20:10:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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