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2025-11-08 - 18:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Nov 08, 2025 12:45:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29886992919,0cyclictest0-21swapper/211:14:142
29886992718,9cyclictest0-21swapper/209:05:162
2988499241,18cyclictest10898-21cat10:25:010
2988699230,5cyclictest0-21swapper/209:32:562
2988599230,18cyclictest0-21swapper/107:23:201
2988699214,11cyclictest0-21swapper/211:05:592
2988699210,20cyclictest0-21swapper/212:25:502
2988599210,3cyclictest0-21swapper/108:14:221
2988499215,9cyclictest0-21swapper/009:05:460
29884992117,3cyclictest922-21rs:main0
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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