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2026-02-07 - 10:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Feb 07, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14241992322,1cyclictest0-21swapper/000:20:170
14242992220,1cyclictest28179-21mii-tool23:25:161
1424299220,21cyclictest843-21systemd-network22:41:041
1424199210,5cyclictest0-21swapper/022:11:040
1424399202,17cyclictest0-21swapper/200:25:002
14243992018,1cyclictest0-21swapper/223:12:412
14242992017,2cyclictest6447-21grep21:45:131
14242992012,4cyclictest0-21swapper/123:36:501
14241992013,3cyclictest111rcu_preempt19:30:190
1424199200,2cyclictest0-21swapper/019:51:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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