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2026-05-03 - 06:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun May 03, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3210099230,18cyclictest0-21swapper/200:25:182
3210099212,13cyclictest0-21swapper/219:42:522
3208999210,17cyclictest0-21swapper/021:20:010
32100992017,2cyclictest10078-21cron22:20:002
32100992015,3cyclictest0-21swapper/222:35:192
32100992015,3cyclictest0-21swapper/222:35:182
32095992014,3cyclictest0-21swapper/100:05:191
3208999204,15cyclictest21357-21grep23:35:150
3210099194,1cyclictest0-21swapper/223:20:172
3210099194,1cyclictest0-21swapper/223:03:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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