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2026-09-19 - 23:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Sep 19, 2026 12:46:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1879999230,5cyclictest0-21swapper/211:07:292
18798992314,3cyclictest4035-21H222:10:211
1879899230,5cyclictest0-21swapper/112:29:061
18799992222,0cyclictest0-21swapper/210:52:492
1879999220,21cyclictest870-21systemd-logind10:26:522
1879899223,16cyclictest3979-21H222:10:211
18798992214,7cyclictest3991-21H222:10:211
18798992214,2cyclictest14526-21grep10:50:161
18798992214,2cyclictest13938-21nfsd411:45:181
1879899220,21cyclictest1079-21cups-browsed12:35:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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