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2026-04-29 - 04:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Apr 29, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
136199239,13cyclictest0-21swapper/121:23:581
136199230,5cyclictest0-21swapper/122:41:101
136799217,13cyclictest0-21swapper/219:23:432
136199213,17cyclictest0-21swapper/121:18:141
136199210,3cyclictest0-21swapper/123:27:401
1357992115,3cyclictest0-21swapper/023:48:500
135799210,3cyclictest0-21swapper/021:47:430
135799210,20cyclictest0-21swapper/023:57:350
136199205,0cyclictest0-21swapper/123:35:191
136199201,13cyclictest0-21swapper/122:49:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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