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2026-03-03 - 09:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Mar 03, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
456899221,15cyclictest0-21swapper/020:16:420
456899212,16cyclictest0-21swapper/023:24:220
4568992118,2cyclictest29377-21awk20:50:160
4575992017,2cyclictest8013-21ntp_kernel_pll_00:00:182
4569992019,0cyclictest0-21swapper/100:18:501
456899202,17cyclictest0-21swapper/020:37:560
4575991916,1cyclictest0-21swapper/219:23:562
4575991915,3cyclictest0-21swapper/221:32:122
4575991915,3cyclictest0-21swapper/200:23:352
4575991912,5cyclictest0-21swapper/220:40:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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