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2026-02-10 - 10:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Feb 10, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1180299221,14cyclictest0-21swapper/119:49:451
1180199220,18cyclictest0-21swapper/020:00:550
11803992117,3cyclictest0-21swapper/220:24:362
11803992114,3cyclictest0-21swapper/219:33:262
11801992118,2cyclictest2069-21systemd-udevd22:44:510
11803992017,2cyclictest23369-21perf23:19:592
11803992017,1cyclictest0-21swapper/200:12:532
1180299200,17cyclictest0-21swapper/120:39:481
11801992018,1cyclictest0-21swapper/000:35:140
1180399192,16cyclictest455-21plymouthd22:25:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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