You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-07 - 12:05
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Aug 07, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24623992726,0cyclictest0-21swapper/122:25:161
24624992514,10cyclictest4526-21fschecks_count23:15:172
24624992414,10cyclictest0-21swapper/219:20:172
2462499230,18cyclictest0-21swapper/221:00:152
2462399230,5cyclictest0-21swapper/121:25:411
2462399230,18cyclictest0-21swapper/121:00:171
2462399210,3cyclictest0-21swapper/122:33:311
24624992017,2cyclictest5582-21ntp_kernel_err21:25:192
24624992017,2cyclictest3976-21H222:10:212
2462499201,18cyclictest13638-21ls21:40:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional