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2025-11-26 - 00:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Nov 25, 2025 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24832992624,1cyclictest17073-21kworker/0:209:59:070
2483399230,22cyclictest0-21swapper/107:38:581
24832992313,5cyclictest13182-21latency_hist09:40:020
2483499220,4cyclictest0-21swapper/210:20:372
2483499220,21cyclictest4526-21H212:26:332
24833992212,5cyclictest0-21swapper/110:53:521
2483299210,1cyclictest0-21swapper/007:52:020
2483299200,19cyclictest0-21swapper/008:30:140
2483499194,1cyclictest0-21swapper/208:06:392
2483499193,15cyclictest28-21ksoftirqd/207:43:102
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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