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2026-05-05 - 21:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue May 05, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2502992217,4cyclictest0-21swapper/107:30:171
250299220,1cyclictest0-21swapper/108:00:151
250199220,4cyclictest0-21swapper/009:55:500
2503992113,4cyclictest0-21swapper/210:03:462
250299212,16cyclictest0-21swapper/108:22:141
250199210,3cyclictest0-21swapper/008:23:400
2503992018,1cyclictest271rcuc/210:12:262
250199203,9cyclictest30707-21/usr/sbin/munin11:05:000
250399191,17cyclictest28-21ksoftirqd/210:48:222
250399190,4cyclictest399-20systemd-journal07:28:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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