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2026-01-19 - 19:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Mon Jan 19, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
78302840,2sleep60-21swapper/611:50:266
78132800,0sleep40-21swapper/411:14:094
312602800,0sleep70-21swapper/709:37:477
152562790,0sleep30-21swapper/312:37:103
23212740,1sleep560-21ksoftirqd/511:31:255
260072720,1sleep10-21swapper/110:17:401
261672710,0sleep70-21swapper/709:41:327
206852710,0sleep5591ktimersoftd/512:01:305
103412710,0sleep50-21swapper/511:46:165
35052700,0sleep40-21swapper/410:10:064
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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