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2026-01-14 - 12:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Wed Jan 14, 2026 00:45:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1590421460,3sleep71918999cyclictest00:30:297
167121260,4sleep61918599cyclictest21:35:466
97621250,4sleep31916599cyclictest23:09:453
1306821250,3sleep01914899cyclictest23:07:420
1217421240,0sleep50-21swapper/522:47:365
1649021230,0sleep00-21swapper/000:29:170
2778121220,1sleep427782-21sshd23:50:514
3232121180,1sleep732317-21bash23:53:337
366321110,3sleep21915999cyclictest23:17:222
219982940,0sleep10-21swapper/121:55:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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