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2026-01-29 - 07:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Thu Jan 29, 2026 00:45:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1914621530,1sleep02009399cyclictest21:23:290
1728721390,0sleep00-21swapper/021:13:050
2877821010,0sleep00-21swapper/023:51:340
240962930,0sleep30-21swapper/321:35:273
300832910,1sleep30-21swapper/322:09:423
226062890,4sleep22010599cyclictest22:43:152
220232870,1sleep3401rcuc/300:25:193
220232870,1sleep3401rcuc/300:25:193
107262860,1sleep40-21swapper/423:37:274
52962850,1sleep05295-21systemd-cgroups22:58:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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