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2026-02-08 - 21:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Sun Feb 08, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1167321190,1sleep60-21swapper/610:34:466
99972820,4sleep41678999cyclictest10:06:074
311522760,0sleep20-21swapper/211:33:572
311522760,0sleep20-21swapper/211:33:562
219262760,1sleep51012-21runrttasks11:37:125
253862750,0sleep60-21swapper/612:01:106
253072750,1sleep1231ktimersoftd/110:13:091
59972740,0sleep20-21swapper/210:29:132
60262730,0sleep00-21swapper/010:00:490
132622730,0sleep30-21swapper/310:01:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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