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2026-03-21 - 12:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Sat Mar 21, 2026 00:45:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3211421220,0sleep50-21swapper/523:01:135
248722860,1sleep024853-21sshd22:48:340
7772850,0sleep50-21swapper/500:11:195
7772850,0sleep50-21swapper/500:11:195
118962850,1sleep4491rcuc/423:14:114
60882840,1sleep20-21swapper/221:50:012
34772840,1sleep07-21ksoftirqd/000:29:010
46402820,0sleep70-21swapper/723:24:247
321942820,0sleep30-21swapper/322:43:403
302312820,2sleep5679-21dbus-daemon21:42:275
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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