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2026-01-18 - 06:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Sun Jan 18, 2026 00:45:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
833421610,5sleep43140999cyclictest21:28:094
1341321260,0sleep30-21swapper/323:36:143
49702910,1sleep34962-21sshd22:25:383
218412880,0sleep70-21swapper/700:06:577
31702860,1sleep2311rcuc/200:18:532
30482850,0sleep33042-21sshd21:42:573
30482850,0sleep33042-21sshd21:42:573
211052850,0sleep20-21swapper/223:35:182
181372840,1sleep20-21swapper/222:16:072
288782830,1sleep10-21swapper/123:39:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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