You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-18 - 19:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Wed Feb 18, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19232880,0sleep30-21swapper/311:11:443
19232880,0sleep30-21swapper/311:11:443
209682750,3sleep124-21ksoftirqd/112:25:151
177072750,1sleep4501ktimersoftd/410:40:594
209152740,1sleep60-21swapper/609:59:186
199522740,0sleep10-21swapper/110:41:201
120962740,0sleep10-21swapper/111:22:401
178762700,1sleep451-21ksoftirqd/412:39:044
178762700,1sleep451-21ksoftirqd/412:39:044
249932690,0sleep00-21swapper/009:22:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional