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2026-01-16 - 16:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Fri Jan 16, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
180621180,0sleep60-21swapper/611:51:556
71902800,0sleep40-21swapper/409:51:244
42862800,0sleep00-21swapper/012:37:180
164182800,6sleep40-21swapper/408:40:004
82062740,0sleep00-21swapper/011:57:180
196502740,0sleep00-21swapper/011:40:510
108312740,0sleep10-21swapper/111:16:561
286372720,0sleep7761rcuc/711:42:117
17312700,3sleep5478699cyclictest10:48:485
289422690,3sleep6479099cyclictest12:09:186
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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