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2026-01-20 - 15:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Tue Jan 20, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
131182920,0sleep70-21swapper/712:32:507
82442900,0sleep60-21swapper/611:46:176
173072900,0sleep00-21swapper/011:34:000
150362850,1sleep615031-21sshd11:10:426
150362850,1sleep615031-21sshd11:10:426
156882770,1sleep10-21swapper/111:47:231
189492760,2sleep50-21swapper/512:15:165
13442750,0sleep2311rcuc/211:27:062
245722730,1sleep669-21ksoftirqd/611:57:466
205562730,0sleep50-21swapper/509:59:175
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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