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2026-01-23 - 04:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Fri Jan 23, 2026 00:45:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2129021450,3sleep02309099cyclictest23:32:510
562221230,1sleep7761rcuc/721:29:477
2095621190,0sleep10-21swapper/121:10:091
1129121110,1sleep211290-21sshd22:51:332
825521100,0sleep20-21swapper/200:30:322
987121080,2sleep52312399cyclictest23:52:445
987121080,2sleep52312399cyclictest23:52:445
2440021040,0sleep30-21swapper/321:16:043
211932920,0sleep50-21swapper/521:40:355
5642890,1sleep40-21swapper/423:52:194
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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