You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-20 - 01:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Tue Jan 20, 2026 00:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
605221230,0sleep50-21swapper/500:39:495
2610621210,0sleep30-21swapper/321:30:473
168321170,1sleep07-21ksoftirqd/023:35:150
3133621150,0sleep20-21swapper/200:07:552
252521150,0sleep30-21swapper/322:08:383
915321120,1sleep07-21ksoftirqd/022:46:260
699021100,0sleep30-21swapper/322:58:553
2698621100,19sleep280250irq/25-eno1-rx-22:39:392
2425121070,1sleep60-21swapper/623:31:046
172582910,1sleep217210-21sshd00:36:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional