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2026-02-25 - 19:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Wed Feb 25, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73892860,0sleep00-21swapper/009:22:430
53572840,1sleep50-21swapper/512:10:055
271982840,1sleep20-21swapper/210:32:332
227042790,0sleep50-21swapper/510:22:185
250082770,3sleep22363899cyclictest07:10:172
86252760,1sleep60-21swapper/610:44:156
156072760,1sleep3401rcuc/310:50:053
136942760,1sleep61-21systemd09:52:146
129612750,0sleep30-21swapper/312:20:373
322722740,5sleep42365099cyclictest11:16:194
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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