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2026-01-12 - 17:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Mon Jan 12, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1029321420,4sleep2560799cyclictest11:17:532
111472760,1sleep61012-21runrttasks11:25:496
21792740,0sleep30-21swapper/309:34:153
201742710,0sleep70-21swapper/712:15:597
39392700,1sleep33942-21switchtime08:10:183
226552700,0sleep70-21swapper/710:49:287
190692680,0sleep20-21swapper/212:23:562
52582670,0sleep00-21swapper/009:11:040
183512670,0sleep60-21swapper/612:15:266
528125949,6sleep10-21swapper/107:08:491
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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