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2026-01-16 - 02:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Fri Jan 16, 2026 00:45:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2759921210,1sleep227598-21sshd23:44:302
2440221180,5sleep22319199cyclictest22:57:012
37812960,1sleep60-21swapper/622:21:556
190082920,0sleep30-21swapper/321:41:203
232452900,2sleep60-21swapper/623:01:156
252602890,1sleep50-21swapper/521:14:375
252602890,1sleep50-21swapper/521:14:375
224562880,0sleep233-21ksoftirqd/200:25:502
126532880,0sleep40-21swapper/423:56:424
98172850,4sleep42320199cyclictest23:50:494
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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