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2026-01-30 - 08:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Fri Jan 30, 2026 00:45:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3193121200,1sleep3401rcuc/321:27:183
2514021200,0sleep30-21swapper/322:23:203
176521080,0sleep30-21swapper/300:35:533
139792870,0sleep10-21swapper/123:05:501
191872850,1sleep419133-21sshd21:13:254
191872850,1sleep419133-21sshd21:13:254
183902850,0sleep70-21swapper/723:28:257
255372830,1sleep40-21swapper/423:36:074
140552830,1sleep014048-21sshd21:14:410
140552830,1sleep014048-21sshd21:14:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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