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2026-01-17 - 16:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Sat Jan 17, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2569521070,0sleep60-21swapper/609:53:006
82572980,1sleep1221rcuc/111:34:561
24442810,1sleep42442-21sshd10:35:054
230352800,0sleep10-21swapper/109:48:061
230352800,0sleep10-21swapper/109:48:061
122592790,1sleep40-21swapper/410:54:364
209022760,0sleep60-21swapper/612:31:196
83502750,1sleep2311rcuc/211:44:032
158862710,0sleep30-21swapper/309:20:033
121832710,0sleep50-21swapper/510:00:135
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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