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2026-05-21 - 10:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Thu May 21, 2026 00:45:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
420021330,0sleep14199-21sshd00:28:591
420021330,0sleep14199-21sshd00:28:581
2776221150,0sleep40-21swapper/422:07:074
1512321120,0sleep2321ktimersoftd/221:45:572
316042900,0sleep2311rcuc/200:33:492
316042900,0sleep2311rcuc/200:33:482
288472890,1sleep7681-21dbus-daemon23:35:437
57192880,0sleep10-21swapper/121:36:591
111292880,0sleep70-21swapper/721:13:337
213972870,1sleep521386-21sshd22:52:445
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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