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2026-01-26 - 06:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Mon Jan 26, 2026 00:45:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
341921470,0sleep70-21swapper/723:25:217
3038721400,0sleep60-21swapper/600:20:586
1298221370,1sleep712985-21bash00:37:497
1298221370,1sleep712985-21bash00:37:497
254621140,0sleep50-21swapper/523:25:185
216682920,1sleep721618-21sshd00:10:167
316592870,0sleep10-21swapper/122:38:091
144722860,1sleep60-21swapper/600:35:006
144722860,1sleep60-21swapper/600:35:006
119072860,0sleep10-21swapper/119:30:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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