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2026-02-11 - 15:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Wed Feb 11, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
815521100,0sleep40-21swapper/409:51:244
315312870,1sleep00-21swapper/010:12:350
173672870,1sleep1221rcuc/112:39:181
289362860,1sleep60-21swapper/610:21:076
136842800,1sleep60-21swapper/610:28:046
232102780,1sleep00-21swapper/012:12:560
116362780,0sleep00-21swapper/011:03:480
116362780,0sleep00-21swapper/011:03:480
10032770,0sleep00-21swapper/009:19:220
298812760,1sleep00-21swapper/010:57:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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