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2026-01-21 - 15:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Wed Jan 21, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1230321200,0sleep012304-21sshd12:16:480
223952870,1sleep31038-21sshd12:36:473
174622850,1sleep00-21swapper/012:08:230
259752790,1sleep60-21swapper/609:13:586
199832760,0sleep60-21swapper/612:18:006
158652740,0sleep40-21swapper/411:58:574
117182740,1sleep50-21swapper/511:49:055
264932710,0sleep70-21swapper/711:23:267
246232700,0sleep20-21swapper/209:13:462
310582690,0sleep50-21swapper/510:24:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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