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2026-02-03 - 22:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Tue Feb 03, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
822321460,0sleep50-21swapper/510:56:085
131912860,0sleep00-21swapper/012:12:240
131912860,0sleep00-21swapper/012:12:240
219182830,1sleep50-21swapper/511:35:515
200232830,0sleep20-21swapper/210:20:142
306092810,0sleep20-21swapper/212:00:402
306092810,0sleep20-21swapper/212:00:392
188072800,1sleep4501ktimersoftd/412:13:164
188072800,1sleep4501ktimersoftd/412:13:164
133362760,0sleep60-21swapper/609:32:106
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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