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2026-02-03 - 09:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Tue Feb 03, 2026 00:45:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1841821560,3sleep6690999cyclictest22:25:166
3181321520,0sleep431760-21sshd22:03:344
793321380,3sleep1688299cyclictest00:31:341
2479821200,4sleep1688299cyclictest23:44:371
1787921160,4sleep233-21ksoftirqd/200:09:392
2389021140,1sleep723887-21sshd22:47:537
2389021140,1sleep723887-21sshd22:47:527
285412870,4sleep2688899cyclictest23:46:152
230842870,1sleep021600-21kworker/0:221:16:570
20572860,0sleep40-21swapper/422:30:274
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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