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2026-01-19 - 07:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Mon Jan 19, 2026 00:45:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
323521530,1sleep13239-21bash21:25:081
875521510,4sleep7946999cyclictest23:40:437
2681421350,3sleep2944199cyclictest22:44:272
1959021330,0sleep319589-21sshd00:00:103
1720521300,1sleep417204-21sshd00:10:134
2120621240,0sleep10-21swapper/122:23:581
2351021230,0sleep40-21swapper/421:10:444
1426221200,0sleep5581rcuc/522:24:595
460621150,3sleep0943199cyclictest22:19:330
460621150,3sleep0943199cyclictest22:19:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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