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2026-01-25 - 05:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Sun Jan 25, 2026 00:45:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1032721400,0sleep00-21swapper/000:11:050
3108021320,0sleep30-21swapper/322:21:443
3244521270,0sleep60-21swapper/623:37:056
683721220,3sleep21675599cyclictest23:03:512
33322910,1sleep70-21swapper/723:21:117
138682890,1sleep213864-21bash00:39:052
317982880,5sleep61678099cyclictest00:25:146
272242880,2sleep40-21swapper/423:12:034
240012880,0sleep70-21swapper/723:38:117
127872860,1sleep20-21swapper/200:06:512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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