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2026-02-28 - 20:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Sat Feb 28, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
314752790,1sleep431457-21sshd10:22:164
36342770,0sleep40-21swapper/407:25:014
127372770,0sleep70-21swapper/711:59:487
32082750,0sleep40-21swapper/409:49:464
128112750,0sleep70-21swapper/710:57:377
63622730,0sleep00-21swapper/010:23:250
289602720,0sleep40-21swapper/411:52:314
167132710,0sleep20-21swapper/211:50:382
252252700,0sleep20-21swapper/209:15:072
218122700,0sleep40-21swapper/410:11:184
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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