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2026-02-09 - 22:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Mon Feb 09, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1149621150,0sleep20-21swapper/210:13:502
204162810,1sleep20-21swapper/211:00:542
91662800,0sleep40-21swapper/410:36:204
322532790,4sleep72176599cyclictest11:30:167
175642770,0sleep70-21swapper/711:46:357
175642770,0sleep70-21swapper/711:46:357
29152750,0sleep20-21swapper/209:22:052
217972750,1sleep021800-21gltestperf08:15:130
20982750,1sleep60-21swapper/612:16:396
199452750,0sleep20-21swapper/212:33:102
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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