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2026-02-15 - 15:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Sun Feb 15, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1371421560,0sleep70-21swapper/711:37:037
287782870,0sleep50-21swapper/511:30:115
144252840,1sleep60-21swapper/609:44:176
223882780,0sleep70-21swapper/711:15:307
320002770,1sleep51-21systemd10:49:575
5642760,0sleep00-21swapper/010:31:490
85102740,0sleep6671rcuc/610:46:296
32352720,0sleep70-21swapper/710:32:127
28742720,0sleep60-21swapper/610:00:286
104322670,0sleep30-21swapper/309:43:433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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