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2026-01-13 - 23:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Tue Jan 13, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
77672810,0sleep10-21swapper/109:52:391
94702800,0sleep70-21swapper/711:05:067
94702800,0sleep70-21swapper/711:05:067
92332780,0sleep60-21swapper/611:50:006
166562780,0sleep40-21swapper/412:36:074
307352760,0sleep40-21swapper/411:35:004
27642760,0sleep00-21swapper/012:20:330
274102760,0sleep40-21swapper/408:05:144
269062730,0sleep20-21swapper/211:43:242
26472730,0sleep00-21swapper/010:36:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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