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2026-02-10 - 10:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Tue Feb 10, 2026 00:45:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2058721430,16sleep280250irq/25-eno1-rx-00:00:102
555521180,1sleep65552-21sshd00:27:476
1832921160,0sleep40-21swapper/423:48:104
1429621160,0sleep30-21swapper/322:30:343
543921100,0sleep20-21swapper/223:10:182
154002920,0sleep00-21swapper/023:25:380
228842870,1sleep322887-21grepconf.sh23:45:213
70772860,2sleep5591ktimersoftd/523:17:505
70532830,0sleep40-21swapper/423:58:044
299782820,0sleep00-21swapper/021:51:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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