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2026-02-04 - 08:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Wed Feb 04, 2026 00:45:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
300321540,1sleep42995-21sshd23:24:544
300321540,1sleep42995-21sshd23:24:534
733221450,0sleep60-21swapper/600:26:196
2215321170,1sleep669-21ksoftirqd/621:26:186
149292910,1sleep40-21swapper/421:27:274
106882890,2sleep10-21swapper/122:28:241
157142880,0sleep70-21swapper/721:37:577
189532870,0sleep40-21swapper/423:25:344
265022860,1sleep226435-21sshd22:50:052
131642860,1sleep10-21swapper/122:53:571
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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