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2026-02-02 - 08:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Mon Feb 02, 2026 00:45:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
981521200,0sleep00-21swapper/022:44:580
595221190,3sleep32213199cyclictest00:21:113
535321140,0sleep40-21swapper/421:10:534
361221120,0sleep00-21swapper/023:02:140
30552880,0sleep20-21swapper/221:56:202
92232830,0sleep00-21swapper/000:03:290
172862830,2sleep20-21swapper/200:18:462
284982820,0sleep70-21swapper/721:24:437
17222810,0sleep70-21swapper/722:26:067
280512800,0sleep00-21swapper/021:23:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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