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2026-01-24 - 16:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Sat Jan 24, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
264421050,0sleep40-21swapper/409:50:434
287142780,0sleep40-21swapper/409:17:414
122172770,1sleep512221-21cpuspeed_turbos12:20:145
233152760,0sleep30-21swapper/311:58:403
126202750,0sleep70-21swapper/709:56:477
278032740,0sleep40-21swapper/409:13:004
298752730,0sleep50-21swapper/507:45:135
116852730,1sleep30-21swapper/311:24:343
234672720,1sleep223475-21pmu-power09:35:182
264352710,0sleep50-21swapper/510:58:485
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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