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2026-02-11 - 01:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Wed Feb 11, 2026 00:45:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3234821580,3sleep3173599cyclictest22:32:113
1200921410,4sleep3173599cyclictest00:00:593
1683021230,1sleep30-21swapper/323:07:213
1683021230,1sleep30-21swapper/323:07:213
99921220,0sleep50-21swapper/523:45:305
666721190,0sleep50-21swapper/522:54:565
2068421110,0sleep40-21swapper/400:23:534
2068421110,0sleep40-21swapper/400:23:534
2721621080,0sleep40-21swapper/422:15:294
145232910,1sleep10-21swapper/122:31:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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