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2026-01-16 - 00:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot0.osadl.org (updated Thu Jan 15, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
770121120,0sleep60-21swapper/612:20:236
27332880,1sleep10-21swapper/112:06:161
231552790,1sleep10-21swapper/111:24:151
295572770,0sleep50-21swapper/512:37:055
206462770,0sleep10-21swapper/111:55:181
88862740,1sleep11012-21runrttasks09:30:111
88862740,1sleep11012-21runrttasks09:30:111
251812740,0sleep00-21swapper/009:36:510
188622740,1sleep6681ktimersoftd/610:47:436
139812740,0sleep60-21swapper/612:12:216
124012720,0sleep40-21swapper/410:19:594
173782710,1sleep00-21swapper/011:41:220
102402710,0sleep10-21swapper/111:13:261
258082700,0sleep20-21swapper/211:02:052
258082700,0sleep20-21swapper/211:02:052
33472690,0sleep60-21swapper/612:06:206
49142600,0sleep50-21swapper/511:53:145
42862590,0sleep30-21swapper/311:21:293
2969625848,6sleep50-21swapper/507:08:595
2774225848,6sleep70-21swapper/707:05:087
195592580,4sleep13001599cyclictest10:20:441
2968125129,7sleep10-21swapper/107:08:471
16592510,0sleep10-21swapper/110:09:301
2940724634,6sleep60-21swapper/607:05:236
2975724434,6sleep30-21swapper/307:09:453
2774424332,7sleep00-21swapper/007:05:090
2963024030,6sleep40-21swapper/407:08:104
2943224028,7sleep20-21swapper/207:05:432
3005399293,24cyclictest0-21swapper/710:05:137
3004699270,12cyclictest0-21swapper/611:15:596
93732260,1sleep61012-21runrttasks10:37:246
3004199260,21cyclictest0-21swapper/507:37:355
3002599250,23cyclictest0-21swapper/312:04:023
3004199240,23cyclictest0-21swapper/510:32:535
3003699242,21cyclictest0-21swapper/407:13:134
3003699240,20cyclictest0-21swapper/411:52:564
3002599240,19cyclictest0-21swapper/307:30:133
3002099243,17cyclictest0-21swapper/210:56:482
3005399233,18cyclictest0-21swapper/712:00:137
3005399232,20cyclictest0-21swapper/710:44:147
3005399230,22cyclictest0-21swapper/709:07:087
3005399230,19cyclictest0-21swapper/710:11:317
3005399230,18cyclictest0-21swapper/709:32:377
3005399230,18cyclictest0-21swapper/709:32:377
3004699233,18cyclictest0-21swapper/607:44:146
3004199233,19cyclictest0-21swapper/507:51:025
3003699233,17cyclictest0-21swapper/410:34:384
3003699231,21cyclictest0-21swapper/410:00:464
3002599233,18cyclictest0-21swapper/310:09:283
3002599230,21cyclictest0-21swapper/307:50:383
3002099234,18cyclictest0-21swapper/208:24:522
3002099233,18cyclictest0-21swapper/211:34:112
3002099233,18cyclictest0-21swapper/210:11:502
3002099233,18cyclictest0-21swapper/207:12:522
3001599233,19cyclictest0-21swapper/111:45:251
3001599233,18cyclictest0-21swapper/110:40:381
3001599233,18cyclictest0-21swapper/108:39:431
3001599233,18cyclictest0-21swapper/107:49:531
3001599233,15cyclictest0-21swapper/110:38:501
3001599230,21cyclictest0-21swapper/107:42:141
3000899233,19cyclictest0-21swapper/009:56:030
3000899232,19cyclictest0-21swapper/009:41:570
3000899230,22cyclictest0-21swapper/009:03:320
259562230,1sleep71012-21runrttasks09:23:367
217492230,1sleep21012-21runrttasks11:28:332
3005399223,18cyclictest0-21swapper/711:47:197
3005399223,18cyclictest0-21swapper/709:18:267
3005399223,18cyclictest0-21swapper/709:11:537
3005399223,18cyclictest0-21swapper/708:39:167
3005399222,18cyclictest0-21swapper/711:11:527
3005399222,18cyclictest0-21swapper/708:49:047
3005399220,20cyclictest0-21swapper/709:02:387
3005399220,20cyclictest0-21swapper/707:51:177
3004699223,18cyclictest0-21swapper/609:56:426
3004699223,18cyclictest0-21swapper/609:28:366
3004699223,18cyclictest0-21swapper/609:28:366
3004699223,18cyclictest0-21swapper/608:33:206
3004699223,18cyclictest0-21swapper/608:24:456
3004699223,18cyclictest0-21swapper/608:16:456
3004699223,18cyclictest0-21swapper/608:14:006
3004699223,18cyclictest0-21swapper/608:14:006
3004699223,18cyclictest0-21swapper/607:35:056
3004699220,21cyclictest0-21swapper/611:53:256
3004699220,21cyclictest0-21swapper/611:29:576
3004699220,21cyclictest0-21swapper/611:24:316
3004699220,20cyclictest0-21swapper/609:50:146
3004699220,20cyclictest0-21swapper/609:10:006
3004699220,19cyclictest0-21swapper/611:05:096
3004199223,18cyclictest0-21swapper/510:29:075
3004199222,19cyclictest0-21swapper/509:55:455
3004199222,18cyclictest0-21swapper/511:39:225
3004199222,15cyclictest0-21swapper/509:53:335
3004199221,19cyclictest0-21swapper/508:36:585
3004199220,21cyclictest0-21swapper/510:23:015
3004199220,20cyclictest0-21swapper/508:53:585
3004199220,20cyclictest0-21swapper/508:05:275
3004199220,20cyclictest0-21swapper/507:11:135
3004199220,19cyclictest0-21swapper/510:45:115
3004199220,19cyclictest0-21swapper/508:25:455
3004199220,17cyclictest0-21swapper/508:31:225
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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