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2026-01-18 - 23:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot0.osadl.org (updated Sun Jan 18, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
276322870,0sleep20-21swapper/211:24:482
293772860,0sleep40-21swapper/410:39:224
293772860,0sleep40-21swapper/410:39:224
111382790,1sleep50-21swapper/510:00:125
162002780,0sleep20-21swapper/212:31:562
275332750,5sleep10-21swapper/112:38:121
33092730,1sleep30-21swapper/310:35:293
33092730,1sleep30-21swapper/310:35:293
303932730,0sleep60-21swapper/611:52:336
35592710,0sleep20-21swapper/211:07:332
215042710,0sleep40-21swapper/410:47:174
215042710,0sleep40-21swapper/410:47:164
209132710,1sleep20-21swapper/210:10:352
128722710,1sleep612864-21sshd11:27:096
217392700,0sleep50-21swapper/511:33:005
177752690,0sleep10-21swapper/110:01:051
235752680,0sleep00-21swapper/010:38:300
235752680,0sleep00-21swapper/010:38:300
1980025949,6sleep60-21swapper/607:09:336
1972525848,6sleep50-21swapper/507:08:345
1980725747,6sleep40-21swapper/407:09:394
1961725746,7sleep00-21swapper/007:07:100
1950725028,6sleep30-21swapper/307:05:453
1982224635,7sleep10-21swapper/107:09:431
1971824130,7sleep70-21swapper/707:08:297
1961924130,7sleep20-21swapper/207:07:122
2007699310,14cyclictest0-21swapper/310:33:043
2007699310,14cyclictest0-21swapper/310:33:043
2007699290,19cyclictest0-21swapper/310:54:043
2007699290,19cyclictest0-21swapper/310:54:043
2008799287,18cyclictest0-21swapper/510:18:465
2007699280,16cyclictest0-21swapper/310:27:483
2007699273,22cyclictest0-21swapper/311:08:483
2007699270,17cyclictest0-21swapper/310:48:563
2007699270,17cyclictest0-21swapper/310:48:563
2007699270,14cyclictest0-21swapper/310:42:403
2007699270,14cyclictest0-21swapper/310:42:403
172502270,0sleep50-21swapper/511:27:485
2009699260,22cyclictest0-21swapper/609:35:106
2008299260,20cyclictest0-21swapper/409:04:154
2010499250,21cyclictest0-21swapper/707:57:317
2010499250,21cyclictest0-21swapper/707:57:317
2009699253,20cyclictest0-21swapper/609:00:146
2007699253,19cyclictest0-21swapper/309:40:033
2007699250,20cyclictest0-21swapper/311:55:443
2007699250,20cyclictest0-21swapper/309:49:083
2007699250,19cyclictest0-21swapper/311:48:493
2010499244,18cyclictest0-21swapper/711:54:367
2010499242,21cyclictest0-21swapper/708:04:447
2010499241,21cyclictest0-21swapper/707:49:197
2010499240,19cyclictest0-21swapper/708:14:507
2009699244,19cyclictest0-21swapper/607:25:306
2009699243,18cyclictest0-21swapper/612:30:156
2009699240,20cyclictest0-21swapper/611:22:176
2009699240,18cyclictest0-21swapper/607:15:126
2008299243,19cyclictest0-21swapper/407:30:194
2008299240,19cyclictest0-21swapper/408:27:144
2007699243,19cyclictest0-21swapper/311:32:023
2007699240,23cyclictest0-21swapper/311:53:183
2007699240,21cyclictest0-21swapper/312:17:343
2007699240,21cyclictest0-21swapper/312:17:343
2007699240,19cyclictest0-21swapper/309:55:263
2007699240,19cyclictest0-21swapper/307:36:583
2007099241,21cyclictest0-21swapper/210:26:212
2006599241,19cyclictest0-21swapper/108:45:161
2010499233,19cyclictest0-21swapper/711:33:547
2010499233,19cyclictest0-21swapper/710:43:287
2010499233,19cyclictest0-21swapper/710:43:287
2010499233,18cyclictest0-21swapper/711:18:027
2010499233,18cyclictest0-21swapper/708:58:427
2010499233,15cyclictest0-21swapper/709:37:167
2010499232,20cyclictest0-21swapper/712:00:217
2010499231,21cyclictest0-21swapper/709:01:397
2010499230,18cyclictest0-21swapper/707:25:177
2008799232,20cyclictest0-21swapper/508:06:015
2008299230,22cyclictest0-21swapper/407:15:364
2007699234,18cyclictest0-21swapper/307:42:463
2007699232,20cyclictest0-21swapper/309:10:433
2007699232,19cyclictest0-21swapper/311:14:283
2007699232,19cyclictest0-21swapper/309:29:173
2007699231,19cyclictest0-21swapper/309:35:373
2007699230,22cyclictest0-21swapper/312:22:433
2007699230,22cyclictest0-21swapper/311:22:383
2007699230,22cyclictest0-21swapper/310:21:423
2007699230,22cyclictest0-21swapper/310:19:083
2007699230,22cyclictest0-21swapper/310:10:583
2007699230,22cyclictest0-21swapper/310:07:363
2007699230,22cyclictest0-21swapper/309:15:053
2007699230,22cyclictest0-21swapper/309:15:053
2007699230,22cyclictest0-21swapper/308:55:133
2007699230,22cyclictest0-21swapper/308:45:013
2007699230,20cyclictest0-21swapper/312:31:493
2007699230,20cyclictest0-21swapper/312:12:223
2007699230,20cyclictest0-21swapper/312:12:223
2007699230,20cyclictest0-21swapper/311:42:483
2007699230,20cyclictest0-21swapper/311:16:193
2007699230,20cyclictest0-21swapper/311:02:583
2007699230,20cyclictest0-21swapper/309:51:243
2007699230,19cyclictest0-21swapper/307:15:113
2007699230,18cyclictest0-21swapper/312:25:453
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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