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2026-04-21 - 22:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Tue Apr 21, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26302800,1sleep50-21swapper/510:59:035
229652780,0sleep70-21swapper/712:30:177
133212750,1sleep70-21swapper/709:14:227
143522740,0sleep10-21swapper/110:37:111
310232720,1sleep00-21swapper/011:12:200
214982720,1sleep2681-21dbus-daemon10:47:382
108582720,1sleep2321ktimersoftd/212:14:492
274242710,0sleep70-21swapper/709:30:007
259502710,0sleep7761rcuc/710:01:507
258712710,3sleep12089899cyclictest10:48:161
293812700,1sleep129380-21sshd09:44:061
239692700,0sleep10-21swapper/109:52:231
130042700,0sleep50-21swapper/509:41:375
312792690,0sleep30-21swapper/309:30:213
203812690,0sleep70-21swapper/711:10:437
273642680,0sleep70-21swapper/711:21:017
119992660,0sleep10-21swapper/110:32:141
102202660,0sleep30-21swapper/311:28:023
258152650,0sleep20-21swapper/209:48:082
249172630,0sleep10-21swapper/110:29:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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