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2026-08-04 - 01:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Mon Aug 03, 2026 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1051921290,0sleep610520-21sshd12:05:506
2384921260,0sleep123850-21bash11:26:421
1153221080,0sleep50-21swapper/510:27:565
3268821070,0sleep40-21swapper/410:42:534
285522870,0sleep50-21swapper/511:02:505
310892810,0sleep50-21swapper/511:35:445
212332790,0sleep30-21swapper/307:20:193
210992780,4sleep21497999cyclictest10:04:372
217902770,1sleep00-21swapper/010:49:470
128082760,0sleep40-21swapper/411:37:354
270932750,0sleep10-21swapper/111:23:051
236242750,0sleep50-21swapper/509:32:105
55052740,1sleep1221rcuc/110:51:401
224992740,1sleep40-21swapper/409:32:004
138482740,0sleep50-21swapper/510:36:215
209472720,0sleep60-21swapper/611:18:146
194072720,0sleep10-21swapper/110:37:051
111102720,0sleep50-21swapper/512:14:145
29382710,0sleep0121rcuc/010:18:370
147612700,1sleep233-21ksoftirqd/212:14:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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