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2026-02-28 - 10:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Sat Feb 28, 2026 00:45:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2200121370,0sleep00-21swapper/021:39:330
763321300,1sleep07586-21sshd00:22:520
683121280,0sleep50-21swapper/521:44:505
608721260,0sleep40-21swapper/422:47:584
608721260,0sleep40-21swapper/422:47:574
1797521150,1sleep10-21swapper/123:50:151
3030421140,0sleep00-21swapper/021:23:210
868721120,2sleep4649099cyclictest23:42:164
9832880,1sleep20-21swapper/222:32:412
171682880,0sleep60-21swapper/623:48:436
87332870,2sleep30-21swapper/322:42:043
87332870,2sleep30-21swapper/322:42:043
54642840,0sleep00-21swapper/021:19:140
241672840,0sleep40-21swapper/422:35:164
241672840,0sleep40-21swapper/422:35:154
174932830,0sleep70-21swapper/723:15:347
60222820,1sleep30-21swapper/322:58:313
225312820,1sleep4501ktimersoftd/423:50:254
76602800,0sleep40-21swapper/400:15:184
265722770,0sleep00-21swapper/021:50:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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