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2026-09-03 - 02:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Thu Sep 03, 2026 00:45:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
631321530,0sleep66261-21sshd22:24:196
208121530,0sleep62080-21id23:23:516
325521510,0sleep30-21swapper/323:44:553
1581021470,3sleep1937899cyclictest23:32:361
393421420,3sleep6941099cyclictest22:53:136
1914321220,0sleep00-21swapper/000:14:510
1175021190,0sleep40-21swapper/422:26:094
1279821180,1sleep2321ktimersoftd/223:14:402
52421160,0sleep70-21swapper/721:16:157
52421160,0sleep70-21swapper/721:16:157
82882860,3sleep7941699cyclictest22:17:557
116472840,1sleep6671rcuc/622:32:376
116472840,1sleep6671rcuc/622:32:366
216412830,0sleep00-21swapper/022:42:490
216412830,0sleep00-21swapper/022:42:480
22072810,1sleep30-21swapper/322:54:463
302312800,0sleep00-21swapper/021:17:440
302312800,0sleep00-21swapper/021:17:440
209582790,0sleep20-21swapper/222:57:182
294582780,0sleep50-21swapper/522:20:335
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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