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2026-05-05 - 22:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Tue May 05, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37872820,1sleep31014-21runrttasks09:36:343
279652790,0sleep40-21swapper/410:21:234
104742790,0sleep20-21swapper/211:35:512
296932740,0sleep30-21swapper/310:57:533
97922730,1sleep50-21swapper/511:08:455
55452730,0sleep70-21swapper/709:32:217
184232730,0sleep1221rcuc/107:20:201
103342720,0sleep70-21swapper/709:10:257
64452690,0sleep50-21swapper/510:54:425
281532690,0sleep20-21swapper/212:37:202
217492680,0sleep1231ktimersoftd/112:36:241
161832680,0sleep20-21swapper/212:31:032
36412670,0sleep00-21swapper/012:02:090
20362670,2sleep61190699cyclictest10:04:116
20362670,2sleep61190699cyclictest10:04:116
195062670,0sleep61014-21runrttasks11:28:086
95062590,4sleep31188599cyclictest12:21:033
1138525949,6sleep50-21swapper/507:06:485
1136825948,7sleep60-21swapper/607:06:316
1146325848,6sleep00-21swapper/007:07:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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