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2026-02-21 - 09:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Sat Feb 21, 2026 00:45:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1212421490,4sleep2319699cyclictest22:01:232
2742121120,3sleep7322699cyclictest22:31:427
641721100,0sleep1318999cyclictest23:10:231
78421090,4sleep5321199cyclictest21:49:415
218421080,0sleep00-21swapper/000:02:410
212821080,0sleep40-21swapper/423:44:174
309462830,1sleep60-21swapper/623:28:316
20562830,0sleep70-21swapper/700:14:027
325242820,1sleep70-21swapper/723:18:397
313642810,2sleep20-21swapper/222:38:592
219392810,1sleep081ktimersoftd/023:45:080
177482810,1sleep7771ktimersoftd/723:22:157
66222800,0sleep16621-21sshd21:47:051
57832800,0sleep60-21swapper/621:38:366
57832800,0sleep60-21swapper/621:38:356
229612800,1sleep522957-21sshd23:43:465
226272800,5sleep2319699cyclictest21:50:342
143282800,1sleep614326-21sshd23:43:236
264012790,0sleep40-21swapper/423:15:314
176362790,1sleep00-21swapper/022:11:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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