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2026-06-04 - 22:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Thu Jun 04, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
779821190,0sleep70-21swapper/710:17:527
2418621180,1sleep560-21ksoftirqd/511:36:045
1288221150,0sleep10-21swapper/109:55:011
141292830,4sleep0166199cyclictest11:44:170
150472800,0sleep20-21swapper/212:08:072
98552780,0sleep60-21swapper/609:40:166
98552780,0sleep60-21swapper/609:40:166
93952770,0sleep70-21swapper/711:48:167
64882770,0sleep40-21swapper/410:50:434
55002770,1sleep30-21swapper/311:04:593
197492760,4sleep7170599cyclictest10:52:457
290272750,1sleep429029-21kworker/u16:010:40:014
22412750,2sleep60-21swapper/610:55:026
264362740,0sleep30-21swapper/312:00:143
225842740,0sleep70-21swapper/712:18:467
38452730,1sleep50-21swapper/509:48:565
38452730,1sleep50-21swapper/509:48:565
166482730,0sleep30-21swapper/310:42:483
274572720,1sleep07-21ksoftirqd/011:31:490
91842710,0sleep40-21swapper/411:57:434
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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