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2026-07-04 - 22:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Sat Jul 04, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2879621380,0sleep7761rcuc/710:50:357
1106621170,3sleep52585099cyclictest09:13:275
179802830,1sleep50-21swapper/511:31:365
31822820,0sleep10-21swapper/109:50:091
137142790,0sleep60-21swapper/609:51:356
185502770,1sleep5581rcuc/510:39:505
300492750,0sleep20-21swapper/211:42:552
300492750,0sleep20-21swapper/211:42:542
92312740,4sleep42584599cyclictest11:54:114
38952740,0sleep40-21swapper/411:58:044
134372740,1sleep20-21swapper/212:37:122
298642730,0sleep20-21swapper/209:16:042
280392730,0sleep0121rcuc/011:42:370
280392730,0sleep0121rcuc/011:42:370
18582730,1sleep40-21swapper/409:40:194
207872720,0sleep20-21swapper/211:46:152
295052700,0sleep70-21swapper/712:01:437
277012700,0sleep30-21swapper/310:45:423
244202700,0sleep40-21swapper/410:50:074
132242700,0sleep10-21swapper/111:40:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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