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2026-01-08 - 07:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Thu Jan 08, 2026 00:45:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
218832830,1sleep20-21swapper/223:29:462
40872810,1sleep00-21swapper/000:39:330
260162810,0sleep1221rcuc/121:19:221
274542800,0sleep00-21swapper/023:15:570
185902770,0sleep60-21swapper/621:46:366
113582770,0sleep70-21swapper/723:46:197
13282760,1sleep31-21systemd00:28:303
108332760,0sleep50-21swapper/500:22:225
130192750,0sleep00-21swapper/023:42:580
109342740,0sleep00-21swapper/023:39:130
275892730,1sleep60-21swapper/622:22:586
90772720,0sleep0121rcuc/022:10:180
80382710,1sleep20-21swapper/222:17:172
225382710,0sleep50-21swapper/522:32:595
100552710,0sleep60-21swapper/623:46:096
307582700,0sleep50-21swapper/521:58:385
230552700,0sleep20-21swapper/200:27:162
184622700,0sleep30-21swapper/323:32:513
99072690,0sleep30-21swapper/321:42:083
41122690,1sleep1231ktimersoftd/122:13:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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