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2025-11-06 - 08:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Thu Nov 06, 2025 00:45:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1319421410,0sleep613195-21sshd21:29:306
136622950,1sleep5581rcuc/521:16:315
95922830,0sleep30-21swapper/323:57:383
53432820,2sleep10-21swapper/122:59:021
278932810,1sleep00-21swapper/000:32:300
139642780,0sleep10-21swapper/120:05:201
247042770,0sleep50-21swapper/521:43:325
199012770,4sleep51797399cyclictest23:26:145
13032760,0sleep30-21swapper/322:35:553
76592750,0sleep70-21swapper/723:57:267
13552750,1sleep4501ktimersoftd/421:15:184
82102740,1sleep325197-1kworker/3:2H21:48:193
302792740,0sleep70-21swapper/723:24:087
289852740,0sleep00-21swapper/000:19:240
18722740,1sleep3411ktimersoftd/322:13:283
18722740,1sleep3411ktimersoftd/322:13:273
319232730,0sleep60-21swapper/621:47:256
89512720,1sleep5581rcuc/522:49:445
87782720,0sleep30-21swapper/322:46:213
55682720,1sleep15570-21id22:10:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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