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2025-05-03 - 01:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Sat May 03, 2025 00:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2980921480,3sleep31257299cyclictest00:00:183
299221130,0sleep20-21swapper/200:27:262
299221130,0sleep20-21swapper/200:27:252
179072900,1sleep4491rcuc/423:12:584
179072900,1sleep4491rcuc/423:12:584
291492850,0sleep70-21swapper/723:07:327
65972820,1sleep50-21swapper/500:17:525
56082800,1sleep4501ktimersoftd/423:34:544
163282800,0sleep00-21swapper/023:42:270
317682780,1sleep60-21swapper/622:18:356
260202780,0sleep70-21swapper/721:21:527
268232770,0sleep70-21swapper/722:50:497
227252770,1sleep60-21swapper/623:00:186
227252770,1sleep60-21swapper/623:00:186
224922770,1sleep60-21swapper/623:16:446
141602770,4sleep01255799cyclictest19:10:230
164652760,0sleep30-21swapper/323:09:373
250432750,0sleep60-21swapper/600:09:516
296142740,1sleep429612-21sshd21:32:164
296142740,1sleep429612-21sshd21:32:154
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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