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2026-04-07 - 19:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Tue Apr 07, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2802321170,0sleep50-21swapper/512:28:385
2883121070,0sleep70-21swapper/711:43:207
3153421020,1sleep10-21swapper/107:05:101
28522790,0sleep20-21swapper/212:15:522
65932780,4sleep7133699cyclictest10:55:057
256892770,0sleep20-21swapper/209:18:422
256892770,0sleep20-21swapper/209:18:422
175142770,1sleep20-21swapper/211:41:402
71392730,2sleep40-21swapper/410:00:514
86372720,0sleep10-21swapper/110:01:051
11362720,0sleep20-21swapper/210:27:112
28502710,1sleep081ktimersoftd/010:36:210
136002690,0sleep10-21swapper/109:35:011
136002690,0sleep10-21swapper/109:35:011
106692680,0sleep10-21swapper/111:36:101
78802670,0sleep50-21swapper/509:16:065
78802670,0sleep50-21swapper/509:16:065
223192670,0sleep70-21swapper/712:00:277
320642660,0sleep00-21swapper/009:46:210
293312650,0sleep40-21swapper/409:23:424
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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