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2025-11-02 - 21:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Sun Nov 02, 2025 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
179992830,0sleep50-21swapper/510:23:315
175142820,0sleep60-21swapper/609:40:206
279132780,0sleep60-21swapper/609:13:366
11452780,1sleep70-21swapper/712:34:537
322102770,1sleep31036-21runrttasks11:13:463
292062770,0sleep50-21swapper/509:28:015
61232750,0sleep00-21swapper/009:48:160
280992740,0sleep30-21swapper/311:27:333
144452740,0sleep40-21swapper/410:32:364
258332730,0sleep70-21swapper/712:38:227
246162730,0sleep50-21swapper/509:41:245
9112720,2sleep30-21swapper/311:18:433
77482710,0sleep50-21swapper/510:31:325
233922710,1sleep2321ktimersoftd/211:21:552
320452690,1sleep70-21swapper/709:28:277
55662680,0sleep20-21swapper/210:50:212
264062680,0sleep30-21swapper/310:39:163
168112680,0sleep30-21swapper/310:56:553
137632670,0sleep40-21swapper/410:27:394
137632670,0sleep40-21swapper/410:27:394
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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