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2025-09-18 - 18:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Thu Sep 18, 2025 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
96062830,1sleep69600-21sshd09:34:196
130642830,2sleep00-21swapper/009:53:380
313202820,1sleep10-21swapper/111:49:191
150932810,1sleep1231ktimersoftd/109:20:431
150932810,1sleep1231ktimersoftd/109:20:431
10062790,1sleep40-21swapper/411:49:394
204032780,1sleep3401rcuc/309:21:353
204032780,1sleep3401rcuc/309:21:353
144762770,0sleep50-21swapper/510:36:055
6092760,0sleep00-21swapper/011:11:430
271302760,0sleep70-21swapper/709:41:267
284282750,0sleep60-21swapper/611:06:216
70362740,0sleep50-21swapper/512:04:305
187272740,1sleep618726-21sshd11:52:056
182252720,0sleep60-21swapper/609:16:336
182252720,0sleep60-21swapper/609:16:326
41112710,0sleep50-21swapper/510:30:045
41112710,0sleep50-21swapper/510:30:045
322602710,0sleep00-21swapper/010:20:050
29242700,0sleep10-21swapper/110:25:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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