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2026-03-24 - 16:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Tue Mar 24, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1286421550,3sleep72634299cyclictest10:20:057
644621490,5sleep32631799cyclictest09:12:373
518421140,0sleep70-21swapper/711:25:227
67502860,2sleep30-21swapper/310:09:433
131782850,0sleep20-21swapper/210:39:082
77462820,0sleep40-21swapper/410:33:334
83242810,0sleep20-21swapper/211:25:492
279612810,0sleep50-21swapper/508:20:005
269172810,0sleep30-21swapper/311:23:573
320742790,0sleep40-21swapper/409:25:454
299682790,1sleep50-21swapper/511:29:135
103552790,2sleep00-21swapper/011:11:520
210092780,1sleep451-21ksoftirqd/410:21:074
228892760,1sleep122888-21sshd11:09:051
60542750,1sleep60-21swapper/609:50:246
52012750,1sleep65182-21sshd12:08:256
236952750,1sleep523692-21sshd10:21:325
264352740,0sleep10-21swapper/112:01:551
264352740,0sleep10-21swapper/112:01:551
255242740,1sleep11012-21runrttasks10:26:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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