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2026-02-22 - 13:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #0

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System r0s0s.osadl.org (updated Sun Feb 22, 2026 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14022182307291,9sleep40-21swapper/407:07:544
14021082304274,23sleep00-21swapper/007:06:220
14002682297278,12sleep70-21swapper/707:05:087
14022722294276,12sleep20-21swapper/207:08:402
14023052293257,28sleep50-21swapper/507:09:085
14022642289270,12sleep30-21swapper/307:08:343
14022242289269,13sleep10-21swapper/107:07:591
14020942286266,13sleep60-21swapper/607:06:126
1402841993735,1cyclictest1552379-21kworker/u16:3+events_unbound12:13:364
140284199365,1cyclictest171rcu_preempt12:30:284
1402841993634,2cyclictest1438097-21kworker/u16:2+events_unbound08:18:244
140284199362,31cyclictest171rcu_preempt07:38:084
140284199355,0cyclictest0-21swapper/410:41:444
140284199351,1cyclictest1402547-21kworker/4:0-events07:14:484
1402839993529,5cyclictest449069-21snmpd08:30:172
1402839993529,5cyclictest449069-21snmpd08:30:172
140284199345,29cyclictest1540790-21ipmitool11:40:204
140284199344,30cyclictest0-21swapper/408:46:244
140284199344,0cyclictest0-21swapper/411:35:344
1402841993432,2cyclictest0-21swapper/407:33:024
140284199343,1cyclictest171rcu_preempt11:27:464
140284199341,1cyclictest171rcu_preempt09:09:344
140284199341,0cyclictest171rcu_preempt10:05:164
140284199340,1cyclictest171rcu_preempt09:32:424
140283999340,33cyclictest0-21swapper/211:28:252
1402837993431,2cyclictest449069-21snmpd10:51:240
1402843993330,2cyclictest449069-21snmpd10:45:276
1402843993330,2cyclictest449069-21snmpd08:49:596
140284399330,1cyclictest0-21swapper/610:51:366
140284199334,0cyclictest0-21swapper/409:25:284
140284199334,0cyclictest0-21swapper/407:53:044
140284199333,30cyclictest0-21swapper/411:00:144
140284199333,30cyclictest0-21swapper/410:35:284
140284199333,30cyclictest0-21swapper/409:55:364
1402841993330,2cyclictest1458994-21kworker/4:2-mm_percpu_wq09:39:284
140284199332,0cyclictest0-21swapper/410:24:504
140284199332,0cyclictest0-21swapper/410:24:504
140284199331,31cyclictest171rcu_preempt12:29:484
140284199330,2cyclictest171rcu_preempt07:22:224
140284199330,1cyclictest0-21swapper/410:52:424
1402840993330,2cyclictest449069-21snmpd09:20:123
140283999330,30cyclictest0-21swapper/209:45:432
1402838993330,2cyclictest449069-21snmpd10:17:321
1402838993330,2cyclictest449069-21snmpd09:59:461
1402838993330,2cyclictest1538242-21cat11:35:141
140283899330,30cyclictest0-21swapper/111:01:121
140283799330,1cyclictest0-21swapper/009:19:120
1402844993230,2cyclictest449069-21snmpd10:36:417
1402844993230,1cyclictest1474020-21kworker/7:0+events10:00:247
1402844993229,3cyclictest449069-21snmpd08:09:527
1402844993229,2cyclictest449069-21snmpd09:46:287
140284499320,31cyclictest0-21swapper/712:10:157
1402843993230,1cyclictest449069-21snmpd11:37:256
1402843993230,1cyclictest449069-21snmpd08:15:356
1402843993229,2cyclictest449069-21snmpd10:00:226
140284399320,31cyclictest0-21swapper/612:39:336
140284399320,31cyclictest0-21swapper/610:33:296
140284399320,31cyclictest0-21swapper/607:55:136
1402842993230,1cyclictest449069-21snmpd07:20:275
140284299320,30cyclictest0-21swapper/511:13:405
140284299320,30cyclictest0-21swapper/507:25:095
140284199324,28cyclictest1421798-21kworker/u16:2+events_unbound08:05:504
140284199323,29cyclictest1469375-21kworker/u16:3+events_unbound09:21:244
1402841993232,0cyclictest0-21swapper/409:40:504
1402841993231,1cyclictest1408228-21kworker/u16:4+writeback07:55:044
1402841993231,1cyclictest0-21swapper/410:30:424
1402841993231,1cyclictest0-21swapper/408:54:084
1402841993230,2cyclictest1570116-21kworker/u16:1+events_unbound12:38:504
140284199322,30cyclictest1522123-21kworker/u16:3+events_unbound11:19:004
140284199322,30cyclictest1501644-21kworker/4:1-events12:04:404
140284199322,30cyclictest0-21swapper/410:28:144
140284199322,30cyclictest0-21swapper/410:28:144
140284199321,30cyclictest0-21swapper/407:26:004
140284199321,1cyclictest171rcu_preempt12:21:224
140284199320,32cyclictest1501644-21kworker/4:1+events12:08:504
140284199320,32cyclictest1402547-21kworker/4:0-events08:32:344
140284199320,32cyclictest1402547-21kworker/4:0-events08:32:344
140284199320,1cyclictest0-21swapper/408:23:204
140284199320,0cyclictest0-21swapper/408:42:284
1402840993230,2cyclictest449069-21snmpd10:57:063
1402840993230,2cyclictest449069-21snmpd08:00:373
1402840993229,2cyclictest449069-21snmpd07:32:483
1402839993230,2cyclictest449069-21snmpd11:42:582
1402839993230,2cyclictest449069-21snmpd09:00:152
1402839993229,2cyclictest449069-21snmpd08:02:412
1402839993227,4cyclictest449069-21snmpd07:11:122
1402838993229,2cyclictest449069-21snmpd08:05:131
140283899320,31cyclictest0-21swapper/109:44:431
140283899320,31cyclictest0-21swapper/107:32:331
1402837993230,2cyclictest449069-21snmpd11:24:490
1402837993229,2cyclictest1414200-21cat07:30:150
1402844993130,1cyclictest902-21mta-sts-daemon09:53:287
1402844993129,1cyclictest449069-21snmpd12:36:067
1402844993129,1cyclictest449069-21snmpd12:27:187
1402844993129,1cyclictest449069-21snmpd10:56:577
1402844993129,1cyclictest449069-21snmpd07:45:137
1402844993128,2cyclictest449069-21snmpd11:56:387
140284499310,31cyclictest0-21swapper/711:49:177
140284499310,31cyclictest0-21swapper/710:33:567
140284499310,31cyclictest0-21swapper/710:12:057
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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