You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-05 - 20:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #0, slot #0

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System r0s0s.osadl.org (updated Thu Feb 05, 2026 12:46:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6766622309281,21sleep30-21swapper/307:09:343
6766602300281,12sleep10-21swapper/107:09:321
6764742297258,31sleep70-21swapper/707:06:577
6765332296262,26sleep00-21swapper/007:07:460
6766052292273,12sleep20-21swapper/207:08:452
6765722291257,26sleep50-21swapper/507:08:165
6766252287268,12sleep40-21swapper/407:09:034
6763982287267,13sleep60-21swapper/607:05:516
67716799363,1cyclictest171rcu_preempt08:15:114
677169993535,0cyclictest0-21swapper/610:09:586
677169993535,0cyclictest0-21swapper/609:26:056
677169993535,0cyclictest0-21swapper/609:26:056
677168993534,1cyclictest834088-21kworker/u16:1+events_unbound12:35:235
67716799355,30cyclictest854-21lldpd11:40:454
67716799355,0cyclictest0-21swapper/410:12:534
67716799354,30cyclictest0-21swapper/409:15:034
67716799353,1cyclictest171rcu_preempt07:15:234
67716999344,30cyclictest0-21swapper/607:43:316
67716999344,0cyclictest0-21swapper/609:46:116
677169993434,0cyclictest0-21swapper/608:35:446
67716799345,29cyclictest0-21swapper/409:03:274
67716799344,30cyclictest0-21swapper/411:19:234
67716799344,30cyclictest0-21swapper/410:45:514
67716799344,30cyclictest0-21swapper/409:27:014
67716799344,30cyclictest0-21swapper/409:27:014
67716799344,30cyclictest0-21swapper/409:05:464
67716799344,30cyclictest0-21swapper/408:44:274
67716799344,0cyclictest0-21swapper/407:54:014
67716799344,0cyclictest0-21swapper/407:28:314
67716799343,0cyclictest171rcu_preempt10:08:294
67716799342,1cyclictest171rcu_preempt08:59:194
67716799340,32cyclictest53-21ksoftirqd/409:14:274
67716799340,2cyclictest53-21ksoftirqd/407:36:044
67716799340,2cyclictest53-21ksoftirqd/407:36:034
67716799340,1cyclictest53-21ksoftirqd/412:34:074
677166993431,2cyclictest449069-21snmpd12:10:263
677170993330,2cyclictest738828-21cat09:10:137
67717099330,30cyclictest0-21swapper/708:55:477
677169993332,1cyclictest0-21swapper/609:10:356
67716999333,0cyclictest0-21swapper/610:52:116
677168993332,1cyclictest16-21pr/tty008:45:395
67716799334,29cyclictest0-21swapper/408:21:304
67716799334,0cyclictest0-21swapper/410:40:474
67716799334,0cyclictest0-21swapper/410:26:574
67716799334,0cyclictest0-21swapper/410:00:534
67716799334,0cyclictest0-21swapper/409:56:014
67716799333,30cyclictest0-21swapper/411:09:314
67716799333,30cyclictest0-21swapper/411:01:074
67716799333,30cyclictest0-21swapper/409:52:534
67716799333,30cyclictest0-21swapper/409:36:394
677167993332,1cyclictest702960-21kworker/4:0-events09:45:554
67716799333,0cyclictest0-21swapper/412:29:154
67716799333,0cyclictest0-21swapper/411:32:034
67716799333,0cyclictest0-21swapper/409:40:094
67716799333,0cyclictest0-21swapper/409:20:334
67716799332,31cyclictest712560-21kworker/u16:2-edac-poller08:26:334
67716799332,31cyclictest521ktimers/407:12:554
67716799332,0cyclictest171rcu_preempt08:05:414
67716799330,2cyclictest171rcu_preempt10:50:154
677166993330,2cyclictest449069-21snmpd10:44:413
677166993330,2cyclictest449069-21snmpd07:15:503
67716699330,30cyclictest0-21swapper/308:55:383
677165993332,1cyclictest781276-21kworker/u16:0+flush-8:010:40:262
67716499330,1cyclictest0-21swapper/109:13:061
677170993230,2cyclictest690159-21kworker/7:1+events09:20:007
677170993230,1cyclictest449069-21snmpd11:57:207
677170993229,2cyclictest449069-21snmpd08:51:117
67717099320,31cyclictest0-21swapper/712:21:277
67717099320,31cyclictest0-21swapper/710:24:297
67717099320,30cyclictest0-21swapper/710:01:197
67717099320,30cyclictest0-21swapper/708:05:557
67716999322,1cyclictest0-21swapper/608:21:156
67716999322,0cyclictest0-21swapper/612:32:316
67716999321,31cyclictest681ktimers/611:05:366
677169993211,21cyclictest0-21swapper/611:10:176
67716999320,1cyclictest0-21swapper/607:22:596
677168993232,0cyclictest0-21swapper/512:03:295
677168993232,0cyclictest0-21swapper/510:54:375
677168993232,0cyclictest0-21swapper/508:44:175
677168993231,1cyclictest16-21pr/tty008:56:525
677168993230,2cyclictest781882-21cat10:35:155
67716899320,31cyclictest0-21swapper/507:35:125
67716899320,31cyclictest0-21swapper/507:35:125
677167993232,0cyclictest0-21swapper/412:02:154
677167993231,1cyclictest702960-21kworker/4:0-mm_percpu_wq08:10:434
677167993231,1cyclictest702960-21kworker/4:0-events11:59:294
67716799323,0cyclictest0-21swapper/411:11:114
67716799323,0cyclictest0-21swapper/408:52:314
67716799323,0cyclictest0-21swapper/408:37:574
67716799323,0cyclictest0-21swapper/408:03:354
67716799323,0cyclictest0-21swapper/407:21:174
67716799322,30cyclictest521ktimers/407:46:274
67716799322,0cyclictest0-21swapper/411:36:234
67716799322,0cyclictest0-21swapper/411:21:114
67716799322,0cyclictest0-21swapper/411:21:104
67716799322,0cyclictest0-21swapper/407:55:354
67716799321,1cyclictest521ktimers/410:30:174
677166993230,2cyclictest796899-21cat11:05:163
677166993230,2cyclictest449069-21snmpd07:56:063
677166993229,2cyclictest449069-21snmpd10:46:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional