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2026-02-02 - 10:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #0

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System r0s0s.osadl.org (updated Mon Feb 02, 2026 00:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21388822320302,11sleep60-21swapper/619:06:056
21391512300292,5sleep10-21swapper/119:09:551
21389112290273,11sleep20-21swapper/219:06:262
21390982289270,12sleep40-21swapper/419:09:104
21391302288268,12sleep70-21swapper/719:09:377
21390282287267,13sleep00-21swapper/019:08:090
21390242286266,13sleep50-21swapper/519:08:065
21389572286266,13sleep30-21swapper/319:07:073
2139633993330,3cyclictest449069-21snmpd21:52:077
2139633993330,2cyclictest449069-21snmpd20:56:337
2139633993329,3cyclictest449069-21snmpd22:21:087
2139632993330,3cyclictest449069-21snmpd19:15:336
2139632993330,2cyclictest449069-21snmpd21:57:136
2139632993330,2cyclictest1849915-21ntpd22:26:416
2139632993330,2cyclictest1849915-21ntpd21:06:416
2139630993330,2cyclictest449069-21snmpd23:15:084
213963099330,30cyclictest0-21swapper/419:38:004
2139629993330,2cyclictest449069-21snmpd21:48:433
2139627993330,2cyclictest2206314-21cat21:20:151
213962799330,30cyclictest0-21swapper/100:11:411
2139626993330,2cyclictest2201276-21cat21:10:150
213962699330,30cyclictest0-21swapper/019:47:460
2139633993230,2cyclictest449069-21snmpd19:20:357
2139633993230,2cyclictest449069-21snmpd19:19:307
2139633993230,2cyclictest449069-21snmpd19:11:547
2139633993230,2cyclictest449069-21snmpd00:37:057
2139633993230,2cyclictest2118893-21kworker/7:0+events21:45:287
2139633993230,1cyclictest449069-21snmpd23:14:547
2139633993230,1cyclictest449069-21snmpd22:13:207
2139633993230,1cyclictest449069-21snmpd21:24:577
2139633993229,2cyclictest449069-21snmpd22:29:587
2139633993229,2cyclictest449069-21snmpd00:07:177
2139633993228,3cyclictest449069-21snmpd19:40:047
2139632993230,2cyclictest449069-21snmpd19:13:306
2139632993230,2cyclictest1849915-21ntpd00:06:416
2139632993230,1cyclictest449069-21snmpd22:00:226
2139632993229,2cyclictest449069-21snmpd23:45:086
2139632993229,2cyclictest1849915-21ntpd22:11:416
2139632993229,2cyclictest1849915-21ntpd20:16:416
213963299320,31cyclictest0-21swapper/621:10:096
213963299320,31cyclictest0-21swapper/620:14:386
2139631993230,2cyclictest449069-21snmpd20:58:545
2139631993230,2cyclictest449069-21snmpd20:24:405
2139630993230,2cyclictest449069-21snmpd00:31:304
2139630993230,2cyclictest2214827-21cat21:40:104
2139630993229,2cyclictest449069-21snmpd00:29:424
2139630993229,2cyclictest449069-21snmpd00:29:414
213963099320,30cyclictest0-21swapper/423:36:344
213963099320,30cyclictest0-21swapper/422:56:244
213963099320,30cyclictest0-21swapper/422:14:474
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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