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2025-11-25 - 19:35

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #0

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System r0s0s.osadl.org (updated Tue Nov 25, 2025 12:46:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32276872303271,26sleep00-21swapper/007:09:290
32275312298260,13sleep40-21swapper/407:07:324
32274872297283,9sleep10-21swapper/107:06:561
32276272292257,27sleep70-21swapper/707:08:397
32276432291271,13sleep50-21swapper/507:08:535
32275592287266,13sleep30-21swapper/307:07:553
32276442286267,12sleep60-21swapper/607:08:546
32277222285266,12sleep20-21swapper/207:09:562
322820799381,4cyclictest61-21ksoftirqd/508:25:255
3228207993634,2cyclictest3163983-21kworker/5:0-mm_percpu_wq07:49:395
322820799363,1cyclictest171rcu_preempt08:39:015
322820799363,1cyclictest171rcu_preempt07:14:235
322820799355,30cyclictest3289551-21ntpq09:15:235
322820799355,0cyclictest0-21swapper/507:50:115
322820799352,2cyclictest171rcu_preempt10:05:215
322820799352,2cyclictest171rcu_preempt08:07:435
322820799352,1cyclictest171rcu_preempt11:32:315
322820799352,1cyclictest171rcu_preempt11:32:315
322820799352,1cyclictest171rcu_preempt11:16:575
322820799352,1cyclictest171rcu_preempt11:12:315
322820799352,1cyclictest171rcu_preempt09:27:435
322820799351,30cyclictest171rcu_preempt07:44:415
322820799351,1cyclictest171rcu_preempt09:31:235
322820799351,1cyclictest0-21swapper/511:40:035
322820799351,0cyclictest171rcu_preempt12:25:295
3228205993532,2cyclictest3333719-21kworker/u16:2+flush-8:010:50:123
322820799345,29cyclictest0-21swapper/507:36:375
322820799344,30cyclictest0-21swapper/512:02:465
322820799344,30cyclictest0-21swapper/507:26:295
3228207993433,1cyclictest0-21swapper/511:02:135
3228207993433,1cyclictest0-21swapper/507:23:175
3228207993432,2cyclictest0-21swapper/512:12:495
3228207993432,2cyclictest0-21swapper/510:39:455
322820799343,0cyclictest171rcu_preempt08:00:255
322820799342,30cyclictest171rcu_preempt10:01:235
322820799342,30cyclictest171rcu_preempt08:24:195
322820799342,0cyclictest171rcu_preempt09:46:235
322820799340,1cyclictest61-21ksoftirqd/509:23:255
322820799340,1cyclictest61-21ksoftirqd/509:00:375
322820799334,29cyclictest0-21swapper/511:39:565
322820799334,0cyclictest0-21swapper/510:31:415
3228207993333,0cyclictest0-21swapper/511:27:275
322820799333,30cyclictest0-21swapper/510:58:255
3228207993331,2cyclictest3255099-21kworker/5:2-mm_percpu_wq08:52:595
3228207993331,2cyclictest0-21swapper/512:17:415
3228207993331,2cyclictest0-21swapper/508:31:515
322820799333,0cyclictest0-21swapper/509:37:075
322820799333,0cyclictest0-21swapper/509:37:075
322820799332,0cyclictest171rcu_preempt12:34:395
322820799332,0cyclictest171rcu_preempt07:58:535
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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