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2025-10-19 - 01:19

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #1

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot1s.osadl.org (updated Sun Oct 19, 2025 00:45:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2447199128125,2cyclictest0-21swapper/419:39:344
2449499127124,2cyclictest0-21swapper/720:28:537
24480991270,126cyclictest0-21swapper/522:33:465
2447199127126,1cyclictest0-21swapper/423:12:254
2446799127125,1cyclictest37-21ksoftirqd/300:35:463
2449499126124,1cyclictest23816-21chk_conn_tcp23:03:087
2449499126124,1cyclictest0-21swapper/721:16:037
2448899126124,1cyclictest22105-21chk_conn_tcp00:31:086
2448099126124,1cyclictest6132-21chk_conn_tcp20:07:195
2444999126126,0cyclictest21-21ksoftirqd/122:01:031
24488991251,1cyclictest0-21swapper/600:00:006
24471991250,124cyclictest0-21swapper/400:29:144
2444999125125,0cyclictest21-21ksoftirqd/123:30:411
2449499124122,1cyclictest0-21swapper/723:46:107
2448899124123,1cyclictest0-21swapper/619:43:306
24488991240,123cyclictest0-21swapper/622:35:466
24488991240,123cyclictest0-21swapper/622:35:466
2448099124123,1cyclictest0-21swapper/521:28:175
2447199124122,2cyclictest0-21swapper/423:32:254
24471991240,123cyclictest0-21swapper/420:11:544
2444599124123,1cyclictest0-21swapper/000:17:200
2444599124123,0cyclictest3-21ksoftirqd/022:51:240
2448899123122,1cyclictest0-21swapper/623:46:586
2447199123121,1cyclictest0-21swapper/419:43:104
2446799123118,4cyclictest37-21ksoftirqd/320:13:503
2446799123116,6cyclictest37-21ksoftirqd/319:47:483
2446099123123,0cyclictest29-21ksoftirqd/222:26:002
2444999123123,0cyclictest21-21ksoftirqd/120:27:351
2449499122121,1cyclictest0-21swapper/723:54:047
2448899122122,0cyclictest190750irq/36-eth1-rx-20:55:196
2448099122121,1cyclictest0-21swapper/521:12:175
2448099122120,1cyclictest0-21swapper/523:13:515
2447199122120,1cyclictest0-21swapper/421:24:004
2446799122121,0cyclictest37-21ksoftirqd/323:45:483
2444599122121,0cyclictest3-21ksoftirqd/023:34:010
2449499121118,2cyclictest0-21swapper/722:11:077
2448899121119,1cyclictest24161-21chk_conn_tcp00:06:336
2446099121119,1cyclictest12650irq/19-ata_piix00:00:002
2444599121121,0cyclictest3-21ksoftirqd/023:50:550
2448899120119,1cyclictest0-21swapper/619:37:436
2448899120118,1cyclictest479-21chk_conn_tcp19:47:326
2448099120119,1cyclictest0-21swapper/520:13:135
2447199120118,1cyclictest0-21swapper/419:48:374
2446799120120,0cyclictest37-21ksoftirqd/321:52:233
2446799120116,4cyclictest37-21ksoftirqd/322:32:013
2446099120118,1cyclictest29-21ksoftirqd/222:35:462
2446099120118,1cyclictest29-21ksoftirqd/222:35:462
2444999120120,0cyclictest21-21ksoftirqd/122:33:461
2444599120119,0cyclictest350ksoftirqd/021:10:430
2446799119119,0cyclictest37-21ksoftirqd/322:00:063
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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